Gigabyte GA-78LMT-S2 Schematic REV. 1.0
5
GA-78LMT-S2
4
Revision : 1.0
26
3
TITLEPAGE
NB/SB POWER, VCC12HT, VDDA25
2
1
D D
PAGE
TITLE
9M-00
27
DDRIII POWER, VCC18
01 COVER SHEET
02
03
04
05
06
07
C C
08
09
10
11
12
13
14
15
B B
16
BOM & PCB MODIFY HISTORY
BLOCK DIAGRAM
CPU HYPER TRANSPORT
CPU DDRIII MEMORY
CPU CONTROL
CPU POWER & GND
DDRIII CHANNEL A0, B0
RS780 HT-LINK I/F
RS780 SYSTEM I/F,STRAP,DVI
RS780 POWER & GND
IDT 9LPRS485C
ATI SB710 PCIE/PCI/CPU/LPC/CLK
ATI SB710 ACPI/USB/GPIO/AUDIO
ATI SB710 SATA/IDE/HWM/SPI
ATI SB710 POWER & GND
17
18
19
20
21
22
A A
23
24
25
PCI EXPRESS x16 ,x1
PCI SLOT
LAN AR8151/8152
ALC887-VD2
RGB, COM, F_USB ,USB
IT8728DX,Dual-BIOS FAN/HWMO
ATX, FRONT PANEL
VCORE(RT8868+RT9612)
POWER SEQUENCE,EUP
5
Title
Title
Title
COVER SHEET
COVER SHEET
COVER SHEET
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
1
1 27Wednesday, April 11, 2012
1 27Wednesday, April 11, 2012
1 27Wednesday, April 11, 2012
5
4
3
2
1
Model Name:GA-78LMT-S2
Component value change history
D D
Change ItemDate
2012.03.12
2012.04.11
C C
E_BOM Release. PCB: 0.1
P_BOM Release. PCB: 1.0 change P-BOM to 10A
Modify from 78LMT-S2P 5.02
Reason
Version: 1.0
P-Code: U99098-0
Circuit or PCB layout change for next version
Change ItemDate Version
2012.03.11
2012.04.11 1.0 Gerber out 1. change PCB Ver 1.0 2. Add "RB"
0.1 Gerber out
change From 78LMT-S2P 5.02
(RS760=RS780L)
B B
A A
Title
Title
Title
BOM & PCB HISTORY
BOM & PCB HISTORY
BOM & PCB HISTORY
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
2 27Wednesday, April 11, 2012
2 27Wednesday, April 11, 2012
2 27Wednesday, April 11, 2012
1
5
www.schematic-x.blogspot.com
4
3
2
1
RS780L CUSTOMER DESKTOP DESIGN
DDRIII 1066 / 1333
AMD AM3
D D
Clock
Generator
RT880T-792
12
HyperTransport
LINK
OUT
4,5,6,7
16x16
IN
AM3 SOCKET
128bit
DDRIII 1066 / 1333
UNBUFFERED
DDRIII DIMM1
UNBUFFERED
DDRIII DIMM2
DDRIII FIRST LOGICAL DIMM
8
8
ATI NB
RS760G
HyperTransport LINK0 CPU I/F
1 16X PCIE VIDEO I/F
4 1X PCIE I/F
1 4X PCIE I/F WITH SB
DX10 IGP
USB 2.0
ATI SB
SB710
USB2.0
SATA II
AZALIA
ATA 66/100/133
ACPI
LPC I/F
INT RTC
HW MONITOR
9,10,11
4X
PCIE
13,14,15,16
HD AUDIO I/F
SATA II I/F
ALC887
HD AUDIO CODEC
SATA#0
20,21
SATA#1
15
DESKTOP AM3
POWER
DDR3 MEMORY
POWER
15
SATA#2
15
27
SATA#3
15
RS760 CORE & PCIE
POWER
SB710 CORE & PCIE
POWER
SATA#4 SATA#5
15
15
29
2930
PCIE SLOT
1X
USB-3
19
USB-10
RGB
16X
17
USB-2
19
USB-11
VGA
CON
PCIE SLOT
16X
C C
RTL811F
USB-7
21
B B
USB-8
21 23 23
23
17
1X PCIE INTERFACE
19
USB-6
21
USB-9
21
PCI BUS
22
22
3
SPI BIOS
15
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
3 27Wednesday, April 11, 2012
3 27Wednesday, April 11, 2012
3 27Wednesday, April 11, 2012
1
PCI SLOT
#1
18
LPC BUS
ITE LPC SIO IT8728 EX
A A
HW
MONITOR
22
5
KBD
4
L0_CADIN_L[0..15]
L0_CADIN_H[0..15]
L0_CADIN_L[0..15] <9>
L0_CADIN_H[0..15] <9>
L0_CADOUT_L[0..15]
L0_CADOUT_H[0..15]
L0_CLKIN_H1<9>
L0_CLKIN_L1<9>
L0_CLKIN_H0<9>
L0_CLKIN_L0<9>
L0_CTLIN_L1<9>
L0_CTLIN_H0<9>
L0_CTLIN_L0<9>
L0_CADOUT_L[0..15] <9>
L0_CADOUT_H[0..15] <9>
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
N6
P6
N3
N2
V4
V5
U1
V1
U6
V6
T4
T5
R6
T6
P4
P5
M4
M5
L6
M6
K4
K5
J6
K6
U3
U2
R1
T1
R3
R2
N1
P1
L1
M1
L3
L2
J1
K1
J3
J2
M2CPUA
M2CPUA
HYPERTRANSPORT
HYPERTRANSPORT
L0_CLKIN_H(1)
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKIN_L(0)
L0_CTLIN_H(1)
L0_CTLIN_L(1)
L0_CTLIN_H(0)
L0_CTLIN_L(0)
L0_CADIN_H(15)
L0_CADIN_L(15)
L0_CADIN_H(14)
L0_CADIN_L(14)
L0_CADIN_H(13)
L0_CADIN_L(13)
L0_CADIN_H(12)
L0_CADIN_L(12)
L0_CADIN_H(11)
L0_CADIN_L(11)
L0_CADIN_H(10)
L0_CADIN_L(10)
L0_CADIN_H(9)
L0_CADIN_L(9)
L0_CADIN_H(8)
L0_CADIN_L(8)
L0_CADIN_H(7)
L0_CADIN_L(7)
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADIN_H(5)
L0_CADIN_L(5)
L0_CADIN_H(4)
L0_CADIN_L(4)
L0_CADIN_H(3)
L0_CADIN_L(3)
L0_CADIN_H(2)
L0_CADIN_L(2)
L0_CADIN_H(1)
L0_CADIN_L(1)
L0_CADIN_H(0)
L0_CADIN_L(0)
CPU-SK/941AM3/S/15u/[10SC1-A01942-01R_10SC1-A01942-02R]
CPU-SK/941AM3/S/15u/[10SC1-A01942-01R_10SC1-A01942-02R]
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1 <9>
L0_CLKOUT_L1 <9>
L0_CLKOUT_H0 <9>
L0_CLKOUT_L0 <9>
L0_CTLOUT_H1 <9>L0_CTLIN_H1<9>
L0_CTLOUT_L1 <9>
L0_CTLOUT_H0 <9>
L0_CTLOUT_L0 <9>
CPU_VDD_RUN = VCORE
CPU_VDDA_RUN = VDDA25
VLDT_RUN = VCC12_HT
CPU_VDDIO_SUS = DDR18V
CPU_VTT_SUS = DDRVTT
VLDT_A = VCC12_HT
VLDT_B = HT12B
M2CPU
M2CPU
AMD RM/BLUE
AMD RM/BLUE
Title
Title
Title
CPU HYPER TRANSPORT
CPU HYPER TRANSPORT
CPU HYPER TRANSPORT
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
4 27Wednesday, April 11, 2012
4 27Wednesday, April 11, 2012
4 27Wednesday, April 11, 2012
M2CPUB
M2CPUB
MEMORY INTERFACE A
AG21
AG20
G19
H19
U27
U26
-CSA1
-CSA0
MODT_A0
DCLKA0
-DCLKA0
AC25
AA24
AC28
AE20
AE19
W27
AD27
AA25
G20
G21
V27
-CSA1<8>
-CSA0<8>
MODT_A0<8>
A00P
DCLKA0<8>
A00N B00P
-DCLKA0<8>
AC27
-SCASA
-SWEA
-SRASA
SBAA2
SBAA1
SBAA0
CKEA1
CKEA0
MAAA15
MAAA14
MAAA13
MAAA12
MAAA11
MAAA10
MAAA9
MAAA8
MAAA7
MAAA6
MAAA5
MAAA4
MAAA3
MAAA2
MAAA1
MAAA0
DQSA7
-DQSA7
DQSA6
-DQSA6
DQSA5
-DQSA5
DQSA4
-DQSA4
DQSA3
-DQSA3
DQSA2
-DQSA2
DQSA1
-DQSA1
DQSA0
-DQSA0
DMA7
DMA6
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
AB25
AB27
AA26
AA27
AC26
W24
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
AF15
AF19
AJ25
AH29
N25
Y27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
U25
D29
C29
C25
D25
E19
G15
B29
E24
E18
H15
L27
T25
T27
F19
F15
MAAA[0..15]<8>
-DQSA[0..8]
DQSA[0..8]
MA_CK[0..7]
DMA[0:8]
-SCASA<8>
-SWEA<8>
-SRASA<8>
SBAA2<8>
SBAA1<8>
SBAA0<8>
CKEA1<8>
CKEA0<8>
-DQSA[0..8] <8>
DQSA[0..8] <8>
MA_CK[0..7] <8>
DMA[0..8] <8>
MEMORY INTERFACE A
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
CPU-SK/941AM3/S/15u/[10SC1-A01942-01R_10SC1-A01942-02R]
CPU-SK/941AM3/S/15u/[10SC1-A01942-01R_10SC1-A01942-02R]
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MDA63
MDA62
MDA61
MDA60
MDA59
MDA58
MDA57
MDA56
MDA55
MDA54
MDA53
MDA52
MDA51
MDA50
MDA49
MDA48
MDA47
MDA46
MDA45
MDA44
MDA43
MDA42
MDA41
MDA40
MDA39
MDA38
MDA37
MDA36
MDA35
MDA34
MDA33
MDA32
MDA31
MDA30
MDA29
MDA28
MDA27
MDA26
MDA25
MDA24
MDA23
MDA22
MDA21
MDA20
MDA19
MDA18
MDA17
MDA16
MDA15
MDA14
MDA13
MDA12
MDA11
MDA10
MDA9
MDA8
MDA7
MDA6
MDA5
MDA4
MDA3
MDA2
MDA1
MDA0
DQSA8
-DQSA8
DMA8
MA_CK7
MA_CK6
MA_CK5
MA_CK4
MA_CK3
MA_CK2
MA_CK1
MA_CK0
MDA[0..63] <8>
M2CPUC
M2CPUC
MEMORY INTERFACE B
AJ19
AK19
A18
A19
U31
U30
-CSB1
-CSB0
MODT_B0
DCLKB0
-DCLKB0
AE30
AC31
AD29
AL19
AL18
C19
D19
W29
W28
AE29
AB31
B00N
-CSB1<8>
-CSB0<8>
MODT_B0<8>
DCLKB0<8>
-DCLKB0<8>
AD31
-SCASB
-SWEB
-SRASB
SBAB2
SBAB1
SBAB0
CKEB1
CKEB0
MAAB15
MAAB14
MAAB13
MAAB12
MAAB11
MAAB10
MAAB9
MAAB8
MAAB7
MAAB6
MAAB5
MAAB4
MAAB3
MAAB2
MAAB1
MAAB0
DQSB7
-DQSB7
DQSB6
-DQSB6
DQSB5
-DQSB5
DQSB4
-DQSB4
DQSB3
-DQSB3
DQSB2
-DQSB2
DQSB1
-DQSB1
DQSB0
-DQSB0
DMB7
DMB6
DMB5
DMB4
DMB3
DMB2
DMB1
DMB0
AC29
AC30
AB29
N31
AA31
AA28
M31
M29
N28
N29
AE31
N30
AA29
R29
R28
R31
R30
U29
U28
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
D31
C31
C24
C23
D17
C17
C14
C13
AJ14
AH17
AJ23
AK29
C30
P29
P31
T31
T29
A23
B17
B13
-SCASB<8>
-SWEB<8>
-SRASB<8>
SBAB2<8>
SBAB1<8>
SBAB0<8>
CKEB1<8>
CKEB0<8>
MAAB[0..15]<8>
MEMORY INTERFACE B
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
-DQSB[0..8]
DQSB[0..8]
MB_CK[0..7]
DMB[0..8]
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
CPU-SK/941AM3/S/15u/[10SC1-A01942-01R_10SC1-A01942-02R]
CPU-SK/941AM3/S/15u/[10SC1-A01942-01R_10SC1-A01942-02R]
-DQSB[0..8] <8>
DQSB[0..8] <8>
MB_CK[0..7] <8>
DMB[0..8] <8>
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MDB63
MDB62
MDB61
MDB60
MDB59
MDB58
MDB57
MDB56
MDB55
MDB54
MDB53
MDB52
MDB51
MDB50
MDB49
MDB48
MDB47
MDB46
MDB45
MDB44
MDB43
MDB42
MDB41
MDB40
MDB39
MDB38
MDB37
MDB36
MDB35
MDB34
MDB33
MDB32
MDB31
MDB30
MDB29
MDB28
MDB27
MDB26
MDB25
MDB24
MDB23
MDB22
MDB21
MDB20
MDB19
MDB18
MDB17
MDB16
MDB15
MDB14
MDB13
MDB12
MDB11
MDB10
MDB9
MDB8
MDB7
MDB6
MDB5
MDB4
MDB3
MDB2
MDB1
MDB0
DQSB8
-DQSB8
DMB8
MB_CK7
MB_CK6
MB_CK5
MB_CK4
MB_CK3
MB_CK2
MB_CK1
MB_CK0
MDB[0..63] <8>
Title
Title
Title
CPU DDRII MEMORY
CPU DDRII MEMORY
CPU DDRII MEMORY
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
5 27Wednesday, April 11, 2012
5 27Wednesday, April 11, 2012
5 27Wednesday, April 11, 2012
SB600
CPU_PWR / DDR18V
-CPURST
-LDT_STOP
CPU_PG_SB<13>
PWROK >
SVC/SVD(CPU_PWROK)
10 uS
0.01U/4/X7R/25V/K/X
0.01U/4/X7R/25V/K/X
DDR15V
R26 300/4R26 300/4
R36 300/4R36 300/4
C74 150P/4/NPO/50V/J/XC74 150P/4/NPO/50V/J/X
3VDUAL VCC3
DDR15V
Q309
Q309
R2756
R2756
300/4
300/4
R1 1K/4/1R1 1K/4/1
MMBT2222A/SOT23/600mA/40
MMBT2222A/SOT23/600mA/40
C1791
C1791
G S
G S
2
2N7002/SOT23/25pF/5
2N7002/SOT23/25pF/5
0.01U/4/X7R/25V/K
0.01U/4/X7R/25V/K
R2506
R2506
8.2K/4/1
8.2K/4/1
3
D
D
1
VCORE
BC1
BC1
R2507
R2507
8.2K/4/1
8.2K/4/1
3
Q310
Q310
D
D
G S
G S
2
1
2N7002/SOT23/25pF/5
2N7002/SOT23/25pF/5
DDR15V
3
Q355
Q355
D
D
G S
G S
2
VDDA25
C3
C3
4.7u/8/Y5V/10V/Z
4.7u/8/Y5V/10V/Z
CPUCLK0_H<12>
CPUCLK0_L<12>
R2754
R2754
300/4
300/4
CPU_PWRGD
CPUCLK0_H
CPUCLK0_L
SI_CLK<22>
PWM_PWRGD <24> CPU_TDI<14>
C1752
C1752
0.1u/4/Y5V/16V/Z/X
0.1u/4/Y5V/16V/Z/X
C1790
C1790
0.1u/4/Y5V/16V/Z/X
0.1u/4/Y5V/16V/Z/X
SI_DAT<22>
DDR15V
DDR15V
1
3.9n/4/X7R/50V/K
3.9n/4/X7R/50V/K
C1
C1
C2
C2
3.9n/4/X7R/50V/K
3.9n/4/X7R/50V/K
DDR15V
DDR15V
DDR15V
R75 1K/4/1R75 1K/4/1
R35 1K/4/1R35 1K/4/1
CPU_M_VREF
DDR15V
DDR15V
-CPURST
100P/4/NPO/50V/J
100P/4/NPO/50V/J
C13
C13
3.3n/4/X7R/50V/K
3.3n/4/X7R/50V/K
R5
169/4/1R5169/4/1
R49 1K/4/1R49 1K/4/1
R17 1K/4/1R17 1K/4/1
R19 1K/4/1R19 1K/4/1
COREFB+<24>
COREFB-<24>
R42 510/4/1R42 510/4/1
R43 510/4/1R43 510/4/1
C1798
C1798
-LDT_STOP<10,13>
-CPURST<10,13>
GNDA<22>
TMPIN2<22>
C4
C4
0.22u/6/X7R/16V/K
0.22u/6/X7R/16V/K
CLKIN_H
CLKIN_L
CPU_PWRGD
-LDT_STOP
-CPURST
CPU_PRESENT_L
CPU_TDI
CPU_TRSTL
CPU_TCK
CPU_TCK<14>
CPU_TMS
CPU_TMS<14>
CPU_DBREQL
39.2/4/1R11 39.2/4/1R11
39.2/4/1R12 39.2/4/1R12
CPU_TEST25_H
CPU_TEST25_L
CPU_TEST18
300/4R13 300/4R13
CPU_TEST19
300/4R14 300/4R14
1K/4/1R2727 1K/4/1R2727
SI_CLK
SI_DAT
M_ZN
M_ZP
CPU_TEST12
M2CPUD
M2CPUD
MISC
MISC
VDDA1
VDDA2
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
THERMTRIP_L
SIC
PROCHOT_L
SID
TDI
TRST_L
TCK
TMS
DBREQ_L
VDDIO_FB_H
VDD_FB_H
VDDIO_FB_L
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2
CPU-SK/941AM3/S/15u/[10SC1-A01942-01R_10SC1-A01942-02R]
CPU-SK/941AM3/S/15u/[10SC1-A01942-01R_10SC1-A01942-02R]
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
TDO
DBRDY
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
D2
D1
C1
E3
E2
E1
AK7
AL7
AK10
B6
AK11
AL11
F1
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
AL10
AJ10
AH10
AH11
AJ11
AK6
AH9
AG9
AG8
AH7
C10
D10
A8
B8
C9
D8
C7
AL3
AL6
AL9
A5
G2
G1
E12
F12
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
E5
AJ5
AJ6
DDR15V
R2555
R2555
1K/4/1
1K/4/1
THERMTRIP_L
-PROCHOT_CPU
R2556
R2556
1K/4/X
1K/4/X
44.2/4/1R53 44.2/4/1R53
44.2/4/1R54 44.2/4/1R54
R55 80.6/4/1/XR55 80.6/4/1/X
CPU_TEST24 CPU_TEST24
CPU_TEST23 CPU_TEST23
CPU_TEST22 CPU_TEST22
CPU_TEST21 CPU_TEST21
CPU_TEST20 CPU_TEST20
CPU_TEST27 CPU_TEST27
CPU_TEST26 CPU_TEST26
Q62
Q62
4
L1117LG/N/SOT223/1A
L1117LG/N/SOT223/1A
1.25*(1+100/100)=2.5V
0.1U/4/Y5V/16V/Z/X
0.1U/4/Y5V/16V/Z/X
Asus-used
R87
R2557
R2557
1K/4/1
1K/4/1
R2558
R2558
1K/4/X
1K/4/X
VCC_SB
R57
R57
300/4
300/4
R60
R60
300/4
300/4
DDR15V
R174 1K/4/1R174 1K/4/1
R87
1K/4/X
1K/4/X
R176 1K/4/1R176 1K/4/1
VID3 <24>
VID2 <24>
VID1 <24>
VID0 <24>
Q10
Q10
SOT23
SOT23
132
MMBT2222A/SOT23/600mA/40
MMBT2222A/SOT23/600mA/40
-PROCHOT_CPU <13,26>
Route as 80-Ohm differential impedance
Keep trace to resistor less than 1" from CPU pin
R2731 1K/4/1R2731 1K/4/1
R44 1K/4/1R44 1K/4/1
R2730 1K/4/1R2730 1K/4/1
R47 1K/4/1R47 1K/4/1
R2729 1K/4/1R2729 1K/4/1
R2728 1K/4/1R2728 1K/4/1
R37 1K/4/1R37 1K/4/1
DDR15V
VCC
BC132
BC132
0.1U/4/Y5V/16V/Z
0.1U/4/Y5V/16V/Z
BC2
BC2
3
2
1
250mA
R394
R394
100/4/1
100/4/1
R395
R395
100/4/1
100/4/1
3VDUAL
R59
R59
8.2K/4/1
8.2K/4/1
THERMTRIP_CPU_L
Q9
Q9
MMBT2222A/SOT23/600mA/40
MMBT2222A/SOT23/600mA/40
SOT23
SOT23
132
BC18
BC18
22U/8/X5R/6.3V/M
22U/8/X5R/6.3V/M
Erratum 133, Revision Guide for
AMD NPT 0Fh Processors
VDDA25VDDA25
THERMTRIP_CPU_L <14>
CPUVREF
40 MILS WIDTH
SBC12
SBC12
SBC31
SBC31
1N/4/X7R/50V/K
1N/4/X7R/50V/K
0.1u/4/X7R/16V/K
0.1u/4/X7R/16V/K
CPU_M_VREF
12
SC35
SC35
1U/6/X7R/16V/K
1U/6/X7R/16V/K
DDR15V
SR19
SR19
16.9/4/1
16.9/4/1
SR20
SR20
16.9/4/1
16.9/4/1
A01P
A01N
B01P
B01N
M2CPUE
M2CPUE
INTERNAL MISC
INTERNAL MISC
L25
RSVD1
L26
RSVD2
L31
RSVD3
L30
RSVD4
W26
DCLKA2
AM3 only
DCLKA1<8>
-DCLKA1<8>
MODT_A1<8>
DCLKA1
-DCLKA1
MODT_A1
AM3 only
DCLKB1<8>
-DCLKB1<8>
DCLKB1
-DCLKB1
MODT_B1
W25
AE27
U24
V24
AE28
Y31
Y30
AG31
V31
W31
AF31
DCLKA2MODT_A3
DCLKA1
DCLKA1MODT_A1
DCLKB2
DCLKB2MODT_B3
DCLKB1
DCLKB1MODT_B1
MA_RESETMB_RESET-
RSVD19
RSVD20
RSVD21
RSVD22
M_VDDIO_PWRGD
COREFB_NB+
COREFB_NB-
CORE_TYP_DET
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
MB_EVENT_L
MA_EVENT_L
AM3 only
MA_RESET_L
E20
MB_RESET_L
B19
CPU_ALERT-
AL4
AK4
AK3
F2
CPU_IDLEEXIT-
F3
G4
G3
CORE_TYPE_DET
G5
AD25
AE24
AE25
AJ18
AJ20
C18
C20
AM3 =>DRAM Thermal Event Status
G24
R104 1K/4/1R104 1K/4/1
G25
H25
MB_EVENT_L
V29
MA_EVENT_L
W30
R105 1K/4/1R105 1K/4/1
R16 1K/4/1R16 1K/4/1
R21 1K/4/1R21 1K/4/1
R10 1K/4/1R10 1K/4/1
R2448 300/4R2448 300/4
AM2: high, AM2R2: low
DDR15V
MB_EVENT_L <8>
MA_EVENT_L <8>MODT_B1<8>
DDR15V
EVENT pins are for future AM3r2
MA_RESET_L <8>
MB_RESET_L <8>
DDR15V
DDR15V
COREFB_NB+ <24>
COREFB_NB- <24>
DDR15V
Layout: Route as 60 ohms
with 5/10 W/S from CPU pins.
Title
Title
Title
CPU CONTROL
CPU CONTROL
CPU CONTROL
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
6 27Wednesday, April 11, 2012
6 27Wednesday, April 11, 2012
6 27Wednesday, April 11, 2012
VCORE_NB
VCORE
VCORE_NB
VCORE
VCORE_NB
VCORE
VCORE_NB
VCORE
VCORE_NB
VCORE
VCORE_NB
VCORE
VCORE_NB
VCORE
AA10
AA12
AA14
AA16
AA18
AB11
AC10
AE10
AA8
AB7
AB9
AC4
AC5
AC8
AD2
AD3
AD7
AD9
AF7
AF9
AG4
AG5
AG7
AH2
AH3
E10
G10
G12
H11
H23
K11
K13
K15
K17
K19
K21
K23
Y17
Y19
VLDT_RUN_B is connected to the VLDT_RUN power
VCORE_NB
supply through the package or on the die. It is only connected
M2CPUF
M2CPUF
VDD1
VDD1
A4
VDD1
A6
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
B3
VDD28
B5
VDD29
B7
VDD30
C2
VDD31
C4
VDD32
C6
VDD33
C8
VDD34
D3
VDD35
D5
VDD36
D7
VDD37
D9
VDD38
E4
VDD39
E6
VDD40
E8
VDD41
VDD42
F5
VDD43
F7
VDD44
F9
VDD45
F11
VDD46
G6
VDD47
G8
VDD48
VDD49
VDD50
H7
VDD51
VDD52
VDD53
J8
VDD54
J12
VDD55
J14
VDD56
J16
VDD57
J18
VDD58
J20
VDD59
J22
VDD60
J24
VDD61
K7
VDD62
K9
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
L4
VDD71
L5
VDD72
L8
VDD73
L10
VDD74
L12
VDD75
VDD150
VDD151
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
VCORE VCORE
M2CPUG
M2CPUG
VDD2
M11
M13
M15
M17
M19
N10
N12
N14
N16
N18
P11
P13
P15
P17
P19
R10
R12
R14
R16
R18
R20
U10
U12
U14
U16
U18
U20
V11
V13
V15
V17
V19
V21
W10
W12
W14
W16
W18
W20
Y11
Y13
Y15
Y21
L14
L16
L18
T11
T13
T15
T17
T19
T21
W4
W5
W8
VDD2
VDD1
VDD2
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
N8
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
P7
VDD19
P9
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
U8
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
V9
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
VDD72
VDD73
VDD74
VDD75
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
M21
M23
N20
N22
R22
U22
W22
H20
AE7
M2CPUH
M2CPUH
VDD3
VDD3
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
L20
VDD19
L22
VDD20
VDD21
VDD22
VDD23
VDD24
P21
VDD25
P23
VDD26
VDD27
T23
VDD28
VDD29
V23
VDD30
VDD31
Y23
VDD32
B2
NB/RSVD
NP/VSS1
NP/VSS2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
on the board to decoupling near the CPU package.
VCC_SB
DDR15V
VCC_SB
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
VCORE
SC16
SC16
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
VCORE
SC24
SC24
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
M2CPUI
M2CPUI
VDDIO
VDDIO
AJ4
VLDT_A1
AJ3
VLDT_A2
AJ2
VLDT_A3
AJ1
VLDT_A4
D12
VDDR_4
C12
VDDR_3
B12
VDDR_2
A12
VDDR_1
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO29
M24
VDDIO9
M26
VDDIO10
M28
VDDIO11
M30
VDDIO12
P24
VDDIO13
P26
VDDIO14
P28
VDDIO15
P30
VDDIO16
T24
VDDIO17
T26
VDDIO18
T28
VDDIO19
T30
VDDIO20
V25
VDDIO21
V26
VDDIO22
V28
VDDIO23
V30
VDDIO24
Y24
VDDIO25
Y26
VDDIO26
Y28
VDDIO27
Y29
VDDIO28
BUTTOM SIDE
SC17
SC17
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
SC25
SC25
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VDDR_5
VDDR_6
VDDR_7
VDDR_8
VDDR_9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
SC18
SC18
SC26
SC26
H6
H5
H2
H1
AG12
AH12
AJ12
AK12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
VCC_SB
SC19
SC19
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
SC27
SC27
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
HT12B
BC795
BC795
4.7u/8/Y5V/10V/Z
4.7u/8/Y5V/10V/Z
VCORE
SC20
SC20
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
SC28
SC28
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
DDR15V
DDR15V
22u/8/X5R/6.3V/M/X
22u/8/X5R/6.3V/M/X
SC11
SC11
0.22u/6/X7R/16V/K
0.22u/6/X7R/16V/K
SC21
SC21
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
SC29
SC29
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
C1343
C1343
C1344
C1344
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
1U/6/Y5V/10V/Z
1U/6/Y5V/10V/Z
SC2
SC2
0.22u/6/X7R/16V/K
0.22u/6/X7R/16V/K
SC10
SC10
SC9
SC9
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
BUTTOM SIDE
SC12
SC12
0.22u/6/X5R/10V/K/X
0.22u/6/X5R/10V/K/X
SC22
SC22
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
SC30
SC30
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
C1342
C1342
0.1U/4/Y5V/16V/Z
0.1U/4/Y5V/16V/Z
BUTTOM SIDE
SC4
SC4
0.22u/6/X7R/16V/K/X
0.22u/6/X7R/16V/K/X
SC7
SC7
4.7u/8/Y5V/10V/Z
4.7u/8/Y5V/10V/Z
SC13
SC13
0.22u/6/X5R/10V/K/X
0.22u/6/X5R/10V/K/X
SC23
SC23
22u/8/X5R/6.3V/M/X
22u/8/X5R/6.3V/M/X
C1345
C1345
0.01U/4/X7R/25V/K
0.01U/4/X7R/25V/K
SC5
SC5
0.01U/4/X7R/25V/K
0.01U/4/X7R/25V/K
SC8
SC8
4.7u/8/Y5V/10V/Z/X
4.7u/8/Y5V/10V/Z/X
SC14
SC14
0.01U/4/X7R/16V/K/X
0.01U/4/X7R/16V/K/X
C1346
C1346
180P/4/NPO/50V/J
180P/4/NPO/50V/J
SC6
SC6
180P/4/NPO/50V/J
180P/4/NPO/50V/J
SC31
SC31
180P/4/NPO/50V/J/X
180P/4/NPO/50V/J/X
SC15
SC15
180P/4/NPO/50V/J
180P/4/NPO/50V/J
VCC_SB
C1328
C1328
4.7u/8/Y5V/10V/Z
4.7u/8/Y5V/10V/Z
C1329
C1329
4.7u/8/Y5V/10V/Z
4.7u/8/Y5V/10V/Z
C1333
C1331
C1331 4.7u/8/Y5V/10V/Z
C1330
C1330
0.22u/6/X7R/16V/K
0.22u/6/X7R/16V/K
0.22u/6/X7R/16V/K
0.22u/6/X7R/16V/K
C1332
C1332
180P/4/NPO/50V/J
180P/4/NPO/50V/J
C1333
180P/4/NPO/50V/J
180P/4/NPO/50V/J
DDR15V
C1324
C1324
4.7u/8/Y5V/10V/Z
C1326
C1326
22U/8/X5R/6.3V/M
22U/8/X5R/6.3V/M
C1327
C1327
22U/8/X5R/6.3V/M
22U/8/X5R/6.3V/M
VCC_SB
C1316
C1316
4.7u/8/Y5V/10V/Z
4.7u/8/Y5V/10V/Z
VCC_SB
C1334
C1334
4.7u/8/Y5V/10V/Z
4.7u/8/Y5V/10V/Z
C1317
C1317
4.7u/8/Y5V/10V/Z
4.7u/8/Y5V/10V/Z
C1335
C1335
22u/8/X5R/6.3V/M
22u/8/X5R/6.3V/M
C1318
C1318
0.22u/6/X7R/16V/K
0.22u/6/X7R/16V/K
C1336
C1336
0.22u/6/X7R/16V/K
0.22u/6/X7R/16V/K
C1320
C1320
1N/4/X7R/50V/K
1N/4/X7R/50V/K
C1338
C1338
1N/4/X7R/50V/K
1N/4/X7R/50V/K
C1321
C1321
1N/4/X7R/50V/K
1N/4/X7R/50V/K
C1339
C1339
1N/4/X7R/50V/K
1N/4/X7R/50V/K
C1322
C1322
180P/4/NPO/50V/J
180P/4/NPO/50V/J
C1340
C1340
100P/4/NPO/50V/J
100P/4/NPO/50V/J
C1323
C1323
180P/4/NPO/50V/J
180P/4/NPO/50V/J
C1341
C1341
100P/4/NPO/50V/J
100P/4/NPO/50V/J
VCC_SB
1021 EMI
BC24
BC24
180P/4/NPO/50V/J
180P/4/NPO/50V/J
Title
Title
Title
CPU POWER & GND
CPU POWER & GND
CPU POWER & GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
BC25
BC25
180P/4/NPO/50V/J
180P/4/NPO/50V/J
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
7 27Wednesday, April 11, 2012
7 27Wednesday, April 11, 2012
7 27Wednesday, April 11, 2012
8
DDRVTT
-DQSA[0..8]
D D
DQSA[0..8]
DMA[0..8]
MA_CK[0..7]
C C
VCC3
B B
A A
-DQSA[0..8] <5>
DQSA[0..8] <5>
DMA[0..8] <5>
MA_CK[0..7] <5>
C275 0.1u/4/Y5V/16V/ZC275 0.1u/4/Y5V/16V/Z
C283 0.1u/4/Y5V/16V/ZC283 0.1u/4/Y5V/16V/Z
C282 0.1u/4/Y5V/16V/ZC282 0.1u/4/Y5V/16V/Z
SMBCLK<12,14,24>
SMBDATA<12,14,24>
SBAA2<5>
SBAA1<5>
SBAA0<5>
CKEA1<5>
CKEA0<5>
-CSA1<5>
-CSA0<5>
-DCLKA1<6>
DCLKA1<6>
-DCLKA0<5>
DCLKA0<5>
MAAA[0..15]<5>
MA_RESET_L<6>
-SCASA<5>
-SRASA<5>
-SWEA<5>
8
DDR15V
VREFCA_A
VREFDQ_A
SMBCLK
SMBDATA
SBAA2
SBAA1
SBAA0
CKEA1
CKEA0
-CSA0
-DCLKA1
DCLKA1
-DCLKA0
DCLKA0
MAAA0
MAAA1
MAAA2
MAAA3
MAAA4
MAAA5
MAAA6
MAAA7
MAAA8
MAAA9
MAAA10
MAAA11
MAAA12
MAAA13
MAAA14
MAAA15
MA_RESET_L
-SCASA
-SRASA
-SWEA
7
DDR3_1
DDR3_1
120
VTT
240
VTT
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
80
VSS
83
VSS
86
VSS
89
VSS
92
VSS
95
VSS
98
VSS
101
VSS
104
VSS
107
VSS
110
VSS
113
VSS
116
VSS
119
VSS
121
VSS
124
VSS
127
VSS
130
VSS
133
VSS
136
VSS
139
VSS
142
VSS
145
VSS
148
VSS
151
VSS
154
VSS
157
VSS
160
VSS
163
VSS
166
VSS
199
VSS
202
VSS
205
VSS
208
VSS
211
VSS
214
VSS
217
VSS
220
VSS
223
VSS
226
VSS
229
VSS
232
VSS
235
VSS
239
VSS
51
VDD
54
VDD
57
VDD
60
VDD
62
VDD
65
VDD
66
VDD
69
VDD
72
VDD
75
VDD
78
VDD
170
VDD
173
VDD
176
VDD
179
VDD
182
VDD
183
VDD
186
VDD
189
VDD
191
VDD
194
VDD
197
VDD
236
VDDSPD
67
VREFCA
1
VREFDQ
118
SCL
238
SDA
237
SA1
117
SA0
52
BA2
190
BA1
71
BA0
169
CKE1
50
CKE0
76
S1*
193
S0*
64
CK1/NU*
63
CK1/NU
185
CK0*
184
CK0
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
168
RESET*
74
CAS*
192
RAS*
73
WE*
7
6
FREE
FREE
FREE
FREE
RSVD
ODT1
ODT0
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQS0
DQS0*
DQS1
DQS1*
DQS2
DQS2*
DQS3
DQS3*
DQS4
DQS4*
DQS5
DQS5*
DQS6
DQS6*
DQS7
DQS7*
DQS8
DQS8*
DM0/DQS9
NC/DQS9*
DM1/DQS10
NC/DQS10*
DM2/DQS11
NC/DQS11*
DM3/DQS12
NC/DQS12*
DM4/DQS13
NC/DQS13*
DM5/DQS14
NC/DQS14*
DM6/DQS15
NC/DQS15*
DM7/DQS16
NC/DQS16*
DM8/DQS17
NC/DQS17*
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DDR3/240/BU/VA/D
DDR3/240/BU/VA/D
6
5
BC4
BC4
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
BC8
BC8
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
BC6
BC6
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
VREFDQ_A
VREFCA_A
Trace min 10/10
SMBCLK<12,14,24>
SMBDATA<12,14,24>
-DCLKB1<6>
DCLKB1<6>
-DCLKB0<5>
DCLKB0<5>
MAAB[0..15]<5>
MB_RESET_L<6>
-SCASB<5>
-SRASB<5>
SBAB2<5>
SBAB1<5>
SBAB0<5>
CKEB1<5>
CKEB0<5>
-CSB1<5>
-CSB0<5>
-SWEB<5>
DDRVTT
DDR15V
VCC3
48
49
MA_EVENT_L
187
198
79
77
195
68
53
167
39
40
45
46
158
159
164
165
7
6
16
15
25
24
34
33
85
84
94
93
103
102
112
111
43
42
125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162
3
4
9
10
122
123
128
129
12
13
18
19
131
132
137
138
21
22
27
28
140
141
146
147
30
31
36
37
149
150
155
156
81
82
87
88
200
201
206
207
90
91
96
97
209
210
215
216
99
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234
MODT_A1
MODT_A0
MA_CK0
MA_CK1
MA_CK2
MA_CK3
MA_CK4
MA_CK5
MA_CK6
MA_CK7
DQSA0
-DQSA0
DQSA1
-DQSA1
DQSA2
-DQSA2
DQSA3
-DQSA3
DQSA4
-DQSA4
DQSA5
-DQSA5
DQSA6
-DQSA6
DQSA7
-DQSA7
DQSA8
-DQSA8
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
DMA8
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MA_EVENT_L <6>
MODT_A1 <6>
MODT_A0 <5>
DDR15V Decouple
DDR15V
DDR15V
R106
R106
15/4/1
15/4/1
VREFDQ_A
Trace min 10/10
R107
R107
15/4/1
15/4/1
DDR15V
R52
R52
15/4/1
15/4/1
VREFCA_A
R56
R56
15/4/1
15/4/1
MDA[0..63] <5>
VCC3
C284 0.1u/4/Y5V/16V/ZC284 0.1u/4/Y5V/16V/Z
C285 0.1u/4/Y5V/16V/ZC285 0.1u/4/Y5V/16V/Z
5
VREFCA_A
VREFDQ_A
SMBCLK
SMBDATA
SBAB2
SBAB1
SBAB0
CKEB1
CKEB0
-CSB1
-CSB0
-DCLKB1
DCLKB1
-DCLKB0
DCLKB0
MAAB0
MAAB1
MAAB2
MAAB3
MAAB4
MAAB5
MAAB6
MAAB7
MAAB8
MAAB9
MAAB10
MAAB11
MAAB12
MAAB13
MAAB14
MAAB15
MB_RESET_L
-SCASB
-SRASB
-SWEB
4
DDR3_2
DDR3_2
120
VTT
240
VTT
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
80
VSS
83
VSS
86
VSS
89
VSS
92
VSS
95
VSS
98
VSS
101
VSS
104
VSS
107
VSS
110
VSS
113
VSS
116
VSS
119
VSS
121
VSS
124
VSS
127
VSS
130
VSS
133
VSS
136
VSS
139
VSS
142
VSS
145
VSS
148
VSS
151
VSS
154
VSS
157
VSS
160
VSS
163
VSS
166
VSS
199
VSS
202
VSS
205
VSS
208
VSS
211
VSS
214
VSS
217
VSS
220
VSS
223
VSS
226
VSS
229
VSS
232
VSS
235
VSS
239
VSS
51
VDD
54
VDD
57
VDD
60
VDD
62
VDD
65
VDD
66
VDD
69
VDD
72
VDD
75
VDD
78
VDD
170
VDD
173
VDD
176
VDD
179
VDD
182
VDD
183
VDD
186
VDD
189
VDD
191
VDD
194
VDD
197
VDD
236
VDDSPD
67
VREFCA
1
VREFDQ
118
SCL
238
SDA
237
SA1
117
SA0
52
BA2
190
BA1
71
BA0
169
CKE1
50
CKE0
76
S1*
193
S0*
64
CK1/NU*
63
CK1/NU
185
CK0*
184
CK0
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10/AP
55
A11
174
A12
196
A13
172
A14
171
A15
168
RESET*
74
CAS*
192
RAS*
73
WE*
4
3
DDR3/240/BU/VA/D
DDR3/240/BU/VA/D
3
FREE
FREE
FREE
FREE
RSVD
ODT1
ODT0
NC/PAR_IN
NC/ERR_OUT
NC/TEST4
DQS0
DQS0*
DQS1
DQS1*
DQS2
DQS2*
DQS3
DQS3*
DQS4
DQS4*
DQS5
DQS5*
DQS6
DQS6*
DQS7
DQS7*
DQS8
DQS8*
DM0/DQS9
NC/DQS9*
DM1/DQS10
NC/DQS10*
DM2/DQS11
NC/DQS11*
DM3/DQS12
NC/DQS12*
DM4/DQS13
NC/DQS13*
DM5/DQS14
NC/DQS14*
DM6/DQS15
NC/DQS15*
DM7/DQS16
NC/DQS16*
DM8/DQS17
NC/DQS17*
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2
48
49
MB_EVENT_L
187
198
79
MODT_B1
77
MODT_B0
195
68
53
167
MB_CK0
39
CB0
MB_CK1
40
CB1
MB_CK2
45
CB2
MB_CK3
46
CB3
MB_CK4
158
CB4
MB_CK5
159
CB5
MB_CK6
164
CB6
MB_CK7
165
CB7
DQSB0
7
-DQSB0
6
DQSB1
16
-DQSB1
15
DQSB2
25
-DQSB2
24
DQSB3
34
-DQSB3
33
DQSB4
85
-DQSB4
84
DQSB5
94
-DQSB5
93
DQSB6
103
-DQSB6
102
DQSB7
112
-DQSB7
111
DQSB8
43
-DQSB8
42
125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162
MDB0
3
DQ0
MDB1
4
DQ1
MDB2
9
DQ2
MDB3
10
DQ3
MDB4
122
DQ4
MDB5
123
DQ5
MDB6
128
DQ6
MDB7
129
DQ7
MDB8
12
DQ8
MDB9
13
DQ9
MDB10
18
MDB11
19
MDB12
131
MDB13
132
MDB14
137
MDB15
138
MDB16
21
MDB17
22
MDB18
27
MDB19
28
MDB20
140
MDB21
141
MDB22
146
MDB23
147
MDB24
30
MDB25
31
MDB26
36
MDB27
37
MDB28
149
MDB29
150
MDB30
155
MDB31
156
MDB32
81
MDB33
82
MDB34
87
MDB35
88
MDB36
200
MDB37
201
MDB38
206
MDB39
207
MDB40
90
MDB41
91
MDB42
96
MDB43
97
MDB44
209
MDB45
210
MDB46
215
MDB47
216
MDB48
99
MDB49
100
MDB50
105
MDB51
106
MDB52
218
MDB53
219
MDB54
224
MDB55
225
MDB56
108
MDB57
109
MDB58
114
MDB59
115
MDB60
227
MDB61
228
MDB62
233
MDB63
234
MB_EVENT_L < 6>
MODT_B1 <6>
MODT_B0 <5>
-DQSB[0..8]
DQSB[0..8]
DMB[0..8]
MB_CK[0..7]
DDR15V Decouple
DDR15V
DMB0
DMB1
DMB2
DMB3
DMB4
DMB5
DMB6
DMB7
DMB8
DDRVTT
BC131
BC131
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
BC129
BC129
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
BC125
BC125
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
DDRVTT
BC118
BC118
22U/8/X5R/6.3V/M
22U/8/X5R/6.3V/M
MDB[0..63] <5>
DDRVTT Decouple
DDRVTT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
0.1u/4/Y5V/16V/ZBC149 0.1u/4/Y5V/16V/ZBC149
GIGABYTE
GIGABYTE
GIGABYTE
DDRII CHANNEL A
DDRII CHANNEL A
DDRII CHANNEL A
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
-DQSB[0..8] <5>
DQSB[0..8] <5>
DMB[0..8] <5>
MB_CK[0..7] <5>
BC9
BC9
0.1u/4/Y5V/16V/Z
0.1u/4/Y5V/16V/Z
1
8 27
8 27
8 27
1
5
4
3
2
1
L0_CADIN_L[0..15]
L0_CADIN_H[0..15]
L0_CADOUT_L[0..15]
D D
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
C C
L0_CLKOUT_H0<4>
L0_CLKOUT_L0<4>
L0_CLKOUT_H1<4>
L0_CLKOUT_L1<4>
L0_CTLOUT_H0<4>
L0_CTLOUT_L0<4>
L0_CTLOUT_H1<4>
L0_CTLOUT_L1<4>
R267 301/4/1R267 301/4/1
B B
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
HT_RXCALP
HT_RXCALN
VCORE
BC14
BC14
0.1U/4/X7R/16V/K
0.1U/4/X7R/16V/K
L0_CADOUT_H[0..15]
U3A
U3A
Y25
HT_RXCAD0P
Y24
HT_RXCAD0N
V22
HT_RXCAD1P
V23
HT_RXCAD1N
V25
HT_RXCAD2P
V24
HT_RXCAD2N
U24
HT_RXCAD3P
U25
HT_RXCAD3N
T25
HT_RXCAD4P
T24
HT_RXCAD4N
P22
HT_RXCAD5P
P23
HT_RXCAD5N
P25
HT_RXCAD6P
P24
HT_RXCAD6N
N24
HT_RXCAD7P
N25
HT_RXCAD7N
AC24
HT_RXCAD8P
AC25
HT_RXCAD8N
AB25
HT_RXCAD9P
AB24
HT_RXCAD9N
AA24
HT_RXCAD10P
AA25
HT_RXCAD10N
Y22
HT_RXCAD11P
Y23
HT_RXCAD11N
W21
HT_RXCAD12P
W20
HT_RXCAD12N
V21
HT_RXCAD13P
V20
HT_RXCAD13N
U20
HT_RXCAD14P
U21
HT_RXCAD14N
U19
HT_RXCAD15P
U18
HT_RXCAD15N
T22
HT_RXCLK0P
T23
HT_RXCLK0N
AB23
HT_RXCLK1P
AA22
HT_RXCLK1N
M22
HT_RXCTL0P
M23
HT_RXCTL0N
R21
HT_RXCTL1P
R20
HT_RXCTL1N
C23
HT_RXCALP
A24
HT_RXCALN
RS780L/FCBGA528/A13/[10HB1-06760G-20R]
RS780L/FCBGA528/A13/[10HB1-06760G-20R]
BC7
BC7
0.1U/4/X7R/16V/K
0.1U/4/X7R/16V/K
L0_CADIN_L[0..15] <4>
L0_CADIN_H[0..15] <4>
L0_CADOUT_L[0..15] <4>
L0_CADOUT_H[0..15] <4>
PART 1 OF 6
PART 1 OF 6
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H24
H25
L21
L20
M24
M25
P19
R18
B24
B25
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
HT_TXCALP
HT_TXCALN
L0_CLKIN_H0 <4>
L0_CLKIN_L0 <4>
L0_CLKIN_H1 <4>
L0_CLKIN_L1 <4>
L0_CTLIN_H0 <4>
L0_CTLIN_L0 <4>
L0_CTLIN_H1 <4>
L0_CTLIN_L1 <4>
R268 301/4/1R268 301/4/1
PCIE2_IP<17>
PCIE2_IN<17>
ML_IP<19>
ML_IN<19>
A_RX0P<13>
A_RX0N<13>
A_RX1P<13>
A_RX1N<13>
A_RX2P<13>
A_RX2N<13>
A_RX3P<13>
A_RX3N<13>
EXP_A_RXP[0..15]
EXP_A_RXN[0..15]
EXP_A_RXP0
EXP_A_RXN0
EXP_A_RXP1
EXP_A_RXN1
EXP_A_RXP2
EXP_A_RXN2
EXP_A_RXP3
EXP_A_RXN3
EXP_A_RXP4
EXP_A_RXN4
EXP_A_RXP5
EXP_A_RXN5
EXP_A_RXP6
EXP_A_RXN6
EXP_A_RXP7
EXP_A_RXN7
EXP_A_RXP8
EXP_A_RXN8
EXP_A_RXP9
EXP_A_RXN9
EXP_A_RXP10
EXP_A_RXN10
EXP_A_RXP11
EXP_A_RXN11
EXP_A_RXP12
EXP_A_RXN12
EXP_A_RXP13
EXP_A_RXN13
EXP_A_RXP14
EXP_A_RXN14
EXP_A_RXP15
EXP_A_RXN15
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
EXP_A_RXP[0..15] <17>
EXP_A_RXN[0..15] <17>
U3B
U3B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS780L/FCBGA528/A13/[10HB1-06760G-20R]
RS780L/FCBGA528/A13/[10HB1-06760G-20R]
PART 2 OF 6
PART 2 OF 6
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
EXP_A_TXP[0..15]
EXP_A_TXN[0..15]
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
PCIE I/F GFX
PCIE I/F GFX
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
SB_TX3N
EXP_A_TXP[0..15] <17>
EXP_A_TXN[0..15] <17>
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
AC1
AC2
GPP_TX1P_C
AB4
GPP_TX1N_C
AB3
GPP_TX2P_C
AA2
GPP_TX2N_C
AA1
Y1
Y2
Y4
Y3
V1
V2
A_TX0P_C
AD7
A_TX0N_C
AE7
A_TX1P_C
AE6
A_TX1N_C
AD6
A_TX2P_C
AB6
A_TX2N_C
AC6
A_TX3P_C
AD5
A_TX3N_C
AE5
R210 1.27K/4/1R210 1.27K/4/1
AC8
R212 2K/4/1R212 2K/4/1
AB8
EXP_A_TXP0
EXP_A_TXN0
EXP_A_TXP1
EXP_A_TXN1
EXP_A_TXP2
EXP_A_TXN2
EXP_A_TXP3
EXP_A_TXN3
EXP_A_TXP4
EXP_A_TXN4
EXP_A_TXP5
EXP_A_TXN5
EXP_A_TXP6
EXP_A_TXN6
EXP_A_TXP7
EXP_A_TXN7
EXP_A_TXP8
EXP_A_TXN8
EXP_A_TXP9
EXP_A_TXN9
EXP_A_TXP10
EXP_A_TXN10
EXP_A_TXP11
EXP_A_TXN11
EXP_A_TXP12
EXP_A_TXN12
EXP_A_TXP13
EXP_A_TXN13
EXP_A_TXP14
EXP_A_TXN14
EXP_A_TXP15
EXP_A_TXN15
C130 0.1U/4/X7R/16V/KC130 0.1U/4/X7R/16V/K
C129 0.1U/4/X7R/16V/KC129 0.1U/4/X7R/16V/K
C136 0.1U/4/X7R/16V/KC136 0.1U/4/X7R/16V/K
C137 0.1U/4/X7R/16V/KC137 0.1U/4/X7R/16V/K
C138 0.1U/4/X7R/16V/KC138 0.1U/4/X7R/16V/K
C139 0.1U/4/X7R/16V/KC139 0.1U/4/X7R/16V/K
C140 0.1U/4/X7R/16V/KC140 0.1U/4/X7R/16V/K
C141 0.1U/4/X7R/16V/KC141 0.1U/4/X7R/16V/K
C142 0.1U/4/X7R/16V/KC142 0.1U/4/X7R/16V/K
C143 0.1U/4/X7R/16V/KC143 0.1U/4/X7R/16V/K
C144 0.1U/4/X7R/16V/KC144 0.1U/4/X7R/16V/K
C145 0.1U/4/X7R/16V/KC145 0.1U/4/X7R/16V/K
NB_VCC
PCIE2_OP <17>
PCIE2_ON <17>
ML_OP <19>
ML_ON <19>
A_TX0P <13>
A_TX0N <13>
A_TX1P <13>
A_TX1N <13>
A_TX2P <13>
A_TX2N <13>
A_TX3P <13>
A_TX3N <13>
PLACE CAP CLOSE
TO CONNECTOR
1
NB_HS
NB_HS
1
A A
2
2
NB_HS/[12SPS-SA0502-01R_12SPS-SA0502-02R]
NB_HS/[12SPS-SA0502-01R_12SPS-SA0502-02R]
5
4
3
2
Title
Title
Title
RS780 HT-LINK I/F
RS780 HT-LINK I/F
RS780 HT-LINK I/F
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
GA-78LMT-S2 1.0
1
9 27Wednesday, April 11, 2012
9 27Wednesday, April 11, 2012
9 27Wednesday, April 11, 2012
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