Gigabyte F71862 Schematics

F71862

F71862FG

Super Hardware Monitor + LPC I/O

Release Date: Nov., 2006 Version: V0.21P

Nov., 2006

V0.21P

F71862 Datasheet Revision History

Version Date Page Revision History

0.10P 2006/04/21 - Preliminary Version

0.20P 2006/06/14 - Release Version

0.21P 2006/11/23 62 Modified the description of Wakeup Control Register 2Dh

F71862

bit 7(SPI_CS1_EN)

Please note that all data and specifications are subject to change without notice. All the trade marks of products

and companies mentioned in this data sheet belong to their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from

such improper use or sales.

Nov., 2006

V0.21P

F71862

Table of Content

1. General Description........................................................................................................................6

2. Feature List .....................................................................................................................................6

3. Key Specification............................................................................................................................9

4. Block Diagram................................................................................................................................9

5. Pin Configuration..........................................................................................................................10

6. Pin Description..............................................................................................................................10

6.1 Power Pin..................................................................................................................................11

6.2 LPC Interface............................................................................................................................11

6.3 FDC...........................................................................................................................................11

6.4 UART and SIR..........................................................................................................................12

6.5 Parallel Port...............................................................................................................................14

6.6 Hardware Monitor.....................................................................................................................15

6.7 ACPI Function Pins ..................................................................................................................16

6.8 VID Controller and Others........................................................................................................17

6.9 KPC Function............................................................................................................................17

7. Function Description.....................................................................................................................18

7.1 Power on Strapping Option.......................................................................................................18

7.2 FDC...........................................................................................................................................18

7.3 UART........................................................................................................................................32

7.4 Parallel Port...............................................................................................................................35

7.5 Keyboard Contoller...................................................................................................................39

7.6 Hardware Monitor.....................................................................................................................41

7.7 SPI Interface..............................................................................................................................49

7.8 ACPI Function..........................................................................................................................49

7.9 AMDSI and Intel PECI Function..............................................................................................52

8. Register Description......................................................................................................................54

8.1 Global Control Registers...........................................................................................................58

8.2 FDC Registers (CR00)..............................................................................................................63

8.3 UART1 Registers (CR01).........................................................................................................65

8.4 UART 2 Registers (CR02)........................................................................................................66

8.5 Parallel Port Registers (CR03)..................................................................................................68

8.6 Hardware Monitor Registers (CR04)........................................................................................70

8.6.2.1 Configuration Register  Index 01h..................................................................................70

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F71862

8.6.2.2 Configuration Register  Index 02h..................................................................................70

8.6.2.3 Configuration Register  Index 03h..................................................................................71

8.6.2.4 Configuration Register  Index 0Ah.................................................................................71

8.6.2.5 Configuration Register  Index 0Bh (MEAS_TYPE == 2’b01) ...................................71

8.6.2.6 Configuration Register  Index 0Bh (MEAS_TYPE ==2’b10) ....................................72

8.6.2.7 Configuration Register  Index 0Ch (MEAS_TYPE == 2’b01) ...................................72

8.6.2.8 Configuration Register  Index 0Ch (MEAS_TYPE ==2’b10) ....................................72

8.6.2.9 Configuration Register  Index 0Dh.................................................................................72

8.6.2.10 Configuration Register  Index 0Eh...............................................................................72

8.6.2.11 Configuration Register  Index 0Fh................................................................................72

8.6.2.12 Voltage1 Voltage reading and limit Index 20h- 4Fh .....................................................72

8.6.2.13 Temperature PME# Enable Register  Index 60h...........................................................73

8.6.2.14 Temperature Interrupt Status Register  Index 61h ........................................................73

8.6.2.15 Temperature Real Time Status Register  Index 62h......................................................74

8.6.2.16 Temperature BEEP Enable Register  Index 63h...........................................................74

8.6.2.17 OVT Output Enable Register 1  Index 66h...................................................................74

8.6.2.18 Temperature Sensor Type Register  Index 6Bh ............................................................75

8.6.2.19 TEMP1 Limit Hystersis Select Register -- Index 6Ch.....................................................75

8.6.2.20 TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh................................75

8.6.2.21 DIODE OPEN Status Register -- Index 6Fh....................................................................75

8.6.2.22 Temperature Filter Select Register -- Index 8Eh .............................................................76

8.6.2.23 FAN PME# Enable Register  Index 90h.......................................................................76

8.6.2.24 FAN Interrupt Status Register

 Index 91h.....................................................................76

8.6.2.25 FAN Real Time Status Register  Index 92h..................................................................77

8.6.2.26 FAN BEEP# Enable Register  Index 93h .....................................................................77

8.6.2.27 Fan Type Select Register -- Index 94h.............................................................................77

8.6.2.28 Fan mode Select Register -- Index 96h............................................................................78

8.6.2.29 Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h..........................78

8.6.2.30 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 99h..........................78

8.6.2.31 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 9Bh..........................78

8.6.2.32 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE

 Index 9Ch........................79

8.6.2.33 FAN3 START UP DUTY-CYCLE/VOLTAGE  Index 9Dh .........................................79

8.6.2.34 Fan Fault Time Register -- Index 9Fh..............................................................................79

8.6.2.35 VT1 BOUNDARY 1 TEMPERATURE – Index A6h......................................................80

8.6.2.36 VT1 BOUNDARY 2 TEMPERATURE – Index A9........................................................80

8.6.2.37 FAN1 SEGMENT 1 SPEED COUNT – Index ABh.....................................................80

8.6.2.38 FAN1 SEGMENT 2 SPEED COUNT – Index AEh...................................................80

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F71862

8.6.2.39 FAN1 Temperature Mapping Select – Index AFh.......................................................80

8.6.2.40 VT2 BOUNDARY 1 TEMPERATURE – Index B6h......................................................81

8.6.2.41 VT2 BOUNDARY 2 TEMPERATURE – Index B9........................................................81

8.6.2.42 FAN2 SEGMENT 1 SPEED COUNT – Index BBh.....................................................81

8.6.2.43 FAN2 SEGMENT 2 SPEED COUNT – Index BEh...................................................82

8.6.2.44 FAN2 Temperature Mapping Select – Index BFh.......................................................82

8.6.2.45 VT3 BOUNDARY 1 TEMPERATURE – Index C6h......................................................83

8.6.2.46 VT3 BOUNDARY 2 TEMPERATURE – Index C9........................................................83

8.6.2.47 FAN3 SEGMENT 1 SPEED COUNT – Index CBh.....................................................83

8.6.2.48 FAN3 SEGMENT 2 SPEED COUNT – Index CEh...................................................83

8.6.2.49 FAN3 Temperature Mapping Select – Index CFh.......................................................83

8.7 KBC Registers (CR05) .............................................................................................................84

8.8 GPIO Registers (CR06) ............................................................................................................85

8.9 VID Registers (CR07)...............................................................................................................92

8.10 SPI Registers (CR08)................................................................................................................94

8.11 PME and ACPI Registers (CR0A)............................................................................................97

9. Electron Characteristic................................................................................................................100

9.1 Absolute Maximum Ratings...................................................................................................100

9.2 DC Characteristics..................................................................................................................100

9.3 DC Characteristics Continued.................................................................................................100

10. Ordering Information..................................................................................................................101

11. Package Dimensions...................................................................................................................102

12. Application Circuit......................................................................................................................103

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F71862

1. General Description

The F71862 is the featured IO chip for PC system. Equipped with one IEEE 1284

Parallel Port, two UART Ports, Hardware Keyboard Controller, Serial Peripheral Interface

(SPI), SIR and one FDC. The F71862 integrated with hardware monitor, 9 sets of voltage sensor, 3 sets of creative auto-controlling fans and 3 temperature sensor pins for the

accurate dual current type temp. measurement for CPU thermal diode or external

transistors 2N3906. Others, the F71862 supports newest AMDSI and Intel PECI interfaces for temperature sensing.

The F71862 provides flexible features for multi-directional application. For instance,

supports 4-In and 4-Out pins CPU VID controlling with offset implement., provides 30 GPIO pins (multi-pin), IRQ sharing function also designed in UART feature for particular usage

and accurate current mode H/W monitor will be worth in measurement of temperature,

provides 3 modes fan speed control mechanism included Manual Mode/Stage Auto Mode/Linear Auto Mode for users’ selection.

The F71862 also integrated SPI interface. The SPI interface is for BIOS usage

including bridge function and back up function. User can implement BIOS data in second flash to boot system when primary BIOS error. These features as above description will help

you more and improve product value. Finally, the F71862 is powered by 3.3V voltage, with

the LPC interface in the green package of 128-PQFP.

2. Feature List

General Functions

¾ Comply with LPC Spec. 1.0

¾ Support DPM (Device Power Management), ACPI

¾ 4-VIDIN and 4-VIDOUT for Vcore use.

¾ Provides one FDC, two UARTs, Hardware KBC and Parallel Port

¾ H/W monitor functions

¾ SPI interface for BIOS usage

¾ Support AMD SID/SIC interface and Intel PECI interface

¾ 30 GPIO Pins for flexible application

¾ 24/48 MHz clock input

¾ Packaged in 128-PQFP and powered by 3.3VCC

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F71862

FDC

¾ Compatible with IBM PC AT disk drive systems

¾ Variable write pre-compensation with track selectable capability

¾ Support vertical recording format

¾ DMA enable logic

¾ 16-byte data FIFOs

¾ Support floppy disk drives and tape drives

¾ Detects all overrun and under run conditions

¾ Built-in address mark detection circuit to simplify the read electronics

¾ Completely compatible with industry standard 82077

¾ 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate

UART

¾ Two high-speed 16C550 compatible UART with 16-byte FIFOs

¾ Fully programmable serial-interface characteristics

¾ Baud rate up to 115.2K

¾ Support IRQ sharing

Infrared

¾ Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps

Parallel Port

¾ One PS/2 compatible bi-directional parallel port

¾ Support Enhanced Parallel Port (EPP)

¾ Support Extended Capabilities Port (ECP)

specification

¾ Enhanced printer port back-drive current protection

− Compatible with IEEE 1284 specification

− Compatible with IEEE 1284

Keyboard Controller

¾ LPC interface support serial interrupt channel 1, 12.

¾ Two 16bit Programmable Address fully decoder, default 0x60 and 0x64.

¾ Support two PS/2 interface, one for PS/2 mouse and the other for keyboard.

¾ Keyboard’s scan code support set1, set2.

¾ Programmable compatibility with the 8042.

¾ Support both interrupt and polling modes.

¾ Fast Gate A20 and Hardware Keyboard Reset.

Hardware Monitor Functions

¾ 3 dual current type (±3℃) thermal inputs for CPU thermal diode and 2N3906 transistors

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¾ Temperature range -40℃~127 ℃

¾ 9 sets voltage monitoring (6 external and 3 internal powers)

¾ High limit signal (PME#) for Vcore level

¾ 3 fan speed monitoring inputs

¾ 3 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans)

¾ Stage auto mode ( 2-Limit and 3-Stage)/Linear auto mode/Manual mode

¾ Issue PME# and OVT# hardware signals output

¾ Case intrusion detection circuit

¾ WATCHDOG comparison of all monitored values

Serial Peripheral Interface Compatible

¾ Support SPI Bridge Function for BIOS use

¾ Support Back Up BIOS function

Integrate AMD SI Interface Integrate Intel PECI Interface

F71862

Package

¾ 128-pin PQFP Green Package

Noted: Patented TW207103 TW207104 TW220442 US6788131 B1 TWI235231 TW237183 TW235553

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3. Key Specification

Supply Voltage 3.0V to 3.6V

Operating Supply Current 10 mA typ.

4. Block Diagram

CPU

Chipset

(NB+SB)

F71862

Super H/W Monitor + I/O

F71862

IDE

USB

AC’97

Temperature Voltage Fan

AMDSI

A PECI

KBC

IrDA

Parallel

ACPI

SPI

LED(GPIO)

COM

Floppy

VID

Controlle

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5. Pin Configuration

F71862

6. Pin Description

I/O

- TTL level bi-directional pin with 12 mA source-sink cap ability.

12t

I/OOD

I/OD

16t5v

16-u10-5v

I/OD

12ts5v

ILv/O

D8-S1

ILv/OD

- TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA

12t

source-sink capability.

- TTL level bi-directional pin,Open-drain output with 16 mA source-sink capability, 5V tolerance.

- Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance.

- TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink capability, 5V tolerance.

- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 8mA drive and 1mA sink capability.

- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 12mA sink

capability.

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F71862

O O O O30 AOUT - Output pin(Analog). OD OD OD24 IN INts IN AIN - Input pin(Analog). P - Power.

6.1 Power Pin

Pin No. Pin Name Type Description

4,37,99 VCC P Power supply voltage input with 3.3V

68 VSB P Stand-by power supply voltage input 3.3V

86 VBAT P Battery voltage input

88 AGND(D-) P Analog GND

20, 48, 73, 117 GND P Digital GND

- Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.

8-u47-5v

- Output pin with 8 mA source-sink capability.

- Output pin with 12 mA source-sink capability.

- Output pin with 30 mA source-sink capability.

12-5v

- Open-drain output pin with 12 mA sink capability.

- Open-drain output pin with 12 mA sink capability, 5V tolerance.

- Open-drain output pin with 24 mA sink capability.

t5v

- TTL level input pin,5V tolerance.

- TTL level input pin and schmitt trigger.

- TTL level input pin and schmitt trigger, 5V tolerance.

ts5v

6.2 LPC Interface

Pin No. Pin Name Type PWR Description

29 LRESET# IN

VCC Reset signal. It can connect to PCIRST# signal on the

ts5v

host.

30 LDRQ# O12 VCC Encoded DMA Request signal.

31 SERIRQ I/O

VCC Serial IRQ input/Output.

12t

32 LFRAM# INts VCC Indicates start of a new cycle or termination of a

broken cycle.

36-33 LAD[3:0] I/O

VCC These signal lines communicate address, control, and

12t

data information over the LPC bus between a host and a peripheral.

38 PCICLK INts VCC 33MHz PCI clock input.

39 CLKIN INts VCC System clock input. According to the input frequency

24/48MHz.

6.3 FDC

Pin No. Pin Name Type PWR Description

DENSEL#

OD24 VCC Drive Density Select.

Set to 1 - High data rate.(500Kbps, 1Mbps) Set to 0 – Low data rate. (250Kbps, 300Kbps)

OD24 VCC Motor A On. When set to 0, this pin enables disk drive

MOA#

0. This is an open drain output.

9 DRVA# OD24 VCC Drive Select A. When set to 0, this pin enables disk

drive A. This is an open drain output.

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10 WDATA# OD24 VCC Write data. This logic low open drain writes

pre-compensation serial data to the selected FDD. An open drain output.

11 DIR# OD24 VCC Direction of the head step motor. An open drain output.

Logic 1 = outward motion Logic 0 = inward motion

12 STEP# OD24 VCC Step output pulses. This active low open drain output

produces a pulse to move the head to another track.

13 HDSEL# OD24 VCC Head select. This open drain output determines which

disk drive head is active. Logic 1 = side 0 Logic 0 = side 1

14 WGATE# OD24 VCC Write enable. An open drain output.

15 RDATA# IN

16 TRK0# IN

17 INDEX# IN

18 WPT# IN

19 DSKCHG# IN

VCC The read data input signal from the FDD.

ts5v

VCC Track 0. This Schmitt-triggered input from the disk

ts5v

drive is active low when the head is positioned over the outermost track.

VCC This Schmitt-triggered input from the disk drive is

ts5v

active low when the head is positioned over the beginning of a track marked by an index hole.

VCC Write protected. This active low Schmitt input from the

ts5v

disk drive indicates that the diskette is write-protected.

VCC Diskette change. This signal is active low at power on

ts5v

and whenever the diskette is removed.

6.4 UART and SIR

Pin No. Pin Name Type PWR Description

IRTX O12 Infrared Transmitter Output. 27

GPIO42 I/OOD

IRRX INts Infrared Receiver input. 28

GPIO43 I/OOD

118 DCD1# IN

119 RI1# IN

120 CTS1# IN

121

DTR1#

FAN60_100 IN

VCC Data Carrier Detect. An active low signal indicates th

t5v

VCC Ring Indicator. An active low signal indicates that a ring

t5v

VCC Clear To Send is the modem control input.

t5v

8-u47,5v

t5v

VCC

12t

General Purpose IO

VSB

12t

General Purpose IO.

modem or data set has detected a data carrier.

signal is being received from the modem or data set.

VCC

UART 1 Data Terminal Ready. An active low signa

informs the modem or data set that controller is ready t communicate. Internal 47k ohms pulled high and disabl after power on strapping.

Power on strapping pin: 1(Default): (Internal pull high) Power on fan speed default duty is 60%.(PWM) 0: (External pull down) Power on fan speed default duty is 100%.(PWM)

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122 RTS1#

123 DSR1# IN

124

SOUT1

Config4E_2E IN

125 SIN1 IN

126 DCD2# IN

F71862

VCC UART 1 Request To Send. An active low signal inform

8-u47,5v

the modem or data set that the controller is ready t send data. Internal 47k ohms pulled high and disabl after power on strapping.

VCC Data Set Ready. An active low signal indicates th

t5v

modem or data set is ready to establish communication link and transfer data to the UART.

VCC

UART 1 Serial Output. Used to transmit serial data ou

8-u47,5v

to the communication link. Internal 47k ohms pulled hig and disable after power on strapping.

t5v

VCC Serial Input. Used to receive serial data through th

t5v

VCC Data Carrier Detect. An active low signal indicates th

t5v

Power on strapping: 1(Default)Configuration register:4E

0 Configuration register:2E

communication link.

modem or data set has detected a data carrier.

127 RI2#

128 CTS2# IN

DTR2#

FWH_TRAP IN

RTS2#

HPWM_DC IN

3 DSR2# IN

SOUT2

SPI_TRAP

t5v

VCC Ring Indicator. An active low signal indicates that a rin

signal is being received from the modem or data set.

VCC Clear To Send is the modem control input.

t5v

VCC

UART 2 Data Terminal Ready. An active low signa

8-u47,5v

informs the modem or data set that controller is ready t communicate. Internal 47k ohms pulled high and disabl after power on strapping.

t5v

Power on strapping : 1(Default): SPI as a backup BIOS 0 : SPI as a primary BIOS

VCC

UART 2 Request To Send. An active low signal inform

8-u47,5v

the modem or data set that the controller is ready t send data. Internal 47k ohms pulled high and disabl after power on strapping.

t5v

Power on strapping :

1 (Default): Fan control method will be PWM Mode

0 Drive :Fan control method will be DAC Mode

VCC Data Set Ready. An active low signal indicates th

t5v

modem or data set is ready to establish communication link and transfer data to the UART.

VCC

UART 2 Serial Output. Used to transmit serial data ou

8-u47,5v

to the communication link. Internal 47k ohms pulle high and disable after power on strapping.

t5v

Power on strapping:

1(Default) : SPI function disable

0 : SPI function enable

6 SIN2 IN

66 GPIO17 I/OOD

t5v

VCC Serial Input. Used to receive serial data through th

communication link.

VSB General Purpose IO

12t

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F71862

6.5 Parallel Port

Pin No. Pin Name Type PWR Description

100 SLCT IN

101 PE IN

102 BUSY IN

103 ACK# IN

104 SLIN# OD

105 INIT#

106 ERR#

107 AFD# OD

108 STB# OD

109

110

111

112

113

114

115

116

I/O

PD0

I/O

PD1

I/O

PD2

I/O

PD3

I/O

PD4

I/O

PD5

I/O

PD6

I/O

PD7

VCC An active high input on this pin indicates that the

ts5v

printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode.

VCC An active high input on this pin indicates that the

ts5v

printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

VCC An active high input indicates that the printer is not

ts5v

ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode.

VCC An active low input on this pin indicates that the printer

ts5v

has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

VCC Output line for detection of printer selection. Refer to

12-5v

the description of the parallel port for the definition of this pin in ECP and EPP mode.

VCC Output line for the printer initialization. Refer to the

12-5v

description of the parallel port for the definition of this pin in ECP and EPP mode.

ts5v

VCC An active low input on this pin indicates that the printer

has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

VCC An active low output from this pin causes the printer to

12-5v

auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

VCC An active low output is used to latch the parallel data

12-5v

into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode.

VCC Parallel port data bus bit 0. Refer to the description of

12ts5v

the parallel port for the definition of this pin in ECP and EPP mode.

VCC Parallel port data bus bit 1.

12ts5v

VCC Parallel port data bus bit 2.

12ts5v

VCC Parallel port data bus bit 3.

12ts5v

VCC Parallel port data bus bit 4.

12ts5v

VCC Parallel port data bus bit 5.

12ts5v

VCC Parallel port data bus bit 6.

12ts5v

VCC Parallel port data bus bit 7.

12ts5v

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F71862

6.6 Hardware Monitor

Pin No. Pin Name Type PWR Description

93-97 VIN6~VIN2 AIN VCC Voltage Input 2 ~ 6.

98 Vcore(VIN1) AIN VCC Voltage Input for Vcore.

21 FANIN1 IN

22 FAN_CTL1 OD

ts5v

12-5v

AOUT

23 FANIN2 IN

24 FAN_CTL2 OD

ts5v

12-5v

AOUT

FANIN3 IN

ts5v

GPIO40 I/OOD

FAN_CTL3*

12-5V

AOUT

GPIO41 I/OOD

89 D3+(System) AIN VCC Thermal diode/transistor temperature sensor input for

90 D2+ AIN VCC Thermal diode/transistor temperature sensor input.

91 D1+(CPU) AIN VCC CPU thermal diode/transistor temperature sensor

92 VREF AOUT

PME#

12-5v

GPIO25 I/OOD

GPIO10 I/OOD

SPI_SLK O12

GPIO11 I/OOD

SPI_CS0# O12

GPIO12 I/OOD

SPI_MISO IN

t5v

VCC Fan 1 tachometer input.

VCC Fan 1 control output. This pin provides PWM

duty-cycle output or a voltage output.

VCC Fan 2 tachometer input.

VCC Fan 2 control output. This pin provides PWM

duty-cycle output or a voltage output.

VCC

12t

VCC

Fan 3 speed input. 25

General purpose IO.

Fan 3 control output. This pin provides PWM duty-cycle output or a voltage output. *This pin default function is FANCTL (PWM signal output), please take care the application if user want to implement GPIO function.

12t

General purpose IO.

system use.

input. This pin is for CPU use.

VCC Voltage sensor output.

VSB

Generated PME event. It supports the PCI PME# interface. This signal allows the peripheral to request the system to wake up from the S3 state.

12t

VSB

General Purpose IO.

General purpose IO. 59

Serial clock output pin for SPI device.

12t

VSB

General purpose IO. 60

Function A: When using firmware hub BIOS for primary BIOS and SPI BIOS for second BIOS, please connect this pin to SPI BIOS chip select pin. Function B: When using two SPI Flashes for primary and back up BIOS, please connect this pin to primary BIOS chip select pin.

VSB

12t

General purpose IO.

SPI master in/slave out pin.

FANCTL1_1 OD

12-5v

GPIO13 I/OOD

SPI_MOSI O12

BEEP OD24

63 GPIO14 I/OOD

Fan 1 control output. This pin provides PWM duty-cycle open drain output for Intel 4-pin Fan.

12t

VSB

General purpose IO.

SPI master out/slave in pin.

Beep pin.

VSB General purpose IO.

12t

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F71862

67 OVT# OD

FWH_DIS O12 Firmware hub disable

WDTRST# OD

SPI_CS1# O

12-5v

6.7 ACPI Function Pins

Pin No. Pin Name Type PWR Description

GPIO15 I/OOD

LED_VSB OD12 Power LED for VSB.

ALERT# OD

GPIO16 I/OOD

LED_VCC OD

PCIRST1# OD12 It is a output buffer of RSTCON# and LRESET#. 74

GPIO20 I/OOD

PCIRST2# O12 It is a output buffer of RSTCON# and LRESET#. 75

GPIO21 I/OOD

PCIRST3# O12 It is a output buffer of RSTCON# and LRESET#. 76

Watch dog timer signal output.

When using two SPI Flashes for primary and back up BIOS, please connect this pin to back up BIOS chip select pin.

VSB Over temperature signal output.

VSB

12t

VSB

12t

General purpose IO.

Alert a signal when temperature over limit setting.

General purpose IO. 65

Power LED for VCC.

VSB

General purpose IO.

VSB

General purpose IO.

VSB

GPIO22 I/OOD

S5# IN

GPIO23 I/OOD12 General purpose IO. (Default)

RSTCON#

ATXPG_IN AIN ATX Power Good input. 78

GPIO24 I/OOD

PWROK OD12 PWROK function, It is power good signal of VCC,

GPIO32 I/OOD

PWSIN# IN

GPIO26 I/OOD

PWSOUT#

OD12 Panel Switch Output. This pin is low active and pulse

GPIO27 I/OOD

S3# IN

GPIO30 I/OOD

PSON#

GPIO31 I/OOD

RSMRST#

OD12 Resume Reset# function, It is power good signal of

GPIO33 I/OOD

87 COPEN# IN

S5# signal input.

ts5v

VSB

General purpose IO.

RESET Connect# with 50ms debouce function, it connects to reset button, and also other reset source on the motherboard.

VSB

12t

General purpose IO.

VSB

which is delayed 400ms (default) as VCC arrives at

2.8V.

General purpose IO.

ts5v

12t

VSB Main power switch button input. 80

General purpose IO.

12t

VSB

output. It is power on request output#.

12t

ts5v

12-5v

VSB

12t

VSB Power supply on-off control output. Connect to ATX

General purpose IO.

S3# Input is Main power on-off switch input. 82

General purpose IO.

power supply PS_ON# signal.

General purpose IO.

12t

VBAT

VSB, which is delayed 66ms as VSB arrives at 2.3V.

12t

VBAT Case Open Detection #. This pin is connected to a

ts5v

General purpose IO.

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specially designed low power CMOS flip-flop backed by the battery for case open state preservation during power loss.

6.8 VID Controller and Others

Pin No. Pin Name Type PWR Description

45-42 VIDIN[D:A] IN

52-49 VIDOUT[D:A] OD12 VSB CPU VID output pins.

ts5v

VCC CPU VID input pins.

Special level input VIHÆ 0.9, VIL Æ 0.6

F71862

46 GPIO44 I/OOD

47 GPIO45 I/OOD

53 GPIO00 I/OOD

54 GPIO01 I/OOD

ST2 OD

VCC General purpose IO.

12t

VCC General purpose IO.

12t

VSB General purpose pin.

12t

VSB General purpose pin.

12t

VSB

Status Pin2 for S0#/S3#/S5# states application. In S0# Æ ST2 pin status is Tri-state. In S3# Æ ST2 pin status is Low level. In S5# Æ ST2 pin status is Low level, and can be programmed to Tri-state.

SLOTOCC# IN

GPIO02 I/OOD

ST1 OD12 Status Pin1 for S0#/S3#/S5# states application.

ts5v

12t

VSB

CPU SLOTOCC# input.

General purpose pin.

In S0# Æ ST1 pin status is Tri-state. In S3# Æ ST1 pin status is Low level. In S5# Æ ST1 pin status is Tri-state.

GPIO03 I/OOD

WDTRST# OD

12-5v

12t

General purpose pin.

Watch dog timer signal output.

57 SIC OD12 VSB AMDSI interface clock output.

PECI ILv/O

SID I

/OD

D8-S1

VSB

Intel PECI hardware monitor interface. 58

AMDSI interface data input.

6.9 KPC Function

Pin No. Pin Name Type PWR Description

40 KBRST#

41 GA20

69 KDATA I/OD

70 KCLK I/OD

71 MDAT I/OD

72 MCLK I/OD

16-u10,5V

16t,5V

VCC Keyboard reset. This pin is high after system reset.

Internal pull high 3.3V with 10k ohms. (KBC P20)

VCC Gate A20 output. This pin is high after system reset.

Internal pull high 3.3V with 10k ohms. (KBC P21)

VSB Keyboard Data.

VSB Keyboard Clock.

VSB PS2 Mouse Data.

VSB PS2 Mouse Clock.

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7. Function Description

7.1 Power on Strapping Option

The F71862 provides four pins for power on hardware strapping to select functions. There

is a form to describe how to set the functions you want.

Pin No. Symbol Value Description

1 SPI as a backup BIOS (Default) 1 FWH_TRAP 0 SPI as a primary BIOS 1 Fan control mode: PWM mode. ( Default) 2 PWM_DC 0 Fan control mode: Linear mode. 1 SPI function disable (Default) 5 SPI_TRAP 0 SPI function enable 1 Power on Fan speed default duty is 60%(PWM)(Default) 121 FAN60_100 0 Power on Fan speed default duty is 100%(PWM) 1 Configuration Register I/O port is 4E/4F. (Default) 124 Config4E_2E 0 Configuration Register I/O port is 2E/2F.

7.2 FDC

The Floppy Disk Controller provides the interface between a host processor and one

floppy disk drives. It integrates a controller and a digital data separator with write

pre-compensation, data rate selection logic, microprocessor interface, and a set of registers.

The FDC supports data transfer rates of 250 Kbps, 300 Kbps, 500 Kbps, and 1 Mbps. It

operates in PC/AT mode and supports 3-mode type drives.

The FDC configuration is handled by software and a set of Configuration registers.

Status, Data, and Control registers facilitate the interface between the host microprocessor

and the disk drive, providing information about the condition and/or state of the FDC. These

configuration registers can select the data rate, enable interrupts, drives, and DMA modes,

and indicate errors in the data or operation of the FDC/FDD. The controller manages data

transfers using a set of data transfer and control commands. These commands are handled

in three phases: Command, Execution, and Result. Not all commands utilize all these three

phases.

The below content is about the FDC device register descriptions. All the registers are

for software porting reference.

Status Register A (PS/2 mode)  Base + 0

Bit Name R/W Default Description

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7 INTPEND R 0 This bit indicates the state of the interrupt output.

6 DRV2_N R - 0: a second drive has been installed.

1: a second drive has not been installed.

5 STEP R 0 This bit indicates the complement of STEP# disk interface output.

4 TRK0_N R - This bit indicates the state of TRK0# disk interface input.

3 HDSEL R 0 This bit indicates the complement of HDSEL# disk interface output.

0: side 0.

1: side 1.

2 INDEX_N R - This bit indicates the state of INDEX# disk interface input.

1 WPT_N R - This bit indicates the state of WPT# disk interface input.

0: disk is write-protected.

1: disk is not write-protected.

0 DIR R 0 This bit indicates the complement of DIR# disk interface output.

Status Register A (Model 30 mode)  Base + 0

Bit Name R/W Default Description

7 INTPEND R 0 This bit indicates the state of the interrupt output.

6 DRQ R 0 This bit indicates the state of the DRQ signal.

5 STEP_FF R 0 This bit indicates the complement of latched STEP# disk interface output.

4 TRK0 R - This bit indicates the complement of TRK0# disk interface input.

3 HDSEL_N R 1 This bit indicates the state of HDSEL# disk interface output.

0: side 0.

1: side 1.

2 INDEX R - This bit indicates the complement of INDEX# disk interface input.

1 WPT R - This bit indicates the complement of WPT# disk interface input.

0: disk is write-protected.

1: disk is not write-protected.

0 DIR_N R 1 This bit indicates the state of DIR# disk interface output.

0: head moves in inward direction.

1: head moves in outward direction.

Status Register B (PS/2 Mode)  Base + 1

Bit Name R/W Default Description

7-6 Reserved R 11 Reserved. Return 11b when read.

5 DR0 R 0 Drive select 0. This bit reflects the bit 0 of Digital Output Register.

4 WDATA R 0 This bit changes state at every rising edge of WDATA#.

3 RDATA R 0 This bit changes state at every rising edge of RDATA#.

2 WGATE R 0 This bit indicates the complement of WGATE# disk interface output.

1 MOTEN1 R 0 This bit indicates the complement of MOB# disk interface output. Not support

in this design.

0 MOTEN0 R 0 This bit indicates the complement of MOA# disk interface output.

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Status Register B (Model 30 Mode)  Base + 1

Bit Name R/W Default Description

7 DRV2_N R - 0: a second drive has been installed.

1: a second drive has not been installed.

6 DSB_N R 1 This bit indicates the state of DRVB# disk interface output. Not support in this

design.

5 DSA_N R 1 This bit indicates the state of DRVA# disk interface output.

4 WDATA_FF R 0 This bit is latched at the rising edge of WDATA# and is cleared by a read from

the Digital Input Register.

3 RDATA_FF R 0 This bit is latched at the rising edge of RDATA# and is cleared by a read form

the Digital Input Register.

2 WGATE_FF R 0 This bit is latched at the falling edge of WGATE# and is cleared by a read from

the Digital Input Register.

1 DSD_N R 1 This bit indicates the complement of DRVD# disk interface output. Not support

in this design.

0 DSC_N R 1 This bit indicates the complement of DRVC# disk interface output. Not support

in this design.

Digital Output Register  Base + 2

Bit Name R/W Default Description

7 MOTEN3 R 0 Motor enable 3. Not support in this design.

6 MOTEN2 R 0 Motor enable 2. Not support in this design.

5 MOTEN1 R/W 0 Motor enable 1. Used to control MOB#. MOB# is not support in this design.

4 MOTEN0 R/W 0 Motor enable 0. Used to control MOA#.

3 DAMEN R/W 0 DMA enable. This bit has two mode of operation.

PC-AT and Model 30 mode: write 1 will enable DMA and IRQ, write 0 will disable DMA and IRQ.

PS/2 mode: This bit is reserved. DMA and IRQ are always enabled in PS/2 mode.

2 RESET R 0 Write 0 to this bit will reset the controller. I will remain in reset condition until a 1

is written.

1 DSD_N R 1 This bit indicates the complement of DRVD# disk interface output. Not support

in this design.

0 DSC_N R 1 This bit indicates the complement of DRVC# disk interface output. Not support

in this design.

Tape Drive Register  Base + 3

Bit Name R/W Default Description

7-6 Reserved R 00 Reserved. Return 00b when read.

5-4 TYPEID R 11 Reserved in normal function, return 11b when read.

If 3 mode FDD function is enabled. These bits indicate the drive type ID.

3-2 Reserved R 11 Reserved. Return 11b when read in normal function.

Return 00b when read in 3 mode FDD function.

1-0 TAPESEL R/W 0 These bits assign a logical drive number to be a tape drive.

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Main Status Register  Base + 4

Bit Name R/W Default Description

7 RQM R 0 Request for Master indicates that the controller is ready to send or receive data

from the uP through the FIFO.

6 DIO R 0 Data I/O (direction):

0: the controller is expecting a byte to be written to the Data Register.

1: the controller is expecting a byte to be read from the Data Register.

5 NON_DMA R 0 Non DMA Mode:

0: the controller is in DAM mode.

1: the controller is interrupt or software polling mode.

4 FDC_BUSY R 0 This bit indicate that a read or write command is in process.

3 DRV3_BUSY R 0 FDD number 3 is in seek or calibration condition. FDD number 3 is not support

in this design.

2 DRV2_BUSY R 0 FDD number 2 is in seek or calibration condition. FDD number 2 is not support

in this design.

1 DRV1_BUSY R 0 FDD number 1 is in seek or calibration condition. FDD number 1 is not support

in this design.

0 DRV0_BUSY R 0 FDD number 0 is in seek or calibration condition.

Data Rate Select Register  Base + 4 Bit Name R/W Default Description

7 SOFTRST W 0 A 1 written to this bit will software reset the controller. Auto clear after reset. 6 PWRDOWN W 0 A 1 to this bit will put the controller into low power mode which will turn off the

5 Reserved - - Return 0 when read.

4-2 PRECOMP W 000 Select the value of write precompensation:

1-0 DRATE W 10 Data rate select:

oscillator and data separator circuits.

250K-1Mbps 2Mbps 000: default delays default delays 001: 41.67ns 20.8ns 010: 83.34ns 41.17ns 011: 125.00ns 62.5ns 100: 166.67ns 83.3ns 101: 208.33ns 104.2ns 110: 250.00ns 125.00ns 111: 0.00ns (disabled) 0.00ns (disabled)

The default value of corresponding data rate: 250Kbps: 125ns 300Kbps: 125ns 500Kbps: 125ns 1Mbps: 41.67ns 2Mbps: 20.8ns

MFM FM 00: 500Kbps 250Kbps 01: 300Kbps 150Kbps 10: 250Kbps 125Kbps 11: 1Mbps illegal

Data (FIFO) Register  Base + 5

Bit Name R/W Default Description

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7-0 DATA R/W 00h The FIFO is used to transfer all commands, data and status between controller

and the system. The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. The FIFO is default disabled and could be enabled via the CONFIGURE command.

Status Registers 0

Bit Name R/W Default Description

7-6 IC R - Interrupt code :

00: Normal termination of command.

01: Abnormal termination of command.

10: Invalid command.

11: Abnormal termination caused by poling.

5 SE R - Seek end.

Set when a SEEK or RECALIBRATE or a READ or WRITE with implied seek command is completed.

4 EC R - Equipment check.

0: No error

1: When a fault signal is received form the FDD or the TRK0# signal fails to occur after 77 step pulses.

3 NR R - Not ready.

0: Drive is ready

1: Drive is not ready.

2 HD R - Head address.

The current head address.

1-0 DS R - Drive select.

00: Drive A selected.

01: Drive B selected.

10: Drive C selected.

11: Drive D selected.

Status Registers 1

Bit Name R/W Default Description

7 EN R - End of Track.

Set when the FDC tries to access a sector beyond the final sector of a cylinder.

6 DE R - Data Error.

The FDC detect a CRC error in either the ID field or the data field of a sector.

4 OR R - Overrun/Underrun.

Set when the FDC is not serviced by the host system within a certain time interval during data transfer.

3 Reserved - - Unused. This bit is always “0”

2 ND R - No Data.

Set when the following conditions occurred:

1. The specified sector is not found during any read command.

2. The ID field cannot be read without errors during a READ ID command.

3. The proper sector sequence cannot be found during a READ TRACK command.

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1 NW R - No Writable

Set when WPT# is active during execution of write commands.

0 MA R - Missing Address Mark.

Set when the following conditions occurred:

1. Cannot detect an ID address mark at the specified track after encountering the index pulse form the INDEX# pin twice.

2. Cannot detect a data address mark or a deleted data address mark on the specified track.

Status Registers 2

Bit Name R/W Default Description

7 Reserved - - Unused. This bit is always “0”.

6 CM R - Control Mark.

Set when following conditions occurred:

1. Encounters a deleted data address mark during a READ DATA command.

2. Encounters a data address mark during a READ DELETED DATA command.

5 DD R - Data Error in Data Field.

The FDC detects a CRC error in the data field.

4 WC R - Wrong Cylinder.

Set when the track address from the sector ID field is different from the track address maintained inside the FDC.

3 SE R - Scan Equal.

Set if the equal condition is satisfied during execution of the SCAN command.

2 SN R - Scan Not Satisfied.

Set when the FDC cannot find a sector on the track which meets the desired condition during any scan command.

1 BC R - Bad Cylinder.

The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FFh which indicates a bad track.

0 MD R - Missing Data Address Mark.

Set when the FDC cannot detect a data address mark or a deleted data address mark.

F71862

Status Registers 3

Bit Name R/W Default Description

7 Reserved - - Unused. This bit is always “0”.

6 WP R - Write Protect.

Indicates the status of WPT# pin.

5 Reserved R - Unused. This bit is always “1”.

4 T0 R - Track 0.

Indicates the status of the TRK0# pin.

3 Reserved. R - Unused. This bit is always “1”.

2 HD R - Head Address.

Indicates the status of the HDSEL# pin.

1 DS1 R - Drive Select.

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F71862

0 DS0 R -

Digital Input Register (PC-AT Mode)  Base + 7

Bit Name R/W Default Description

7 DSKCHG R - This bit indicates the complement of DSKCHG# disk interface input.

6-0 Reserved R - Reserved.

Digital Input Register (PS/2 Mode)  Base + 7

Bit Name R/W Default Description

7 DSKCHG R - This bit indicates the complement of DSKCHG# disk interface input.

6-3 Reserved - - Reserved.

2-1 DRATE R 10 These bits indicate the status of the DRATE programmed through the Data

0 HIGHDEN_N R 1 0: 1Mbps or 500Kbps data rate is chosen.

Digital Input Register (Model 30 Mode)  Base + 7

These two bits indicate the DS1, DS0 bits in the command phase.

Rate Select Register or Configuration Control Register.

1: 300Kbps or 250Kbps data rate is chosen.

Bit Name R/W Default Description

7 DSKCHG_N R - This bit indicates the state of DSKCHG# disk interface input.

6-4 Reserved - - Reserved.

3 DMAEN R 0 This bit reflects the DMA bit in Digital Output Register.

2 NOPRE R 0 This bit reflects the NOPRE bit in Configuration Control Register.

1-0 DRATE R 10 These bits indicate the status of DRATE programmed through the Data Rate

Select Register or Configuration Control Register.

Configuration Control Register (PC-AT and PS/2 Mode)  Base + 7

Bit Name R/W Default Description

7-2 Reserved - - Reserved.

1-0 DRATE W 10 These bit determine the data rate of the floppy controller. See DRATE bits in

Data Rate Select Register.

Configuration Control Register (Model 30 Mode)  Base + 7

Bit Name R/W Default Description

7-3 Reserved - - Reserved.

2 NOPRE W 0 This bit could be programmed through Configuration Control Register and be

read through the bit 2 in Digital Input Register in Model 30 Mode. But it has no functionality.

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1-0 DRATE W 10 These bit determine the data rate of the floppy controller. See DRATE bits in

Data Rate Select Register.

FDC Commands

Terminology:

C Cylinder Number 0 -256 D Data Pattern DIR Step Direction 0: step out 1: step in DS0 Drive Select 0 DS1 Drive Select 1 DTL Data Length EC Enable Count EOT End of Track EFIFO Enable FIFO 0: FIFO is enabled. 1: FIFO is disabled. EIS Enable Implied Seek FIFOTHR FIFO Threshold GAP Alters Gap Length GPL Gap Length H/HDS Head Address HLT Head Load Time HUT Head Unload Time LOCK Lock EFIFO, FIFOTHR, PTRTRK bits. Prevent these bits from being affected by software reset. MFM MFM or FM mode 0: FM 1: MFM MT Multi-Track N Sector Size Code. All values up to 07h are allowable. 00: 128 bytes 01: 256 bytes

.. ..

07 16 Kbytes NCN New Cylinder Number ND Non-DMA Mode OW Overwritten PCN Present Cylinder Number POLL Polling disa ble 0: polling is enabled. 1: polling is disabled. PRETRK Precompensation Start Track Number R Sector address RCN Relative Cylinder Number SC Sector per Cylinder SK Skip deleted data address mark SRT Step Rate Time ST0 Status Register 0 ST1 Status Register 1 ST2 Status Register 2 ST3 Status Register 3 WGATE Write Gate alters timing of WE.

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F71862

Read Data

Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark

Command W MT MFM SK 0 0 1 1 0 Command code

W 0 0 0 0 0 HDS DS1 DS0

W ----------------------------- C ---------------------------

W ----------------------------- H ---------------------------

W ----------------------------- R ---------------------------

W ------------------------------ N ---------------------------

W ---------------------------- EOT --------------------------

W ---------------------------- GPL --------------------------

W ---------------------------- DTL --------------------------

Execution Data transfer

Result R ---------------------------- ST0 --------------------------

R ----------------------------- ST1 --------------------------

R ---------------------------- ST2 --------------------------

R ----------------------------- C ---------------------------

R ----------------------------- H ---------------------------

R ----------------------------- R ---------------------------

R ----------------------------- N ---------------------------

Sector ID information prior to command execution

between the FDD and system

Status information after command execution.

Sector ID information after command execution.

Read Deleted Data

Phase R/W D7 D6 D5 D4 D3 D2 D1 D0 Remark

Command W MT MFM SK 0 1 1 0 0 Command code