Gigabyte F71805 Schematics
F71805F/FG
F71805
Super H/W Monitor + LPC IO
Release Date: Dec., 2006
Revision: V0.25P
F71805 Dec., 2006
V0.25P
F71805 Datasheet Revision History
F71805
Version Date Page Revision History
0.20P 07/07/2004 - Preliminary Release Version.
0.21P 07/28/2004 Revised PWM frequency range.
0.22P 10/12/2004 10 Added FANCTL Functions.
22 Revised Voltage Fault Enable Register (Index 29h bit 7).
- Modified Application Circuit.
0.23P 04/15/2005 91 Added “Green Package” ordering information
0.24P 09/05/2006 16 Modified typo.
- Added PWM Output frequency setting description.
0.25P 12/28/2006 4 Added Patent Note.
Please note that all data and specifications are subject to change without notice. All the trade marks of products and
companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for use
in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such
improper use or sales.
F71805 Dec., 2006
V0.25P
F71805
Table of Contents
1. GENERAL DESCRIPTION.........................................................................................................................................................3
2. FEATURES....................................................................................................................................................................................3
3. KEY SPECIFICATIONS..............................................................................................................................................................5
4. PIN CONFIGURATI ON...............................................................................................................................................................5
5. PIN DESCRIPTION......................................................................................................................................................................6
5.1 POWER PIN.........................................................................................................................................................................6
5.2 LPC INTERFACE.................................................................................................................................................................6
5.3 FDC...................................................................................................................................................................................7
5.4 UART PORT AND SIR.........................................................................................................................................................7
5.5 IEEE 1284 PARALLEL PORT ...............................................................................................................................................9
5.6 H/W MONITOR...................................................................................................................................................................9
5.7 FLASH ROM INTERF ACE AND GPIO.................................................................................................................................10
6. FUNCTION DESCRIPTION .....................................................................................................................................................11
6.1 POWER ON STRAPPING OPTIONS.......................................................................................................................................11
6.2 HARDWARE MONITOR......................................................................................................................................................11
6.3 FDC.................................................................................................................................................................................18
6.4 UART..............................................................................................................................................................................19
6.5 PARALLEL PORT ...............................................................................................................................................................19
7. REGISTER DESCRIPTION......................................................................................................................................................19
7.1 GLOBAL CONTROL REGISTERS.........................................................................................................................................19
7.1.1 Software Reset Register Index 02h............................................................................................................................20
7.1.2 Logic Device Number Register Index 07h................................................................................................................. 20
7.1.3 Chip ID Register Index 20h....................................................................................................................................... 20
7.1.4 Chip ID Register Index 21h....................................................................................................................................... 20
7.1.5 Vendor ID Register Index 23h ...................................................................................................................................20
7.1.6 Vendor ID Register Index 24h ...................................................................................................................................20
7.1.7 Software Power Down Register Index 25h................................................................................................................ 20
7.1.8 UART IRQ Sharing Register Index 26h ....................................................................................................................21
7.1.9 Power On Trap Status Register Index 27h.................................................................................................................21
7.1.10 Flash Control Register Index 28h ..............................................................................................................................21
7.1.11 Voltage Fault Enable Register Index 29h...................................................................................................................22
1
Dec., 2006
V0.25P
F71805
7.2 FDC REGISTER.................................................................................................................................................................22
7.2.1 Logic Device Number Register........................................................................................................................................22
7.2.2 FDC Configuration Registers........................................................................................................................................... 23
7.2.3 Device Registers..............................................................................................................................................................25
7.3 UART 1 REGISTER ...........................................................................................................................................................40
7.3.1 Logic Device Number Register........................................................................................................................................40
7.3.2 UART 1 Configuration Register.......................................................................................................................................41
7.3.3 Device Registers..............................................................................................................................................................42
7.4 UART 2 REGISTER ...........................................................................................................................................................45
7.4.1 Logic Device Number Register........................................................................................................................................45
7.4.2 UART 2 Configuration Registers..................................................................................................................................... 45
7.4.3 Device Registers..............................................................................................................................................................47
7.5 PARALLEL PORT REGISTER ...............................................................................................................................................50
7.5.1 Logic Device Number Register........................................................................................................................................50
7.5.2 Parallel Port Configuration Registers...............................................................................................................................50
7.5.3 Device Registers..............................................................................................................................................................51
7.6 HARDWARE MONITOR REGISTER ..................................................................................................................................... 55
7.6.1 Logic Device Number Registers...................................................................................................................................... 55
7.6.2 Hardware Monitor Configuration Registers..................................................................................................................... 55
7.6.3 Device Registers..............................................................................................................................................................56
7.7 GPIO REGISTER...............................................................................................................................................................76
7.7.1 Logic Device Number Register........................................................................................................................................76
7.7.2 GPIO Configuration Registers......................................................................................................................................... 76
7.8 PME REGISTER ................................................................................................................................................................83
7.8.1 Logic Device Number Register........................................................................................................................................83
7.8.2 PME Configuration Registers..........................................................................................................................................83
8. PCB LAYOUT GUIDE................................................................................................................................................................85
9. ELECTRICAL CHARACTERISTIC........................................................................................................................................86
9.1 ABSOLUTE MAXIMUM RATIN GS .......................................................................................................................................86
9.2 DC CHARACTERISTICS.....................................................................................................................................................86
9.3 AC CHARACTERISTICS.....................................................................................................................................................87
10. ORDERING INFORMATION................................................................................................................................................87
11. PACKAGE DIMENSIO NS......................................................................................................................................................88
12. F71805 DEMO CIRCUIT........................................................................................................................................................89
2
Dec., 2006
V0.25P
1. General Description
The F71805 is the featured IO chip specifically for PC system. Equipped with one IEEE 1284
parallel port, two UART port and FDC, F71805 provides SIR and Flash ROM Interface. Integrated with
hardware monitor, F71805 supports 9 sets of voltage sensor and 4 voltage fault signal outputs, 3 sets of
creative auto-controlling fans and 3 temperature sensor pins for the accurate current type temp.
measurement for CPU thermal diode or external transistors 2N3906.
The F71805 provides flexible features for multi-directional application. For instance, supports 24
GPIO pins which include pulse/level mode selection, IRQ sharing function also designed in UART
feature for particular usage and accurate current mode H/W monitor will be worth in measurement of
F71805
temperature. The F71805 is powered by 3.3V voltage, with the LPC interface in the package of 128-QFP.
2. Features
General Functions
¾ Comply with LPC Spec. 1.0
¾ Supports 24 GPIO pins. One set of GPIO supports High/Low Level/Pulse selection.
¾ 48 MHz clock input
FDC
¾ Compatible with IBM PC AT disk drive systems
¾ Variable write pre-compensation with track selectable capability
¾ Support vertical recording format
¾ DMA enable logic
¾ 16-byte data FIFOs
¾ Support floppy disk drives and tape drives
¾ Detects all overrun and under run conditions
¾ Built-in address mark detection circuit to simplify the read electronics
¾ Completely compatible with industry standard 82077
¾ 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
¾ Support 3-mode FDD, and its Win95/98/2K/XP driver
UART
¾ Two high-speed 16C550 compatible UART with 16-byte FIFOs
¾ Fully programmable serial-interface characteristics
3
Dec., 2006
V0.25P
Infrared
Flash ROM Interface
Parallel Port
F71805
¾ Baud rate up to 115.2K
¾ Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
¾ Up to 4M bits flash ROM supported
¾ One PS/2 compatible bi-directional parallel port
¾ Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification
¾ Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification
¾ Enhanced printer port back-drive current protection
Hardware Monitor Functions
¾ 3 current type accurate (±3) ℃ thermal inputs for CPU thermal diode and 2N3906 transistors
¾ 9 voltage monitoring inputs (8 external and Vcc power)
¾ 4 voltage_fault# hardware signal outputs
¾ 3 fan speed monitoring inputs
¾ 3 fan speed auto-control --- support 3 wire and 4 wire fans
¾ WATCHDOG comparison of all monitored values
¾ Issue PME#, OVT# and independent Voltage_fault #
Package
¾ 128-pin PQFP
Noted: Patented TW207103 TW207104 US6788131 B1 TW235231 TW237183 TWI263778
4
Dec., 2006
V0.25P
3. Key Specifications
Supply Voltage 3.0V to 3.6V
Operating Supply Current 5 mA typ.
4. Pin Configuration
F71805
F71805
Figure 1
5
Dec., 2006
V0.25P
5. Pin Description
I/O
- TTL level bi-directional pin with 12 mA source-sink cap ability.
12t
I/OOD
I/OOD
- TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA source-sink
12t
capability.
- TTL level bi-directional pin, can select to OD or OUT by register, with 16 mA source-sink
16t
capability.
F71805
I/OD
I/O8t
I/O
8t-u47,5V
I/O
12ts5V
O
12
O8
12ts5V
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink capability,
5V tolerance.
- TTL level bi-directional pin with 8 mA sink capability.
- TTL level bi-directional pin with 8 mA sink capability, pull-up 47k ohms, 5V tolerance.
- TTL level bi-directional pin and schmitt trigger with 12 mA sink capability, 5V tolerance.
- Output pin with 12 mA source-sink capability.
- Output pin with 8 A source-sink capability.
AOUT - Output pin(Analog).
OD
OD
IN
ts
IN
t5V
IN
ts5V
AIN
12
24
- Open-drain output pin with 12 mA sink capability.
- Open-drain output pin with 24 mA sink capability.
- TTL level input pin and schmitt trigger.
- TTL level input, 5V tolerance.
- TTL level input pin and schmitt trigger, 5V tolerance.
- Input pin(Analog).
P - Power.
5.1 Power Pin
Pin No. Pin Name Type Description
4,35,99 VCC P Power supply voltage input with 3.3V
86 AGND(D-) P Analog GND
15,43,67,117 GNDD P Digital GND
5.2 LPC Interface
Pin No. Pin Name Type PWR Description
45 LRESET# INts VCC Reset signal. It can connect to PCIRST# signal on the host.
36 LDRQ# O12 VCC Encoded DMA Request signal.
37 SERIRQ I/O
46 LFRAM# INts VCC Indicates start of a new cycle or termination of a broken
VCC Serial IRQ input/Output.
12t
6
Dec., 2006
V0.25P
41-38 LAD[3:0] I/O
42 PCICLK INts VCC PCI clock input.
44 CLKIN INts VCC System clock input. According to the input frequency 48MHz.
5.3 FDC
Pin No. Pin Name Type PWR Description
57
58
60 DRVA# OD24 VCC Drive Select A. When set to 0, this pin enables disk drive A.
62 WDATA# OD24 VCC Write data. This logic low open drain writes
63 DIR# OD24 VCC Direction of the head step motor. An open drain output.
64 STEP# OD24 VCC Step output pulses. This active low open drain output
65 HDSEL# OD24 VCC Head select. This open drain output determines which disk
66 WGATE# OD24 VCC Write enable. An open drain output.
68 RDATA# IN
69 TRK0# IN
70 INDEX# IN
71 WPT# IN
72 DSKCHG# IN
DENSEL#
MTRA#
OD24 VCC Motor A On. When set to 0, this pin enables disk drive 0.
F71805
cycle.
VCC These signal lines communicate address, control, and data
12t
information over the LPC bus between a host and a
peripheral.
OD24 VCC Drive Density Select.
Set to 1 - High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
This is an open drain output.
This is an open drain output.
pre-compensation serial data to the selected FDD. An open
drain output.
Logic 1 = outward motion
Logic 0 = inward motion
produces a pulse to move the head to another track.
drive head is active.
Logic 1 = side 0
Logic 0 = side 1
VCC The read data input signal from the FDD.
ts5V
VCC Track 0. This Schmitt-triggered input from the disk drive is
ts5V
active low when the head is positioned over the outermost
track.
VCC This Schmitt-triggered input from the disk drive is active low
ts5V
when the head is positioned over the beginning of a track
marked by an index hole.
VCC Write protected. This active low Schmitt input from the disk
ts5V
drive indicates that the diskette is write-protected.
VCC Diskette change. This signal is active low at power on and
ts5V
whenever the diskette is removed.
5.4 UART Port and SIR
Pin No. Pin Name Type PWR Description
82 IRTX O12 VCC Infrared Transmitter Output.
83 IRRX INts VCC Infrared Receiver input.
118 DCD1# IN
119 RI1# IN
VCC Data Carrier Detect. An active low signal indicates the
t5V
modem or data set has detected a data carrier.
VCC Ring Indicator. An active low signal indicates that a ring
t5V
signal is being received from the modem or data set.
7
Dec., 2006
V0.25P
F71805
120 CTS1# IN
121 DTR1#/JP1 I/O
122 RTS1#/JP2 I/O
123 DSR1# IN
124 SOUT1/JP3
I/O
125 SIN1 IN
126 DCD2# IN
127 RI2# IN
128 CTS2# IN
1 DTR2#/JP4 I/O
2 RTS2#/JP6 I/O
3 DSR2# IN
5 SOUT2/JP5
I/O
6 SIN2 IN
VCC Clear To Send is the modem control input.
t5V
8t-u47,5V
VCC
UART 1 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to
communicate. (Internal 47k pulled high and disable after
power on strapping)
Power on strapping: Default is high. Flash Rom Interface
Address Segment 1 Enable (FFFC0000h-FFFFFFFFh,
000E0000h-000FFFFFh).
(000E0000h-000EFFFFh Can be disabled by register change.)
8t-u47,5V
VCC
UART 1 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send
data.(Internal 47k pulled high and disable after power on
strapping)
Power on strapping: Default is high. Flash Rom Interface
Address Segment 2 Enable (FFEE0000h-FFEFFFFFh).
VCC Data Set Ready. An active low signal indicates the modem
t5V
or data set is ready to establish a communication link and
transfer data to the UART.
8t-u47,5V
VCC
UART 1 Serial Output. Used to transmit serial data out to
the communication link.( Internal 47k pulled high and disable
after power on strapping )
Power on strapping: Default is high. Flash Rom Interface
Address Segment 3 Enable (FFF80000h-FFFBFFFFh).
VCC Serial Input. Used to receive serial data through the
t5V
communication link.
VCC Data Carrier Detect. An active low signal indicates the
t5V
modem or data set has detected a data carrier.
VCC Ring Indicator. An active low signal indicates that a ring
t5V
signal is being received from the modem or data set.
VCC Clear To Send is the modem control input.
t5V
8t-u47,5V
VCC
UART 2 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to
communicate.( Internal 47k pulled high and disable after
power on strapping )
Power on strapping : 1 PWM Mode (Default)
0 Linear Mode
8t-u47,5V
VCC
UART 2 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send
data.(Internal 47k pulled high and disable after power on
strapping )
Power on strapping : 1 XBUS Interface (Default)
0 Reserved.
VCC Data Set Ready. An active low signal indicates the modem
t5V
or data set is ready to establish a communication link and
transfer data to the UART.
8t-u47,5V
VCC
UART 2 Serial Output. Used to transmit serial data out to
the communication link.(Internal 47k pulled high and disable
after power on strapping )
Power on strapping : 1 Configuration register:4E (Default)
0 C
onfiguration register:2E
VCC Serial Input. Used to receive serial data through the
t5V
communication link.
8
Dec., 2006
V0.25P
5.5 IEEE 1284 Parallel Port
Pin No. Pin Name Type PWR Description
100 SLCT IN
101 PE IN
102 BUSY IN
103 ACK# IN
104 SLIN# I/OD
105 INIT#
106 ERR#
107 AFD# I/OD
108 STB# I/OD
109
110
111
112
113
114
115
116
I/O
PD0
I/O
PD1
I/O
PD2
I/O
PD3
I/O
PD4
I/O
PD5
I/O
PD6
I/O
PD7
F71805
VCC An active high input on this pin indicates that the printer is
ts5V
selected. Refer to the description of the parallel port for
definition of this pin in ECP and EPP mode.
VCC An active high input on this pin indicates that the printer has
ts5V
detected the end of the paper. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP
mode.
VCC An active high input indicates that the printer is not ready to
ts5V
receive data. Refer to the description of the parallel port for
definition of this pin in ECP and EPP mode.
VCC An active low input on this pin indicates that the printer has
ts5V
received data and is ready to accept more data. Refer to the
description of the parallel port for the definition of this pin in
ECP and EPP mode.
VCC Output line for detection of printer selection. Refer to the
12ts5V
description of the parallel port for the definition of this pin in
ECP and EPP mode.
I/OD
IN
ts5V
12ts5V
12ts5V
12ts5V
12ts5V
12ts5V
12ts5V
12ts5V
12ts5V
VCC Output line for the printer initialization. Refer to the
12ts5V
description of the parallel port for the definition of this pin in
ECP and EPP mode.
VCC An active low input on this pin indicates that the printer has
encountered an error condition. Refer to the description of
the parallel port for the definition of this pin in ECP and EPP
mode.
VCC An active low output from this pin causes the printer to auto
12ts5V
feed a line after a line is printed. Refer to the description of
the parallel port for the definition of this pin in ECP and EPP
mode.
VCC An active low output is used to latch the parallel data into the
12ts5V
printer. Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
VCC Parallel port data bus bit 0. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP
mode.
VCC Parallel port data bus bit 1.
VCC Parallel port data bus bit 2.
VCC Parallel port data bus bit 3.
VCC Parallel port data bus bit 4.
VCC Parallel port data bus bit 5.
VCC Parallel port data bus bit 6.
VCC Parallel port data bus bit 7.
5.6 H/W Monitor
Pin No. Pin Name Type PWR Description
91-98 VIN8~VIN1 AIN VCC Voltage input 8 ~ 1.
73-75 FAN_TAC1~
FAN_TAC3
IN
ts
VCC Fan tachometer inputs.
9
Dec., 2006
V0.25P
F71805
78-80 FAN_CTL1~
FAN_CTL3
87-89 D3~ D1 AIN VCC CPU thermal diode/transistor temperature sensor input.
90 VREF AOUT
81 PME# OD12 VCC Generated PME event.
85 OVT# OD12 VCC Generated over temperature event.
49-52 GP00~ GP03/
Voltage_fault1~4
O12 VCC Fan control outputs. These pins provide PWM duty-cycle
output or a voltage output.
VCC Voltage sensor output.
I/OOD
VCC
12t
General purpose IO.
1. Support Level and Pulse mode output.
2. Open drain and drive select.
3. Without input de-bounce.
Voltage fault indication for VIN abnormal event.
VIN1 Æ Voltage_fault1
VIN2 Æ Voltage_fault2
VIN3 Æ Voltage_fault3
VIN4 Æ Voltage_fault4
53-55 GP04~ GP06/
VIN7_ID0~2
I/OOD
VCC
12t
General purpose IO.
1. Support Level and Pulse mode output.
2. Open drain and drive select
3. Without input de-bounce.
Voltage fault indication is for VIN7 abnormal event ID.
5.7 Flash ROM Interface and GPIO
Pin No. Pin Name Type PWR Description
7-14 FD0~ FD7 I/O8t VCC Flash ROM interface data [0:7].
16-23 FA0~ FA7/
GP10~ GP17
24-25 FA8~ FA9 O8 VCC Flash ROM interface address [8:9].
26-33 FA10~ FA17/
GP20~ GP27
34 FRD# O8 VCC Flash ROM interface Read Strobe#.
47 FCS# O8 VCC Flash ROM interface Chip Select#.
48 FWE# O8 VCC Flash ROM interface Write Enable#.
59 FA18 O8 VCC Flash ROM interface address18.
56 GP07/FANCTL I/OOD
O8
I/O
O8
I/O
8t
8t
VCC The first functions of these pins are the Flash ROM interface
address [0:7].
The second Functions of these pins are GPIO [10:17].
VCC The first functions of these pins are the Flash ROM interface
address [10:17].
The second Functions of these pins are GPIO [20:27].
VCC
12t
General purpose IO.
1. Support Level and Pulse mode output.
2. Open drain and drive select
3. Without input de-bounce.
Fan 1 control output for Intel 4-pin Fan. All the registers are
as same as FANCTL1.
10
Dec., 2006
V0.25P
6. Function Description
6.1 Power on Strapping Options
The F71805 provides four pins for power on hardware strapping to select functions. There is a form
to describe how to set the functions you want.
Pin No. Symbol Value Description
121 JP1
122 JP2
124 JP3
F71805
1 Fan control mode: PWM mode. ( Default) 1 JP4
0 Fan control mode: Linear mode.
1 ISA ROM Interface enable ( Default) 2 JP6
0 Reserved
1 Chip selection in configuration 4E. (Default) 5 JP5
0 Chip selection in configuration 2E.
1 Flash Rom Interface Address Segment 1 Enable (Default)
(FFFC0000h-FFFFFFFFh, 000E0000h-000FFFFFh).
0 Disable.
1 Flash Rom Interface Address Segment 2 Enable (Default)
(FFEE0000h-FFEFFFFFh).
0 Disable.
1 Flash Rom Interface Address Segment 3 Enable (Default)
(FFF80000h-FFFBFFFFh).
0 Disable.
6.2 Hardware Monitor
6.2.1 Analog Input
The F71805 provides 8 pins (8-bit) ADC voltage inputs. These input voltages should be positive and is
limited at range of 0v to 2.048V. The minimum resolution (1-LSB) is 8mV. If the voltage is over this range,
the divider resistor must be added and the divided voltage is also in the range of 0V to 2.048V.
The maximum input voltage of the analog pin is 2.048V because the 8-bit ADC has a 8mv LSB. Really,
the application of the PC monitoring would most often be connected to power suppliers. The voltage range
of 0V to 2.048V can be connected to these analog inputs. The 3.3V and VSB5V should be reduced a factor
with external resistors so as to obtain the input range..
There are 8 voltage inputs in the F71805 and the voltage divided formula is shown as follows:
R
2
If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which is within the
×=
VVIN
V
+
12
RR
+
21
For instance, where V
is the analog input voltage.
+12V
11
Dec., 2006
V0.25P
tolerance. As for application circuit, it can be refer to the figure shown as follows.
VIN(Lower than 2.048V)
R1
R2
F71805
F71805
VREF
R
10K, 1%
Typical Thermister
Connection
10K, 25 C
D1/D2/D3
D1/D2/D3
AGND(D-)
C
2200pF
2N3906
6.2.2 Temperature Monitoring and Offset
The F71805 can be measured from 0°C to 140°C. The status depends on different situation. As
connected to a BJT thermal diode, detected temperature ranges from 0°C to 140°C without considering
the OFFSET effect. As connected to a thermistor, detected temperature ranges from 0°C to 127°C without
considering the OFFSET effect. The temperature format is as the following table:
Temperature ( High Byte ) Digital Output
0°C 0000 0000
1°C 0000 0001
25°C 0001 1001
50°C 0011 0010
75°C 0100 1011
90°C 0101 1010
100°C 0110 0100
140°C 1000 1100
The F71805 provides offset register for each temperature. The offset value is an 7-bit, 2’s
complement value. The reading temperature value will be the result of the offset value added to the
monitored value. The offset format is as the following table:
12
Dec., 2006
V0.25P
The F71805 can provide two external thermal sensors to detect temperature. When monitored
temperature exceeds the over-temperature threshold value, OVT# (pin85) will be asserted until the
temperature goes below the hysteresis temperature.
F71805
Offset Value High Byte
63°C 0011 1111
2°C 0000 0010
1°C 0000 0001
0°C 0000 0000
-1°C 0100 0001
-2°C 0100 0010
-64°C 0100 0000
To
T
HYST
OVT#
6.2.3 Fan speed count
Inputs are provided by the signals from fans equipped with tachometer outputs. The level of these
signals should be set to TTL level, and maximum input voltage cannot be over VCC. If the input signals
from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce
the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as follows:
+12V
FAN Out
GND
+12V
Pull-up resister
4.7K Ohms
22K~30K
Fan Input
10K
FANIN 1
F71805
FAN
Connector
+12V
FAN Out
GND
+12V
Pull-up resister < 1K
or totem-pole output
> 1K
3.3V Zener
Fan Input
FANIN 1
F71805
Fan with Tach Pull-Up to +12V, or Totern-Pole
Output and Register Attenuator
13
Fan with Tach Pull-Up to +12V, or
Totem-Pole Putput and Zener Clamp
Dec., 2006
V0.25P
FAN Out
+5V
GND
+5V
Pull-up resister
4.7K Ohms
1K~2.7K
Fan Input
10K
FANIN1
F71805
FAN Out
FAN
Connector
+5V
GND
+5V
Pull-up resister < 1K
or totem-pole output
> 1K
3.3V Zener
F71805
Fan Input
FANIN1
F71805
Fan with Tach Pull-Up to +5V, or Totern-Pole
Output and Register Attenuator
Fan with Tach Pull-Up to +5V, or
Totem-Pole Putput and Zener Clamp
Determine the fan counter according to:
6
105.1 ×
RPM
Count
=
In other words, the fan speed counter has been read from register, the fan speed can be evaluated by the
following equation. As for fan, it would be best to use 2 pulses tachmeter output per round.
6
RPM
=
105.1 ×
Count
6.2.4 Fan speed control
The F71805 provides 2 fan speed control methods: 1. Linear FAN Control 2. PWM Duty Cycle
Linear Fan Control
The range of DC output is 0~3.3V, controlled by 8-bit register (CR6Bh for FAN1, CR7Bh for FAN2
and CR8Bh for FAN3). 1 LSB is about 0.013V. The output DC voltage is amplified by external OP circuit,
thus to reach maximum FAN OPERATION VOLTAGE, 12V.
The output voltage will be given as followed:
And the suggested application circuit for linear fac control would be:
3.3(V) tageOutput_vol ×=
ValueRegister bit -8 Programmed
255
14
Dec., 2006
V0.25P
DC OUTPUT VOLTAGE
3.9K
F71805
12V
84
3
+
2
-
LM358
R
PMOS
1
JP1
R10K
DC FAN Control with OP
C
47u
CON3
1N4148
3
2
1
D1
C
0.1u
R
4.7K
R27K
R
10K
FANIN MONITOR
PWM duty Fan Control
The duty cycle of PWM can be programmed by a 8-bit register which are defined in the CR6Bh,
CR7Bh and CR8Bh. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh.
The expression of duty can be represented as follows.
(%)Duty_cycle ×=
ValueRegister bit -8 Programmed
%100
255
R1
D
NMOS
S
+5V
R2
PNP Transistor
+
C
-
FAN
PWM Clock Input
+12V
R1
R2
D
G
NMOS
S
PNP Transistor
+
C
-
FAN
PWM Clock Input
G
6.2.5 Fan speed control mechanism
There are 3 modes to control fan speed and they are manual, fan speed mode and temperature
mode. For manual mode, it generally acts as PWM fan speed control. As for speed mode and
temperature mode, they are more intelligent fan speed control and described as below:
Fan Speed mode
Fan speed mode is an intelligent method according to expected fan speed pre-setting by BIOS. In the
beginning, fan speed will be operated at full speed and the F71805 will get the full speed count value.
After that, the fan speed will automatically rotate according to the expected fan speed setting by BIOS.
15
Dec., 2006
V0.25P
r
For instance, the register CR69h and CR6Ah are used for this mode of FAN1.
Temperature mode
At this mode, F71805 provides the clever system to automatically control fan speed related to
temperature system. The F71805 can provide three temperature boundaries and three intervals for user
setting, and each interval has its related fan speed count. All these values should be set by BIOS first. In
the F71805 design, the F71805 will auto-generate temperature boundaries (average value) between
those boundaries that user setting, and it will auto-produce interval fan speed count (average value)
between users setting value.
If the temperature value is set to 40, 50 and 90°C, it will auto-generate two temperature boundaries
F71805
value of 45°C (This value is calculated automatically by hardware design of the F71805. (50+40)/2 =45 )
and 70°C. The same way, the related desired fan speed counts for each interval are 4200RPM, 3600RPM,
3000RPM, 2500RPM, 2000RPM and Stop Counts. When the temperature is within 50~70°C, the fan
speed counts will be 3000RPM (Registers CRA4h~CRA9h, CRB4h~CRB9h and CRC4h~CRC9h). The
F71805 will auto-adjust PWMOUT (PWM_DUTY) to make fan speed match the expected value. It can be
said that the fan will be turned on with a specific speed set by BIOS and automatically controlled with the
temperature varying. The F71805 will take charge of all the fan speed control and need no software
support.
Auto-Generated
(Average value)
90 Degree C
70 Degree C
50 Degree C
45 Degree C
40 Degree C
Desired Counts (RPM)
4200
3600
3000
2500
2000
Stop Counts
Auto-Gene
(Average value)
ated
PWMOUT Duty-cycle operating process
In both “FAN SPEED” and “TEMPERATURE” modes, F71805 adjust PWMOUT (PWM_DUTY1
(CR6B) of Fan1, PWM_DUTY2 (CR7B) of Fan2, PWM_DUTY3 (CR8B) of Fan3) duty-cycle according to
current fan count and expected fan count. It will operate as follows:
(1). When expected count is FFFFh, PWMOUT duty-cycle (PWM_DUTY)will be set to 00h to turn off
fan.
(2). When expected count is 0000h, PWMOUT duty-cycle (PWM_DUTY) will be set to FFh to turn on
fan with full speed.
16
Dec., 2006
V0.25P
(3). If both (1) and (2) are not true and KEEP_STOP (see INDEX 60h) is set to 0:
F71805
(a). When PWMOUT duty-cycle decrease to STOP_DUTY(≠ 00h), obviously the duty-cycle will
decrease to 00h next, F71805 will keep duty-cycle at 00h 3 seconds
starts to compare current fan count and expected count in order to increase or decrease its
duty-cycle. This ensures that if there is any glitch during the 3 seconds
ignore it.
(b). When PWMOUT duty-cycle increase from 00h to START_DUTY(≠ 00h), F71805 also will
keep duty-cycle at START_DUTY 3 seconds
1
. After that, F71805 starts to compare current
fan count and expected count in order to increase or decrease its duty-cycle. This ensures
that if there is any glitch during the 3 seconds
1
period, F71805 will ignore it.
1
. After that, F71805
1
period, F71805 will
Note 1: The period of HOLD_DUTY_TIME can be programmed at INDEX 67h of FAN1.
START
STOP
START
STOP
6.2.6 FAN_FAULT#
Fan_Fault will be asserted ( PME# Pin 81) when the fan speed doesn’t meet the expected fan speed
within a programmable period (default is 3 seconds) or when PWMOUT duty-cycle is 100%.
17
Dec., 2006
V0.25P
)
F71805
Current Fan Count
Expected Fan Count
100%
Duty-cycle
Fan_Fault#
3 sec(default
6.2.7 VOLT_FAULT# (Voltage Fault Signal)
When voltage leaps from the security range setting by BIOS, the warning signal VOLT_FAULT# will
be activated. Shown in figure.
High limit
Low limit
VOLT_FAULT#
6.3 FDC
The Floppy Disk Controller provides the interface between a host processor and one floppy disk
drives. It integrates a controller and a digital data separator with write pre-compensation, data rate
selection logic, microprocessor interface, and a set of registers. The FDC supports data transfer rates of
250 Kbps, 300 Kbps, 500 Kbps, and 1 Mbps. It operates in PC/AT mode and supports 3-mode type drives.
The FDC configuration is handled by software and a set of Configuration registers. Status, Data, and
Control registers facilitate the interface between the host microprocessor and the disk drive, providing
information about the condition and/or state of the FDC. These configuration registers can select the data
rate, enable interrupts, drives, and DMA modes, and indicate errors in the data or operation of the
FDC/FDD. The controller manages data transfers using a set of data transfer and control commands.
These commands are handled in three phases: Command, Execution, and Result. Not all commands
utilize all these three phases.
18
Dec., 2006
V0.25P
6.4 UART
The UARTs are used to convert data between parallel format and serial format. They convert parallel
data into serial format on transmission and serial format into parallel data on receiver side. The serial
format is formed by one start bit, followed by five to eight data bits, a parity bit if programmed and one
( 1.5 or 2 ) stop bits. The UARTs include complete modem control capability and an interrupt system that
may be software trailed to the computing time required to handle the communication link. They have FIFO
mode to reduce the number of interrupts presented to the host. Both receiver and transmitter have a
16-byte FIFO.
F71805
6.5 Parallel Port
The parallel port in F71805 supports an IBM XT/AT compatible parallel port ( SPP ), bi-directional
paralle port ( BPP ), Enhanced Parallel Port ( EPP ), Extended Capabilities Parallel Port ( ECP ) mode.
Refer to the configuration registers for more information on selecting the mode of operation.
7. Register Description
7.1 Global Control Registers
The configuration register is used to control the behavior of the corresponding devices. To configure
the register, using the index port to select the index and then writing data port to alter the parameters. The
default index port and data port are 0x4E and 0x4F respectively. Pull down the SOUT2/JP5 pin to change
the default value to 0x2E/0x2F. To enable configuration, the entry key 0x87 must be written to the index
port. To disable configuration, write exit key 0xAA to the index port. Following is a example to enable
configuration and disable configuration by using debug.
-o 4e 87
-o 4e 87 ( enable configuration )
-o 4e aa ( disable configuration )
19
Dec., 2006
V0.25P
7.1.1 Software Reset Register Index 02h
Bit Name R/W Default Description
7-1 Reserved - - Reserved.
0 SOFT_RST R/W 0 Write 1 to reset the register and device powered by VDD ( VCC ).
7.1.2 Logic Device Number Register Index 07h
Bit Name R/W Default Description
7-0 LDN R/W 00h 00h: Select FDC device configuration registers.
F71805
01h: Select UART 1 device configuration registers.
02h: Select UART 2 device configuration registers.
03h: Select Parallel Port device configuration registers.
04h: Select Hardware Monitor device configuration registers.
06h: Select GPIO device configuration registers.
0ah: Select PME device configuration registers.
Otherwise: reserved.
7.1.3 Chip ID Register Index 20h
Bit Name R/W Default Description
7-0 CHIP_ID1 R 04h Chip ID 1 of F71805.
7.1.4 Chip ID Register Index 21h
Bit Name R/W Default Description
7-0 CHIP_ID2 R 06h Chip ID2 of F71805.
7.1.5 Vendor ID Register Index 23h
Bit Name R/W Default Description
7-0 VENDOR_ID1 R 19h Vendor ID 1 of Fintek devices.
7.1.6 Vendor ID Register Index 24h
Bit Name R/W Default Description
7-0 VENDOR_ID2 R 34h Vendor ID 2 of Fintek devices.
7.1.7 Software Power Down Register Index 25h
Bit Name R/W Default Description
20
Dec., 2006
V0.25P
7-6 Reserved - - Reserved
4 SOFTPD_HM R/W 0
3 SOFTPD_PRT R/W 0
2 SOFTPD_UR2 R/W 0
1 SOFTPD_UR1 R/W 0
0 SOFTPD_FDC R/W 0
7.1.8 UART IRQ Sharing Register Index 26h
Bit Name R/W Default Description
F71805
Power down the Hardware Monitor device. This will stop the Hardware Monitor
clock.
Power down the Parallel Port device. This will stop the Parallel Port clock.
Power down the UART 2 device. This will stop the UART 2 clock.
Power down the UART 1 device. This will stop the UART 1 clock.
Power down the FDC device. This will stop the FDC clock.
7-2 Reserved - -
1 IRQ_MODE R/W 0
0 IRQ_SHAR R/W 0
Reserved.
0: PCI IRQ sharing mode (low level).
1: ISA IRQ sharing mode (low pulse).
0: disable IRQ sharing of two UART devices.
1: enable IRQ sharing of two UART devices.
7.1.9 Power On Trap Status Register Index 27h
Bit Name R/W Default Description
7-6 Reserved - -
5 PORT4E_EN R/W 1
4 XBUS_EN R/W 1
3 SEG_000E_EN R/W 1
2 SEG_FFFF_EN R/W 1
1 SEG_FFEF_EN R/W 1
0 SEG_FFF8_EN R/W 1
Reserved.
0: Configuration Register port is 2E/2F.
1: Configuration Register port is 4E/4F.
0: disable XBUS. FA17/GP27 ~ FA10/GP20 function as GP2. FA7/GP17 ~
FA0/GP10 function as GP1.
1: enable XBUS.
0: disable segment 000E0000h-000EFFFFh.
1: enable segment 000E000h-000EFFFFh.
0: disable segment FFFFFFFFh-FFFC0000h.
1: enable segment FFFFFFFFh-FFFC0000h.
0: disable segment FFEFFFFFh-FFEE0000h.
1: enable segment FFEFFFFFh-FFEE0000h.
0: disable segment FFFBFFFFh-FFF80000h.
1: enable segment FFFBFFFFh-FFF80000h.
7.1.10 Flash Control Register Index 28h
Bit Name R/W Default Description
7 FLASH_WR_EN R/W 0
6-5 Reserved - -
0: disable flash write.
1: enable flash write.
Reserved.
21
Dec., 2006
V0.25P
F71805
4-0 WAIT_TIMES R/W 8h
Adjust the cycles of the FCS# to improve the performance of the XBUS.
The length of FCS# is from 7 LCLK cycles ( WAIT_TIMES == 00h) to 38 LCLK
cycles (WAIT_TIMES == 1fh).
7.1.11 Voltage Fault Enable Register Index 29h
Bit Name R/W Default Description
7
FANCTL_GPEN R/W 0
6 VIN7_ID2_EN R/W 0
5 VIN7_ID1_EN R/W 0
4 VIN7_ID0_EN R/W 0
3 VOLT_FAULT4_EN R/W 0
2 VOLT_FAULT3_EN R/W 0
1 VOLT_FAULT2_EN R/W 0
0 VOLT_FAULT1_EN R/W 0
0: the function of GP07 is GP07.
1: the function of GP07 is FANCTL.
0: the function of GP06/VIN7_ID2 is GP06.
1: the function of GP06/VIN7_ID2 is VIN7_ID2.
0: the function of GP05/VIN7_ID1 is GP05.
1: the function of GP05/VIN7_ID1 is VIN7_ID1.
0: the function of GP04/VIN7_ID0 is GP04.
1: the function of GP04/VIN7_ID0 is VIN7_ID0.
0: the function of GP03/Voltage_fault4 is GP03.
1: the function of GP03/Voltage_fault4 is Voltage_fault4.
0: the function of GP02/Voltage_fault3 is GP02.
1: the function of GP02/Voltage_fault3 is Voltage_fault3.
0: the function of GP01/Voltage_fault2 is GP01.
1: the function of GP01/Voltage_fault2 is Voltage_fault2.
0: the function of GP00/Voltage_fault1 is GP00.
1: the function of GP00/Voltage_fault1 is Voltage_fault1.
7.2 FDC Register
7.2.1 Logic Device Number Register
Logic Device Number Register
Bit Name R/W Default Description
7-0 LDN R/W 00h 00h: Select FDC device configuration registers.
Index 07h
01h: Select UART 1 device configuration registers.
02h: Select UART 2 device configuration registers.
03h: Select Parallel Port device configuration registers.
04h: Select Hardware Monitor device configuration registers.
06h: Select GPIO device configuration registers.
0ah: Select PME device configuration registers.
Otherwise: reserved.
22
Dec., 2006
V0.25P
7.2.2 FDC Configuration Registers
FDC Device Enable Register Index 30h
Bit Name R/W Default Description
7-1 Reserved - - Reserved
0 FDC_EN R/W 1 0: disable FDC.
Base Address High Register Index 60h
Bit Name R/W Default Description
F71805
1: enable FDC.
7-0 BASE_ADDR_HI R/W 03h The MSB of FDC base address.
Base Address Low Register Index 61h
Bit Name R/W Default Description
7-0 BASE_ADDR_LO R/W F0h The LSB of FDC base address.
IRQ Channel Select Register Index 70h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
3-0 SELFDCIRQ R/W 06h Select the IRQ channel for FDC.
DMA Channel Select Register Index 74h
Bit Name R/W Default Description
7-3 Reserved - - Reserved.
2-0 SELFDCDMA R/W 010 Select the DAM channel for FDC.
FDD Mode Register Index F0h
Bit Name R/W Default Description
7-4 Reserved - - Reserved.
23
Dec., 2006
V0.25P
3-2 IF_MODE R/W 11 00: Model 30 mode.
1 FDMAMODE R/W 1 0: enable burst mode.
0 EN3MODE R/W 0 0: normal floppy mode (default).
FDD Drive Type Register Index F2h
F71805
01: PS/2 mode.
10: Reserved.
11: AT mode (default).
1: non-busrt mode (default).
1: enhanced 3-mode FDD.
Bit Name R/W Default Description
7-2 Reserved - - Reserved.
1-0 FDD_TYPE R/W 11 FDD drive type.
FDD Selection Register Index F4h
Bit Name R/W Default Description
7-5 Reserved - - Reserved.
4-3 FDD_DRT R/W 00 Data rate table select, refer to table A.
00: select regular drives and 2.88 format.
01: 3-mode drive.
10: 2 mega tape.
11: reserved.
2 Reserved - - Reserved.
1-0 FDD_DT R/W 00 Drive type select, refer to table B.
TABLE A
Data Rate Table Select Data Rate Selected Data Rate DENSEL
FDD_DRT[1] FDD_DRT[0] DATARATE1 DATARATE0 MFM FM
0 0 500K 250K 1
0 0
0 1 0 0 500K 250K 1
0 1 300K 150K 0
1 0 250K 125K 0
1 1 1Meg --- 1
24
Dec., 2006
V0.25P
F71805
1 0
TABLE B
Drive Type
FDD_DT1 FDD_DT0
0 DENSEL 4/2/1 MB 3.5”
0
0 1 DATARATE1
1 0 DENSEL#
1 1 DATARATE0
0 1 500K 250K 0
1 0 250K 125K 0
1 1 1Meg --- 1
0 0 500K 250K 1
0 1 2Meg --- 0
1 0 250K 125K 0
1 1 1Meg --- 1
DRVDEN0 Remark
2/1 MB 5.25”
1/1.6/1 MB 3.5” (3-Mode )
7.2.3 Device Registers
7.2.3.1 Status Register A (PS/2 mode) Base + 0
Bit Name R/W Default Description
7 INTPEND R 0 This bit indicates the state of the interrupt output.
6 DRV2_N R - 0: a second drive has been installed.
1: a second drive has not been installed.
5 STEP R 0 This bit indicates the complement of STEP# disk interface output.
4 TRK0_N R - This bit indicates the state of TRK0# disk interface input.
3 HDSEL R 0 This bit indicates the complement of HDSEL# disk interface output.
0: side 0.
1: side 1.
2 INDEX_N R - This bit indicates the state of INDEX# disk interface input.
1 WPT_N R - This bit indicates the state of WPT# disk interface input.
0: disk is write-protected.
1: disk is not write-protected.
0 DIR R 0 This bit indicates the complement of DIR# disk interface output.
7.2.3.2 Status Register A (Model 30 mode) Base + 0
Bit Name R/W Default Description
25
Dec., 2006
V0.25P
7 INTPEND R 0 This bit indicates the state of the interrupt output.
6 DRQ R 0 This bit indicates the state of the DRQ signal.
5 STEP_FF R 0 This bit indicates the complement of latched STEP# disk interface output.
4 TRK0 R - This bit indicates the complement of TRK0# disk interface input.
3 HDSEL_N R 1 This bit indicates the state of HDSEL# disk interface output.
2 INDEX R - This bit indicates the complement of INDEX# disk interface input.
1 WPT R - This bit indicates the complement of WPT# disk interface input.
0 DIR_N R 1 This bit indicates the state of DIR# disk interface output.
F71805
0: side 0.
1: side 1.
0: disk is write-protected.
1: disk is not write-protected.
0: head moves in inward direction.
1: head moves in outward direction.
7.2.3.3 Status Register B (PS/2 Mode) Base + 1
Bit Name R/W Default Description
7-6 Reserved R - Reserved. Return 11b when read.
5 DR0 R 0 Drive select 0. This bit reflects the bit 0 of Digital Output Register.
4 WDATA R 0 This bit changes state at every rising edge of WDATA#.
3 RDATA R 0 This bit changes state at every rising edge of RDATA#.
2 WGATE R 0 This bit indicates the complement of WGATE# disk interface output.
1 MOTEN1 R 0 This bit indicates the complement of MOB# disk interface output. Not support
in this design.
0 MOTEN0 R 0 This bit indicates the complement of MOA# disk interface output.
7.2.3.4 Status Register B (Model 30 Mode) Base + 1
Bit Name R/W Default Description
7 DRV2_N R - 0: a second drive has been installed.
1: a second drive has not been installed.
6 DSB_N R 1 This bit indicates the state of DRVB# disk interface output. Not support in this
design.
5 DSA_N R 1 This bit indicates the state of DRVA# disk interface output.
4 WDATA_FF R 0 This bit is latched at the rising edge of WDATA# and is cleared by a read from
the Digital Input Register.
3 RDATA_FF R 0 This bit is latched at the rising edge of RDATA# and is cleared by a read form
the Digital Input Register.
2 WGATE_FF R 0 This bit is latched at the falling edge of WGATE# and is cleared by a read from
the Digital Input Register.
1 DSD_N R 1 This bit indicates the complement of DRVD# disk interface output. Not support
in this design.
0 DSC_N R 1 This bit indicates the complement of DRVC# disk interface output. Not support
in this design.
26
Dec., 2006
V0.25P
7.2.3.5 Digital Output Register Base + 2
Bit Name R/W Default Description
7 MOTEN3 R 0 Motor enable 3. Not support in this design.
6 MOTEN2 R 0 Motor enable 2. Not support in this design.
5 MOTEN1 R/W 0 Motor enable 1. Used to control MOB#. MOB# is not support in this design.
4 MOTEN0 R/W 0 Motor enable 0. Used to control MOA#.
3 DAMEN R/W 0 DMA enable. This bit has two mode of operation.
2 RESET R 0 Write 0 to this bit will reset the controller. I will remain in reset condition until a 1
1 DSD_N R 1 This bit indicates the complement of DRVD# disk interface output. Not support
0 DSC_N R 1 This bit indicates the complement of DRVC# disk interface output. Not support
F71805
PC-AT and Model 30 mode: write 1 will enable DMA and IRQ, write 0 will
disable DMA and IRQ.
PS/2 mode: This bit is reserved. DMA and IRQ are always enabled in PS/2
mode.
is written.
in this design.
in this design.
7.2.3.6 Tape Drive Register Base + 3
Bit Name R/W Default Description
7-6 Reserved R - Reserved. Return 00b when read.
5-4 TYPEID R 11 Reserved in normal function, return 11b when read.
If 3 mode FDD function is enabled. These bits indicate the drive type ID.
3-2 Reserved R 11 Reserved. Return 11b when read in normal function.
Return 00b when read in 3 mode FDD function.
1-0 TAPESEL R/W 00 These bits assign a logical drive number to be a tape drive.
7.2.3.7 Main Status Register Base + 4
Bit Name R/W Default Description
7 RQM R 0 Request for Master indicates that the controller is ready to send or receive data
from the uP through the FIFO.
6 DIO R 0 Data I/O (direction):
0: the controller is expecting a byte to be written to the Data Register.
1: the controller is expecting a byte to be read from the Data Register.
5 NON_DMA R 0 Non DMA Mode:
0: the controller is in DAM mode.
1: the controller is interrupt or software polling mode.
4 FDC_BUSY R 0 This bit indicate that a read or write command is in process.
3 DRV3_BUSY R 0 FDD number 3 is in seek or calibration condition. FDD number 3 is not support
in this design.
2 DRV2_BUSY R 0 FDD number 2 is in seek or calibration condition. FDD number 2 is not support
in this design.
27
Dec., 2006
V0.25P
Loading...