Gigabyte ноуты 01/biostar_a78ga-m2t_rev_6.4_sch/biostar_a78ga-m2t_rev_6.4_sch Schematics ноуты 01/biostar_a78ga-m2t_rev_6.4_sch/biostar_a78ga-m2t_rev_6.4_sch Schematics
5
4
3
2
1
D D
PAGE
1
2
3
4
5
6-10
11
12
13
14
15
16
17
C C
B B
A A
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CONTENTS
COVER
BLOCK DIAGRAM
POWER DELIVERY
CLOCK DISTRIBUTION
REVISION HISTROY
SKT 940 K8 M2 CPU
CPU DECOUPLING
DDR CLK BYPASS
DDR2 DIMM A1
DDR2 DIMM B1
DDR2 DIMM A2
DDR2 DIMM B2
DDR2 VTT TERM
DDR2 DECOUPLING
RS780-HT LINK
RS780-PCIE
RS780-SYSTEM
RS780-PWOER&SBD_MEM
CLOCK GEN
SB700-PCIE/PCI/CPU/LPC
SB700-ACPI/GPIO/USB/AUD
SB700-SATA/IDE/HWM/SPI
SB700-POWER&DECOUPLING
SB700-STRAPS
CRT & DVI
PCI-E SLOT
PCI SLOT
IDE ATA 133
USB CONN
CODEC ALC662
AUDIO CONNECTOR
SUPER I/O ITE8718F
HW MONITOR / FAN CONTROL
FDD / PS2 CONN / FLASH
COM&LPT CONNECTOR
ATX PWR / FRONT PANEL / LED
OVER VOLTAGE IC
FRONT USB
PWRGD / MISC DC-DC
VCC_CORE DC-DC CONVER
MEMORY POWER
NB/SB CORE POWER
Realtek RTL8111C
BOM
A78GA-M2T ( RS780&SB700 )
REV 6.4
DDR2 X 4 Dual channel , PCI-Ex16 X 1 , PCI-Ex1 X 1 , PCI X
2 , Realtek 10/100/1000 PCI-E Lan , AMD K8-940
Title
Size Document Number Rev
Custom
Date: Sheet
5
4
3
2
COVER
A78GA-M2T
1
148Tuesday, February 03, 2009
6.4
of
5
4
3
2
1
AMD
AM2/AM2+
D D
Clock Generator
RTM880N-793
DVI/TMDS CON
VGA CON
PCIE
16X
SLOT1
TMDS
16X
HyperTransport
LINK
M2 SOCKET
16x16
OUT
IN
AMD NB
RS780
HyperTransport LINK0 CPU I/F
INTEGRATED GRAPHICS
LVTM
1 16X PCIE VIDEO I/F
1 1X PCIE I/F
DDRII 533,667,800
128bit
DDRII 533,667,800
UNBUFFERED
DDRII
DIMM1
UNBUFFERED
DDRII DIMM2
DDRII FIRST LOGICAL DIMM
UNBUFFERED
DDRII DIMM3
UNBUFFERED
DDRII DIMM4
DDRII SECOND LOGICAL DIMM
C C
ATI SB
SB700
4X
PCIE
SPI I/F
HD AUDIO I/F
SATA II I/F
ATA 66/100/133 I/F
SPI ROM
AZILIA
CODEC
SATA#0
IDE1
HW
MONITOR
SATA#1
SATA#2
SATA#3
SATA#4 SATA#5
GIGABIT
Realtek RTL8111C
USB-5
USB-6
USB-4
USB-7
USB-3
USB-8
B B
USB-2
USB-9
4 1X PCIE
INTERFACE
USB-1
USB-10 USB-11
PCI BUS
PCIE GPP0
X1
USB-0
BOOTSTRAPS
ROM (SB)
USB 2.0
I2C I/F
USB2.0 (12)
SATA II (6)
AC97 2.3/ AZALIA
ATA 66/100/133
ACPI
LPC I/F
INT RTC
HW MONITOR
PCI SLOT #1
DESKTOP M2 POWER
RS780
CORE & PCIE POWER
DDR MEMORY POWER
PCI SLOT #2
PCI SLOT #3
ITE LPC SIO 8716/8718
FLOPPY
KBD
MOUSE
HW
MONITOR
A A
Title
Size Document Number Rev
Custom
Date: Sheet
5
4
3
2
BLOCK DIAGRAM
A78GA-M2T
1
248Tuesday, February 03, 2009
6.4
of
5
ATX P/S WITH 1A STBY CURRENT
5VSB
+/-5%
5V
+/-5%
3.3V
+/-5%
12V
+/-5%
-12V
+/-5%
CPU
PW
12V
+/-5%
D D
VCC 1.1V SW
REGULATOR
4
+5VDUAL_MEM (S0,S5)
VCC 1.2V SW
REGULATOR
2.5V SHUNT
REGULATOR
VRM SW
REGULATOR
1.8V VDD SW
REGULATOR
VCC 1.1V SW
REGULATOR
3
0.9V VTT_DDR
REGULATOR
+1.1V RX780/RS780; +1.2V RS740 (S0, S1)
+1.1V RX780/RS780; +1.2V RS740 (S0, S1)
1.8V LINEAR
REGULATOR
+1.2V(S0, S1)
+1.8V(S0, S1)
2
CPU_VDDA_RUN
VDD_CPUCORE_RUN (S0, S1)/VDD_CPUNB_RUN ( S0 , S1 )
CPU_VTT_SUS (S0,S1,S3)
CPU_VDDIO_SUS(S0,S1,S3)
DDRII DIMMs
VTT_DDR 2A
VDD MEM 12A
1.5V LINEAR
REGULATOR
+1.5V(S0, S1)
(S0, S1)
AM2
VDDA 2.5V 0.2A
VDDCORE
0.8-1.55V
110A
DDRII MEM I/F
VTT 2A, VDD
10A
VLDT 1.2V 0.5A
RS780
VDDHT/RX 1.1V 1.2A
VDDHTTX 1.2V 0.5A
VDDPCIE 1.1V 2A
NB CORE VDDC
1.1V 7A
VDDA18PCIE 1.8V 0.9A
PLLs 1.8V 0.1A
VDD18/VDD18_MEM
1.8V 0.01A
VDD_MEM 1.8V/1.5V 0.5A
AVDD 3.3V 0.135A
1
+3.3VSB (S0, S1, S3, S 4 , S5)
+3.3VSB REGULATOR
ACPI CONTROLLER
C C
+3.3VDUAL (S0, S1, S3, S4, S5)
+5VDUAL (S0, S1, S3, S4, S5)
1.2V STB LDO
REGULATOR
+1.2VSB (S5)
SB700
X4 PCI-E 0.8A
ATA I/O 0.5A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
CLOCK
1.2V S5 PW 0.22A
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
3.3V I/O 0.45A
AZALIA CODEC CON
3.3V CORE 0.3A
Custom
5V ANALOG 0.1A
12V 0.1A
POWER DELIVERY
A78GA-M2T
348Tuesday, February 03, 2009
6.4
of
1
B B
PCI Slot (per slot) X16 PCIE
5V
3.3V
12V
A A
3.3Vaux
0.375A
-12V
X1 PCIE per
3.3V
12V
3.3Vaux
3.0A
0.5A
0.1A
3.3V
12V
5.0A
7.6A 5VDual
3.0A
5.5A
X16 PCIE
3.3V
5.5A
12V
USB X6 FR
VDD 3.0A
5VDual
2.0A0.5A
USB X6 RL
VDD
2.0A
0.1A
+3.3VDUAL (S0, S1, S3 )
5
4
3
2XPS/2
5VDual
1.0A
GBE
3.3V 0.5A (S0, S1)
3.3V 0.1A (S3)
Title
Size Document Number Rev
Date: Sheet
2
5
4
3
2
1
DIMM3
D D
DIMM1
3 PAIR MEM CLK
3 PAIR MEM CLK
AM2/AM2g2 CPU
AM2 SOCKET
C C
B B
DIMM4
1 PAIR CPU CLK
DIMM2
200MHZ
HT ref clock
100MHZ DIFF(RX780/RS780)
HT REFCLK
66MHz SE(RS740)
14.318MHZ OSC
3 PAIR MEM CLK
3 PAIR MEM CLK
1 PAIR CPU CLK
200MHZ
EXTERNAL
CLK GEN.
(RS740/RX780)
HT REFCLK
66MHz SE(RS740)
100MHz
DIFF(RX780/RS780)
NB-OSCIN
14.318MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
NB GFX PCIE CLK
100MHZ
NB GPP PCIE CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
USB CLK
48MHZ
AMD NB
RS740/RX780/RS780
(RX780)
PCIE GFX SLOT 1 - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 4 LANES
PCIE GBE
25MHZ OSC INPUT
NB PCIE Ref clock
100MHZ
NB Disp clock
100MHZ DIFF(RS780)
GPP Ref clock
100MHZ
GFX Ref clock
100MHZ
GPP Ref clock
100MHZ
GPP Ref clock
100MHZ
GPP Ref clock
100MHZ
25MHz
SATA
CPU_HT_CLK
NB_HT_CLK
25M_48M_66M_OSC
AMD SB
SB700
NB_DISP_CLK
GPP_CLK3
PCIE_RCLK/
NB_LNK_CLK
SLT_GFX_CLK
GPP_CLK0
GPP_CLK1
GPP_CLK2
USB_CLK
SB_BITCLK
48MHZ
PCI CLK0
33MHZ
PCI CLK1
33MHZ
PCI CLK2
33MHZ
LPC_CLK0
33MHZ
LPC CLK1
33MHZ
PCI CLK3
33MHZ
PCI CLK4
33MHZ
25MHz
PCI SLOT 0
PCI SLOT 1
PCI SLOT 2
TPM
LPC BIOS
DEBUG POST
SUPER IO
IT8716F
HD AUDIO CON
TPM (BCM5755/5761)
SIO CLK
48MHZ
A A
External clock mode
32.768KHz
Internal clock mode
Title
Size Document Number Rev
Custom
Date: Sheet
5
4
3
2
CLOCK DISTRIBUTION
A78GA-M2T
448Tuesday, February 03, 2009
1
6.4
of
5
REV
DATA
16/09/086.3
6.4
D D
02/02/09
1. Add U6- --->解決3850
1. EMI ( A76GA-M
修改 問題及螺絲孔 使用
2.Add D14,R307,R323
3.U12,U13
4.R320 NI
用料修改
顯卡有時點不亮問題
FP6321A
4
Page:30
2T V6.0 PCB修改)
3
DESCRIPTION
2
1
C C
B B
A A
Title
Size Document Number Rev
Custom
Date: Sheet
5
4
3
2
REVISION HISTORY
A78GA-M2T
548Tuesday, February 03, 2009
1
6.4
of
5
4
3
2
1
D D
HT_CLKIN1_P19
HT_CLKIN1_N19
HT_CLKIN0_P19
HT_CLKIN0_N19
HT_CTLIN1_P19
HT_CTLIN1_N19
HT_CTLIN0_N19
HT_CADIN15_P19
HT_CADIN15_N19
HT_CADIN14_P19
HT_CADIN14_N19
HT_CADIN13_P19
C C
B B
HT_CADIN13_N19
HT_CADIN12_P19
HT_CADIN12_N19
HT_CADIN11_P19
HT_CADIN11_N19
HT_CADIN10_P19
HT_CADIN9_P19
HT_CADIN9_N19
HT_CADIN8_P19
HT_CADIN8_N19
HT_CADIN7_P19
HT_CADIN7_N19
HT_CADIN6_P19
HT_CADIN6_N19
HT_CADIN5_P19
HT_CADIN5_N19
HT_CADIN4_P19
HT_CADIN4_N19
HT_CADIN3_P19
HT_CADIN3_N19
HT_CADIN2_P19
HT_CADIN2_N19 HT_CADOUT2_N 19
HT_CADIN1_P19
HT_CADIN1_N19
HT_CADIN0_P19
HT_CADIN0_N19
HyperTransport
CPU1A
N6
L0_CLKIN_H(1)
P6
L0_CLKIN_L(1)
N3
L0_CLKIN_H(0)
N2
L0_CLKIN_L(0)
V4
L0_CTLIN_H(1)
V5
L0_CTLIN_L(1)
U1
L0_CTLIN_H(0)
V1
L0_CTLIN_L(0)
U6
L0_CADIN_H(15)
V6
L0_CADIN_L(15)
T4
L0_CADIN_H(14)
T5
L0_CADIN_L(14)
R6
L0_CADIN_H(13)
T6
L0_CADIN_L(13)
P4
L0_CADIN_H(12)
P5
L0_CADIN_L(12)
M4
L0_CADIN_H(11)
M5
L0_CADIN_L(11)
L6
L0_CADIN_H(10)
M6
L0_CADIN_L(10)
K4
L0_CADIN_H(9)
K5
L0_CADIN_L(9)
J6
L0_CADIN_H(8)
K6
L0_CADIN_L(8)
U3
L0_CADIN_H(7)
U2
L0_CADIN_L(7)
R1
L0_CADIN_H(6)
T1
L0_CADIN_L(6)
R3
L0_CADIN_H(5)
R2
L0_CADIN_L(5)
N1
L0_CADIN_H(4)
P1
L0_CADIN_L(4)
L1
L0_CADIN_H(3)
M1
L0_CADIN_L(3)
L3
L0_CADIN_H(2)
L2
L0_CADIN_L(2)
J1
L0_CADIN_H(1)
K1
L0_CADIN_L(1)
J3
L0_CADIN_H(0)
J2
L0_CADIN_L(0)
HYPERTRANSPORT
SOCKET_M2 940 SMD
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
HT_CLKOUT1_P 19
HT_CLKOUT1_N 19
HT_CLKOUT0_P 19
HT_CLKOUT0_N 19
HT_CTLOUT1_P 19
HT_CTLOUT1_N 19
HT_CTLOUT0_P 19HT_CTLIN0_P19
HT_CTLOUT0_N 19
HT_CADOUT15_P 19
HT_CADOUT15_N 19
HT_CADOUT14_P 19
HT_CADOUT14_N 19
HT_CADOUT13_P 19
HT_CADOUT13_N 19
HT_CADOUT12_P 19
HT_CADOUT12_N 19
HT_CADOUT11_P 19
HT_CADOUT11_N 19
HT_CADOUT10_P 19
HT_CADOUT10_N 19HT_CADIN10_N19
HT_CADOUT9_P 19
HT_CADOUT9_N 19
HT_CADOUT8_P 19
HT_CADOUT8_N 19
HT_CADOUT7_P 19
HT_CADOUT7_N 19
HT_CADOUT6_P 19
HT_CADOUT6_N 19
HT_CADOUT5_P 19
HT_CADOUT5_N 19
HT_CADOUT4_P 19
HT_CADOUT4_N 19
HT_CADOUT3_P 19
HT_CADOUT3_N 19
HT_CADOUT2_P 19
HT_CADOUT1_P 19
HT_CADOUT1_N 19
HT_CADOUT0_P 19
HT_CADOUT0_N 19
A A
Title
Size Document Number Rev
Custom
Date: Sheet
5
4
3
2
K8 CPU HT
A78GA-M2T
648Tuesday, February 03, 2009
1
6.4
of
5
4
3
2
1
Vout=Vref (1.25V) X ( 1+R2/R1 )=2.5V
D D
C533
1UF 16V 0805 Y5V
ROUTE AS DIF 20/5/5/5/20
LAYOUT: PLACE 169 OHM WITHIN
600mils OF CPU
AND TRACE TO AC CAPS LESS
THAN 1250mil
C C
+1.8V_SUS
R6
16.9 1% 0402
R10
16.9 1% 0402
1 2
12
LESS THAN 1000mil
5/10 M_ZN,M_ZP
B B
+5V
12
OIA
Q1
AZ1117H-ADJ SOT-223
Layout: keep trace to resistors less than 1" from CPU pins
CPU_M_VREFF
12
C6
0.1UF 16V Y5V 0402
R1
R1
100 0402
R4
R2
100 0402
CPU_CLKIN_P23
CPU_CLKIN_N23
12
C7
1000P 50V X7R 0402
12
CT1
10UF 10V 0805 Y5V
CPUCLK
CPUCLK#
CPU_PRESENT#25
ROUTE AS DIFF PAIR
10/5/5/5/10
+1.8V_SUS
+1.8V_SUS
12
C3
0.1UF 16V Y5V 0402
+1.8V_SUS
CPU_CORE_FB44
CPU_CORE_FB_44
CPU_THERMDC36
CPU_THERMDA36
12
C1
1UF 16V 0805 Y5V
C4
3900P 50V X7R 0402
12
R5
C53900P 50V X7R 0402
169 1% 0402
12
1 2
R7 1K 0402
1 2
R8 1K 0402
1 2
R9 1K 0402
1 2
R528 0 0402
1 2
R507 300 0402
R12 39.2 1% 0402
1 2
R14 39.2 1% 0402
1 2
R15 510 0402
1 2
R16 510 0402
1 2
R508 300 0402
R509 300 0402
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
12
CPU_CORE_FB
CPU_CORE_FB_
CPU_M_VREFF
12
12
CPU_VDDA
12
C2
3300P 50V X7R 0402
CPU_PRESENT#
C10
D10
AK6
AK4
AL10
AJ10
AH10
AH11
AJ11
AH9
AG9
AG8
AH7
A8
B8
C9
D8
C7
AL3
AL6
AL9
A5
G2
G1
E12
F1
F12
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
E5
AJ5
AJ6
VDDA1
VDDA2
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
SIC
SID
CPU_SA0
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
VTT_SENSE
PSI_L
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2
CPU1D
MISC
CORE_TYPE
THERMTRIP_L
PROCHOT_L
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
TEST29_H
TEST29_L
SOCKET_M2 940 SMD
TEST28_H
TEST28_L
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
TDO
ALERT_
DBRDY
HTREF1
HTREF0
TEST24
TEST23
TEST22
TEST21
TEST20
TEST27
TEST26
TEST10
TEST8
+1.8V_SUS
RN1
330 8P4R
1 2
3 4
5 6
7 8
G5
D2
D1
C1
E3
E2
E1
AK7
AL7
AK10
AL4
B6
AK11
AL11
G4
G3
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
CPU_THERMTRIP
CPU_PROCHOT_L_1.8
R529 1K 0402
R11 44.2 1% 0402
R13 44.2 1% 0402
FBCLKOUT
FBCLKOUT_
R510 300 0402
R511 300 0402
R18 300 0402
Required for compatibility
with future processors
+1.8V_SUS
12
12
12
R17 80.6 1% 0402
+1.8V_SUS
+1.2V_HT
12
12
12
12
+1.8V_SUS
R2
R3
1K 0402
1K 0402
1 2
1 2
K8_VID5 44
K8_VID4 44
K8_VID3 44
K8_VID2 44
K8_VID1 44
K8_VID0 44
+3.3V_DUAL
G
Q2
APM2300AAC SOT23
CPU_THERMTRIP#
DS
R382
4.7K 0402 /NI
1 2
LAYOUT: PLACE WITHIN 1 INCH OF CPU
5/10
20/8/5/8/20
LAYOUT: PLACE WITHIN 1 INCH OF CPU
LAYOUT: ROUTE 80 OHM DIFF IMPEDENCE
CPU_THERMTRIP# 25
CPU_PROCHOT# 24
3 4
5 6
7 8
CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#
RN4
680 8P4R
1 2
Title
Size Document Number Rev
Custom
Date: Sheet
4
3
2
K8 CPU MISC
A78GA-M2T
1
748Tuesday, February 03, 2009
6.4
of
LDT_RST#24
SB_CPUPWRGD24
LDT_STOP#21,24
A A
+1.8V_SUS
5
5
D D
C C
MEM_MA_ADD[15..0]13,15,17
MEM_MA_DQS_H[8..0]13,15
MEM_MA_DQS_L[8..0]13,15
MEM_MA_ADD[15..0]
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_L[8..0]
MEM_MA0_CLK_H212,13
MEM_MA0_CLK_L212,13
MEM_MA0_CLK_H112,13
MEM_MA0_CLK_L112,13
MEM_MA0_CLK_H012,13
MEM_MA0_CLK_L012,13
MEM_MA0_CS_L113,17
MEM_MA0_CS_L013,17
MEM_MA0_ODT013,17
MEM_MA1_CLK_H212,15
MEM_MA1_CLK_L212,15
MEM_MA1_CLK_H112,15
MEM_MA1_CLK_L112,15
MEM_MA1_CLK_H012,15
MEM_MA1_CLK_L012,15
MEM_MA1_CS_L115,17
MEM_MA1_CS_L015,17
MEM_MA1_ODT015,17
MEM_MA_CAS_L13,15,17
MEM_MA_WE_L13,15,17
MEM_MA_RAS_L13,15,17
MEM_MA_BANK213,15,17
MEM_MA_BANK113,15,17
MEM_MA_BANK013,15,17
MEM_MA_CKE115,17
MEM_MA_CKE013,17
B B
MEM_MA_DM[8..0]13,15
MEM_MA_DM[8..0]
4
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AG21
AG20
G19
H19
U27
U26
AC25
AA24
AC28
AE20
AE19
G20
G21
V27
W27
AD27
AA25
AC27
AB25
AB27
AA26
N25
Y27
AA27
M25
M27
N24
AC26
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
W24
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
D29
C29
C25
D25
E19
F19
F15
G15
AF15
AF19
AJ25
AH29
B29
E24
E18
H15
L27
CPU1B
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
MEMORY INTERFACE A
SOCKET_M2 940 SMD
3
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_DQS_H8
MEM_MA_DQS_L8
MEM_MA_DM8
MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
2
MEM_MA_DATA[0..63]
MEM_MA_DATA[0..63] 13,15
MEM_MA_CHECK[7..0]
1
MEM_MA_CHECK[7..0] 13,15
A A
Title
Size Document Number Rev
Custom
Date: Sheet
5
4
3
2
K8 CPU MEMORY-1
A78GA-M2T
848Tuesday, February 03, 2009
1
6.4
of
5
MEM_MB0_CLK_H212,14
MEM_MB0_CLK_L212,14
MEM_MB0_CLK_H112,14
MEM_MB0_CLK_L112,14
D D
C C
MEM_MB_ADD[15..0]14,16,17
MEM_MB_DQS_H[8..0]14,16
MEM_MB_DQS_L[8..0]14,16
B B
MEM_MB_DM[8..0]14,16
MEM_MB0_CLK_H012,14
MEM_MB0_CLK_L012,14
MEM_MB0_CS_L114,17
MEM_MB0_CS_L014,17
MEM_MB0_ODT014,17
MEM_MB1_CLK_H212,16
MEM_MB1_CLK_L212,16
MEM_MB1_CLK_H112,16
MEM_MB1_CLK_L112,16
MEM_MB1_CLK_H012,16
MEM_MB1_CLK_L012,16
MEM_MB1_CS_L116,17
MEM_MB1_CS_L016,17
MEM_MB1_ODT016,17
MEM_MB_CAS_L14,16,17
MEM_MB_WE_L14,16,17
MEM_MB_RAS_L14,16,17
MEM_MB_BANK214,16,17
MEM_MB_BANK114,16,17
MEM_MB_BANK014,16,17
MEM_MB_CKE116,17
MEM_MB_CKE014,17
MEM_MB_ADD[15..0]
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_L[8..0]
MEM_MB_DM[8..0]
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
A
DD3
MEM_MB_
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
4
CPU1C
AJ19
AK19
A18
A19
U31
U30
AE30
AC31
AD29
AL19
AL18
C19
D19
W29
W28
AE29
AB31
AD31
AC29
AC30
AB29
N31
AA31
AA28
M31
M29
N28
N29
AE31
N30
P29
AA29
P31
R29
R28
R31
R30
T31
T29
U29
U28
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
D31
C31
C24
C23
D17
C17
C14
C13
AJ14
AH17
AJ23
AK29
C30
A23
B17
B13
MEMORY INTERFACE B
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
3
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DM8
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
MEM_MB_DATA[0..63]
MEM_MB_CHECK[7..0]
2
MEM_MB_DATA[0..63] 14,16
MEM_MB_CHECK[7..0] 14,16
1
A A
Title
Size Document Number Rev
Custom
Date: Sheet
5
4
3
2
K8 CPU MEMORY-2
A78GA-M2T
948Tuesday, February 03, 2009
1
6.4
of
5
D D
4
3
10UF 10V 0805 Y5V
+1.2V_HT
1 2
2
C9
C10
0.1UF 16V Y5V 0402
1
+V_CPU +V_CPU +V_CPU +1.2V_HT
AA10
AA12
AA14
AA16
AA18
AB11
AC10
C C
AE10
B B
A A
AA8
AB7
AB9
AC4
AC5
AC8
AD2
AD3
AD7
AD9
AF7
AF9
AG4
AG5
AG7
AH2
AH3
E10
G10
G12
H11
H23
K11
K13
K15
K17
K19
K21
K23
Y17
Y19
F11
J12
J14
J16
J18
J20
J22
J24
L10
L12
CPU1F
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD150
VDD151
VDD1
A4
A6
B3
B5
B7
C2
C4
C6
C8
D3
D5
D7
D9
E4
E6
E8
F5
F7
F9
G6
G8
H7
J8
K7
K9
L4
L5
L8
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
M11
M13
M15
M17
M19
N10
N12
N14
N16
N18
P11
P13
P15
P17
P19
R10
R12
R14
R16
R18
R20
T11
T13
T15
T17
T19
T21
U10
U12
U14
U16
U18
U20
V11
V13
V15
V17
V19
V21
W10
W12
W14
W16
W18
W20
Y11
Y13
Y15
Y21
CPU1G
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD2
L14
L16
L18
M2
M3
M7
M9
N8
P7
P9
R4
R5
R8
T2
T3
T7
T9
U8
V9
W4
W5
W8
Y2
Y3
Y7
Y9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
L20
L22
M21
M23
N20
N22
P21
P23
R22
T23
U22
V23
W22
Y23
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
CPU1H
VDD3
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
+1.8V_SUS
+0.9V_SUS
AJ4
AJ3
AJ2
AJ1
D12
C12
B12
A12
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4
VTT1
VTT2
VTT3
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO29
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
CPU1I
VDDIO
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
H6
H5
H2
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
C11
1 2
10UF 10V 0805 Y5V
+0.9V_SUS
Title
Size Document Number Rev
Custom
Date: Sheet
5
4
3
2
K8 CPU POWER
A78GA-M2T
1
6.4
of
10 48Tuesday, February 03, 2009
5
DECOUPLING BETWEEN PROCESSOR AND DIMMS
PLACE AS CLOSE TO PROCESSOR AS
POSSIBLE
4
3
2
1
D D
+0.9V_SUS
12
C13
10UF 10V 0805 Y5V /NI
+0.9V_SUS
+V_CPU
12
C24
10UF 10V 0805 Y5V
+V_CPU
12
C553
12
C15
10UF 10V 0805 Y5V
10UF 10V 0805 Y5V
C C
B B
12
C16
0.1UF 16V Y5V 0402
PLACE BOTTOM SIDE DECOUPLING
12
C25
10UF 10V 0805 Y5V
12
C29
10UF 10V 0805 Y5V
12
C14
1UF 16V 0805 Y5V
12
C17
0.1UF 16V Y5V 0402
12
C26
10UF 10V 0805 Y5V
12
C30
10UF 10V 0805 Y5V
12
C549
10UF 10V 0805 Y5V
12
12
C554
10UF 10V 0805 Y5V
C18
0.1UF 16V Y5V 0402
12
C27
10UF 10V 0805 Y5V
12
12
C550
10UF 10V 0805 Y5V /NI
12
C19
0.1UF 16V Y5V 0402 /NI
C555
10UF 10V 0805 Y5V
12
C556
10UF 10V 0805 Y5V
+1.8V_SUS
12
10UF 10V 0805 Y5V
C21
12
C557
10UF 10V 0805 Y5V
12
C22
10UF 10V 0805 Y5V
12
C35
10UF 10V 0805 Y5V
12
C23
10UF 10V 0805 Y5V
12
C36
10UF 10V 0805 Y5V
12
C20
10UF 10V 0805 Y5V
12
C38
10UF 10V 0805 Y5V
+1.8V_SUS
A A
12
C40
0.1UF 50V 0805 Y5V
12
C41
0.1UF 16V Y5V 0402 /NI
5
12
C42
1UF 16V 0805 Y5V
4
+V_CPU
12
C46
10UF 10V 0805 Y5V
3
12
C47
10UF 10V 0805 Y5V
Title
Size Document Number Rev
Custom
Date: Sheet
2
CPU DECPOULING CAP
A78GA-M2T
1
of
11 48Tuesday, February 03, 2009
6.4
5
4
3
2
1
MEM_MA0_CLK_H28,13
D D
C C
B B
MEM_MA0_CLK_L28,13
MEM_MA0_CLK_H18,13
MEM_MA0_CLK_L18,13
MEM_MA0_CLK_H08,13
MEM_MA0_CLK_L08,13
MEM_MB0_CLK_H29,14
MEM_MB0_CLK_L29,14
MEM_MB0_CLK_H09,14
MEM_MB0_CLK_L09,14
12
C48
1.5P 50V NPO 0402
12
C50
1.5P 50V NPO 0402
12
C52
1.5P 50V NPO 0402
12
C54
1.5P 50V NPO 0402
12
C56
1.5P 50V NPO 0402
12
C58
1.5P 50V NPO 0402
MEM_MA1_CLK_H28,15
MEM_MA1_CLK_L28,15
MEM_MA1_CLK_H18,15
MEM_MA1_CLK_L18,15
MEM_MA1_CLK_H08,15
MEM_MA1_CLK_L08,15
MEM_MB1_CLK_H29,16
MEM_MB1_CLK_L29,16
MEM_MB1_CLK_H19,16MEM_MB0_CLK_H19,14
MEM_MB1_CLK_L19,16MEM_MB0_CLK_L19,14
MEM_MB1_CLK_H09,16
MEM_MB1_CLK_L09,16
12
C49
1.5P 50V NPO 0402
12
C51
1.5P 50V NPO 0402
12
C53
1.5P 50V NPO 0402
12
C55
1.5P 50V NPO 0402
12
C57
1.5P 50V NPO 0402
12
C59
1.5P 50V NPO 0402
A A
Title
Size Document Number Rev
Custom
Date: Sheet
5
4
3
2
DDR CLK BYPASS
A78GA-M2T
12 48Tuesday, February 03, 2009
1
6.4
of
5
4
3
2
1
+1.8V_SUS
+3.3V
DIMMA1
D D
MEM_MA_DM[8..0]8,15
MEM_MA_DQS_H[8..0]8,15
MEM_MA_DQS_L[8..0]8,15
MEM_MA_DQS_L[8..0]
MEM_MA_DM[8..0]
C C
SCLK14,15,16,23,25,44
SDATA14,15,16,23,25,44
MEM_MA_BANK28,15,17
MEM_MA_BANK18,15,17
MEM_MA_ADD[15..0]8,15,17
MEM_MA_BANK08,15,17
B B
MEM_MA_CHECK[7..0]8,15
A A
MEM_MA_CHECK[7..0]
MEM_MA0_CLK_H08,12
MEM_MA0_CLK_L08,12
MEM_MA0_CLK_H18,12
MEM_MA0_CLK_L18,12
MEM_MA0_CLK_H28,12
MEM_MA0_CLK_L28,12
MEM_MA_CKE08,17
MEM_MA_RAS_L8,15,17
MEM_MA_CAS_L8,15,17
MEM_MA0_CS_L08,17
MEM_MA0_CS_L18,17
MEM_MA_DM8
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
MEM_MA_DQS_H8
MEM_MA_DQS_L
MEM_MA_DQS_H7MEM_MA_DQS_H[8..0]
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
EM_MA_ADD8
M
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
MEM_MA_CKE0
DIMMA1
172
178
184
187
189
1975359646769170
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
164
DQS17_H
165
DQS17_L
232
DQS16_H
233
DQS16_L
223
DQS15_H
224
DQS15_L
211
DQS14_H
212
DQS14_L
202
DQS13_H
203
DQS13_L
155
DQS12_H
156
DQS12_L
146
DQS11_H
147
DQS11_L
134
DQS10_H
135
DQS10_L
125
DQS9_H
126
DQS9_L
46
DQS8_H
8
45
DQS8_L
114
DQS7_H
113
DQS7_L
105
DQS6_H
104
DQS6_L
93
DQS5_H
92
DQS5_L
84
DQS4_H
83
DQS4_L
37
DQS3_H
36
DQS3_L
28
DQS2_H
27
DQS2_L
16
DQS1_H
15
DQS1_L
7
DQS0_H
6
DQS0_L
101
SA2
240
SA1
239
SA0
120
SCL
119
SDA
54
BA2
190
BA1
71
BA0
173
A15
174
A14
196
A13
176
A12
57
A11
70
A10
177
A9
179
A8
58
A7
180
A6
60
A5
61
A4
182
A3
63
A2
183
A1
188
A0
168
CB7
167
CB6
162
CB5
161
CB4
49
CB3
48
CB2
43
CB1
42
CB0
185
CK0_H
186
CK0_L
137
CK1_H
138
CK1_L
220
CK2_H
221
CK2_L
18
RESET_L
52
CKE0
171
CKE1
192
RAS_L
74
CAS_L
193
S0_L
76
S1_L
DDR2-240 pin-T
VDD7
VDD8
VDD9
VDD10
VDD11
175
VDDQ1
VDDQ2
181
191
194515662727578
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
238
VDDQ11
VDDSPD
ERR_OUT_L
PAR_IN
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WE_L
VREF
TEST
ODT0
ODT1
NC1
236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22
21
13
12
129
128
123
122
10
9
4
3
73
1
102
195
77
55
68
19
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_WE_L 8,15,17
MEM_MA0_ODT08,17
MEM_MA_DATA[0..63]
+1.8V_SUS
16.9 1% 0402
16.9 1% 0402
MEM_M_VREF
MEM_MA_DATA[0..63]8,15
R19
12
C60
0.1UF 16V Y5V 0402
1 2
R20
12
C61
1000P 50V X7R 0402
1 2
MEM_M_VREF
PLACE NEAR DIMM SOCKETS
Title
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
DDR DIMM-1
A78GA-M2T
1
13 48Tuesday, February 03, 2009
6.4
of
5
4
3
2
1
+1.8V_SUS
+3.3V
DIMMB1
D D
MEM_MB_DM[8..0]9,16
MEM_MB_DQS_H[8..0]9,16
MEM_MB_DQS_L[8..0]9,16
MEM_MB_DM[8..0]
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_L[8..0]
C C
SCLK13,15,16,23,25,44
SDATA13,15,16,23,25,44
MEM_MB_BANK29,16,17
MEM_MB_BANK19,16,17
MEM_MB_BANK09,16,17
MEM_MB_ADD[15..0]9,16,17
MEM_MB_ADD[15..0]
B B
MEM_MB_CHECK[7..0]9,16
A A
MEM_MB_CHECK[7..0]
MEM_MB0_CLK_H09,12
MEM_MB0_CLK_L09,12
MEM_MB0_CLK_H19,12
MEM_MB0_CLK_L19,12
MEM_MB0_CLK_H29,12
MEM_MB0_CLK_L29,12
MEM_MB_CKE09,17
MEM_MB_RAS_L9,16,17
MEM_MB_CAS_L9,16,17
MEM_MB0_CS_L09,17
MEM_MB0_CS_L19,17
5
MEM_MB_DM8
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_
M
B_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
+3.3V
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7 MEM_MB_DATA9
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
4
DIMMB1
164
DQS17_H
165
DQS17_L
232
DQS16_H
233
DQS16_L
223
DQS15_H
224
DQS15_L
211
DQS14_H
212
DQS14_L
202
DQS13_H
203
DQS13_L
155
DQS12_H
156
DQS12_L
146
DQS11_H
147
DQS11_L
134
DQS10_H
135
DQS10_L
125
DQS9_H
126
DQS9_L
46
DQS8_H
45
DQS8_L
114
DQS7_H
113
DQS7_L
105
DQS6_H
104
DQS6_L
93
DQS5_H
92
DQS5_L
84
DQS4_H
83
DQS4_L
37
DQS3_H
36
DQS3_L
28
DQS2_H
27
DQS2_L
16
DQS1_H
15
DQS1_L
7
DQS0_H
6
DQS0_L
101
SA2
240
SA1
239
SA0
120
SCL
119
SDA
54
BA2
190
BA1
71
BA0
173
A15
174
A14
196
A13
176
A12
57
A11
70
A10
177
A9
179
A8
58
A7
180
A6
60
A5
61
A4
182
A3
63
A2
183
A1
188
A0
168
CB7
167
CB6
162
CB5
161
CB4
49
CB3
48
CB2
43
CB1
42
CB0
185
CK0_H
186
CK0_L
137
CK1_H
138
CK1_L
220
CK2_H
221
CK2_L
18
RESET_L
52
CKE0
171
CKE1
192
RAS_L
74
CAS_L
193
S0_L
76
S1_L
DDR2-240 pin-T
172
178
VDD1
VDD2
184
187
189
1975359646769170
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
175
VDDQ1
VDDQ2
181
191
194515662727578
VDDQ3
VDDQ4
VDDQ5
VDDQ6
3
VDDQ7
VDDQ8
VDDQ9
VDDQ10
238
VDDQ11
VDDSPD
ERR_OUT_L
PAR_IN
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WE_L
VREF
TEST
ODT0
ODT1
NC1
236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22
21
13
12
129
128
123
122
10
9
4
3
73
1
102
195
77
55
68
19
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_WE_L 9,16,17
MEM_MB0_ODT09,17
2
MEM_MB_DATA[0..63]
12
C62
0.1UF 16V Y5V 0402
PLACE NEAR DIMM SOCKETS
Title
Size Document Number Rev
Date: Sheet
MEM_M_VREF
Custom
MEM_MB_DATA[0..63]9,16
DDR DIMM-2
A78GA-M2T
1
14 48Tuesday, February 03, 2009
6.4
of
5
4
3
2
1
+1.8V_SUS
+3.3V
DIMMA2
D D
MEM_MA_DM[8..0]8,13
MEM_MA_DQS_H[8..0]8,13
C C
MEM_MA_DQS_L[8..0]8,13
MEM_MA_ADD[15..0]8,13,17
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_L[8..0]
MEM_MA_DM[8..0]
SCLK13,14,16,23,25,44
SDATA13,14,16,23,25,44
MEM_MA_BANK28,13,17
MEM_MA_BANK18,13,17
MEM_MA_BANK08,13,17
B B
MEM_MA_CHECK[7..0]8,13
A A
MEM_MA_CHECK[7..0]
MEM_MA1_CLK_H08,12
MEM_MA1_CLK_L08,12
MEM_MA1_CLK_H18,12
MEM_MA1_CLK_L18,12
MEM_MA1_CLK_H28,12
MEM_MA1_CLK_L28,12
MEM_MA_CKE18,17
MEM_MA_RAS_L8,13,17
MEM_MA_CAS_L8,13,17
MEM_MA1_CS_L08,17
MEM_MA1_CS_L18,17
5
MEM_MA_DQS_H8
MEM_MA_DQS_L8
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
+3.3V
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
MEM_MA_CKE1
MEM_MA_DM8
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
4
DIMMA2
164
DQS17_H
165
DQS17_L
232
DQS16_H
233
DQS16_L
223
DQS15_H
224
DQS15_L
211
DQS14_H
212
DQS14_L
202
DQS13_H
203
DQS13_L
155
DQS12_H
156
DQS12_L
146
DQS11_H
147
DQS11_L
134
DQS10_H
135
DQS10_L
125
DQS9_H
126
DQS9_L
46
DQS8_H
45
DQS8_L
114
DQS7_H
113
DQS7_L
105
DQS6_H
104
DQS6_L
93
DQS5_H
92
DQS5_L
84
DQS4_H
83
DQS4_L
37
DQS3_H
36
DQS3_L
28
DQS2_H
27
DQS2_L
16
DQS1_H
15
DQS1_L
7
DQS0_H
6
DQS0_L
101
SA2
240
SA1
239
SA0
120
SCL
119
SDA
54
BA2
190
BA1
71
BA0
173
A15
174
A14
196
A13
176
A12
57
A11
70
A10
177
A9
179
A8
58
A7
180
A6
60
A5
61
A4
182
A3
63
A2
183
A1
188
A0
168
CB7
167
CB6
162
CB5
161
CB4
49
CB3
48
CB2
43
CB1
42
CB0
185
CK0_H
186
CK0_L
137
CK1_H
138
CK1_L
220
CK2_H
221
CK2_L
18
RESET_L
52
CKE0
171
CKE1
192
RAS_L
74
CAS_L
193
S0_L
76
S1_L
DDR2-240 pin-G
172
178
VDD1
VDD2
184
187
189
1975359646769170
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
175
VDDQ1
VDDQ2
181
191
194515662727578
VDDQ3
VDDQ4
VDDQ5
VDDQ6
3
VDDQ7
VDDQ8
VDDQ9
VDDQ10
238
VDDQ11
VDDSPD
ERR_OUT_L
PAR_IN
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WE_L
VREF
TEST
ODT0
ODT1
NC1
236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22
21
13
12
129
128
123
122
10
9
4
3
73
1
102
195
77
55
68
19
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
ATA3
D
MEM_MA_
MEM_MA_DATA2MEM_MA_ADD0
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_WE_L 8,13,17
MEM_MA1_ODT08,17
2
MEM_MA_DATA[0..63]
MEM_M_VREF
12
C63
0.1UF 16V Y5V 0402
PLACE NEAR DIMM SOCKETS
Title
Size Document Number Rev
Custom
Date: Sheet
MEM_MA_DATA[0..63]8,13
DDR DIMM-3
A78GA-M2T
1
15 48Tuesday, February 03, 2009
6.4
of
Loading...