Genesys GL852G-HHGXX, GL852G-MNGXX, GL852G-OHGXX, GL852G-PMGXX Schematics

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Genesys Logic, Inc.

GL852G

USB 2.0 MTT Hub Controller

Datasheet

Revision 1.26

May 16, 2012

GL852G Datasheet

Ownership and Title

Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder.

Disclaimer

All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.

Genesys Logic, Inc.

12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231, New Taipei City, Taiwan

Tel : (886-2) 8913-1888

Fax : (886-2) 6629-6168

http ://www.genesyslogic.com

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GL852G Datasheet

		Revision History

Revision	Date	Description
1.00	05/26/2009	First formal release
1.01	06/18/2009	Add On-chip power regulator spec, Ch6.6, p.28
		Update 3.3 pin description,p.14
1.02	09/01/2009	Update table-6.2 operating ranges, p.24
1.02	09/01/2009	Update table-6.3 power dissipation, p.25
		Update Ch8 order information, p.32
1.03	10/23/2009	Modify table 5.3 – port number configuration, p.23
1.04	11/04/2009	Update Table 6.6 – DC Supply Current, p.26
1.05	05/17/2010	Update Table 6.6 – DC Supply Current for GL852G-1x version, p.26
1.06	06/04/2010	Update Table 5.3 – port number configuration for GL852G-1x version,
1.06	06/04/2010	p.24
		Add SSOP28 package information, p.8, 9, 12~15, 26
1.07	12/27/2010	Modify Ch2 features, p.9
1.07	12/27/2010	Modify 5.2.5 EEPROM Setting, p.24
		Modify 6.6 On-Chip Power Regulator, p.31
1.08	03/22/2011	Modify SSOP28 pinout, p.12~15
1.08	03/22/2011	Update table-6.3 DC characteristics except USB signals, p.27
1.09	04/21/2011	Add LQFN 46 package information, p8, 9, 13, 15~17, 26, 27, 37, 38
1.10	05/11/2011	Modify SSOP28 package dimension information, p.36
1.20	07/15/2011	Update Table 3.3 pin description, RREF I/O type, p.16
1.21	07/15/2011	Update Table 3.1, 3.2, 3.3, 3.4, 3.5 RREF I/O type, p.14~16
1.22	08/26/2011	Update Table-6.3 DC characteristics except USB signals (RDN, RUP), p.29
1.23	11/21/2011	Update Table 3.5 Pin Description, p.17
1.24	12/22/2011	Updated Table 6.2 Operating Ranges, p.28
1.25	01/03/2012	Updated Table 3.5 Pin Descriptions, p.17
1.26	05/16/2012	Modified CH8 Ordering Information, p.38

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		GL852G Datasheet
	Table of Contents
CHAPTER 1	GENERAL DESCRIPTION ........................................................................	8
CHAPTER 2	FEATURES....................................................................................................	9
CHAPTER 3	PIN ASSIGNMENT ....................................................................................	10
3.1 Pinouts .........................................................................................................................		10
3.2 Pin List.........................................................................................................................		14
3.3 Pin Descriptions..........................................................................................................		16
CHAPTER 4	BLOCK DIAGRAM ...................................................................................	19
CHAPTER 5	FUNCTION DESCRIPTION.....................................................................	20
5.1 General Description....................................................................................................		20
5.1.1 USPORT Transceiver.........................................................................................		20
5.1.2 PLL (Phase Lock Loop) .....................................................................................		20
5.1.3 FRTIMER ...........................................................................................................		20
5.1.4 μC .........................................................................................................................		20
5.1.5 UTMI (USB 2.0 Transceiver Microcell Interface)...........................................		20
5.1.6 USPORT Logic ...................................................................................................		20
5.1.7 SIE (Serial Interface Engine).............................................................................		20
5.1.8 Control/Status Register......................................................................................		20
5.1.9 REPEATER ........................................................................................................		21
5.1.10 TT (Transaction Translator) ...........................................................................		21
5.1.11 REPEATER/TT Routing Logic.......................................................................		21
5.1.12 DSPORT Logic .................................................................................................		22
5.1.13 DSPORT Transceiver.......................................................................................		22
5.2 Configuration and I/O Settings .................................................................................		23
5.2.1 RESET Setting ....................................................................................................		23
5.2.2 PGANG Setting...................................................................................................		24
5.2.3 SELF/BUS Power Setting ..................................................................................		25
5.2.4 LED Connections................................................................................................		25
5.2.5 EEPROM Setting................................................................................................		26
5.2.6 Power Switch Enable Polarity (Only Available for LQFP48/LQFN46
Package)........................................................................................................................		26
5.2.7 Port Number Configuration (Only Available for LQFP48/LQFN46 Package)
.......................................................................................................................................		26
©2012 Genesys Logic, Inc. - All rights reserved.		Page 4

	GL852G Datasheet
5.2.8 Non-removable Port Configuration (Only Available for LQFP48/LQFN46
Package).........................................................................................................................		27
5.2.9 Reference Clock Configuration (Only Available for LQFP48/LQFN46
Package)........................................................................................................................		27
CHAPTER 6	ELECTRICAL CHARACTERISTICS.....................................................	28
6.1 Maximum Ratings ......................................................................................................		28
6.2 Operating Ranges .......................................................................................................		28
6.3 DC Characteristics .....................................................................................................		28
6.4 Power Consumption ...................................................................................................		30
6.5 AC Characteristics .....................................................................................................		30
6.5.1 93C46 EEPROM IF............................................................................................		31
6.5.2 24C02 EEPROM Interface ................................................................................		32
6.6 On-Chip Power Regulator.........................................................................................		33
CHAPTER 7	PACKAGE DIMENSION ..........................................................................	34
CHAPTER 8	ORDERING INFORMATION ..................................................................	38

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GL852G Datasheet

List of Figures
Figure 3.1 - GL852G 48 Pin LQFP Pinout Diagram ..........................................................	10
Figure 3.2 - GL852G 28 Pin QFN Pinout Diagram.............................................................	11
Figure 3.3 - GL852G SSOP 28 Pin Pinout Diagram ...........................................................	12
Figure 3.4 - GL852G LQFN 46 Pin Pinout Diagram..........................................................	13
Figure 4.1 - GL852G Block Diagram (Multiple TT)...........................................................	19
Figure 5.1 - Operating in USB 1.1 Schemes.........................................................................	21
Figure 5.2 - Operating in USB 2.0 Schemes.........................................................................	22
Figure 5.3 - Power on Reset Diagram...................................................................................	23
Figure 5.4 - Power on Sequence of GL852G........................................................................	23
Figure 5.5 - Timing of PGANG Strapping...........................................................................	24
Figure 5.6 - GANG Mode Setting .........................................................................................	24
Figure 5.7 - SELF/BUS Power Setting .................................................................................	25
Figure 5.8 - LED Connection ................................................................................................	25
Figure 5.9 - Schematics between GL852G and 93C46........................................................	26
Figure 6.1 - Vin(V5) vs Vout(V33)*......................................................................................	33
Figure 7.1 - GL852G 48 Pin LQFP Package........................................................................	34
Figure 7.2 - GL852G 28 Pin QFN Package..........................................................................	35
Figure 7.3 - GL852G 28 Pin SSOP Package ........................................................................	36
Figure 7.4 - GL852G 46 Pin LQFN Package .......................................................................	37

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GL852G Datasheet

	List of Tables
Table 3.1 - GL852G LQFP 48 Pin List.................................................................................		14
Table 3.2 - GL852G QFN 28 Pin List...................................................................................		14
Table 3.3 - GL852G SSOP 28 Pin List .................................................................................		14
Table 3.4 - GL852G LQFN 46 Pin List ................................................................................		15
Table 3.5 - Pin Descriptions...................................................................................................		16
Table 5.1 - Configuration by Power Switch Type ...............................................................		26
Table 5.2 - Port Number Configuration...............................................................................		26
Table 5.3 - Ref. Clock Configuration....................................................................................		27
Table 6.1 - Maximum Ratings...............................................................................................		28
Table 6.2 - Operating Ranges................................................................................................		28
Table 6.3 - DC Characteristics except USB Signals ............................................................		28
Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode..................................		29
Table 6.5 - DC Characteristics of USB Signals under HS Mode .......................................		29
Table 6.6	- DC Supply Current.............................................................................................	30
Table 6.7	- AC Characteristics of EEPROM Interface (93C46)........................................	31
Table 6.8	- AC Characteristics of EEPROM Interface (24C02)........................................	32
Table 8.1	- Ordering Information.........................................................................................	38

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GL852G Datasheet

CHAPTER 1 GENERAL DESCRIPTION

GL852G is Genesys Logic’s premium 4-port hub solution which fully complies with Universal Serial Bus Specification Revision 2.0. GL852G implements multiple TT* (Note1) architecture that provide dedicated TT* to each downstream (DS) ports, which guarantee Full-Speed(FS) data passing bandwidth when multiple FS device perform heavy loading operations. The controller inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design. GL852G has proven compatibility, lower power consumption figure and better cost structure above all USB2.0 hub solutions worldwide.

GL852G implements multiple hub configuration features onto internal mask ROM, which traditionally requires one external EEPROM. The microprocessor detects general purpose I/O (GPIO) status during the initial stage to configure hub settings such as (1) number of DSport, (2) declare of compound device (3) gang/individual mode selection…etc. External EEPROM can be removed if no vendor specified PID/VID or product string is required for the application.

GL852G supports three package types, summarized as below table. LQFP48/LQFN46 package provides full hub features such as (1) two-color (green/amber) status LEDs for each DS ports, (2) Individual/Gang mode power management scheme that indicates DS port over-current events. (3) Number of DS ports setting configured by GPIO setting (4) non-removable declaration configured by GPIO setting (5) Support both 93C46 and 24C02 EEPROM (6) power switch polarity selections…etc. QFN28/SSOP28 package support only partial hub features but provide smaller footprint that targets space limited PCB layout environments such as embedded system or UMPC/MID applications.

Package

# of DS

Port #

Non-removable

Power Mgmt.

LED Support

EEPROM

Type

Ports

Config.

Declaration

LQFP 48

GPIO

EEPROM/

Individual/Gang

Green/Amber

93C46/ 24C02

GPIO

QFN 28

EEPROM

Individual/Gang

N/A

24C02

SSOP 28

EEPROM

Gang

N/A

24C02

LQFN46

GPIO

EEPROM/

Individual/Gang

Green/Amber

93C46/ 24C02

GPIO

GL852G Package – Feature Summary

*Note 1: TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports.

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GL852G Datasheet

CHAPTER 2 FEATURES

Compliant to USB specification Revision 2.0

4 downstream ports

Upstream port supports both high-speed (HS) and full-speed (FS) traffic

Downstream ports support HS, FS, and low-speed (LS) traffic

1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)

Backward compatible to USB specification Revision 1.1

On-chip 8-bit micro-processor

RISC-like architecture

USB optimized instruction set

Dual cycle instruction execution

Performance: 6 MIPS @ 12MHz

With 64-byte RAM and 2K internal ROM

Support customized PID, VID by reading external EEPROM

Support downstream port configuration by reading external EEPROM

Multiple Transaction translator (MTT)

MTT provides respective TT control logics for each downstream port.

Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0

Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors

Support both individual and gang modes of power management and over-current detection for downstream ports

Conform to bus power requirements of USB 2.0 specification

Automatic switching between self-powered and bus-powered modes

Integrate USB 2.0 transceiver

Embedded PLL support external 12 MHz crystal / Oscillator clock input

Optional 27/48 MHz Oscillator clock input (Only available in LQFP48/ LQFN46 package)

Support compound-device (non-removable in downstream ports) by I/O pin configuration (Only available in LQFP48/ LQFN46 package)

Number of Downstream port can be configured by GPIO without external EEPROM (Only available in LQFP48/ LQFN46 package)

Built-in 5V to 3.3V regulator

Improve output drivers with slew-rate control for EMI reduction

Internal power-fail detection for ESD recovery

Available package types: 48 pin LQFP, 28 pin QFN, 28 pin SSOP and 46 pin LQFN

Applications:

Stand-alone USB hub / USB docking

UMPC/MID, motherboard on-board applications

Consumer electronics built-in hub application

Monitor built-in hub

Embedded systems

Compound device to support USB hub function such as keyboard hub applications

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GL852G Datasheet

CHAPTER 3 PIN ASSIGNMENT

3.1 Pinouts



	PSELF	37	24	AMBER4
	PSELF	37	24	AMBER4


	DVDD	38	23	GREEN4
	DVDD	38	23	GREEN4


	PGANG	39	22	DP4
	PGANG	39	22	DP4


	OVCUR2#	40	21	DM4
	OVCUR2#	40	21	DM4


	PWREN2#	41	20	GND
	PWREN2#	41	20	GND



	OVCUR1#	42	19	AVDD
	OVCUR1#	42	19	AVDD



PWREN1# / SDA		43	18	DP3
PWREN1# / SDA		43	18	DP3


	SEL27#	44	17	DM3
	SEL27#	44	17	DM3



	GREEN1/EE_SK	45	16	AVDD
	GREEN1/EE_SK	45	16	AVDD



AMBER1/EE_CS		46	15	X2
AMBER1/EE_CS		46	15	X2


	V5	47	14	X1
	V5	47	14	X1


	V33	48	13	GND
	V33	48	13	GND

Figure 3.1 - GL852G 48 Pin LQFP Pinout Diagram

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Genesys GL852G-HHGXX, GL852G-MNGXX, GL852G-OHGXX, GL852G-PMGXX Schematics

GL852G Datasheet

DVDD

OVCUR3#

OVCUR4#

TEST/SCL

RESET#

DP4

DM4

PSELF			22									14	AVDD
PSELF			22									14	AVDD
PGANG		23										13	DP3
PGANG		23										13	DP3
OVCUR2#				24								12	DM3
OVCUR2#				24								12	DM3
OVCUR1#				25								11	X2
OVCUR1#				25								11	X2
SDA				26								10	X1
SDA				26								10	X1
V5				27				QFN-28				9	AVDD
V5				27								9	AVDD
V33					28							8	RREF
V33					28							8	RREF
	1					2	3		4	5	6	7


										AVDD		DP2
					DM0	DP0	DM1		DP1	AVDD	DM2	DP2
					Figure 3.2 - GL852G 28 Pin QFN Pinout Diagram

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GL852G Datasheet

AVDD	1	28	DP1
AVDD	1	28	DP1
DM2	2	27	DM1
DM2	2	27	DM1
DP2	3	26	DP0
DP2	3	26	DP0
RREF	4	25	DM0
RREF	4	25	DM0
AVDD	5	24	V33
AVDD	5	24	V33
X1	6	23	V5
X1	6	23	V5
X2	7	22	PWREN1#
X2	7	22	PWREN1#
DM3	8	21	OVCUR1#
DM3	8	21	OVCUR1#
DP3	9	20	PWREN2#
DP3	9	20	PWREN2#
AVDD 10		19	OVCUR2#
AVDD 10		19	OVCUR2#
DM4	11	18	PGANG


DP4	12	17	PSELF
DP4	12	17	PSELF
RESET#	13	16	DVDD
RESET#	13	16	DVDD
TEST/SCL	14	15 GND
TEST/SCL	14	15 GND

Figure 3.3 - GL852G SSOP 28 Pin Pinout Diagram

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