GENESYS GL850 Datasheet

Genesys Logic, Inc.

GL850

USB 2.0

4-PORT HUB Controller

Datasheet

Revision 1.11

Jun. 25, 2003

GL850 USB 2.0 4-Port HUB Controller

Copyright:

Copyright © 2003 Genesys Logic Incorporated. All rights reserved. No part of the materials may be
reproduced in any form or by any means without prior written consent of Genesys Logic Inc..

Disclaimer:

ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY
KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF
GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND
CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR
EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC
BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING
FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS
MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE
MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.

Trademarks:

is a registrated trademark of Genesys Logic Inc..

All trademarks are the properties of their respective owners.

Office:

Genesys Logic, Inc.

12F, No. 205, Sec. 3, Beishin Rd., Shindian City,
Taipei, Taiwan
Tel: [phone]
Fax: [phone]

http://www.genesyslogic.com

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 2

GL850 USB 2.0 4-Port HUB Controller

Revision History

Revision Date Description

1.00 05/22/2003 First formal release

1.10 06/11/2003

1.11 06/25/2003

Add Bus Power statement
Gang/Individual mode setting modified

Add “4 port” bus power statement

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 3

GL850 USB 2.0 4-Port HUB Controller

TABLE OF CONTENTS

CHAPTER 1 GENERAL DESCRIPTION........................................................................ 9

CHAPTER 2 FEATURES ................................................................................................. 10

CHAPTER 3 PIN ASSIGNMENT.................................................................................... 11

3.1 PINOUTS ....................................................................................................................... 11

3.2 PIN LIST........................................................................................................................ 12

3.3 PIN DESCRIPTIONS .......................................................................................................13

CHAPTER 4 BLOCK DIAGRAM................................................................................... 15

CHAPTER 5 FUNCTION DESCRIPTION .................................................................... 16

5.1 GENERAL...................................................................................................................... 16

5.1.1 USPORT Transceiver......................................................................................... 16

5.1.2 PLL (Phase Lock Loop) .....................................................................................16

5.1.3 FRTIMER ........................................................................................................... 16

5.1.4 µC ......................................................................................................................... 16

5.1.5 UTM (USB2.0 Transceiver Macrocell Interface) ............................................ 16

5.1.6 USPORT logic ..................................................................................................... 16

5.1.7 SIE (Serial Interface Engine)............................................................................. 16

5.1.8 Control/Status register ....................................................................................... 16

5.1.9 REPEATER ........................................................................................................ 17

5.1.10 TT (Transaction Translator) ........................................................................... 17

5.1.11 REPEATER/TT routing logic ......................................................................... 17

5.1.11.1 Connected to 1.1 Host/Hub ...................................................................... 17

5.1.11.2 Connected to USB2.0 Host/Hub .............................................................. 18

5.1.12 DSPORT logic ................................................................................................... 18

5.1.13 DSPORT Transceiver....................................................................................... 18

5.2 CONFIGURATION AND I/O SETTINGS .......................................................................... 19

5.2.1 RESET# Setting .................................................................................................. 19

5.2.2 PGANG/SUSPND Setting .................................................................................. 20

5.2.3 SELF/BUS Power Setting .................................................................................. 21

5.2.4 LED Connections................................................................................................ 22

5.2.5 EEPROM Setting................................................................................................ 22

5.3 USB PROTOCOLS ......................................................................................................... 23

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 4

GL850 USB 2.0 4-Port HUB Controller

5.3.1 Host Commands and Hub Answers .................................................................. 24

5.3.1.1 Standard Requests ...................................................................................... 24

5.3.1.2 Hub Class Requests .................................................................................... 25

ESCRIPTORS ............................................................................................................... 27

5.4 D

5.4.1 Full Speed Case................................................................................................... 27

5.4.1.1 Device Descriptor........................................................................................ 27

5.4.1.2 Device Qualifier Descriptor ....................................................................... 28

5.4.1.3 Configuration Descriptor ........................................................................... 28

5.4.1.4 Interface Descriptor.................................................................................... 29

5.4.1.5 Endpoint Descriptor ................................................................................... 29

5.4.1.6 Other Speed Configuration Descriptor..................................................... 30

5.4.1.7 Interface Descriptor combined with Other Speed Configuration

Descriptor .................................................................................................... 30

5.4.1.8 Endpoint Descriptor combined with Other Speed Configuration

Descriptor .................................................................................................... 31

5.4.1.9 String Descriptor......................................................................................... 31

5.4.2 High Speed Case ................................................................................................. 32

5.4.2.1 Device Descriptor........................................................................................ 32

5.4.2.2 Device Qualifier Descriptor ....................................................................... 33

5.4.2.3 Configuration Descriptor ........................................................................... 33

5.4.2.4 Interface Descriptor.................................................................................... 34

5.4.2.5 Endpoint Descriptor in Configuration Descriptor .................................. 34

5.4.2.6 Other Speed Configuration Descriptor..................................................... 35

5.4.2.7 Interface Descriptor in Other Speed Configuration Descriptor............. 35

5.4.2.8 Endpoint Descriptor in Other Speed Configuration Descriptor ............ 36

5.4.2.9 String Descriptor......................................................................................... 36

5.4.3 Hub Class Descriptor ......................................................................................... 37

CHAPTER 6 ELECTRICAL CHARACTERISTICS .................................................... 38

6.1 M

AXIMUM RATINGS .................................................................................................... 38

6.2 DC CHARACTERISTICS................................................................................................ 38

CHAPTER 7 PACKAGE DIMENSION.......................................................................... 40

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 5

GL850 USB 2.0 4-Port HUB Controller

LIST OF FIGURES

FIGURE 3.1 - PINOUT DIAGRAM ........................................................................................ 11

FIGURE 4.1 - BLOCK DIAGRAM ......................................................................................... 15

FIGURE 5.1 - OPERATING IN USB1.1 SCHEME.................................................................. 17

FIGURE 5.2 - OPERATING IN USB2.0 SCHEME.................................................................. 18

FIGURE 5.3 - RESET# (EXTERNAL RESET) SETTING AND APPLICATION........................ 19

FIGURE 5.4 - POWER ON SEQUENCE OF GL850 ................................................................ 20

FIGURE 5.5 - TIMING OF PGANG/SUSPND STRAPPING ................................................. 20

FIGURE 5.6 - GANG MODE SETTING ............................................................................... 21

FIGURE 5.7 - SELF/BUS POWER SETTING ...................................................................... 21

FIGURE 5.8 - LED CONNECTION ...................................................................................... 22

FIGURE 5.9 - SCHEMATICS BETWEEN GL850 AND 93C46............................................... 23

FIGURE 7.1 - GL850 64 PIN LQFP PACKAGE .................................................................. 40

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 6

GL850 USB 2.0 4-Port HUB Controller

LIST OF TABLES

TABLE 3.1 - PIN LIST ......................................................................................................... 12

TABLE 3.2 - PIN DESCRIPTIONS......................................................................................... 13

TABLE 5.1 - 93C46 CONFIGURATION................................................................................ 22

ABLE 5.2 - STANDARD REQUEST LIST............................................................................. 24

T

T

ABLE 5.3 - HUB CLASS REQUESTS LIST.......................................................................... 25

TABLE 5.4 - DEVICE DESCRIPTOR FOR FULL SPEED ........................................................ 27

ABLE 5.5 - DEVICE QUALIFIER FOR FULL SPEED........................................................... 28

T

T

ABLE 5.6 - CONFIGURATION DESCRIPTOR FOR FULL SPEED......................................... 28

TABLE 5.7 - INTERFACE DESCRIPTOR FOR FULL SPEED .................................................. 29

TABLE 5.8 - ENDPOINT DESCRIPTOR FOR FULL SPEED.................................................... 29

TABLE 5.9 - OTHER SPEED CONFIGURATION DESCRIPTOR FOR FULL SPEED ................ 30

TABLE 5.10 - OTHER SPEED INTERFACE DESCRIPTOR FOR FULL SPEED........................ 30

TABLE 5.11 - OTHER SPEED ENDPOINT DESCRIPTOR FOR FULL SPEED ......................... 31

TABLE 5.12 - STRING INDEX0 FOR FULL SPEED............................................................... 31

TABLE 5.13 - STRING INDEX1 FOR FULL SPEED............................................................... 31

TABLE 5.14 - STRING INDEX2 FOR FULL SPEED............................................................... 32

ABLE 5.15 - DEVICE DESCRIPTOR FOR HIGH SPEED...................................................... 32

T

T

ABLE 5.16 - DEVICE QUALIFIER FOR HIGH SPEED ........................................................ 33

ABLE 5.17 - CONFIGURATION DESCRIPTOR FOR HIGH SPEED ...................................... 33

T

T

ABLE 5.18 - INTERFACE DESCRIPTOR FOR HIGH SPEED................................................ 34

TABLE 5.19 - ENDPOINT DESCRIPTOR FOR HIGH SPEED ................................................. 34

ABLE 5.20 - OTHER SPEED CONFIGURATION DESCRIPTOR FOR HIHG SPEED .............. 35

T

T

ABLE 5.21 - OTHER SPEED INTERFACE DESCRIPTOR FOR HIGH SPEED ....................... 35

TABLE 5.22 - OTHER SPEED ENDPOINT DESCRIPTOR FOR HIGH SPEED ......................... 36

TABLE 5.23 - STRING INDEX0 FOR HIGH SPEED............................................................... 36

TABLE 5.24 - STRING INDEX1 FOR HIGH SPEED............................................................... 36

TABLE 5.25 - STRING INDEX2 FOR HIGH SPEED............................................................... 36

ABLE 5.26 - HUB CLASS DESCRIPTOR ............................................................................ 37

T

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 7

GL850 USB 2.0 4-Port HUB Controller

TABLE 6.1 - MAXIMUM RATINGS ...................................................................................... 38

TABLE 6.2 - DC CHARACTERISTICS EXCEPT USB SIGNALS ........................................... 38

TABLE 6.3 - DC CHARACTERISTICS OF USB SIGNALS UNDER FS/LS MODE................. 38

TABLE 6.4 - DC CHARACTERISTICS OF USB SIGNALS UNDER HS MODE ...................... 39

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 8

GL850 USB 2.0 4-Port HUB Controller

CHAPTER 1 GENERAL DESCRIPTION

GL850 is a 4-port standard Universal Serial Bus (USB) hub controller complies with Universal Serial Bus
Specification Revision 2.0. GL850 can be connected to an USB1.1 host/hub or an USB2.0 host/hub. When

GL850 is connected to an USB1.1 host/hub, it works just like an USB1.1 hub; the upstream port will operate
in full-speed (FS) and the downstream port can operate in full-speed or low-speed (LS). When GL850 is
connected to an USB2.0 host/hub, it works as an USB2.0 hub; the upstream port will operate in high-speed
(HS) and the downstream port can operate in high-speed, full-speed, or low-speed. The bandwidths of high
speed, full speed, and low speed are 480 Mbps, 12 Mbps, and 1.5 Mbps respectively.

GL850 embeds an 8-bit RISC processor to manipulate the control/status registers and responds to the requests
from USB host. Firmware of GL850 will control its general purpose I/O (GPIO) to access the external
EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM.
GL850 responds to the host the default settings in the internal ROM if there exists no external EEPROM.
GL850 is designed for customers with much flexibility. Customers can easily design GL850 as 4-port self/bus
powered, individual/ganged mode, by setting the I/O pins of GL850 (Ref. to Chapter 5). The more
complicated settings such as PID, VID, and number of downstream ports settings are easily achieved by
programming the external EEPROM.

TT (transaction translator) is the main traffic control engine in an USB2.0 hub to handle the unbalanced traffic
speed between the upstream port and the downstream ports. GL850 adopts single TT architecture, which
shares the same TT buffer for all downstream devices.

Each downstream port of GL850 supports two-color (green/amber) status LEDs to indicate normal/abnormal
status. The downstream ports of GL850 can be configured as individual mode or gang mode (4 ports as a
group) for power management. Gang mode is very helpful for cost consideration, since we can use one
poly-fuse, but not expensive power switch chips, to detect over current.

GL850 passes the current requirement (< 2.5mA) for bus-power mode when being suspended. The current
consumption is smaller than 100mA for the GL850 silicon itself. The above requirements are necessary for a
4-port bus power hub. Under adequate PCB designing, GL850 provide a good choice for customers as a 4-port
bus powered hub. Besides, GL850 can switch automatically between self-power mode and bus-power mode
without re-plugging into the PC host. The slew rate control circuits and the power fail detection circuits inside
this chip give better ESD and EMI abilities to GL850.

GL850 is designed mainly for stand-alone hub. It can also be integrated into PC motherboard or any other
compound devices to support USB hub function.

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 9

GL850 USB 2.0 4-Port HUB Controller

CHAPTER 2 FEATURES

Compliant to USB specification Revision 2.0

•

− 4 downstream ports

− Upstream port supports both high-speed (HS) and full-speed (FS) traffic

− Downstream ports support HS, FS, and low-speed (LS) traffic

− 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data

payload)

− Backward compatible to USB specification Revision 1.1

• On-chip 8-bit micro-processor

− RISC-like architecture

− USB optimized instruction set

− Dual cycle instruction execution

− Performance: 6 MIPS @ 12MHz

− With 64-byte RAM and 2K internal ROM

− Support customized PID, VID by reading external EEPROM

− Support downstream port configuration by reading external EEPROM

• Single Transaction Translator (TT) architecture

− Single TT shares the same TT control logics for all downstream port devices. This is the most cost

effective solution for TT

• Each downstream port supports two-color status indicator, with automatic and manual modes compliant to

USB specification Revision 2.0

• Support both individual and gang modes of power management and over-current detection for

downstream ports

• Conform to bus power requirements

• Automatic switching between self-powered and bus-powered modes

• Integrated USB2.0 transceiver

• 0.35um CMOS technology

• PLL embedded with external 12 MHz crystal

• Operate on 3.3 Volts

• Improved output drivers with slew-rate control for EMI reduction

• Internal power-fail detection for ESD recovery

• 64-pin LQFP package

• Applications:

− Stand-alone USB hub

− PC motherboard USB hub, Ducking of notebook

− Any compound device to support USB HUB function

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 10

GL850 USB 2.0 4-Port HUB Controller

CHAPTER 3 PIN ASSIGNMENT

3.1 Pinouts

PWREN3#42OVCUR3#41PWREN4#40OVCUR4#39TEST38RESET#37DVDD36DGND35AMBER434GREEN433DP4

GREEN3

AMBER3

DGND

DVDD

GREEN2

43

44

45

46

47

48

AMBER2 49

PSELF 50

DGND 51

DVDD 52

PGANG/SUSPND 53

OVCUR2# 54

PWREN2# 55

OVCUR1# 56 25

PWREN1# 57

DGND 58

DVDD 59

GREEN1 60

AMBER1 61

AGND 62

AVDD 63

AVDD 64

3

2

1

GL850

LQFP - 64

6

7

5

4

8

9

10

11

12

13

14

32

DPH4

31

DMH4

30

DM4

29

AGND

28

AVDD

27

DP3

26

DPH3

DMH3

24

DM3

23

AGND

22

AVDD

21

XTAL2

20

XTAL1

19

AGND

18

AVDD

17

RREF

15

16

AGND

DMF0

DMH0

DPH0

DPF0

RPU

DM1

DMH1

DPH1

DP1

AVDD

AGND

DM2

DMH2

DPH2

DP2

Figure 3.1 - Pinout Diagram

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 11

GL850 USB 2.0 4-Port HUB Controller

3.2 Pin List

Table 3.1 - Pin List

Pin# Pin Name Type Pin# Pin Name Typ e Pin# Pin Name Typ e Pin# Pin Name Ty pe

1 AGND P 17 RREF B 33 DP4 B 49 AMBER2 O

2 DMF0 B 18 AVDD P 34 GREEN4 B 50 PSELF I

3 DMH0 B 19 AGND P 35 AMBER4 O 51 DGND P

4 DPH0 B 20 XTAL1 I 36 DGND P 52 DVDD P

5 DPF0 B 21 XTAL2 O 37

6 RPU B 22 AVDD P 38 RESET# I 54 OVCUR2# I

7 DM1 B 23 AGND P 39 TEST I 55 PWREN2# O

8 DMH1 B 24 DM3 B 40 OVCUR4# I 56 OVCUR1# I

9 DPH1 B 25 DMH3 P 41 PWREN4# O 57 PWREN1# O

DVDD P

53

PGANG/
SUSPND

B

10 DP1 B 26 DPH3 P 42 OVCUR3# I 58 DGND P

11 AVDD P 27 DP3 B 43 PWREN3# O 59 DVDD P

12 AGND P 28 AVDD P 44 GREEN3 B 60 GREEN1 O

13 DM2 B 29 AGND P 45 AMBER3 O 61 AMBER1 O

14 DMH2 B 30 DM4 B 46 DGND P 62 AGND P

15 DPH2 B 31 DMH4 B 47 DVDD P 63 AVDD P

16 DP2 B 32 DPH4 B 48 GREEN2 O 64 AVDD P

©2000-2003 Genesys Logic Inc.—All rights reserved. Page 12