GE MiCOM P40 Technical Manual

GE
Grid Solutions

MiCOM P40 Agile

P446SV

Technical Manual
Distance Protection IED

Hardware Version: P
Software Version: 80
Publication Reference: P446SV-TM-EN-1

Contents

Chapter 1 Introduction 1

1 Chapter Overview 3
2 Foreword 4

2.1 Target Audience 4

2.2 Typographical Conventions 4

2.3 Nomenclature 5

2.4 Compliance 5

3 Product Scope 6

3.1 Product Versions 6

3.2 Ordering Options 7

4 Features and Functions 8

4.1 Distance Protection Functions 8

4.2 Protection Functions 8

4.3 Control Functions 9

4.4 Measurement Functions 9

4.5 Communication Functions 9

5 Logic Diagrams 11
6 Functional Overview 13

Chapter 2 Safety Information 15

1 Chapter Overview 17
2 Health and Safety 18
3 Symbols 19
4 Installation, Commissioning and Servicing 20

4.1 Lifting Hazards 20

4.2 Electrical Hazards 20

4.3 UL/CSA/CUL Requirements 21

4.4 Fusing Requirements 21

4.5 Equipment Connections 22

4.6 Protection Class 1 Equipment Requirements 22

4.7 Pre-energisation Checklist 23

4.8 Peripheral Circuitry 23

4.9 Upgrading/Servicing 24

5 Decommissioning and Disposal 25
6 Regulatory Compliance 26

6.1 EMC Compliance: 2014/30/EU 26

6.2 LVD Compliance: 2014/35/EU 26

6.3 R&TTE Compliance: 2014/53/EU 26

6.4 UL/CUL Compliance 26

6.5 ATEX Compliance: 2014/34/EU 26

Chapter 3 Hardware Design 29

1 Chapter Overview 31
2 Hardware Architecture 32
3 Mechanical Implementation 33

3.1 Housing Variants 33

3.2 List of Boards 34

4 Front Panel 35

4.1 40TE Front Panel 35

4.1.1 Front Panel Compartments 35

4.1.2 Keypad 36

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4.1.3 Front Serial Port (SK1) 36

4.1.4 Front Parallel Port (SK2) 37

4.1.5 Fixed Function LEDs 37

4.1.6 Programable LEDs 37

5 Rear Panel 38
6 Boards and Modules 39

6.1 PCBs 39

6.2 Main Processor Board 40

6.3 Power Supply Board 41

6.3.1 Watchdog 43

6.3.2 Rear Serial Port 44

6.4 IEC61850-9-2LE Ethernet Board 45

6.5 Standard Output Relay Board 46

6.6 IRIG-B Board 47

6.7 Fibre Optic Board 48

6.8 Rear Communication Board 49

6.9 Ethernet Board 49

6.10 Redundant Ethernet Board 51

6.11 Coprocessor Board 53

6.11.1 Coprocessor board with 1PPS input 53

6.12 High Break Output Relay Board 54

Chapter 4 Software Design 57

1 Chapter Overview 59
2 Sofware Design Overview 60
3 System Level Software 61

3.1 Real Time Operating System 61

3.2 System Services Software 61

3.3 Self-Diagnostic Software 61

3.4 Startup Self-Testing 61

3.4.1 System Boot 61

3.4.2 System Level Software Initialisation 62

3.4.3 Platform Software Initialisation and Monitoring 62

3.5 Continuous Self-Testing 62

4 Platform Software 64

4.1 Record Logging 64

4.2 Settings Database 64

4.3 Interfaces 64

5 Protection and Control Functions 65

5.1 Acquisition of Samples 65

5.2 Frequency Tracking 65

5.3 Direct Use of Sample Values 65

5.4 Distance Protection 65

5.5 Fourier Signal Processing 66

5.6 Programmable Scheme Logic 67

5.7 Event Recording 67

5.8 Disturbance Recorder 68

5.9 Fault Locator 68

5.10 Function Key Interface 68

Chapter 5 Configuration 69

1 Chapter Overview 71
2 Settings Application Software 72
3 Using the HMI Panel 73

3.1 Navigating the HMI Panel 74

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3.2 Getting Started 74

3.3 Default Display 75

3.4 Default Display Navigation 76

3.5 Password Entry 77

3.6 Processing Alarms and Records 78

3.7 Menu Structure 78

3.8 Changing the Settings 79

3.9 Direct Access (The Hotkey menu) 80

3.9.1 Setting Group Selection Using Hotkeys 80

3.9.2 Control Inputs 81

3.9.3 Circuit Breaker Control 81

3.10 Function Keys 82

4 Line Parameters 84

4.1 Tripping Mode 84

4.1.1 CB Trip Conversion Logic Diagram 85

4.2 Residual Compensation 85

4.3 Mutual Compensation 86

5 Date and Time Configuration 88

5.1 Using an SNTP Signal 88

5.2 Using an IRIG-B Signal 88

5.3 Using an IEEE 1588 PTP Signal 88

5.4 Without a Timing Source Signal 89

5.5 Time Zone Compensation 89

5.6 Daylight Saving Time Compensation 90

6 Settings Group Selection 91

Chapter 6 Sampled Value Operation 93

1 Chapter Overview 95
2 Introduction To Sampled Values 96
3 Data Resampling 97
4 Sampled Value Alignment 98

4.1 Channel mappings for SAV Test, SAV Questionable, SAV Invalid 98

4.2 Data Quality 98

4.2.1 Impact of Data Quality on Protection Functions 99

4.3 Process Bus Performance 99

4.3.1 Sample Loss Data 100

4.4 VT Switching 100

4.5 Virtual Inputs and Outputs 101

4.5.1 P446, P546, P841B Virtual Inputs and Outputs DDBs 101

4.5.2 Virtual CT and VT Ratio Settings 101

4.6 IED Alarms 102

4.6.1 P446, P546, P841B Alarms 102

Chapter 7 Distance Protection 105

1 Chapter Overview 107
2 Introduction 108

2.1 Distance Protection Principle 108

2.2 Performance Influencing Factors 108

2.3 Impedance Calculation 109

2.4 Implementation with Comparators 109

2.5 Polarization of Distance Characteristics 109

3 Distance Measuring Zones Operating Principles 110

3.1 Mho Characteristics 111

3.1.1 Directional Mho Characteristic for Phase Faults 111

3.1.2 Offset Mho Characteristic for Phase Faults 111

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3.1.3 Directional Self-Polarized Mho Characteristic for Earth Faults 112

3.1.4 Offset Mho Characteristic for Earth Faults 114

3.1.5 Memory Polarization of Mho Characteristics 116

3.1.6 Dynamic Mho Expansion and Contraction 116

3.1.7 Cross Polarization of Mho Characteristics 119

3.1.8 Implementation of Mho Polarization 120

3.2 Quadrilateral Characteristic 121

3.2.1 Directional Quadrilaterals 122

3.2.2 Quadrilateral Characteristic for Phase Faults 126

3.2.3 Earth Fault Quadrilateral Characteristics 130

4 Phase and Earth Fault Distance Protection Implementation 139

4.1 Phase Fault Characteristics 139

4.2 Earth Fault Characteristics 139

4.3 Distance Protection Tripping Decision 139

4.4 Distance Protection Phase Selection 140

4.4.1 Faulted Phase Selection 140

4.5 Biased Neutral Current Detector 141

4.6 Distance Element Zone Settings 142

4.6.1 Directionalizing the Distance Elements 142

4.6.2 Advanced Distance Zone Settings 143

4.6.3 Distance Zone Sensitivities 143

4.7 Capacitor VT Applications 144

4.7.1 CVTs with Passive Suppression of Ferroresonance 144

4.7.2 CVTs with Active Suppression of Ferroresonance 144

4.8 Load Blinding 145

4.9 Cross Country Fault Protection 146

5 Delta Directional Element 147

5.1 Delta Directional Principle and Setup 147

5.2 Delta Directional Decision 148

6 Application Notes 150

6.1 Setting Mode Choice 150

6.2 Operating Characteristic Selection 150

6.2.1 Phase Characteristic 150

6.2.2 Earth Fault Characteristic 151

6.3 Zone Reach Setting Guidelines 151

6.3.1 Quadrilateral Resistive Reaches 152

6.4 Earth Fault Resistive Reaches and Tilting 152

6.4.1 Dynamic Tilting 153

6.4.2 Fixed Tilting 154

6.5 Phase Fault Zone Settings 154

6.6 Directional Element for Distance Protection 155

6.7 Filtering Setup 155

6.7.1 Distance Digital Filter 155

6.7.2 Setting up CVTs 155

6.8 Load Blinding Setup 156

6.9 Polarizing Setup 156

6.10 Delta Directional Element Setting Guidelines 157

6.10.1 Delta Thresholds 157

6.11 Distance Protection Worked Example 157

6.11.1 Line Impedance Calculation 158

6.11.2 Residual Compensation for Earth Fault Elements 159

6.11.3 Zone 1 Phase and Ground Reach Settings 159

6.11.4 Zone 2 Phase and Ground Reach Settings 159

6.11.5 Zone 3 Phase and Ground Reach Settings 160

6.11.6 Zone 3 Reverse Reach Settings 160

6.11.7 Zone 4 Reverse Reach Settings 160

6.11.8 Load Avoidance 161

6.11.9 Quadrilateral Resistive Reach Settings 161

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6.12 Teed Feeder Applications 162

Chapter 8 Carrier Aided Schemes 165

1 Chapter Overview 167
2 Introduction 168
3 Carrier Aided Schemes Implementation 169

3.1 Carrier Aided Scheme Types 169

3.2 Default Carrier Aided Schemes 170

4 Aided Distance Scheme Logic 171

4.1 Permissive Underreach Scheme 171

4.2 Permissive Over-reach Scheme 172

4.2.1 Permissive Overreach Trip Reinforcement 174

4.2.2 Permissive Overreach Weak Infeed Features 175

4.3 Permissive Scheme Loss Of Guard 175

4.4 Current Reversal Guard Logic 176

4.5 Aided Distance Blocking Schemes 177

4.6 Aided Distance Unblocking Schemes 178

4.7 Aided Distance Logic Diagrams 180

4.7.1 Aided Distance Send Logic 180

4.7.2 Carrier Aided Schemes Receive Logic 180

4.7.3 Aided Distance Tripping Logic 181

4.7.4 PUR Aided Tripping logic 181

4.7.5 POR Aided Tripping logic 182

4.7.6 Aided Scheme Blocking 1 Tripping logic 183

4.7.7 Aided Scheme Blocking 2 Tripping logic 183

5 Aided DEF Scheme Logic 184

5.1 Aided DEF Introduction 184

5.2 Implementation 184

5.3 Aided DEF Polarization 184

5.3.1 Zero Sequence Polarizing 185

5.3.2 Negative Sequence Polarizing 186

5.4 Aided DEF Setting Guidelines 187

5.5 Aided DEF POR Scheme 188

5.6 Aided DEF Blocking Scheme 189

5.7 Aided DEF Logic Diagrams 190

5.7.1 DEF Directional Signals 190

5.7.2 Aided DEF Send Logic 191

5.7.3 Carrier Aided Schemes Receive Logic 191

5.7.4 Aided DEF Tripping Logic 192

5.7.5 POR Aided Tripping logic 193

5.7.6 Aided Scheme Blocking 1 Tripping logic 194

5.7.7 Aided Scheme Blocking 2 Tripping logic 194

6 Aided Delta Scheme Logic 195

6.1 Aided Delta POR Scheme 195

6.2 Aided Delta Blocking Scheme 196

6.3 Aided Delta Logic Diagrams 198

6.3.1 Aided Delta Send Logic 198

6.3.2 Carrier Aided Schemes Receive Logic 198

6.3.3 Aided Delta Tripping Logic 199

6.3.4 POR Aided Tripping logic 200

6.3.5 Aided Scheme Blocking 1 Tripping logic 201

6.3.6 Aided Scheme Blocking 2 Tripping logic 201

7 Application Notes 202

7.1 Aided Distance PUR Scheme 202

7.2 Aided Distance POR Scheme 202

7.3 Aided Distance Blocking Scheme 202

7.4 Aided DEF POR Scheme 203

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7.5 Aided DEF Blocking Scheme 203

7.6 Aided Delta POR Scheme 203

7.7 Aided Delta Blocking Scheme 203

7.8 Teed Feeder Applications 204

7.8.1 POR Schemes for Teed Feeders 205

7.8.2 PUR Schemes for Teed Feeders 205

7.8.3 Blocking Schemes for Teed Feeders 206

Chapter 9 Non-Aided Schemes 209

1 Chapter Overview 211
2 Non-Aided Schemes 212
3 Basic Schemes 213

3.1 Basic Scheme Modes 213

3.2 Basic Scheme Setting 215

4 Trip On Close Schemes 217

4.1 Switch On To Fault (SOTF) 218

4.1.1 Switch Onto Fault Mode 218

4.1.2 SOTF Tripping 219

4.1.3 SOTF Tripping with CNV 219

4.2 Trip On Reclose (TOR) 219

4.2.1 Trip On Reclose Mode 220

4.2.2 TOR Tripping Logic for Appropriate Zones 220

4.2.3 TOR Tripping Logic with CNV 220

4.3 Polarisation during Circuit Engergisation 220

5 Zone1 Extension Scheme 221
6 Loss of Load Scheme 222

Chapter 10 Power Swing Functions 225

1 Chapter Overview 227
2 Introduction to Power Swing Blocking 228
3 Power Swing Blocking 230

3.1 Power Swing Detection 230

3.1.1 Settings-Free Power Swing Detection 230

3.1.2 Slow Power Swing Detection 232

3.2 Detection of a Fault During a Power Swing 234

3.3 Power Swing Blocking Configuration 234

3.4 Power Swing Load Blinding Boundary 235

3.5 Power Swing Blocking Logic 236

3.6 Power Swing Blocking Setting Guidelines 237

3.6.1 Setting the Resistive Limits 238

3.6.2 Setting the Reactive Limits 238

3.6.3 PSB Timer Setting Guidelines 239

4 Out of Step Protection 241

4.1 Out of Step Detection 241

4.2 Out of Step Protection Operataing Principle 242

4.3 Out of Step Logic Diagram 243

4.4 OST Application Notes 243

4.4.1 Setting the OST Mode 243

Chapter 11 Autoreclose 249

1 Chapter Overview 251
2 Introduction to Autoreclose 252
3 Autoreclose Implementation 253

3.1 Autoreclose Logic Inputs from External Sources 254

3.1.1 Circuit Breaker Healthy Input 254

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3.1.2 Inhibit Autoreclose Input 254

3.1.3 Block Autoreclose Input 254

3.1.4 Reset Lockout Input 255

3.1.5 Pole Discrepancy Input 255

3.1.6 External Trip Indication 255

3.2 Autoreclose Logic Inputs 255

3.2.1 Trip Initiation Signals 255

3.2.2 Circuit Breaker Status Inputs 255

3.2.3 System Check Signals 255

3.3 Autoreclose Logic Outputs 255

3.4 Autoreclose Operating Sequence 256

3.4.1 AR Timing Sequence - Transient Fault 256

3.4.2 AR Timing Sequence - Evolving/Permanent Fault 256

3.4.3 AR Timing Sequence - Evolving/Permanent Fault Single-phase 257

3.4.4 AR Timing Sequence - Transient Fault Dual CB 257

3.4.5 AR Timing Sequence - Evolving/Permanent Fault Dual CB 258

3.4.6 AR Timing Sequence - Persistent Fault 259

4 Autoreclose System Map 261

4.1 Autoreclose System Map Diagrams 263

4.2 Autoreclose Internal Signals 272

4.3 Autoreclose DDB Signals 277

5 Logic Modules 289

5.1 Circuit Breaker Status Monitor 289

5.1.1 CB State Monitor 290

5.2 Circuit Breaker Open Logic 290

5.2.1 Circuit Breaker Open Logic Diagram 291

5.3 Circuit Breaker in Service Logic 291

5.3.1 Circuit Breaker in Service Logic Diagram 292

5.4 Autoreclose Enable Logic 292

5.4.1 Autoreclose Enable Logic Diagram 292

5.5 Autoreclose Leader/Follower 292

5.5.1 Leader/Follower CB Selection Logic Diagram 293

5.5.2 Leader Follower Logic Diagram 294

5.6 Autoreclose Modes 295

5.6.1 Single-Phase and Three-Phase Autoreclose 295

5.6.2 Autoreclose Modes Enable Logic Diagram 296

5.7 AR Force Three-Phase Trip Logic 297

5.7.1 Force Three-Phase Trip Logic Diagram 297

5.8 Autoreclose Initiation Logic 298

5.8.1 Autoreclose Initiation Logic Diagram 299

5.8.2 Autoreclose Trip Test Logic Diagram 299

5.8.3 External Trip Logic Diagram for CB1 300

5.8.4 External Trip Logic Diagram for CB2 301

5.8.5 Protection Reoperation and Evolving Fault Logic Diagram 302

5.8.6 Fault Memory Logic Diagram 302

5.9 Autoreclose In Progress 302

5.9.1 Autoreclose In Progress Logic Diagram for CB1 303

5.9.2 Autoreclose In Progress Logic Diagram for CB2 304

5.10 Sequence Counter 304

5.10.1 Autoreclose Sequence Counter Logic Diagram 305

5.11 Autoreclose Cycle Selection 305

5.11.1 Single Phase Autoreclose Cycle Selection Logic Diagram 306

5.11.2 3-phase Autoreclose Cycle Selection 307

5.12 Dead Time Control 307

5.12.1 Dead Time Start Enable Logic Diagram 308

5.12.2 Single-phase Leader Dead Time Logic Diagram 309

5.12.3 3-phase Leader Dead Time Logic Diagram 310

5.12.4 Follower Enable Logic Diagram 311

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5.12.5 Single-phase Follower Timing Logic Diagram 312

5.12.6 Three-phase Follower Timing Logic Diagram 313

5.13 Circuit Breaker Autoclose 313

5.13.1 Circuit Breaker Autoclose Logic Diagram 314

5.14 Reclaim Time 314

5.14.1 Prepare Reclaim Initiation Logic Diagram 315

5.14.2 Reclaim Time Logic Diagram 316

5.14.3 Succesful Autoreclose Signals Logic Diagram 317

5.14.4 Autoreclose Reset Successful Indication Logic Diagram 318

5.15 CB Healthy and System Check Timers 318

5.15.1 CB Healthy and System Check Timers Logic Diagram 319

5.16 Autoreclose Shot Counters 319

5.16.1 Autoreclose Shot Counters Logic Diagram 321

5.17 Circuit Breaker Control 322

5.17.1 CB Control Logic Diagram 322

5.18 Circuit Breaker Trip Time Monitoring 323

5.18.1 CB Trip Time Monitoring Logic Diagram 324

5.19 Autoreclose Lockout 325

5.19.1 CB Lockout Logic Diagram 326

5.20 Reset Circuit Breaker Lockout 327

5.20.1 Reset CB Lockout Logic Diagram 329

5.21 Pole Discrepancy 329

5.21.1 Pole Discrepancy Logic Diagram 330

5.22 Circuit Breaker Trip Conversion 330

5.22.1 CB Trip Conversion Logic Diagram 331

5.23 Monitor Checks for CB Closure 331

5.23.1 Voltage Monitor for CB Closure 332

5.23.2 Check Synchronisation Monitor for CB Closure 333

5.24 Synchronisation Checks for CB Closure 334

5.24.1 Three-phase Autoreclose Leader Check Logic Diagram 336

5.24.2 Three-phase Autoreclose Follower Check Logic Diagram 338

5.24.3 CB Manual Close System Check Logic Diagram 340

6 Setting Guidelines 341

6.1 De-ionising Time Guidance 341

6.2 Dead Timer Setting Guidelines 341

6.2.1 Example Dead Time Calculation 341

6.3 Reclaim Time Setting Guidelines 342

6.4 Autoreclose Shot Counters 342

Chapter 12 CB Fail Protection 345

1 Chapter Overview 347
2 Circuit Breaker Fail Protection 348
3 Circuit Breaker Fail Implementation 349

3.1 Circuit Breaker Fail Timers 349

3.2 Zero Crossing Detection 349

4 Circuit Breaker Fail Logic 351

4.1 Circuit Breaker Fail Logic - Part 1 351

4.2 Circuit Breaker Fail Logic - Part 2 352

4.3 Circuit Breaker Fail Logic - Part 3 353

4.4 Circuit Breaker Fail Logic - Part 4 354

5 Application Notes 355

5.1 Reset Mechanisms for CB Fail Timers 355

5.2 Setting Guidelines (CB fail Timer) 355

5.3 Setting Guidelines (Undercurrent) 356

Chapter 13 Current Protection Functions 357

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1 Chapter Overview 359
2 Phase Fault Overcurrent Protection 360

2.1 POC Implementation 360

2.2 Directional Element 360

2.3 POC Logic 362

3 Negative Sequence Overcurrent Protection 363

3.1 Negative Sequence Overcurrent Protection Implementation 363

3.2 Directional Element 363

3.3 NPSOC Logic 364

3.4 Application Notes 364

3.4.1 Setting Guidelines (Current Threshold) 364

3.4.2 Setting Guidelines (Time Delay) 364

3.4.3 Setting Guidelines (Directional element) 364

4 Earth Fault Protection 366

4.1 Earth Fault Protection Implementation 366

4.2 IDG Curve 366

4.3 Directional Element 367

4.3.1 Residual Voltage Polarisation 367

4.3.2 Negative Sequence Polarisation 368

4.4 Earth Fault Protection Logic 369

4.5 Application Notes 369

4.5.1 Residual Voltage Polarisation Setting Guidelines 369

4.5.2 Setting Guidelines (Directional Element) 369

5 Sensitive Earth Fault Protection 371

5.1 SEF Protection Implementation 371

5.2 EPATR B Curve 371

5.3 Sensitive Earth Fault Protection Logic 372

5.4 Application Notes 373

5.4.1 Insulated Systems 373

5.4.2 Setting Guidelines (Insulated Systems) 374

6 High Impedance REF 376

6.1 High Impedance REF Principle 376

7 Thermal Overload Protection 378

7.1 Single Time Constant Characteristic 378

7.2 Dual Time Constant Characteristic 378

7.3 Thermal Overload Protection Implementation 379

7.4 Thermal Overload Protection Logic 379

7.5 Application Notes 379

7.5.1 Setting Guidelines for Dual Time Constant Characteristic 379

7.5.2 Setting Guidelines for Single Time Constant Characteristic 381

8 Broken Conductor Protection 382

8.1 Broken Conductor Protection Implementation 382

8.2 Broken Conductor Protection Logic 382

8.3 Application Notes 382

8.3.1 Setting Guidelines 382

Chapter 14 Voltage Protection Functions 385

1 Chapter Overview 387
2 Undervoltage Protection 388

2.1 Undervoltage Protection Implementation 388

2.2 Undervoltage Protection Logic 389

2.3 Application Notes 390

2.3.1 Undervoltage Setting Guidelines 390

3 Overvoltage Protection 391

3.1 Overvoltage Protection Implementation 391

3.2 Overvoltage Protection Logic 392

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3.3 Application Notes 393

3.3.1 Overvoltage Setting Guidelines 393

4 Compensated Overvoltage 394
5 Residual Overvoltage Protection 395

5.1 Residual Overvoltage Protection Implementation 395

5.2 Residual Overvoltage Logic 396

5.3 Application Notes 396

5.3.1 Calculation for Solidly Earthed Systems 396

5.3.2 Calculation for Impedance Earthed Systems 397

5.3.3 Setting Guidelines 398

Chapter 15 Frequency Protection Functions 399

1 Chapter Overview 401
2 Frequency Protection 402

2.1 Underfrequency Protection 402

2.1.1 Underfrequency Protection Implementation 402

2.1.2 Underfrequency Protection logic 403

2.1.3 Application Notes 403

2.2 Overfrequency Protection 403

2.2.1 Overfrequency Protection Implementation 403

2.2.2 Overfrequency Protection logic 404

2.2.3 Application Notes 404

3 Independent R.O.C.O.F Protection 405

3.1 Indepenent R.O.C.O.F Protection Implementation 405

3.2 Independent R.O.C.O.F Protection Logic 405

Chapter 16 Monitoring and Control 407

1 Chapter Overview 409
2 Event Records 410

2.1 Event Types 410

2.1.1 Opto-input Events 411

2.1.2 Contact Events 411

2.1.3 Alarm Events 411

2.1.4 Fault Record Events 412

2.1.5 Maintenance Events 412

2.1.6 Protection Events 412

2.1.7 Security Events 413

2.1.8 Platform Events 413

3 Disturbance Recorder 414
4 Measurements 415

4.1 Measured Quantities 415

4.2 Measurement Setup 415

4.3 Fault Locator 415

4.4 Opto-input Time Stamping 415

5 CB Condition Monitoring 416

5.1 Broken Current Accumulator 417

5.2 CB Trip Counter 418

5.3 CB Operating Time Accumulator 419

5.4 Excessive Fault Frequency Counter 420

5.5 Reset Lockout Alarm 421

5.6 CB Condition Monitoring Logic 422

5.7 Reset Circuit Breaker Lockout 423

5.7.1 Reset CB Lockout Logic Diagram 425

5.8 Application Notes 425

5.8.1 Setting the Thresholds for the Total Broken Current 425

5.8.2 Setting the thresholds for the Number of Operations 426

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5.8.3 Setting the thresholds for the Operating Time 426

5.8.4 Setting the Thresholds for Excesssive Fault Frequency 426

6 CB State Monitoring 427

6.1 CB State Monitor 428

7 Circuit Breaker Control 429

7.1 CB Control using the IED Menu 429

7.2 CB Control using the Hotkeys 430

7.3 CB Control using the Function Keys 430

7.4 CB Control using the Opto-inputs 431

7.5 Remote CB Control 431

7.6 CB Healthy Check 432

7.7 Synchronisation Check 432

7.8 CB Control AR Implications 432

7.9 CB Control Logic Diagram 433

8 Pole Dead Function 435

8.1 Pole Dead Logic 435

9 System Checks 436

9.1 System Checks Implementation 436

9.1.1 VT Connections 436

9.1.2 Voltage Monitoring 437

9.1.3 Check Synchronisation 437

9.1.4 Check Syncronisation Vector Diagram 437

9.2 Voltage Monitor for CB Closure 439

9.3 Check Synchronisation Monitor for CB Closure 440

9.4 System Check PSL 442

9.5 Application Notes 442

9.5.1 Predictive Closure of Circuit Breakers 442

9.5.2 Voltage and Phase Angle Correction 442

Chapter 17 Supervision 445

1 Chapter Overview 447
2 Voltage Transformer Supervision 448

2.1 Loss of One or Two Phase Voltages 448

2.2 Loss of all Three Phase Voltages 448

2.3 Absence of all Three Phase Voltages on Line Energisation 448

2.4 VTS Implementation 449

2.5 VTS Logic 450

3 Current Transformer Supervision 452

3.1 CTS Implementation 452

3.2 Standard CTS Logic 453

3.3 CTS Blocking 453

3.4 Application Notes 453

3.4.1 Setting Guidelines 453

4 Trip Circuit Supervision 454

4.1 Trip Circuit Supervision Scheme 1 454

4.1.1 Resistor Values 454

4.1.2 PSL for TCS Scheme 1 455

4.2 Trip Circuit Supervision Scheme 2 455

4.2.1 Resistor Values 456

4.2.2 PSL for TCS Scheme 2 456

4.3 Trip Circuit Supervision Scheme 3 456

4.3.1 Resistor Values 457

4.3.2 PSL for TCS Scheme 3 457

Chapter 18 Digital I/O and PSL Configuration 459

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1 Chapter Overview 461
2 Configuring Digital Inputs and Outputs 462
3 Scheme Logic 463

3.1 PSL Editor 464

3.2 PSL Schemes 464

3.3 PSL Scheme Version Control 464

4 Configuring the Opto-Inputs 465
5 Assigning the Output Relays 466
6 Fixed Function LEDs 467

6.1 Trip LED Logic 467

7 Configuring Programmable LEDs 468
8 Function Keys 470
9 Control Inputs 471

Chapter 19 Fibre Teleprotection 473

1 Chapter Overview 475
2 Protection Signalling Introduction 476

2.1 Unit Protection Schemes 476

2.2 Teleprotection Commands 476

2.3 Transmission Media and Interference 477

3 Fibre Teleprotection Implementation 478

3.1 Setting up the IM64 Scheme 478

3.1.1 Fibre Teleprotection Scheme Terminal Addressing 479

3.1.2 Setting up IM64 480

3.1.3 Two-Terminal IM64 Operation 480

3.1.4 Dual Redundant Two-Terminal IM64 Operation 480

3.1.5 Three-Terminal IM64 Operation 480

3.1.6 Physical Connection 481

4 IM64 Logic 485
5 Application Notes 487

5.1 Alarm Management 487

5.2 Alarm Logic 487

5.3 Two-ended Scheme Extended Supervision 488

5.4 Three-ended Scheme Extended Supervision 488

Chapter 20 Electrical Teleprotection 491

1 Chapter Overview 493
2 Introduction 494
3 Teleprotection Scheme Principles 495

3.1 Direct Tripping 495

3.2 Permissive Tripping 495

4 Implementation 496
5 Configuration 497
6 Connecting to Electrical InterMiCOM 499

6.1 Short Distance 499

6.2 Long Distance 499

7 Application Notes 500

Chapter 21 Communications 503

1 Chapter Overview 505
2 Communication Interfaces 506
3 Serial Communication 507

3.1 EIA(RS)232 Bus 507

3.2 EIA(RS)485 Bus 507

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3.2.1 EIA(RS)485 Biasing Requirements 508

3.3 K-Bus 508

4 Standard Ethernet Communication 510

4.1 Hot-Standby Ethernet Failover 510

5 Redundant Ethernet Communication 511

5.1 Supported Protocols 511

5.2 Parallel Redundancy Protocol 512

5.3 High-Availability Seamless Redundancy (HSR) 513

5.3.1 HSR Multicast Topology 513

5.3.2 HSR Unicast Topology 513

5.3.3 HSR Application in the Substation 514

5.4 Rapid Spanning Tree Protocol 515

5.5 Self Healing Protocol 516

5.6 Dual Homing Protocol 517

5.7 Configuring IP Addresses 519

5.7.1 Configuring the IED IP Address 520

5.7.2 Configuring the REB IP Address 520

5.8 PRP/HSR Configurator 522

5.8.1 Connecting the IED to a PC 523

5.8.2 Installing the Configurator 523

5.8.3 Starting the Configurator 523

5.8.4 PRP/HSR Device Identification 524

5.8.5 Selecting the Device Mode 524

5.8.6 PRP/HSR IP Address Configuration 524

5.8.7 SNTP IP Address Configuration 524

5.8.8 Check for Connected Equipment 524

5.8.9 PRP Configuration 524

5.8.10 HSR Configuration 525

5.8.11 Filtering Database 525

5.8.12 End of Session 526

5.9 RSTP Configurator 526

5.9.1 Connecting the IED to a PC 526

5.9.2 Installing the Configurator 527

5.9.3 Starting the Configurator 527

5.9.4 RSTP Device Identification 527

5.9.5 RSTP IP Address Configuration 528

5.9.6 SNTP IP Address Configuration 528

5.9.7 Check for Connected Equipment 528

5.9.8 RSTP Configuration 528

5.9.9 End of Session 529

5.10 Switch Manager 529

5.10.1 Installation 530

5.10.2 Setup 531

5.10.3 Network Setup 531

5.10.4 Bandwidth Used 531

5.10.5 Reset Counters 531

5.10.6 Check for Connected Equipment 531

5.10.7 Mirroring Function 532

5.10.8 Ports On/Off 532

5.10.9 VLAN 532

5.10.10 End of Session 532

6 Simple Network Management Protocol (SNMP) 533

6.1 SNMP Management Information Bases 533

6.2 Main Processor MIBS Structure 533

6.3 Redundant Ethernet Board MIB Structure 534

6.4 Accessing the MIB 538

6.5 Main Processor SNMP Configuration 538

7 Data Protocols 540

P446SV-TM-EN-1 xiii

Contents P446SV

7.1 Courier 540

7.1.1 Physical Connection and Link Layer 540

7.1.2 Courier Database 541

7.1.3 Settings Categories 541

7.1.4 Setting Changes 541

7.1.5 Event Extraction 541

7.1.6 Disturbance Record Extraction 543

7.1.7 Programmable Scheme Logic Settings 543

7.1.8 Time Synchronisation 543

7.1.9 Courier Configuration 544

7.2 IEC 60870-5-103 545

7.2.1 Physical Connection and Link Layer 545

7.2.2 Initialisation 546

7.2.3 Time Synchronisation 546

7.2.4 Spontaneous Events 546

7.2.5 General Interrogation (GI) 546

7.2.6 Cyclic Measurements 546

7.2.7 Commands 546

7.2.8 Test Mode 547

7.2.9 Disturbance Records 547

7.2.10 Command/Monitor Blocking 547

7.2.11 IEC 60870-5-103 Configuration 547

7.3 DNP 3.0 548

7.3.1 Physical Connection and Link Layer 548

7.3.2 Object 1 Binary Inputs 549

7.3.3 Object 10 Binary Outputs 549

7.3.4 Object 20 Binary Counters 550

7.3.5 Object 30 Analogue Input 550

7.3.6 Object 40 Analogue Output 551

7.3.7 Object 50 Time Synchronisation 551

7.3.8 DNP3 Device Profile 551

7.3.9 DNP3 Configuration 559

7.4 IEC 61850 560

7.4.1 Benefits of IEC 61850 561

7.4.2 IEC 61850 Interoperability 561

7.4.3 The IEC 61850 Data Model 561

7.4.4 IEC 61850 in MiCOM IEDs 562

7.4.5 IEC 61850 Data Model Implementation 563

7.4.6 IEC 61850 Communication Services Implementation 563

7.4.7 IEC 61850 Peer-to-peer (GOOSE) communications 563

7.4.8 Mapping GOOSE Messages to Virtual Inputs 563

7.4.9 Ethernet Functionality 564

7.4.10 IEC 61850 Configuration 564

7.4.11 IEC 61850 Edition 2 565

8 Read Only Mode 569

8.1 IEC 60870-5-103 Protocol Blocking 569

8.2 Courier Protocol Blocking 569

8.3 IEC 61850 Protocol Blocking 570

8.4 Read-Only Settings 570

8.5 Read-Only DDB Signals 570

9 Time Synchronisation 571

9.1 Demodulated IRIG-B 571

9.1.1 IRIG-B Implementation 571

9.2 SNTP 572

9.2.1 Loss of SNTP Server Signal Alarm 572

9.3 IEEE 1588 Precision time Protocol 572

9.3.1 Accuracy and Delay Calculation 572

9.3.2 PTP Domains 573

9.4 Time Synchronsiation using the Communication Protocols 573

xiv P446SV-TM-EN-1

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Chapter 22 Cyber-Security 575

1 Overview 577
2 The Need for Cyber-Security 578
3 Standards 579

3.1 NERC Compliance 579

3.1.1 CIP 002 580

3.1.2 CIP 003 580

3.1.3 CIP 004 580

3.1.4 CIP 005 580

3.1.5 CIP 006 580

3.1.6 CIP 007 581

3.1.7 CIP 008 581

3.1.8 CIP 009 581

3.2 IEEE 1686-2007 581

4 Cyber-Security Implementation 583

4.1 NERC-Compliant Display 583

4.2 Four-level Access 584

4.2.1 Blank Passwords 585

4.2.2 Password Rules 586

4.2.3 Access Level DDBs 586

4.3 Enhanced Password Security 586

4.3.1 Password Strengthening 586

4.3.2 Password Validation 587

4.3.3 Password Blocking 587

4.4 Password Recovery 588

4.4.1 Password Recovery 588

4.4.2 Password Encryption 589

4.5 Disabling Physical Ports 589

4.6 Disabling Logical Ports 589

4.7 Security Events Management 590

4.8 Logging Out 592

Chapter 23 Installation 593

1 Chapter Overview 595
2 Handling the Goods 596

2.1 Receipt of the Goods 596

2.2 Unpacking the Goods 596

2.3 Storing the Goods 596

2.4 Dismantling the Goods 596

3 Mounting the Device 597

3.1 Flush Panel Mounting 597

3.2 Rack Mounting 598

4 Cables and Connectors 600

4.1 Terminal Blocks 600

4.2 Power Supply Connections 601

4.3 Earth Connnection 601

4.4 Watchdog Connections 601

4.5 EIA(RS)485 and K-Bus Connections 601

4.6 IRIG-B Connection 602

4.7 Opto-input Connections 602

4.8 Output Relay Connections 602

4.9 Ethernet Metallic Connections 602

4.10 Ethernet Fibre Connections 602

4.11 RS232 connection 603

4.12 Download/Monitor Port 603

P446SV-TM-EN-1 xv

Contents P446SV

4.13 GPS Fibre Connection 603

4.14 Fibre Communication Connections 603

5 Case Dimensions 604

5.1 Case Dimensions 40TE 604

Chapter 24 Commissioning Instructions 605

1 Chapter Overview 607
2 General Guidelines 608
3 Commissioning Test Menu 609

3.1 Opto I/P Status Cell (Opto-input Status) 609

3.2 Relay O/P Status Cell (Relay Output Status) 609

3.3 Test Port Status Cell 609

3.4 Monitor Bit 1 to 8 Cells 609

3.5 Test Mode Cell 610

3.6 Test Pattern Cell 610

3.7 Contact Test Cell 610

3.8 Test LEDs Cell 610

3.9 Test Autoreclose Cell 610

3.10 Static Test Mode 611

3.11 Loopback Mode 611

3.12 IM64 Test Pattern 612

3.13 IM64 Test Mode 612

3.14 Red and Green LED Status Cells 612

3.15 Using a Monitor Port Test Box 612

4 Commissioning Equipment 613

4.1 Recommended Commissioning Equipment 613

4.2 Essential Commissioning Equipment 613

4.3 Advisory Test Equipment 614

5 Product Checks 615

5.1 Product Checks with the IED De-energised 615

5.1.1 Visual Inspection 616

5.1.2 Current Transformer Shorting Contacts 616

5.1.3 Insulation 616

5.1.4 External Wiring 616

5.1.5 Watchdog Contacts 617

5.1.6 Power Supply 617

5.2 Product Checks with the IED Energised 617

5.2.1 Watchdog Contacts 617

5.2.2 Test LCD 618

5.2.3 Date and Time 618

5.2.4 Test LEDs 619

5.2.5 Test Alarm and Out-of-Service LEDs 619

5.2.6 Test Trip LED 619

5.2.7 Test User-programmable LEDs 619

5.2.8 Test Opto-inputs 619

5.2.9 Test Output Relays 619

5.2.10 Test Serial Communication Port RP1 620

5.2.11 Test Serial Communication Port RP2 621

5.2.12 Test Ethernet Communication 621

5.3 Secondary Injection Tests 622

5.3.1 Test Current Inputs 622

5.3.2 Test Voltage Inputs 622

6 Electrical Intermicom Communication Loopback 624

6.1 Setting up the Loopback 624

6.2 Loopback Test 624

6.2.1 InterMicom Command Bits 625

6.2.2 InterMicom Channel Diagnostics 625

xvi P446SV-TM-EN-1

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6.2.3 Simulating a Channel Failure 625

7 Intermicom 64 Communication 626

7.1 Checking the Interface 626

7.2 Setting up the Loopback 627

7.3 Loopback Test 627

8 Setting Checks 628

8.1 Apply Application-specific Settings 628

8.1.1 Transferring Settings from a Settings File 628

8.1.2 Entering settings using the HMI 628

9 IEC 61850 Edition 2 Testing 630

9.1 Using IEC 61850 Edition 2 Test Modes 630

9.1.1 IED Test Mode Behaviour 630

9.1.2 Sampled Value Test Mode Behaviour 630

9.2 Simulated Input Behaviour 631

9.3 Testing Examples 631

9.3.1 Test Procedure for Real Values 632

9.3.2 Test Procedure for Simulated Values - No Plant 632

9.3.3 Test Procedure for Simulated Values - With Plant 633

9.3.4 Contact Test 634

10 Distance Protection 635

10.1 Single-ended Testing 635

10.1.1 Preliminaries 635

10.1.2 Zone 1 Reach Check 635

10.1.3 Zone 2 Reach Check 636

10.1.4 Zone 3 Reach Check 636

10.1.5 Zone 4 Reach Check 636

10.1.6 Zone P Reach Check 636

10.1.7 Resistive Reach 637

10.1.8 Load Blinder 637

10.2 Operation and Contact Assignment 637

10.2.1 Phase A 637

10.2.2 Phase B 637

10.2.3 Phase C 637

10.2.4 Time Delay Settings 638

10.3 Scheme Testing 638

10.3.1 Scheme Trip Test for Zone 1 Extension 639

10.3.2 Scheme Trip Tests for Permissive Schemes 639

10.3.3 Scheme Trip Tests for Blocking Scheme 639

10.3.4 Signal Send Test for Permissive Schemes 640

10.3.5 Signal Send Test for Blocking Scheme 640

10.3.6 Scheme Timer Settings 640

11 Delta Directional Comparison 641

11.1 Single-ended Testing 641

11.1.1 Preliminaries 641

11.1.2 Single-ended Injection Test 641

11.1.3 Forward Fault Preparation 641

11.2 Operation and Contact Assignment 642

11.2.1 Phase A 642

11.2.2 Phase B 642

11.2.3 Phase C 642

11.3 Delta Protection Scheme Testing 643

11.3.1 Signal Send Test for Permissive Schemes 643

11.3.2 Signal Send Test for Blocking Schemes 643

12 DEF Aided Schemes 644

12.1 Earth Current Pilot Scheme 644

12.1.1 Preliminaries 644

12.1.2 Perform the Test 644

12.1.3 Forward Fault Trip Test 645

P446SV-TM-EN-1 xvii

Contents P446SV

12.2 Scheme Testing 645

12.2.1 Signal Send Test for Permissive Schemes 645

12.2.2 Signal Send Test for Blocking Schemes 645

13 Out of Step Protection 646

13.1 OST Setting 646

13.2 Predictive OST Setting 647

13.3 Predictive and OST Setting 647

13.4 OST Timer Test 647

14 Protection Timing Checks 648

14.1 Overcurrent Check 648

14.2 Connecting the Test Circuit 648

14.3 Performing the Test 648

14.4 Check the Operating Time 648

15 System Check and Check Synchronism 650

15.1 Check Synchronism Pass 650

15.2 Check Synchronism Fail 650

16 Check Trip and Autoreclose Cycle 651
17 End-to-End Communication Tests 652

17.1 Remove Local Loopbacks 652

17.1.1 Restoring Direct Fibre Connections 652

17.1.2 Restoring C37.94 Fibre Connections 653

17.1.3 Communications using P59x Interface Units 653

17.2 Remove Remote Loopbacks 653

17.3 Verify Communication between IEDs 653

18 End-to-End Scheme Tests 655

18.1 Aided Scheme 1 655

18.1.1 Preparation at Remote End 655

18.1.2 Performing the Test 655

18.1.3 Channel Check in the Opposite Direction 655

18.2 Aided Scheme 2 655

19 Onload Checks 657

19.1 Confirm Current Connections 657

19.2 Confirm Voltage Connections 657

19.3 On-load Directional Test 658

20 Final Checks 659
21 Commmissioning the P59x 660

21.1 Visual Inspection 660

21.2 Insulation 660

21.3 External Wiring 660

21.4 P59x Auxiliary Supply 660

21.5 P59x LEDs 661

21.6 Received Optical Signal Level 661

21.7 Optical Transmitter Level 661

21.8 Loopback Test 662

Chapter 25 Maintenance and Troubleshooting 663

1 Chapter Overview 665
2 Maintenance 666

2.1 Maintenance Checks 666

2.1.1 Alarms 666

2.1.2 Opto-isolators 666

2.1.3 Output Relays 666

2.1.4 Measurement Accuracy 666

2.2 Replacing the Device 667

2.3 Repairing the Device 668

2.4 Removing the front panel 668

xviii P446SV-TM-EN-1

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2.5 Replacing PCBs 669

2.5.1 Replacing the main processor board 669

2.5.2 Replacement of communications boards 670

2.5.3 Replacement of the input module 671

2.5.4 Replacement of the power supply board 671

2.5.5 Replacement of the I/O boards 672

2.6 Recalibration 672

2.7 Changing the battery 672

2.7.1 Post Modification Tests 673

2.7.2 Battery Disposal 673

2.8 Cleaning 673

3 Troubleshooting 674

3.1 Self-Diagnostic Software 674

3.2 Power-up Errors 674

3.3 Error Message or Code on Power-up 674

3.4 Out of Service LED on at power-up 675

3.5 Error Code during Operation 676

3.5.1 Backup Battery 676

3.6 Mal-operation during testing 676

3.6.1 Failure of Output Contacts 676

3.6.2 Failure of Opto-inputs 676

3.6.3 Incorrect Analogue Signals 677

3.7 Coprocessor board failures 677

3.7.1 Signalling failure alarm (on its own) 677

3.7.2 C diff failure alarm (on its own) 677

3.7.3 Signalling failure and C diff failure alarms together 677

3.7.4 Incompatible IED 677

3.7.5 Comms changed 677

3.7.6 IEEE C37.94 fail 678

3.8 PSL Editor Troubleshooting 678

3.8.1 Diagram Reconstruction 678

3.8.2 PSL Version Check 678

3.9 Repair and Modification Procedure 678

Chapter 26 Technical Specifications 681

1 Chapter Overview 683
2 Interfaces 684

2.1 Front Serial Port 684

2.2 Download/Monitor Port 684

2.3 Rear Serial Port 1 684

2.4 Fibre Rear Serial Port 1 684

2.5 Rear Serial Port 2 685

2.6 Optional Rear Serial Port (SK5) 685

2.7 IRIG-B (Demodulated) 685

2.8 IRIG-B (Modulated) 685

2.9 Rear Ethernet Port Copper 686

2.10 Rear Ethernet Port Fibre 686

2.10.1 100 Base FX Receiver Characteristics 686

2.10.2 100 Base FX Transmitter Characteristics 687

2.11 1 PPS Port 687

2.12 Fibre Teleprotection Interface 687

3 Protection Functions 688

3.1 Distance Protection 688

3.2 Power Swing Blocking 688

3.3 Out Of Step Protection 689

3.4 Fibre Teleprotection Transfer Times 689

3.5 Autoreclose and Check Synychronism 689

P446SV-TM-EN-1 xix

Contents P446SV

3.6 Phase Overcurrent Protection 689

3.6.1 Transient Overreach and Overshoot 690

3.6.2 Phase Overcurrent Directional Parameters 690

3.7 Earth Fault Protection 690

3.7.1 Earth Fault Directional Parameters 690

3.8 Sensitive Earth Fault Protection 691

3.8.1 Sensitive Earth Fault Protection Directional Element 691

3.9 High Impedance Restricted Earth Fault Protection 691

3.10 Negative Sequence Overcurrent Protection 691

3.10.1 NPSOC Directional Parameters 692

3.11 Circuit Breaker Fail and Undercurrent Protection 692

3.12 Broken Conductor Protection 692

3.13 Thermal Overload Protection 692

4 Monitoring, Control and Supervision 693

4.1 Voltage Transformer Supervision 693

4.2 Standard Current Transformer Supervision 693

4.3 Differential Current Transformer Supervision 693

4.4 CB State and Condition Monitoring 693

4.5 PSL Timers 694

5 Measurements and Recording 695

5.1 General 695

5.2 Disturbance Records 695

5.3 Event, Fault and Maintenance Records 695

5.4 Fault Locator 695

6 Ratings 696

6.1 AC Measuring Inputs 696

6.2 Current Transformer Inputs 696

6.3 Voltage Transformer Inputs 696

6.4 Auxiliary Supply Voltage 696

6.5 Nominal Burden 697

6.6 Power Supply Interruption 697

6.7 Battery Backup 698

7 Input / Output Connections 699

7.1 Isolated Digital Inputs 699

7.1.1 Nominal Pickup and Reset Thresholds 699

7.2 Standard Output Contacts 699

7.3 High Break Output Contacts 700

7.4 Watchdog Contacts 700

8 Mechanical Specifications 701

8.1 Physical Parameters 701

8.2 Enclosure Protection 701

8.3 Mechanical Robustness 701

8.4 Transit Packaging Performance 701

9 Type Tests 702

9.1 Insulation 702

9.2 Creepage Distances and Clearances 702

9.3 High Voltage (Dielectric) Withstand 702

9.4 Impulse Voltage Withstand Test 702

10 Environmental Conditions 703

10.1 Ambient Temperature Range 703

10.2 Temperature Endurance Test 703

10.3 Ambient Humidity Range 703

10.4 Corrosive Environments 703

11 Electromagnetic Compatibility 704

11.1 1 MHz Burst High Frequency Disturbance Test 704

11.2 Damped Oscillatory Test 704

11.3 Immunity to Electrostatic Discharge 704

xx P446SV-TM-EN-1

P446SV Contents

11.4 Electrical Fast Transient or Burst Requirements 704

11.5 Surge Withstand Capability 704

11.6 Surge Immunity Test 705

11.7 Immunity to Radiated Electromagnetic Energy 705

11.8 Radiated Immunity from Digital Communications 705

11.9 Radiated Immunity from Digital Radio Telephones 705

11.10 Immunity to Conducted Disturbances Induced by Radio Frequency Fields 705

11.11 Magnetic Field Immunity 706

11.12 Conducted Emissions 706

11.13 Radiated Emissions 706

11.14 Power Frequency 706

12 Regulatory Compliance 707

12.1 EMC Compliance: 2014/30/EU 707

12.2 LVD Compliance: 2014/35/EU 707

12.3 R&TTE Compliance: 2014/53/EU 707

12.4 UL/CUL Compliance 707

12.5 ATEX Compliance: 2014/34/EU 707

Appendix A Ordering Options 709

Appendix B Settings and Signals 711

Appendix C Wiring Diagrams 713

P446SV-TM-EN-1 xxi

Contents P446SV

xxii P446SV-TM-EN-1

Table of Figures

Figure 1: P40L family - version evolution 7
Figure 2: Key to logic diagrams 12
Figure 3: Functional Overview 13
Figure 4: Hardware architecture 32
Figure 5: Exploded view of IED 33
Figure 6: Front panel (40TE) 35
Figure 7: Rear view of populated case 38
Figure 8: Rear connection to terminal block 39
Figure 9: Main processor board 40
Figure 10: Power supply board 41
Figure 11: Power supply assembly 42
Figure 12: Power supply terminals 43
Figure 13: Watchdog contact terminals 44
Figure 14: Rear serial port terminals 45
Figure 15: IEC 61850-9-2LE board 45
Figure 16: Standard output relay board - 8 contacts 46
Figure 17: IRIG-B board 47
Figure 18: Fibre optic board 48
Figure 19: Rear communication board 49
Figure 20: Ethernet board 49
Figure 21: Redundant Ethernet board 51
Figure 22: Fully populated Coprocessor board 53
Figure 23: High Break relay output board 54
Figure 24: High Break contact operation 55
Figure 25: Software Architecture 60
Figure 26: Frequency response of FIR filters 66
Figure 27: Frequency Response (indicative only) 67
Figure 28: Navigating the HMI 74
Figure 29: Default display navigation 76
Figure 30: Circuit Breaker Trip Conversion Logic Diagram (Module 63) 85
Figure 31: Comparison of Conventional IED and Sampled Values IED 96
Figure 32: Data sampling using an IEC 61850-9-2LE interface 97
Figure 33: System Impedance Ratio 108
Figure 34: Directional mho element construction 111
Figure 35: Offset Mho characteristic 112
Figure 36: Directional Mho element construction – impedance domain 113
Figure 37: Offset Mho characteristics – impedance domain 114
Figure 38: Offset mho characteristics – voltage domain 115

Table of Figures P446SV

Figure 39: Simplified forward fault 116
Figure 40: Mho expansion – forward fault 117
Figure 41: Simplified Reverse Fault 118
Figure 42: Mho contraction – reverse fault 119
Figure 43: Simplified quadrilateral characteristics 121
Figure 44: General Quadrilateral Characteristic Limits 122
Figure 45: Directional Quadrilateral Characteristic 123
Figure 46: Quadrilateral Characteristic featuring 2 directional forward zones and 1 offset zone 123
Figure 47: Five-sided polygon formed by Quadrilateral characteristic with Directional-Line

124

intersection of Reverse Impedance Reach Line

Figure 48: Impedance Reach line construction 126
Figure 49: Reverse impedance reach line construction 127
Figure 50: Resistive reach of phase elements 128
Figure 51: Resistive Reach line construction 128
Figure 52: Reverse resistive reach line construction 129
Figure 53: Phase Fault Quadrilateral characteristic summary 129
Figure 54: Impedance Reach line in Z1 plane 132
Figure 55: Impedance Reach line in ZLP plane 133
Figure 56: General characteristic in ZLP plane 134
Figure 57: Phase relations between I2 and Iph for leading and lagging polarizing currents 135
Figure 58: General characteristic in Z1 plane 136
Figure 59: Simplified characteristic in Z1 plane 137
Figure 60: Phase to phase current changes for C phase-to-ground (CN) fault 141
Figure 61: Biased Neutral Current Detector Characteristic 142
Figure 62: Load Blinder Characteristics 145
Figure 63: Sequence networks connection for an internal A-N fault 148
Figure 64: - DV Forward and Reverse tripping regions 149
Figure 65: Settings required to apply a quadrilateral zone 150
Figure 66: Settings required to apply a mho zone 151
Figure 67: Over-tilting effect 153
Figure 68: Example power system 158
Figure 69: Apparent Impedances seen by Distance Protection on a Teed Feeder 163
Figure 70: Scheme Assignment 169
Figure 71: Aided Distance PUR scheme 172
Figure 72: Aided Distance POR scheme 174
Figure 73: Example of fault current reversal of direction 176
Figure 74: Aided Distance Blocking scheme (BOP) 178
Figure 75: Aided Distance Send logic 180
Figure 76: Carrier Aided Schemes Receive logic 180
Figure 77: Aided Distance Tripping logic 181

xxiv P446SV-TM-EN-1

P446SV Table of Figures

Figure 78: PUR Aided Tripping logic 181
Figure 79: POR Aided Tripping logic 183
Figure 80: Aided Scheme Blocking 1 Tripping logic 183
Figure 81: Aided Scheme Blocking 2 Tripping logic 183
Figure 82: Virtual Current Polarization 186
Figure 83: Directional criteria for residual voltage polarization 187
Figure 84: Aided DEF POR scheme 189
Figure 85: Aided DEF Blocking scheme 190
Figure 86: DEF Directional Signals 190
Figure 87: Aided DEF Send logic 191
Figure 88: Carrier Aided Schemes Receive logic 191
Figure 89: Aided DEF Tripping logic 192
Figure 90: POR Aided Tripping logic 194
Figure 91: Aided Scheme Blocking 1 Tripping logic 194
Figure 92: Aided Scheme Blocking 2 Tripping logic 194
Figure 93: Aided Delta POR scheme 196
Figure 94: Aided Delta Blocking scheme 197
Figure 95: Aided Delta Send logic 198
Figure 96: Carrier Aided Schemes Receive logic 198
Figure 97: Aided Delta Tripping logic 199
Figure 98: POR Aided Tripping logic 201
Figure 99: Aided Scheme Blocking 1 Tripping logic 201
Figure 100: Aided Scheme Blocking 2 Tripping logic 201
Figure 101: Apparent Impedances seen by Distance Protection on a Teed Feeder 204
Figure 102: Problematic Fault Scenarios for PUR Scheme Application to Teed Feeders 206
Figure 103: Any Distance Start 214
Figure 104: Standard basic scheme mode logic 214
Figure 105: Alternative basic timer start scheme mode logic 215
Figure 106: Basic time stepped distance scheme 216
Figure 107: Trip On Close logic 217
Figure 108: Trip On Close based on CNV level detectors 218
Figure 109: SOTF Tripping 219
Figure 110: SOTF Tripping with CNV 219
Figure 111: TOR Tripping logic for appropriate zones 220
Figure 112: TOR Tripping logic with CNV 220
Figure 113: Zone 1 extension scheme 221
Figure 114: Zone 1 extension logic 221
Figure 115: Loss of load accelerated trip scheme 222
Figure 116: Loss of Load Logic 223
Figure 117: Power transfer related to angular difference between two generation sources 228

P446SV-TM-EN-1 xxv

Table of Figures P446SV

Figure 118: Phase selector timing for power swing condition 231
Figure 119: Phase selector timing for fault condition 231
Figure 120: Phase selector timing for fault during a power swing 232
Figure 121: Slow Power Swing detection characteristic 233
Figure 122: Load Blinder Boundary Conditions 236
Figure 123: Power swing blocking logic 237
Figure 124: Setting the resistive reaches 238
Figure 125: Reactive reach settings 239
Figure 126: PSB timer setting guidelines 240
Figure 127: Out of Step detection characteristic 241
Figure 128: Out of Step logic diagram 243
Figure 129: OST setting determination for the positive sequence resistive component OST R5 244
Figure 130: OST R6max determination 245
Figure 131: Example of timer reset due to MOVs operation 248
Figure 132: Autoreclose sequence for a Transient Fault 256
Figure 133: Autoreclose sequence for an evolving or permanent fault 257
Figure 134: Autoreclose sequence for an evolving or permanent fault - single-phase operation 257
Figure 135: Dual CB Autoreclose Sequence for a Transient Fault 258
Figure 136: Autoreclose Sequence for an evolving/permanent fault on a dual CB application 259
Figure 137: Autoreclose Sequence for a persistent fault on a multishot dual CB application set

259

for single-phase operation

Figure 138: Key to logic diagrams 262
Figure 139: Autoreclose System Map - part 1 263
Figure 140: Autoreclose System Map - part 2 264
Figure 141: Autoreclose System Map - part 3 265
Figure 142: Autoreclose System Map - part 4 266
Figure 143: Autoreclose System Map - part 5 267
Figure 144: Autoreclose System Map - part 6 268
Figure 145: Autoreclose System Map - part 7 269
Figure 146: Autoreclose System Map - part 8 270
Figure 147: Autoreclose System Map - part 9 271
Figure 148: Autoreclose System Map - part 10 272
Figure 149: CB State logic diagram (Module 1) 290
Figure 150: Circuit Breaker Open logic diagram (Module 3) 291
Figure 151: CB In Service logic diagram (Module 4) 292
Figure 152: Autoreclose Enable logic diagram (Module 5) 292
Figure 153: Leader/Follower CB Selection Logic Diagram (Module 6) 293
Figure 154: Leader/Follower logic diagram (Module 7 & 8) 294
Figure 155: Autoreclose Modes Enable logic diagram (Module 9) 296
Figure 156: Force three-phase trip logic diagram (Module 10) 297

xxvi P446SV-TM-EN-1

P446SV Table of Figures

Figure 157: Autoreclose Initiation logic diagram (Module 11) 299
Figure 158: Autoreclose Trip Test logic diagram (Module 12) 299
Figure 159: Autoreclose initiation by internal single and three phase trip or external trip for CB1

300

(Module 13)

Figure 160: Autoreclose initiation by internal single and three phase trip or external trip for CB2

301

(Module 14)

Figure 161: Protection Reoperation and Evolving Fault logic diagram (Module 20) 302
Figure 162: Fault Memory logic diagram (Module 15) 302
Figure 163: Autoreclose In Progress logic diagram for CB1 (Module 16) 303
Figure 164: Autoreclose In Progress logic diagram for CB2 (Module 17) 304
Figure 165: Autoreclose Sequence Counter logic diagram (Module 18) 305
Figure 166: Single-phase Autoreclose Cycle Selection logic diagram (Module 19) 306
Figure 167: Three-phase Autoreclose Cycle Selection logic diagram (Module 21) 307
Figure 168: Dead time Start Enable logic diagram (Module 22) 308
Figure 169: Single-phase Leader Dead Time logic diagram (Module 24) 309
Figure 170: Three-phase Leader CB Dead Time logic diagram (Module 25) 310
Figure 171: Follower Enable logic diagram (Module 27) 311
Figure 172: Single-phase Follower CB timing logic diagram (Module 28) 312
Figure 173: Three-phase Follower CB timing logic diagram (Module 29) 313
Figure 174: Circuit Breaker Autoclose Logic Diagram (Modules 32 & 33) 314
Figure 175: Prepare Reclaim Initiation logic diagram (Module 34) 315
Figure 176: Reclaim Time logic diagram (Module 35) 316
Figure 177: Successful Autoreclose Signals logic diagram (Module 36) 317
Figure 178: Autoreclose Reset Successful Indication logic diagram (Modules 37 & 38) 318
Figure 179: Circuit Breaker Healthy and System Check Timers Healthy logic diagram (Module 39) 319
Figure 180: Autoreclose Shot Counters logic diagram (Modules 41 & 42) 321
Figure 181: CB1 Control Logic (Module 43) 322
Figure 182: CB2 Control Logic (Module 44) 323
Figure 183: Circuit Breaker Trip Time Monitoring logic diagram (Modules 53 & 54) 324
Figure 184: CB1 Lockout Logic Diagram (Module 55) 326
Figure 185: CB2 Lockout Logic Diagram (Module 56) 327
Figure 186: Reset Circuit Breaker Lockout Logic Diagram (Modules 57 & 58) 329
Figure 187: Pole Discrepancy Logic Diagram (Module 62) 330
Figure 188: Circuit Breaker Trip Conversion Logic Diagram (Module 63) 331
Figure 189: Voltage Monitor for CB Closure (Module 59) 332
Figure 190: Check Synchronisation Monitor for CB1 closure (Module 60) 333
Figure 191: Check Synchronisation Monitor for CB2 closure (Module 61) 334
Figure 192: Three-phase AR System Check logic diagram for CB1 as leader (Module 45) 336
Figure 193: Three-phase AR System Check logic diagram for CB2 as leader (Module 46) 337
Figure 194: Three-phase AR System Check logic d for CB1 as follower (Module 47) 338
Figure 195: Three-phase AR System Check logic diagram for CB2 as follower (Module 48) 339

P446SV-TM-EN-1 xxvii

Table of Figures P446SV

Figure 196: CB Manual Close System Check Logic Diagram (Modules 51 & 52) 340
Figure 197: Circuit Breaker Fail logic - part 1 351
Figure 198: Circuit Breaker Fail logic - part 2 352
Figure 199: Circuit Breaker Fail logic - part 3 353
Figure 200: Circuit Breaker Fail logic - part 4 354
Figure 201: CB Fail timing 356
Figure 202: Phase Overcurrent Protection logic diagram 362
Figure 203: Negative Phase Sequence Overcurrent Protection logic diagram 364
Figure 204: IDG Characteristic 367
Figure 205: Earth Fault Protection logic diagram 369
Figure 206: EPATR B characteristic shown for TMS = 1.0 372
Figure 207: Sensitive Earth Fault Protection logic diagram 372
Figure 208: Current distribution in an insulated system with C phase fault 373
Figure 209: Phasor diagrams for insulated system with C phase fault 374
Figure 210: Positioning of core balance current transformers 375
Figure 211: High Impedance REF principle 376
Figure 212: High Impedance REF Connection 377
Figure 213: Thermal overload protection logic diagram 379
Figure 214: Spreadsheet calculation for dual time constant thermal characteristic 380
Figure 215: Dual time constant thermal characteristic 380
Figure 216: Broken conductor logic 382
Figure 217: Undervoltage - single and three phase tripping mode (single stage) 389
Figure 218: Overvoltage - single and three phase tripping mode (single stage) 392
Figure 219: Residual Overvoltage logic 396
Figure 220: Residual voltage for a solidly earthed system 397
Figure 221: Residual voltage for an impedance earthed system 398
Figure 222: Underfrequency logic (single stage) 403
Figure 223: Overfrequency logic (single stage) 404
Figure 224: Rate of change of frequency logic (single stage) 405
Figure 225: Fault recorder stop conditions 412
Figure 226: Broken Current Accumulator logic diagram 417
Figure 227: CB Trip Counter logic diagram 418
Figure 228: Operating Time Accumulator 419
Figure 229: Excessive Fault Frequency logic diagram 420
Figure 230: Reset Lockout Alarm logic diagram 421
Figure 231: CB1 Condition Monitoring logic diagram 422
Figure 232: CB2 Condition Monitoring logic diagram 423
Figure 233: Reset Circuit Breaker Lockout Logic Diagram (Modules 57 & 58) 425
Figure 234: CB State logic diagram (Module 1) 428
Figure 235: Hotkey menu navigation 430

xxviii P446SV-TM-EN-1

P446SV Table of Figures

Figure 236: Default function key PSL 431
Figure 237: Remote Control of Circuit Breaker 432
Figure 238: CB1 Control Logic (Module 43) 433
Figure 239: CB2 Control Logic (Module 44) 434
Figure 240: Pole Dead logic 435
Figure 241: Check Synchronisation vector diagram 438
Figure 242: Voltage Monitor for CB Closure (Module 59) 439
Figure 243: Check Synchronisation Monitor for CB1 closure (Module 60) 440
Figure 244: Check Synchronisation Monitor for CB2 closure (Module 61) 441
Figure 245: System Check PSL 442
Figure 246: VTS logic 450
Figure 247: Standard CTS 453
Figure 248: TCS Scheme 1 454
Figure 249: PSL for TCS Scheme 1 455
Figure 250: TCS Scheme 2 455
Figure 251: PSL for TCS Scheme 2 456
Figure 252: TCS Scheme 3 456
Figure 253: PSL for TCS Scheme 3 457
Figure 254: Scheme Logic Interfaces 463
Figure 255: Trip LED logic 467
Figure 256: Fibre Teleprotection connections for a three-terminal Scheme 479
Figure 257: Interfacing to PCM multiplexers 483
Figure 258: IM64 channel fail and scheme fail logic 485
Figure 259: IM64 general alarm signals logic 485
Figure 260: IM64 communications mode and IEEE C37.94 alarm signals 486
Figure 261: IM64 two-terminal scheme extended supervision 488
Figure 262: IM64 three-terminal scheme extended supervision 488
Figure 263: Example assignment of InterMiCOM signals within the PSL 498
Figure 264: Direct connection 499
Figure 265: Indirect connection using modems 499
Figure 266: RS485 biasing circuit 508
Figure 267: Remote communication using K-Bus 509
Figure 268: IED attached to separate LANs 512
Figure 269: HSR multicast topology 513
Figure 270: HSR unicast topology 514
Figure 271: HSR application in the substation 515
Figure 272: IED attached to redundant Ethernet star or ring circuit 515
Figure 273: IED, bay computer and Ethernet switch with self healing ring facilities 516
Figure 274: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches 516

P446SV-TM-EN-1 xxix

Table of Figures P446SV

Figure 275: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches

517

after failure

Figure 276: Dual homing mechanism 518
Figure 277: Application of Dual Homing Star at substation level 519
Figure 278: IED and REB IP address configuration 520
Figure 279: Connection using (a) an Ethernet switch and (b) a media converter 523
Figure 280: Connection using (a) an Ethernet switch and (b) a media converter 527
Figure 281: Control input behaviour 550
Figure 282: Data model layers in IEC61850 562
Figure 283: Edition 2 system - backward compatibility 566
Figure 284: Edition 1 system - forward compatibility issues 566
Figure 285: Example of Standby IED 567
Figure 286: Standby IED Activation Process 568
Figure 287: GPS Satellite timing signal 571
Figure 288: Timing error using ring or line topology 573
Figure 289: Default display navigation 584
Figure 290: Location of battery isolation strip 597
Figure 291: Rack mounting of products 598
Figure 292: Terminal block types 600
Figure 293: 40TE case dimensions 604
Figure 294: RP1 physical connection 620
Figure 295: Remote communication using K-bus 621
Figure 296: InterMicom loopback testing 624
Figure 297: Simulated input behaviour 631
Figure 298: Test example 1 632
Figure 299: Test example 2 633
Figure 300: Test example 3 634
Figure 301: State impedances 646
Figure 302: Possible terminal block types 668
Figure 303: Front panel assembly 670

xxx P446SV-TM-EN-1

CHAPTER 1

INTRODUCTION

Chapter 1 - Introduction P446SV

2 P446SV-TM-EN-1

P446SV Chapter 1 - Introduction

1 CHAPTER OVERVIEW

This chapter provides some general information about the technical manual and an introduction to the device(s)
described in this technical manual.

This chapter contains the following sections:
Chapter Overview 3
Foreword 4
Product Scope 6
Features and Functions 8
Logic Diagrams 11
Functional Overview 13

P446SV-TM-EN-1 3

Chapter 1 - Introduction P446SV

2 FOREWORD

This technical manual provides a functional and technical description of General Electric's P446SV, as well as a
comprehensive set of instructions for using the device. The level at which this manual is written assumes that you
are already familiar with protection engineering and have experience in this discipline. The description of principles
and theory is limited to that which is necessary to understand the product. For further details on general
protection engineering theory, we refer you to Alstom's publication NPAG, which is available online or from our
contact centre.

We have attempted to make this manual as accurate, comprehensive and user-friendly as possible. However we
cannot guarantee that it is free from errors. Nor can we state that it cannot be improved. We would therefore be
very pleased to hear from you if you discover any errors, or have any suggestions for improvement. Our policy is to
provide the information necessary to help you safely specify, engineer, install, commission, maintain, and
eventually dispose of this product. We consider that this manual provides the necessary information, but if you
consider that more details are needed, please contact us.

All feedback should be sent to our contact centre via the following URL:

www.gegridsolutions.com/contact

2.1

This manual is aimed towards all professionals charged with installing, commissioning, maintaining,
troubleshooting, or operating any of the products within the specified product range. This includes installation and
commissioning personnel as well as engineers who will be responsible for operating the product.

The level at which this manual is written assumes that installation and commissioning engineers have knowledge
of handling electronic equipment. Also, system and protection engineers have a thorough knowledge of protection
systems and associated equipment.

2.2

The following typographical conventions are used throughout this manual.

● The names for special keys appear in capital letters.

● When describing software applications, menu items, buttons, labels etc as they appear on the screen are

● Filenames and paths use the courier font

● Special terminology is written with leading capitals

● If reference is made to the IED's internal settings and signals database, the menu group heading (column)

● If reference is made to the IED's internal settings and signals database, the setting cells and DDB signals are

● If reference is made to the IED's internal settings and signals database, the value of a cell's content is

TARGET AUDIENCE

TYPOGRAPHICAL CONVENTIONS

For example: ENTER

written in bold type.
For example: Select Save from the file menu.

For example: Example\File.text

For example: Sensitive Earth Fault

text is written in upper case italics
For example: The SYSTEM DATA column

written in bold italics
For example: The Language cell in the SYSTEM DATA column

written in the Courier font
For example: The Language cell in the SYSTEM DATA column contains the value English

4 P446SV-TM-EN-1

P446SV Chapter 1 - Introduction

2.3 NOMENCLATURE

Due to the technical nature of this manual, many special terms, abbreviations and acronyms are used throughout
the manual. Some of these terms are well-known industry-specific terms while others may be special product­specific terms used by General Electric. The first instance of any acronym or term used in a particular chapter is
explained. In addition, a separate glossary is available on the General Electric website, or from the General Electric
contact centre.

We would like to highlight the following changes of nomenclature however:

● The word 'relay' is no longer used to describe the device itself. Instead, the device is referred to as the 'IED'

(Intelligent Electronic Device), the 'device', or the 'product'. The word 'relay' is used purely to describe the
electromechanical components within the device, i.e. the output relays.

● British English is used throughout this manual.

● The British term 'Earth' is used in favour of the American term 'Ground'.

2.4

The device has undergone a range of extensive testing and certification processes to ensure and prove
compatibility with all target markets. A detailed description of these criteria can be found in the Technical
Specifications chapter.

COMPLIANCE

P446SV-TM-EN-1 5

Chapter 1 - Introduction P446SV

3 PRODUCT SCOPE

Unlike a conventional IED, a device with an IEC61850-9-2 interface, or Sampled Value (SV) device accepts current
and voltage measurement inputs, which have already been digitized in accordance with the IEC 61850-9-2LE
standard.

The P446SV is such a device. It accepts sampled analogue values from merging units. It does not accept analogue
values directly and therefore does not have any current or voltage transformers. This provides a number of
advantages over conventional devices, which are discussed throughout this technical manual.

The P446SV has been designed for distance protection of overhead line and underground cable applications,
where the network is solidly grounded. It is used for dual circuit breaker applications, such as breaker-and-a-half,
or ring bus topologies, where two circuit breakers feed each line. As well as distance protection, this device can
also be used for 4-shot phase-segregated Autoreclose protection and a range of standard current, voltage, power
and frequency backup protection applications.

3.1

This product belongs to the P40L family. Although this technical manual is specific to this product, it is useful to
know where the product fits into the family and to describe the evolution path of the entire product family. The
following diagram attempts to do this:

PRODUCT VERSIONS

6 P446SV-TM-EN-1

V00062

 XCPU3
 Cyber-security
 New Protection

functions

P445: P41

P54x No Distance: M61

P841A: M61

All other products: M71

 New Protection

functions

P445: P45

P54x No Distance: M65

P841A: M65

All other products: M75

 Current Differential

Starters for P54x

 Other improvements

P445: P46

P54x No Distance: M66

P841A: M66

All other products: M76

P446, P546, P841B: M74

 Sub-cy cle differential for

non-dis tance versions

P543, P545: M63

Non-distance

 IEC 61850 Edition 2
 IEEE 1588 support

P543, P545: M83

Non-distance

 IEC 61850 Edition 2
 IEEE 1588 support
 40TE case

P446, P546, P841B: P80

 XCPU3
 Cyber-security
 NCIT (9-2LE interface)

 NCIT (now obsolete)

Non-distance products: M81

Distance products: M82

 IEC 61850 Edition 2
 IEEE 1588 support

P445: J37

P54x No Distance: K47

P841A: K47

All other products: K57

P446, P546, P841B: M72

Conventional Stream NCIT Stream

Sub-cycle Diff Stream

P54A, P54B: P01

P54C, P54E: M01

Non-distance

 Multi-end
 Sub-cy cle

Multi-end subcycle stream

P446SV Chapter 1 - Introduction

Figure 1: P40L family - version evolution

3.2

All current models and variants for this product are defined in an interactive spreadsheet called the CORTEC. This is
available on the company website.

Alternatively, you can obtain it via the Contact Centre at the following URL:

www.gegridsolutions.com/contact

A copy of the CORTEC is also supplied as a static table in the Appendices of this document. However, it should only
be used for guidance as it provides a snapshot of the interactive data taken at the time of publication.

P446SV-TM-EN-1 7

ORDERING OPTIONS

Chapter 1 - Introduction P446SV

4 FEATURES AND FUNCTIONS

4.1 DISTANCE PROTECTION FUNCTIONS

Feature IEC 61850 ANSI

Distance zones, full-scheme protection (5) DisPDIS 21/21N
Phase characteristic (Mho and quadrilateral)
Ground characteristic (Mho and quadrilateral)
CVT transient overreach elimination
Load blinder
Easy setting mode
Communication-aided schemes, PUTT, POTT, Blocking, Weak

Infeed
Accelerated tripping – loss of load and Z1 extension
Switch on to fault and trip on reclose – elements for fast fault

clearance on breaker closure
Power swing blocking PsbRPSB 68
Directional earth fault (DEF) unit protection 67N
Out of step OstRPSB 78
Delta directional comparison - fast channel schemes operating

on fault generated superimposed quantities
Mutual compensation (for fault locator and distance zones)

DisPSCH 85

SofPSOF/ TorPSOF 50SOTF/27SOTF

78DCB/78DCUB

InterMiCOM64 teleprotection for direct device-to-device
communication (optional)

4.2 PROTECTION FUNCTIONS

Feature IEC 61850 ANSI

Tripping Mode (1 & 3 pole) PTRC
ABC and ACB phase rotation
Phase overcurrent , with optional directionality (4 stages) OcpPTOC/RDIR 50/51/67
Earth/Ground overcurrent stages, with optional directionality (4

stages)
Sensitive earth fault (SEF) (4 stages) SenPTOC/RDIR 50N/51N/67N
High impedance restricted earth fault (REF) SenRefPDIF 64
Negative sequence overcurrent stages, with optional

directionality (4 stages)
Broken conductor, used to detect open circuit faults 46
Thermal overload protection ThmPTTR 49
Undervoltage protection (2 stages) VtpPhsPTUV 27
Overvoltage protection (2 stages) VtpPhsPTOV 59
Remote overvoltage protection (2 stages) VtpCmpPTOV 59R
Residual voltage protection (2 stages) VtpResPTOV 59N
Underfrequency protection (4 stages) FrqPTUF 81
Overfrequency protection (2 stages) FrqPTOF 81

EfdPTOC/RDIR 50N/51N/ 67N

NgcPTOC/RDIR 67/46

8 P446SV-TM-EN-1

P446SV Chapter 1 - Introduction

Feature IEC 61850 ANSI

Rate of change of frequency protection (4 stages) DfpPFRC 81
High speed breaker fail suitable for re-tripping and back-

tripping (2 stages)
Current Transformer supervision 46
Voltage transformer supervision 47/27
Auto-reclose (4 shots) RREC 79
Check synchronisation (2 stages) RSYN 25

RBRF 50BF

4.3 CONTROL FUNCTIONS

Feature IEC 61850 ANSI

Watchdog contacts
Read-only mode
Function keys FnkGGIO
Programmable LEDs LedGGIO
Programmable hotkeys
Programmable allocation of digital inputs and outputs
Fully customizable menu texts
Circuit breaker control, status & condition monitoring XCBR 52
CT supervision
VT supervision
Trip circuit and coil supervision
Control inputs PloGGIO1
Power-up diagnostics and continuous self-monitoring
Dual rated 1A and 5A CT inputs
Alternative setting groups (4)
Graphical programmable scheme logic (PSL)
Fault locator RFLO

4.4 MEASUREMENT FUNCTIONS

Measurement Function IEC 61850 ANSI

Measurement of all instantaneous & integrated values
(Exact range of measurements depend on the device model)

Disturbance recorder for waveform capture – specified in samples per cycle RDRE DFR
Fault Records
Maintenance Records
Event Records / Event logging Event records
Time Stamping of Opto-inputs Yes Yes

MET

4.5 COMMUNICATION FUNCTIONS

Feature ANSI

NERC compliant cyber-security

P446SV-TM-EN-1 9

Chapter 1 - Introduction P446SV

Feature ANSI

Front RS232 serial communication port for configuration 16S
Rear serial RS485 communication port for SCADA control 16S
2 Additional rear serial communication ports for SCADA control and

teleprotection (fibre and copper) (optional)
Ethernet communication (optional) 16E
Redundant Ethernet communication (optional) 16E
Courier Protocol 16S
IEC 61850 edition 2 16E
IEC 60870-5-103 (optional) 16S
DNP3.0 over serial link (optional) 16S
DNP3.0 over Ethernet (optional) 16E
SNMP 16E
IRIG-B time synchronisation (optional) CLK
IEEE 1588 PTP (Edition 2 devices only)

16S

10 P446SV-TM-EN-1

P446SV Chapter 1 - Introduction

5 LOGIC DIAGRAMS

This technical manual contains many logic diagrams, which should help to explain the functionality of the device.
Although this manual has been designed to be as specific as possible to the chosen product, it may contain
diagrams, which have elements applicable to other products. If this is the case, a qualifying note will accompany
the relevant part.

The logic diagrams follow a convention for the elements used, using defined colours and shapes. A key to this
convention is provided below. We recommend viewing the logic diagrams in colour rather than in black and white.
The electronic version of the technical manual is in colour, but the printed version may not be. If you need coloured
diagrams, they can be provided on request by calling the contact centre and quoting the diagram number.

P446SV-TM-EN-1 11

V00063

Key:

DDB Signal

Internal function

&AND gate

OR gate 1

Setting cell

Setting value Timer

SR Latch
Reset Dominant

Internal Signal

0Logic 0

Comparator for detecting
overvalues

Energising Quantity

Hardcoded setting

R

D

Q

S

Comparator for detecting
undervalues

Switch

Measurement Cell

Derived setting

SR Latch

HMI key

Pulse / Latch

Connection / Node Inverted logic input

Soft switch

Latched on positive edge

XMultiplier

2

1

NOT gate

XOR

XOR gate

R

Q

S

Internal Calculation

Switch

Bandpass filter

Chapter 1 - Introduction P446SV

Figure 2: Key to logic diagrams

12 P446SV-TM-EN-1

V00010

X

X

X

I

E sen

67

50/27

46BC STCN76

27/
59

VTS50BF

79-250BF-2 2 5- 2

79

25

Fault record s

Disturban ce

Record

Measurement s

PSL

Local

Communication

2ndRemote

comm. port

Remote

LINE

LINE

BUS

BUS

comm. port

P443,P445 & P446

Inte r MiCOM

LEDs

Conventiona l
signalling

Always

available

P443 & P446

only

P446

only

Optiona l

Protection
communication

V

ref

V

ref

V

I

Self monitoring

85

FL

50N /

51N

∆I /∆V

67/

46

67N

SEF

68 78

59N

Neu tral current
(if present)
from para llel line

I

M

49

SOTF/TOR

64

REF

21G21P

50/51

IEC

618 50

I

P446SV Chapter 1 - Introduction

6 FUNCTIONAL OVERVIEW

This diagram is applicable to three products in the P40L family; P443, P445 and P446. Use the key on the diagram
to determine the features relevant to the product described in this technical manual.

Figure 3: Functional Overview

P446SV-TM-EN-1 13

Chapter 1 - Introduction P446SV

14 P446SV-TM-EN-1

CHAPTER 2

SAFETY INFORMATION

Chapter 2 - Safety Information P446SV

16 P446SV-TM-EN-1

P446SV Chapter 2 - Safety Information

1 CHAPTER OVERVIEW

This chapter provides information about the safe handling of the equipment. The equipment must be properly
installed and handled in order to maintain it in a safe condition and to keep personnel safe at all times. You must
be familiar with information contained in this chapter before unpacking, installing, commissioning, or servicing the
equipment.

This chapter contains the following sections:
Chapter Overview 17
Health and Safety 18
Symbols 19
Installation, Commissioning and Servicing 20
Decommissioning and Disposal 25
Regulatory Compliance 26

P446SV-TM-EN-1 17

Chapter 2 - Safety Information P446SV

2 HEALTH AND SAFETY

Personnel associated with the equipment must be familiar with the contents of this Safety Information.
When electrical equipment is in operation, dangerous voltages are present in certain parts of the equipment.

Improper use of the equipment and failure to observe warning notices will endanger personnel.
Only qualified personnel may work on or operate the equipment. Qualified personnel are individuals who are:

● familiar with the installation, commissioning, and operation of the equipment and the system to which it is

being connected.

● familiar with accepted safety engineering practises and are authorised to energise and de-energise

equipment in the correct manner.

● trained in the care and use of safety apparatus in accordance with safety engineering practises

● trained in emergency procedures (first aid).

The documentation provides instructions for installing, commissioning and operating the equipment. It cannot,
however cover all conceivable circumstances. In the event of questions or problems, do not take any action
without proper authorisation. Please contact your local sales office and request the necessary information.

18 P446SV-TM-EN-1

P446SV Chapter 2 - Safety Information

3 SYMBOLS

Throughout this manual you will come across the following symbols. You will also see these symbols on parts of
the equipment.

Caution:
Refer to equipment documentation. Failure to do so could result in damage to the
equipment

Warning:
Risk of electric shock

Earth terminal. Note: This symbol may also be used for a protective conductor (earth) terminal if that terminal
is part of a terminal block or sub-assembly.

Protective conductor (earth) terminal

Instructions on disposal requirements

Note:
The term 'Earth' used in this manual is the direct equivalent of the North American term 'Ground'.

P446SV-TM-EN-1 19

Chapter 2 - Safety Information P446SV

4 INSTALLATION, COMMISSIONING AND SERVICING

4.1 LIFTING HAZARDS

Many injuries are caused by:

● Lifting heavy objects

● Lifting things incorrectly

● Pushing or pulling heavy objects

● Using the same muscles repetitively

Plan carefully, identify any possible hazards and determine how best to move the product. Look at other ways of
moving the load to avoid manual handling. Use the correct lifting techniques and Personal Protective Equipment
(PPE) to reduce the risk of injury.

4.2

ELECTRICAL HAZARDS

Caution:
All personnel involved in installing, commissioning, or servicing this equipment must be
familiar with the correct working procedures.

Caution:
Consult the equipment documentation before installing, commissioning, or servicing
the equipment.

Caution:
Always use the equipment as specified. Failure to do so will jeopardise the protection
provided by the equipment.

Warning:
Removal of equipment panels or covers may expose hazardous live parts. Do not touch
until the electrical power is removed. Take care when there is unlocked access to the
rear of the equipment.

Warning:
Isolate the equipment before working on the terminal strips.

Warning:
Use a suitable protective barrier for areas with restricted space, where there is a risk of
electric shock due to exposed terminals.

Caution:
Disconnect power before disassembling. Disassembly of the equipment may expose
sensitive electronic circuitry. Take suitable precautions against electrostatic voltage
discharge (ESD) to avoid damage to the equipment.

20 P446SV-TM-EN-1

P446SV Chapter 2 - Safety Information

Caution:
NEVER look into optical fibres or optical output connections. Always use optical power
meters to determine operation or signal level.

Warning:
Testing may leave capacitors charged to dangerous voltage levels. Discharge
capacitors by rediucing test voltages to zero before disconnecting test leads.

Caution:
Operate the equipment within the specified electrical and environmental limits.

Caution:
Before cleaning the equipment, ensure that no connections are energised. Use a lint
free cloth dampened with clean water.

Note:
Contact fingers of test plugs are normally protected by petroleum jelly, which should not be removed.

4.3

The information in this section is applicable only to equipment carrying UL/CSA/CUL markings.

UL/CSA/CUL REQUIREMENTS

Caution:
Equipment intended for rack or panel mounting is for use on a flat surface of a Type 1
enclosure, as defined by Underwriters Laboratories (UL).

Caution:
To maintain compliance with UL and CSA/CUL, install the equipment using UL/CSA­recognised parts for: cables, protective fuses, fuse holders and circuit breakers,
insulation crimp terminals, and replacement internal batteries.

4.4 FUSING REQUIREMENTS

Caution:
Where UL/CSA listing of the equipment is required for external fuse protection, a UL or
CSA Listed fuse must be used for the auxiliary supply. The listed protective fuse type is:
Class J time delay fuse, with a maximum current rating of 15 A and a minimum DC
rating of 250 V dc (for example type AJT15).

Caution:
Where UL/CSA listing of the equipment is not required, a high rupture capacity (HRC)
fuse type with a maximum current rating of 16 Amps and a minimum dc rating of 250 V
dc may be used for the auxiliary supply (for example Red Spot type NIT or TIA).
For P50 models, use a 1A maximum T-type fuse.
For P60 models, use a 4A maximum T-type fuse.

P446SV-TM-EN-1 21

Chapter 2 - Safety Information P446SV

Caution:
Digital input circuits should be protected by a high rupture capacity NIT or TIA fuse with
maximum rating of 16 A. for safety reasons, current transformer circuits must never be
fused. Other circuits should be appropriately fused to protect the wire used.

Caution:
CTs must NOT be fused since open circuiting them may produce lethal hazardous
voltages

4.5 EQUIPMENT CONNECTIONS

Warning:
Terminals exposed during installation, commissioning and maintenance may present a
hazardous voltage unless the equipment is electrically isolated.

Caution:
Tighten M4 clamping screws of heavy duty terminal block connectors to a nominal
torque of 1.3 Nm.
Tighten captive screws of terminal blocks to 0.5 Nm minimum and 0.6 Nm maximum.

Caution:
Always use insulated crimp terminations for voltage and current connections.

Caution:
Always use the correct crimp terminal and tool according to the wire size.

Caution:
Watchdog (self-monitoring) contacts are provided to indicate the health of the device
on some products. We strongly recommend that you hard wire these contacts into the
substation's automation system, for alarm purposes.

4.6 PROTECTION CLASS 1 EQUIPMENT REQUIREMENTS

Caution:
Earth the equipment with the supplied PCT (Protective Conductor Terminal).

Caution:
Do not remove the PCT.

Caution:
The PCT is sometimes used to terminate cable screens. Always check the PCT’s integrity
after adding or removing such earth connections.

22 P446SV-TM-EN-1

P446SV Chapter 2 - Safety Information

Caution:
Use a locknut or similar mechanism to ensure the integrity of stud-connected PCTs.

Caution:
The recommended minimum PCT wire size is 2.5 mm² for countries whose mains supply
is 230 V (e.g. Europe) and 3.3 mm² for countries whose mains supply is 110 V (e.g. North
America). This may be superseded by local or country wiring regulations.
For P60 products, the recommended minimum PCT wire size is 6 mm². See product
documentation for details.

Caution:
The PCT connection must have low-inductance and be as short as possible.

Caution:
All connections to the equipment must have a defined potential. Connections that are
pre-wired, but not used, should be earthed, or connected to a common grouped
potential.

4.7 PRE-ENERGISATION CHECKLIST

Caution:
Check voltage rating/polarity (rating label/equipment documentation).

Caution:
Check CT circuit rating (rating label) and integrity of connections.

Caution:
Check protective fuse or miniature circuit breaker (MCB) rating.

Caution:
Check integrity of the PCT connection.

Caution:
Check voltage and current rating of external wiring, ensuring it is appropriate for the
application.

4.8 PERIPHERAL CIRCUITRY

Warning:
Do not open the secondary circuit of a live CT since the high voltage produced may be
lethal to personnel and could damage insulation. Short the secondary of the line CT
before opening any connections to it.

P446SV-TM-EN-1 23

Chapter 2 - Safety Information P446SV

Note:
For most Alstom equipment with ring-terminal connections, the threaded terminal block for current transformer termination
is automatically shorted if the module is removed. Therefore external shorting of the CTs may not be required. Check the
equipment documentation and wiring diagrams first to see if this applies.

Caution:
Where external components such as resistors or voltage dependent resistors (VDRs) are
used, these may present a risk of electric shock or burns if touched.

Warning:
Take extreme care when using external test blocks and test plugs such as the MMLG,
MMLB and P990, as hazardous voltages may be exposed. Ensure that CT shorting links
are in place before removing test plugs, to avoid potentially lethal voltages.

4.9 UPGRADING/SERVICING

Warning:
Do not insert or withdraw modules, PCBs or expansion boards from the equipment
while energised, as this may result in damage to the equipment. Hazardous live
voltages would also be exposed, endangering personnel.

Caution:
Internal modules and assemblies can be heavy and may have sharp edges. Take care
when inserting or removing modules into or out of the IED.

24 P446SV-TM-EN-1

P446SV Chapter 2 - Safety Information

5 DECOMMISSIONING AND DISPOSAL

Caution:
Before decommissioning, completely isolate the equipment power supplies (both poles
of any dc supply). The auxiliary supply input may have capacitors in parallel, which may
still be charged. To avoid electric shock, discharge the capacitors using the external
terminals before decommissioning.

Caution:
Avoid incineration or disposal to water courses. Dispose of the equipment in a safe,
responsible and environmentally friendly manner, and if applicable, in accordance with
country-specific regulations.

P446SV-TM-EN-1 25

Chapter 2 - Safety Information P446SV

6 REGULATORY COMPLIANCE

Compliance with the European Commission Directive on EMC and LVD is demonstrated using a technical file.

6.1 EMC COMPLIANCE: 2014/30/EU

The product specific Declaration of Conformity (DoC) lists the relevant harmonised standard(s) or conformit
assessment used to demonstrate compliance with the EMC directive.

6.2

The product specific Declaration of Conformity (DoC) lists the relevant harmonized standard(s) or conformity
assessment used to demonstrate compliance with the LVD directive.

Safety related information, such as the installation I overvoltage category, pollution degree and operating
temperature ranges are specified in the Technical Data section of the relevant product documentation and/or on
the product labelling .

Unless otherwise stated in the Technical Data section of the relevant product documentation, the equipment is
intended for indoor use only. Where the equipment is required for use in an outdoor location, it must be mounted
in a specific cabinet or housing to provide the equipment with the appropriate level of protection from the
expected outdoor environment.

6.3

Radio and Telecommunications Terminal Equipment (R&TTE) directive 2014/53/EU.
Conformity is demonstrated by compliance to both the EMC directive and the Low Voltage directive, to zero volts.

6.4

If marked with this logo, the product is compliant with the requirements of the Canadian and USA Underwriters
Laboratories.

The relevant UL file number and ID is shown on the equipment.

LVD COMPLIANCE: 2014/35/EU

R&TTE COMPLIANCE: 2014/53/EU

UL/CUL COMPLIANCE

6.5

Products marked with the 'explosion protection' Ex symbol (shown in the example, below) are compliant with the
ATEX directive. The product specific Declaration of Conformity (DoC) lists the Notified Body, Type Examination
Certificate, and relevant harmonized standard or conformity assessment used to demonstrate compliance with
the ATEX directive.

The ATEX Equipment Protection level, Equipment group, and Zone definition will be marked on the
product.
For example:

26 P446SV-TM-EN-1

ATEX COMPLIANCE: 2014/34/EU

P446SV Chapter 2 - Safety Information

Where:

'II' Equipment Group: Industrial.

'(2)G' High protection equipment category, for control of equipment in gas atmospheres in Zone 1 and 2.

This equipment (with parentheses marking around the zone number) is not itself suitable for operation
within a potentially explosive atmosphere.

P446SV-TM-EN-1 27

Chapter 2 - Safety Information P446SV

28 P446SV-TM-EN-1

CHAPTER 3

HARDWARE DESIGN

Chapter 3 - Hardware Design P446SV

30 P446SV-TM-EN-1

P446SV Chapter 3 - Hardware Design

1 CHAPTER OVERVIEW

This chapter provides information about the product's hardware design.
This chapter contains the following sections:
Chapter Overview 31
Hardware Architecture 32
Mechanical Implementation 33
Front Panel 35
Rear Panel 38
Boards and Modules 39

P446SV-TM-EN-1 31

Communications

Sample Value Inputs

I/O

I

n

t

e

r

c

o

n

n

e

c

t

i

o

n

Output relay boards

Opto-input boards

IEC 61850-9-2LE

input board

RS485 modules

Ethernet modules

Keypad

LCD

LEDs

Front port

Watchdog module

PSU module

Watchdog

contacts

+ LED

Auxiliary

Supply

IRIG-B module

P

r

o

c

e

s

s

o

r

m

o

d

u

l

e

F

r

o

n

t

p

a

n

e

l

H

M

I

Output relay contacts

Digital inputs

Sampled Values

RS485 communication

Time synchronisation

Ethernet communication

V00280

Note: Not all modules are applicable to all products

Memory

Flash memory for settings

Battery-backed SRAM

for records

Chapter 3 - Hardware Design P446SV

2 HARDWARE ARCHITECTURE

The main components comprising an General Electric Sampled Values device are as follows:

● The housing, consisting of a front panel and connections at the rear

● The Main processor module consisting of the main CPU (Central Processing Unit), memory and an interface

to the front panel HMI (Human Machine Interface)

● A selection of plug-in boards and modules with presentation at the rear for the sampled values inputs,

power supply, communication functions, digital I/O and time synchronisation connectivity

All boards and modules are connected by a parallel data and address bus, which allows the processor module to
send and receive information to and from the other modules as required. There is also a separate serial data bus
for conveying sampled data from the input module to the CPU. These parallel and serial databuses are shown as a
single interconnection module in the following figure, which shows typical modules and the flow of data between
them.

Figure 4: Hardware architecture

32 P446SV-TM-EN-1

P446SV Chapter 3 - Hardware Design

3 MECHANICAL IMPLEMENTATION

All products based on the Px4x platform have common hardware architecture. The hardware is modular and
consists of the following main parts:

● Case and terminal blocks

● Boards and modules

● Front panel

The case comprises the housing metalwork and terminal blocks at the rear. The boards fasten into the terminal
blocks and are connected together by a ribbon cable. This ribbon cable connects to the processor in the front
panel.

The following diagram shows an exploded view of a typical product. The diagram shown does not necessarily
represent exactly the product model described in this manual.

Figure 5: Exploded view of IED

3.1

The Px4x range of products are implemented in a range of case sizes. Case dimensions for industrial products
usually follow modular measurement units based on rack sizes. These are: U for height and TE for width, where:

● 1U = 1.75 inches = 44.45 mm

● 1TE = 0.2 inches = 5.08 mm

The products are available in panel-mount or standalone versions. All products are nominally 4U high. This equates
to 177.8 mm or 7 inches.

The cases are pre-finished steel with a conductive covering of aluminium and zinc. This provides good grounding
at all joints, providing a low resistance path to earth that is essential for performance in the presence of external
noise.

The case width depends on the product type and its hardware options. There are three different case widths for
the described range of products: 40TE, 60TE and 80TE. The case dimensions and compatibility criteria are as
follows:

P446SV-TM-EN-1 33

HOUSING VARIANTS

Chapter 3 - Hardware Design P446SV

Case width (TE) Case width (mm) Case width (inches)

40TE 203.2 8
60TE 304.8 12
80TE 406.4 16

Note:
Not all case sizes are available for all models.

3.2 LIST OF BOARDS

The product's hardware consists of several modules drawn from a standard range. The exact specification and
number of hardware modules depends on the model number and variant. Depending on the exact model, the
product in question will use a selection of the following boards.

Board Use

Main Processor board - 40TE or smaller Main Processor board – without support for function keys
Power supply board - 24/54V DC Power supply input. Accepts DC voltage between 24V and 54V
Power supply board - 48/125V DC Power supply input. Accepts DC voltage between 48V and 125V
Power supply board - 110/250V DC Power supply input. Accepts DC voltage between 110V and 125V
IEC 61850 9-2LE board Ethernet board for accepting IEC 61850 sampled values
IRIG-B board - modulated input Interface board for modulated IRIG-B timing signal
IRIG-B board - demodulated input Interface board for demodulated IRIG-B timing signal
Fibre board Interface board for fibre-based RS485 connection
Fibre board + IRIG-B Interface board for fibre-based RS485 connection + demodulated IRIG-B
2nd rear communications board Interface board for RS232 / RS485 connections
2nd rear communications board with IRIG-B input Interface board for RS232 / RS485 + IRIG-B connections
100MhZ Ethernet board Standard 100MHz Ethernet board for LAN connection (fibre + copper)
100MhZ Ethernet board with modulated IRIG-B Standard 100MHz Ethernet board (fibre / copper) + modulated IRIG-B
100MhZ Ethernet board with demodulated IRIG-B Standard 100MHz Ethernet board (fibre / copper)+ demodulated IRIG-B
High-break output relay board Output relay board with high breaking capacity relays
Redundant Ethernet SHP+ modulated IRIG-B Redundant SHP Ethernet board (2 fibre ports) + modulated IRIG-B input
Redundant Ethernet SHP + demodulated IRIG-B Redundant SHP Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet RSTP + modulated IRIG-B Redundant RSTP Ethernet board (2 fibre ports) + modulated IRIG-B input
Redundant Ethernet RSTP+ demodulated IRIG-B Redundant RSTP Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet DHP+ modulated IRIG-B Redundant DHP Ethernet board (2 fibre ports) + modulated IRIG-B input
Redundant Ethernet DHP+ demodulated IRIG-B Redundant DHP Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet PRP+ modulated IRIG-B Redundant PRP Ethernet board (2 fibre ports) + modulated IRIG-B input
Redundant Ethernet PRP+ demodulated IRIG-B Redundant PRP Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet HSR + modulated IRIG-B Redundant HSR Ethernet board (2 fibre ports) + demodulated IRIG-B input
Redundant Ethernet HSR+ demodulated IRIG-B Redundant HSR Ethernet board (2 fibre ports) + demodulated IRIG-B input
Output relay output board Standard output relay board

34 P446SV-TM-EN-1

P446SV Chapter 3 - Hardware Design

4 FRONT PANEL

4.1 40TE FRONT PANEL

The following diagram shows a 40TE case. The hinged covers at the top and bottom of the front panel are shown
closed. An optional transparent front cover physically protects the front panel.

Figure 6: Front panel (40TE)

The front panel consists of:

● Top and bottom compartments with hinged cover

● LCD display

● Keypad

● Fixed function LEDs

● 9 pin D-type serial port (behind hinged cover)

● 25 pin D-type download port (behind hinged cover)

4.1.1

The top compartment contains labels for the:

● Serial number

● Current and voltage ratings.

FRONT PANEL COMPARTMENTS

P446SV-TM-EN-1 35

Chapter 3 - Hardware Design P446SV

The bottom compartment contains:

● A compartment for a 1/2 AA size backup battery (used to back up the real time clock and event, fault, and

disturbance records).

● A 9-pin female D-type front port for an EIA(RS)232 serial connection to a PC.

● A 25-pin female D-type parallel port for monitoring internal signals and downloading software and

language text.

4.1.2 KEYPAD

The keypad consists of the following keys:

4 arrow keys to navigate the menus (organised around the Enter key)

An enter key for executing the chosen option

A clear key for clearing the last command

A read key for viewing larger blocks of text (arrow keys now used for
scrolling)

2 hot keys for scrolling through the default display and for control of
setting groups. These are situated directly below the LCD display.

4.1.2.1 LIQUID CRYSTAL DISPLAY

The LCD is a high resolution monochrome display with 16 characters by 3 lines and controllable back light.

4.1.3

FRONT SERIAL PORT (SK1)

The front serial port is a 9-pin female D-type connector, providing RS232 serial data communication. It is situated
under the bottom hinged cover, and is used to communicate with a locally connected PC. It is used to transfer
settings data between the PC and the IED.

The port is intended for temporary connection during testing, installation and commissioning. It is not intended to
be used for permanent SCADA communications. This port supports the Courier communication protocol only.
Courier is a proprietary communication protocol to allow communication with a range of protection equipment,
and between the device and the Windows-based support software package.

This port can be considered as a DCE (Data Communication Equipment) port, so you can connect this port device
to a PC with an EIA(RS)232 serial cable up to 15 m in length.

The inactivity timer for the front port is set to 15 minutes. This controls how long the unit maintains its level of
password access on the front port. If no messages are received on the front port for 15 minutes, any password
access level that has been enabled is cancelled.

36 P446SV-TM-EN-1

P446SV Chapter 3 - Hardware Design

Note:
The front serial port does not support automatic extraction of event and disturbance records, although this data can be
accessed manually.

4.1.3.1 FRONT SERIAL PORT (SK1) CONNECTIONS

The port pin-out follows the standard for Data Communication Equipment (DCE) device with the following pin
connections on a 9-pin connector.

Pin number Description

2 Tx Transmit data
3 Rx Receive data
5 0 V Zero volts common

You must use the correct serial cable, or the communication will not work. A straight-through serial cable is
required, connecting pin 2 to pin 2, pin 3 to pin 3, and pin 5 to pin 5.

Once the physical connection from the unit to the PC is made, the PC’s communication settings must be set to
match those of the IED. The following table shows the unit’s communication settings for the front port.

Protocol Courier

Baud rate 19,200 bps
Courier address 1
Message format 11 bit - 1 start bit, 8 data bits, 1 parity bit (even parity), 1 stop bit

4.1.4 FRONT PARALLEL PORT (SK2)

The front parallel port uses a 25 pin D-type connector. It is used for commissioning, downloading firmware updates
and menu text editing.

4.1.5

Four fixed-function LEDs on the left-hand side of the front panel indicate the following conditions.

● Trip (Red) switches ON when the IED issues a trip signal. It is reset when the associated fault record is

● Alarm (Yellow) flashes when the IED registers an alarm. This may be triggered by a fault, event or

● Out of service (Yellow) is ON when the IED's functions are unavailable.

● Healthy (Green) is ON when the IED is in correct working order, and should be ON at all times. It goes OFF if

FIXED FUNCTION LEDS

cleared from the front display. Also the trip LED can be configured as self-resetting.

maintenance record. The LED flashes until the alarms have been accepted (read), then changes to
constantly ON. When the alarms are cleared, the LED switches OFF.

the unit’s self-tests show there is an error in the hardware or software. The state of the healthy LED is
reflected by the watchdog contacts at the back of the unit.

4.1.6

PROGRAMABLE LEDS

The device has a number of programmable LEDs, which can be associated with PSL-generated signals. The
programmable LEDs for most models are tri-colour and can be set to RED, YELLOW or GREEN. However the
programmable LEDs for some models are single-colour (red) only. The single-colour LEDs can be recognised by
virtue of the fact they are large and slightly oval, whereas the tri-colour LEDs are small and round.

P446SV-TM-EN-1 37

E00283

Chapter 3 - Hardware Design P446SV

5 REAR PANEL

The MiCOM P40Agile Modular series uses a modular construction. Most of the internal workings are on boards and
modules which fit into slots. Some of the boards plug into terminal blocks, which are bolted onto the rear of the
unit. However, some boards such as the communications boards have their own connectors. The rear panel
consists of these terminal blocks plus the rears of the communications boards.

The back panel cut-outs and slot allocations vary. This depends on the product, the type of boards and the
terminal blocks needed to populate the case. The following diagram shows the rear view of a 40TE. The IEC
61850-9-2LE interface is highlighted in grey.

Figure 7: Rear view of populated case

Note:
This diagram is a typical example and may not show the exact same arrangement of boards as your particular model. Refer
to the Cortec for product details.

38 P446SV-TM-EN-1

P446SV Chapter 3 - Hardware Design

6 BOARDS AND MODULES

Each product comprises a selection of PCBs (Printed Circuit Boards) and subassemblies, depending on the chosen
configuration.

6.1 PCBS

A PCB typically consists of the components, a front connector for connecting into the main system parallel bus via
a ribbon cable, and an interface to the rear. This rear interface may be:

● Directly presented to the outside world (as is the case for communication boards such as Ethernet Boards)

● Presented to a connector, which in turn connects into a terminal block bolted onto the rear of the case (as is

the case for most of the other board types)

Figure 8: Rear connection to terminal block

P446SV-TM-EN-1 39

Chapter 3 - Hardware Design P446SV

6.2 MAIN PROCESSOR BOARD

Figure 9: Main processor board

The main processor board performs all calculations and controls the operation of all other modules in the IED,
including the data communication and user interfaces. This is the only board that does not fit into one of the slots.
It resides in the front panel and connects to the rest of the system using an internal ribbon cable.

The LCD and LEDs are mounted on the processor board along with the front panel communication ports.
The memory on the main processor board is split into two categories: volatile and non-volatile. The volatile

memory is fast access SRAM, used by the processor to run the software and store data during calculations. The
non-volatile memory is sub-divided into two groups:

● Flash memory to store software code, text and configuration data including the present setting values.

● Battery-backed SRAM to store disturbance, event, fault and maintenance record data.

There are two board types available depending on the size of the case:

● For models in 40TE cases

● For models in 60TE cases and larger

40 P446SV-TM-EN-1

P446SV Chapter 3 - Hardware Design

6.3 POWER SUPPLY BOARD

Figure 10: Power supply board

The power supply board provides power to the unit. One of three different configurations of the power supply
board can be fitted to the unit. This is specified at the time of order and depends on the magnitude of the supply
voltage that will be connected to it.

There are three board types, which support the following voltage ranges:

● 24/54 V DC

● 48/125 V DC or 40-100V AC

● 110/250 V DC or 100-240V AC

The power supply board connector plugs into a medium duty terminal block. This terminal block is always
positioned on the right hand side of the unit looking from the rear.

The power supply board is usually assembled together with a relay output board to form a complete subassembly,
as shown in the following diagram.

P446SV-TM-EN-1 41

Chapter 3 - Hardware Design P446SV

Figure 11: Power supply assembly

The power supply outputs are used to provide isolated power supply rails to the various modules within the unit.
Three voltage levels are used by the unit’s modules:

● 5.1 V for all of the digital circuits

● +/- 16 V for the analogue electronics such as on the input board

● 22 V for driving the output relay coils.

All power supply voltages, including the 0 V earth line, are distributed around the unit by the 64-way ribbon cable.
The power supply board incorporates inrush current limiting. This limits the peak inrush current to approximately

10 A.
Power is applied to pins 1 and 2 of the terminal block, where pin 1 is negative and pin 2 is positive. The pin

numbers are clearly marked on the terminal block as shown in the following diagram.

42 P446SV-TM-EN-1

P446SV Chapter 3 - Hardware Design

Figure 12: Power supply terminals

6.3.1

The Watchdog contacts are also hosted on the power supply board. The Watchdog facility provides two output
relay contacts, one normally open and one normally closed. These are used to indicate the health of the device
and are driven by the main processor board, which continually monitors the hardware and software when the
device is in service.

WATCHDOG

P446SV-TM-EN-1 43

Chapter 3 - Hardware Design P446SV

Figure 13: Watchdog contact terminals

6.3.2

The rear serial port (RP1) is housed on the power supply board. This is a three-terminal EIA(RS)485 serial
communications port and is intended for use with a permanently wired connection to a remote control centre for
SCADA communication. The interface supports half-duplex communication and provides optical isolation for the
serial data being transmitted and received.

The physical connectivity is achieved using three screw terminals; two for the signal connection, and the third for
the earth shield of the cable. These are located on pins 16, 17 and 18 of the power supply terminal block, which is
on the far right looking from the rear. The interface can be selected between RS485 and K-bus. When the K-Bus
option is selected, the two signal connections are not polarity conscious.

The polarity independent K-bus can only be used for the Courier data protocol. The polarity conscious MODBUS,
IEC 60870-5-103 and DNP3.0 protocols need RS485.

The following diagram shows the rear serial port. The pin assignments are as follows:

● Pin 16: Earth shield

● Pin 17: Negative signal

● Pin 18: Positive signal

REAR SERIAL PORT

44 P446SV-TM-EN-1

RX

TX

LINK

ACTIVITY

Fibre optic
Ethernet
connections

RJ45 service
port for
commissioning
and testing only

E00227

RJ45

1
2
3
4
5
6
7
8

TX+
TX­RX+

RX-

P446SV Chapter 3 - Hardware Design

Figure 14: Rear serial port terminals

An additional serial port with D-type presentation is available as an optional board, if required.

6.4

Figure 15: IEC 61850-9-2LE board

IEC61850-9-2LE ETHERNET BOARD

Optical Fibre Connectors

The board uses 1300 nm multi mode 100BaseFx with ST connectors.

P446SV-TM-EN-1 45

Chapter 3 - Hardware Design P446SV

RJ45 Connector

This is a service port for commissioning and testing only. Do not use this for permanent connections.

LEDs

LED Function On Off Flashing

Green Link Link ok Link broken
Yellow Activity Traffic

Note:
The 9-2LE interface fibre port does not support auto negotiation. Ensure the Ethernet port of the device connected to the 9-2
LE interface fibre port is set to 100Mbps full duplex.

6.5

STANDARD OUTPUT RELAY BOARD

Figure 16: Standard output relay board - 8 contacts

This output relay board has 8 relays with 6 Normally Open contacts and 2 Changeover contacts.
The output relay board is provided together with the power supply board as a complete assembly, or

independently for the purposes of relay output expansion.
There are two cut-out locations in the board. These can be removed to allow power supply components to

protrude when coupling the output relay board to the power supply board. If the output relay board is to be used
independently, these cut-out locations remain intact.

The terminal numbers are as follows:

Terminal Number

Terminal 1 Relay 1 NO
Terminal 2 Relay 1 NO
Terminal 3 Relay 2 NO

46 P446SV-TM-EN-1

Output Relay

P446SV Chapter 3 - Hardware Design

Terminal Number Output Relay

Terminal 4 Relay 2 NO
Terminal 5 Relay 3 NO
Terminal 6 Relay 3 NO
Terminal 7 Relay 4 NO
Terminal 8 Relay 4 NO
Terminal 9 Relay 5 NO
Terminal 10 Relay 5 NO
Terminal 11 Relay 6 NO
Terminal 12 Relay 6 NO
Terminal 13 Relay 7 changeover
Terminal 14 Relay 7 changeover
Terminal 15 Relay 7 common
Terminal 16 Relay 8 changeover
Terminal 17 Relay 8 changeover
Terminal 18 Relay 8 common

6.6 IRIG-B BOARD

Figure 17: IRIG-B board

The IRIG-B board can be fitted to provide an accurate timing reference for the device. The IRIG-B signal is
connected to the board via a BNC connector. The timing information is used to synchronise the IED's internal real­time clock to an accuracy of 1 ms. The internal clock is then used for time tagging events, fault, maintenance and
disturbance records.

IRIG-B interface is available in modulated or demodulated formats.

P446SV-TM-EN-1 47

Chapter 3 - Hardware Design P446SV

The IRIG-B facility is provided in combination with other functionality on a number of additional boards, such as:

● Fibre board with IRIG-B

● Second rear communications board with IRIG-B

● Ethernet board with IRIG-B

● Redundant Ethernet board with IRIG-B

There are two types of each of these boards; one type which accepts a modulated IRIG-B input and one type
which accepts a demodulated IRIG-B input.

6.7

FIBRE OPTIC BOARD

Figure 18: Fibre optic board

This board provides an interface for communicating with a master station. This communication link can use all
compatible protocols (Courier, IEC 60870-5-103, MODBUS and DNP 3.0). It is a fibre-optic alternative to the metallic
RS485 port presented on the power supply terminal block. The metallic and fibre optic ports are mutually exclusive.

The fibre optic port uses BFOC 2.5 ST connectors.
The board comes in two varieties; one with an IRIG-B input and one without:

48 P446SV-TM-EN-1

P446SV Chapter 3 - Hardware Design

6.8 REAR COMMUNICATION BOARD

Figure 19: Rear communication board

The optional communications board containing the secondary communication ports provide two serial interfaces
presented on 9 pin D-type connectors. These interfaces are known as SK4 and SK5. Both connectors are female
connectors, but are configured as DTE ports. This means pin 2 is used to transmit information and pin 3 to receive.

SK4 can be used with RS232, RS485 and K-bus. SK5 can only be used with RS232 and is used for electrical
teleprotection. The optional rear communications board and IRIG-B board are mutually exclusive since they use
the same hardware slot. However, the board comes in two varieties; one with an IRIG-B input and one without.

6.9

ETHERNET BOARD

Figure 20: Ethernet board

P446SV-TM-EN-1 49

Chapter 3 - Hardware Design P446SV

This is a communications board that provides a standard 100-Base Ethernet interface. This board supports one
electrical copper connection and one fibre-pair connection.

There are several variants for this board as follows:

● 100 Mbps Ethernet board

● 100 Mbps Ethernet with on-board modulated IRIG-B input

● 100 Mbps Ethernet with on-board unmodulated IRIG-B input

Two of the variants provide an IRIG-B interface. IRIG-B provides a timing reference for the unit – one board for
modulated IRIG-B and one for demodulated. The IRIG B signal is connected to the board with a BNC connector.

The Ethernet and other connection details are described below:

IRIG-B Connector

● Centre connection: Signal

● Outer connection: Earth

LEDs

LED Function On Off Flashing

Green Link Link ok Link broken
Yellow Activity Traffic

Optical Fibre Connectors

Connector Function

Rx Receive
Tx Transmit

RJ45connector

Pin Signal name Signal definition

1 TXP Transmit (positive)
2 TXN Transmit (negative)
3 RXP Receive (positive)
4 - Not used
5 - Not used
6 RXN Receive (negative)
7 - Not used
8 - Not used

50 P446SV-TM-EN-1

IRIG-B

Pin3

Link Fail

connector

Pin 2

Pin 1

Link channel

A (green LED)

Activity channel

A (yellow LED)

Link channel B

(green LED)

Activity channel B

(yellow LED)

A

B

C

D

V01009

P446SV Chapter 3 - Hardware Design

6.10 REDUNDANT ETHERNET BOARD

Figure 21: Redundant Ethernet board

This board provides dual redundant Ethernet (supported by two fibre pairs) together with an IRIG-B interface for
timing.

Different board variants are available, depending on the redundancy protocol and the type of IRIG-B signal
(unmodulated or modulated). The available redundancy protocols are:

● SHP (Self healing Protocol)

● RSTP (Rapid Spanning Tree Protocol)

● DHP (Dual Homing Protocol)

● PRP (Parallel Redundancy Protocol)

There are several variants for this board as follows:

● 100 Mbps redundant Ethernet running RSTP, with on-board modulated IRIG-B

● 100 Mbps redundant Ethernet running RSTP, with on-board unmodulated IRIG-B

● 100 Mbps redundant Ethernet running SHP, with on-board modulated IRIG-B

● 100 Mbps redundant Ethernet running SHP, with on-board unmodulated IRIG-B

● 100 Mbps redundant Ethernet running DHP, with on-board modulated IRIG-B

● 100 Mbps redundant Ethernet running DHP, with on-board unmodulated IRIG-B

● 100 Mbps redundant Ethernet running PRP, with on-board modulated IRIG-B

● 100 Mbps redundant Ethernet running PRP, with on-board demodulated IRIG-B

The Ethernet and other connection details are described below:

IRIG-B Connector

● Centre connection: Signal

● Outer connection: Earth

P446SV-TM-EN-1 51

Chapter 3 - Hardware Design P446SV

Link Fail Connector (Ethernet Board Watchdog Relay)

Pin Closed Open

1-2 Link fail Channel 1 (A) Link ok Channel 1 (A)
2-3 Link fail Channel 2 (B) Link ok Channel 2 (B)

LEDs

LED Function On Off Flashing

Green Link Link ok Link broken
Yellow Activity SHP running PRP, RSTP or DHP traffic

Optical Fibre Connectors (ST)

Connector DHP RSTP SHP PRP

A RXA RX1 RS RXA
B TXA TX1 ES TXA
C RXB RX2 RP RXB
D TXB TX2 EP TXB

RJ45connector

Pin Signal name Signal definition

1 TXP Transmit (positive)
2 TXN Transmit (negative)
3 RXP Receive (positive)
4 - Not used
5 - Not used
6 RXN Receive (negative)
7 - Not used
8 - Not used

52 P446SV-TM-EN-1

P446SV Chapter 3 - Hardware Design

6.11 COPROCESSOR BOARD

Figure 22: Fully populated Coprocessor board

Note:
The above figure shows a coprocessor complete with GPS input and 2 fibre-optic serial data interfaces, and is not necessarily
representative of the product and model described in this manual. These interfaces will not be present on boards that do not
require them.

Where applicable, a second processor board is used to process the special algorithms associated with the device.
This second processor board provides fast access (zero wait state) SRAM for use with both program and data
memory storage. This memory can be accessed by the main processor board via the parallel bus. This is how the
software is transferred from the flash memory on the main processor board to the coprocessor board on power
up. Further communication between the two processor boards is achieved via interrupts and the shared SRAM.
The serial bus carrying the sample data is also connected to the co-processor board, using the processor’s built-in
serial port, as on the main processor board.

There are several different variants of this board, which can be chosen depending on the exact device and model.
The variants are:

● Coprocessor board with current differential inputs and GPS input

● Coprocessor board with current differential inputs only

● Coprocessor board with GPS input only

6.11.1

COPROCESSOR BOARD WITH 1PPS INPUT

In some applications, where the communication links between two remote devices are provided by a third party
telecommunications partner, the transmit and receive paths associated with one channel may differ considerably
in length, resulting in very different transmission and receive times.

If, for example, Device A is transmitting to Device B information about the value of its measured current, the
information Device A is receiving from Device B about the current measured at the same time, may reach device B
at a different time. This has to be compensated for. A 1pps GPS timing signal applied to both devices will help the
IEDs achieve this, because it is possible to measure the exact time taken for both transmission and receive paths.

P446SV-TM-EN-1 53

Chapter 3 - Hardware Design P446SV

Note:
The 1 pps signal is always supplied by a GPS receiver (such as a P594).

Note:
This signal is used to control the sampling process, and timing calculations and is not used for time stamping or real time
synchronisation.

6.12

HIGH BREAK OUTPUT RELAY BOARD

Figure 23: High Break relay output board

A High Break output relay board is available as an option. It comprises four normally open output contacts, which
are suitable for high breaking loads.

A High Break contact consists of a high capacity relay with a MOSFET in parallel with it. The MOSFET has a varistor
placed across it to provide protection, which is required when switching off inductive loads. This is because the
stored energy in the inductor causes a high reverse voltage that could damage the MOSFET, if not protected.

When there is a control input command to operate an output contact the miniature relay is operated at the same
time as the MOSFET. The miniature relay contact closes in nominally 3.5 ms and is used to carry the continuous
load current. The MOSFET operates in less than 0.2 ms, but is switched off after 7.5 ms.

When the control input is reset, the MOSFET is again turned on for 7.5 mS. The miniature relay resets in nominally

3.5 ms before the MOSFET. This means the MOSFET is used to break the load. The MOSFET absorbs the energy
when breaking inductive loads and so limits the resulting voltage surge. This contact arrangement is for switching
DC circuits only.

The board number is:

● ZN0042 001

High Break Contact Operation

The following figure shows the timing diagram for High Break contact operation.

54 P446SV-TM-EN-1

V00246

3.5ms + contact bounce

Load current

Relay contact

Databus
control input

MOSFET reset

MOSFET operate

on

7ms

on

3.5ms

Closed

on

7ms

off

P446SV Chapter 3 - Hardware Design

Figure 24: High Break contact operation

High Break Contact Applications

● Efficient scheme engineering

● Accessibility of CB auxiliary contacts

● Breaker fail

● Initiation of teleprotection

In traditional hard wired scheme designs, High Break capability could only be achieved using external
electromechanical trip relays. Instead, these internal High Break contacts can be used thus reducing space
requirements.

It is common practise to use circuit breaker 52a (CB Closed) auxiliary contacts to break the trip coil current
on breaker opening, thereby easing the duty on the protection contacts. In some cases (such as operation
of disconnectors, or retrofitting), it may be that 52a contacts are either unavailable or unreliable. In such
cases, High Break contacts can be used to break the trip coil current in these applications.

In the event of failure of the local circuit breaker (stuck breaker), or defective auxiliary contacts (stuck
contacts), it is incorrect to use 52a contact action. The interrupting duty at the local breaker then falls on the
relay output contacts, which may not be rated to perform this duty. High Break contacts should be used in
this case to avoid the risk of burning out relay contacts.

The High Break contacts also offer fast making, which results in faster tripping. In addition, fast keying of
teleprotection is a benefit. Fast keying bypasses the usual contact operation time, such that permissive,
blocking and intertrip commands can be routed faster.

P446SV-TM-EN-1 55

Warning:
These relay contacts are POLARITY SENSITIVE. External wiring must comply with the polarity
requirements described in the external connection diagram to ensure correct operation.

Chapter 3 - Hardware Design P446SV

56 P446SV-TM-EN-1

CHAPTER 4

SOFTWARE DESIGN

Chapter 4 - Software Design P446SV

58 P446SV-TM-EN-1

P446SV Chapter 4 - Software Design

1 CHAPTER OVERVIEW

This chapter describes the software design of the IED.
This chapter contains the following sections:
Chapter Overview 59
Sofware Design Overview 60
System Level Software 61
Platform Software 64
Protection and Control Functions 65

P446SV-TM-EN-1 59

V00307

R

e

c

o

r

d

s

P

r

o

t

e

c

t

i

o

n

a

n

d

c

o

n

t

r

o

l

s

e

t

t

i

n

g

s

Protection and Control Software Layer

Fault locator

task

Disturbance

recorder task

Sampling function

Control of output contacts
and programmable LEDs

Sample data + digital
logic inputs

System Level Software Layer

System services (e.g. device drivers) / Real time operating system / Self-diagnostic software

Control of interfaces to keypad , LCD, LEDs,
front & rear ports.
Self-checking maintenance records

Hardware Device Layer

LEDs / LCD / Keypad / Memory / FPGA

Protection Task

Programmable & fixed

scheme logic

Signal processing

Coprocessor protection

algorithms

Supervisor task

Platform Software Layer

Event, fault,

disturbance,

maintenance record

logging

Remote

communications

interfaces

Front panel

interface

(LCD + Keypad)

Local

communications

interfaces

Settings database

Protection algorithms

Chapter 4 - Software Design P446SV

2 SOFWARE DESIGN OVERVIEW

The device software can be conceptually categorized into several elements as follows:

● The system level software

● The platform software

● The protection and control software

These elements are not distinguishable to the user, and the distinction is made purely for the purposes of
explanation. The following figure shows the software architecture.

Figure 25: Software Architecture

The software, which executes on the main processor, can be divided into a number of functions as illustrated
above. Each function is further broken down into a number of separate tasks. These tasks are then run according
to a scheduler. They are run at either a fixed rate or they are event driven. The tasks communicate with each other
as and when required.

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P446SV Chapter 4 - Software Design

3 SYSTEM LEVEL SOFTWARE

3.1 REAL TIME OPERATING SYSTEM

The real-time operating system is used to schedule the processing of the various tasks. This ensures that they are
processed in the time available and in the desired order of priority. The operating system also plays a part in
controlling the communication between the software tasks, through the use of operating system messages.

3.2

The system services software provides the layer between the hardware and the higher-level functionality of the
platform software and the protection and control software. For example, the system services software provides
drivers for items such as the LCD display, the keypad and the remote communication ports. It also controls things
like the booting of the processor and the downloading of the processor code into RAM at startup.

3.3

The device includes several self-monitoring functions to check the operation of its hardware and software while in
service. If there is a problem with the hardware or software, it should be able to detect and report the problem, and
attempt to resolve the problem by performing a reboot. In this case, the device would be out of service for a short
time, during which the ‘Healthy’ LED on the front of the device is switched OFF and the watchdog contact at the
rear is ON. If the restart fails to resolve the problem, the unit takes itself permanently out of service; the ‘Healthy’
LED stays OFF and watchdog contact stays ON.

If a problem is detected by the self-monitoring functions, the device attempts to store a maintenance record to
allow the nature of the problem to be communicated to the user.

The self-monitoring is implemented in two stages: firstly a thorough diagnostic check which is performed on boot­up, and secondly a continuous self-checking operation, which checks the operation of the critical functions whilst
it is in service.

3.4

The self-testing takes a few seconds to complete, during which time the IED's measurement, recording, control,
and protection functions are unavailable. On a successful start-up and self-test, the ‘health-state’ LED on the front
of the unit is switched on. If a problem is detected during the start-up testing, the device remains out of service
until it is manually restored to working order.

SYSTEM SERVICES SOFTWARE

SELF-DIAGNOSTIC SOFTWARE

STARTUP SELF-TESTING

The operations that are performed at start-up are:

1. System boot

2. System software initialisation

3. Platform software initialisation and monitoring

3.4.1

The integrity of the Flash memory is verified using a checksum before the program code and stored data is loaded
into RAM for execution by the processor. When the loading has been completed, the data held in RAM is compared
to that held in the Flash memory to ensure that no errors have occurred in the data transfer and that the two are
the same. The entry point of the software code in RAM is then called. This is the IED's initialisation code.

P446SV-TM-EN-1 61

SYSTEM BOOT

Chapter 4 - Software Design P446SV

3.4.2 SYSTEM LEVEL SOFTWARE INITIALISATION

The initialization process initializes the processor registers and interrupts, starts the watchdog timers (used by the
hardware to determine whether the software is still running), starts the real-time operating system and creates
and starts the supervisor task. In the initialization process the device checks the following:

● The status of the backup battery

● The integrity of the battery-backed SRAM that is used to store event, fault and disturbance records

● The operation of the LCD controller

● The watchdog operation

At the conclusion of the initialization software the supervisor task begins the process of starting the platform
software. Coprocessor board checks are also made as follows:

● A check is made for the presence of the coprocessor board

● The RAM on the coprocessor board is checked with a test bit pattern before the coprocessor board is

transferred from flash memory

If any of these checks produces an error, the coprocessor board is left out of service. The other protection
functions provided by the main processor board are left in service.

3.4.3

When starting the platform software, the IED checks the following:

● The integrity of the data held in non-volatile memory (using a checksum)

● The operation of the real-time clock

● The optional IRIG-B function (if applicable)

● The presence and condition of the input board

● The analog data acquisition system (it does this by sampling the reference voltage)

At the successful conclusion of all of these tests the unit is entered into service and the application software is
started up.

3.5

When the IED is in service, it continually checks the operation of the critical parts of its hardware and software. The
checking is carried out by the system services software and the results are reported to the platform software. The
functions that are checked are as follows:

● The Flash memory containing all program code and language text is verified by a checksum.

● The code and constant data held in system memory is checked against the corresponding data in Flash

● The system memory containing all data other than the code and constant data is verified with a checksum.

● The integrity of the digital signal I/O data from the opto-inputs and the output relay coils is checked by the

● The operation of the analog data acquisition system is continuously checked by the acquisition function

● The operation of the optional Ethernet board is checked by the software on the main processor card. If the

● The operation of the optional IRIG-B function is checked by the software that reads the time and date from

In the event that one of the checks detects an error in any of the subsystems, the platform software is notified and
it attempts to log a maintenance record.

PLATFORM SOFTWARE INITIALISATION AND MONITORING

CONTINUOUS SELF-TESTING

memory to check for data corruption.

data acquisition function every time it is executed.

every time it is executed. This is done by sampling the reference voltages.

Ethernet board fails to respond an alarm is raised and the card is reset in an attempt to resolve the problem.

the board.

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P446SV Chapter 4 - Software Design

If the problem is with the battery status or the IRIG-B board, the device continues in operation. For problems
detected in any other area, the device initiates a shutdown and re-boot, resulting in a period of up to 10 seconds
when the functionality is unavailable.

A restart should clear most problems that may occur. If, however, the diagnostic self-check detects the same
problem that caused the IED to restart, it is clear that the restart has not cleared the problem, and the device takes
itself permanently out of service. This is indicated by the ‘’health-state’ LED on the front of the device, which
switches OFF, and the watchdog contact which switches ON.

P446SV-TM-EN-1 63

Chapter 4 - Software Design P446SV

4 PLATFORM SOFTWARE

The platform software has three main functions:

● To control the logging of records generated by the protection software, including alarms, events, faults, and

maintenance records

● To store and maintain a database of all of the settings in non-volatile memory

● To provide the internal interface between the settings database and the user interfaces, using the front

panel interface and the front and rear communication ports

4.1

The logging function is used to store all alarms, events, faults and maintenance records. The records are stored in
non-volatile memory to provide a log of what has happened. The IED maintains four types of log on a first in first
out basis (FIFO). These are:

● Alarms

● Event records

● Fault records

● Maintenance records

The logs are maintained such that the oldest record is overwritten with the newest record. The logging function
can be initiated from the protection software. The platform software is responsible for logging a maintenance
record in the event of an IED failure. This includes errors that have been detected by the platform software itself or
errors that are detected by either the system services or the protection software function. See the Monitoring and
Control chapter for further details on record logging.

4.2

The settings database contains all the settings and data, which are stored in non-volatile memory. The platform
software manages the settings database and ensures that only one user interface can modify the settings at any
one time. This is a necessary restriction to avoid conflict between different parts of the software during a setting
change.

Changes to protection settings and disturbance recorder settings, are first written to a temporary location SRAM
memory. This is sometimes called 'Scratchpad' memory. These settings are not written into non-volatile memory
immediately. This is because a batch of such changes should not be activated one by one, but as part of a
complete scheme. Once the complete scheme has been stored in SRAM, the batch of settings can be committed to
the non-volatile memory where they will become active.

RECORD LOGGING

SETTINGS DATABASE

4.3

The settings and measurements database must be accessible from all of the interfaces to allow read and modify
operations. The platform software presents the data in the appropriate format for each of the interfaces (LCD
display, keypad and all the communications interfaces).

64 P446SV-TM-EN-1

INTERFACES

P446SV Chapter 4 - Software Design

5 PROTECTION AND CONTROL FUNCTIONS

The protection and control software processes all of the protection elements and measurement functions. To
achieve this it has to communicate with the system services software, the platform software as well as organise its
own operations.

The protection task software has the highest priority of any of the software tasks in the main processor board. This
ensures the fastest possible protection response.

The protection and control software provides a supervisory task, which controls the start-up of the task and deals
with the exchange of messages between the task and the platform software.

5.1

After initialization, the protection and control task waits until there are enough samples to process. The acquisition
of samples on the main processor board is controlled by a ‘sampling function’ which is called by the system
services software.

This sampling function takes samples from the input module and stores them in a two-cycle FIFO buffer. These
samples are also stored concurrently by the coprocessor. The sample rate is 48 samples per cycle. This results in a
nominal sample rate of 2,400 samples per second for a 50 hz system and 2,880 samples per second for a 60 Hz
system. However the sample rate is not fixed. It tracks the power system frequency as described in the next
section.

In normal operation, the protection task is executed 16 times per cycle.

5.2

The device provides a frequency tracking algorithm so that there are always 48 samples per cycle irrespective of
frequency drift. The frequency range in which 48 samples per second are provided is between 45 Hz and 66 z. If
the frequency falls outside this range, the sample rate reverts to its default rate of 2,400 Hz for 50 Hz or 2,880 Hz
for 60 Hz.

The frequency tracking of the analog input signals is achieved by a recursive Fourier algorithm which is applied to
one of the input signals. It works by detecting a change in the signal’s measured phase angle. The calculated value
of the frequency is used to modify the sample rate being used by the input module, in order to achieve a constant
sample rate per cycle of the power waveform. The value of the tracked frequency is also stored for use by the
protection and control task.

ACQUISITION OF SAMPLES

FREQUENCY TRACKING

The frequency tracks off any voltage or current in the order VA, VB, VC, IA, IB, IC, down to 10%Vn for voltage and
5%In for current.

5.3

Most of the IED’s protection functionality uses the Fourier components calculated by the device’s signal processing
software. However RMS measurements and some special protection algorithms available in some products use
the sampled values directly.

The disturbance recorder also uses the samples from the input module, in an unprocessed form. This is for
waveform recording and the calculation of true RMS values of current, voltage and power for metering purposes.

In the case of special protection algorithms, using the sampled values directly provides exceptionally fast response
because you do not have to wait for the signal processing task to calculate the fundamental. You can act on the
sampled values immediately.

5.4

The current and voltage inputs are filtered using Finite Impulse Response (FIR) digital filters. This reduces the
effects of non-power frequency components in the input signals, such as DC offsets in current waveforms, and

P446SV-TM-EN-1 65

DIRECT USE OF SAMPLE VALUES

DISTANCE PROTECTION

E00308

Filter Response

Gain

Harmonic

Full

Quarter

Half

0 18

15

129

63

0.5

1

2

1.5

0

21

2.5

Chapter 4 - Software Design P446SV

capacitor voltage transformer (CVT) transients in the voltages. The device uses a combination of a 1/4 cycle filter
using 12 coefficients, a 1/2 cycle filter using 24 coefficients, and a single cycle filter using 48 coefficients. The
device automatically performs intelligent switching in the application of the filters, to select the best balance of
removal of transients with fast response. The protection elements themselves then perform additional filtering,
implemented for example, by the trip count strategy.

The following figure shows the frequency response of the 12, 24 and 48 coefficient filters, noting that all have a
gain of unity at the fundamental frequency:

Figure 26: Frequency response of FIR filters

5.5

FOURIER SIGNAL PROCESSING

All backup protection and measurement functions use single-cycle fourier digital filtering to extract the power
frequency component. This filtering is performed on the main processor board.

When the protection and control task is re-started by the sampling function, it calculates the Fourier components
for the analog signals. Although some protection algorithms use some Fourier-derived harmonics (e.g. second
harmonic for magnetizing inrush), most protection functions are based on the Fourier-derived fundamental
components of the measured analog signals. The Fourier components of the input current and voltage signals are
stored in memory so that they can be accessed by all of the protection elements’ algorithms.

The Fourier components are calculated using single-cycle Fourier algorithm. This Fourier algorithm always uses
the most recent 48 samples from the 2-cycle buffer.

Most protection algorithms use the fundamental component. In this case, the Fourier algorithm extracts the power
frequency fundamental component from the signal to produce its magnitude and phase angle. This can be
represented in either polar format or rectangular format, depending on the functions and algorithms using it.

The Fourier function acts as a filter, with zero gain at DC and unity gain at the fundamental, but with good
harmonic rejection for all harmonic frequencies up to the nyquist frequency. Frequencies beyond this nyquist
frequency are known as alias frequencies, which are introduced when the sampling frequency becomes less than
twice the frequency component being sampled. However, the Alias frequencies are significantly attenuated by an
anti-aliasing filter (low pass filter), which acts on the analog signals before they are sampled. The ideal cut-off point
of an anti-aliasing low pass filter would be set at:

(samples per cycle) ´ (fundamental frequency)/2

At 48samples per cycle, this would be nominally 1200 Hz for a 50 Hz system, or 1440 Hz for a 60 Hz system.
The following figure shows the nominal frequency response of the anti-alias filter and the Fourier filter for a 48-

sample single cycle fourier algorithm acting on the fundamental component:

66 P446SV-TM-EN-1

Ideal anti-alias filter response

Real anti-alias filter

response

2 3...

1

0.2

0.4

0.6

0.8

241

50 Hz 1200 Hz 2400 Hz

V00306

Fourier Response

without anti-alias filter

Fourier Response

with anti-alias filter

Alias frequency

P446SV Chapter 4 - Software Design

Figure 27: Frequency Response (indicative only)

5.6

PROGRAMMABLE SCHEME LOGIC

The purpose of the programmable scheme logic (PSL) is to allow you to configure your own protection schemes to
suit your particular application. This is done with programmable logic gates and delay timers. To allow greater
flexibility, different PSL is allowed for each of the four setting groups.

The input to the PSL is any combination of the status of the digital input signals from the opto-isolators on the
input board, the outputs of the protection elements such as protection starts and trips, and the outputs of the fixed
protection scheme logic (FSL). The fixed scheme logic provides the standard protection schemes. The PSL consists
of software logic gates and timers. The logic gates can be programmed to perform a range of different logic
functions and can accept any number of inputs. The timers are used either to create a programmable delay,
and/or to condition the logic outputs, such as to create a pulse of fixed duration on the output regardless of the
length of the pulse on the input. The outputs of the PSL are the LEDs on the front panel of the relay and the output
contacts at the rear.

The execution of the PSL logic is event driven. The logic is processed whenever any of its inputs change, for
example as a result of a change in one of the digital input signals or a trip output from a protection element. Also,
only the part of the PSL logic that is affected by the particular input change that has occurred is processed. This
reduces the amount of processing time that is used by the PSL. The protection & control software updates the logic
delay timers and checks for a change in the PSL input signals every time it runs.

The PSL can be configured to create very complex schemes. Because of this PSL desing is achieved by means of a
PC support package called the PSL Editor. This is available as part of the settings application software MiCOm S1
Agile, or as a standalone software module.

5.7

EVENT RECORDING

A change in any digital input signal or protection element output signal is used to indicate that an event has taken
place. When this happens, the protection and control task sends a message to the supervisor task to indicate that
an event is available to be processed and writes the event data to a fast buffer controlled by the supervisor task.
When the supervisor task receives an event record, it instructs the platform software to create the appropriate log
in non-volatile memory (battery backed-up SRAM). The operation of the record logging to battery backed-up SRAM
is slower than the supervisor buffer. This means that the protection software is not delayed waiting for the records
to be logged by the platform software. However, in the rare case when a large number of records to be logged are
created in a short period of time, it is possible that some will be lost, if the supervisor buffer is full before the
platform software is able to create a new log in battery backed-up SRAM. If this occurs then an event is logged to
indicate this loss of information.

Maintenance records are created in a similar manner, with the supervisor task instructing the platform software to
log a record when it receives a maintenance record message. However, it is possible that a maintenance record
may be triggered by a fatal error in the relay in which case it may not be possible to successfully store a
maintenance record, depending on the nature of the problem.

P446SV-TM-EN-1 67

Chapter 4 - Software Design P446SV

For more information, see the Monitoring and Control chapter.

5.8 DISTURBANCE RECORDER

The disturbance recorder operates as a separate task from the protection and control task. It can record the
waveforms for up to 12 calibrated analog channels and the values of up to 32 digital signals. The recording time is
user selectable. Up to 50 seconds of data can be recorded. A minimum number of 5 records with a capacity of 10
seconds each, up to a maximum of 50 records with a capacity of 10 seconds each can be set. The disturbance
recorder is supplied with data by the protection and control task once per cycle. The disturbance recorder collates
the data that it receives into the required length disturbance record. The disturbance records can be extracted by
settings application software such as MiCOM S1 Agile, which can also store the data in COMTRADE format,
therefore allowing the use of other packages to view the recorded data.

For more information, see the Monitoring and Control chapter.

5.9

The fault locator uses 12 cycles of the analog input signals to calculate the fault location. The result is returned to
the protection and control task, which includes it in the fault record. The pre-fault and post-fault voltages are also
presented in the fault record. When the fault record is complete, including the fault location, the protection and
control task sends a message to the supervisor task to log the fault record.

The Fault Locator is not available on all models.

5.10

The function keys interface directly into the PSL as digital input signals. A change of state is only recognized when
a key press is executed on average for longer than 200 ms. The time to register a change of state depends on
whether the function key press is executed at the start or the end of a protection task cycle, with the additional
hardware and software scan time included. A function key press can provide a latched (toggled mode) or output
on key press only (normal mode) depending on how it is programmed. It can be configured to individual protection
scheme requirements. The latched state signal for each function key is written to non-volatile memory and read
from non-volatile memory during relay power up thus allowing the function key state to be reinstated after power­up, should power be inadvertently lost.

FAULT LOCATOR

FUNCTION KEY INTERFACE

68 P446SV-TM-EN-1