CRITIKON,
4.3.3
On/Off
Low
INC.
Control
Battery
and
Shutdown
Quad
CMOS
voltage
was
available.
bistable
is
this
one
switched
supplies
When
reference
comparator
latch
set
turns
monitor
of
switching
limited
selected
flip-flop
set
and
flip-flop
junction
supply
power
the
the
bistable
by
UA,
off
the
trom
positive
gate
U5
to a safe
so
that
This
prevents
USA
reset
by
drives
drop
below
is
to
emitter
voltage,
Vs
of
of
U1A,
turning
flip-flop.
turns
monitor
deep
feedback
Vs.
SECTION
is
powered
value
it
draws
no
discharging
and
USB
the
front
panei
the
base
of
the
CMOS
limited
reference
Q8
discharging
Q12
conducts
off,
removing
and
to
reference
to
about
shunt
is
at
on
the
If
the
unlatches
4.
PRINCIPLES
at
all
times
by
Zener
diode
current
stores
the
least
and
regulated
input
the
when
the
battery
the
on/off
ON
and
OFF
emitter-follower,
gate
supply
13.4
Vdc.
regulator,
one
junction
supplies
supplies.
voltage
power
from
the
on/off
battery.
U4
for
threshold
from
Vp,
with
CR7.
This
only
battery
when
the
state
of
switches.
Q12,
voltage.
This
emitter-follower
U4,
and
the
drop
above
power
falls
the
R34
(Vs)
Vs
below
comparator.
flip-flop,
supplies a small
hysteresis
OF
OPERATION
its
supply
zener
voltage
power
is
unit
is
off.
the
monitor
The
output
whose
is
the
preventing
Thus,
this
emitter
the
to
the
fed
back
threshold
This
and
output
of
amount
fast
The
and
of
is
output
Q8.
to
action
the
4.3.4
Logic
Master
4.3.5
Battery
System
Reset
Charger.
4.4
CPU
BOARD
OPERATION
Circuit
Circuit
When
Vs
is
off,
(RESET-0)
through
unasserted
C13
through
removal
When
from a separate
This
charge
on
Q6
current
the
feedback
Operating
output
Vdc).
The
CPU
in
Section
R42.
of
line
IC
drives
the
when
limit
voltage
«
»
*
*
«
+
+
asserted.
After a delay
and
R33
Vs
to
power
switching
battery.
the
input
network
so
the
board
6.
The
the
microprocessor
the
analog
the
switchpanel
the
display
the
pneumatics
the
fail-safe
the
external
gate
U5
When
allows
and
re-arm
is
available,
DC
supply,
Resistor
current
of
U3,
from
battery
(float)
to
circuits
circuits
subsystem,
board
turns
on
FET
Q10,
holding
Vs
switches
of
about
the
processor
the
open-collector
the
time
delay
the
switching
Vbc,
supplied
transistor
exceeds
reducing
is
not
the
are
are
interface
module
timer
communications & control
Q11
R30
senses
about
the
the
battery
discharged.
proper
shown
divided
system,
interface
circuit,
on,
C13
40
to
104
milliseconds,
to
start.
Diode,
output
circuit.
regulator
by
rectifiers
which
supplies
the
charging
350
milliamps.
pulse
width.
when
the
R12
adjusts
value
for
the
on
schematic
into 7 functional
circuits,
circuits,
interface
and
circuits,
the
reset
begins
CR15,
of
U5-3
U3
receives
CR8
power
current
Q6
FET
Q2
battery
battery
charger
the
(generally
SC315-293
circuits;
circuits.
line
to
charge
RESET-0
discharges
quickly
upon
power
and
CR9.
from
and
drives
disconnects
is
maximum
contained
Vp
to
turns
the
not
13.65
is
81
DINAMAP™
VITAL
4.4.1
Microprocessor
SIGNS
System
MONITOR
MODEL
The
bit
EPROM
digital
8100T
SERVICE
microprocessor
MANUAL
system
consists
microprocessor, a custom-designed
circuit,
1/0,
one
8K x 8
and a digital
output
Static
RAM,
latch.
of a master
gate
array
an
analog-to-digital
clock
circuit, a CMOS
circuit, a 32K
x 8
converter
8-
with
4.4.1.1
shown
MASTER
on
sheet 2 of
R1, R2, C1, C2,
‘oscillator.
fundamental
to
the
clocks
the
Interface
4.4.1.2
circuit
a
CMOS
a
16-bit
32K
storage
program.
The
pulses
gate
AGIA
interrupt
generated
performed
controlled
ACIA ( U6),
transfers
The
frequency
gate
array,
for
the
1.8432
MHz
Adapter
MICROPROCESSOR
is
shown
6309E,
address
EPROM
(as
long
is.
provided
6309E
and
array,
requires
these
U2.
interrupt
request
by
by
by
and
from
CPU
and
the
CLOCK
the
schematic.
C3 and
clock
clock
on
8-bit
bus
as
Y1,
circuit
of
3.6864
U2,
where
at
0.9216
(UCLK)
(ACIA)
.
sheet 2 of
processor.
which
to
communicate
power
by
two,
externally
are
derived
The
interrupt
which
is
enabled
liné
at
U1-4,
the
gate
array,
the
operating
microprocessor
the
a/d
converter
or
to
the
data
CIRCUIT.
configured
oscillates
it
is
divided
Mhz,
for
The
It
consists
to
form a crystal-controlled
between
MHz.
The
down
the 2 millisecond
the
Asynchronous
CIRCUIT.
the
schematic.
It
has
an
it
uses
to
address
with
various
is
on)
for
data
generated
8K
by
8-bit-
CMOS
generated E (U1-34)
from
the
master
request
FIRQ,
U2,
program.
line
or
disabled
is
which
The
and
is
and
digital
at
driven
triggers
used
bus.
masier
CMOS
master
to
of
CMOS
provide
clock
logic
clock
FIRQ
Communications
The
microprocessor
The
microprocessor,
8-bit
bidirectional
the
stored
I/O
devices.
by
static
RAM's.
and Q (U1-35)
clock
and
U1-3,
IRQ,
under
software
by
the
1200
all
the
read/write
by
the
YO
(U7),
circuit
inverter,
levels
is
sent
the E and
interrupt,
data
program
Temporary
the
operating
generated
is
driven
control.
Hz
interrupt
background
line
at
U1-32
gate
array
for
gating
is
US,
at
a
directly
Q
and
U1,
bus
and
in
the
clock
by
the
by
the
The
tasks
is
(U2),
the
data
is
82
The
reset
line
connector
J5-18
depressions.
4.4.1.3
sheet 2 of
high
clock
the
High
functions,
gate
following
and,
GATE
the
order
address
functions,
failsafe
order
timer
address
for
array,
and
table
where
applicable,
(U1-37)
is
in
response
ARRAY
schematic.
decoding,
controlling
reset
pulse,
decoding
generating
for
generating
defines
the
shows
driven
to
by
POWER
CIRCUIT.
It
is a custom
dividing
the
processor
and
is
provided
certain
select
certain
addresses
the
the
power
ON
The
gate
-designed
the
interrupt
discrete
for
signals
discrete
decoded,
output
pin
supply
and
POWER
array
master
digital
clock
/O.
addressing
for
digital
specifies
and
signal
module
circuit
circuit
that
to
(FIRQ),
certain
devices
I/O
signals.
name:
through
OFF
switch
is
shown
provides
obtain
various
controlling
internal
external
to
The
their
function
on
for
the
CRITIKON,
INC,
SECTION
4.
PRINCIPLES
OF
OPERATION
4.4.1
Microprocessor
Continued
System
ADD
0000H
0800H
1000H
2000H
2800H
3000H
3100H
8200H
3300H
3400H
3500H
3600H
3700H
3800H
3900H
3A00H
3B00H
8C00H
3D00H
3E00H
SFOOH
4000H
8000H
COCOH
A
clock
(ZOSC)
S
to
07FFH
to
OFFFH
to
1FFFH
to
27FFH
to
2FFFH
to
30FFH
to
31FFH
to
32FFH
to
33FFH
to
34FFH
to
35FFH
to
36FFH
to
37FFH
to
38FFH
to
39FFH
to
3AFFH
to
3BFFH
to
SCFFH
to
3DFFH
to
SEFFH
to
3FFFH
to
7FFFH
toBFFFH
to
divider
and
and Q clock
clocks
the
kHz)
1.8432
ACIA
is
used
by
are
MHz
divided
the
FFFFH
circuit
divides
pulses
also
exclusive
clock
circuit
within
gate
EUNCTION
OUTPUT
FRONT
Not
A-to-D
SERIAL
AUDIO
Not
PNEUMATIC
DEFLATE
EXT.
EXT.
EXT.
Not
SET
ENABLE/DISABLE
CLEAR
READ
RE-ARM
Not
READ
COMPARE
RAM
Spare
Not
LATCH
PANEL
Used
CONVERTER
INTERFACE
ANNUNCIATOR
Used
PUMP
VALVE
COMMUNICATION
COMMUNICATION
EQUIPMENT
Used
FAIL-SAFE
1200
Hz
1200
Hz
FAIL-SAFE
Used
AUX.
INPUT
FAIL-SAFE
(U5)
SELECT
Socket
Decoded
which
accepts
it
down
to
at
U2-7
and
ORred
signal
(ZUCLK)
(US)
to
control
the
gate
array
interrupt
(U8)
SELECT
DISPLAY
(U7)SELECT
(U6)
CONTROL
CONTROL
CONTROL
TIMER
1200
FLAG/DEACT.
FLAG
LOGIC
(ROM
program)
the
921.6
U2-5,
within
which
the
Baud
array
by
control
SELECT
SELECT
CONTROL
CONTROL
Hz
INT.
INT.
TIMER
master
kHz
to
produce
clock
respectively.
the
gate
array
is
output
rate.
Also,
768
to
produce a 1200
logic.
PIN
#
SIGNAL
U2-10
U2-39
- -
U2-36
U2-17
U2-33
- -
02-31
U2-28
U2-27
U2-30
U2-25
-
U2-34
Internal
Internal
U2-23
LTCHSEL-0
DSPLSEL-0
A/DSEL-0
ACIASEL-0
BEEPER-1
PUMPON-1
DEFLATE-0
RXRRESET-0
TXENAB-1
AUXOUT-0
ZDMANB-O
D7
Internal
- -
U2-40
U2-35
U2-8
U2-9
-
pulse
the
These
to
at
U2-29
the Q clock
AUXIN-0
υ11-9
ZMCS1B-0
ZMCS2B-0
at
U2-2
quadrature
quadrature
produce
and
the
sent
(921.6
Hz
signal
-
-
-
-
-
E
to
The
interrupt
to
read
disable
used
to
control
or
clear
the state
the
1200
set a flag
executing a read
causes
(ZD7D)
1200
3A00H
interrupt
address
3900H
to
the
the
at
U2-23
Hz
flag
(this
(ZTIRQB)
3900H
)all
CPU
gate
can
will
other
at
U2-4
logic
is
of
Hz
interrupt
in
the
gate
instruction
array
to
gate
which
is
connected
be
cleared
also
clear
the
may
be
or
disabled
data
bits
are
whenever
under
software
an
internal
(ZTIRQB).
array
which
of
location
the
state
by
the
CPU
interrupt
enabled
by
by
writing a ZERO
ignored).
it
is
enabled
control
1200
Hz
timer
The
internal
may
be
read
SBOOH. A read
of
the
1200
to
bit 7 (D7)
by
writing
if it
was
enabled).
writing a ONE
in
data
The
interrupt
and
the
and
flag
1200
by
to
Hz
flag
of
the
data
anything
in
data
bit 7 to
(ZTIRQB)
1200
allows
and
enable
Hz
the
CPU
this
to
the
bus.
to
The
bit 7 to
address
Hz
flag
the
CPU
or
signal
is
by
location
output
The
address
1200
Hz
is
output
is
set.
83
DINAMAP™
VITAL
4.4.1
Microprocessor
Continued
SIGNS
System
MONITOR
MODEL
The
array
8100T
fail-safe
that
responds
commands.
microprocessor
safe
timer
reset
1.
Write
2.
Write
The
first
instruction
timer
reset
clock cycle
gate
array
conditions:
1.
Any
and
SERVICE
timer
reset
In
this
way,
software
pulse.
80H
or
7FH
or
pulse
(ZDMANB)
and
then
software
write
of
38FFH,
MANUAL
pulse
only
to
the
the
logic
execution
The
proper
higher
lower
causes
to
to
the
at
returns
high.
monitoring
7FH
or
below
inclusive.
(U2-34)
proper
is
driven
sequence
provides a system
in
the
process
software
address
address
gate
U2-34.
logic
3C00H.
array
The
to
to
any
3800H.
logic
The
second
detect
address
by
control
of
of
sequence
to
generate a fail-safe
signal
goes
instruction
the
following
logic
certain
software
check
of
generating
is:
low
re-arms
error
between
in
the
the
for
one
3800H
the
E
the
gate
fail-
2.
Any
3.
Two
between
intervening
3800H
4.
Any
and
5.
Any
6.
Two
between
intervening
3800H
If
any
of
these
disables
thus,
fail-safe
Discrete
reading
by
the
are
the
allow
alarm.
digital
the
writing
data
bus.
shown
read
of
address
consecutive
3800H
write
and
38FFH,
write
of
80H
3CFFH,
read
of
address
consecutive
3C00H
write
and
38FFH,
error
conditions
fail-safe
the
fail-safe
inputs
appropriate
to
the
appropriate
The
appropriate
in
the
address
3800H
writes
of
and
38FFH,
of
7FH
or
inclusive.
or
above
inclusive.
3C00H
writes
of
and
3CFFH,
of
80H
or
inclusive.
occur,
timer
reset
timer
to
time
are
read
from
address.
address
addresses,
map
above.
to
38FFH,
80H
or
inclusive,
below
to
any
to
3CFFH,
7FH
or
inclusive,
above
the
strobe
out
bit 7 (D7)
Discrete
with
inclusive.
above
to
without
to
any
address
address
inclusive.
below
to
without
to
any
address
gate
array
from
being
in 4 seconds
on
the
digital
the
desired
signal
name,
any
address
an
between
any
address
an
logic
sets a latch
output
and
data
outputs
data
and
between
3C00H
between
to
U2-34
produce
bus
when
are
generated
on
bit 7 (D7)
logic
that
and,
the
of
state
84
CRITIKON,
INC.
4.4.1
Microprocessor
Continued
System
4.4.1.4
stored
EPROM
in
addresses
enabling
CIRCUIT.
U4, a CMOS
C000H
the
through
EPROM
32K
at
U4-20
SECTION
The
operating
x 8
EPROM.
FFFFH
with
through
4,
PRINCIPLES
program
The
memory
bit
15
of
inverter
for
responds
the
address
U9-10.
OF
OPERATION
the
monitor
bus
is
to
(A15)
4.4.1.5
location
for
diagnostic
RAM
U5.
storing
CIRCUIT.
This
prior
programs
communications
the
high-order
array,
U2,
allowing
4000H
4.4.1.6
digital
to-D
+5
(Vref)
the
‘2000H
clock
internally
control
Dedicated
jumpers
normal
controls
jumper
alternately
20
to
7FFFH.
A/D
converter
which
Vdc
logic
at
U7-40.
chip
select
through
at
U7-18,
by
double-byte
JMP21
operation
the
is
installed
is
installed,
CONVERTER
also
supply
the
digital
CUFF
displayed
during a stepped
displayed
pressure
the
as
displays
pressure
mmHg
displays
One
provides
temporary
determination
which
may
port
and
executed
address
provides
A/DSEL-0
27FFH)
and
decode,
the
RAM
(U7,
shown
some
at
U7-39
I/O
transfers
(asserted
at
address
converter
to
U7-20,
to
transfers.
inputs
DIS
through
of
the
JMP19,
monitor
pressure
in
JMP
20,
with
the
only
CUFF
pressure
deflation.
or
kPa.
show
pressure
show
CMOS
storage
data.
It
be
down-loaded
by
ZMCS1B,
respond
WITH
on
sheet
digital
and
provided
and
a-to-d
by
the
bit
A1
at
select
control
through
DI5
respectively.
and
should
display
the
in
CUFF
previous
is
JMP
19
controls
When
no
in
mmHg.
pressure
8K
x 8
static
for a CPU
is
also
used
the
CPU.
which
to
addresses
DIGITAL
3)
is a CMOS,
YO.
The
circuit
with
conversions
the
gate
read/write
U7-19.
Address
and
are
used
JMP
not
the
MAP
pressure
MAP
determination.
displayed
whether
jumper
is
When
in
kPa.
RAM
scratchpad
for
storage
through
The
RAM
is
produced
in
the
I/O.
The
16
channel,
is
powered
the
voltage
are
array
for
line
at
U7-17,
bit
data
registers
to
read
21
has
be
inserted.
window.
at
each
in
the
MAP
pressure
installed
JMP
is
provided
of
the
is
selected
by
the
range
of
analog-to-
8-bit
by
reference
controlled
addresses
the
CPU
A1
is
used
and
to
the state
no
use
JMP
20
When
no
deflation
When
window
is
in
JMP
19,
19
is
installed,
in
and
by
gate
A-
the
by
of
in
the
step
JMP
the
E
is
DIO0
through
program
time
scan
CR13,
in
the
and
sequentially
the
switch
CR14
simultaneous
DIO2
are
monitor
strobes
panel
matrix
and
CR15
keyswitch
programmable
programs
these
these
as
KEYROWO,
are
used
to
closures
burning
digital
to
be
outputs
KEYROW1
preclude
out a digital
1/0
lines.
The
operating
digital
outputs
as a background
and
the
possibility
output
at
power
task
to
KEYROW2.
of
stage.
on
85
ΏΙΝΑΜΑΡΙΝ
ΥΠ;
4.4.1
Microprocessor
Continued
l
System
MONITOR
MODEL
Shared
(U7-27
KEYCOLO
keyswitch
(U7-23)
circuit
sense
trom
The
allow
Vdc.
8100T
digital
thru
through
closures
samples
VICE
ports
U7-22)
the
MANUAL
(PO - P5)
as
digital
KEYCOL3,
when
square
voltage-to-frequency
the
occurrence
the
pneumatics
nine
analog
for
digitizing
The channel
of
module
input
channels,
(0 - 255)
assignments
interpret
inputs.
respectively , and
KEYROWO
wave
output
converter
an
overpressure
via
J3-12.
ANO
analog
voltages
are
-
the
PO
through
thru
applied
through
as
follows:
voltage
present
P3
are
are
KEYROW2
of
the
temperature
to
JMP
condition,
ANO
(there
in
the
range
assigned
used
are
output.
22.
OP-1,
of
on
these
to
sense
detection
P5
(U7-22)
which
is
no
AN‘),
+0
Vdc
to
P4
is
to
pins
sent
+5
CHAN
ANO
AN2 FPT
AN3
AN4 +8V
ANS
ANS
AN7
AN8
AN9
SIG
PT
+5V
v
Vbs
Vbc
PTEX
V
VLVSENSE
SOURCE
This
is
the
cuff
of
+0
This
is
signal
Vde.
This
is
to
the
(pulsatile
the
+4.5
Vde.
filtered
+5
pressure
Vdc
J5-5,6.
This
is
the
+8
Vdc
9,10.
This
is
the
-6.2
Vde nominal
Vref
across
is
the
at
J5-13,
is
the
divider
is
the
to
is
the
current
brought
R64
voltage.
battery
battery
R66
pressure
pin 1 of
voltage
drain
testing
representative
This
supply
This
voltage
30
Vde.
This
applied
This
of
the
module
manufacturing
transducer
(AC
coupled) pressure
complexes)
logic
supply
supply
from
and
R65
to
voltage
charging
in
divided
and
R67
transducer
the
pressure
across
of
the
valve
at
J3-40.
.
signal
in
the
range
from
the
power
the
power
analog
supply
give a positive
by 3 from
voltage applied
representative
excitation
transducer
R86
which
is
representative
coils
in
is
the
used
This
in
the
range
transducer
of
+0
to
+4.5
supply
supply
at
applied
the
power
across
of
13.6
voltage
(TX1).
pneumatics
only
during
at
J5-
to
to
86
CRITIKON,
INC.
4.4.1
Microprocessor
Continued
4.4.2
Analog
Subsystem
System
4.4.1.7
latch
(U8)
CMOS
inputs
gate,
gate
The
edge
control
flip-flops
are
U10.
array
output
of
the
filtered
and
dump
the
pneumatics
The
following
DIGITAL
is
shown
which
steered
in
of
by
U10
is
enabled
response
U10
goes
the Q clock,
offsets
pressure
valve
of
transducer
control
module
circuits
+
Negative
+
Pressure
*
Automatic
*
Oscillation
«
Reference
«
Power
supply
SECTION
OUTPUT
on
sheet 3 of
have a common
the
microprocessor
by
to
an
address
low
during
goes
high
the
pressure
circuit
signals
via
J3-16
comprise
bias
supply
transducer
zero
setting
channel
voltage
voltage
4.
LATCH
the
schematic.
clock
LTCHSEL-0
in
the O clock
to
latch
the
transducer
test
pulse
(ZERO-1
and
J3-15,
the
analog
circuit
and
preamp
circuit
amplifier
supply
circuit
circuit
monitors
PRINCIPLES
CIRCUIT.
input
data
bus and
which
the
range
and
data.
amplifier
(FPTTEST-1),
and
DUMP-0)
respectively.
subsystem:
circuit
The
This
circuit
at
U8-11.
is
generated
of
0000H
then,
The
outputs
OF
OPERATION
digital
output
contains
The
clocked
by
by
to
07FFH.
on
the
of
the
circuits,
which
and
are
the
the
8
D
NAND
the
trailing
latch
zero
sent
to
4.4.2.1
voltage
provide
circuit
comprise
buffer
of
about
translate
between
NEGATIVE
supply
the
negative
is
shown
an
oscillator
the
output
transistors
7.4
Q3
volts
the
pulse
+0.7
is
Vdc
provide a supply
switching
components.
BIAS
generated
rail
on
sheet 1 of
operating
of
this
and
Q4,
p-p.
C24
waveform
and
of
about
SUPPLY
from
the
for
the
analog
the
schematic.
at
oscillator
the
and
and
output
CR9
such
-6.7
Vdc.
-6.0
volts
CIRCUIT.
+8
volt
circuitry.
about
drive
of
which
serve
as a clamping
that
the
CR8
rectifies
across
A
supply
on
This
Three
sections
20
kHz.
Two
the
output
is a rectangular
voltage
C25,
at
this
which
negative
negative
the
CPU
negative
of
sections
amplifier
waveform
level
shifter
CRS
switches
pulse
filters
out the
bias
board
supply
Ui8
of
U18
made
to
to
to
up
of
87
DINAMAP™
4.4.2
Analog
Continued
VITAL
SIGNS
Subsystem
MONITOR
MODEL
8100T
4.4.2.2
transducer
Q2,
and a section
controlled
provides
compensation
40
to
amplifier
of
TX1
set
scale
of a section
100
sections
to
voltages
A/D
by
the
60
mV
using
as
well
by
R33
factor
from
the
of
converter.
SERVICE
PRESSURE
TX1
is
excited
of
U20.
R17,
which
correct
at
(PT
is
of
transducer
U14
between 0 and
source
of
the
pressure
255
mmHg
two
additional
as
the
offset
ZERO)
calibrated
U14
to
be
serve
to
MANUAL
TRANSDUCER
by a constant
The
current
limits
the
impedance
transducer.
pressure,
sections
of
the
and
buffered
by
R20
(SCALE
1.00
mmHg/ADU,
to
the
A/D
constrain
5.0
volts
current
through
current
for
is
amplified
of
preamp
by
the
ADJUST)
converter.
the
output
to
ensure
CIRCUIT.
generator
the
to
13.5
proper
The
output
by
U20."
The
are
coarsely
fourth
Pressure
comprising
transducer
milliamperes.
temperature
of
the
the
differential
zero
pressure
nulled
section
of
trimmer
providing a nominal
CR3,
CR4,
and
of
the
transducer
proper
operation
is
R16
transducer,
offset
by a voltage
U20.
The
and
the
gain
gain
of
two
amplifier
of
the
-
Q1,
4.4.2.3
the
calibration
During
reading,
In
order
mmHg,
signal
ofisets
processor
auto
signal
DASH50
then
4.4.2.4
provides a low
Stages
to
5.0
Means
response
FPTTEST-1
channel
AUTOMATIC
transducer
the
auto
zero,
and
subtracts
to
preserve
the
signal
to
reduce
the
PT
to
measure
zero
time.
is
asserted,
offset
be
subtracted
OSCILLATION
of
high
volt
clamp
are
also
of
the
signal
ahead
channel
coarse
signal
pass
pass
that a controlled
through
A/D
correct
analog
the
FPT
converter
values,
section.
and
ZERO
is
accomplished
offset
trimmer
the
processor
this
reading
the
capability
"DASH50"
it
by
about
by
During
the
A/D
is
added
to
filter, a switchable
filter.
similar
provided
FPT
section
is
coupled
of
the
FPT
amplitude
channel.
features
establishing
from
50
+100
to
exactly
operation,
is
read
to
the
obtain
the
CHANNEL
CR6, CR7,
to
the
to
characterize
during
pickoff
step
The
of
greater
SETTING
is
activates
from
of
reading
the
units.
The
+130
ADU,
the
value
if
the
again,
A/D
reading.
pressure
set
CIRCUIT.
mainly
processor
A/D
in
for
an
the
zero
subsequent
pressures
signal
is
available
of
the
"DASH50"
reading
and
the
The
reading.
AMPLIFIER
gain
amplifier,
and
two
sections
one
in
the
PT
channel,
the
gain
calibration
mode
through a section
point.
The
gain
voltage
resulting
the
of
about 1 mmHg
response
response
compared
confidence
Auto
software.
A/D
reading
valve,
records
pressure
above
adds
an
"PLUS100"
to
is
255,
exact
value
stored
of
in
and
of
and
frequency
or
buffer
from
can
the
operation
zero
CIRCUIT.
two
U15
wait
this
be
against
Zero
During
of
17.
the
readings.
200
offset
to
Which
allow
the
offset
during
the
DASH50
of
the
offset
clampable
provide
times.
U17
into
point
is
is
passed
digitized
known
of
of
the
may
U15
The
the
such
by
the
PT
PT
a0
PT
the
88
CRITIKON,
4.4.2
Analog
Continued
INC.
Subsystem
4.4.2.5
programmable
source
current
reference
used
REFERENCE
to
set
for
the
for
to
set
this
shunt
regulator,
the
scale
pressure
the
preamplifier
voltage
SECTION
VOLTAGE
provides
factor
of
the
transducer,
and
the
to
the
correct
4,
PRINCIPLES
SUPPLY
an
A/D
converter
as
well
as a stable
calibrated
value.
OF
CIRCUIT.
independent
and
the
source
50
mmHg
OPERATION
U19,a
4.50
volt
excitation
for
the
offset.
R48
zero
is
4.4.3
Switchpanel
Interface
4.4.2.6
supply
power
onthe
ranges
the
is
control
The
switches
in a matrix
the
involves
line
POWER
voltages
supplies
A/D
of
values
battery
available.
the
switch
on
CPU
through
strobing
to
determine
KEYROW
developed
These
digital
and
prevent
panel
applied
sequentially
-
digital
output
J2-6,
+5
switches
to
KEYCOL1,
J2-1,
J2-2,
channels
digital
input
the
pneumatic
to
allow
the
pneumatic
PO, P1,
SUPPLY
of
+5
volts,
are
connected,
multiplexer.
to
operate
charger
This
state
panel
the
(as
signals,
by
through
Vdc
one
KEYCOL2
J2-3
channels
board.
controller
information
of
the
interface
front
shown
the
each
which,
KEYROW0,
the
digital
/O
bits
bits
and
diodes
from
be
pressed
of
the
to
determine
and
P2
system
CANCEL
panel,
in
A-to-D
are
are
being
KEYROW
J2-4,
and
at
switch
VOLTAGE
+8
volts,
through
These
"BATTERY"
KEYROW
the
voltage,
is
is
shown
except
Figure
converter,
if
any,
readings
power
used,
4-7)
keyswitch
KEYROW1
VO
bits,
programmed
applied
CR15,
applied
at
the
lines,
which
and
KEYCOL3
respectively
P3.
These
power-up.
reset
circuit,
to
reset
-6
volts,
appropriate
are
supply
is
used
along
led.
on
sheet 3 of
the
ON
which
is
U7.
line
followed
has
DIOO,
DIO1
by
the
to
the
switch
CR14
and
to
the
same
time.
the
KEYCOL
keyswitch
are
and
channels
Note
that
shown
the
overpressure
MONITORS.
plus
the
battery
dividers,
compared
alarms.
to
with
the
and
interrogated
An
by
been
and
and
CPU
panel
CR13.
digital
While a digital
is
pressed.
brought
applied
KEYCOL2
on
sheet 2 of
against
Additionally,
indicate
battery
the
schematic.
OFF
switches,
interrogation
reading
pressed.
KEYROW2
DIO2,
at
power-up
matrix
These
outputs
lines
into
to
are
programmed
The
system
and
line
to.
inputs
the
correct
Vbc,
when
line
voltage,
All
are
wired
at a 40
Hz
sequence
each
The
rate
KEYCOL
are
respectively.
to
be
at
J2-4,
diodes
should
are
KEYCOLO,
the
analog
is
the
latch
two
"one"
is
read
CPU
board
input
to
also
sent
schematic,
on
the
power
to
the
by
J2-5
front
at
be
to
The
front
J2-8
and
through
panel
J2-9,
J5-17
ON
and
OFF
respectively,
and
J5-19
and
as
switches
sent
shown
on
are
brought
directly
to
sheet 1 of
into
the
the
power
the
CPU
board
supply
schematic.
at
89
DINAMAP™
4.4.4
Display
VITAL
Board
SIGNS
MONITOR
Interface
MOREL
The
transfers
2
display
of
the
8100T
from
schematic.
generated
Any
I/O
data
be
asserted
address
the
DO
board
bits
display
through
via
E1-18
synchronized
the
gate
array
SERVICE
board
the
by
the
transfer
and
sent
AO
through
board
D7,
are
through
with
at
U2-5
is
an
CPU.
The
high
in
to
via
E1-11
driven
the
MANUAL
output
Most
display
order
address
the
range
the
display
A3
are
through
directly by
E1-25,
CPU
by
and
sent
device
of
the
interface
board
which
is
selected
decode
of
0800H
board
via
driven
directly
E1-14,
the
CPU
respectively.
the Q clock,
to
the
display
is
controlled
circuits
circuit
to
08FFH
E1-9.
by
are
by
DSPSEL-0
in
will
The
the
CPU
the
low
respectively.
and
seni
to
Data
transfers
QCLK,
board
which
via
E1-8.
by
data
shown
on
sheet
which
gate
array,
cause U2-39
order
and
sent
to
The
data
bits,
the
display
are
is
generated
is
U2.
to
by
4.4.5
Pneumatics
Interface
Module
Supply
the
The
as
supply
and
R68
voltage
The
These
The
voltage
display
MAINSLED
shown
at
J5-14
turned
and
sent
for
pneumatic
signals
pneumatic
DEFLATE-0.
discrete
on
sheet
digital
3.
pneumatic
ZERO-1
is
pressure
discrete
on
digital
sheet
pressure
valve
ports
deflate
output
When
the
the
valve
bit
DEFLATE-0
cuff
pressure
deflate
is
brought
board
as
shown
signal
on
sheet 3 of
and
is
on
at
the
power
to
the
display
the
MAINSLED.
module
are
shown
valve
control
The
auto zero
output
When
ZERO-1
line
from
the
not
asserted,
transducer.
output
3.
When
DUMP-9
line
to
atmosphere.
the
output
is
controlled
generated
is
line
valve
is
energized
in
from
on
is
derived
the
schematic.
present
entry
board
interface
on
all
signals
valve
bit
generated
is
pressure
the
auto zero
The
dump
bit
generated
is
of
the
air
by
DEFLATE-0
by
the
gate
true
the
to
atmosphere.
the
power
sheet 1 of
from
the
only
when
module.
via
E1-7
is
effected
three
sheets
are
is
controlled
by
true,
the
transducer
valve
valve
is
by
true,
the
When
DUMP-0
pump
to
array,
deflate
valve
When
to
block
supply
the
schematic.
battery
Vbc
is
brought
the
AC
This
voltage
where
at
J3
of
the
ZERO-1,
by
the
digital
auto
zero
to
applies
controlled
the
digital
dump
valve
is
the
cuff
which
U2-28,
as
is
de-energized
DEFLATE-0
the
cuff
pressure
and
routed
charger
line
it
of
DUMP-0
ZERO-1
latch,
valve
voltage,
in
from
power
is
reduced
is
used
as
the
CPU
schematic.
and
which
U8-16,
applies
atmosphere.
cuff
pressure
by
DUMP-0
latch,
U8-19,
ports
the
not
asserted,
pressure
line.
is a discrete
shown
on
is
deflate
directly
Vbc,
the
power
is
connected
by
drive
board.
is
a
as
shown
the
When
to
which
as
shown
cuff
the
dump
The
digital
sheet
2.
and
applies
not
asserted,
line.
to
the
is
a
90
CRITIKON,
INC,
4.4.5
Pneumatics
Interface
Continued
Module
The
air
pump
control
generated
PUMPON-1
the
air
The
Q7,
overpressure
by
is
pump.
pneumatic
CR1
and
the
CR2
signal
positive-going
the
front
panel
turned
approximately
biases
off
Q6.
on, the
CR1
to
When
PNEURESET-1
charge
and
through
PNEURESET-1
overpressure
to
gate
Q7
which
duration
of
the
signal
gate
array,
asserted,
system
as
reset
shown
latch
edge
whenever
CANCEL
power
supply
50
milliseconds.
hold
PNEURESET-1
RESET-0
is
asserted
R84
and
is
latch
by
pressing
turns
switch
panel
SECTION
(PUMPON-1)
U2-31,
it
enables
as
regulated
signal,
on
sheet
in
the
pneumatics
the
monitor
switch
is
pressed.
asserts
When
low
goes
high,
CR1
by
+5
through
R85.
When
un-asserted.
the
CANCEL
off
Q6,
thus
asserting
interrogation
4.
PRINCIPLES
is a discrete
shown
on
DC
power
PNEURESET-1,
2.
This
signal
board
is
first
When
RESET-0
RESET-0
and
C13
To
forward
and
R83,
is
charged,
allow
and
is
CR2
and
for
switch,
PNEURESET-1
pulse.
OF
digital
sheet
2.
When
to
be
is
generated
is
used
and
is
required
turned
on
the
monitor
holds
it
asserted,
biases
are
reverse
C13
begins
Q6
is
reseiting
KEYCOL2
OPERATION
output
bit
applied
by
to
reset
to
or
whenever
is
first
low
for
it
forward
CR2
to
turn
biased,
to
turned
on
the
is
used
for
the
to
Q6,
the
be
a
4.4.6
Fail-safe
Timer
Circuit
The
fail-safe.timer
circuit
consists
binary
counter.
times
out
in 4 seconds
gate
array,
and
comparison
stage
down
ripple
to a 2
to
counter
Hz
U11.
U11
is
reset
at
power
supply
microprocessor
array
(U2-34)
capacitively
counter
some
way,
hold
the
generates
the
pneumatics
audio
alarm
is
also
external
before
coupled
reset.
U11-6
clock
the
and
used
to
communication
circuit
is
shown
of a crystal-controlled
It
performs
it
provides a crystal-controlled
the
microprocessor
signal
power
and
resets
must
If
the
will
divider
fail-safe
module
inhibit
disable
two
if
not
which
divides
(U12-3)
on
time
U11
periodically
the
binary
to
U10
microprocessor
go
high
in a clear
alarm,
through
the
valve
the
TXEN-O
port
on
sheet 2 of
oscillator, a clock
functions:
reset
by
the
clock
as a system
the
oscillator
which
is
used
by
RESET-0
through
U10.
generate
counter
by
C9
tallies 4 seconds.
to
prevent a stuck
should
after 4 seconds
state
at
U12-12.
FSALARM-0
J3-17
where
drive
circuits.
signal
on
the
pneumatics
it
microprocessor
at
the
schematic.
acts
as a fail-safe
time
base
check.
frequency.
to
clock
the
which
is
generated
Thereafter,
ZDMANB-0
fail
to
generate
since
the
When
through
U10-6
it
is
used
The
fail-safe
which
U9-8,
module.
divider
through
for
periodic
of
binary
the
through
ZDMANB-0
bit
from
the
last
reset
U11-6
which
to
generate
alarm
is
sent
This
and
a
timer
which
the
U12is
a7-
32.768 kHz
counter,
by
the
the
gate
holding
reset
the
in
and
goes
high
is
sent
the
at
U9-8
to
the
is
it
to
91
DINAMAP™
4.4.6
Fail-safe
Continued
4.4.7
External
and
Control
VITAL
SIGNS
Timer
MONITOR
Circuit
Communications
MODEL
The
aminute)
array
one
8100T
third
stage
(U2-35)
of
the
read
oscillators
microprocessor
The
external
of
the
schematic.
supported
by
communications
Adaptor
MARK,
600
resistor,
a
inputs.
Refer
(U6)
+5V = SPACE)
baud.
R72, and
5.1V
Zener
The
to
Section 3 of
The
transmit
SERVICE
of
by
to
check
generates
MANUAL
the
binary
counter
the
microprocessor
the
oscillator
is
off
frequency
the
communications
AUXIN-0,
the
software
between
and
an
AUXOUT-0,
at
the
external
serial
received
which
signal,
applied
allows
line,
this
manual
to
RS232
TxD-0,
(U11-9)
as a digital
circuits.
by
more
901
alarm
and
and
control
circuits
RXR-1
this
time.
The
Asynchronous
device
capable
communication
the
RxD-0,
input
for
logic
is
output
the
is
terminated
of a CMOS
levels
by
serial
is
periodically
input
through
If
the
comparison
than
+0.5%,
stops
monitor
are
shown
and
TXE-1
software
does
Communications
of
receiving
signals
logic
in
ASCII
by a 10k
inverter,
to
be
applied
the
CMOS
inverter,
communication
(at
least
twice
the
gate
shows
the
operation.
on
sheet
are
not
support
serial
Interface
level
(OV
format
U13.
as
at
ohm
CR11
signal
U13-4.
protocol.
that
3
=
is
4.5
PNEUMATIC
CONTROL
4.5.1
Valve
Drive
CIRCUITS
Circuit
The
pneumatic
Functionally,
drive
circuits
The
valve
digital
The
AUTO
ZERO-1.
input
port
these
and
solenoids
control
ZERO
When
and
de-energized,
to
the
CUFF
The
DUMP
10
goes
alarm
energized,
the
CUFF
valve
valve,
high
(FSALARM-0)
the
pressure
ports
the
control
circuits
the
of
the
VMOS
valve,
energized,
connects
the
AUTO
input
port.
MTS,
when
DUMP-0
DUMP
port
output
circuits
are
consist
overpressure
are
powered
FET
switches,
MT1,
is
energized
the
AUTO ZERO
the
pressure
is
or
the
valve
to
of
ZERO
the
valve
energized
is
asserted
overpressure
blocks
atmosphere.
air
pump
shown
of
the
and
safety
by
the
transducer
connects
when
the
output
to
on
schematic
valve
drive
interlocks.
+8V
supply
O1,
O3
when
valve
O4
is
or
(U3-3)
signal
of
When
the
CUFF
SC315-292.
circuits,
and
and
Q3
is
blocks
to
atmosphere.
the
pressure
turned
when
(OP-1)
the
air
the
energized
O4.
turned
the
on
by
the
fail-safe
is
asserted.
pump
de-energized,
pressure
port.
pump
by
on
by
CUFF
When
transducer
U2-10,
U2-
When
and
ports
the
DUMP
92
CRITIKON,
4.5.1
Valve
Continued
INC.
Drive
Circuit
The
DEFLATE
This
occurs
or
OP-1
is
asserted.
line
from
the
is
de-energized,
restrictor
provides
in
for a faster
when
CUFF
the
valve,
either
When
pressure
the
deflate
DEFLATE
collapse
MT2,
the
SECTION
is
energized
DEFLATE-0
the
DEFLATE
port
is
line
is
valve
common
of
the
4,
PRINCIPLES
when
is
blocked.
ported
to
port
solenoid
Q1
is
turned
unasserted,
valve
is
energized,
When
the
atmosphere
tubing.
fields
of
OF
or
DEFLATE
through
Zener
MT2
OPERATION
on
by
U2-4.
FSALARM-0
the
deflate
valve
a
diode,
and
MT3.
D1,
4.5.2
Pump
4.5.3
Overpressure
and
Drive
Safety
Circuit
Switch
Interlocks
Resistors
VLVSENSE,
used
The
the
modulator
circuitry
the
driven
DEFLATE
provide a regulated
The
pressure
transients
set
closed
the
the
R6
de-energize
pump
energize
signal
When
PNEURESET-1
from
the
KEYCOL2
R25,
R26
indicative
in
manufacturing
unregulated
pump
through
whose
causes
modulator
by
overpressure
to
trigger
contacts
NOR
switch,
to
assert
(U2-12).
as a digital
the
holding
CPU
are
U2-11.
valve
port
with a restrictor
from
in
latch
in
the
OP-1.
the
the
DUMP
overpressure
the
board
(CANCEL
pump
Q2
open-collector
the
turned
When
is
switch
falsely
the
of
the
contacts
DEFLATE
OP-1
input
at
latch
by
and
R27
of
the
tests.
voltage,
and
is
modulator
on
PUMPON-1
energized
12
Vdc
to
is
fed
triggering
range
of
the
overpressure
reset
state.
open
OP-1
enables
valve
also
turns
valve
in
bit
to
switch
U3-8.
Capacitor,
in
the
the
trailing
switch
provide
current
regulated
and
(closed),
inline.
265
and
the
generate
reset
depression).
an
drain
Vp,
from
by
outputs
to
operate
off
by
the
is
asserted,
the
the
pump
by a pneumatic
The
the
overpressure
mmHg
on
event
closes,
edge
switch
When
the
NOR
U3-3
to
dump
Q7
the
C1,
state.
of
to
to
which
O4
the
RESET-0
average
the
U1.
drive
at
motor
restrictor
355
an
800
prevents a stuck
PNEURESET-1
voltage
of
all
three
solenoids
power
about 5 kHz.
shutdown,
modulator
pull
overpressure
latch
energize
cuff
fails.
NOR
supply
U1
is a pulse width
the
base
SD,
and
providing
is
through
line
from
prevents
switch.
mmHg.
U3-12
pressure
provides a back-up
The
visual
is
set
the
CPU
and
latch
or
by
The
to
by
DUMP
may
the
reading,
which
is
applied
of
Q2.
The R-C
The
outputs
input
which
the
turned
Q2.
on
the
CUFF
pressure
The
switch
normally-
ground
condition
+5 V through
and
reads
audible
PNEURESET-1
is
leading
to
valve
turn
off
to
the
alarm.
be
reset
generated
to
to
is
hold
trips
and
the
OP-1
by
edge
is
of
is
on
of
The
fail-safe
when
the
cause
the
and
the
cause
the
constant
alarm
fail-safe
DUMP
pump
drive
audio
audio
alarm.
interlocks
alarm
occurs
valve
to
energize,
circuit
to
annunciator
are
effected
(FSALARM-0).
the
be
disabled.
circuit
to
generate
by
U3-3
which
Thus, a fail-safe
DEFLATE
The
valve
output
the
disables
to
de-energize
at
U3-4
highest
U2
alarm
will
also
volume,
will
93
INAMAPTM
|
MONITOR.
M
100T_
SERVICE
MANUA!
4.6
AUDIO
ANNUNCIATOR
SYSTEM
4.7
DISPLAY
BOARD
The
audio
consists
voltage
normal
generated
which
Q5
BEEPER-1.
across
of
an
of
J1-7
The
contained
board
of
converter
operation,
drives
applies
AL1
the
emitter
integral
3000
Hz.
on
the
display
are:
»
*
annunciator
switching
by
the
the
base
The
in
-collector
oscillator
The
external
board
in
Section
the
the
the
the
transistor
(U4),
the
audio
CPU.
base
of
drive
voltage
the
range
and
alarm
communication
circuits
6.
Seven-segment
Discrete
Display
Scan
Failure
and
the
Temperature
system
and
to
junction
may
LED's,
Data
(shown
(Q5),
the
alarm
BEEPER-1
Q5.
The
Q6
which
converter,
of
OV
to
annunciator
be
are
shown
The
functional
displays,
Transfer
Protection
Conversion
on
schematic
volume
Piezo
is
controlled
is a pulse-modulated
R-C
is
proportional
U4,
about 15V
of
Q6.
which
disabled
connector
on
Timing
control
annunciator
by
network
The
circuits
and
in
applies a voltage
proportional
Piezo
operates
by
connecting
to
schematic,
that
Circuits,
Ghosting
Circuit.
SC 315-292)
transistor
module
BEEPER-1
digital
the
collector
to
the
duty
differential
to
alarm
module,
at a fixed
J1-15
assert
ALMDIS-0.
SC
315-288,
comprise
Prevention
(Q6),
(AL1).
which
signal
circuit
cycle
the
resistance
ALI,
frequency
to
J1-1
the
display
Circuits,
During
is
of
of
is
or
4.7.1
Seven-Segment
4.7.2
Discrete
LED
(point)
Displays
Displays
The
seven-segment
These
SYSTOLIC,
cathode
segments,
powered
drive
are
common
pulled
are
array
for
these
switched
to
NPN
Darlington
The
discrete
Those
when
driven
sheet
shown
collector
leading
on
shown
the
by
1)
on
edge
sheet
grouped
PULSE
plus
by
the
cathode
ground
address
the
selected
sheet 1 have
outputs
2.
and
of
seven
decimal
+5
supply,
transistors
by
the
connections
by
drivers,
(point)
on
sheet 2 have
latch
+5 V supply
by
of
of
the
displays
identified
and
DIASTOLIC.
segments
point,
as
is
output
the
the
of
outputs
U5-U6.
LED's
are
bit
DG14
through
the
state
their
data
address
are
shown
as
and a decimal
are
driven
shown
provided
the
data
for
each
of
the
shown
their
is
asserted.
the
of
the
cathodes
latch,
U14.
decode,
on
sheet 2 of
CYCLE,
Each
on
by
latch,
address
on
cathodes
data
DG15,
TEMPERATURE,
digit
by
the
sheet 1 of
the
LM324
U1,
digit
display
sheets 1 & 2 of
pulled
Each
2907
PNP
latch,
pulled
to
The
data
generated
the
display
point.
The
2907
PNP
the
schematic.
linear
shown
latch,
U1.
on
are
U7-U8,
to
LED
transistor
The
ground
latch
is
schematic.
is a common-
seven
transistors,
Base
op-amps
sheet
individually
the
ground
of
this
(shown
discrete
by
the
selected
by
U8
which
1.
The
through
schematic.
by
U6-11
group
on
LED's
common
by
as
shown
the
is
the
94
CRITKON.
4.7.3
Display
Transfer
INC.
_
Data
Timing
The
display
controlled
address
written
the
DSPLSEL-0
that
address
The
(LDO-LD7)
as
the
(or
The
are
and
(or
associated
address
edge
The
occurs
latch
by
signal
the
trailing
(A0-A3)
data
latch,
shown
associated
point
LED
address
used
to
U8.
The
point
LED
is
of
DSPLSEL-0
decoding
in
data
transfers
by
various
(U4)
as
the
CPU
DSPLSEL-0
causes
edge
at
Ut,
are
applied
on
sheet
driver
drive)
latch,
steer
and
decoded
group)
NPN
Darlington
delayed
lasts
response
SECTION
between
NAND
to
U12-3
of
U4-9.
is a CMOS
2.
to
U4,
by
until
to
gates
shown
any
transistor
by
to
on
address
is
asserted
to
QCLK
to
the
inverting
When
the
the
address-selected
is a CMOS
gate
the
address
pulling
driver
approximately
prevent
the
leading
the
FIRQ
4,
the
CPU
in
U12,
sheets
enable
will
octal
in
the
by
the
the
latch
D-type
inputs
1.
the
output
is
turned
quad
inputs
of
(DGO - DG15)
the
cathode
(U5 - U6).
10
ghosting
edge
(1200
Hz)
PRINCIPLES
and
the
display
the
data
latch
When
output
range
of
0800H
gate
array
on
latch
trigger
data
(DO-D7)
flip-flop
of
any
on
to
D-type
the
octal
microseconds
due
of
interrupt
whose Q outputs
of
linear
op-amp
apply
display.
flip-flop
address
is
used
to
ground
The
decoding
to
propagation
the
next
to
OF
OPERATION
board
(U1),
data
through
the
CPU
circuit
at
at
U1-11
op-amps
goes
+5V
segment
whose
decoders,
to
select
through
of
after
DSPLSEL-0
the
CPU.
are
and
the
(DO-D7)
OFFFH,
board.
U12-5
and
U9-U10,
true
(high),
drive
outputs
the
digit
its
the
latched
the
leading
delays.
which
is
so
the
U7
4.7.4
Scan
and
Failure
Ghosting
Protection
Prevention
Scan
failure
CMOS
retriggerable
failure
microsecond
The
output
response
address
to
generate
times
prevent
The
output
(DSPLSEL-0
decoding
propagation
protection
multivibrator,
one-shot
protection),
at
to
the
the
display
the
out
(2 - 20
the
last
at
of
the
delays.
and
ghosting
U13.
One
at-U13-6
and
the
other
one-shot
U13-6
FIRQ
DSPLSEL-0
U13-9
is
approximately 1 microsecond
at
U13-9
remains
interrupt.
in
response
milliseconds)
selected
goes
address
signal,
LED
low
by
U12-11
high
prevention
half
of
U13
with a period
half
is
configured
(ghosting
as
long
Should
to
the
FIRQ
U13-6
and
disable
from
being
for
10
microseconds
and,
is
provided
is
configured
of 2 -
20
to
prevention).
as
DSPLSEL-0
the
microprocessor
interrupt
will
go
low
the
address
overdriven.
in
length)
thus,
prevent
by a dual
to
be
a
milliseconds
be a 10
is
asserted
fail
or
the
gate
when
the
decode
after
DSPLSEL-0
to
delay
ghosting
(scan
in
to
array
fail
one-shot
circuits
the
due
to
to
95
DINAMAPIM
4.7.5
Temperature
Circuit
VIT,
IGN
Conversion
|
RM
L
8100T
The
temperature
digital
conversion , auto-calibration
temperature
calibrated
is
connected
voltage
proportionally
about
corrected
The
voltage
to-frequency
the
output
interval
network.
stability
of
the
under
probe
negative
into a network comprising a precision
reference.
with
normal
VFC.
software
body
in
software.
from
converter
frequency
which
is
The
specified
in
the
A/D
To
M
conversion
contains a thermistor
temperature
The
temperature
temperature.
the
thermistor
by
proportional
conversion
meet
the
control
circuits
output
(VFC),
counting
to
accuracy
specification, a method
is
employed.
provide
and
patient
which
coefficient
of
the
network
and
linearily
Nonlinearities
input
network
The
8100T
transitions
the
voltage
of
the
Model
than
is
provided
software
for
temperature
isolation.
exhibits a precisely
of
resistance.
is a voltage
inthe
outside
is
digitized
during a controlled
output
8100T
by
of
The
The
resistance
that
temperature
this
range
using a voltage-
system
from
the
automatic
measures
the
thermistor
requires
long-term
detection,
thermistor
and
varies
range
are
gate
greater
stability
calibration
The
input
to
the
multiplexer,
three
voltage
The
software
and
offset
Thus,
the
reference
factor
reference
This
system
temperature
The
temperature
SC315-288
inputs
source
of
the
system
and
offset
voltage
the
the
the
the
the
*
the
»
the
one
are
VFC
is
selected
input
of
which
reference
as
the
thermistor
can
measure
the
measurements
accuracy
divider
also
probe
and
isolated
precision
temperature
temperature
temperature
data
and
thermistor
due
to
temperature
or
the
VFC
provides a self
type
(oral
conversion
comprise
power
reference
voltage-to-frequency
isolators
from
is
voltages
the
known
depends
and
test
or
rectal).
circuits
supply,
probe
calibration
channel
among
the
thermistor
derived
network.
references
to
cause
associated
voltage
thermistor
the
only
on
input
resistors.
coefficients
capability
are
shown
and
selector,
converter,
four
sources
network.
from
the
and
conversions
the
stability
or
circuitry
and a means
on
supply,
interface,
probe
type
and
by an
The
same
excitation
adjust
the
to
and
accuracy
Variations
long
term
can
be
of
sheet 3 of
detector,
analog
other
scale
be
correct.
of
in
scale
drifts
of
the
cancelled.
detecting
schematic
96
CRITIKON,
4.7.5
INC.
Temperature
Circuit
Continued
Conversion
4.7.5.1
converter
monitor
comprise
collector
Isolated
power
+8Vdc
an
astable
supply
current
Power
is
provided
multivibrator
flows
transformer. A square
wave
rectified
and
filtered
+9Vdo.
SECTION
Supply.
by
at
J1-5.
through
wave
appears
by
CR1,
an
inverter
O1
and
operating
the
primary
at
CR2,
4,
PRINCIPLES
Isolation
for
which
O2,
with
at
30
of
T1, a ferrite
the
secondary
and
C7.
OF
the
temperature
is
supplied
associated
kHz
nominal.
pot
of
T1
Nominal
output
OPERATION
from
the
components,
The
core
and
is
full
is
4.7.5.2
adjustable
reference
network,
reference
(U16)
the
4.7.5.3
excitation
The
thermistor
R40
Precision
shunt
voltage
the
reference
is
adjustable
and
timing
automatic
Temperature
voltage
thermistor
resistance
and
R41
locate a linear
temperature
excessive
4.7.5.4
A
voltage
two
voltages
reference
The
software
C
(channel
these
reference
C
reference
temperature
rectal
(pins 2 &
slightly
necessary
when
and
self-heating
Temperature
divider
for
1)
two
points,
voltage. A voltage
voltage
circuit
probe
is
7)
effectively
higher
for
in
NORMAL
Reference
voltage
source
regulator,
(+3.24
network,
to
compensate
capacitor
calibration
is
in
algorithm.
and
the
parallel
decreases,
to
increase.
(C6),
Probe
load
with
The
Voltage
U15,
Vdc,
and
thereby,
Thermistor
resistance
R40.
causing
values
temperature-to-voltage
to
set
the
excitation
effects
at
the
Calibration
comprising
representing
minimum
periodically
and
adjusts
thus
R44 - R47
10° C and
error
at
the
reads
the
the
offset
cancelling
most
voltages
and
the
divider
(channel
and
attached, a jumper
and
allows
the
software
2)
which
for
identification
in
shorting
out
the
software
to
accurately
R63
mode.
Supply. A precision
provides
nominal)
the
for
VFC
reference
initial
for
tolerances
centering
Interface.
are
provided
As
the
temperature
the
voltage
of
these
resistors
function
voltage
around
for
thermistor.
and
Probe
divides
37°
tightly
scale
effects
C.
for
of
the
R42
specified
10° C
factors
drifts
comprising
is
read
for
of
the
probe
the
probe
connector
which
shifts
to
identify
predict a rectal
the
regulated
the
thermistor
network.
the
dynamic
by
at
the
were
normal
maximum
Type
reference
and
R43
accuracy
(channel
for
zero
in
the
R63 - R66
self
test
type.
the
42° C standard
the
probe
temperature
input
The
in
the
VFC
range
The
R40
and
R41.
increases
junction
the
of
selected
body
output
without
Detector.
voltage
trim
the
37°
point.
0)
and
error
at
VFC
and
provide a 42°
of
the
When
the
shorts
type.
E4
This
to
of
to
into
C
37°
E5
is
4.7.5.5
multiplexer,
calibration
software
isolated
Temperature
U17,
sources
via
the
by
optoisolators
switches
or
to
two
bits
Channel
the
input
the
probe
from
the
data
U19 & U20.
Selector, A CMOS
to
the
VFC
among
interface.
latch,
The
U14,
input
which
analog
the
three
is
selected
are
patient-
by
the
97
DINAMAP™
VITAL
4.7.5
Temperature
Circuit
Continued
SIGNS
MONITOR
Conversion
MODEL
4.7.5.6
frequency
wave
The
an
network
8100T
Voltage-to-Frequency
converter,
at a frequency
voltage
internal
at
op-amp.
R48
voltage.source
R49.
The
current
between
would
The
established
the
input
appear
combination
by
SERVICE
MANUAL,
U16,
determined
pin 3 follows
Pin 3 is
and
R49
which
behind
out
the
of
voltage
at
the
junction
results
the
reference
Converter.
is a monolithic
by
C6
the
input
connected
(by
Thevenin's
parallel
pin 3 is,
at
in a VFC
combination
therefore,
pin 4 and
of
R48
and
with a scale
voltage , C6,
VFC
and
the
voltage
to
the
Theorem)
proportional
the
open
R49
R48,
The
whose
current
applied
to
reference
of
resistances
circuit
if
U16
were
factor
and
and
R49.
voltage-to-
output
is a square
drawn
pin 4 by
from
virtue
voltage
is
equivalent
R48
to
the
difference
voltage
that
disconnected.
input
offset
pin
3.
of
through
to
a
and
4.7.5.7
Data
transmitted
U18.
The
control
by
optoisolators
Isolators.
to
the
CPU
bits
U19 & U20.
The
board
(SELO,
square
at
JMP22
SEL1)
wave
(digital
from
the
output
input
data
latch,
of
U16
port)
U14,
is
by
optoisolator
are
isolated
98
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