GE Critikon Dinamap 8100T User manual

CRITIKON,

4.3.3 On/Off

Low

INC.

Control

Battery

and

Shutdown

Quad

CMOS voltage was

available. bistable is

this

one

switched

supplies

When

reference comparator

latch set

turns

monitor of switching

limited

selected

flip-flop

set

and

flip-flop

junction

supply

power

the

bistable

by

UA,

off

the

trom

positive

gate

U5

to a safe

so

that

This

prevents

USA

reset

by

drives

drop

below

is

to

emitter

voltage,

Vs

of

U1A,

turning

flip-flop.

turns

monitor

deep

feedback

Vs.

SECTION

is

powered value

it

draws

no

discharging

and

USB

the

front

panei

the

base

of

the

CMOS

limited

reference

Q8

discharging

Q12

conducts

off,

removing

and

to

reference

to

about

shunt

is

at

on

the

If

the

unlatches

4.

PRINCIPLES

at

all

times

by

Zener

diode

current

stores

the

least

and

regulated

input

the

when

the

battery

the

on/off

ON

and

OFF

emitter-follower,

gate

supply

13.4

Vdc.

regulator,

one

junction

supplies

supplies.

voltage

power

from

the

on/off

battery.

U4

for

threshold

from

Vp,

with

CR7.

This

only

battery

when

the

state

of

switches.

Q12,

voltage.

This

emitter-follower

U4,

and

the

drop

above

power

falls

the

R34

(Vs)

Vs

below

comparator.

flip-flop,

supplies a small

hysteresis

OF

OPERATION

its

supply

zener

voltage

power

is

unit

is

off.

the

monitor

The

output

whose

is

the

preventing

Thus,

this

emitter

the

to

the

fed

back

threshold

This

and

output

of

amount

fast

The

and

of

is

output

Q8.

to

action

the

4.3.4

Logic Master

4.3.5 Battery

System

Reset

Charger.

4.4 CPU

BOARD

OPERATION

Circuit

When

Vs

is

off, (RESET-0) through unasserted C13

through

removal

When from a separate This charge on

Q6

current

the

feedback Operating output Vdc).

The

CPU

in

Section

R42.

of

line

IC

drives

the

when

limit

voltage

« » * *

«

+

asserted.

After a delay

and

R33

Vs

to

power

switching

battery.

the

input

network

so

the

board

6.

The

the

microprocessor

the

analog

the

switchpanel

the

display

the

pneumatics

the

fail-safe

the

external

gate

U5

When

allows

and

re-arm

is

available,

DC

supply,

Resistor

current

of

U3,

from

battery

(float)

to

circuits

subsystem,

board

turns

on

FET

Q10,

holding

Vs

switches

of

about

the

processor

the

open-collector

the

time

delay

the

switching

Vbc,

supplied

transistor

exceeds

reducing

is

not

the

are

interface

module

timer

communications & control

Q11

R30

senses

about

the

battery

discharged.

proper

shown

divided

system,

interface

circuit,

on,

C13

40

to

104

milliseconds,

to

start.

Diode,

output

circuit.

regulator

by

rectifiers

which

supplies

the

charging

350

milliamps.

pulse

width.

when

the

R12

adjusts

value

for

the

on

schematic

into 7 functional

circuits,

interface

and

circuits,

the

reset

begins

CR15,

of

U5-3

U3

receives

CR8

power

current

Q6

FET

Q2

battery

charger

the

(generally

SC315-293

circuits;

circuits.

line

to

charge

RESET-0 discharges

quickly

upon

power

and

CR9.

from

and

drives

disconnects

is

maximum

contained

Vp

to

turns

the

not

13.65

is

81

DINAMAP™

VITAL

4.4.1 Microprocessor

SIGNS

System

MONITOR

MODEL

The

bit

EPROM

digital

8100T

SERVICE

microprocessor

MANUAL

system

consists

microprocessor, a custom-designed

circuit,

1/0,

one

8K x 8

and a digital

output

Static

RAM,

latch.

of a master

gate

array

an

analog-to-digital

clock

circuit, a CMOS

circuit, a 32K

x 8

converter

8-

with

4.4.1.1 shown

MASTER

on

sheet 2 of

R1, R2, C1, C2,

‘oscillator.

fundamental to

the

clocks the

Interface

4.4.1.2 circuit

a

CMOS

a

16-bit 32K storage

program.

The

pulses

gate

AGIA interrupt generated

performed

controlled

ACIA ( U6),

transfers

The

frequency

gate

array,

for

the

1.8432

MHz

Adapter

MICROPROCESSOR

is

shown

6309E,

address

EPROM

(as

long

is.

provided

6309E

and

array,

requires these U2.

interrupt

request

by

and

from

CPU

and

the

CLOCK

the

schematic.

C3 and

clock

on

8-bit

bus

as

Y1,

circuit

of

3.6864

U2,

where

at

0.9216 (UCLK)

(ACIA)

.

sheet 2 of

processor.

which

to

communicate

power

by

two,

externally

are

derived

The

interrupt

which

is

enabled

liné

at

U1-4,

the

gate

array,

the

operating

microprocessor

the

a/d

converter

or

to

the

data

CIRCUIT.

configured

oscillates

it

is

divided

Mhz,

for

The

It

consists

to

form a crystal-controlled

between

MHz.

The

down

the 2 millisecond

the

Asynchronous

CIRCUIT.

the

schematic.

It

has

an

it

uses

to

address

with

various

is

on)

for

data

generated

8K

by

8-bit-

CMOS

generated E (U1-34)

from

the

master

request

FIRQ,

U2,

program.

line

or

disabled

is

which

The

and

is

and

digital

at

driven

triggers

used

bus.

masier

CMOS

master

to

of

CMOS

provide

clock

logic

clock

FIRQ

Communications

The

microprocessor

The

microprocessor,

8-bit

bidirectional

the

stored

I/O

devices.

by

static

RAM's.

and Q (U1-35)

clock

and

U1-3,

IRQ,

under

software

by

the

1200

all

the

read/write

by

the

YO

(U7),

circuit

inverter,

levels

is

sent

the E and

interrupt,

data

program

Temporary

the

operating

generated

is

driven

control.

Hz

interrupt

background

line

at

U1-32

gate

array

for

gating

is

US,

at

a

directly

Q

and

U1,

bus

and

in

the

clock by

the

by

the

The

tasks is

(U2),

the

data

is

82

The

reset

line

connector

J5-18

depressions.

4.4.1.3 sheet 2 of high clock the

High functions, gate following

and,

GATE

the

order

address

functions,

failsafe

order

timer

address

for

array,

and

table

where

applicable,

(U1-37)

is

in

response

ARRAY

schematic.

decoding,

controlling

reset

pulse,

decoding

generating

for

generating

defines

the shows

driven

to

by

POWER

CIRCUIT.

It

is a custom

dividing

the

processor

and

is

provided

certain

select

certain

addresses

the

power

ON

The

gate

-designed

the

interrupt

discrete

for

signals

discrete

decoded,

output

supply

and

POWER

array

master

digital

clock

/O.

addressing

for

digital

specifies

and

signal

module

circuit

that

to

(FIRQ),

certain

devices

I/O

signals.

name:

through

OFF

switch

is

shown

provides

obtain

various

controlling

internal

external

to

The

their

function

on

for

the

CRITIKON,

INC,

SECTION

4.

PRINCIPLES

OF

OPERATION

4.4.1 Microprocessor Continued

System

ADD

0000H

0800H

1000H

2000H

2800H 3000H

3100H

8200H 3300H

3400H 3500H

3600H 3700H 3800H 3900H

3A00H 3B00H

8C00H

3D00H 3E00H SFOOH

4000H

8000H COCOH

A

clock

(ZOSC)

S

to

07FFH

to

OFFFH

to

1FFFH

to

27FFH

to

2FFFH

to

30FFH

to

31FFH

to

32FFH

to

33FFH

to

34FFH

to

35FFH

to

36FFH

to

37FFH

to

38FFH

to

39FFH

to

3AFFH

to

3BFFH

to

SCFFH

to

3DFFH

to

SEFFH

to

3FFFH

to

7FFFH

toBFFFH

to

divider

and and Q clock clocks

the

kHz)

1.8432 ACIA

is

used

by

are

MHz

divided

the

FFFFH

circuit

divides

pulses

also

exclusive

clock

circuit

within

gate

EUNCTION

OUTPUT

FRONT

Not

A-to-D

SERIAL AUDIO

Not

PNEUMATIC DEFLATE

EXT.

EXT. EXT. Not SET ENABLE/DISABLE CLEAR

READ

RE-ARM

Not READ COMPARE

RAM

Spare

Not

LATCH

PANEL

Used

CONVERTER

INTERFACE

ANNUNCIATOR

Used

PUMP

VALVE

COMMUNICATION COMMUNICATION

EQUIPMENT

Used

FAIL-SAFE

1200

Hz

1200

Hz

FAIL-SAFE

Used

AUX.

INPUT

FAIL-SAFE

(U5)

SELECT

Socket

Decoded

which

accepts

it

down

to

at

U2-7

and

ORred

signal

(ZUCLK)

(US)

to

control

the

gate

array

interrupt

(U8)

SELECT

DISPLAY

(U7)SELECT

(U6)

CONTROL

TIMER

1200

FLAG/DEACT.

FLAG

LOGIC

(ROM

program)

the

921.6 U2-5,

within

which

the

Baud

array

by

control

SELECT

CONTROL CONTROL

Hz

INT.

TIMER

master

kHz

to

produce

clock

respectively.

the

gate

array

is

output

rate.

Also,

768

to

produce a 1200

logic.

#

SIGNAL

U2-10

U2-39

- -

U2-36 U2-17

U2-33

- -

02-31 U2-28

U2-27 U2-30 U2-25

- U2-34 Internal

Internal

U2-23

LTCHSEL-0

DSPLSEL-0

A/DSEL-0

ACIASEL-0

BEEPER-1 PUMPON-1

DEFLATE-0

RXRRESET-0 TXENAB-1 AUXOUT-0

ZDMANB-O

D7

Internal

- - U2-40 U2-35

U2-8

U2-9

-

pulse the

These

to

at

U2-29

the Q clock

AUXIN-0 υ11-9

ZMCS1B-0

ZMCS2B-0

at

U2-2

quadrature

produce

and

the

sent

(921.6

Hz

signal

-

E

to

The

interrupt

to

read disable used

to

control

or

clear

the state

the

1200

set a flag

executing a read

causes

(ZD7D) 1200

3A00H

interrupt address 3900H to

the

at

U2-23

Hz

flag

(this

(ZTIRQB)

3900H

)all

CPU

gate

can

will

other

at

U2-4

logic

is

of

Hz

interrupt

in

the

gate

instruction

array

to

gate

which

is

connected

be

cleared

also

clear

the

may

be

or

disabled

data

bits

are

whenever

under

software

an

internal

(ZTIRQB).

array

which

of

location

the

state

by

the

CPU

interrupt

enabled

by

writing a ZERO

ignored).

it

is

enabled

control

1200

Hz

timer

The

internal

may

be

read SBOOH. A read of

the

1200

to

bit 7 (D7)

by

writing

if it

was

enabled).

writing a ONE

in

data

The

interrupt

and

the

and

flag

1200

by

to

Hz

flag

of

the

data

anything

in

data

bit 7 to

(ZTIRQB)

1200

allows

and

enable

Hz

the

CPU

this

to

the

bus.

to

The

bit 7 to

address

Hz

flag

the

CPU

or

signal

is

by

location

output

The

address

1200

Hz

is

output

is

set.

83

DINAMAP™

VITAL

4.4.1

Microprocessor

Continued

SIGNS

System

MONITOR

MODEL

The

array

8100T

fail-safe

that

responds

commands.

microprocessor

safe

timer

reset

1.

Write

2.

Write

The

first

instruction

timer

reset clock cycle gate

array

conditions:

1.

Any

and

SERVICE

timer

reset

In

this

way,

software

pulse.

80H

or

7FH

or

pulse

(ZDMANB)

and

then

software

write

of

38FFH,

MANUAL

pulse

only

to

the

logic

execution

The

proper

higher

lower

causes

to

the

at

returns

high.

monitoring

7FH

or

below

inclusive.

(U2-34)

proper

is

driven

sequence

provides a system

in

the

process

software

address

gate

U2-34.

logic

3C00H.

array

The

to

any

3800H.

logic

The

second

detect

address

by

control

of

sequence

to

generate a fail-safe

signal

goes

instruction

the

following

logic

certain

software

check

of

generating

is:

low

re-arms

error

between

in

the

for

one

3800H

the

E

the

gate

fail-

2.

Any

3.

Two between

intervening

3800H

4.

Any

and

5.

Any

6.

Two between

intervening

3800H

If

any

of

these disables thus, fail-safe

Discrete

reading by the

are

the

allow

alarm.

digital

the

writing

data

bus.

shown

read

of

address

consecutive

3800H

write

and

38FFH,

write

of

80H

3CFFH,

read

of

address

consecutive

3C00H

write

and

38FFH,

error

conditions

fail-safe

the

fail-safe

inputs

appropriate

to

the

appropriate

The

appropriate

in

the

address

3800H

writes

of

and

38FFH,

of

7FH

or

inclusive.

or

above

inclusive.

3C00H

writes

of

and

3CFFH,

of

80H

or

inclusive.

occur,

timer

reset

timer

to

time

are

read

from

address.

address

addresses,

map

above.

to

38FFH,

80H

or

inclusive,

below

to

any

to

3CFFH,

7FH

or

inclusive,

above

the

strobe

out

bit 7 (D7)

Discrete

with

inclusive.

above

to

without

to

any

address

inclusive.

below

to

without

to

any

address

gate

array

from

being

in 4 seconds

on

the

digital

the

desired

signal

name,

any

address

an

between

any

address

an

logic

sets a latch

output

and

data

outputs

data

and

between

3C00H

between

to

U2-34

produce

bus

when

are

generated

on

bit 7 (D7)

logic

that

and,

the

of

state

84

CRITIKON,

INC.

4.4.1 Microprocessor

Continued

System

4.4.1.4 stored

EPROM

in

addresses

enabling

CIRCUIT.

U4, a CMOS

C000H

the

through

EPROM

32K

at

U4-20

SECTION

The

operating

x 8

EPROM.

FFFFH

with

through

4,

PRINCIPLES

program

The

memory

bit

15

of

inverter

for responds

the

address

U9-10.

OF

OPERATION

the

monitor

bus

is

to

(A15)

4.4.1.5 location

for

diagnostic

RAM

U5.

storing

CIRCUIT.

This

prior

programs

communications the

high-order

array,

U2,

allowing

4000H

4.4.1.6 digital to-D

+5

(Vref)

the

‘2000H

clock

internally

control

Dedicated jumpers normal controls jumper

alternately 20

to

7FFFH.

A/D

converter

which

Vdc

logic

at

U7-40.

chip

select

through

at

U7-18,

by

double-byte

JMP21

operation

the

is

installed

is

installed,

CONVERTER

also

supply

the

digital

CUFF

displayed

during a stepped displayed pressure the

as

displays

pressure

mmHg

displays

One

provides

temporary

determination

which

may

port

and

executed

address

provides

A/DSEL-0

27FFH) and

decode,

the

RAM

(U7,

shown

some

at

U7-39

I/O

transfers

(asserted

at

address

converter

to

U7-20,

to

transfers.

inputs

DIS

through

of

the

JMP19,

monitor

pressure

in

JMP

20,

with

the

only

CUFF

pressure

deflation.

or

kPa.

show

pressure

show

CMOS

storage

data.

It

be

down-loaded

by

ZMCS1B,

respond

WITH

on

sheet

digital

and

provided

and

a-to-d

by

the

bit

A1

at

select

control

through

DI5

respectively.

and

should

display

the

in

CUFF

JMP

19

controls

When

no

in

mmHg.

pressure

8K

x 8

static

for a CPU

is

also

used

the

CPU.

which

to

addresses

DIGITAL

3)

is a CMOS,

YO.

The

circuit

with

conversions

the

gate

read/write

U7-19.

Address

and

are

used

JMP

not

the

MAP

pressure

MAP

determination.

displayed

whether

jumper

is

When

in

kPa.

RAM

scratchpad

for

storage

through

The

RAM

is

produced

in

the

I/O.

The

16

channel,

is

powered

the

voltage

are

array

for

line

at

U7-17,

bit

data

registers

to

read

21

has

be

inserted.

window.

at

each

in

the

MAP

pressure

installed

JMP

is

provided

of

the

is

selected

by

the

range

of

analog-to-

8-bit by

reference

controlled

addresses

the

CPU

A1

is

used

and

to

the state

no

use

JMP

20

When

no

deflation

When

window

is

in

JMP

19,

19

is

installed,

in

and

by

gate

A-

the

by

of

in

the

step

JMP

the

E

is

DIO0

through

program

time

scan

CR13,

in

the

and

sequentially

the

switch

CR14

simultaneous

DIO2

are

monitor

strobes

panel

matrix

and

CR15

keyswitch

programmable

programs

these

as

KEYROWO,

are

used

to

closures

burning

digital

to

be

outputs

KEYROW1

preclude

out a digital

1/0

lines.

The

operating

digital

outputs

as a background

and

the

possibility

output

at

power

task

to

KEYROW2.

of

stage.

on

85

ΏΙΝΑΜΑΡΙΝ

ΥΠ;

4.4.1

Microprocessor Continued

l

System

MONITOR

MODEL

Shared

(U7-27 KEYCOLO

keyswitch

(U7-23) circuit sense

trom

The allow Vdc.

8100T

digital

thru

through

closures

samples

VICE

ports

U7-22)

the

MANUAL

(PO - P5)

as

digital

KEYCOL3,

when

square

voltage-to-frequency

the

occurrence

the

pneumatics

nine

analog

for

digitizing

The channel

of

module

input

channels,

(0 - 255)

assignments

interpret

inputs.

respectively , and

KEYROWO

wave

output

converter

an

overpressure

via

J3-12.

ANO

analog

voltages

are

-

the

PO

through

thru

applied

through

as

follows:

voltage

present

P3

are

KEYROW2

of

the

temperature

to

JMP

condition,

ANO

(there

in

the

range

assigned

used

are

output.

22.

OP-1,

of

on

these

to

sense

detection

P5

(U7-22)

which

is

no

AN‘),

+0

Vdc

to

P4

is

to

pins

sent

+5

CHAN

ANO

AN2 FPT

AN3

AN4 +8V

ANS

AN7

AN8

AN9

SIG

PT

+5V

v

Vbs

Vbc

PTEX

V

VLVSENSE

SOURCE

This

is

the

cuff

of

+0

This

is signal Vde.

This

is

to

the

(pulsatile

the

+4.5

Vde.

filtered

+5

pressure

Vdc

J5-5,6.

This

is

the

+8

Vdc

9,10.

This

is

the

-6.2

Vde nominal

Vref

across

is

the

at

J5-13,

is

the

divider

is

the

to

is

the

current

brought

R64

voltage.

battery

R66

pressure

pin 1 of

voltage

drain

testing

representative

This

supply

This voltage 30

Vde.

This applied

This

of

the module manufacturing

transducer

(AC

coupled) pressure

complexes)

logic

supply

from

and

R65

to

voltage

charging

in

divided

and

R67

transducer

the

pressure

across

of

the

valve

at

J3-40.

.

signal

in

the

range

from

the

power

the

power

analog

supply

give a positive

by 3 from

voltage applied

representative

excitation

transducer

R86

which

is

representative

coils

in

is

the

used

This

in

the

range

transducer

of

+0

to

+4.5

supply

at

applied

the

power

across

of

13.6

voltage

(TX1).

pneumatics

only

during

at

J5-

to

86