GE Critikon Dinamap 7310 User manual

SPO2 MODULE

INTRODUCTION

This area contains service information about the
Model 7310 Pulse Oximetry Module. The SpO2
Module monitors functional oxygen saturation of
arterial blood by calculating the ratio of oxygenated
hemoglobin to hemoglobin that is capable of
transporting oxygen. It provides continuous,
noninvasive measurements of SpO2 and can
display a plethysmographic waveform. Heart rate
values are also derived from the pulse oximetry
signal.

PHYSICAL
DESCRIPTION

The SpO2 module, shown in FO-32B, is enclosed in
a single wide module enclosure. The module
consists of two rigid PWAs, a front sensor flex
connector, interconnect cabling, and the mechanical
enclosure components. The digital PWA, with its
PNet interface connector, occupies the left slot in the
module enclosure (when viewed from the sensor
connector end of the module), and the OEM PWA,
with shield/mounting assembly, occupies the right
slot in the module enclosure.

FUNCTIONAL
PRINCIPLES OF
OPERATION

Isolated Circuits

A functional block diagram of the SpO2 Module is
shown in FO-32A. The diagram is divided into
isolated circuitry and non-isolated circuitry. The
isolated circuitry includes the SpO2 sensor, the flex
PWA, and the OEM PWA. The isolated (ISO)
interface and DC-DC converter isolate this circuitry
from the non-isolated core logic.

The core logic provides communication between the
system host and Module through the PNet
synchronous serial interface. It also includes an
asynchronous data channel to the OEM PWA and
controls the isolated DC-to-DC convertor.

Isolated circuits are shown in the top half of FO-32A.
Signals from the SpO2 sensor are conditioned,
digitized, and processed on the OEM PWA. The
SpO2 sensor is connected to the OEM PWA through
a 9-pin D connector on the module front panel and
flex PWA 313-112.

Non-Isolated Circuits

The isolated interface provides an opto-coupled
asynchronous serial communication channel
between the core logic and the OEM PWA.

The isolated power block consists of a monolithic
DC-DC converter that provides +15V, +5V, and -15V
to the OEM PWA.

Non-isolated circuits are shown in the bottom half of

FO-32A. Functional blocks include the PNet

interface, isolated power control, reset/failsafe,
68302 CPU, 128Kx8 data memory, 128Kx8 program
memory, the model and serial number EEPROM,
and logic analyzer/test interface.

Power (+12V and +5V), is received through J1. The
+12V is applied to DC-to-DC converter PM100, which
powers the isolated circuitry. ISO power control

controls PM100 power-on after the CPU is reset and
shuts down PM100 if a failsafe condition occurs.

The Module will not be damaged when plugged into
a live slot. Core logic power inputs to a Module are
limited to a peak inrush current during hot-plugging.
Within 2 seconds the Module responds to
identification and wakes up in a minimized power
state until registered with the system.

The PNet interface allows asynchronous and
synchronous data transfer between the core logic
and the external devices. Synchronous operation is
always used in MPS systems. Asynchronous
operation is for test and development only. The
reset/failsafe logic provides power-on reset,
processor reset and halt, and failsafe if a problem
occurs with the microprocessor. The
microprocessor controls and transfers data within
the core logic. The program memory is a FLASH
device that can be loaded with program information
from the PNET interface or the logic analyzer
interface. Data memory temporarily stores status
and monitoring data for processing.

COMPONENT
PRINCIPLES OF
OPERATION

SpO2 Front End

Schematic diagram of the SpO2 Digital PWA. The

first sheet of the schematic shows an overall block
diagram of the SpO2 digital PWA.

EMI filtering at the front end is provided on the flex
circuit and the OEM PWA. The PWA is also shielded.
Signals are sent and received through front end
connector J102 with the following pin-out:

PIN NAME PIN NAME

1 RCAL 6 GND
2 +LED 7 SGND
3 -LED 8 Not Used
4 Not Used 9 CATHODE
5 ANODE

The transducer plug shield is connected to shield
ground (SGND).

OEM PWA

Isolated Power

The OEM PWA supplies power to light the sensor
LED. A waveform generated by the sensor photo­diode is applied to the PWA where it is conditioned,
digitized, processed and sent to the isolated
interface shown on sheet 7 of the schematic.

The isolated power section provides patient isolation
from earth ground by isolating the power for the
patient connected circuitry. The isolated power
supply is shown on sheet 7 of the schematic.

Isolated Interface

Power (+12V) is applied to DC-to-DC converter
PM100 at +VIN and returned at -VIN. After the CPU is
reset, ISO_PS-0 goes LOW and turns off Q102. This
turns on Q100 and applies power to PM100. For
reduced power operation when the Module is not in
use, the program allows ISO_PS-0 to float, turning
off the isolated power supply.

If a failsafe condition occurs, FS-1 will go HI, turn on
Q103, turn off Q100, and shut down power to PM100.
It will remain in the state until the failsafe is cleared.

PM100 provides isolated, regulated power outputs of
±15VDC (ISO_+15V and ISO_-15V) and +5V
(ISO_+5V) to the OEM PWA. Q101 turns on the +5V
supply after the +15V supply is up.

As shown on sheet 7 of the schematic, opto­couplers U100 and U101 provide a full duplex,
isolated serial channel between the non-isolated
core logic and the isolated circuitry. Q105 and Q106
buffer the signal to the opto-couplers.

Core Logic

The core logic is shown on sheets 2 through 7 of the
schematic. The core logic provides communication
between the system host and Module through the
PNet synchronous serial interface. It also controls
data acquisition and data processing functions for
the SpO2 sensor. The Module is an 8-bit version of
the core logic with one 128Kx8 RAM and 128Kx8
ROM device. The microprocessor runs at 9.416
MHz.

PNet Interface

The PNet interface, shown on sheet 2 of the
schematic, provides the following functions:

• RS485 drivers (U7 and U8) for serial data and
clock,

• Module select and presence detection (U2),

• Module synchronization.

Core signals are received on PNet connector J1
(sheet 2) with the following pin-out:

PIN NAME PIN NAME

1A,1B +5V 6B M_SELECT
2A DATA+ 7A M_PRESENT
2B DATA- 7B TXOC-0
3A,3B +3.3V 8A M_SYNC-0
4A CLK+ 8B -12V
4B CLK- 10A,10B +12V
5A,5B GROUND 1,2 GROUND
6A M_RESET

The SpO2 Module is designed to be hot-plugged, or
inserted and removed from powered systems.
Ground pins 1 and 2 are longer than the other
connector pins, thus they make first and break last to
protect circuitry. This is partially because of
protective impedance located on the system
backplane, in series with the Modules +5V and +12V
power. Also series impedance on PNet control lines
limits inrush and protects logic devices from
excessive currents during a hot-plug power up.

The PNet protocol defines two modes of operation:
synchronous and asynchronous. The normal mode
of operation is synchronous, with half duplex
transmitted and received data on differential signals
DATA+ and DATA-. As shown on sheet 2 of the
schematic, the device transmitting the serial data
also generates differential clock signals CLK+ and
CLK-. Transceiver direction for data and clock are
controlled by the 68302 processor-generated TX_EN­0 (low true transmit enable) signal through U2. In the
synchronous mode, both data and clock transceivers
U7 and U8 are set to receive (i.e., transmit disabled)
when fail-safe signal FS-0 is asserted.

The alternate serial mode, full duplex asynchronous,
is entered by asserting processor generated control
bit ASYCH_EN. This mode transmits data onto the
differential signals CLK+ and CLK-, and receives data
from the differential signals DATA+ and DATA-. The
transmitter in the Module is disabled unless the
Module has been commanded to transmit per the
PNet protocol. The Module transmitter is immediately
disabled after the last character of a transmission
has been sent.

The Module select input (M_SELECT, hi true)
instructs the Module to respond to identification
requests. When both M_SELECT input and
M_RESET input (hi true) are asserted, a Module
performs a hardware reset.

The Module present output, M_PRESENT is
connected to M_SELECT through diode CR1 to allow
a means of determining if the Module is plugged into
an instrument. When M_SELECT is asserted (pulled
hi) M_PRESENT is hi true.

Module transmitter open collector signal TXOC-0 from
Q1 signifies the Module transmitter is enabled. Serial
data is then transmitted in the synchronous mode.

M_SYNC is used for timing of shorter latency periods
than supported by the serial data protocols. A Module
only asserts M_SYNC when enabled by the host.

Reset Logic

The reset logic is shown on sheet 3 of the
schematic. Reset logic U9 generates a power-on­reset when power is applied. RESET-0 AND HALT-0
signals remain low for minimum of 130 msec after
all logic voltages are in specification.

External reset, processor reset, and halt signals are
low for minimum of 24 clocks when external reset
asserted. Power monitoring, processor reset, and
halt signals low if logic voltages drop below
specification. They remain low for minimum of 130
msec after logic voltages return to the specified
range.

The reset circuit (U6-4,5,6; U6-11,12,13) provides
open drain outputs to the processor bi-directional
reset and halt signals.

Fail-Safe Logic

Fail-safe latch (U6-1,2,3; U6-8,9,10) ensures that the
Module enters a safe state if the processor fails to
operate correctly. The latch is set by a low true output
from the processor watchdog timer (WDOG-0). The
data transmitter is disabled, isolated power is shut
down, and the Module remains in a safe state until
the latch is cleared by a power on or external reset.

Microprocessor

The core logic design is based around the 68302
microprocessor (U10) shown on sheet 4 of the
schematic. The 68302 combines a 68000 core with
a three channel communication processor, and
system integration circuits.