GE C2K Hardware Reference Manual
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GE
Intelligent Platforms
Hardware Reference
C2K* 6U CPCI
Single Board Computer
Publication No: 70000524-800 Rev. C
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Document History
Hardware Reference Document Number: 70000524-800 Rev. C
September 30, 2011
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Chapter 1: Introduction
1.1 Overview .......................................................................................................................... 1-1
1.2 Specifications ................................................................................................................... 1-3
1.3 Compliance ...................................................................................................................... 1-4
1.4 C2K GPIO DC Electrical Characteristics ......................................................................... 1-4
1.5 Block Diagram ................................................................................................................. 1-5
1.6 Technical Support ............................................................................................................ 1-7
1.7 Related Documents ......................................................................................................... 1-7
Chapter 2: Installation
2.1 What Is Included .............................................................................................................. 2-1
2.2 Equipment Needed .......................................................................................................... 2-1
2.3 Power Requirements ....................................................................................................... 2-2
2.4 Configurations Jumpers ................................................................................................... 2-2
2.4.1 FLASH_WP# (P6) ................................................................................................ 2-2
2.4.2 EM_BOOTSEL# (P7) ........................................................................................... 2-2
2.4.3 PCI VIO Select (P9, P12) ..................................................................................... 2-2
2.4.4 COP_EN (P10) .................................................................................................... 2-3
2.4.5 C8051 Debug (P11) ............................................................................................. 2-3
2.4.6 Header/Jumper Locations .................................................................................... 2-3
2.5 Installation ........................................................................................................................ 2-3
2.5.1 C2K C-style Installation ........................................................................................ 2-3
2.5.2 C2K N-style Installation ........................................................................................ 2-4
2.6 U-Boot Utility .................................................................................................................... 2-7
2.6.1 Installation ............................................................................................................ 2-7
2.6.2 Initialization .......................................................................................................... 2-7
2.6.3 Commands ........................................................................................................... 2-7
2.6.4 Information Commands ........................................................................................ 2-9
2.6.5 Memory Commands ........................................................................................... 2-10
2.6.6 Flash Memory Commands ................................................................................. 2-11
2.6.7 Execution Control Commands ........................................................................... 2-12
2.6.8 Download Commands ........................................................................................ 2-12
2.6.9 Environment Variables Commands ................................................................... 2-13
2.6.10 Miscellaneous Commands ................................................................................. 2-14
Table of Contents
C2K User’s Guide 3
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Chapter 3: Interfaces
3.1 Front Panel ...................................................................................................................... 3-1
3.2 Connectors ....................................................................................................................... 3-2
3.2.1 Connector Locations ............................................................................................ 3-2
3.2.2 CompactPCI Connector Pin Assignments ........................................................... 3-4
3.2.3 PMC Connector Pin Assignments ...................................................................... 3-10
3.2.4 COP Port (J6) Pin Assignments ......................................................................... 3-14
3.2.5 JTAG Port (J7) Pin Assignments ....................................................................... 3-14
3.2.6 Front-panel USB (USB4) Connector (J8) Pin Assignments ............................... 3-15
3.2.7 Serial I/O COM Port Termination Header (P15) Pin Assignments ..................... 3-15
3.3 Front-panel LEDs ........................................................................................................... 3-16
Chapter 4: Functional Blocks
4.1 Processor ......................................................................................................................... 4-1
4.2 DDR SDRAM ...................................................................................................................4-1
4.3 Flash Memory .................................................................................................................. 4-1
4.3.1 Flash Write Protection .......................................................................................... 4-1
4.3.2 Boot Code Selection ............................................................................................ 4-3
4.4 PCI Busses ...................................................................................................................... 4-3
4.5 Device Bus ....................................................................................................................... 4-4
4.6 SMBus ............................................................................................................................. 4-4
4.7 Gigabit Ethernet ............................................................................................................... 4-4
4.8 Serial I/O .......................................................................................................................... 4-5
4.8.1 Serial RS-232/422 Ports—COM1, COM2 ............................................................ 4-5
4.8.2 Serial RS-232/422 Ports—COM3, COM4 ............................................................ 4-5
4.8.3 Serial RS-422/485 Ports—COM5–COM8 ............................................................ 4-5
4.9 USB Ports ........................................................................................................................ 4-6
4.10 General-Purpose I/O ........................................................................................................4-6
4.11 Serial ATA I/O .................................................................................................................. 4-6
4.12 Counter/Timers ................................................................................................................ 4-7
4.12.1 Watchdog Timer ................................................................................................... 4-7
4.13 FPGA ............................................................................................................................... 4-8
4.13.1 System Management Interrupt ............................................................................. 4-8
4.14 RTC .................................................................................................................................. 4-9
4.15 CompactPCI Backplane Interface .................................................................................... 4-9
4.16 IPMI and Hot Swap ........................................................................................................ 4-11
4.16.1 Hot Swap Controller ........................................................................................... 4-11
4.16.2 CPLD ................................................................................................................. 4-11
4.16.3 PCI 6254 cPCI Bus Bridge ................................................................................. 4-11
4.16.4 C8051 Microcontroller ........................................................................................ 4-11
4.17 PMC Sites ...................................................................................................................... 4-14
4.17.1 PMC0 Site Features ........................................................................................... 4-14
4.17.2 PMC1 Site Features ........................................................................................... 4-15
4.18 Temperature Sensor ...................................................................................................... 4-15
4.19 Interrupt Circuitry ........................................................................................................... 4-15
4.20 EEPROMS ..................................................................................................................... 4-16
4 C2K User’s Guide
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4.21 JTAG Boundary Scan Circuitry ...................................................................................... 4-17
4.21.1 Configuration Headers ....................................................................................... 4-17
Chapter 5: Resources
5.1 Memory and I/O Address Mapping .................................................................................. 5-1
5.1.1 PCI Buses ............................................................................................................ 5-1
5.1.2 SMBus ................................................................................................................. 5-2
5.1.3 Device Bus ........................................................................................................... 5-2
5.1.4 Multi-Purpose Pins (MPP) .................................................................................... 5-3
5.2 FPGA Registers ............................................................................................................... 5-4
5.2.1 Main Registers ..................................................................................................... 5-7
5.2.2 Interrupt Registers ............................................................................................. 5-11
5.2.3 GPIO Registers .................................................................................................. 5-16
5.2.4 Counter/timers ................................................................................................... 5-37
5.2.5 USART Registers ............................................................................................... 5-45
5.2.6 Standard USART Registers ............................................................................... 5-46
5.2.7 USART Divisor Latch Registers ......................................................................... 5-53
5.3 Component Locations .................................................................................................... 5-54
Chapter 6: Transition Module C2K-TM
6.1 Overview .......................................................................................................................... 6-1
6.2 Physical Description ......................................................................................................... 6-2
6.3 Block Diagram .................................................................................................................. 6-3
6.4 Connector Pin Assignments ............................................................................................. 6-4
6.4.1 CompactPCI Connectors ..................................................................................... 6-4
6.4.2 Ethernet Connectors (J6, J7, and J8) .................................................................. 6-7
6.4.3 Serial ATA Connectors (P19, P20) ...................................................................... 6-7
6.4.4 USB Connectors (J9, J10, and J11) .................................................................... 6-8
6.4.5 Serial RS-232 Connectors—COM1, COM2 (P15, P16) ....................................... 6-8
6.4.6 Serial RS-422/485—COM1–COM8 (P1–P8) ....................................................... 6-9
6.4.7 Serial RS-232—COM3, COM4 (P9, P10) ............................................................ 6-9
6.4.8 BATT+ Header (P13) ........................................................................................... 6-9
6.4.9 ICMB Interface Header (P17) ............................................................................ 6-10
6.4.10 GPIO Connector (P14) ....................................................................................... 6-10
6.4.11 Misc. Connector (P18) ....................................................................................... 6-11
6.4.12 PMC I/O Connectors (P11 and P12) .................................................................. 6-12
6.5 Connector Locations ...................................................................................................... 6-13
6.6 TM Schematics .............................................................................................................. 6-14
Index
C2K User’s Guide 5
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List of Figures
Figure 1-1 C2K Block diagram (a) ........................................................................................................ 1-5
Figure 1-2 C2K Block diagram (b) ........................................................................................................ 1-6
Figure 2-1 C2K (C-style) with PMC modules installed ......................................................................... 2-5
Figure 2-2 C2K (N-style) with PMC modules installed ......................................................................... 2-6
Figure 3-1 Front panels: a. C-style; b. N-style...................................................................................... 3-1
Figure 3-2 Connector locations (C-style).............................................................................................. 3-2
Figure 3-3 Connector locations (N-style).............................................................................................. 3-3
Figure 3-4 USB front-panel connector (J8) pinout.............................................................................. 3-15
Figure 3-5 Front-panel LEDs.............................................................................................................. 3-16
Figure 4-1 Watchdog timer circuitry...................................................................................................... 4-8
Figure 4-2 SMI processing ................................................................................................................... 4-9
Figure 4-3 Interrupt circuitry ............................................................................................................... 4-16
Figure 4-4 JTAG circuitry.................................................................................................................... 4-18
Figure 5-1 C2K component locations (primary side) .......................................................................... 5-54
Figure 5-2 C2K component locations (secondary side)...................................................................... 5-55
Figure 6-1 C2K-TM block diagram ....................................................................................................... 6-3
Figure 6-2 Ethernet RJ-45 connector pinout ........................................................................................ 6-7
Figure 6-3 SATA connector pinout ....................................................................................................... 6-7
Figure 6-4 USB connector pinout ......................................................................................................... 6-8
Figure 6-5 Serial RS-232 DB9 connector pinout .................................................................................. 6-8
Figure 6-6 C2K-TM connector locations............................................................................................. 6-13
C2K User’s Guide 6
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List of Tables
Table 1-1 C2K GPIO DC Electrical Characteristics..............................................................................1-4
Table 3-1 cPCI connector J1 pin assignments .....................................................................................3-4
Table 3-2 CompactPCI connector J2 pin assignments ........................................................................3-5
Table 3-3 CompactPCI connector J3 pin assignments ........................................................................3-6
Table 3-4 cPCI connector J4 pin assignments .....................................................................................3-7
Table 3-5 CompactPCI connector J5 pin assignments ........................................................................3-8
Table 3-6 PMC0_J11 and PMC0_J12 pin assignments..................................................................... 3-10
Table 3-7 PMC0_J13 and PMC0_J14 pin assignments..................................................................... 3-11
Table 3-8 PMC1_J21 and PMC1_J22 pin assignments..................................................................... 3-12
Table 3-9 PMC1_J23 and PMC1_J24 pin assignments..................................................................... 3-13
Table 3-10 COP Port (J20) pin assignments........................................................................................3-14
Table 3-11 JTAG Port (J7) pin assignments ........................................................................................3-14
Table 3-12 Front-panel Ethernet connector (J8) pin assignment .........................................................3-15
Table 3-13 Serial I/O COM port termination header (P15) pin assignments ........................................3-15
Table 4-1 Gigabit Ethernet on-board indicator LEDs. ..........................................................................4-4
Table 4-2 USB on-board indicator LEDs ..............................................................................................4-6
Table 4-3 SATA on-board activity indicator LEDs ................................................................................4-7
Table 4-4 C8051 external I/O ports pin assignments ......................................................................... 4-12
Table 4-5 I/O controller pin assignments............................................................................................4-13
Table 5-1 PCI local bus configuration ..................................................................................................5-1
Table 5-2 SMBus addressing ...............................................................................................................5-2
Table 5-3 Device bus devices, access, size and default address range ..............................................5-2
Table 5-4 MV64460 System Controller MPP pin assignments ............................................................5-3
Table 5-5 FPGA memory map - 16-bit Chip Select..............................................................................5-4
Table 5-6 FPGA memory map - 8-bit Chip Select................................................................................5-7
Table 5-7 Main registers.......................................................................................................................5-7
Table 5-8 Interrupt summary registers ...............................................................................................5-11
Table 5-9 GPIO registers ...................................................................................................................5-16
Table 5-10 Counter/timer registers.......................................................................................................5-37
C2K User’s Guide 7
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Table 5-11 USART Resister .................................................................................................................5-45
Table 5-12 Standard 16550-compatible USART registers ...................................................................5-46
Table 5-13 Baud-rate divisor settings ...................................................................................................5-53
Table 6-1 CompactPCI connector J3 pin assignments ........................................................................6-4
Table 6-2 cPCI connector J4 pin assignments .....................................................................................6-5
Table 6-3 CompactPCI connector J5 pin assignments ........................................................................6-6
Table 6-4 Ethernet RJ-45 rear-panel connectors (J6, J7, J8) pin assignments ...................................6-7
Table 6-5 Serial ATA connectors (P19, P20) pin assignments ............................................................6-7
Table 6-6 USB connectors (J9, J10, and J11) pin assignments...........................................................6-8
Table 6-7 COM1 (P15) and COM2 (P16) pin assignments ..................................................................6-8
Table 6-8 COM1 (P1) through COM8 (P8) pin assignments ................................................................6-9
Table 6-9 COM3 (P9) and COM4 (P10) pin assignments ....................................................................6-9
Table 6-10 BATT+ header (P13) pin assignment ...................................................................................6-9
Table 6-11 ICMB interface header (P17) pin assignment ....................................................................6-10
Table 6-12 GPIO on-board header (P2) pin assignments ....................................................................6-10
Table 6-13 JTAG header (P18) pin assignments .................................................................................6-11
Table 6-14 PMC0_P11 and PMC1_P12 pin assignments....................................................................6-12
C2K User’s Guide 8
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Chapter 1: Introduction
1.1 Overview
The C2K* is a 6U PICMG 2.16 compatible Single Board Computer intended for both system controller and peripheral slot applications. The board provides a CPU core, PICMG 2.16 compatible
backplane interface, and several peripheral devices/interfaces. The CPU core circuitry consists of
a Freescale MPC7448 or MPC7447A CPU operating at up to 1.4GHz, the Marvell® MV64460
PCI controller, up to 1GB of 167MHz DDR system memory, up to 512MB of boot memory, and
general support logic. An expanded feature list is below.
• 6U PICMG 2.16 compatible Single Board Computer, with full hot-swap support per
PICMG 2.1.
• IPMI controller with IPMB0 serial interface, per PICMG 2.9. Peripheral and BMC functions.
• 500MHz to 1.4GHz MPC7448 CPU, or 500MHz to 1.0GHz MPC7447A CPU with
Marvell MV64460 PCI Controller.
• Up to two 512MB banks of 167MHz DDR SDRAM, with ECC.
• PLX PCI 6254 PCI-to-PCI Interface for CPCI backplane.
• Two selectable 115kbps RS-232 or 2Mbps source-synchronous RS-422 ports available to
the backplane connectors.
• Six additional 460kbps source-synchronous RS-422/485 ports available to the backplane
connectors.
• Two 10/100/1000T Ethernet ports available to the backplane connector J3, wired per
PICMG 2.16.
• One 10/100/1000T Ethernet port available to the backplane J4.
• One 64-bit, PCI 33/66MHz or PCI-X 133MHz PMC site, with selectable +3.3V/+5.0V
VIO.
• One 64-bit PCI 33/66MHz PMC site with selectable +3.3V/+5.0V VIO.
• One bank of 64MB to 512MB Boot FEPROM with protected area feature.
• Three USB2.0 ports to the backplane connectors.
• One USB2.0 port to the front panel, on convection models.
• Thermal probe to monitor CPU die temperature and board ambient temperature.
• Sixteen 32-bit general-purpose counter/timers.
• Real Time Clock
• Two 1.5Gbps SATA 1.0 ports to the backplane.
• N-style and C-style versions.
C2K User’s Guide 1-1
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Introduction
C2K Transition Module
GEIP offers an optional C2K Transition Module (C2K-TM) with the following on-board and
rear-panel connections:
• BATT+ (P13)—on-board 2 x 5 connector
• ETH0 (J6)—rear-panel RJ-45 connector
• ETH1 (J7)—rear-panel RJ-45 connector
• ETH2 (J8)—rear-panel RJ-45 connector
• GPIO connector (P14)—on-board 2 x 10-pin header
• ICMB interface (P17)—on-board 2 x 5-pin header
• Misc. Control header (P18)—on-board 2 x 5-pin header
• PMC0 I/O (P11)—on-board 2 x 32-pin header
• PMC1 I/O (P12)—on-board 2 x 32-pin header
• Reset switch, (S1)—rear-panel manual hardware reset micro-switch
• SATA1 (P19)—rear-panel connector
• SATA2 (P20)—rear-panel connector
• Serial I/O: COM1, COM2 RS-232 (P15, P16)—rear-panel DB9 connectors
• Serial I/O: COM3, COM4 RS-232 (P10, P9)—on-board 2 x 5-pin headers
• Serial I/O: COM1–COM4 RS-422 (P1–P4)—on-board 2 x 5-pin headers
• Serial I/O: COM5–COM8 RS-485 (P5–P8)—on-board 2 x 5-pin headers
• USB1 (J9)—rear-panel Type A USB connector
• USB2 (J10)—rear-panel Type A USB connector
• USB3 (J11)—rear-panel Type A USB connector
1-2 C2K User’s Guide
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1.2 Specifications
Physical Description
Form Factor: 6U per PICMG 2.16
Height: 233.20 ± 0.15 mm (9.1811 ± 0.0059 in.)
Depth: 159.85 ± 0.15 mm (6.2933 ± 0.0059 in.)
Weight
C-style:
N-style:
Power Requirements
+5V, +3.3V, +12V: Required from the cPCI backplane
±12V: As required by installed PMC modules
TBD
TBD
NOTE: The +12V requires 10mA for the Hot Swap circuitry which is
otherwise not used by the board.
Introduction
Power Consumption
Peak: 5.7A 4.10A
Idle: TBD TBD
Inrush: 2.0A @ 120µs 2.0A @ 120µs
BATT+: 10µA
Total: 42W
* Measured at VxWorks® prompt
+5V +3.3V
Temperature (operating)
C-style: 0° C to 70° C (ambient)
N-style: -40° C to 85° C
Temperature (storage)
C-style: -40° C to 85° C
N-style: -55° C to 105° C
Relative Humidity - @ 40° C (non-condensing)
C-style: 5–95% @ 40° C
N-style: 5–95% @ 40° C
Shock (half-sine)
C-style: 20g peak / 6ms (3 axes, up & down, 3 hits / direction)
N-style: 40g peak / 11ms (3 axes, up & down, 3 hits / direction),
100g peak / 6ms (3 axes, up & down, 3 hits / direction)
Vibration (random)
C-style: 0.04g2 / Hz @ 5-100Hz (2g rms), 60 min. / axis
N-style: 0.1g2 / Hz @ 5-2000Hz (12g rms), 60 min. / axis
C2K User’s Guide 1-3
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1.3 Compliance
MTBF
Calculations are available in accordance with MIL-HDBK-217.
Please contact GEIP for latest values.
Safety
Designed to meet standard UL1950/60950
Emissions
Designed to meet FCC Part15, SubPart A
1.4 C2K GPIO DC Electrical Characteristics
Introduction
Table 1-1 C2K GPIO DC Electrical Characteristics
Symbol Parameter Min Max Unit
GPIO
Igpio GPIO source current 12 mA
lgpio GPIO sink current 12 mA
Vih GPIO input high voltage 2.0 5.5 V
Vil GPIO input low voltage 0.8 V
Voh GPIO output high voltage 2.4 V
Vol GPIO output low voltage 0.4
Unit Supply Current and Power Dissipation
Ppmc
Maximum Power available to each PMC site, sum of
+5.0V and +3.3V powers
7.5 W
1-4 C2K User’s Guide
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1.5 Block Diagram
MPC7448
G4
Processor
512KB
L2 Cache
MPX
Bus
167MHz
MV64460
PowerPC
System
Controller
DDR
SDRAM
Mem Bus
167MHz
PCI Bus 0
64-bit 33/66MHz64-bit 33/66MHz
RGMII0
RGMII1
RGMII2
COP (J6)
PCI Bus 0
or 133MHz
PCI-X
PCI 6254
cPCI
Bridge
PMC0
J11
J12
J13
J14
VSC8244
Gigabit
Ethernet
PHY
JTAG_J7
to
JTAG
Scan
Chain
cPCI bus
ETH0
ETH1
ETH2
Introduction
cPCI_J1
cPCI_J2
cPCI_J3
cPCI_J3
cPCI_J4
PCI Bus 1
64-bit 33/66MHz
Tem p
Sensor
Board
Config.
EEPROM
User
EEPROM
RTC
Device Bus
Flash
ROM
(soldered)
PMC1
J21
J22
J23
J24
PCI2050B
PCI/PCI
Bridge
GD31244
SATA
Controller
FPGA
SATA 1
SATA 2
ISP 1563
USB 2.0
Controller
8051
IPMC
Hot
Swap
Ctlr
cPCI_J5
USB1
USB2
USB3
Figure 1-1 C2K Block diagram (a)
C2K User’s Guide 1-5
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MV64460
PowerPC
System
Controller
FPGA
USART
COM3
COM4
COM5
COM6
COM7
COM8
GPIO0
GPIO1
GPIO2
GPIO3
RS-232 I/F
RS-422 I/F
RS-232 I/F
RS-422 I/F
RS-422 I/F
RS-485 I/F
RS-485 I/F
RS-485 I/F
RS-485 I/F
Introduction
cPCI_J4
MPSC
Device
Bus
UART0
UART1
GPIO
RS-422 I/F
RS-232 I/F
RS-422 I/F
RS-232 I/F
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
COM1 (RS-422)
COM1 (RS-232)
COM2 (RS-422)
COM2 (RS-232)
cPCI_J5
Figure 1-2 C2K Block diagram (b)
1-6 C2K User’s Guide
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Introduction
1.6 Technical Support
Most issues can be resolved by referring to this manual. If any problems cannot be resolved,
please contact GEIP Technical Support:
If products must be returned, contact GE for a Return Material Authorization (RMA) Number.
This RMA Number must be obtained prior to any return.
RMA request forms can be obtained from:
www.ge-ip.com/rma
GE Technical Support is available at: 1-800-433-2682 in North America,
or +1-780-401-7700 for international calls. Requests for Technical Support can be sent to:
support.huntsville.ip@ge.com
Or, visit our website:
www.ge-ip.com
1.7 Related Documents
For more information on C2K components, refer to the following documents:
Components
• MPC7448 RISC Microprocessor Hardware Specifications—Motorola® Inc., MPC7448EC
Rev. 2, February 2004
• MV64460, MV64461, MV64462 System Controller Hardware Specification - Parts 1 &
2—Marvell Semiconductor, Inc.®, Doc. no. MV-S101286-00(01) Rev B, July 2004
• PCI 6254 (HB6) Dual Mode Universal PCI-to-PCI Bridge DataBook—PLX Technology,
Inc., Version 2.0, May 2003
• PCI2050B PCI-to-PCI Data Manual—Texas Instruments Incorporated, SCPS076E,
November 2004
• ISP1563 Hi-Speed USB PCI Host Controller Product Data—Philips Semiconductors, Document Order Number 9397 750 14244 Rev 01, July 2005
• Intel® 31244 PCI-X to Serial ATA Controller Datasheet—Intel Corporation, Document
Number 273595-005, April 2004
• VSC8244 Quad Port 10/100/1000Base-T PHY with RGMII / RTBI MAC Interfaces—Vitesse Semiconductor Corporation, PB-VSC8244-002, September 2004
• 512Mb: x4, x8, x16, DDR SDRAM Datasheet—Micron Technology, Inc., Rev G 4/04 EN,
April 2004
• Spartan-3E FPGA Family: Complete Data Sheet—Xilinx, Inc., DS312, March 2005
• S29GLxxxN MirrorBit™ Flash Family S29GL512N, S29GL256N, S29GL128N, Data
Sheet—AMD Spansion
• S29GLxxxM MirrorBit™ Flash Family S29GL256M, S29GL128M, S29GL064M,
S29GL032M Data Sheet—AMD Spansion, Publication Number: S29GLxxxM_00 Revi
sion A Amendment 4, March 2004
-
C2K User’s Guide 1-7
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• C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Mixed Signal ISP Flash MCU Family—Silicon Laboratories Inc., Rev 1.3, August 2004
• M41T62 Serial Access Real-Time Clock with Alarms - STMicroelectronics, Rev 10.0,
November 2005
• LTC4244/LTC4244-1 Rugged, CompactPCI Bus Hot Swap Controllers—Linear Technology Corporation, 42441f, February 2004
• Maxim MAX6657/MAX6658/MAX6659 ±1°C, SMBus-Compatible Remote/Local Temperature Sensors with Overtemperature Alarms—Maxim Integrated Products, 19-2034;
Rev. 2, March 2002
Specifications
• ICMB 1.0 Rev 1.3—Intelligent Chassis Management Bus Bridge Specification, April
2003.
• IEEE Std. 802.3-2002—IEEE Standard for Information Technology- Telecommunications
and information exchange between systems- Local and metropolitan area networks - Specific requirements Part 3: Carrier sense multiple access with collision detection
(CSMD/CD) access method and physical layer specifications, March 2002.
• IEEE Std. 1101.2-1992(2001)—IEEE Standard for Mechanical Core Specifications for
Conduction-Cooled Eurocards, January 1993.
• IEEE Std. 1101.10-1996—IEEE Standard for Additional Mechanical Specifications for
Microcomputers using the IEEE Std 1101.1-1991 Equipment Practice, December 1996.
• IEEE Std. 1149.1-1990—IEEE Standard Test Access Port and Boundary Scan Architecture, June 1993.
Introduction
• IEEE Std. 1284-2000—IEEE Standard Signaling Method for a Bidirectional Parallel
Peripheral Interface for Personal Computers, September 2000.
• IEEE1386-2001—IEEE Standard for a Common Mezzanine Card (CMC) Family, June,
2001.
• IEEE1386.1-2001—IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC), June, 2001.
• IEEE Std. 802.3-2002—Part 3: Carrier Sense Multiple Access Collision Detection
(CSMA/CD) Access Method and Physical Layer Definitions, March 2002.
• Intel, Universal Host Controller Interface (UHCI) Design Guide, Revision 1.1,
297650-002.
• IPC-A-610—Acceptability of Electronic Assemblies, Revision C, January 2000.
• IPC-6012A with Amendment 1—Qualification and Performance Specification for Rigid
Printed Boards, July 2000.
• PICMG 2.0 Rev 3.0—CompactPCI Specification, October 1999.
• PICMG 2.1 Rev 2.0—Hot Swap Specification, January 2001
• PICMG 2.16 Rev 1.0—Packet Switching Backplane Specification, September 2001
• PICMG 2.3 Rev 1.0—PMC on CompactPCI Specification, August, 1998.
• PICMG 2.9 Rev 1.0—CompactPCI System Management Specification, February, 2000.
• PCI Special Interest Group—PCI Local Bus Specification, Revision 2.3, October 2001.
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Introduction
• PCI Special Interest Group—PCI-X Local Bus
• Phillips Semiconductors—The I2C Specification, version 2.1, document 9398-393-40011,
January 2000.
• TIA / EIA-232-F-1997, Telecommunications Industry Association—Interface Between
Data Terminal Equipment and Data Circuit-Terminating Equipment Employing Serial
Binary Data Interchange, October 1997.
• TIA / EIA-485-F-1997, Telecommunications Industry Association—
• VITA Standards Organization, VITA 20-2001—American National Standard for Conduction Cooled PMC, August, 2001.
• VITA Standards Organization, VITA 30.1-2002—American National Standard for 2mm
Connector Practice on Conduction Cooled Euroboards, August, 2002.
• VITA Standards Organization, VITA 32-2002—Processor PMC Standard for Processor
PCI Mezzanine Cards, September 2002.
• VITA Standards Organization, VITA 39-2003—PCIX Auxiliary Standard for PMCs and
Processor PMCs, August 2003.
• Universal Serial Bus Specification, Revision 2.0, April 2000.
1. PICMG Specifications are available to PICMG members only. GEIP is not authorized to distribute copies of
these specifications. More information can be found at http://www.picmg.org.
2. VITA Specifications are available to VITA members only. GEIP is not authorized to distribute copies of these
specifications. More information can be found at http://www.vita.com.
3. Data sheets from hardware components can be downloaded from individual vendors web sites.
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Chapter 2: Installation
2.1 What Is Included
The C2K Single Board Computer (SBC) is shipped with the following items:
• C2K SBC Printed Circuit Assembly
2.2 Equipment Needed
The following items are needed to install and operate the C2K:
• C-style CompactPCI-compatible chassis
or
• N-style CompactPCI-compatible chassis
E.S.D.
Caution! Always use proper Electrostatic Discharge (ESD) protection when han-
dling printed circuit boards to avoid seriously damaging components. Product handlers must always be properly grounded.
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Installation
2.3 Power Requirements
The C2K requires +5.0V and +3.3V from the CompactPCI backplane and Hot Swap functions
require +12V. Installed PMC modules may require ±12V.
2.4 Configurations Jumpers
The C2K provides the following configuration header/jumpers:
2.4.1 FLASH_WP# (P6)
P6 is a 2-pin Flash Write-Protect header/jumper that enables write-protection for the flash memory.
If a jumper is installed on P6, the FLASH_WP# signal is asserted preventing writes to the
flash ROM.
If a jumper is not installed on P6, the FLASH_WP# signal is de-asserted allowing writes the
flash ROM.
2.4.2 EM_BOOTSEL# (P7)
P7 is a 2-pin Emergency Boot Select header/jumper that determines which boot code the C2K will
execute after reset. Boot code provided by GEIP is stored in the upper 8MB of flash memory.
If a jumper is installed on the EM_BOOTSEL header (P7), the GEIP firmware will boot
from the GEIP provided emergency boot code stored in the Emergency Boot area of flash.
If a jumper is not installed on the EM_BOOTSEL header (P7), the firmware will jump to
user boot code area and begin executing custom boot code (see “Boot Code Selection” on
page 4-3).
2.4.3 PCI VIO Select (P9, P12)
P9 and P12 are 3-pin header/jumpers that set the VIO for PCI Busses (PMC sites) at +3.3V or
+5V. P12 controls the VIO for PCI Bus 0 (PMC0) and P9 controls VIO for PCI Bus 1 (PMC1).
If a jumper is installed on pins 1 and 2, the VIO is set to +3.3V.
If a jumper is installed on pins 2 and 3, the VIO is set to +5V
1. +3.3V
2. PMC VIO
3. +5V
12 3
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Installation
2.4.4 COP_EN (P10)
P10 is a 2-pin COP Enable header/jumper that isolates the MPC7448 processor from the JTAG
Scan chain and connects the COP header (J6) to the processor to enable software debugging (see
“JTAG circuitry” on page 4-18).
If a jumper is installed on P10, the on-board COP header (J6) is connected to the MCP7448
processor for software debugging.
If a jumper is not installed on P10, the COP header (J6) is disconnected from the processor.
2.4.5 C8051 Debug (P11)
P11 is a 2-pin C8051 Debug header/jumper that isolates the C8051 Microcontroller from the
JTAG Scan chain to enable IPMI software debugging.
If a jumper is installed on P11, the C8051 debugging is enabled.
If a jumper is not installed on P11, the C8051 debugging is disabled.
2.4.6 Header/Jumper Locations
For header/jumper locations, please refer to Figure 3-2 on page 3-2.
NOTE: With the exception of the PCI Bus VIO Select header/jumpers (P9 and P12), none of the
preceding header/jumpers need to have a jumper installed for C2K initial power-up.
2.5 Installation
Caution! Do not attempt to install the C2K in a backplane where the J4 connector is
bused or routed in accordance with the CompactPCI H110 specification. The C2K is
equipped with an IEC key to prevent such installation but if the backplane is not
keyed, installation is still possible.
Caution! Do not attempt to install the C2K in a Fabric slot of a PICMG 2.16 Packet
Switching Backplane. The C2K is equipped with an IEC key to prevent such
installation, but if the backplane is not keyed installation is still possible.
2.5.1 C2K C-style Installation
1. Remove the C2K from the static-safe envelope (see “E.S.D. Caution” on page 2-1).
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Installation
2. Install optional PMC module(s) per manufacturers instructions (see “PMC Sites” on
page 4-14 for restrictions).
3. Configure the PMC VIO using VIO configuration jumpers P9, P12 (see “PCI VIO Select
(P9, P12)” on page 2-2).
4. Install the C2K in a 6U C-style CompactPCI-compliant chassis.
5. Slide the C2K into the slot guide, applying even pressure to the upper and lower extraction
handles. Be careful not to bend connector pins.
NOTE: The C-style C2K is Hot Swap-compliant and can be installed in and removed from
a powered-on Hot Swap-compliant chassis.
After sliding the C2K in the slot guide until the card engages the pins, wait for the blue
front-panel Hot Swap LED to turn off before closing the ejector handle switch (bottom
ejector handle).
6. Push up on the lower extraction handle and down on the upper handle to seat the CompactPCI connectors in the backplane connectors. The red tab on the extraction handles should
“click” when the board is locked into the chassis.
7. Tighten the small phillips-head screws embedded in the upper and lower extraction handles
to secure the C2K to the chassis.
8. Apply power to the chassis.
NOTE: C2K can be installed in a system controller or peripheral slot. If the C2K is not installed
in a system slot, a system controller card must be installed in the system slot to supply a PCI reference clock to C2K.
2.5.2 C2K N-style Installation
1. Remove the C2K SBC from the static-safe envelope (see “E.S.D. Caution” on page 2-1).
2. Install optional PMC module(s) per manufacturers instructions (see “PMC Sites” on
page 4-14 for restrictions).
3. Configure the PMC VIO using VIO configuration jumpers P9, P12 (see “PCI VIO Select
(P9, P12)” on page 2-2).
4. Install the C2K in a 6U N-style CompactPCI-compliant chassis.
5. Slide the C2K into the slot guide, applying even pressure to the upper and lower extraction
handles. Be careful not to bend connector pins.
6. Tighten upper and lower Wedge-Loks™ to 115inch/ounces using a 3/32-inch hex driver.
This secures the C2K in the system chassis and ensures proper heat conduction. Do not
overtighten.
7. Apply power to the chassis.
NOTE: C2K can be installed in a system controller or peripheral slot. If the C2K is not installed
in a system slot, a system controller card must be installed in the system slot to supply a PCI reference clock to C2K.
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PMC Module
Installation
PMC Module
Figure 2-1 C2K (C-style) with PMC modules installed
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PMC Module
Installation
PMC Module
Figure 2-2 C2K (N-style) with PMC modules installed
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Installation
2.6 U-Boot Utility
The C2K includes a universal boot loader (U-Boot) utility that is pre-installed in flash ROM.
U-Boot is designed to work with any operating system including Linux and VxWorks® and performs the following functions:
• Load the O/S kernel from Ethernet, user flash area, or USB
• Program the user flash
• Program the boot flash (self update)
• Load the O/S kernel from user flash
• Set the Real-Time Clock
• Save boot parameters in EEPROM
• Configure the MV64460 Memory Controller
2.6.1 Installation
The C2K is shipped with U-Boot pre-installed in flash memory.
2.6.2 Initialization
The C2K has been initialized during production and testing.
2.6.3 Commands
The following is a summary of commands the U-Boot utility uses for the C2K:
?
autoscr
base
bdinfo
boot boots default, e.g., run ‘bootcmd’
bootd boots default, e.g., run ‘bootcmd’
bootelf
bootm
bootp
bootvx
cmp
coninfo
cp
crc32
date
echo
erase
flinfo
alias for ‘help’
runs script from memory
prints or sets address offset
prints Board Info structure
boots from an ELF image in memory
boots application image from memory
boots image from the network using BootP/TFTP protocol
boots VxWorks from an ELF image
compares memory
prints console devices and information
copies memory
calculates checksum
gets / sets / resets date and time
echoes arguments to console
erases flash memory
prints flash memory information
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Installation
to
help
iminfo
imls
loadb
loads
loop
md
mm
mtest
mw
nm
ping
printenv
protect
rarpboot
reset
run
saveenv
setenv
sleep
tfpboot
version
starts application at address ‘addr’
prints online help
prints header information for application image
lists all images found in flash
loads binary file over serial line (kermit mode)
loads S-Record file over serial line
performs infinite loop on address range
displays memory
modifies memory (auto-incrementing)
tests RAM
writes memory (fill)
modifies memory (constant address)
sends ICMP ECHO REQUEST to network host
prints environment variables
enables or disables flash write-protect
boots image from network using RARP/TFRP protocol
resets the CPU
runs commands in an environment variable
saves environment variables to a persistent storage
sets environment variables
delays execution for some time
boots image from network using TFTP protocol
prints monitor version
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2.6.4 Information Commands
The following U-Boot commands provide information
bdinfo
C2K=> help bdinfo
bdinfo:
prints board information used by U-Boot, such as memory addresses and sizes, clock frequencies
and MAC addresses.
coninfo
C2K=> help coninfo
cp [.b, .w, .l] source target count:
displays console I/O device information.
flinfo
C2K=> help flinfo
flinfo:
Installation
prints information for all flash memory banks.
flinfo N:
prints information for flash memory bank # N.
iminfo
C2K=> help iminfo
iminfo addr [addr ...]:
prints header information for application image starting at address ‘addr’ in memory; this includes verification of the image contents (magic number, header and payload checksums).
imls
C2K=> help imls
imls:
prints information about all images found at sector boundaries in flash.
help
C2K=> help
help [command ...]:
shows help information (for ‘command’).
prints online help for the monitor commands.
without arguments, it prints a short usage message for all commands.
to get detailed information about specific commands, type ‘help’ with one or more command names
as arguments.
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2.6.5 Memory Commands
base
C2K=> help base
base:
prints address offset from memory commands.
base off:
sets address offset for memory commands to ‘off’.
crc32
C2K=> help crd32
crc32 address count [addr]:
calculates CRC32 checksum [save at addr].
cmp
C2K=> help cmp
Installation
cmp [.b, .w, .l] adder1 addr2 count:
compares memory.
cp
C2K=> help cp
cp [.b, .w, .l] source target count:
copies memory.
md
C2K=> help md
md [.b, .w, .l] address [# of objects]:
displays memory.
mm
C2K=> help mm
mm [.b, .w, .l] address:
modifies memory, automatically increments address.
mtest
C2K=> help mtest
mtest [start [end [pattern]]]:
performs simple RAM read/write test.
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mw
C2K=> help mw
mw [.b, .w, .l] address value [count]:
perform memory write.
nm
C2K=> help nm
nm [.b, .w, .l] address:
modifies memory, read and keep address.
loop
C2K=> help loop
loop [.b, .w, .l] address number_of_objects:
performs loop on a set of addresses.
2.6.6 Flash Memory Commands
erase
C2K=> help erase
Installation
erase start end:
erases flash from addr ‘start’ to addr ‘end’.
erase N:SF [-SL]:
erases sectors SF–SL in flash bank # N.
erase bank N:
erases flash bank # N.
erase all:
erases all flash banks.
protect
C2K=> help protect
protect on start end:
protects flash from addr ‘start’ to addr ‘end’.
protect on N:SD [-SL]:
protects sectors SF–SL in flash bank # N.
protect on bank N:
protects flash bank N.
protect on start all:
protects all flash banks.
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protect off start end:
enables writes to flash from addr ‘start’ to addr ‘end’.
protect on N:SD [-SL]:
enables writes to sectors SF–SL in flash bank # N.
protect on bank N:
enables writes to flash bank N.
protect on start all:
enables writes to all flash banks.
2.6.7 Execution Control Commands
boot
C2K=> help boot
bootm
C2K=> help bootm
bootm [addr [arg...]]:
Installation
boots application image stored in memory passing argument ‘arg ...’; when booting a Linux kernel,
‘arg’ can be the address of an initrd image.
go
C2K=> help go
go addr[arg ...]:
starts application at address ‘addr’ passing ‘arg’ as arguments.
2.6.8 Download Commands
bootp
C2K=> help bootp
bootp [loadAddress] [bootfilename]:
bootelf
C2K=> help bootelf
bootelf [address]:
loads address of ELF image.
bootvx
C2K=> help bootvx
bootvx [address]:
loads address of VxWorks ELF image.
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