BEFORE SERVICING THE UNIT, READ THE "SAFETY PRECAUTIONS"
IN THIS MANUAL.
WARNING
WARNING
DVA-206LX
To prevent fire or shock hazard, do not
expose the unit to rain or moisture.
To avoid electrical shock, do not open the
cabinet. Refer servicing to qualified
personnel only. Mains lead must only be
changed at a qualified service shop.
This appliance is classified as a CLASS 1 LASER
product. The CLASS 1 LASER PRODUCT
MARKING is located on the rear panel.
CAU TION . INV ISIB LE LASER R ADIATI ON WHEN O PEN AND IN TERLO CKS DEFE ATED.AV OID EXPO SURE TO BE AM.
VOR SICHT I . UNSIC HTBAR E LASERS TRAHL UNG TRI TT AUS, WE NN DECK EL GEOFFNET UND WENN
SICH ERHEI TSVER RIEGE LUNG UB ERBRU CKT IST. NIC HT DEM ST RAHL AUSS ETZEN I
VARN ING . OSYN LIG LAS ERSTR ALNIN G NAR DEN NA DEL AR OPPN AD OCH SPA RR AR URKO PPLAD ST RALEN
AR FARLI G.
ADVA RSEL. U SYNLIG L ASERS TRALI NG VED ABN ING NAR .
SIKK ERHED SAFBR YDERE E R UDE AF F UNKTI ON . UNDG A UDS/ ETTE LSE FOR ST RALIN G
.
This label is located on the Laser protective
housing inside the enclosure.
Dear Customer,
Thank you for purchasing our product, before
you using it, please read this safety information
and precautions contained in the following
pages to ensure the safe use of your DVD
Player.
To prevent fire or shock hazard, do not expose
this product to rain or moisture.
The apparatus shall not be exposed to dripping
or splashing and that no object filled with
liquids, such as vases, shall be placed on the
apparatus.
CAUTION
To avoid electrical shock, do not open the
cover (or back). Refer servicing to qualified
service personnel.
To prevent electric shock match wide bland of
plug to wide slot, fully insert.
DANGER
This DVD Player uses a visible Laser Beam.
The DVD Player is a class 1 laser product.
To prevent direct exposure laser beam. When
the enclosure is opened, visible laser radiation
is present , which is harmful to the eye.
Use of control or adjustments or performance
of procedures other than those specified herein
may result in hazarded radiation exposure.
Do not open the covers and do not repair
yourself.
Refer to the qualified personnel for servicing.
The lightning flash with arrowhead symbol, within
an equilateral triangle, is intended to alert the
user to the presence of uninsulated "danger
voltage" within the product's enclosure that may
be of sufficient magnitude to constitute a risk of
electric shock to persons.
The exclamation point within an equilateral
triangle is intended to alert the user to presence
of important operating and servicing instructions.
1-1
DVA-206LX
I
MPORTANT SAFETY
INSTRUCTIONS
Failed to meet following precautions
may result in damage to DVD Player
Power Sources
Be sure that the power supply voltage of the
area where this unit will be used meets the
required voltage. (230V AC, 50Hz)
Keep the power cord from heating devices.
Do not pinch the power cord by heavy items.
Power cord should be routed well.
Environment
DO NOT
In an environment prone to extreme temperatures
or humidity.
Near heat source like heat registers, stoves,
or other products (including amplifiers) that
produce heat.
Near water - for example, near bath tub,
wash bowl kitchen sink, and the like.
In direct sunlight, heater.
In a dusty environment.
In where strong magnetic fields are generated.
On a surface that is unstable or subject to
vibration.
place the DVD Player
Overloading
Do not overload wall outlet, extension cords,
or integrated convenience receptacles.
Without using
When not using in near future, unplug power
cord.
Cleaning
Unplug this product from the wall outlet before
cleaning.
Do not use liquid cleaners or aerosol cleaners.
Use a damp cloth for cleaning.
Object and Liquid Entry
Do not place heavy objects on the DVD Player.
Do not push objects of any kind into this product.
Never spill liquid of anything on the product.
3. Unplug B16, if mpeg board in its place, need
to unplug B9, B10 yet.
4. Unscrew 3 screws L (Fig.7).
J
JJHH
K
L
L
I
I
Fig.5
Fig.6
L
1-4
Fig.7
Cover top
(See Fig.1)
1. Unscrew 8 screws A.
2. Pull out cover top upward and backword.
Cabinet front assembly
(See Fig.2)
* This work based on step 1.
1. Power this set, then eject the DVD tray.
2. Force and pull the DVD door out.
3. Unscrew 2 screws B and 3 screws C.
4. Unplug B1-B5, B12.
5. Press the lock D toward two sides and pull
out cabinet front assembly.
A
A
A
Fig.1
B
D
Speaker and subwoofer jack
1. Unplug B16.
2. Unscrew 3 screws E.
C
Fig.2
(See Fig.3)
E
Fig.3
1-5
DVA-206LX
Power board
* This work based on step 4.
1. Unplug B14, B17.
2. Unscrew 3 screws
M
.
Transformer
(See Fig.8)
(See Fig.8)
* This work based on step 4 and step 8.
1. Unscrew 2 screws
N
.
DVD mechanism
(See Fig.8)
* This work based on step 2 and step 4.
P
1. Unscrew 4 screws
.
P
N
N
Fig.8
P
1-6
Description of major ICs
TDA7269SA POWER AMPLIFIER
1. Figure 3. Test and Application Circuit (Stereo Configuration)
+V
S
SW1
ST-BY
R2C3
Q1
R1
DZ
R4
SW2
MUTE
MUTE/
ST-BY
5
IN (L)
7
C1
R3
GND
9
C2
IN (R)
11
D94AU087B
-
-
+
+V
3
6
1
-V
S
C7
S
10 IN- (R)
DVA-206LX
C5
C4
OUT (L)
4+
R10
C9
R7
C8
R9
RL (L)
RL (R)
R5
IN- (L)
8
R6
R8
OUT (R)
2
C6
2. APPLICATION SUGGESTIONS (Demo Board Schematic)
The recommended values of the external components are those shown the demoboard
schematic different values can be used, the following table can help the designer.
S
U
COMPONEN
T
GGESTION
V
ALU
E
P
UR
POSE
ARGER THAN
L
RECOMMENDED VALU
E
R110KΩMute CircuitIncrease of Dz Biasing
Current
R215KΩMute CircuitV
R318KΩMute CircuitV
R415KΩMute CircuitV
R5, R818KΩClosed Loop Gain
R6, R9560ΩDecrease of Gain
Setting (*)
#5 Shifted DownwardV
pin
#5 Shifted UpwardV
pin
#5 Shifted UpwardV
pin
Increase of Gain
R7, R104.7ΩFrequency StabilityDanger of OscillationsDanger of Oscillations
C1, C21µFInput DC DecouplingHigher Low Frequency Cutoff
C31µFSt-By/M ute Time
Larger On/Off TimeSmaller On/Off Time
Constant
C4, C61000µFSupply Voltage BypassDanger of Oscillations
C5, C70.1µFSupply Voltage BypassDanger of Oscillations
C8, C90.1µFFrequency Stability
- No external resistors necessary for driver
outputs
(P-ch open-drain + pull-down resistor output)
- Serial interface (CLK, STB, D
- Package: 44-pin plastic QFP and LQFP
2. Pin Assignments
EE (max)
= VDD – 35V )
, D
)
IN
OUT
General Description
The AD6315 is a VFD (Vacuum Fluorescent Display
or fluorescent Indicator Panel) driver that is driven
on a 1/4- to 1/12- duty factor. It consists of 16
segments and 4 grids output lines, 8 segments /
grid output driving lines, a display memory, a control
circuit, and a key scan circuit. Serial data is input to
the AD6315 through a 3-wire serial interface. This
VFD driver is ideal as a peripheral device for a
single-chip microcomputer
.
Seg20/Grid9
Seg21/Grid
Seg22/Grid
Seg23/Grid6
Seg24/Grid5
Grid
Grid3
Grid2
Grid1
V
DD
11
12
/Grid
/Grid
18
17
Seg19/Grid10
Seg
Seg
31
32
33
3435363738394041424344
8
7
16
/KS
16
VEESeg
29
30
28
14
13
12
11
10
/KS
/KS
/KS
/KS
14
13
12
Seg15/KS15
Seg
Seg
Seg
25
26
27
11
Seg
24
/KS
10
Seg
23
2221201918171615141312
Seg9/KS9
Seg8/KS
Seg7/KS
8
7
Seg6/KS6
Seg5/KS5
4
Seg4/KS4
Seg3/KS3
Seg2/KS2
Seg1/KS1
V
DD
1-8
V
V
SS
11
10
9
8
7
6
5
4
3
2
1
1
LED
2
LED
4
OSC
LED
LED3
OUT
D
IN
D
CLK
STB
1
KEY
2
KEY
SS
3. Pin Descriptions
y
Symbol Name No. Description
D
IN
D
OUT
Data input 7
Data output 6
STB Strobe 9
CLK
OSC
Seg
/KS1 to
1
Seg
/KS16
16
Grid
to Grid4 High-voltage output (Grid) 39 to 42 Grid output pins
1
/Grid12 to
Seg
17
Seg
/Grid5
24
to LED4 LED output 1 to 4 CMOS output
LED
1
, KEY2 Key data input 10, 11
KEY
1
V
DD
V
SS
V
EE
Clock input 8
Oscillator pin 5
High-voltage output (Segment) 14 to 29
High-voltage output
(Segment/grid)
31 to 38
Logic power 13, 43
Logic ground 12, 44 Connect this pin to system GND.
Pull-down level 30
Input serial data at rising edge of shift clock,
starting from the low order bit.
Output serial data at the falling edge of the
shift clock, starting from low order bit. This is
N-ch open-drain output pin.
Initializes serial interface at the rising or
falling edge of the AD6315. It then waits for
reception of a command. Data input after
STB falling is processed as a command.
While command data is processed, current
processing is stopped, and the serial
interface is initialized. While STB is high, CLK
is ignored.
Reads serial data at the rising edge, and
outputs data at the falling edge.
Connect resistor in between this pin and Vss to set
up the oscillation frequency.
Segment output pins (Dual function as key
source)
These pins are selectable for segment or grid
driving.
Data input to these pins is latched at the end
of the display cycle.
Logic power supply
Driver power supply
DVA-206LX
4. Ordering Information
AD6315 X X
Package
Q: QFP-44L
Packing
Blank : Tra
L : LQFP-44L
1-9
DVA-206LX
5. Absolute Maximum Ratings (TA = 25OC, VSS = 0V)
Parameter Symbol Rating
Logic supply voltage VDD -0.5 to +6.0 V
Driver supply voltage V
Logic input voltage V
VFD driver output voltage V
LED driver output current I
VFD driver output current I
Power dissipation P
Operating ambient temperature T
Storage temperature T
Note :
Derate at -6.4W/OC TA = 25OC or higher.
Caution :
If the absolute maximum rating of even one of the above parameters is exceeded even
momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,
specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the range of the absolute maximum ratings.
V
EE
- 0.5 to VDD + 0.5 V
I1
V
O2
O1
O2
D
-25 to +85
A
-50 to +150
stg
+ 0.5 to VDD – 40 V
DD
- 0.5 to VDD + 0.5 V
EE
15 mA
-40 (grid)
-15 (segment)
800 (Note) mW
Unit
mA
O
C
O
C
6. Recommended Operating Range (TA = -20 to 70OC, VSS = 0V)
Parameter Symbol Min. Typ. Max. Unit
Remark :
Logic supply voltage V
High-level input voltage V
Low-level input voltage V
Driver supply voltage V
Maximum power consumption
Pmax = VFD driver dissipation + R
consumption
Where
segment current = 3mA, grid current = 15mA, and LED current = 20mA
VFD driver dissipation = number of segments x 6 + number of grids/(number of grids + 1) x
30(mW)
R
Ldissipation
~
(VDD - VEE)2 / 50 x (number of segments + 1 ) (mW)
=
LED driver dissipation = number of LEDs x 20 (mW)
Dynamic power consumption = V
4.5 5 5.5 V
DD
0.7 VDD VDD V
IH
0 0.3 V
IL
0 VDD-35
EE
L dissipation + LED driver dissipation + dynamic power
DD x 5 (mW)
V
DD
V
1-10
7. Application Circuit
DVA-206LX
V
DD
To Microcontroller
-30VV
V
DD
R1
D
OUT
D
IN
CLK
LED
LED1
LED2
R3
In the case of low-level output is display on signal.
OSC
LED3
LED4
R2
STB
AD16315
5
V
DD
0V
V
DD
C
V
SS
EE
to Grid4
1
Grid
4
12
/Grid
/Grid
17
to Seg
Seg
8
24
16
/KS
16
Seg
1
/KS
1
Seg
KEY
KEY
2
1
R4
Key Matrix
Note
(16X2)
Note :
Fluorescent Indicator Panel (FIP)
(VFD)
F+
Driving voltage for FIP (VFD)
F-
1-11
DVA-206LX
BD3871 SOUND PROCESSOR
DescriptionDimension (Units : mm)
BD3871FS is a sound processor for CD/MD radio
cassette player. This IC provides all functions,
such as input selector (3 input sources), an input
gain amplifier (25dB, 27dB, 29dB),and a surround,
tone (bass, treble). This IC can be controlled
by a 2-wire serial data interface.
Features
7.8±0.3
1.8±0.1
5.4±0.2
0.1 1
1) Can select center frequency and Q value of Bass
characteristics by external components.
2) Mute switch at the input terminal can reduce cross talk.
3) Surround function is composed without external components.
4) Ideal for energy-saving designs with low current consumption
due to the adoption of the BiCMOS process, allowing easy-design
of the regulator blocks in the set.
10.0±0.2
24
13
12
1
0.36±0.1
0.8
SSOP-A24
0.3Min
0.15±0.1
0.15
Applications
CD radio cassette player, MD radio cassette player, Micro component stereo
The SST39VF08 8 device is a 1M x8 CMO S Mult i-P urpose
Flash (MPF) manufactured with SST’s proprietary, high
performance CMOS SuperFlash technology. The split-gate
cell design and th ick-oxide tunneling in jector attain better
reliability and manufacturability compared with alternate
approaches. The S ST39V F088 wr i tes (P rogram or E rase)
with a 2.7-3.6V power supply. It conforms to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39VF088 device provides a typical Byte-Program time
of 14 µsec. The devices u s e Toggle Bit or Data# Polling to
indicate the comp letion of Program operation. To protect
against inadver ten t wri te, they have on-chip hardware and
Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
The SST39VF088 device is suited for applications that
require convenient and economica l updating of program,
configuration, or da ta memory. For all system appl i ca tio ns,
they significantly i mp r ove performa nc e an d re liability, while
lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash
technologies. The tota l energy consumed is a function of
the applied voltage, curre nt, and time of ap plic ation. S inc e
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. They
also improve flexibility while l owerin g the cost for program ,
data, and configuration storage applications.
The SuperFlash technology provides fixed Erase an d P r ogram times, independent o f the num ber of Erase/ Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with al ternativ e flas h techn ologies , whos e Erase
and Program times i ncrease with accumul ated Erase/P rogram cycles .
To meet high density, surface mount requirements, the
SST39VF088 is offered in 48-lead TSO P packaging. See
Figure 1 f or pi n assign ments .
CE#Chip EnableTo activate the device when CE# is low.
OE#Output EnableTo gate the data output buffers.
WE#Write EnableTo control the Write operations.
V
DD
V
SS
NCNo ConnectionUnconnected pins.
1. AMS = Most significant address
A
MS
IN DESCRIPTION
Address InputsTo provide memory addresses. During Sector-Erase AMS-A12 address lines will s elect the
0
Data Input/outputTo output data during Read cycles and receive input data during Write cycles.
0
sector. During Block-Erase A
MS-A16
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
Power SupplyTo provide power supply voltage:2.7-3.6V for SST39VF088
Ground
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of t his data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
Description
The AT24 C01A/02/04 /08/1 6 provides 1024/ 2048/40 96/8192/ 16384 bits of ser ial electrically erasable and programmable read-only memor y (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP,
8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8lead TSSOP and 8-ball dBGA2 packages and is accessed via a 2-wire serial interface.
In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V)
versions.
Pin Configurations
Pin NameFunction
A0 - A2Address Inputs
SDASerial Data
SCLSerial Clock Input
WPWrite Pro tect
NCNo Connect
GNDGround
VCCPower Supply
8-lead TSSOP
A0
A1
A2
GND
8-ball dBGA2
VCC
WP
SCL
SDA
Bottom View
8
1
2
3
4
8
7
6
5
VCC
7
WP
6
SCL
5
SDA
1
A0
2
A1
3
A2
4
GND
GND
A0
A1
A2
VCC
WP
SCL
SDA
8-lead SOI C
1
2
3
4
8-lead MAP
8
7
6
5
Bottom View
VCC
8
WP
7
SCL
6
SDA
5
A0
1
A1
2
A2
3
GND
4
16K (2048 x 8)
AT24C01A
AT24C02
AT24C04
AT24C08
AT24C16
Note: 1. This device is not recom-
mended for new designs.
Please refer to AT24C08A.
2. This device is not recommended for new designs.
Please refer to AT24C16A.
(1)
(2)
A0
A1
A2
GND
8-lead PDIP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
5-lead SOT23
SCL
GND
SDA
5-lead SOT23 Rotated (R)
(1k only)
1
2
3
WP
5
VCC
4
SCL
GND
SDA
1
2
3
VCC
5
NC
4
0180R–SEEPR–4/04
1
1-19
DVA-206LX
Absolute Maximum Ratings
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ..........................................6.25V
DC Output Current........................................................5.0 mA
Block Diagram
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the dev ice . This i s a stress r at ing onl y and
functional operati on of the de vic e at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or extend ed periods ma y affect d evice
reliability.
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
R
0180R–SEEPR–4/04
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1B
10/7/03
REV.
1-21
DVA-206LX
K4S161622DCMOS SDRAM
512K x 16Bit x 2 Banks Synchronous DRAM
GENERAL DESCRIPTIONFEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle (2K/32ms)
The K4S161622D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance memory system applications.
CLKSystem ClockActive on the positive going edge to sample all inputs.
CSChip Select
CKEClock Enable
A0 ~ A10/APAddress
BABank Select Address
RASRow Address Strobe
CASColumn Address Strobe
WEWrite Enable
L(U)DQMData Input/Output Mask
DQ0 ~ 15Data Input/OutputData inputs/outputs are multiplexed on the same pins.
VDD/VSSPower Supply/GroundPower and ground for the input buffers and the core logic.
VDDQ/VSSQData Output Power/Ground
N.C/RFU
No Connection/
Reserved for Future Use
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
1-23
DVA-206LX
K4S161622DCMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
ParameterSymbolValueUnit
Voltage on any pin relative to VssVIN, VOUT-1.0 ~ 4.6V
Voltage on VDD supply relative to VssVDD, VDDQ-1.0 ~ 4.6V
Storage temperatureTSTG-55 ~ +150°C
Power dissipationPD1W
Short circuit currentIOS50mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
DSampling Frequency: 5 kHz to 200 kHz
DSystem Clock: 128 f
512 fS, 768 fS, 1152 fS With Auto Detect
, 192 fS, 256 fS, 384 fS,
S
DSoftware Control (PCM1753, PCM1755):
− Accepts 16-, 18-, 20-, and 24-Bit Audio
Formats: Standard, I2S, and Left-Justified
− Digital Attenuation: 0 dB to −63 dB,
0.5 dB/Step
− Digital De-Emphasis
− Digital Filter Rolloff: Sharp or Slow
− Soft Mute
− Zero Flags for Each Output
− Open-Drain Output Zero Flag (PCM1755)
DHardware Control (PCM1754):
− I2S and 16-Bit Word, Right-Justified
− 44.1 kHz Digital De-Emphasis
− Soft Mute
− Zero Flag for L-, R-Channel Common
Output
DPower Supply: 5-V Single Supply
DSmall 16-Lead SSOP Package, Lead-Free
APPLICATIONS
DA/V Receivers
DDVD Movie Players
DDVD Add-On Cards For High-End PCs
DDVD Audio Players
DHDTV Receivers
DCar Audio Systems
DOther Applications Requiring 24-Bit Audio
DESCRIPTION
The PCM1753/54/55 is a CMOS, monolithic, integrated
circuit, which includes stereo digital-to-analog converters
and support circuitry in a small 16-lead SSOP package.
The data converters use TI’s enhanced multilevel
delta-sigma architecture, which employs 4th-order noise
shaping and 8-level amplitude quantization to achieve
excellent dynamic performance and improved tolerance to
clock jitter. The PCM1753/54/55 accepts industrystandard audio data formats with 16- to 24-bit data,
providing easy interfacing to audio DSP and decoder
chips. Sampling rates up to 200 kHz are supported. A full
set of user-programmable functions is accessible through
a three-wire serial control port, which supports register
write functions.
The PCM1753/55 is pin compatible with the PCM1748,
PCM1742, and PCM1741, except for pin 5.
SLES092 − OCTOBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
For the most current specification and package information, refer to our web site at www.ti.com.
PACKAGE
CODE
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
www.ti.com
ORDERING
NUMBER
PCM1753DBQTube
PCM1753DBQRTape and reel
PCM1754DBQTube
PCM1754DBQRTape and reel
PCM1755DBQTube
PCM1755DBQRTape and reel
(1)
TRANSPORT MEDIA
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
Supply voltage: V
Ground voltage differences: AGND, DGND±0.1 V
Input voltage−0.3 V to 6.5 V
Input current (any pins except supplies)±10 mA
Ambient temperature under bias−40°C to 125°C
Storage temperature−55°C to 150°C
Junction temperature150°C
Lead temperature (soldering)260°C, 5 s
Package temperature (IR reflow, peak)260°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CC
(1)
UNIT
−0.3 V to 6.5 V
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VCC = 5 V , fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted
PCM1753DBQ, PCM1754DBQ,
PCM1755DBQ
MINTYPMAX
Resolution24Bits
DATA FORMAT
PCM1753
PCM1755
PCM1754I2S, standard
PCM1753
PCM1755
PCM175416−24-bit (I2S), 16-bit (standard)
Audio data formatMSB first, 2s complement
f
S
Sampling frequency5200kHz
System clock frequency
Standard, I2S, left-justified
16-, 18-, 20-, 24-bit, selectable
128 fS, 192 fS, 256 fS, 384 fS,
512 fS, 768 fS, 1152 f
S
2
1-28
www.ti.com
V
V
PCM1753/PCM1755
PCM1754
PIN ASSIGNMENTS
DVA-206LX
SLES092 − OCTOBER 2003
(TOP VIEW)
BCK
DATA
LRCK
DGND
NC
V
CC
OUT
OUT
1
2
3
4
5
6
L
R
7
8
16
15
14
13
12
11
10
9
FUNCTIONAL BLOCK DIAGRAM
BCK
LRCK
DATA
(FMT) ML
(MUTE) MC
(DEMP) MD
Audio
Serial
Port
Oversampling
Serial
Control
Port
SCK
ML
MC
MD
ZEROL/NA
ZEROR/ZEROA
V
COM
AGND
4y/8y
Digital
Filter
and
Function
Control
Enhanced
Multi-Level
Delta-Sigma
Modulator
BCK
DATA
LRCK
DGND
V
V
OUT
V
OUT
NC
CC
(TOP VIEW)
1
2
3
4
5
6
L
R
DAC
DAC
7
8
Output Amp
and
Low-Pass Filter
Output Amp
and
Low-Pass Filter
16
15
14
13
12
11
10
SCK
FMT
MUTE
DEMP
TEST
ZEROA
V
COM
9
AGND
V
OUT
V
COM
V
OUT
L
R
(TEST)
SCK
†
Open-Drain Output for the PCM1755
( ): PCM1754
System
Clock
Manager
System Clock
Zero Detect
†
ZEROL/NA
†
(ZEROA)
ZEROR/ZEROA
Power Supply
DGND
V
CC
AGND
1-29
I/O
DESCRIPTION
DVA-206LX
SLES092 − OCTOBER 2003
Terminal Functions
TERMINAL
NAMENO.
PCM1753/PCM1755
AGND9−Analog ground
BCK1IAudio data bit clock input
DATA2IAudio data digital input
DGND4−Digital ground
LRCK3IL-channel and R-channel audio data latch enable input
MC14IMode control clock input
MD13IMode control data input
ML15IMode control latch input
NC5−
SCK16ISystem clock input
V
CC
V
COM
V
L7OAnalog output for L-channel
OUT
V
R8OAnalog output for R-channel
OUT
ZEROR/ZEROA11OZero flag output for R-channel/Zero flag output for L-/R-channels
ZEROL/NA12OZero flag output for L-channel/Not assigned
PCM1754
AGND9−Analog ground
BCK1IAudio data bit clock input
DATA2IAudio data digital input
DEMP13IDe-emphasis control
DGND4−Digital ground
FMT15IData format select
LRCK3IL-channel and R-channel audio data latch enable input
MUTE14IAnalog mixing control
NC5−
SCK16ISystem clock input
TEST12ITest pin. Ground or open
V
CC
V
COM
V
L7OAnalog output for L-channel
OUT
V
R8OAnalog output for R-channel
OUT
ZEROA11OZero flag output for L/R channels
(1)
Schmitt-trigger input with internal pulldown.
(2)
Open-drain output (PCM1755).
6−Analog power supply, 5 V
10−Common voltage decoupling
6−Analog power supply, 5 V
10−Common voltage decoupling
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
www.ti.com
(2)
1-30
MECHANICAL DATA
MSOI004E JANUARY 1995 – REVISED MAY 2002
DBQ (R–PDSO–G**) PLASTIC SMALL–OUTLINE P ACKAGE
DVA-206LX
0.025 (0,64)
24
112
A
0.010 (0,25)
0.004 (0,10)
0.012 (0,30)
0.008 (0,20)
13
0.157 (3,99)
0.150 (3,81)
0.069 (1,75) MAX
0.005 (0,13)
0.244 (6,20)
0.228 (5,80)
Seating Plane
0.004 (0,10)
0.008 (0,20) NOM
Gauge Plane
0.010 (0,25)
0°–8°
0.035 (0,89)
0.016 (0,40)
PINS **
DIM
A MAX
A MIN
D
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO–137.
M0–137
VARIATION
16
0.197
(5,00)
0.189
(4,80)
ABADAEAF
2024
0.344
(8,74)
0.337
(8,56)
0.344
(8,74)
0.337
(8,56)
28
0.394
(10,01)
0.386
(9,80)
4073301/F 02/02
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1-31
DVA-206LX
DVD SINGLE CHIP MPEG A/V PROCESSOR
1. GENERAL DESCRIPTION
PPrreelliimmiinnaarry
y
SPHE8281S/Sx
SPHE8281S A/V decoder is a single-chip integrated DVD A/V
decoder. It is designed to maximize system performance with
minimum cost. It integrates DVD/CD controller, host processor,
A/V decoding hardware, audio quality ADC and a 6-channel
multi-format TV-encoder.
SPHE8281S supports DVD and CD physical formats. For logical
formats it supports DVD-Video, Super Video CD, Video CD,
CD-DA, OKO, and CD-ROM discs.
SPHE8281S performs real-time decoding and playback of
ISO/IEC 11172 MPEG1, 13818 MPEG2 sources. For audio it
supports Dolby Digital and MPEGI/II Layer1/2, PCM, LPCM audio
playback.
Application utilizing the SPHE8281S is presented below:
IR
VFD
front panel
SPHE8281S
SPHE8281S also combines all the functions required for a
high-performance progressive-scan DVD system. Built-in
de-interlacing hardware allows high quality DVD playback. The
embedded digital audio decoder is able to support key control and
audio sound effects for Karaoke.
In additional to that SPHE8281S includes a flexible 2D graphics
engine for high quality user interface and other applications.
Complex application could be built using this platform easily.
Development tools of SPHE8281S include complete compiler
tools, programming guide and system application libraries.
P 1470-011100-001X0POLY BAG2IB/ACCESSORY
P 2470-011526-000X0POLY BAG1AC CORD
P 3450-021410-001X0EPE FOAM BAG1UNIT
P 4450-001385-001W0POLY FORM TOP1UNIT
P 5450-001386-000W0POLY FORM BOTTOM1UNIT
P 6410-020918-000*0GIFT BOX 1UNIT
P 7430-002085-000X0MASTER CARTON1UNIT
▓ Parts list (Accessories)
!
ItemParts numberParts nameQ'tyDescriptionArea
A 1600-D20LXB-02SX0REMOTE CONTROL1
A 2440-001750-000X0INSTRUCTION MANUAL1
A 3AN-0105-1-----YFM ANT WIRE1
A 4AN-0103-1-----VAM LOOP ANT1
A 55-30-32BATTERY2
A 611-F1500-SA0-3VVEDIO LINE CORD1
A 7644-206LX0-02S00Speaker Box Assembly1
2-10
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