Fujitsu Pro V3505 Schematics

A

Y41/Y40 Block Diagram

B

C

D

E

Project code: 91.4P501.001

4 4

CLK GEN.

IDT CV125

3 4, 5

Mobile CPU

Yonah 478
Celeron M

G792

19

PCB P/N : 48.4P501.011
Layout PCB #: 05249-1

Y41 SMT BOM: 55.4P501.M01G
Y40 SMT BOM: 55.4B601.M01G

SYSTEM DC/DC

TPS51120

INPUTS

DCBATOUT

OUTPUTS

5V_S5

3V_S5

38

HOST BUS

DDR2

533/667MHz

533/667 MHz

DDR2

11,12

533/667MHz

Calistoga

533/667 MHz

3 3

Line In/MIC In

28

28

Internal MIC In

Line Out

To Port Replicator

28

Line Out

2 2

28

INT.SPKR

RJ11

23

1 1

11,12

Codec

ALC861

27

OP AMP

G1421B

MODEM

MDC Card

HDD

CDROM

MINI USB
Blue-tooth

21

AZALIA

28

21

20

20

USB x1 port

DMI I/F

ICH7-M

SATA

PATA

USB/B

4 PORTS

USB x4 ports

21

http://laptop-motherboard-schematic.blogspot.com/

400/533/667MHz

6,7,8,9,10

100MHz

PCI BUS

PCIEx1

PCIEx1

LPC BUS

15,16,17,18

USB

2 PORTS

Adapter-in

C/Y

LVDS

0 Ohm resistor

(Y40)

RGB CRT

RGB switch

(Y41)

14

To Port Replicator

ENE

CB714

CARDBUS

CardReader

24

LAN

10/100/GIGA
88E8055

Mini Card

802.11A/B/G

22

FIR

32

6102

(Y41)

33

PS2

Ext. MS/KB

SIO

87383

(Y41)

COM

PORT PORT

LPT

Port Replicator

TV Out

WXGA/SXGA+
15"LCD

CRT

PCMCIA I/F

PWR SW

CP2211

LAN switch

(Reserved)

26

KBC

KB3910

(Y41)

14

13

14

PCMCIA
SLOT

Support
TypeII

25 25

SD/MMC/MS

3 in 1

23

INT.
KB

Touch
Pad

BIOS ROM
MX29LV800

TXFM

CRT

PORT

LAN

PORT

PCB STACKUP

TOP

VCC

S

S

GND

BUTTOM

25

TXFM RJ45

To Port Replicator

30

LPC

DEBUG
CONN.

30

31

Phone
jack
Line Out

3129

33

SYSTEM DC/DC

TPS51124

INPUTS OUTPUTS

DDR_VREF_S3
DDR_VREF_S0

OUTPUTSINPUTS
BT+

18V 4.0A

UP+5V

5V 100mA

OUTPUTS
VCC_CORE

0~1.3V
48A

144Friday, April 07, 2006

144Friday, April 07, 2006

144Friday, April 07, 2006

1D05V_S0
1D8V_S3

36,37

DCBATOUT

TPS51100

1D8V_S3

APL5332KAC

3D3V_S5 2D5V_S0

APL5912-U

1D8V_S3 1D5V_S0

MAXIM CHARGER

MAX8725

2323

DCBATOUT

CPU DC/DC

ISL6262

INPUTS

DCBATOUT

<Variant Name>

<Variant Name>

<Variant Name>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet of

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

39

41

41

41

40

A

ICH7M Integrated Pull-up
and Pull-down Resistors

EE_DIN,EE_DOUT,
GNT[4]#/GPIO48,
LAD[3:0]#/FHW[3:0]#,
LDRQ[0], LDRQ[1]/GPIO[41],

4 4

PWRBTN#,

DDREQ

DD[7],

ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0],

EE_CS,

SPI_ARB, SPI_CLK,

USB[7:0][P,N]

LAN_CLK

GNT[3:0],
GNT[5]#/GPO17,

TP[3]

ACZ_SYNC,ACZ_SDOUT,

GPIO[25],

PME#,

LAN_RXD[2:0]

DPRSLPVR/GPIO16,

SPKR,

ICH7 internal 20K pull-ups

ICH7 internal 11.5K pull-downs

ICH7 internal 20K pull-downs

ICH7 internal 15K pull-downs

ICH7 internal 15K pull-upSATALED#

ICH7 internal 100K pull-down

ICH7-M EDS 17837 1.5V1

ICH7M IDE Integrated Series
Termination Resistors

3 3

DD[15:0],
DDACK#,
DCS3#,

IORDY,

IDEIRQ

DIOR#, DREQ,DIOW#,

DA[2:0],

DCS1#,

approximately 33 ohm

ICH7M Functional Strap Definitions

Signal

ACZ_SDOUT

ACZ_SYNC

EE_CS
EE_DOUT

2 2

GNT2#

GNT3#

GNT5#/
GPIO17#,
GNT4#/
GPIO48

DPRSLPVR Reserved
GPIO25

INTVRMEN

LINKALERT#
REQ[4:1]#

1 1

SATALED#
SPKR

TP3

Usage/When Sampled

XOR Chain Entrance/
PCIE Port Config bit1,
Rising Edge of PWROK

PCIE bit0,
Rising Edge of PWROK.

Reserved
Reserved
Reserved
Top-Block

Swap Override.
Rising Edge of PWROK.

Boot BIOS Destination
Selection.
Rising Edge of PWROK.

Reserved.
Rising Edge of RSMRST#.

Integrated VccSus1_05
VRM Enable/Disable.
Always sampled.

Reserved
XOR Chain Selection.

Rising Edge of PWROK.
Reserved This signal should not be pull low.
No Reboot.

Rising Edge of PWROK.

XOR Chain Entrance.
Rising Edge of PWROK.

Allows entrance to XOR Chain testing when TP3
pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h)

Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal should not be pull high.
This signal should not be pull low.
This signal should not be pull low.
Sampled low:Top-Block Swap mode(inverts A16 for

all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.

This signal should not be pull high.

This signal should not be pull low.
Enables integrated VccSus1_05 VRM when

sampled high

Requires an external pull-up resistor.

TBD, Chapter 8.

If sampled high, the system is strapped to the
"No Reboot" mode(ICH7 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.

This signal should not be pull low unless using
XOR Chain testing.

Comment

http://laptop-motherboard-schematic.blogspot.com/

B

954305D 27Mhz/LCDCLK Spread
and Frequency Selection Table

SS2

SS3
Byte9
bit 7

000
0000

0
0
0
0
0
1 +-0.25 Center
1
1
1
1
1
11
11

SS1

bit6

bit5

0

1

0

1

1

0
0

1

1

1
11

0

0
00
001
0

1
0

1
1
1

1

PCI Routing

CB714

page 16

22 0

C

SS0
bit4

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

INT -> PIRQ
A->G, B->E,

Spread Amount%

-0.50 Down

-1.00 Down

-1.50 Down

-2.00 Down

-0.75 Down

-1.25 Down

-1.75 Down

-2.25 Down

+-0.5 Center
+-0.75 Center
+-1.0 Center
+-0.25 Center
+-0.5 Center
+-0.75 Center
+-1.0 Center

page 24

D

E

Calistoga Strapping Signals and
Configuration

page 3

REQ/GNTIDSEL

Pin Name

CFG[2:0]

CFG[4:3]
CFG5

CFG7

CFG8

CFG9

CFG[11:10] Reserved

CFG[13:12]

CFG[15:14]
CFG16

CFG17
CFG18

CFG19

CFG20

SDVOCRTL
_DATA

All strap signals are sampled with respect to the leading

NOTE:

edge of the Calistoga GMCH PWORK in signal.

Strap Description

FSB Frequency Select

Reserved
DMI x2 Select
ReservedCFG6

CPU Strap
Reserved

PCI Express Graphics
Lane Reversal

XOR/ALL Z test
straps

Reserved
FSB Dynamic ODT

Global R-comp Disable
(All R-comps)

VCC Select

DMI Lane Reversal

SDVO/PCIE
Concurrent

SDVO Present

EDS 17050 0.71

Configuration

001 = FSB533
011 = FSB667
others = Reserved

0 = DMI x2

1 = DMI x4

0 = Reserved

1 =Mobile CPU(Default)

0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane
Numbered in order

00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled

11 = Normal Operation

(Default)

Reserved

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled

0 = All R-comp Disable

1 = Normal Operation (Default)
0 = 1.05V

1 = 1.5V

0 = Normal operation (Default):lane
Numbered in order

1 =Reverse Lane,4->0,3->1 ect...

0 = Only SDVO or PCIE x1 is
operational (Default)

1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port

0 = No SDVO Card present

1= SDVO Card present

(Default)

(Default)

(Default)

page 7

(Default)

Device SSID/SVID

Device

10C1LAN 88E8055

Codec ALC861 10C1

SVIDSSID
1734
1734

<Variant Name>

<Variant Name>

<Variant Name>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet of

Reference

Reference

Reference

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

244Friday, April 07, 2006

244Friday, April 07, 2006

244Friday, April 07, 2006

A

3D3V_S0 3D3V_S0

3D3V_CLKPLL_S0

R236

R236

12

0R3-0-U-GP

0R3-0-U-GP

12

C264

C264
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C263

C263
SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

12

B

R432

R432

3D3V_48MPWR_S0

12

4D99R3F-1-GP

4D99R3F-1-GP

C446

C446
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C451

C451
SC10U10V5KX-2GP

SC10U10V5KX-2GP

Y41-SB

C448

C448
SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

C

12

C450

C450
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_CLKGEN_S0

12

C256

C256
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C449

C449
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C257

C257
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

D

R433

R433
0R3-0-U-GP

0R3-0-U-GP

12

C255

C255
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_S0

12

12

C447

C447
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

E

4 4

3D3V_S0

12

R428

R428
10KR2J-3-GP

10KR2J-3-GP

DY

DY

SS_SEL

H/L: 100/96MHz

12

R429

R429
10KR2J-3-GP

10KR2J-3-GP

3 3

C249

C249

1 2

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

C248

C248

1 2

SC33P50V2JN-3GP

SC33P50V2JN-3GP

Y41,-1

2 2

D_REFCLK7

D_REFCLK#7

12

PCLK_KBC29

TP54TPAD30TP54TPAD30

PCLK_CB24
PCLK_SIO32

PCLK_FWH31
CLK_ICHPCI16

PM_STPPCI#16

SMBC_ICH11,18

SMBD_ICH11,18

SRN33J-5-GP-U

SRN33J-5-GP-U

GEN_XTAL_OUT_R

X2

X2
X-14D31818M-31GP

X-14D31818M-31GP

82.30005.831

82.30005.831

CLK14_SIO32
CLK_ICH1416

CLK_EN#36

R228 33R2J-2-GPR228 33R2J-2-GP

1 2

R207 33R2J-2-GP

R207 33R2J-2-GP

1 2

R208 33R2J-2-GPR208 33R2J-2-GP

1 2

R209 33R2J-2-GPR209 33R2J-2-GP

1 2

R211 33R2J-2-GPR211 33R2J-2-GP

1 2

R210 33R2J-2-GPR210 33R2J-2-GP

1 2

1

4

2 3

RN17

RN17

GEN_XTAL_IN

R227 470R2J-2-GPR227 470R2J-2-GP
R230 22R2J-2-GPR230 22R2J-2-GP
R229 22R2J-2-GPR229 22R2J-2-GP

DY

DY

R200 10KR2J-3-GPR200 10KR2J-3-GP

H/L : CPU_ITP/SRC7

1 2
1 2

1 2

3D3V_S0

R201

R201

10KR2J-3-GP

10KR2J-3-GP

1 2

D_REFCLK_1

D_REFCLK#_1

12

DY

DY

PCLKCLK0
PCLKCLK1
PCLKCLK2PCLKCLK2
PCLKCLK3PCLKCLK3PCLKCLK3

SS_SEL
ITP_EN

GEN_XTAL_OUT

GEN_REF

GEN_REF

GEN_IREF

R231475R2F-L1-GP R231475R2F-L1-GP

12

56

PCI0

3

PCI1

4

PCI2

5

PCI3

9

PCIF1/SEL100/96#

8

PCIF0/ITP_EN

55

PCI_STOP#

46

SCL

47

SDA

14

DOT96

15

DOT96#

50

XTAL_IN

49

XTAL_OUT

52

REF

39

IREF

10

VTT_PWRGD#/PD

2

VSS_PCI

6

VSS_PCI

51

VSS_REF

45

VSS_CPU

38

VSSA

13

VSS48

29

VSS_SRC

IDTCV125PAG-GP

IDTCV125PAG-GP

CPU2_ITP#/SRC7#

FSB/TEST_MODE

LVDS

LVDS#

SRC1

SRC1#

SRC2

SRC2#

SRC3

SRC3#

SRC4

SRC4#

SRC5

SRC5#

SRC6

SRC6#

CPU2_ITP/SRC7

CPU0

CPU0#

CPU1

CPU1#

CPU_STOP#

FSC/TEST_SEL

USB48/FSA

VDD_SRC
VDD_SRC

VDD_PCI
VDD_PCI

VDD_REF
VDD_CPU

VDDA

VDD48

VDD_SRC

71.00125.A0W

71.00125.A0W

U19

U19

17
18

CLK_MCH_3GPLL_1

19

CLK_MCH_3GPLL_1#

20

CLK_PCIE_ICH_1

22

CLK_PCIE_ICH_1#

23

CLK_PCIE_LAN_1

24

CLK_PCIE_LAN_1#

25

CLK_PCIE_SATA_1

26

CLK_PCIE_SATA_1#

27

CLK_PCIE_NEW_1

31

CLK_PCIE_NEW_1#

30

CLK_PCIE_MINI1_1

33

CLK_PCIE_MINI1_1#

32
36

35

CLK_CPU_BCLK_1

44

CLK_CPU_BCLK_1#

43
41
40

54
53
16
12

34
21

7
1

48
42
37
11
28

CLK_MCH_BCLK_1
CLK_MCH_BCLK_1#

CPU_SEL2
CPU_SEL1
CPU_SEL0_1

D_REFSSCLK_1
D_REFSSCLK#_1

3D3V_CLKGEN_S0

3D3V_CLKPLL_S0
3D3V_48MPWR_S0

R213

R213

1 2

33R2J-2-GP

33R2J-2-GP

R212

R212

1 2

2K2R2J-2-GP

2K2R2J-2-GP

RN18

RN18

RN19

RN19

RN20

RN20

RN21

RN21

RN22

RN22

RN29

RN29

RN28

RN28

RN26

RN26

RN27

RN27

DY

DY

4

2 3
1

2 3
1

2 3
1

2 3
1

1
2 3

1
2 3

4

4

1
23

SRN33J-5-GP-U

SRN33J-5-GP-U

4

SRN33J-5-GP-U

SRN33J-5-GP-U

4

SRN33J-5-GP-U

SRN33J-5-GP-U

4

SRN33J-5-GP-U

SRN33J-5-GP-U

4

SRN33J-5-GP-U

SRN33J-5-GP-U

CLK_PCIE_NEW

4

CLK_PCIE_NEW#

SRN33J-5-GP-U

SRN33J-5-GP-U

4

SRN33J-5-GP-U

SRN33J-5-GP-U

23
1

SRN33J-5-GP-U

SRN33J-5-GP-U

23
1

SRN33J-5-GP-U

SRN33J-5-GP-U

CPU_SEL2 4,7
CPU_SEL1 4,7
CLK48_ICH 16

CPU_SEL0 4,7

D_REFSSCLK 7
D_REFSSCLK# 7

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16

CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22

CLK_PCIE_SATA 15
CLK_PCIE_SATA# 15

CLK_PCIE_MINI1 26
CLK_PCIE_MINI1# 26

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
PM_STPCPU# 16

3D3V_S04,7,9,11,13,14,15,16,17,18,19,20,21,22,24,25,26,27,29,31,32,33,34,36,38,39,41,43
1D05V_S04,5,6,9,10,15,17,34,39,43

3D3V_S0
1D05V_S0

RN11

1D05V_S0

12

12

R431

R431

R430

R430

DY

DY

A

12

DUMMY-R2

DUMMY-R2

12

R203

R203
470R2J-2-GP

470R2J-2-GP

DY

DY

R202

R202
DUMMY-R2

DUMMY-R2

SEL1

SEL2

0
0

0
1
1 100M
1
1

SEL0

0

0

0

01200M

1
1

1

0

00333M
1

0

0

1

1

1

RN32

CLK_PCIE_MINI1
CLK_PCIE_MINI1#

SRN49D9F-GP

SRN49D9F-GP

CPU_SEL2 4,7
CPU_SEL1 4,7
CPU_SEL0 4,7

CPU

FSB

266M

X

133M

533M
X

166M

667M
X
X

400M

X

Reserved

X

http://laptop-motherboard-schematic.blogspot.com/

B

CLK_PCIE_LAN
CLK_PCIE_LAN#

SRN49D9F-GP

SRN49D9F-GP

CLK_PCIE_SATA
CLK_PCIE_SATA#

SRN49D9F-GP

SRN49D9F-GP

CLK_PCIE_ICH
CLK_PCIE_ICH#

SRN49D9F-GP

SRN49D9F-GP

RN32

2 3
1

RN15

RN15

2 3
1

RN16

RN16

2 3
1

RN14

RN14

2 3
1

4

4

4

4

C

12

R192

R192

DUMMY-R2

DUMMY-R2

1 1

470R2J-2-GP

470R2J-2-GP

R193

R193

12

DY

DY

470R2J-2-GP

470R2J-2-GP

D_REFSSCLK#
D_REFSSCLK

SRN49D9F-GP

SRN49D9F-GP

CLK_PCIE_NEW#
CLK_PCIE_NEW

SRN49D9F-GP

SRN49D9F-GP

CLK_CPU_BCLK#
CLK_CPU_BCLK

SRN49D9F-GP

SRN49D9F-GP

CLK_MCH_BCLK#
CLK_MCH_BCLK

SRN49D9F-GP

SRN49D9F-GP

D_REFCLK#
D_REFCLK

SRN49D9F-GP

SRN49D9F-GP

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

SRN49D9F-GP

SRN49D9F-GP

RN11

1
2 3

RN33

RN33

DY

DY

2 3
1

RN30

RN30

2 3
1

RN31

RN31

2 3
1

RN10

RN10

1
2 3

RN12

RN12

2 3
1

4

4

4

4

4

4

D

PCLK_SIO
CLK_ICH14
PCLK_FWH

PCLK_CB
PCLK_KBC
CLK_ICHPCI
CLK48_ICH

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet of

Date: Sheet of

Clock Generator IDTCV125PAG

Clock Generator IDTCV125PAG

Clock Generator IDTCV125PAG

EC6

EC6

1 2
1 2
1 2

1 2
1 2
1 2
1 2

DY

DY

SC10P50V3JN-GP

SC10P50V3JN-GP
EC12

EC12

DY

DY

SC10P50V3JN-GP

SC10P50V3JN-GP
EC17

EC17

DY

DY

SC10P50V3JN-GP

SC10P50V3JN-GP

EC2

EC2

DY

DY

SC10P50V3JN-GP

SC10P50V3JN-GP
EC11

EC11

DY

DY

SC10P50V3JN-GP

SC10P50V3JN-GP
EC16

EC16

DY

DY

SC10P50V3JN-GP

SC10P50V3JN-GP
EC1

EC1

DY

DY

SC10P50V3JN-GP

SC10P50V3JN-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

344Wednesday, April 12, 2006

344Wednesday, April 12, 2006

344Wednesday, April 12, 2006

E

of

EMI capacitor

A

B

C

D

E

1D05V_S03,5,6,9,10,15,17,34,39,43
3D3V_S03,7,9,11,13,14,15,16,17,18,19,20,21,22,24,25,26,27,29,31,32,33,34,36,38,39,41,43

U9A

4 4

3 3

2 2

H_A#[31..3]6

H_ADSTB#06

H_REQ#[4..0]6

H_ADSTB#16

H_A20M#15

H_FERR#15

H_IGNNE#15

H_STPCLK#15
H_INTR15
H_NMI15
H_SMI#15

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

TP38TPAD30 TP38TPAD30
TP39TPAD30 TP39TPAD30

TP58TPAD30 TP58TPAD30
TP61TPAD30 TP61TPAD30
TP65TPAD30 TP65TPAD30
TP47TPAD30 TP47TPAD30
TP53TPAD30 TP53TPAD30
TP45TPAD30 TP45TPAD30
TP51TPAD30 TP51TPAD30

TP84TPAD30 TP84TPAD30

U9A

J4

A[3]#

L4

A[4]#

M3

A[5]#

K5

A[6]#

M1

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L1

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

L2

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L5

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U2

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W3

A[27]#

W5

A[28]#

Y4

A[29]#

W2

A[30]#

Y1

A[31]#

V4

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

AA1

RSVD[01]

AA4

RSVD[02]

AB2

RSVD[03]

AA3

RSVD[04]

M4

RSVD[05]

N5

RSVD[06]

T2

RSVD[07]

V3

RSVD[08]

B2

RSVD[09]

C3

RSVD[10]

B25

RSVD[11]

BGA479-SKT6-GPU1

BGA479-SKT6-GPU1

62.10079.001

62.10079.001

ADS#
BNR#

BPRI#

ADDR GROUP 0

ADDR GROUP 0

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

ADDR GROUP 1

ADDR GROUP 1

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALSH CLK

XDP/ITP SIGNALSH CLK

PROCHOT#

THERMDA
THERMDC

THERM

THERM

THERMTRIP#

BCLK[0]
BCLK[1]

RSVD[12]

RSVD[13]
RSVD[14]
RSVD[15]
RSVD[16]
RSVD[17]

RESERVED

RESERVED

RSVD[18]
RSVD[19]
RSVD[20]

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
B1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
A25

C7

A22
A21

T22

D2
F6
D3
C1
AF1
D22
C23
C24

TP35 TPAD30TP35 TPAD30

H_RS#0
H_RS#1
H_RS#2

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK

XDP_TDI

XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

1 2

R404 0R2J-2-GPR404 0R2J-2-GP

TP78 TPAD30TP78 TPAD30

TP46 TPAD30TP46 TPAD30
TP75 TPAD30TP75 TPAD30
TP52 TPAD30TP52 TPAD30
TP33 TPAD30TP33 TPAD30
TP50 TPAD30TP50 TPAD30
TP81 TPAD30TP81 TPAD30
TP80 TPAD30TP80 TPAD30
TP83 TPAD30TP83 TPAD30

H_ADS# 6
H_BNR# 6

H_BPRI# 6

H_DEFER# 6
H_DRDY# 6
H_DBSY# 6

H_BREQ#0 6

H_INIT# 15

H_LOCK# 6

H_CPURST# 6

H_TRDY# 6

H_HIT# 6
H_HITM# 6

TP60 TPAD30TP60 TPAD30
TP48 TPAD30TP48 TPAD30
TP44 TPAD30TP44 TPAD30
TP64 TPAD30TP64 TPAD30
TP40 TPAD30TP40 TPAD30
TP43 TPAD30TP43 TPAD30
TP66 TPAD30TP66 TPAD30
TP68 TPAD30TP68 TPAD30
TP59 TPAD30TP59 TPAD30
TP67 TPAD30TP67 TPAD30
TP76 TPAD30TP76 TPAD30
TP77 TPAD30TP77 TPAD30

H_THERMDA 19
H_THERMDC 19
PM_THRMTRIP-A# 7

CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3

2nd source: 62.10053.401

1D05V_S0

1D05V_S0

12

H_IERR#

H_RS#[2..0] 6

1D05V_S0

Layout Note:

0.5" max length.

R421

R421
56R2J-4-GP

56R2J-4-GP

Place testpoint on
H_IERR# with a GND

0.1" away

H_THERMDA

H_THERMDC

R80

R80
56R2J-4-GP

56R2J-4-GP

1 2

1 2

R86 0R2J-2-GP

R86 0R2J-2-GP

DY

DY

PM_THRMTRIP-I# 34

1D05V_S0

12

R197

R197
1KR2F-3-GP

1KR2F-3-GP

12

R196

R196
2KR2F-3-GP

2KR2F-3-GP

12

C437

C437
SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

H_DSTBN#06
H_DSTBP#06
H_DINV#06

CPU_PROCHOT# 36

PM_THRMTRIP#
should connect to
ICH7 and Calistoga
without T-ing

( No stub)

H_DSTBN#16
H_DSTBP#16
H_DINV#16

12

C187

C187

CPU_SEL03,7

SC1KP16V2KX-GP

SC1KP16V2KX-GP

CPU_SEL13,7
CPU_SEL23,7

CPU_GTLREF0

R190

R190

1KR2J-1-GP

1KR2J-1-GP

1 2

R191 51R2F-2-GPR191 51R2F-2-GP

H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6

U9B

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

DY

DY

TEST1

12

TEST2

U9B

E22

D[0]#

F24

D[1]#

E26

D[2]#

H22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H26

D[12]#

F26

D[13]#

K22

D[14]#

H25

D[15]#

H23

DSTBN[0]#

G22

DSTBP[0]#

J26

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L25

D[20]#

L22

D[21]#

L23

D[22]#

M23

D[23]#

P25

D[24]#

P22

D[25]#

P23

D[26]#

T24

D[27]#

R24

D[28]#

L26

D[29]#

T25

D[30]#

N24

D[31]#

M24

DSTBN[1]#

N25

DSTBP[1]#

M26

DINV[1]#

AD26

GTLREF

C26

TEST1

D25

TEST2

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

BGA479-SKT6-GPU1

BGA479-SKT6-GPU1

62.10079.001

62.10079.001

MISC

MISC

DATA GRP 0 DATA GRP 1

DATA GRP 0 DATA GRP 1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#

DATA GRP 2

DATA GRP 2

D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

DATA GRP 3

DATA GRP 3

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23

AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20

COMP0

R26

COMP1

U26

COMP2

U1

COMP3

V1
E5

B5
D24
D6
D7
AE6

<NO_STUFF>

<NO_STUFF>

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

R194 27D4R2F-L1-GPR194 27D4R2F-L1-GP
R195 54D9R2F-L1-GPR195 54D9R2F-L1-GP
R383 27D4R2F-L1-GPR383 27D4R2F-L1-GP
R384 54D9R2F-L1-GPR384 54D9R2F-L1-GP

H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6

Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .

H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6

1 2
1 2
1 2
1 2

H_DPRSLP# 15,36
H_DPSLP# 15
H_DPWR# 6

H_PWRGD 15,34

H_CPUSLP# 6,15
PSI# 36

H_D#[63..0] 6

1D05V_S0
3D3V_S0

XDP_TDI
XDP_TMS
XDP_TDO
H_CPURST#

1 1

A

XDP_DBRESET#

XDP_TCK
XDP_TRST#

http://laptop-motherboard-schematic.blogspot.com/

R407 150R2F-1-GPR407 150R2F-1-GP

1 2

R408 39D2R3F-2-GPR408 39D2R3F-2-GP

1 2

DY

DY

R406 54D9R2F-L1-GP

R406 54D9R2F-L1-GP

1 2

DY

DY

R73 54D9R2F-L1-GP

R73 54D9R2F-L1-GP

1 2

DY

DY

R426 150R2F-1-GP

R426 150R2F-1-GP

1 2

R396 27D4R2F-L1-GPR396 27D4R2F-L1-GP

1 2

R409 680R3F-GPR409 680R3F-GP

1 2

All place within 2" to CPU

B

3D3V_S0

<Variant Name>

<Variant Name>

<Variant Name>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

C

D

Date: Sheet of

CPU (1 of 2)

CPU (1 of 2)

CPU (1 of 2)

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

444Wednesday, April 12, 2006

444Wednesday, April 12, 2006

444Wednesday, April 12, 2006

E

A

VCC_CORE_S0

U9C

U9C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

4 4

3 3

2 2

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

BGA479-SKT6-GPU1

BGA479-SKT6-GPU1

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26

AD6
AF5
AE5
AF4
AE3
AF2
AE2

AF7

AE7

VCC_CORE_S0

CPU_V6

1 2

0R0402-PAD

0R0402-PAD

12

C396

C396

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

H_VID0 36
H_VID1 36
H_VID2 36
H_VID3 36
H_VID4 36
H_VID5 36
H_VID6 36

12

R397

R397
100R2F-L1-GP-U

100R2F-L1-GP-U

R405

R405

1D05V_S0

B

Layout Note

H_VID[0..6]36

1D5V_VCCA_S0

C186

C186

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

VCC_CORE_S0

12

R410

R410
100R2F-L1-GP-U

100R2F-L1-GP-U

Layout Note:

L15

L15

1 2

BLM18PG121SN-1GP

BLM18PG121SN-1GP

12

VCCSENSE and VSSSENSE lines
should be of equal length.

Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.

68.00084.A41

68.00084.A41

C190

C190
SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

VCC_SENSE 36

VSS_SENSE 36

1D5V_S0

1D05V_S0

12

C432

C432

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

VCC_CORE_S0

12

C407

C407

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C

12

12

C394

C394

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

12

C421

C421

C418

C418

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

12

C429

C429

C430

C430

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

12

C422

C422

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C395

C395

C392

C392

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C435

C435

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

VCC_CORE_S037

1D05V_S03,4,6,9,10,15,17,34,39,43

1D5V_S09,16,17,26,41,43

12

C431

C431

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

D

VCC_CORE_S0

1D05V_S0

1D5V_S0

C197

C197
SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

U9D

U9D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

A26

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

BGA479-SKT6-GPU1

BGA479-SKT6-GPU1

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

E

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24

VCC_CORE_S0

1 1

DY

A

http://laptop-motherboard-schematic.blogspot.com/

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

B

12

12

C423

C423

C401

C401

DY

12

12

C164

C164

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C154

C154

C153

C153

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

12

C168

C168

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C182

C182

C402

C402

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C405

C405

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

DY

12

12

C436

C436

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

C

C403

C403

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C406

C406

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

DY

12

12

C400

C400

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C158

C158

C152

C152

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY

DY

12

C424

C424

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

D

<Variant Name>

<Variant Name>

<Variant Name>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU (2 of 2)

CPU (2 of 2)

CPU (2 of 2)

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

544Wednesday, April 12, 2006

544Wednesday, April 12, 2006

544Wednesday, April 12, 2006

E

A

H_XRCOMP

12

R411

R411
24D9R2F-L-GP

24D9R2F-L-GP

4 4

1D05V_S0

R412

R412
54D9R2F-L1-GP

54D9R2F-L1-GP

1 2

H_XSCOMP

1D05V_S0

12

R166

R166
221R2F-2-GP

221R2F-2-GP

H_XSWING

3 3

2 2

12

12

1D05V_S0

1 2

1D05V_S0

12

12

R163

R163
100R2F-L1-GP-U

100R2F-L1-GP-U

H_YRCOMP

R416

R416
24D9R2F-L-GP

24D9R2F-L-GP

R413

R413
54D9R2F-L1-GP

54D9R2F-L1-GP

H_YSCOMP

R414

R414
221R2F-2-GP

221R2F-2-GP

H_YSWING

R415

R415
100R2F-L1-GP-U

100R2F-L1-GP-U

1 2

1 2

H_D#[63..0]4

C156

C156
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C412

C412
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

B

U50A

W11

AB7
AA9

AB8
AA4

AA7
AA2
AA6

AA10

AA1
AB4

AC9
AB11
AC11

AB3

AC2

AD1

AD9

AC1

AD7

AC6

AB5
AD10

AD4

AC8

AG2

AG1

K11
T10

U11
T11

Y10

F1

J1

H1

J6
H3
K2
G1
G2
K9
K1
K7

J8
H4

J3
G4

T3
U7
U9

W9

T1
T8
T4

W7

U5
T9

W6

T5

W4
W3

Y3
Y7

W5

W2

Y8

E1
E2
E4

Y1
U1

W1

U50A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_XRCOMP
H_XSCOMP
H_XSWING

H_YRCOMP
H_YSCOMP
H_YSWING

H_CLKIN
H_CLKIN#

CALISTOGA

CALISTOGA

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOMP
H_XSCOMP
H_XSWING

H_YRCOMP
H_YSCOMP
H_YSWING

CLK_MCH_BCLK3

CLK_MCH_BCLK#3

C

H_ADSTB#_0
H_ADSTB#_1

HOST

HOST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_ADS#

H_VREF_0

H_BNR#

H_BPRI#

H_BREQ#0

H_CPURST#

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#

H_VREF_1

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_SLPCPU#

H_TRDY#

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13

J7
W8
U3
AB10

K4
T7
Y5
AC4

K3
T6
AA5
AC5

D3
D4
B3

D8
G8
B8
F8
A8

B4
E6
D6

E3
E7

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_VREF

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

R167

R167

1 2

0R0402-PAD

0R0402-PAD

D

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4

H_BNR# 4

H_BPRI# 4

H_BREQ#0 4

H_CPURST# 4

H_DBSY# 4

H_DEFER# 4
H_DPWR# 4

H_DRDY# 4

H_HIT# 4
H_HITM# 4

H_LOCK# 4

H_CPUSLP# 4,15
H_TRDY# 4

H_A#[31..3] 4

C132

C132
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1 2

1D05V_S0

12

R145

R145
100R2F-L1-GP-U

100R2F-L1-GP-U

12

R143

R143
200R2F-L-GP

200R2F-L-GP

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

E

1D05V_S03,4,5,9,10,15,17,34,39,43

1D05V_S0

1 1

Place them near to the chip ( < 0.5")

A

http://laptop-motherboard-schematic.blogspot.com/

B

C

D

<Variant Name>

<Variant Name>

<Variant Name>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet

GMCH (1 of 5)

GMCH (1 of 5)

GMCH (1 of 5)

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

E

of

644Wednesday, April 12, 2006

644Wednesday, April 12, 2006

644Wednesday, April 12, 2006

A

M_CLK_DDR011
M_CLK_DDR111
M_CLK_DDR211
M_CLK_DDR311

M_CLK_DDR#011
M_CLK_DDR#111
M_CLK_DDR#211
M_CLK_DDR#311

12

4

M_RCOMPN

M_RCOMPP

M_CKE011,12
M_CKE111,12
M_CKE211,12
M_CKE311,12

M_CS0#11,12
M_CS1#11,12
M_CS2#11,12
M_CS3#11,12

M_OCDCOMP0
M_OCDCOMP1

R146

R146
40D2R2F-GP

40D2R2F-GP

DY

DY

PM_EXTTS#0

PM_EXTTS#1

A

M_ODT011,12
M_ODT111,12
M_ODT211,12
M_ODT311,12

CLK_MCH_3GPLL#3
CLK_MCH_3GPLL3

D_REFSSCLK#3
D_REFSSCLK3

D_REFCLK#3
D_REFCLK3

TV_DACA

TV_DACB

TV_DACC

GMCH_BLUE

GMCH_GREEN

GMCH_RED

M_RCOMPN
M_RCOMPP

DMI_TXP3

4 4

12

R91

R91
40D2R2F-GP

40D2R2F-GP

DY

DY

DDR_VREF_S3

C212

C212

1
2 3

12

R153

R153
80D6R2F-L-GP

80D6R2F-L-GP

12

R147

R147
80D6R2F-L-GP

80D6R2F-L-GP

12

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DMI_TXN[3..0]16

DMI_TXP[3..0]16

DMI_RXN[3..0]16

DMI_RXP[3..0]16

RN8

RN8

SRN10KJ-5-GP

SRN10KJ-5-GP

12

C211

C211

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3 3

3D3V_S0

2 2

1D8V_S3

1 1

AY35

AW7

AW40
AW35

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20

AF10

BA13
BA12
AY20
AU21

AK41

AF33

AG33

DMI_TXN0

AE35

DMI_TXN1

AF39

DMI_TXN2

AG35

DMI_TXN3

AH39

DMI_TXP0

AC35

DMI_TXP1

AE39

DMI_TXP2

AF35

AG39

DMI_RXN0

AE37

DMI_RXN1

AF41

DMI_RXN2

AG37

DMI_RXN3

AH41

DMI_RXP0

AC37

DMI_RXP1

AE41

DMI_RXP2

AF37

DMI_RXP3

AG41

R386

R386

1 2

1 2

R381 150R2F-1-GPR381 150R2F-1-GP

1 2

R379 150R2F-1-GPR379 150R2F-1-GP

1 2

R84 150R2F-1-GPR84 150R2F-1-GP

1 2

R90 150R2F-1-GPR90 150R2F-1-GP

1 2

R70 150R2F-1-GPR70 150R2F-1-GP

SM_CK_0

AR1

SM_CK_1
SM_CK_2
SM_CK_3

SM_CK#_0

AT1

SM_CK#_1

AY7

SM_CK#_2
SM_CK#_3

SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_OCDCOMP_0
SM_OCDCOMP_1

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

AV9

SM_RCOMP#

AT9

SM_RCOMP

AK1

SM_VREF_0
SM_VREF_1

G_CLKIN#
G_CLKIN

A27

D_REFCLKIN#

A26

D_REFCLKIN

C40

D_REFSSCLKIN#

D41

D_REFSSCLKIN

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

CALISTOGA

CALISTOGA

75R2F-2-GP

75R2F-2-GP

http://laptop-motherboard-schematic.blogspot.com/

B

CFGRSVD

CFGRSVD

DDR MUXINGCLKDMI

DDR MUXINGCLKDMI

B

PM

PM

PM_THRMTRIP#

MISC

MISC

SDVO_CTRLCLK

SDVO_CTRLDATA

NC

NC

3D3V_S0

RSVD_0
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8

RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1

PWROK

RSTIN#

LT_RESET#

NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

R61

R61

1 2

DUMMY-R2

DUMMY-R2
R58

R58

1 2

DUMMY-R2

DUMMY-R2
R60

R60

1 2

DUMMY-R2

DUMMY-R2
R117

R117

1 2

DUMMY-R2

DUMMY-R2
R150

R150

1 2

DUMMY-R2

DUMMY-R2
R151

R151

1 2

DUMMY-R2

DUMMY-R2
R127

R127

1 2

DUMMY-R2

DUMMY-R2
R112

R112

1 2

DUMMY-R2

DUMMY-R2
R140

R140

1 2

DUMMY-R2

DUMMY-R2
R116

R116

1 2

DUMMY-R2

DUMMY-R2
R139

R139

1 2

DUMMY-R2

DUMMY-R2

R148

R148

1 2

2K2R2J-2-GP

2K2R2J-2-GP
R141

R141

1 2

DUMMY-R2

DUMMY-R2
R156

R156

1 2

DUMMY-R2

DUMMY-R2
R142

R142

1 2

DUMMY-R2

DUMMY-R2
R152

R152

1 2

DUMMY-R2

DUMMY-R2
R105

R105

1 2

DUMMY-R2

DUMMY-R2
R154

R154

1 2

DUMMY-R2

DUMMY-R2

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

DY

DY

U50B

U50B

H32
T32
R32
F3
F7
AG11
AF11
H7
J19
K30
J29
A41
A35
A34
D28
D27

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

G28

PM_EXTTS#0

F25

PM_EXTTS#1

H26
G6

GMCH_PWROK

AH33
AH34

H28
H27
K28

D1
C41
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3

CLKREQ_MCH

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

R178

R178

1 2

100R2J-2-GP

100R2J-2-GP

GMCH_DDCCLK14
GMCH_DDCDATA14

CFG18

CFG19
CFG20
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10

CFG11

CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

TP11 TPAD30TP11 TPAD30
TP9 TPAD30TP9 TPAD30
TP37 TPAD30TP37 TPAD30
TP34 TPAD30TP34 TPAD30
TP31 TPAD30TP31 TPAD30
TP32 TPAD30TP32 TPAD30
TP36 TPAD30TP36 TPAD30
TP23 TPAD30TP23 TPAD30
TP8 TPAD30TP8 TPAD30
TP12 TPAD30TP12 TPAD30
TP21 TPAD30TP21 TPAD30
TP24 TPAD30TP24 TPAD30
TP25 TPAD30TP25 TPAD30
TP27 TPAD30TP27 TPAD30
TP26 TPAD30TP26 TPAD30

CPU_SEL0 3,4
CPU_SEL1 3,4
CPU_SEL2 3,4

PM_BMBUSY# 16

PM_THRMTRIP-A# 4

MCH_ICH_SYNC# 16

SRN10KJ-5-GP

SRN10KJ-5-GP

When High 1K Ohm

CFG6:
0=Moby Dick ,1=Calistoga (default)

When Low choice
lower than 3.5K
Ohm

GMCH_PWROK

C

TP7 TPAD30TP7 TPAD30

for calistoga configuration

L_BKLTEN29

LDDC_CLK13
LDDC_DATA13

GMCH_LCDVDD_ON13

PLT_RST1# 16,20,26,29

3D3V_S0

4

RN6

RN6

DY

DY

1

2 3

GMCH_HSY14
GMCH_VSY14

TP22TPAD30 TP22TPAD30
TP6TPAD30 TP6TPAD30

TP30TPAD30 TP30TPAD30

GMCH_GREEN14

R67

R67
255R2F-L-GP

255R2F-L-GP

When PM replace to GM

R179 0R2J-2-GP

R179 0R2J-2-GP

DY

DY

1 2
1 2

R180 0R2J-2-GPR180 0R2J-2-GP

C

LDDC_CLK
LDDC_DATA

GMCH_LCDVDD_ON

LA_CLK#13
LA_CLK13
LB_CLK#13
LB_CLK13

LA_DATA#_013
LA_DATA#_113
LA_DATA#_213

LA_DATA_013
LA_DATA_113
LA_DATA_213

LB_DATA#_013
LB_DATA#_113
LB_DATA#_213

LB_DATA_013
LB_DATA_113
LB_DATA_213

TV_DACB14
TV_DACC14

GMCH_BLUE14

GMCH_RED14

12

L_BKLTEN

LCTLA_CLK
LCTLB_DATA

LIBG

L_LVBG

TV_DACA

R75

R75

1 2

4K99R2F-L-GP

4K99R2F-L-GP

GMCH_DDCCLK

GMCH_DDCDATAGMCH_DDCDATA

VGATE_PWRGD 16,36
PWROK 16,19

D32
H30

H29
G26
G25
B38
C35
F32
C33
C32

A33
A32
E27
E26

C37
B35
A37

B37
B34
A36

G30
D30
F29

F30
D29
F28

A16
C18
A19

B16
B18
B19

E23
D23
C22
B22
A21
B21

C26
C25
G23

H23

J30

J20

J22

U50C

U50C

CALISTOGA

CALISTOGA

L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CLKCTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL

LA_CLK#
LA_CLK
LB_CLK#
LB_CLK

LA_DATA#_0
LA_DATA#_1
LA_DATA#_2

LA_DATA_0
LA_DATA_1
LA_DATA_2

LB_DATA#_0
LB_DATA#_1
LB_DATA#_2

LB_DATA_0
LB_DATA_1
LB_DATA_2

TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC

SEL2

0
0

0
1
1 100M
1
1

D

LVDS

LVDS

TV

TV

VGA

VGA

L_BKLTEN
GMCH_LCDVDD_ON

LIBG

SEL1

SEL0

0

0

0

01200M

1
1

1

0

00333M
1

0

0

1

1

1

D

3D3V_S03,4,9,11,13,14,15,16,17,18,19,20,21,22,24,25,26,27,29,31,32,33,34,36,38,39,41,43

1D8V_S310,11,12,39,41,43
1D5V_PCIE_S09
DDR_VREF_S311,41

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8

EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15

EXP_A_RXP_0

EXP_A_RXP_1

EXP_A_RXP_2

EXP_A_RXP_3

EXP_A_RXP_4

EXP_A_RXP_5

EXP_A_RXP_6

EXP_A_RXP_7

EXP_A_RXP_8

EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15

EXP_A_TXN_0

EXP_A_TXN_1

EXP_A_TXN_2

EXP_A_TXN_3

EXP_A_TXN_4

EXP_A_TXN_5

EXP_A_TXN_6

EXP_A_TXN_7

EXP_A_TXN_8

EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15

EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8

EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15

RN4

RN4

1
2 3

SRN100KJ-6-GP

SRN100KJ-6-GP

1 2

R186 1K5R2F-2-GPR186 1K5R2F-2-GP

<Variant Name>

<Variant Name>

<Variant Name>

CPU

266M
133M

Title

Title

Title

166M

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

400M

A3

A3

A3

Reserved

Date: Sheet of

Date: Sheet of

Date: Sheet

D40
D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

4

LCTLA_CLK
LCTLB_DATA

3D3V_S0

4

1

2 3

GMCH (2 of 5)

GMCH (2 of 5)

GMCH (2 of 5)

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

E

1D8V_S3
1D5V_PCIE_S0
DDR_VREF_S3

3D3V_S0

RN5

RN5
SRN10KJ-5-GP

SRN10KJ-5-GP

LDDC_CLK
LDDC_DATA

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

E

R57

R57

24D9R2F-L-GP

24D9R2F-L-GP

4

RN7

RN7
SRN10KJ-5-GP

SRN10KJ-5-GP

1

2 3

744Wednesday, April 12, 2006

744Wednesday, April 12, 2006

744Wednesday, April 12, 2006

1D5V_PCIE_S0

12

of

A

4 4

U50D

M_A_DQ[63..0]11

3 3

2 2

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AJ35

AJ34
AM31
AM33

AJ36

AK35

AJ32
AH31
AN35

AP33
AR31

AP31
AN38
AM36
AM34
AN33

AK26

AL27
AM26
AN24

AK28

AL28
AM24

AP26

AP23

AL22

AP21
AN20

AL23

AP24

AP20

AT21
AR12
AR14

AP13

AP12

AT13

AT12

AL14

AL12

AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2

AW2

AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

U50D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

CALISTOGA

CALISTOGA

B

M_B_DQ[63..0]11

AU12

SA_BS_0

AV14

SA_BS_1

BA20

SA_BS_2

AY13

SA_CAS#

AJ33

SA_DM_0

AM35

SA_DM_1

AL26

SA_DM_2

AN22

SA_DM_3

AM14

SA_DM_4

AL9

SA_DM_5

AR3

SA_DM_6

AH4

SA_DM_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9

SA_RAS#

SA_WE#

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

AW14
AK23
AK24
AY14

SA_RCVENIN#
SA_RCVENOUT#

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_10

SA_MA_11

SA_MA_12

SA_MA_13

SA_RCVENIN#

SA_RCVENOUT#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

M_A_CAS# 11,12

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4

M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0
M_A_A1
M_A_A2
M_A_A3M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

Place Test PAD Near to Chip
as could as possible

M_A_BS#0 11,12
M_A_BS#1 11,12
M_A_BS#2 11,12

M_A_DQS[7..0] 11

M_A_DQS#[7..0] 11

M_A_RAS# 11,12

TP16 TPAD30TP16 TPAD30
TP13 TPAD30TP13 TPAD30

M_A_WE# 11,12

C

M_A_DM[7..0] 11

M_A_A[13..0] 11,12

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AK39

AJ37
AP39
AR41

AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40

AW38

AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31

AW31

AV29

AW29

AM19

AL19
AP14
AN14
AN17
AM16
AP15

AL15

AJ11
AH10

AN10
AK13
AH11
AK10

BA10

AW10

BA4

AW4
AY10

AY9

AW5

AY5
AV4
AR5
AK4
AK3
AT4
AK5

AJ9

AJ8

AJ5
AJ3

U50E

U50E

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

CALISTOGA

CALISTOGA

D

AT24

SB_BS_0

AV23

SB_BS_1

AY28

SB_BS_2

AR24

SB_CAS#

AK36

SB_DM_0

AR38

SB_DM_1

AT36

SB_DM_2

BA31

SB_DM_3

AL17

SB_DM_4

AH8

SB_DM_5

BA5

SB_DM_6

AN4

SB_DM_7

AM39

SB_DQS_0

AT39

SB_DQS_1

AU35

SB_DQS_2

AR29

SB_DQS_3

AR16

SB_DQS_4

AR10

SB_DQS_5

AR7

SB_DQS_6

AN5

SB_DQS_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_WE#

AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

AU23
AK16
AK18
AR27

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_RCVENIN#

SB_RCVENOUT#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

M_B_CAS# 11,12

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7M_A_DQS5
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

SB_RCVENIN#
SB_RCVENOUT#

Place Test PAD Near to Chip
ascould as possible

E

M_B_BS#0 11,12
M_B_BS#1 11,12
M_B_BS#2 11,12

M_B_RAS# 11,12

M_B_WE# 11,12

M_B_DM[7..0] 11

M_B_DQS[7..0] 11

M_B_DQS#[7..0] 11

M_B_A[13..0] 11,12

TP29 TPAD30TP29 TPAD30
TP28 TPAD30TP28 TPAD30

1 1

A

http://laptop-motherboard-schematic.blogspot.com/

B

C

D

<Variant Name>

<Variant Name>

<Variant Name>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet

GMCH (3 of 5)

GMCH (3 of 5)

GMCH (3 of 5)

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

E

of

844Wednesday, April 12, 2006

844Wednesday, April 12, 2006

844Wednesday, April 12, 2006

A

B

C

D

E

2D5V_S0

C71

C71

2D5V_3GBG_S0

V_TVBG

V_DACA
V_DACB
V_DACC

1D5V_TVDAC_S0

12

C266

C266

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C130

C130

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C

12

2D5V_S0

C219

C219
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5V_DPLLA
1D5V_DPLLB
1D5V_HPLL_S0

1D5V_MPLL_S0

12

12

C110

C110

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5V_S0

12

L22

L22

R248

R248
10R2J-2-GP

10R2J-2-GP

L7

L7

1 2

68.00230.041

68.00230.041

2D5V_S0

12

C239

C239
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C69

C69
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C416

C416
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

C417

C417
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

3D3V_TVDAC

12

1D5V_DPLLA

12

C246

C246
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5V_DPLLB

12

C70

C70
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5V_HPLL_S0

12

C410

C410

1D5V_MPLL_S0

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C411

C411

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

2D5V_CRTDAC VCCA_CRTDAC

R372

R372

12

0R0805-PAD

0R0805-PAD

12

C287

C287

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

R100

R100

12

0R0603-PAD

0R0603-PAD

R66

R66

12

0R0603-PAD

0R0603-PAD

R63

R63

12

0R0603-PAD

0R0603-PAD

R74

R74

0R0603-PAD

0R0603-PAD

12

C82

C82
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

1D5V_S0 1D5V_PCIE_S0

R182

R182

12

0R0805-PAD

0R0805-PAD

1D5V_S0

R176 0R0603-PADR176 0R0603-PAD

V_DACA
V_DACB

12

C88

C88

V_DACCV_DACC

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

V_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBGV_TVBG

12

C104

C104

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

http://laptop-motherboard-schematic.blogspot.com/

B

1D5V_3GPLL_S0

12

C206

C206

3D3V_S0

R355 0R0603-PADR355 0R0603-PAD

12

C105

C105

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C81

C81

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C72

C72

12

C210C210

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

12

C237

C237

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

1D5V_S0

0R0603-PAD

0R0603-PAD

1D5V_S0

R62

R62

1 2

0R0805-PAD

0R0805-PAD

12

C73

C73

12

2D5V_S0

R375

R375

12

C117

C117

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C74

C74

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

12

C222

C222
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5V_S0

12

C245

C245

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D5V_QTVDAC_S0

12

C326

C326

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

12

C76

C76

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

VCCA_CRTDAC

0R0603-PAD

0R0603-PAD
R370

R370

1D5V_AUX

2D5V_3GBG_S0

R184 0R0603-PADR184 0R0603-PAD

12

1D5V_S0

D17

D17

BAT54-4-GP

BAT54-4-GP

D15

D15

1

2

C214C214

3

3

BAT54-4-GP

BAT54-4-GP

L21

L21

1 2

HCB1608KF121T30-GP

HCB1608KF121T30-GP

68.00230.041

68.00230.041

L6

L6

1 2

HCB1608KF121T30-GP

HCB1608KF121T30-GP

68.00230.041

68.00230.041

L23

L23

1 2

HCB1608KF121T30-GP

HCB1608KF121T30-GP

68.00230.041

68.00230.041

L24

L24

1 2

HCB1608KF121T30-GP

HCB1608KF121T30-GP

68.00230.041

68.00230.041

12

R255

R255
10R2J-2-GP

10R2J-2-GP

1 2

HCB1608KF121T30-GP

HCB1608KF121T30-GP

68.00230.041

68.00230.041

12

HCB1608KF121T30-GP

HCB1608KF121T30-GP

4 4

3 3

1D5V_S0

1

2 2

2D5V_S0

1 1

2

1D5V_S0

3D3V_S0

Divide by Trace (Layout Rule approve)

A

H22
C30

B30
A30

AJ41

AB41

Y41
V41
R41
N41

AC33

G41
H41

F21
E21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
A23

B23
B25

H19

AK31

AF31
AE31
AC31

AL30
AK30

AJ30
AH30
AG30

AF30
AE30
AD30
AC30
AG29

AF29
AE29
AD29
AC29
AG28

AF28
AE28
AH22

AJ21
AH21

AJ20
AH20
AH19

P19
P16

AH15

P15
AH14
AG14

AF14

AE14

Y14

AF13

AE13

AF12
AE12
AD12

L41

U50H

U50H

VCCSYNC
VCC_TXLVDS0

VCC_TXLVDS1
VCC_TXLVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC
VCC_HV0

VCC_HV1
VCC_HV2

VCCD_QTVDAC
VCCAUX0

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

POWER

POWER

CALISTOGA

CALISTOGA

AC14

VTT_0

AB14

VTT_1

W14

VTT_2

V14

VTT_3

T14

VTT_4

R14

VTT_5

P14

VTT_6

N14

VTT_7

M14

VTT_8

L14

VTT_9

AD13

VTT_10

AC13

VTT_11

AB13

VTT_12

AA13

VTT_13

Y13

VTT_14

W13

VTT_15

V13

VTT_16

U13

VTT_17

T13

VTT_18

R13

VTT_19

N13

VTT_20

M13

VTT_21

L13

VTT_22

AB12

VTT_23

AA12

VTT_24

Y12

VTT_25

W12

VTT_26

V12

VTT_27

U12

VTT_28

T12

VTT_29

R12

VTT_30

P12

VTT_31

N12

VTT_32

M12

VTT_33

L12

VTT_34

R11

VTT_35

P11

VTT_36

N11

VTT_37

M11

VTT_38

R10

VTT_39

P10

VTT_40

N10

VTT_41

M10

VTT_42

P9

VTT_43

N9

VTT_44

M9

VTT_45

R8

VTT_46

P8

VTT_47

N8

VTT_48

M8

VTT_49

P7

VTT_50

N7

VTT_51

M7

VTT_52

R6

VTT_53

P6

VTT_54

M6

VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76

D

VCCP_GMCH_CAP3

A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2

VCCP_GMCH_CAP2

D2

VCCP_GMCH_CAP1

AB1
R1
P1
N1
M1

SCD47U10V3ZY-GP

SCD47U10V3ZY-GP

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet of

12

C413

C413

C90C90

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

1D5V_PCIE_S07

12

C134

C134
SCD22U16V3ZY-GP

SCD22U16V3ZY-GP

12

12

C159

C159
SCD47U10V3ZY-GP

SCD47U10V3ZY-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GMCH (4 of 5)

GMCH (4 of 5)

GMCH (4 of 5)

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

1D05V_S0

12

C111

C111

1D05V_S03,4,5,6,10,15,17,34,39,43
2D5V_S041
1D5V_S05,16,17,26,41,43
3D3V_S03,4,7,11,13,14,15,16,17,18,19,20,21,22,24,25,26,27,29,31,32,33,34,36,38,39,41,43
1D8V_S37,10,11,12,39,41,43

1D5V_AUX10

E

C414

C414

SC4D7U10V5ZY-3GP

SC4D7U10V5ZY-3GP

1D5V_PCIE_S0

944Wednesday, April 12, 2006

944Wednesday, April 12, 2006

944Wednesday, April 12, 2006

1D05V_S0

2D5V_S0
1D5V_S0
3D3V_S0
1D8V_S3

1D5V_AUX

A

U50G

1D05V_S0

4 4

3 3

2 2

1 1

AA33

W33

N33

AA32

Y32

W32

V32
P32
N32

M32

AA31

W31

V31
T31
R31
P31
N31

M31

AA30

Y30

W30

V30
U30
T30
R30
P30
N30

M30

AA29

Y29

W29

V29
U29
R29
P29

M29

AB28
AA28

Y28
V28
U28
T28
R28
P28
N28

M28

P27
N27

M27

P26
N26

N25

M25

P24
N24

M24
AB23
AA23

Y23
P23
N23

M23
AC22

AB22

Y22

W22

P22
N22

M22
AC21

AA21

W21

N21

M21
AC20

AB20

Y20

W20

P20
N20

M20
AB19

AA19

Y19
N19

M19

N18

M18

P17
N17

M17

N16

M16

P33
L33

J33

L32
J32

L30

L29

L28

L27

L26

L25

L23

L22

L21

L20

L19

L18

L16

U50G

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110

A

VCC

VCC

VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8

VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99

VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

12

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

ST220U2VBM-3GP

ST220U2VBM-3GP

CALISTOGA

CALISTOGA

http://laptop-motherboard-schematic.blogspot.com/

1D05V_S0

C415

C415

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

12

TC2

TC2

B

U50F

U50F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21
U21

R21

AD20

V20
U20

R20

AD19

V19
U19

AD18
AC18
AB18
AA18

W18

V18
U18

12

T21

T20

T19

Y18

T18

C77

C77

VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C78

C78

NCTF

NCTF

CALISTOGA

CALISTOGA

12

C80C80

Place these Caps close VCC_0 ~ VCC_110

1D8V_S3

C399

C399

DY

DY

12

C397

C397

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C390

C390

12

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

B

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

12

C89

C89

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C135

C135

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

12

C112

C112

12

C241

C241

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C

1D5V_AUX

1D05V_S0

12

12

C83

C83

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C213

C213

DY

DY

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C

AC41
AA41

W41

T41
P41
M41

J41

F41

AV40
AP40
AN40
AK40

AJ40
AH40
AG40

AF40
AE40

B40

AY39

AW39

AV39
AR39
AN39

AJ39
AC39
AB39
AA39

Y39

W39

V39

T39
R39
P39
N39
M39

L39

J39
H39
G39

F39
D39

AT38
AM38
AH38
AG38

AF38

AE38

C38

AK37
AH37
AB37
AA37

Y37

W37

V37

T37
R37
P37
N37
M37

L37

J37
H37
G37

F37
D37

AY36

AW36

AN36
AH36
AG36

AF36
AE36
AC36

C36

B36
BA35
AV35
AR35
AH35
AB35
AA35

Y35

W35

V35

T35
R35
P35
N35

TC9

TC9

M35

ST220U2VBM-3GP

ST220U2VBM-3GP

L35

J35
H35
G35

F35
D35

AN34

12

C84

C84

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U50I

U50I

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96

CALISTOGA

CALISTOGA

12

C338

C338

VSS

VSS

12

C379

C379

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C290

C290

VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179

D

U50J

U50J

VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272

1D05V_S0

VSS

VSS

CALISTOGA

CALISTOGA

GMCH (5 of 5)

GMCH (5 of 5)

GMCH (5 of 5)

Y41/Y40

Y41/Y40

Y41/Y40

AK34
AG34
AF34
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23

D

1D05V_S03,4,5,6,9,15,17,34,39,43

AT23
AN23
AM23
AH23
AC23

W23

K23

J23
F23
C23

AA22

K22
G22
F22
E22
D22
A22

BA21

AV21
AR21
AN21

AL21

AB21

Y21
P21
K21

J21
H21
C21

AW20
AR20
AM20

AA20

K20
B20
A20

AN19
AC19

W19

K19
G19
C19

AH18

P18
H18
D18
A18

AY17

AR17

AP17

AM17

AK17
AV16

AN16

AL16

J16
F16
C16

AN15
AM15

AK15

N15

M15

L15
B15
A15

BA14
AT14
AK14

AD14

AA14

U14

K14

H14

E14

AV13
AR13
AN13
AM13

AL13
AG13

P13
F13

D13

B13

AY12
AC12

K12

H12

E12

AD11

AA11

Y11

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet of

E

1D8V_S37,11,12,39,41,43
1D5V_AUX9

J11

VSS_273

D11

VSS_274

B11

VSS_275

AV10

VSS_276

AP10

VSS_277

AL10

VSS_278

AJ10

VSS_279

AG10

VSS_280

AC10

VSS_281

W10

VSS_282

U10

VSS_283

BA9

VSS_284

AW9

VSS_285

AR9

VSS_286

AH9

VSS_287

AB9

VSS_288

Y9

VSS_289

R9

VSS_290

G9

VSS_291

E9

VSS_292

A9

VSS_293

AG8

VSS_294

AD8

VSS_295

AA8

VSS_296

U8

VSS_297

K8

VSS_298

C8

VSS_299

BA7

VSS_300

AV7

VSS_301

AP7

VSS_302

AL7

VSS_303

AJ7

VSS_304

AH7

VSS_305

AF7

VSS_306

AC7

VSS_307

R7

VSS_308

G7

VSS_309

D7

VSS_310

AG6

VSS_311

AD6

VSS_312

AB6

VSS_313

Y6

VSS_314

U6

VSS_315

N6

VSS_316

K6

VSS_317

H6

VSS_318

B6

VSS_319

AV5

VSS_320

AF5

VSS_321

AD5

VSS_322

AY4

VSS_323

AR4

VSS_324

AP4

VSS_325

AL4

VSS_326

AJ4

VSS_327

Y4

VSS_328

U4

VSS_329

R4

VSS_330

J4

VSS_331

F4

VSS_332

C4

VSS_333

AY3

VSS_334

AW3

VSS_335

AV3

VSS_336

AL3

VSS_337

AH3

VSS_338

AG3

VSS_339

AF3

VSS_340

AD3

VSS_341

AC3

VSS_342

AA3

VSS_343

G3

VSS_344

AT2

VSS_345

AR2

VSS_346

AP2

VSS_347

AK2

VSS_348

AJ2

VSS_349

AD2

VSS_350

AB2

VSS_351

Y2

VSS_352

U2

VSS_353

T2

VSS_354

N2

VSS_355

J2

VSS_356

H2

VSS_357

F2

VSS_358

C2

VSS_359

AL1

VSS_360

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

10 44Wednesday, April 12, 2006

10 44Wednesday, April 12, 2006

10 44Wednesday, April 12, 2006

E

1D8V_S3

1D5V_AUX

-1

-1

-1

A

DM1

DM1

M_B_A[13..0]8,12

4 4

M_B_BS#28,12
M_B_BS#08,12

M_B_BS#18,12

M_B_DQ[63..0]8

3 3

2 2

M_B_DQS#[7..0]8

M_B_DQS[7..0]8

1 1

K3

TPAD79K3TPAD79

MEM_VREF_S3

DY

DY

1

12

C579

C579

SC2D2U10V3ZY-1GP

SC2D2U10V3ZY-1GP

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_ODT27,12
M_ODT37,12

12

BC8

BC8

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

A

MH1

102
101
100

99
98
97
94
92
93
91

105

90
89

116

86
84
85

107
106

5

7
17
19

4

6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76

123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

11
29
49
68

129
146
167
186

13
31
51
70

131
148
169
188

114
119

1

2

202

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

BA0
BA1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

OTD0
OTD1

VREF
VSS

GND
MH1

DDR2-200P-20-GP-U

DDR2-200P-20-GP-U

RAS#

WE#

CAS#
CS0#

CS1#
CKE0

CKE1

CK0

CK0#

CK1

CK1#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SDA
SCL

VDDSPD

SA0
SA1

NC#50
NC#69
NC#83

NC#120

NC#163/TEST

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NORMAL TYPE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
GND
MH2

B

108
109
113

110
115

79
80

30
32

164
166

M_B_DM0

10

M_B_DM1

26

M_B_DM2

52

M_B_DM3

67

M_B_DM4

130

M_B_DM5

147

M_B_DM6

170

M_B_DM7

185

195
197

199
198

200
50

69
83
120
163

81
82
87
88
95
96
103
104
111
112
117
118

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

201
MH2

http://laptop-motherboard-schematic.blogspot.com/

12

BC6

BC6

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1

B

1D8V_S3

M_B_RAS# 8,12

M_B_WE# 8,12

M_B_CAS# 8,12

M_CS2# 7,12
M_CS3# 7,12

M_CKE2 7,12
M_CKE3 7,12

M_CLK_DDR3 7
M_CLK_DDR#3 7

M_CLK_DDR2 7
M_CLK_DDR#2 7

M_B_DM[7..0] 8

1

1

SMBD_ICH 3,18
SMBC_ICH 3,18

R177

R177

1 2

10KR2J-3-GP

10KR2J-3-GP

1

K4TPAD79 K4TPAD79

K2TPAD79 K2TPAD79

Place near DM1

M_CLK_DDR3

12

C202

C202

DY

DY

SC10P50V2JN-4GP

SC10P50V2JN-4GP

M_CLK_DDR#3
M_CLK_DDR2

12

DY

DY

C408

C408
SC10P50V2JN-4GP

SC10P50V2JN-4GP

M_CLK_DDR#2

DDR_VREF_S3 MEM_VREF_S3

1 2

0R2J-2-GP

0R2J-2-GP

K6TPAD79 K6TPAD79

R164

R164

K5TPAD79 K5TPAD79

3D3V_S0

M_A_A[13..0]8,12

M_A_BS#28,12
M_A_BS#08,12

M_A_BS#18,12

M_A_DQ[63..0]8

M_A_DQS#[7..0]8

M_A_DQS[7..0]8

M_ODT07,12
M_ODT17,12

MEM_VREF_S3

DY

DY

C

DM2

DM2

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

12

12

C178

C178

BC9

BC9
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SC2D2U10V3ZY-1GP

SC2D2U10V3ZY-1GP

C

MH1

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16/BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

11

DQS0#

29

DQS1#

49

DQS2#

68

DQS3#

129

DQS4#

146

DQS5#

167

DQS6#

186

DQS7#

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

OTD0

119

OTD1

1

VREF

2

VSS

202

GND
MH1

DDR2-200P-21-GP-U

DDR2-200P-21-GP-U

D

3D3V_S03,4,7,9,13,14,15,16,17,18,19,20,21,22,24,25,26,27,29,31,32,33,34,36,38,39,41,43

108

RAS#

109

WE#

113

CAS#

110

CS0#

115

CS1#

79

CKE0

80

CKE1

30

CK0

32

CK0#

164

CK1

166

CK1#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SDA
SCL

VDDSPD

SA0
SA1

NC#50
NC#69
NC#83

NC#120

NC#163/TEST

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NORMAL TYPE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
GND
MH2

D

M_A_DM0

10

M_A_DM1

26

M_A_DM2

52

M_A_DM3

67

M_A_DM4

130

M_A_DM5

147

M_A_DM6

170

M_A_DM7

185

SMBD_ICH

195

SMBC_ICH

197
199
198

200
50

69
83
120
163

81
82
87
88
95
96
103
104
111
112
117
118

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184

<Variant Name>

<Variant Name>

<Variant Name>

187
190
193
196

201

Title

Title

Title

MH2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Custom

Custom

Custom

1D8V_S3

M_CLK_DDR0 7
M_CLK_DDR#0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

3D3V_S0

M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12

M_CS0# 7,12
M_CS1# 7,12

M_CKE0 7,12
M_CKE1 7,12

M_A_DM[7..0] 8

BC7

BC7

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

E

1D8V_S37,10,12,39,41,43

DDR_VREF_S37,41

3D3V_S0

12

Place near DM2

M_CLK_DDR0

12

DY

DY

C204 SC10P50V2JN-4GP

C204 SC10P50V2JN-4GP

M_CLK_DDR#0

M_CLK_DDR1

12

DY

DY

C409 SC10P50V2JN-4GP

C409 SC10P50V2JN-4GP

M_CLK_DDR#1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DDR2 Socket

DDR2 Socket

DDR2 Socket

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

E

1D8V_S3

DDR_VREF_S3

of

of

of

11 44Wednesday, April 12, 2006

11 44Wednesday, April 12, 2006

11 44Wednesday, April 12, 2006

A

B

C

D

PARALLEL TERMINATION Decoupling Capacitor

E

1D8V_S37,10,11,39,41,43

DDR_VREF_S041,43

1D8V_S3

DDR_VREF_S0

DDR_VREF_S0

4 4

3 3

2 2

1 1

A

Put decap near power(0.9V) and pull-up resistor

RN13

RN13

1

8

2

7
6

SRN56J-5-GP

SRN56J-5-GP

R389 56R2J-4-GPR389 56R2J-4-GP
R387 56R2J-4-GPR387 56R2J-4-GP
R367 56R2J-4-GPR367 56R2J-4-GP
R368 56R2J-4-GPR368 56R2J-4-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

3
45

1 2
1 2
1 2
1 2

RN42

RN42

1
2
3
45

RN48

RN48

1
2
3
45

RN44

RN44

1
2
3
45

RN41

RN41

1
2
3
45

RN46

RN46

1
2
3
45

RN47

RN47

1
2
3
45

RN43

RN43

1
2
3
45

RN49

RN49

1
2
3
45

RN40

RN40

1
2
3
45

RN25

RN25

1
2
3
45

RN45

RN45

1
2
3
45

M_B_A12
M_B_A9

M_B_A5
M_B_A3
M_B_A1
M_B_A10

M_B_A13

M_B_A0
M_B_A2
M_B_A4

M_B_A6
M_B_A7
M_B_A11

M_A_A13

M_A_A0
M_A_A2
M_A_A4

M_A_A12
M_A_A8

M_A_A6
M_A_A7
M_A_A11

M_A_A5
M_A_A3
M_A_A1
M_A_A10

M_A_A9
M_B_A8

M_CKE2 7,11
M_B_BS#2 8,11

M_ODT1 7,11
M_ODT3 7,11

M_ODT2 7,11
M_CS2# 7,11
M_B_RAS# 8,11

M_B_BS#1 8,11

M_CKE3 7,11

M_B_BS#0 8,11
M_B_WE# 8,11
M_CS3# 7,11
M_B_CAS# 8,11

M_ODT0 7,11
M_CS0# 7,11
M_A_RAS# 8,11

M_A_BS#1 8,11

M_A_BS#0 8,11
M_A_WE# 8,11
M_A_CAS# 8,11
M_CS1# 7,11

M_CKE0 7,11
M_A_BS#2 8,11

M_CKE1 7,11

http://laptop-motherboard-schematic.blogspot.com/

M_A_A[13..0] 8,11
M_B_A[13..0] 8,11

B

DDR_VREF_S0

12

12

1D8V_S3

1D8V_S3

Put decap near power(0.9V)
and pull-up resistor

12

C216

C216
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C229

C229
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C116

C116
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

C308

C308
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

12

C228

C228
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

12

C382

C382
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

12

C86

C86
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

12

C267

C267
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

12

12

C253

C253
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

C

C223

C223
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C377

C377
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Place these Caps near DM1

Place these Caps near DM2

12

12

C384

C384
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C227

C227
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C92

C92
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

C247

C247
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

C79

C79
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C383

C383
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

12

C381

DY

DY

C381
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C376

C376
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

12

12

12

C231

C231
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C361

C361
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

12

C324

C324
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C133

C133
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

C294

C294

C296

C296

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

12

C224

C224

C220

C220

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C108

C108
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

C96

C96
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

12

12

C123

C123
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

D

12

C252

C385

C385
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C371

C371
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

C252
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C226

C226
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C85

C85
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

12

12

12

C131

C131
SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

C240

C375

C375
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C230

C230
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DDR2 Termination Resistor

DDR2 Termination Resistor

DDR2 Termination Resistor

C240
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

C254

C254
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

12 44Wednesday, April 12, 2006

12 44Wednesday, April 12, 2006

12 44Wednesday, April 12, 2006

E

3D3V_S0

LCD/INVERTER

10KR2J-3-GP

Y41-SB

LAUNCH1

LAUNCH1

7
5

WIRELESS_BTN#

4

INTERNET#

3

PWRBTN#

2
1
6

SPD-CON5-13-GP

SPD-CON5-13-GP

20.K0247.005

20.K0247.005

The pin1 of M/B side connects
the pin5 of Launch/B side.

WLAN_TEST_LED29

10KR2J-3-GP

SB

PWRLED#29

CAP_LED#29

NUM_LED#29

CHRGER_LED#29

STDBY_LED#29

R20

R20

DY

DY

Y41-SB

12

12

Y41,-1

EC25

EC25

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

MEDIA_LED#

CHRGER_LED#

STDBY_LED#

1

23

SRN10KJ-5-GP

SRN10KJ-5-GP
RN3

RN3

DY

DY

4

12

EC26

EC26

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

PWRLED#

CAP_LED#

NUM_LED#

Y41-SB

12

12

EC27

EC27

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

R348

R348

1 2

330R2J-3-GP

330R2J-3-GP

R352

R352

1 2

330R2J-3-GP

330R2J-3-GP

R353

R353

1 2

330R2J-3-GP

330R2J-3-GP

R350

R350

1 2

100R2J-2-GP

100R2J-2-GP

R351

R351

1 2

1KR2J-1-GP

1KR2J-1-GP

R349

R349

1 2

1KR2J-1-GP

1KR2J-1-GP

R346

R346

1 2

1KR2J-1-GP

1KR2J-1-GP

LAUNCH BD CONN

R497

R497
10KR2J-3-GP

10KR2J-3-GP

MAIL# 29

WIRELESS_BTN# 29
INTERNET# 29 LDDC_DATA 7

Y41/Y40 Launch/B Button Definition

Left side Right side

WLAN

LED2

LED2

12

LED-B-48-GP

LED-B-48-GP

LED6

LED6

12

LED-B-48-GP

LED-B-48-GP

LED7

LED7

12

LED-B-48-GP

LED-B-48-GP

LED4

LED4

12

LED-B-48-GP

LED-B-48-GP

LED5

LED5

LED3

LED3

LED1

LED1

AK

AK

AK

LED-O-16-GP

LED-O-16-GP

LED-O-16-GP

LED-O-16-GP

LED-O-16-GP

LED-O-16-GP

3D3V_AUX_S5

R122

R122
100KR2J-1-GP

100KR2J-1-GP

1 2

R121

R121

1 2

470R2J-2-GP

470R2J-2-GP

C99

C99

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Internet

The edge of PCB,Top view

PWR

Mail

3D3V_S0

12

C367

C367
SCD1U50V3KX-GP

SCD1U50V3KX-GP

DY

DY

3D3V_S0

12

C369

C369
SCD1U50V3KX-GP

SCD1U50V3KX-GP

DY

DY

3D3V_S0

12

C370

C370
SCD1U50V3KX-GP

SCD1U50V3KX-GP

DY

DY

3D3V_S0

12

C372

C372
SCD1U50V3KX-GP

SCD1U50V3KX-GP

DY

DY

3D3V_S5

3D3V_S5

12

C368

C368
SCD1U50V3KX-GP

SCD1U50V3KX-GP

DY

DY

3D3V_S0

12

EC_PWRBTN# 29

3D3V_S0

EC3EC3

DCBATOUT

12

LB_DATA#_07

LB_DATA#_17

LB_DATA#_27

SC1U50V5ZY-1-GPC7SC1U50V5ZY-1-GP

GMCH_LCDVDD_ON7

LB_DATA_07

LB_DATA_17

LB_DATA_27

12

C7

LB_CLK#7

LB_CLK7

Layout 60 mil

12

TP14TPAD30 TP14TPAD30
TP10TPAD30 TP10TPAD30

SB

C5

SCD1U25V3KX-GPC5SCD1U25V3KX-GP

C15

C15

SC1U10V3KX-3GP

SC1U10V3KX-3GP

MEDIA_LED#

LCD1

LCD1

41

MH1

1
3

5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

43

MH2

AMP-CONN40-2-UGP

AMP-CONN40-2-UGP

20.F0084.040

20.F0084.040

Layout 40 mil

12

3

83.00056.E11

83.00056.E11

12

C14

C14

SCD1U50V3KX-GP

SCD1U50V3KX-GP

5V_S0

D25

D25

2

1

BAW56PT-U

BAW56PT-U

42
45
2

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

44
46

U2

U2

1

OUT

2

GND
ON/OFF#3IN

AAT4280IGU-3-T1GP

AAT4280IGU-3-T1GP

74.04280.B9P

74.04280.B9P

R341

R341
4K7R2J-2-GP

4K7R2J-2-GP

1 2

HDLED#HDLED#

Y41/Y40 LED's Location and Sequence

PWR ON

Left side Right side

WLAN

The edge of PCB,Top view

STDBY

MEDIA

CHARGER

CAP.

NUM.

http://laptop-motherboard-schematic.blogspot.com/

DY

DY

BRIGHTNESS

Layout 40 mil

IN

GND

CDROM_LED# 20

EC5

EC5

DY

DY

EC4

EC4

1 2

1 2

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

6
5
4

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

LDDC_CLK 7

LA_CLK# 7

LA_CLK 7

LA_DATA#_2 7
LA_DATA_2 7

LA_DATA#_1 7
LA_DATA_1 7

LA_DATA#_0 7
LA_DATA_0 7

3D3V_S0

12

12

R3370R2J-2-GP R3370R2J-2-GP

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet

Date: Sheet

Date: Sheet

LCDVDD_S0

12

C13

C13

DY

DY

3D3V_S0LCDVDD_S0

12

C20

C20

SC1U10V3KX-3GP

SC1U10V3KX-3GP

R340

R340
10KR2J-3-GP

10KR2J-3-GP

SATA_LED# 15

LCD / LAUNCH / LEDs

LCD / LAUNCH / LEDs

LCD / LAUNCH / LEDs

DY

DY

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

12

C17

C17

SCD1U25V3ZY-1GP

SCD1U25V3ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

EC8

EC8

EC7

EC7

1 2

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

3D3V_AUX_S515,19,29,30,31,33,34

DCBATOUT33,34,36,38,39,40,43

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

R24

R24
100KR2J-1-GP

100KR2J-1-GP

1 2

1 2

DY

DY

5V_S014,17,18,19,20,21,25,27,28,29,30,31,33,34,36,43
3D3V_S03,4,7,9,11,14,15,16,17,18,19,20,21,22,24,25,26,27,29,31,32,33,34,36,38,39,41,43
3D3V_S516,17,18,21,22,26,29,33,34,38

13 44Wednesday, April 12, 2006

13 44Wednesday, April 12, 2006

13 44Wednesday, April 12, 2006

BRIGHTNESS 29

BLON_OUT 29

5V_S0
3D3V_S0
3D3V_S5
3D3V_AUX_S5

DCBATOUT

of

of

of

A

Layout Note:
Place these resistors
close to the CRT-out
connector

CRT_RED_SYS

CRT_GREEN_SYS

4 4

CRT_BLUE_SYS

12

12

R183

R183
150R2F-1-GP

150R2F-1-GP

12

R181

R181

150R2F-1-GP

150R2F-1-GP

R171

R171
150R2F-1-GP

150R2F-1-GP

12

C565

C565

Y41,-1

12

C566

C566

SC1D8P50V2CC-GP

SC1D8P50V2CC-GP

SC1D8P50V2CC-GP

SC1D8P50V2CC-GP

1 2

L30 FCB1608CF-GPL30 FCB1608CF-GP

1 2

L27 FCB1608CF-GPL27 FCB1608CF-GP

1 2

L31 FCB1608CF-GPL31 FCB1608CF-GP

1 2

L28 FCB1608CF-GPL28 FCB1608CF-GP

1 2

L32 FCB1608CF-GPL32 FCB1608CF-GP

1 2

L29 FCB1608CF-GPL29 FCB1608CF-GP

12

C567

C567

SC1D8P50V2CC-GP

SC1D8P50V2CC-GP

Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

R160

R160

GMCH_RED7

Y41,-1

GMCH_GREEN7

R187

R187
4K7R2F-GP

4K7R2F-GP

GMCH_BLUE7

12

12

1 2

0R2J-2-GP

0R2J-2-GP

Y40_DY

Y40_DY

R157

R157

1 2

0R2J-2-GP

0R2J-2-GP

Y40_DY

Y40_DY

C193

C193

1 2

SC33P50V3JN-GP

SC33P50V3JN-GP

L16

L16

1 2

MLB201209-0150A-GP

MLB201209-0150A-GP
C200

C200
SC6P50V2CN-1GP

SC6P50V2CN-1GP

C243

C243

1 2

SC33P50V3JN-GP

SC33P50V3JN-GP

L18

L18

1 2

MLB201209-0150A-GP

MLB201209-0150A-GP
C238

C238
SC6P50V2CN-1GP

SC6P50V2CN-1GP

Y41-SB

http://laptop-motherboard-schematic.blogspot.com/

1 2

1 2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

12

DY

DY

12

Y41,-1

3D3V_S0

IN

IN

GMCH_HSY_DOCK33

GMCH_VSY_DOCK33

Q26

Q26

R1

R1

2

IN

IN

R2

R2

DTC115EE-2-GP

DTC115EE-2-GP

VGA_SYS_ON#

Q25

Q25

R1

R1

2

R2

R2

DTC115EE-2-GP

DTC115EE-2-GP

GMCH_HSY7

GMCH_VSY7

R241

R241

1 2

2K2R2F-GP

2K2R2F-GP

3
1

OUT

OUT

3

GND

GND

1

OUT

OUT

GND

GND

3D3V_S0

12

3 3

DOCK_IN#23,29,33

2 2

TV OUT CONN

TV_DACC7

1 1

TV_DACB7

A

12

R204

R204
150R2F-1-GP

150R2F-1-GP

12

R226

R226
150R2F-1-GP

150R2F-1-GP

B

R159

R159
47R2J-2-GP

47R2J-2-GP

R158

R158
47R2J-2-GP

47R2J-2-GP

3D3V_S0

12

C576

C576

Y40_DY

Y40_DY

Y41_DY

Y41_DY

12

C577

C577

GMCH_GREEN

Y40_DY

Y40_DY

Y41_DY

Y41_DY

12

C578

C578

GMCH_BLUE

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Y40_DY

Y40_DY

Y41_DY

Y41_DY

CRMA_1

C205

C205

SC6P50V2CN-1GP

SC6P50V2CN-1GP

LUMA_1

C217

C217
SC6P50V2CN-1GP

SC6P50V2CN-1GP

B

12

5V_S0

14

HSYNC_4

14

5 6

7

VGA_SYS_ON#
CRT_RED_SYS

R294

R294

1 2

0R2J-2-GP

0R2J-2-GP

VGA_SYS_ON# GMCH_GREEN
CRT_GREEN_SYSCRT_GREEN_SYS

R289

R289

1 2

0R2J-2-GP

0R2J-2-GP

VGA_SYS_ON# GMCH_BLUE
CRT_BLUE_SYS

R328

R328

1 2

0R2J-2-GP

0R2J-2-GP

Y41,-1

6
2
4

3
1
5

2 3

U10B

U10B

4

8
7
6
5

SNCB3Q3306APWRGP

SNCB3Q3306APWRGP

8
7
6
5

SNCB3Q3306APWRGP

SNCB3Q3306APWRGP

8
7
6
5

SNCB3Q3306APWRGP

SNCB3Q3306APWRGP

TVOUT1

TVOUT1

GND
GND
CRMA

LUMA
GND
GND

MINDIN4-29-GP

MINDIN4-29-GP

7

TSAHCT125PW-GP

TSAHCT125PW-GP

U47

U47

1OE#

VCC

1A

2OE#

1B

2B

GND

2A

U49

U49

1OE#

VCC

1A

2OE#

1B

2B

GND

2A

U48

U48

1OE#

VCC

1A

2OE#

1B

2B

GND

2A

Y40_DY

Y40_DY

Y40_DY

Y40_DY

Y40_DY

Y40_DY

12

C184

C184

SC1D8P50V2CC-GP

SC1D8P50V2CC-GP

12

C160

C160
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U10A

U10A

1

TSAHCT125PW-GP

TSAHCT125PW-GP

CRT_VSYNC1

1
2
3
4

1
2
3
4

1
2
3
4

C180

C180

SC1D8P50V2CC-GP

SC1D8P50V2CC-GP

Hsync & Vsync level shift

CRT_HSYNC1

GMCH_RED

CRMA_1

Reverse type

C

12

C169

C169

SC1D8P50V2CC-GP

SC1D8P50V2CC-GP

1 2

R162 0R2J-2-GPR162 0R2J-2-GP

For System CRT

1 2

R161 0R2J-2-GPR161 0R2J-2-GP

CRT_RED_DOCK 33

CRT_GREEN_DOCK 33

CRT_BLUE_DOCK 33

5V_S0

D22

D22

2

3

3

TVout

TVout

D19

D19

TVout

TVout

1

2

1

BAV99PT-GP-U

BAV99PT-GP-U

BAV99PT-GP-U

BAV99PT-GP-U

C

CRT_R

CRT_GCRT_GCRT_GCRT_G

CRT_GCRT_G

CRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_B

CRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_B

CRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_BCRT_B

DAT_DDC1_5
JVGA_HS

JVGA_VS

CLK_DDC1_5

JVGA_HS

JVGA_VSVSYNC_4

DDC_CLK & DATA level shift

GMCH_DDCDATA7

GMCH_DDCCLK7

5V_S0

D16

D16

CRT_RLUMA_1

CRT_G

CRT_B

BAV99PT-GP-U

BAV99PT-GP-U

BAV99PT-GP-U

BAV99PT-GP-U

BAV99PT-GP-U

BAV99PT-GP-U

2

3

1

D14

D14

2

3

1

D13

D13

2

3

1

D

5V_S0

21

D18

D18
CH751H-40PT

CH751H-40PT

4

RN50

RN50
SRN4K7J-8-GP

SRN4K7J-8-GP

1

2 3

12

C404

C404

SC100P50V2JN-3GP

SC100P50V2JN-3GP

3D3V_S0

4

RN51

RN51
SRN4K7J-8-GP

SRN4K7J-8-GP

1

2 3

D

E

CRT I/F & CONNECTOR

CRT1

CRT1

Y41,-1

12

C419

C419

SC100P50V2JN-3GP

SC100P50V2JN-3GP

Y41,-1

G

S

2SK3019-N-2GP

2SK3019-N-2GP

12

C155

C155
SC22P50V2JN-4GP

SC22P50V2JN-4GP

D

Q28

Q28

S

<Variant Name>

<Variant Name>

<Variant Name>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet of

Date: Sheet of

Date: Sheet

17

6

11

12
13
14
15
16

12

C147

C147
SC22P50V2JN-4GP

SC22P50V2JN-4GP

Y41,-1

G

2SK3019-N-2GP

2SK3019-N-2GP

CRT/TV Connector

CRT/TV Connector

CRT/TV Connector

1
7

2
8
3
9
4
10
5

VIDEO-15-42-GP-U

VIDEO-15-42-GP-U

20.20378.015

20.20378.015

R498

R498

1 2

0R2J-2-GP

0R2J-2-GP

Y40_DY

Y40_DY

DAT_DDC1_5DAT_DDC1_5DAT_DDC1_5DAT_DDC1_5DAT_DDC1_5DAT_DDC1_5DAT_DDC1_5

DAT_DDC1_5DAT_DDC1_5DAT_DDC1_5

1 2

0R2J-2-GP

0R2J-2-GP

Y40_DY

Y40_DY

D

Q27

Q27

3D3V_S03,4,7,9,11,13,15,16,17,18,19,20,21,22,24,25,26,27,29,31,32,33,34,36,38,39,41,43

Y41/Y40 -1

Y41/Y40 -1

Y41/Y40 -1

CRT_R

CRT_G
CRT_B

Y41-SB

GMCH_DDCDATA_DOCK 33

R499

R499

CLK_DDC1_5

5V_S013,17,18,19,20,21,25,27,28,29,30,31,33,34,36,43

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GMCH_DDCCLK_DOCK 33

14 44Friday, May 26, 2006

14 44Friday, May 26, 2006

14 44Friday, May 26, 2006

E

5V_CRT_S0

C420

C420
SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

5V_S0

3D3V_S0

of