Fujitsu MHR2030AT, MHR2020AT, MHR2010AT, MHR2040AT User Manual

MHR2040AT, MHR2030AT,

MHR2020AT, MHR2010AT

DISK DRIVES

C141-E145-02EN

PRODUCT MANUAL

FOR SAFE OPERATION

Handling of This Manual

This manual contains important information for using this product. Read thoroughly before using
the product. Use this product only after thoroughly reading and understanding especially the
section “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully.

FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering
damage to their property. Use the product according to this manual.

IMPORTANT NOTE TO USERS

READ THE ENTIRE MANUAL CAREFULLY BEFORE USING THIS PRODUCT.
INCORRECT USE OF THE PRODUCT MAY RESULT IN INJURY OR DAMAGE TO
USERS, BYSTANDERS OR PROPERTY.

While FUJITSU has sought to ensure the accuracy of all information in this manual, FUJITSU
assumes no liability to any party for any damage caused by any error or omission contained in this
manual, its updates or supplements, whether such errors or omissions result from negligence,
accident, or any other cause. In addition, FUJITSU assumes no liability with respect to the
application or use of any product or system in accordance with the descriptions or instructions
contained herein; including any liability for incidental or consequential damages arising therefrom.
FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION
CONTAINED HEREIN, WHETHER EXPRESSED, IMPLIED, OR STATUTORY.

FUJITSU reserves the right to make changes to any products described herein without further
notice and without obligation.

This product is designed and manufactured for use in standard applications such as office work,
personal devices and household appliances. This product is not intended for special uses (atomic
controls, aeronautic or space systems, mass transport vehicle operating controls, medical devices
for life support, or weapons firing controls) where particularly high reliability requirements exist,
where the pertinent levels of safety are not guaranteed, or where a failure or operational error could
threaten a life or cause a physical injury (hereafter referred to as "mission-critical" use). Customers
considering the use of these products for mission-critical applications must have safety-assurance
measures in place beforehand. Moreover, they are requested to consult our sales representative
before embarking on such specialized use.

The contents of this manual may be revised without prior notice.

The contents of this manual shall not be disclosed in any way or reproduced in any media without
the express written permission of Fujitsu Limited.

All Rights Reserved, Copyright  FUJITSU LIMITED 2001, 2002

Revision History

(1/1)

Edition Date

01 2001-12-28 — —

02 2002-01-30

Revised section (*1)

(Added/Deleted/Altered)

Details

*1 Section(s) with asterisk (*) refer to the previous edition when those were deleted.

C141-E145-02EN

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This manual describes the MHR Series, 2.5-inch hard disk drives. These drives
have a built-in controller that is compatible with the ATA interface.

This manual describes the specifications and functions of the drives and explains
in detail how to incorporate the drives into user systems. This manual assumes
that the reader has a basic knowledge of hard disk drives and their
implementations in computer systems.

This manual consists of seven chapters and sections explaining the special
terminology and abbreviations used in this manual:

Overview of Manual

CHAPTER 1 Device Overview

This chapter gives an overview of the MHR Series and describes their features.

CHAPTER 2 Device Configuration

Preface

This chapter describes the internal configurations of the MHR Series and the
configuration of the systems in which they operate.

CHAPTER 3 Installation Condit ions

This chapter describes the external dimensions, installation conditions, and switch
settings of the MHR Series.

CHAPTER 4 Theory of Device Operation

This chapter describes the operation theory of the MHR Series.

CHAPTER 5 Interface

This chapter describes the interface specifications of the MHR Series.

CHAPTER 6 Operations

This chapter describes the operations of the MHR Series.

Glossary

The glossary describes the technical terms that need to be understood to read this
manual.

Acronyms and Abbreviations

This section gives the meanings of the definitions used in this manual.

C141-E145-02EN i

Preface

Conventions for Alert Messages

This manual uses the following conventions to show the alert messages. An alert
message consists of an alert signal and alert statements. The alert signal consists
of an alert symbol and a signal word or just a signal word.

The following are the alert signals and their meanings:

This indicates a hazardous situation could result in
minor or moderate personal injury if the user does
not perform the procedure correctly. This alert
signal also indicates that damages to the product or
other property may occur if the user does not perform
the procedure correctly.

This indicates information that could help the user
use the product more efficiently.

In the text, the alert signal is centered, followed below by the indented message.
A wider line space precedes and follows the alert message to show where the alert
message begins and ends. The following is an example:

(Example)

Data corruption:

magnetic sources such as loud speakers. Ensure that the disk drive
is not affected by external magnetic fields.

The main alert messages in the text are also listed in the “Important Alert Items.”

Operating Environment

This product is designed to be used in offices or computer rooms.

Conventions

An MHR-series device is sometimes simply referred to as a "hard disk drive,"
"HDD," "drive," or "device" in this document.

Avoid mounting the disk drive near strong

Decimal numbers are represented normally.

Hexadecimal numbers are represented as shown in the following examples:
X'17B9', 17B9h, 17B9H, or 17B9H.

Binary numbers are represented as shown in the following examples: 010 or
010b.

ii C141-E145-02EN

Attention

Please forward any comments you may have regarding this manual.

To make this manual easier for users to understand, opinions from readers are
needed. Please write your opinions or requests on the Comment at the back of
this manual and forward it to the address described in the sheet.

Liability Exception

“Disk drive defects” refers to defects that involve adjustment, repair, or
replacement.

Fujitsu is not liable for any other disk drive defects, such as those caused by user
misoperation or mishandling, inappropriate operating environments, defects in the
power supply or cable, problems of the host system, or other causes outside the
disk drive.

Preface

C141-E145-02EN iii

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Important Alert Items

Important Alert Messages

The important alert messages in this manual are as follows:

A hazardous situation could result in minor or moderate personal
injury if the user does not perform the procedure correctly. Also,
damage to the product or other property, may occur if the user does not
perform the procedure correctly.

Task Alert message Page

Normal Operation

Data corruption:

magnetic sources such as loud speakers. Ensure that the disk
drive is not affected by external magnetic fields.

Damage:

it too hard, the cover and the spindle motor contact, which
may cause damage to the disk drive.

Static:

ground (500 kΩ or greater). Do not touch the printed circuit
board, but hold it by the edges.

Do not press the cover of the disk drive. Pressing

When handling the device, disconnect the body

Avoid mounting the disk near strong

3-7

C141-E145-02EN v

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Manual Organization

MHR2040AT, MHR2030AT,

MHR2020AT, MHR2010AT

DISK DRIVES

PRODUCT MANUAL

(C141-E145)

<This manual>

MHR2040AT, MHR2030AT,

MHR2020AT, MHR2010AT

DISK DRIVES

MAINTENANCE MANUAL

(C141-F055)

• Device Overview

• Device Configuration

• Installation Conditions

• Theory of Device Operation

• Interface

• Operations

• Maintenance and Diagnosis

• Removal and Replacement Procedure

C141-E145-02EN vii

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Contents

CHAPTER 1 Device Overview....................................................................... 1-1

1.1 Features 1-2

1.1.1 Functions and performance 1-2

1.1.2 Adaptability 1-2

1.1.3 Interface 1-3

1.2 Device Specifications 1-4

1.2.1 Specifications summary 1-4

1.2.2 Model and product number 1-5

1.3 Power Requirements 1-5

1.4 Environmental Specifications 1-7

1.5 Acoustic Noise 1-8

1.6 Shock and Vibration 1-8

1.7 Reliability 1-9

1.8 Error Rate 1-10

1.9 Media Defects 1-10

1.10 Load/Unload Function 1-10

CHAPTER 2 Device Configuration................................................................ 2-1

2.1 Device Configuration 2-2

2.2 System Configuration 2-4

2.2.1 ATA interface 2-4

2.2.2 1 drive connection 2-4

2.2.3 2 drives connection 2-4

C141-E145-02EN ix

Contents

CHAPTER 3 Installation Conditions..............................................................3-1

3.1 Dimensions 3-2

3.2 Mounting 3-3

3.3 Cable Connections 3-9

3.3.1 Device connector 3-9

3.3.2 Cable connector specifications 3-10

3.3.3 Device connection 3-10

3.3.4 Power supply connector (CN1) 3-11

3.4 Jumper Settings 3-11

3.4.1 Location of setting jumpers 3-11

3.4.2 Factory default setting 3-12

3.4.3 Master drive-slave drive setting 3-12

3.4.4 CSEL setting 3-13

3.4.5 Power Up in Standby setting 3-14

CHAPTER 4 Theory of Device Operation......................................................4-1

4.1 Outline 4-2

4.2 Subassemblies 4-2

4.2.1 Disk 4-2

4.2.2 Head 4-2

4.2.3 Spindle 4-3

4.2.4 Actuator 4-3

4.2.5 Air filter 4-3

4.3 Circuit Configuration 4-4

4.4 Power-on Sequence 4-7

4.5 Self-calibration 4-8

4.5.1 Self-calibration contents 4-8

4.5.2 Execution timing of self-calibration 4-9

4.5.3 Command processing during self-calibration 4-10

4.6 Read/write Circuit 4-10

x C141-E145-02EN

Contents

4.6.1 Read/write preamplifier (HDIC) 4-10

4.6.2 Write circuit 4-10

4.6.3 Read circuit 4-12

4.6.4 Digital PLL circuit 4-13

4.7 Servo Control 4-14

4.7.1 Servo control circuit 4-14

4.7.2 Data-surface servo format 4-17

4.7.3 Servo frame format 4-19

4.7.4 Actuator motor control 4-20

4.7.5 Spindle motor control 4-21

CHAPTER 5 Interface..................................................................................... 5-1

5.1 Physical Interface 5-2

5.1.1 Interface signals 5-2

5.1.2 Signal assignment on the connector 5-3

5.2 Logical Interface 5-6

5.2.1 I/O registers 5-7

5.2.2 Command block registers 5-8

5.2.3 Control block registers 5-13

5.3 Host Commands 5-14

5.3.1 Command code and parameters 5-14

5.3.2 Command descriptions 5-18

5.3.3 Error posting 5-104

5.4 Command Protocol 5-106

5.4.1 PIO Data transferring commands from device to host 5-106

5.4.2 PIO Data transferring commands from host to device 5-108

5.4.3 Commands without data transfer 5-110

5.4.4 Other commands 5-112

5.4.5 DMA data transfer commands 5-112

5.5 Ultra DMA Feature Set 5-115

5.5.1 Overview 5-115

5.5.2 Phases of operation 5-116

C141-E145-02EN xi

Contents

5.5.3 Ultra DMA data in commands 5-116

5.5.3.1 Initiating an Ultra DMA data in burst 5-116

5.5.3.2 The data in transfer 5-117

5.5.3.3 Pausing an Ultra DMA data in burst 5-117

5.5.3.4 Terminating an Ultra DMA data in burst 5-118

5.5.4 Ultra DMA data out commands 5-121

5.5.4.1 Initiating an Ultra DMA data out burst 5-121

5.5.4.2 The data out transfer 5-121

5.5.4.3 Pausing an Ultra DMA data out burst 5-122

5.5.4.4 Terminating an Ultra DMA data out burst 5-123

5.5.5 Ultra DMA CRC rules 5-125

5.5.6 Series termination required for Ultra DMA 5-126

5.6 Timing 5-127

5.6.1 PIO data transfer 5-127

5.6.2 Multiword data transfer 5-128

5.6.3 Ultra DMA data transfer 5-129

5.6.3.1 Initiating an Ultra DMA data in burst 5-129

5.6.3.2 Ultra DMA data burst timing requirements 5-130

5.6.3.3 Sustained Ultra DMA data in burst 5-133

5.6.3.4 Host pausing an Ultra DMA data in burst 5-134

5.6.3.5 Device terminating an Ultra DMA data in burst 5-135

5.6.3.6 Host terminating an Ultra DMA data in burst 5-136

5.6.3.7 Initiating an Ultra DMA data out burst 5-137

5.6.3.8 Sustained Ultra DMA data out burst 5-138

5.6.3.9 Device pausing an Ultra DMA data out burst 5-139

5.6.3.10 Host terminating an Ultra DMA data out burst 5-140

5.6.3.11 Device terminating an Ultra DMA data out burst 5-141

5.6.4 Power-on and reset 5-142

CHAPTER 6 Operations .................................................................................6-1

6.1 Device Response to the Reset 6-2

6.1.1 Response to power-on 6-2

6.1.2 Response to hardware reset 6-3

6.1.3 Response to software reset 6-5

xii C141-E145-02EN

6.1.4 Response to diagnostic command 6-6

6.2 Power Save 6-7

6.2.1 Power save mode 6-7

6.2.2 Power commands 6-9

6.3 Defect Processing 6-9

6.3.1 Spare area 6-9

6.3.2 Alternating processing for defective sectors 6-10

6.4 Read-ahead Cache 6-12

6.4.1 Data buffer structure 6-12

6.4.2 Caching operation 6-12

6.4.3 Using the read segment buffer 6-14

6.4.3.1 Miss-hit (no hit) 6-14

6.4.3.2 Sequential reading 6-15

Contents

6.4.3.3 Full hit 6-17

6.4.3.4 Partial hit 6-18

6.5 Write Cache 6-19

6.5.1 Caching operation 6-19

Glossary............................................................................................................GL-1

Acronyms and Abbreviations ........................................................................ AB-1

Index ..................................................................................................................IN-1

C141-E145-02EN xiii

Contents

Figures

Illustrations

Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-7

Figure 2.1 Disk drive outerview 2-2

Figure 2.2 Configuration of disk media heads 2-3

Figure 2.3 1 drive system configuration 2-4

Figure 2.4 2 drives configuration 2-4

Figure 3.1 Dimensions 3-2

Figure 3.2 Orientation 3-3

Figure 3.3 Mounting frame structure 3-4

Figure 3.4 Location of breather 3-5

Figure 3.5 Surface temperature measurement points 3-6

Figure 3.6 Service area 3-7

Figure 3.7 Handling cautions 3-8

Figure 3.8 Connector locations 3-9

Figure 3.9 Cable connections 3-10

Figure 3.10 Power supply connector pins (CN1) 3-11

Figure 3.11 Jumper location 3-11

Figure 3.12 Factory default setting 3-12

Figure 3.13 Jumper setting of master or slave drive 3-12

Figure 3.14 CSEL setting 3-13

Figure 3.15 Example (1) of Cable Select 3-13

Figure 3.16 Example (2) of Cable Select 3-14

Figure 4.1 Head structure 4-3

Figure 4.2 Power Supply Configuration 4-5

Figure 4.3 Circuit Configuration 4-6

Figure 4.4 Power-on operation sequence 4-8

Figure 4.5 Read/write circuit block diagram 4-11

Figure 4.6 Frequency characteristic of programmable filter 4-12

Figure 4.7 Block diagram of servo control circuit 4-14

Figure 4.8 Physical sector servo configuration on disk surface 4-18

Figure 4.9 Servo frame format 4-19

xiv C141-E145-02EN

Contents

Figure 5.1 Interface signals 5-2

Figure 5.2 Execution example of READ MULTIPLE command 5-21

Figure 5.3 Read Sector(s) command protocol 5-107

Figure 5.4 Protocol for command abort 5-108

Figure 5.5 WRITE SECTOR(S) command protocol 5-110

Figure 5.6 Protocol for the command execution without data transfer 5-111

Figure 5.7 Normal DMA data transfer 5-114

Figure 5.8 Ultra DMA termination with pull-up or pull-down 5-126

Figure 5.9 PIO data transfer timing 5-127

Figure 5.10 Multiword DMA data transfer timing (mode 2) 5-128

Figure 5.11 Initiating an Ultra DMA data in burst 5-129

Figure 5.12 Sustained Ultra DMA data in burst 5-133

Figure 5.13 Host pausing an Ultra DMA data in burst 5-134

Figure 5.14 Device terminating an Ultra DMA data in burst 5-135

Figure 5.15 Host terminating an Ultra DMA data in burst 5-136

Figure 5.16 Initiating an Ultra DMA data out burst 5-137

Figure 5.17 Sustained Ultra DMA data out burst 5-138

Figure 5.18 Device pausing an Ultra DMA data out burst 5-139

Figure 5.19 Host terminating an Ultra DMA data out burst 5-140

Figure 5.20 Device terminating an Ultra DMA data out burst 5-141

Figure 5.21 Power-on Reset Timing 5-142

Figure 6.1 Response to power-on 6-3

Figure 6.2 Response to hardware reset 6-4

Figure 6.3 Response to software reset 6-5

Figure 6.4 Response to diagnostic command 6-6

Figure 6.5 Sector slip processing 6-10

Figure 6.6 Alternate cylinder assignment processing 6-11

Figure 6.7 Data buffer structure 6-12

C141-E145-02EN xv

Contents

Tables

Table 1.1 Specifications 1-4

Table 1.2 Model names and product numbers 1-5

Table 1.3 Current and power dissipation 1-6

Table 1.4 Environmental specifications 1-7

Table 1.5 Acoustic noise specification 1-8

Table 1.6 Shock and vibration specification 1-8

Table 3.1 Surface temperature measurement points and standard values 3-6

Table 3.2 Cable connector specifications 3-10

Table 5.1 Signal assignment on the interface connector 5-3

Table 5.2 I/O registers 5-7

Table 5.3 Command code and parameters 5-15

Table 5.4 Information to be read by IDENTIFY DEVICE command 5-34

Table 5.5 Features register values and settable modes 5-44

Table 5.6 Diagnostic code 5-56

Table 5.7 Features Register values (subcommands) and functions 5-68

Table 5.8 Format of device attribute value data 5-72

Table 5.9 Format of insurance failure threshold value data 5-72

Table 5.10 Log Directory Data Format 5-77

Table 5.11 Data format of SMART Summary Error Log (1/2) 5-78

Table 5.12 SMART self test log data format 5-80

Table 5.13 Contents of security password 5-82

Table 5.14 Contents of SECURITY SET PASSWORD data 5-86

Table 5.15 Relationship between combination of Identifier and Security level,

and operation of the lock function 5-87

Table 5.16 DEVICE CONFIGURATION IDENTIFY data structure 5-93

Table 5.17 Command code and parameters 5-104

Table 5.18 Ultra DMA data burst timing requirements 5-130

Table 5.19 Ultra DMA sender and recipient timing requirements 5-132

xvi C141-E145-02EN

CHAPTER 1 Device Overview

1.1 Features

1.2 Device Specifications

1.3 Power Requirements

1.4 Environmental Specifications

1.5 Acoustic Noise

1.6 Shock and Vibration

1.7 Reliability

1.8 Error Rate

1.9 Media Defects

1.10 Load/Unload Function

Overview and features are described in this chapter, and specifications and power
requirement are described.

The MHR Series are 2.5-inch hard disk drives with built-in disk controllers.
These disk drives use the AT-bus hard disk interface protocol and are compact
and reliable.

C141-E145-02EN 1-1

Device Overview

1.1 Features

1.1.1 Functions and performance

The following features of the MHR Series are described.

(1) Compact

The MHR Series has 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its
height is 9.5 mm (0.374 inch).

(2) Large capacity

The disk drive can record up to 20 GB (formatted) on one disk using the 48/50
RLL recording method and 30 recording zone technology. The MHR Series has a
formatted capacity of 40 GB (MHR2040AT), 30 GB (MHR2030AT), 20 GB
(MHR2020AT) and 10 GB (MHR2010AT) respectively.

(3) High-speed Transfer rate

The disk drives (the MHR Series) have an internal data rate up to 32.5 MB/s. The
disk drive supports an external data rate up to 100 MB/s (U-DMA mode 5).

(4) Average positioning time

Use of a rotary voice coil motor in the head positioning mechanism greatly
increases the positioning speed. The average positioning time is 12 ms (at read).

1.1.2 Adaptability

(1) Power save mode

The power save mode feature for idle operation, stand by and sleep modes makes
The disk drives (the MHR Series) ideal for applications where power
consumption is a factor.

(2) Wide temperature range

The disk drives (the MHR Series) can be used over a wide temperature range (5°C
to 55°C).

(3) Low noise and vibration

In Ready status, the noise of the disk drives (the MHR Series) is only 24 dBA
(measured at 0.3 m apart from the drive under the idle mode).

(4) High resistance against shock

The Load/Unload mechanism is highly resistant against non-operation shock up
to 8820 m/s

2

(900G).

1-2 C141-E145-02EN

1.1.3 Interface

(1) Connection to ATA interface

The MHR-series disk drives have built-in controllers compatible with the ATA
interface.

(2) 2 MB data buffer

The disk drives (the MHR Series) use a 2 MB data buffer to transfer data between
the host and the disk media.

In combination with the read-ahead cache system described in item (3) and the
write cache described in item (7), the buffer contributes to efficient I/O
processing.

(3) Read-ahead cache system

After the execution of a disk read command, the disk drive automatically reads
the subsequent data block and writes it to the data buffer (read ahead operation).
This cache system enables fast data access. The next disk read command would
normally cause another disk access. But, if the read ahead data corresponds to the
data requested by the next read command, the data in the buffer can be transferred
instead.

1.1 Features

(4) Master/slave

The disk drives (the MHR Series) can be connected to ATA interface as daisy
chain configuration. Drive 0 is a master device, drive 1 is a slave device.

(5) Error correction and retry by ECC

If a recoverable error occurs, the disk drives (the MHR Series) themselves
attempt error recovery. The ECC has improved buffer error correction for
correctable data errors.

(6) Self-diagnosis

The disk drives (the MHR Series) have a diagnostic function to check operation
of the controller and disk drives. Executing the diagnostic command invokes self­diagnosis.

(7) Write cache

When the disk drives (the MHR Series) receive a write command, the disk drives
post the command completion at completion of transferring data to the data buffer
completion of writing to the disk media. This feature reduces the access time at
writing.

C141-E145-02EN 1-3

Device Overview

1.2 Device Specifications

1.2.1 Specifications summary

Table 1.1 shows the specifications of the disk drives (MHR Series).

Table 1.1 Speci f i cations (1/2)

MHR2040AT MHR2030AT MHR2020AT MHR2010AT
Format Capacity (*1) 40 GB 30 GB
Number of Heads 4 3
Number of Cylinders (User) 35,968
Number of Sectors (User) 78,140,160 58,605,120 39,070,080 19,640,880
Bytes per Sector 512
Recording Method 48/50 RLL
Track Density 2.42 K track/mm (61,500 TPI)
Bit Density 23.30 K bit/mm (592,000 BPI)
Rotational Speed 4,200 rpm ± 1%
Average Latency 7.14 ms
Positioning time (read and seek)

• Minimum (Track to Track)

• Average

• Maximum (Full)
Start time Typ.: 5 sec
Interface ATA-5 (Max. Cable length: 0.46 m)

(equipped with expansion function)

1.5 ms (typ.)

Read: 12 ms (typ.)

22 ms (typ.)

20 GB 10 GB

21

Data Transfer Rate

• To/From Media 18.4 to 32.5 MB/s

• To/From Host 100 MB/s Max.

(U-DMA mode 5)
Data Buffer Size 2 MB
Physical Dimensions

(Height × Width × Depth)
Weight 99 g

*1: Capacity under the LBA mode.

9.5 mm × 100.0 mm ×70.0 mm

1-4 C141-E145-02EN

1.3 Power Requirements

Table 1.1 lists the formatted capacity, number of logical cylinders, number
of heads, and number of sectors of every model for which the CHS mode
has been selected using the BIOS setup utility on the host.

Table 1.1 Speci f i cations (2/2)

Model Capacity No. of Cylinder No. of Heads No. of Sectors

MHR2040AT 8.45 GB 16,383 16 63
MHR2030AT 8.45 GB 16,383 16 63
MHR2020AT 8.45 GB 16,383 16 63
MHR2010AT 8.45 GB 16,383 16 63

1.2.2 Model and product number

Table 1.2 lists the model names and product numbers of the MHR Series.

Table 1.2 M odel names and product numbers

Model Name Capacity

(user area)

MHR2040AT 40 GB M3, depth 3 CA06062-B042
MHR2030AT 30 GB M3, depth 3 CA06062-B032
MHR2020AT 20 GB M3, depth 3 CA06062-B022
MHR2010AT 10 GB M3, depth 3 CA06062-B012

Mounting screw Order No.

1.3 Power Requirements

(1) Input Voltage

•

+ 5 V ± 5 %

(2) Ripple

+5 V
Maximum 100 mV (peak to peak)
Frequency DC to 1 MHz

C141-E145-02EN 1-5

Device Overview

(3) Current Requirements and Power Dissipation

Table 1.3 lists the current and power dissipation (typical).

Table 1.3 Current and power dissipation

Typical RMS Current Typical Power (*3)

MHR Series MHR Series
Spin up (*1) 0.9 A 4.5 W
Idle 130 mA 0.65 W
R/W (on track) (*2) 460 mA 2.3 W
Seek (*5) 460 mA 2.3 W
Standby 50 mA 0.25 W
Sleep 20 mA 0.1 W
Energy

Efficiency (*4)

— 0.016 W/GB

(rank E / MHR2040AT)

(rank E / MHR2030AT)

(rank D / MHR2020AT)

(rank D / MHR2010AT)

0.016 W/GB

0.033 W/GB

0.033 W/GB

*1 Current at starting spindle motor.
*2 Current and power level when the operation (command) that accompanies a

transfer of 63 sectors is executed 3 times in 100 ms
*3 Power requirements reflect nominal values for +5V power.
*4 Energy efficiency based on the Law concerning the Rational Use of Energy

indicates the value obtained by dividing power consumption by the storage

capacity. (Japan only)
*5 The seek average current is specified based on three operations per 100

msec.

(4) Current fluctuation (Typ.) at +5V when power is turned on

1-6 C141-E145-02EN

Figure 1.1 Current fluctuation (Typ.) at +5V w hen power is turned on

(5) Power on/off sequence

The voltage detector circuits (the MHR Series) monitor +5 V. The circuits do not
allow a write signal if either voltage is abnormal. These prevent data from being
destroyed and eliminates the need to be concerned with the power on/off
sequence.

1.4 Environmental Specifications

1.4 Environmental Specifications

Table 1.4 lists the environmental specifications.

Table 1.4 Envi r onment al specifications

Item Specification
Temperature

• Operating

• Non-operating

• Thermal Gradient

Humidity

• Operating

• Non-operating

• Maximum Wet Bulb

5°C to 55°C (ambient)
5°C to 60°C (disk enclosure surface)
–40°C to 65°C
20°C/h or less

8% to 90% RH (Non-condensing)
5% to 95% RH (Non-condensing)
29°C (Operating)

40°C (Non-operating)

Altitude (relative to sea level)

• Operating

• Non-operating

C141-E145-02EN 1-7

–300 to 3,000 m
–300 to 12,000 m

Device Overview

1.5 Acoustic Noise

Table 1.5 lists the acoustic noise specification.

Table 1.5 Acoust i c noi se specification

Item Specification
Sound Pressure

• Idle mode (DRIVE READY) 24 dBA typical at 0.3 m

Note:

Measure the noise from the cover top surface.

1.6 Shock and Vibration

Table 1.6 lists the shock and vibration specification.

Table 1.6 Shock and vi brat i on specification

Item Specification
Vibration (Swept sine, 1/4 octave per minute)

• Operating

5 to 500 Hz, 9.8m/s
(without non-recovered errors)

5 to 500 Hz, 49m/s

• Non-operating

(no damage)

Shock (half-sine pulse)

• Operating

1960 m/s

2

0-peak (200G 0-peak)

2ms duration

• Non-operating

(without non-recovered errors)
8820 m/s

2

0-peak (900G 0-peak)

1ms duration
1176 m/s

2

0-peak (120G 0-peak)

11ms duration
(no damage)

2

0-peak (1G 0-peak)

2

0-peak (5G 0-peak)

1-8 C141-E145-02EN

1.7 Reliability

(1) Mean time between failures (MTBF)

Conditions of 300,000 h Power-on time 250H/month or less 3000H/years

MTBF is defined as follows:

Total operation time in all fields

MTBF= (H)

number of device failure in all fields (*1)

*1 “Disk drive defects” refers to defects that involve repair, readjustment, or

replacement. Disk drive defects do not include failures caused by external
factors, such as damage caused by handling, inappropriate operating
environments, defects in the power supply host system, or interface cable.

1.7 Reliability

or less
Operating time 20% or less of power-on time
Environment 5 to 55°C/8 to 90%

But humidity bulb temperature

29°C or less

(2) Mean time to repair (MTTR)

The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist
maintenance staff member.

(3) Service life

In situations where management and handling are correct, the disk drive requires
no overhaul for five years when the DE surface temperature is less than 48°C.
When the DE surface temperature exceeds 48°C, the disk drives requires no
overhaul for five years or 20,000 hours of operation, whichever occurs first.
Refer to item (3) in Subsection 3.2 for the measurement point of the DE surface
temperature. Also the operating conditions except the environment temperature
are based on the MTBF conditions.

(4) Data assurance in the event of power failure

Except for the data block being written to, the data on the disk media is assured in
the event of any power supply abnormalities. This does not include power supply
abnormalities during disk media initialization (formatting) or processing of
defects (alternative block assignment).

C141-E145-02EN 1-9

Device Overview

1.8 Error Rate

Known defects, for which alternative blocks can be assigned, are not included in
the error rate count below. It is assumed that the data blocks to be accessed are
evenly distributed on the disk media.

(1) Unrecoverable read error

Read errors that cannot be recovered by maximum read retries of drive without
user’s retry and ECC corrections shall occur no more than 10 times when reading
data of 10
recovery procedure, and include read retries accompanying head offset
operations.

(2) Positioning error

14

bits. Read retries are executed according to the disk drive’s error

Positioning (seek) errors that can be recovered by one retry shall occur no more
than 10 times in 10

7

seek operations.

1.9 Media Defects

Defective sectors are replaced with alternates when the disk (the MHR Series) are
formatted prior to shipment from the factory (low level format). Thus, the hosts
see a defect-free devices.

Alternate sectors are automatically accessed by the disk drive. The user need not
be concerned with access to alternate sectors.

1.10Load/Unload Function

The Load/Unload function is a mechanism that loads the head on the disk and
unloads the head from the disk.

The product supports a minimum of 300,000 normal Load/Unload cycles.
Normal Unload is a normal head unloading operation and the commands listed
below are executed.

•

Hard Reset

•

Standby

•

Standby immediate

•

Sleep

•

Idle

1-10 C141-E145-02EN

1.10 Load/Unload Function

Emergency Unload other than Normal Unload is performed when the power is
shut down while the heads are still loaded on the disk.
The product supports the Emergency Unload a minimum of 20,000 times.
When the power is shut down, the controlled Normal Unload cannot be executed.
Therefore, the number of Emergency other than Normal Unload is specified.

C141-E145-02EN 1-11

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CHAPTER 2 Device Configuration

2.1 Device Configuration

2.2 System Configuration

This chapter describes the internal configurations of the hard disk drives and the
configuration of the systems in which they operate.

C141-E145-02EN 2-1

Device Configuration

2.1 Device Configuration

Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE),
read/write preamplifier, and controller PCA. The disk enclosure contains the disk
media, heads, spindle motors, actuators, and a circulating air filter.

Figure 2.1 Disk drive outerview

MHR Series

(1) Disk

(2) Head

The outer diameter of the disk is 65 mm. The inner diameter is 20 mm. The
number of disks used varies with the model, as described below.

MHR2040AT: 2 disks MHR2030AT: 2 disks

MHR2020AT: 1 disk MHR2010AT: 1 disk

The heads are of the load/unload (L/UL) type. The head unloads the disk out of
while the disk is not rotating and loads on the disk when the disk starts.

Figure 2.2 illustrates the configuration of the disks and heads of each model. In
the disk surface, servo information necessary for controlling positioning and
read/write and user data are written. Numerals 0 to 3 indicate read/write heads.

2-2 C141-E145-02EN

2.1 Device Configuration

Head

3
2

1

0

MHR2040AT

(3) Spindle motor

(4) Actuator

Head

3

2

Head

1

0

MHR2030AT

1
0

MHR2020AT

(Either of head 0 or
head 3 is mounted.)

Figure 2.2 Configuration of disk media heads

The disks are rotated by a direct drive Hall-less DC motor.

Head

1

0

MHR2010AT

(Either of head 0 or
head 1 is mounted.)

The actuator uses a revolving voice coil motor (VCM) structure which consumes
low power and generates very little heat. The head assembly at the edge of the
actuator arm is controlled and positioned by feedback of the servo information
read by the read/write head. If the power is not on or if the spindle motor is
stopped, the head assembly stays on the ramp out of the disk and is fixed by a
mechanical lock.

(5) Air circulation system

The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk
enclosure features a closed loop air circulation system that relies on the blower
effect of the rotating disk. This system continuously circulates the air through the
circulation filter to maintain the cleanliness of the air within the disk enclosure.

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves
data reliability by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip to improve reliability. The high­speed microprocessor unit (MPU) achieves a high-performance AT controller.

C141-E145-02EN 2-3

Device Configuration

2.2 System Configuration

2.2.1 ATA interface

Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has
a 44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6
MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode
3/4/5 transfer at 33/66/100 MB/s.

2.2.2 1 drive connection

MHR2040AT
MHR2030AT

MHC2032AT
MHR2020AT

MHC2040AT
MHR2010AT

Figure 2.3 1 drive system configuration

2.2.3 2 drives connection

MHR2040AT
MHR2030AT

(Host adaptor)

Note:

When the drive that is not conformed to ATA is connected to the disk drive above
configuration, the operation is not guaranteed.

MHC2032AT
MHR2020AT

MHC2040AT
MHR2010AT

MHR2040AT

MHG2102AT

MHR2030AT

MHC2032AT

MHH2064AT

MHR2020AT

MHC2040AT

MHH2032AT

MHR2010AT

Figure 2.4 2 drives configuration

2-4 C141-E145-02EN

2.2 System Configuration

IMPORTANT

HA (host adaptor) consists of address decoder, driver, and receiver.
ATA is an abbreviation of “AT attachment”. The disk drive is
conformed to the ATA-5 interface.

At high speed data transfer (PIO mode 4 or DMA mode 2 U-DMA
mode 5), occurrence of ringing or crosstalk of the signal lines (AT
bus) between the HA and the disk drive may be a great cause of the
obstruction of system reliability. Thus, it is necessary that the
capacitance of the signal lines including the HA and cable does not
exceed the ATA-5 standard, and the cable length between the HA
and the disk drive should be as short as possible.

No need to push the top cover of the disk drive. If the over-power
worked, the cover could be contacted with the spindle motor. Thus,
that could be made it the cause of failure.

C141-E145-02EN 2-5

This page is intentionally left blank.

CHAPTER 3 Installation Conditions

3.1 Dimensions

3.2 Mounting

3.3 Cable Connections

3.4 Jumper Settings

This chapter gives the external dimensions, installation conditions, surface
temperature conditions, cable connections, and switch settings of the hard disk
drives.

For information about handling this hard disk drive and the system installation
procedure, refer to the following Integration Guide.
C141-E144

C141-E145-02EN 3-1

Installation Conditions

3.1 Dimensions

Figure 3.1 illustrates the dimensions of the disk drive and positions of the
mounting screw holes. All dimensions are in mm.

Figure 3.1 Dimensions

3-2 C141-E145-02EN

3.2 Mounting

For information on mounting, see the "FUJITSU 2.5-INCH HDD
INTEGRATION GUIDANCE(C141-E144-01EN)."

(1) Orientation

Figure 3.2 illustrates the allowable orientations for the disk drive.

3.2 Mounting

gravity

(a) Horizontal –1

(c) Vertical –1

(b) Horizontal –1

gravity

(d) Vertical –2

gravity

(e) Vertical –3

Figure 3.2 Orientation

C141-E145-02EN 3-3

(f) Vertical –4

Installation Conditions

(2) Frame

The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame
is connected to SG.

Use M3 screw for the mounting screw and the screw length should
satisfy the specification in Figure 3.3.

The tightening torque must be 0.49N·m(5kgf·cm).
When attaching the HDD to the system frame, do not allow the

system frame to touch parts (cover and base) other than parts to
which the HDD is attached.

(3) Limitation of mounting

Note) These dimensions are recommended values; if it is not possible to

IMPORTANT

satisfy them, contact us.

Bottom surface mounting

2

A

Frame of system
cabinet

3.0 or less

DE

2.5

2.5

Frame of system
cabinet

Screw

3.0 or less

Details of A

Details of B

Figure 3.3 Mounting frame structure

Side surface
mounting

PCA

Screw

2.52.5

B

3-4 C141-E145-02EN

3.2 Mounting

IMPORTANT

Because of breather hole mounted to the HDD, do not allow this to
close during mounting.

Locating of breather hole is shown as Figure 3.4.
For breather hole of Figure 3.4, at least, do not allow its around

φ2.4 to block.

Figure 3.4 Location of breather

C141-E145-02EN 3-5

Installation Conditions

(4) Ambient temperature

The temperature conditions for a disk drive mounted in a cabinet refer to the
ambient temperature at a point 3 cm from the disk drive. The ambient
temperature must satisfy the temperature conditions described in Section 1.4, and
the airflow must be considered to prevent the DE surface temperature from
exceeding 60°C.

Provide air circulation in the cabinet such that the PCA side, in particular,
receives sufficient cooling. To check the cooling efficiency, measure the surface
temperatures of the DE. Regardless of the ambient temperature, this surface
temperature must meet the standards listed in Table 3.1. Figure 3.5 shows the
temperature measurement point.

1

•

Figure 3.5 Surface temperature measurement points

Table 3.1 Surface t emperat ure measurement points and standard values

No. Measurement point Temperature

1 DE cover 60°C max

3-6 C141-E145-02EN

(5) Service area

Cable connection

3.2 Mounting

Figure 3.6 shows how the drive must be accessed (service areas) during and after
installation.

Mounting screw hole

Mounting screw hole

Figure 3.6 Service area

(6) Handling cautions

Please keep the following cautions, and handle the HDD under the safety
environment.

Data corruption:

magnetic sources such as loud speakers. Ensure that the disk drive
is not affected by external magnetic fields.

Damage:

hard, the cover and the spindle motor contact, which may cause
damage to the disk drive.

Static:

(500 kΩ or greater). Do not touch the printed circuit board, but
hold it by the edges.

Do not press the cover of the disk drive. Pressing it too

When handling the device, disconnect the body ground

Avoid mounting the disk drive near strong

C141-E145-02EN 3-7

Installation Conditions

- General notes

Wrist strap

Use the Wrist strap.

ESD mat

Shock absorbing mat

Place the shock absorbing mat on the
operation table, and place ESD mat on it.

Do not hit HDD each other.

Do not place HDD vertically
to avoid falling down.

Do not stack when carrying.

Figure 3.7 Handling cautions

- Installation

(1) Please use the driver of a low impact when you use an electric driver.

HDD is occasionally damaged by the impact of the driver.

(2) Please observe the tightening torque of the screw strictly.

M3 ······· 0.49 N·m (5 Kg·cm)

- Recommended equipments

Do not drop.

Contents Model Maker

Wrist strap JX-1200-3056-8 SUMITOMO 3MESD

ESD mat SKY-8A (Color Seiden Mat) Achilles

Shock Low shock driver SS-6500 HIOS

3-8 C141-E145-02EN

3.3 Cable Connections

3.3.1 Device connector

The disk drive has the connectors and terminals listed below for connecting
external devices. Figure 3.8 shows the locations of these connectors and
terminals.

3.3 Cable Connections

Connector,
setting pins

PCA

Figure 3.8 Connector locations

C141-E145-02EN 3-9

Installation Conditions

3.3.2 Cable connector specifications

Table 3.2 lists the recommended specifications for the cable connectors.

Table 3.2 Cabl e connect or speci f ications

Name Model Manufacturer

ATA interface and power
supply cable (44-pin type)

For the host interface cable, use a ribbon cable. A twisted cable or
a cable with wires that have become separated from the ribbon may
cause crosstalk between signal lines. This is because the interface
is designed for ribbon cables and not for cables carrying differential
signals.

3.3.3 Device connection

Figure 3.9 shows how to connect the devices.

Host system

Cable socket
(44-pin type)

IMPORTANT

Interface

89361-144 FCI

Disk Drive #0

Interface

DC
Power supply

Power supply cable

Disk Drive #1

Figure 3.9 Cable connections

3-10 C141-E145-02EN

3.3.4 Power supply connector (CN1)

Figure 3.10 shows the pin assignment of the power supply connector (CN1).

3.4 Jumper Settings

Figure 3.10 Power supply connector pins (CN1)

3.4 Jumper Settings

3.4.1 Location of setting jumpers

Figure 3.11 shows the location of the jumpers to select drive configuration and
functions.

Figure 3.11 Jumper location

C141-E145-02EN 3-11

Installation Conditions

3.4.2 Factory default setting

Figure 3.12 shows the default setting position at the factory.

Open

Figure 3.12 Factory default setting

3.4.3 Master drive-slave drive setting

Master drive (disk drive #0) or slave drive (disk drive #1) is selected.

Open

1C

2

A

BD

Open

Open

AC1

Short

BD2

(b) Slave drive(a) Master drive

Figure 3.13 Jumper setting of master or slave drive

Note:

Pins A and C should be open.

3-12 C141-E145-02EN

3.4.4 CSEL setting

Figure 3.14 shows the cable select (CSEL) setting.

Note:

3.4 Jumper Settings

Open

AC1

BD2

Short

The CSEL setting is not depended on setting between pins Band D.

Figure 3.14 CSEL setting

Figure 3.15 and 3.16 show examples of cable selection using unique interface
cables.

By connecting the CSEL of the master drive to the CSEL Line (conducer) of the
cable and connecting it to ground further, the CSEL is set to low level. The drive
is identified as a master drive. At this time, the CSEL of the slave drive does not
have a conductor. Thus, since the slave drive is not connected to the CSEL
conductor, the CSEL is set to high level. The drive is identified as a slave drive.

drive drive

Figure 3.15 Example (1) of Cable Select

C141-E145-02EN 3-13

Installation Conditions

Figure 3.16 Example (2) of Cable Select

3.4.5 Power Up in Standby setting

When pin C is grounded, the drive does not spin up at power on.

drive drive

3-14 C141-E145-02EN

CHAPTER 4 Theory of Device Operation

4.1 Outline

4.2 Subassemblies

4.3 Circuit Configuration

4.4 Power-on Sequence

4.5 Self-calibration

4.6 Read/write Circuit

4.7 Servo Control

This chapter explains basic design concepts of the disk drive. Also, this chapter
explains subassemblies of the disk drive, each sequence, servo control, and
electrical circuit blocks.

C141-E145-02EN 4-1

Theory of Device Operation

4.1 Outline

This chapter consists of two parts. First part (Section 4.2) explains mechanical
assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a
servo information recorded in the disk drive and drive control method.

4.2 Subassemblies

The disk drive consists of a disk enclosure (DE) and printed circuit assembly
(PCA).

The DE contains all movable parts in the disk drive, including the disk, spindle,
actuator, read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.5.

The PCA contains the control circuits for the disk drive. The disk drive has one
PCA. For details, see Sections 4.3.

4.2.1 Disk

4.2.2 Head

The DE contains disks with an outer diameter of 65 mm and an inner diameter of
20 mm. The MHR2040AT and MHR2030AT have two disks and MHR2020AT
and MHR2010AT have one disk.

Servo data is recorded on each cylinder (total 120). Servo data written at factory
is read out by the read head. For servo data, see Section 4.7.

Figure 4.1 shows the head structures. MHR2040AT has 4 heads and
MHR2030AT has 3 heads and MHR2020AT and MHR2010AT have 2 heads.

4-2 C141-E145-02EN

4.2 Subassemblies

Head

3
2

1
0

MHR2040AT

4.2.3 Spindle

Head

3

2

Head

1

0

MHR2030AT

(Either of head 0 or
head 3 is mounted.)

Figure 4.1 Head structure

The spindle consists of a disk stack assembly and spindle motor. The disk stack
assembly is activated by the direct drive sensor-less DC spindle motor, which has
a speed of 4,200 rpm ±1%. The spindle is controlled with detecting a PHASE
signal generated by counter electromotive voltage of the spindle motor at starting.

1

0

MHR2020AT

Head

1
0

MHR2010AT

(Either of head 0 or
head 1 is mounted.)

4.2.4 Actuator

4.2.5 Air filter

The actuator consists of a voice coil motor (VCM) and a head carriage. The
VCM moves the head carriage along the inner or outer edge of the disk. The head
carriage position is controlled by feeding back the difference of the target position
that is detected and reproduced from the servo information read by the read/write
head.

There are two types of air filters: a breather filter and a circulation filter.

The breather filter makes an air in and out of the DE to prevent unnecessary
pressure around the spindle when the disk starts or stops rotating. When disk
drives are transported under conditions where the air pressure changes a lot,
filtered air is circulated in the DE.

The circulation filter cleans out dust and dirt from inside the DE. The disk drive
cycles air continuously through the circulation filter through an enclosed loop air
cycle system operated by a blower on the rotating disk.

C141-E145-02EN 4-3

Theory of Device Operation

4.3 Circuit Configuration

Figure 4.2 shows the power supply configuration of the disk drive, and Figure 4.3
shows the disk drive circuit configuration.

(1) Read/write circuit

The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and
read channel (RDC).

The PreAMP consists of the write current switch circuit, that flows the write
current to the head coil, and the voltage amplifier circuit, that amplitudes the read
output from the head.

The RDC is the read demodulation circuit using the Modified Extended Partial
Response (MEEPR), and contains the Viterbi detector, programmable filter,
adaptable transversal filter, times base generator, data separator circuits, 48/50
RLL (Limited) encoder Run Length and servo demodulation circuit.

(2) Servo circuit

The position and speed of the voice coil motor are controlled by 2 closed-loop
servo using the servo information recorded on the data surface. The servo
information is an analog signal converted to digital for processing by a MPU and
then reconverted to an analog signal for control of the voice coil motor.

The MPU precisely sets each head on the track according on the servo
information on the media surface.

(3) Spindle motor driver circuit

The circuit measures the interval of a PHASE signal generated by counter­electromotive voltage of a motor and controls the motor speed comparing target
speed.

(4) Controller circuit

Major functions are listed below.

•

Data buffer (2 MB) management

•

ATA interface control and data transfer control

•

Sector format control

•

Defect management

•

ECC control

•

Error recovery and self-diagnosis

4-4 C141-E145-02EN

5.0V

4.3 Circuit Configuration

S-DRAM SVC HDIC F-ROM

3.3V

MCU

&

HDC

- 3.0V

1.8V

RDC

Figure 4.2 Power Supply Configuration

1.8-V

generator

circuit

C141-E145-02EN 4-5

Theory of Device Operation

Figure 4.3 Circuit Configuration

4-6 C141-E145-02EN

4.4 Power-on Sequence

Figure 4.4 describes the operation sequence of the disk drive at power-on. The
outline is described below.

a) After the power is turned on, the disk drive executes the MPU bus test,

internal register read/write test, and work RAM read/write test. When the
self-diagnosis terminates successfully, the disk drive starts the spindle motor.

b) The disk drive executes self-diagnosis (data buffer read/write test) after

enabling response to the ATA bus.

c) After confirming that the spindle motor has reached rated speed, the head

assembly is loaded on the disk.

d) The disk drive positions the heads onto the SA area and reads out the system

information.

e) The disk drive executes self-seek-calibration. This collects data for VCM

torque and mechanical external forces applied to the actuator, and updates the
calibrating value.

4.4 Power-on Sequence

f) The drive becomes ready. The host can issue commands.

C141-E145-02EN 4-7

Theory of Device Operation

Power-on

a)

Self-diagnosis 1

- MPU bus test

- Internal register
write/read test

- Work RAM write/read
test

The spindle motor starts.

b)

Self-diagnosis 2

- Data buffer write/read
test

c)

Confirming spindle motor
speed

Load the head assembly

Start

d)

Initial on-track and read
out of system information

e)

Execute self-calibration

f)

Drive ready state
(command waiting state)

Figure 4.4 Power-on operation sequence

4.5 Self-calibration

The disk drive occasionally performs self-calibration in order to sense and
calibrate mechanical external forces on the actuator, and VCM torque. This
enables precise seek and read/write operations.

4.5.1 Self-calibration contents

(1) Sensing and compensating for external forces

The actuator suffers from torque due to the FPC forces and winds accompanying
disk revolution. The torque vary with the disk drive and the cylinder where the
head is positioned. To execute stable fast seek operations, external forces are
occasionally sensed.

End

The firmware of the drive measures and stores the force (value of the actuator
motor drive current) that balances the torque for stopping head stably. This
includes the current offset in the power amplifier circuit and DAC system.

4-8 C141-E145-02EN

The forces are compensated by adding the measured value to the specified current
value to the power amplifier. This makes the stable servo control.

To compensate torque varying by the cylinder, the disk is divided into 16 areas
from the innermost to the outermost circumference and the compensating value is
measured at the measuring cylinder on each area at factory calibration. The
measured values are stored in the SA cylinder. In the self-calibration, the
compensating value is updated using the value in the SA cylinder.

(2) Compensating open loop gain

Torque constant value of the VCM has a dispersion for each drive, and varies
depending on the cylinder that the head is positioned. To realize the high speed
seek operation, the value that compensates torque constant value change and loop
gain change of the whole servo system due to temperature change is measured
and stored.

For sensing, the firmware mixes the disturbance signal to the position signal at the
state that the head is positioned to any cylinder. The firmware calculates the loop
gain from the position signal and stores the compensation value against to the
target gain as ratio.

4.5 Self-calibration

For compensating, the direction current value to the power amplifier is multiplied
by the compensation value. By this compensation, loop gain becomes constant
value and the stable servo control is realized.

To compensate torque constant value change depending on cylinder, whole
cylinders from most inner to most outer cylinder are divided into 14 partitions at
calibration in the factory, and the compensation data is measured for
representative cylinder of each partition. This measured value is stored in the SA
area. The compensation value at self-calibration is calculated using the value in
the SA area.

4.5.2 Execution timing of self-calibration

Self-calibration is performed once when power is turned on. After that, the disk
drive does not perform self-calibration until it detects an error.

That is, self-calibration is performed each time one of the following events occur:

•

Power is turned on.

•

The number of retries to write or seek data reaches the specified value.

•

The error rate of data reading, writing, or seeking becomes lower than the
specified value.

C141-E145-02EN 4-9

Theory of Device Operation

4.5.3 Command processing during self-calibration

This enables the host to execute the command without waiting for a long time,
even when the disk drive is performing self-calibration. The command execution
wait time is about maximum 72 ms.

When the error rate of data reading, writing, or seeking becomes lower than the
specified value, self-calibration is performed to maintain disk drive stability.

If the disk drive receives a command execution request from the host while
performing self-calibration, it stops the self-calibration and starts to execute the
command. In other words, if a disk read or write service is necessary, the disk
drive positions the head to the track requested by the host, reads or writes data,
and then restarts calibration after 10 seconds.

If the error rate recovers to a value exceeding the specified value, self-calibration
is not performed.

4.6 Read/write Circuit

The read/write circuit consists of the read/write preamplifier (HDIC), the write
circuit, the read circuit, and the time base generator in the read channel (RDC).
Figure 4.4 is a block diagram of the read/write circuit.

4.6.1 Read/write preamplifier (HDIC)

HDIC equips a read preamplifier and a write current switch, that sets the bias
current to the MR device and the current in writing. Each channel is connected to
each data head, and HDIC switches channel by serial I/O. In the event of any
abnormalities, including a head short-circuit or head open circuit, the write unsafe
signal is generated so that abnormal write does not occur.

4.6.2 Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data
format, and sent to the encoder circuit in the RDC. The NRZ write data is
converted from 48-bit data to 50-bit data by the encoder circuit then sent to the
HDIC, and the data is written onto the media.

(1) 48/50 RLL MEEPRML

This device converts data using the 48/50 RLL (Run Length Limited) algorithm.

(2) Write precompensation

Write precompensation compensates, during a write process, for write non­linearity generated at reading.

4-10 C141-E145-02EN

4.6 Read/write Circuit

HDIC

WDX/WDY RDX/RDY

RDC

Write
PreCompen­sation

SD SC

Serial I/O

Registers

Digital
PLL

SE

Flash
Digitizer

MEEPR
Viterbi
Detect

16/17
ENDEC

AGC
Amplifier

Programmable
Filter

ServoPulse
Detector

WTGATE REFCLK

Figure 4.5 Read/write circuit block diagram

RDGATE

DATA
[7:0]

Position
A/B/C/D
(to reg)

RWCLK

SRV_CLK

SRV_OUT[1:0]

C141-E145-02EN 4-11

Theory of Device Operation

4.6.3 Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control
(AGC) circuit. Then the output is converted into the sampled read data pulse by
the programmable filter circuit and the flash digitizer circuit. This clock signal is
converted into the NRZ data by the ENDEC circuit based on the read data
maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the
HDC.

(1) AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value
even when the input amplitude level fluctuates. The AGC amplifier output is
maintained at a constant level even when the head output fluctuates due to the
head characteristics or outer/inner head positions.

(2) Programmable filter circuit

The programmable filter circuit has a low-pass filter function that eliminates
unnecessary high frequency noise component and a high frequency boost-up
function that equalizes the waveform of the read signal.

-3 dB

Cut-off frequency of the low-pass filter and boost-up gain are controlled from the
register in read channel by an instruction of the serial data signal from MPU
(M5). The MPU optimizes the cut-off frequency and boost-up gain according to
the transfer frequency of each zone.

Figure 4.6 shows the frequency characteristic sample of the programmable filter.

Figure 4.6 Frequency characteristic of programmable filter

4-12 C141-E145-02EN

(3) Flash digitizer circuit

This circuit is 10-tap sampled analog transversal filter circuit that cosine­equalizes the head read signal to the Modified Extended Partial Response
(MEEPR) waveform.

(4) Viterbi detection circuit

The sample hold waveform output from the flash digitizer circuit is sent to the
Viterbi detection circuit. The Viterbi detection circuit demodulates data
according to the survivor path sequence.

(5) MEEPRM

This circuit converts the 17-bit read data into the 16-bit NRZ data.

4.6.4 Digital PLL circuit

The drive uses constant density recording to increase total capacity. This is
different from the conventional method of recording data with a fixed data
transfer rate at all data area. In the constant density recording method, data area
is divided into zones by radius and the data transfer rate is set so that the
recording density of the inner cylinder of each zone is nearly constant. The drive
divides data area into 30 zones to set the data transfer rate.

4.6 Read/write Circuit

The MPU transfers the data transfer rate setup data (SD/SC) to the RDC that
includes the Digital PLL circuit to change the data transfer rate.

C141-E145-02EN 4-13

Theory of Device Operation

4.7 Servo Control

The actuator motor and the spindle motor are submitted to servo control. The
actuator motor is controlled for moving and positioning the head to the track
containing the desired data. To turn the disk at a constant velocity, the actuator
motor is controlled according to the servo data that is written on the data side
beforehand.

4.7.1 Servo control circuit

Figure 4.7 is the block diagram of the servo control circuit. The following
describes the functions of the blocks:

(1)

MPU

(2)

Head

Servo
burst
capture

Position Sense

CSR: Current Sense Resister
VCM: Voice Coil Motor

Figure 4.7 Block diagram of servo control circuit

MPU
core

(3)

(5)

DAC

Spindle
motor
control

SVC

(4)

Power
Amp

(6)

Driver

(7)

VCM current

CSR

VCM

Spindle
motor

(1) Microprocessor unit (MPU)

The MPU uses DSP and executes startup of the spindle motor, movement to the
reference cylinder, seek to the specified cylinder, and calibration operations.
Main internal operation of the MPU are shown below.

4-14 C141-E145-02EN

4.7 Servo Control

The major internal operations are listed below.

a. Spindle motor start

Starts the spindle motor and accelerates it to normal speed when power is
applied.

b. Move head to reference cylinder

Drives the VCM to position the head at the any cylinder in the data area. The
logical initial cylinder is at the outermost circumference (cylinder 0).

c. Seek to specified cylinder

Drives the VCM to position the head to the specified cylinder.

d. Calibration

Senses and stores the thermal offset between heads and the mechanical forces
on the actuator, and stores the calibration value.

C141-E145-02EN 4-15

Theory of Device Operation

(2) Servo burst capture circuit

The servo burst capture circuit reproduces signals (position signals) that indicate
the head position from the servo data on the data surface. From the servo area on
the data area surface, via the data head, the burst signal of SERVO A, SERVO B,
SERVO C, and SERVO D is output as shown in Figure 4.9 in subsequent to the
servo mark, gray code that indicates the cylinder position, and index information.
The servo signals do A/D-convert by Fourier-demodulator in the servo burst
capture circuit. At that time the AGC circuit is in hold mode. The A/D converted
data is recognized by the MPU as position information with A-B and C-D
processed.

(3) D/A converter (DAC)

The control program calculates the specified data value (digital value) of the
VCM drive current, and the value is converted from digital-to-analog so that an
analog output voltage is sent to the power amplifier.

(4) Power amplifier

The power amplifier feeds currents, corresponding to the DAC output signal
voltage to the VCM.

(5) Spindle motor control circuit

The spindle motor control circuit controls the sensor-less spindle motor. A
spindle driver IC with a built-in PLL(FLL) circuit that is on a hardware unit
controls the sensor-less spindle motor.

(6) Driver circuit

The driver circuit is a power amplitude circuit that receives signals from the
spindle motor control circuit and feeds currents to the spindle motor.

(7) VCM current sense resistor (CSR)

This resistor controls current at the power amplifier by converting the VCM
current into voltage and feeding back.

4-16 C141-E145-02EN

4.7.2 Data-surface servo format

Figure 4.8 describes the physical layout of the servo frame. The three areas
indicated by (1) to (3) in Figure 4.8 are described below.

(1) Inner guard band

This area is located inside the user area, and the rotational speed of the VCM can
be controlled on this cylinder area for head moving.

(2) Data area

This area is used as the user data area SA area.

(3) Outer guard band

This area is located at outer position of the user data area, and the rotational speed
of the spindle can be controlled on this cylinder area for head moving.

4.7 Servo Control

C141-E145-02EN 4-17

Theory of Device Operation

ÕÖ

Servo frame
(120 servo frames per revolution)

CYLn + 1

W/R Recovery
Servo Mark
Gray Code

IGB

CYLn CYLn – 1 (n: even number)

W/R Recovery
Servo Mark
Gray Code

Data area

expand

W/R Recovery
Servo Mark
Gray Code

Erase Servo A Erase Servo A

Servo B Erase Servo B Erase

Servo C Erase Servo C

Erase Servo D Erase

PAD

Figure 4.8 Physical sector servo configuration on disk surface

OGB

Diameter

direction

Ø
Ø

Circumference

Direction

Erase: DC erase

area

4-18 C141-E145-02EN

4.7.3 Servo frame format

As the servo information, the IDD uses the two-phase servo generated from the
gray code and servo A to D. This servo information is used for positioning
operation of radius direction and position detection of circumstance direction.

The servo frame consists of 6 blocks; write/read recovery, servo mark, gray code,
servo A to D, and PAD. Figure 4.9 shows the servo frame format.

4.7 Servo Control

Figure 4.9 Servo frame format

C141-E145-02EN 4-19

Theory of Device Operation

(1) Write/read recovery

This area is used to absorb the write/read transient and to stabilize the AGC.

(2) Servo mark

This area generates a timing for demodulating the gray code and position­demodulating the servo A to D by detecting the servo mark.

(3) Gray code (including index bit)

This area is used as cylinder address. The data in this area is converted into the
binary data by the gray code demodulation circuit

(4) Servo A, servo B, servo C, servo D

This area is used as position signals between tracks and the IDD control at on­track so that servo A level equals to servo B level.

(5) PAD

This area is used as a gap between servo and data.

4.7.4 Actuator motor control

The voice coil motor (VCM) is controlled by feeding back the servo data recorded
on the data surface. The MPU fetches the position sense data on the servo frame
at a constant interval of sampling time, executes calculation, and updates the
VCM drive current.

The servo control of the actuator includes the operation to move the head to the
reference cylinder, the seek operation to move the head to the target cylinder to
read or write data, and the track-following operation to position the head onto the
target track.

(1) Operation to move the head to the reference cylinder

The MPU moves the head to the reference cylinder when the power is turned.
The reference cylinder is in the data area.

When power is applied the heads are moved from the inner circumference shunt
zone to the normal servo data zone in the following sequence:

a) Micro current is fed to the VCM to press the head against the outer

circumference.
b) The head is loaded on the disk.
c) When the servo mark is detected the head is moved slowly toward the inner

circumference at a constant speed.

4-20 C141-E145-02EN

d) If the head is stopped at the reference cylinder from there. Track following

control starts.

(2) Seek operation

Upon a data read/write request from the host, the MPU confirms the necessity of
access to the disk. If a read/write instruction is issued, the MPU seeks the desired
track.

The MPU feeds the VCM current via the D/A converter and power amplifier to
move the head. The MPU calculates the difference (speed error) between the
specified target position and the current position for each sampling timing during
head moving. The MPU then feeds the VCM drive current by setting the
calculated result into the D/A converter. The calculation is digitally executed by
the firmware. When the head arrives at the target cylinder, the track is followed.

(3) Track following operation

Except during head movement to the reference cylinder and seek operation under
the spindle rotates in steady speed, the MPU does track following control. To
position the head at the center of a track, the DSP drives the VCM by feeding
micro current. For each sampling time, the VCM drive current is determined by
filtering the position difference between the target position and the position
clarified by the detected position sense data. The filtering includes servo
compensation. These are digitally controlled by the firmware.

4.7 Servo Control

4.7.5 Spindle motor control

Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3­phase full/half-wave analog current control circuit is used as the spindle motor
driver (called SVC hereafter). The firmware operates on the MPU manufactured
by Fujitsu. The spindle motor is controlled by sending several signals from the
MPU to the SVC. There are three modes for the spindle control; start mode,
acceleration mode, and stable rotation mode.

(1) Start mode

When power is supplied, the spindle motor is started in the following sequence:

a) After the power is turned on, the MPU sends a signal to the SVC to charge

the charge pump capacitor of the SVC. The charged amount defines the
current that flows in the spindle motor.

b) When the charge pump capacitor is charged enough, the MPU sets the SVC

to the motor start mode. Then, a current (approx. 0.3 A) flows into the
spindle motor.

c) A phase switching signal is generated and the phase of the current flowed in

the motor is changed in the order of (V-phase to U-phase), (W-phase to U­phase), (W-phase to V-phase), (U-phase to V-phase), (U-phase to W-phase),
and (V-phase to W-phase) (after that, repeating this order).

C141-E145-02EN 4-21

Theory of Device Operation

d) During phase switching, the spindle motor starts rotating in low speed, and

generates a counter electromotive force. The SVC detects this counter

electromotive force and reports to the MPU using a PHASE signal for speed

detection.
e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a

specific period, the MPU resets the SVC and starts from the beginning.

When a PHASE signal is sent, the SVC enters the acceleration mode.

(2) Acceleration mode

In this mode, the MPU stops to send the phase switching signal to the SVC. The
SVC starts a phase switching by itself based on the counter electromotive force.
Then, rotation of the spindle motor accelerates. The MPU calculates a rotational
speed of the spindle motor based on the PHASE signal from the SVC, and waits
till the rotational speed reaches 4,200 rpm. When the rotational speed reaches
4,200 rpm, the SVC enters the stable rotation mode.

(3) Stable rotation mode

The SVC calculates a time for one revolution of the spindle motor based on the
PHASE signal. The MPU takes a difference between the current time and a time
for one revolution at 4,200 rpm that the MPU already recognized. Then, the MPU
keeps the rotational speed to 4,200 rpm by charging or discharging the charge
pump for the different time. For example, when the actual rotational speed is
4,000 rpm, the time for one revolution is 15.000 ms. And the time for one
revolution at 4,200 rpm is 14.286 ms. Therefore, the MPU charges the charge
pump for 0.714 ms × k (k: constant value). This makes the flowed current into
the motor higher and the rotational speed up. When the actual rotational speed is
faster than 4,200 rpm, the MPU discharges the pump the other way. This control
(charging/discharging) is performed every 1 revolution.

4-22 C141-E145-02EN

CHAPTER 5 Interface

5.1 Physical Interface

5.2 Logical Interface

5.3 Host Commands

5.4 Command Protocol

5.5 Ultra DMA Feature Set

5.6 Timing

This chapter gives details about the interface, and the interface commands and
timings.

C141-E145-02EN 5-1

Interface

5.1 Physical Interface

5.1.1 Interface signals

Figure 5.1 shows the interface signals.

Host

DATA 0-15: DATA BUS

DMACK-: DMA ACKNOWLEDGE

DMARQ: DMA REQUEST
INTRO: INTERRUPT REQUEST

DIOW-: I/O WRITE
STOP: STOP DURING ULTRA DMA DATA BURSTS

DIOR-:I/O READ
HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS
HSTROBE:DATA STROBE DURING ULTRA DMA DATA OUT BURST

PDIAG-: PASSED DIAGNOSTICS
CBLID-: CABLE TYPE IDENTIFIER
DASP-: DEVICE ACTIVE/SLAVE PRESENT

IORDY:I/O READY
DDMARDY:DMA READY DURING ULTRA DMA DATA OUT BURSTS
DSTROBE: DATA STROBE DURING ULTRA DMA DATA IN BURSTS

IDD

DA 0-2: DEVICE ADDRESS
CS0-: CHIP SELECT 0
CS1-: CHIP SELECT 1

RESET-: RESET
CSEL: CABLE SELECT

MSTR: Master
ENCSEL: ENABLE CSEL

+5V DC: +5 volt

GND: GROUND

Figure 5.1 Interface signals

5-2 C141-E145-02EN

5.1.2 Signal assignment on the connector

Table 5.1 shows the signal assignment on the interface connector.

Table 5.1 Signal assignment on the interface connector

Pin No. Signal Pin No. Signal

5.1 Physical Interface

A
C

E
1
3
5
7

9
11
13
15
17
19
21
23
25

MSTR
PUS­(KEY)
RESET–
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
GND
DMARQ
DIOW-, STOP
DIOR-, HDMRDY,

HSTROBE

B
D

F
2
4
6

8
10
12
14
16
18
20
22
24
26

MSTR/ENCSEL
ENCSEL
(KEY)
GND
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
(KEY)
GND
GND
GND

27

29
31
33
35
37
39
41
43

C141-E145-02EN 5-3

IORDY, DDMARDY,
DSTROBE

DMACK–
INTRQ
DA1
DA0
CS0–
DASP–
+5 VDC
GND

28

30
32
34
36
38
40
42
44

CSEL

GND
reserved (IOCS16-)
PDIAG–, CBLID–
DA2
CS1–
GND
+5 VDC
unused

Interface

[signal] [I/O] [Description]

ENCSEL I This signal is used to set master/slave using the CSEL signal (pin 28).

Pins B and D Open: Sets master/slave using the CSEL signal

is disabled.

Short: Sets master/slave using the CSEL signal

is enabled.

MSTR- I MSTR, I, Master/slave setting

Pin A, B, C, D open: Master setting

Pin A, B Short: Slave setting
PUS- I When pin C is grounded, the drive does not spin up at power on.
RESET- I Reset signal from the host. This signal is low active and is

asserted for a minimum of 25 µs during power on.
DATA 0-15 I/O Sixteen-bit bi-directional data bus between the host and the

device. These signals are used for data transfer
DIOW- I Signal asserted by the host to write to the device register or data

port.
STOP I DIOW- must be negated by the host before starting the Ultra

DMA transfer. The STOP signal must be negated by the host

before data is transferred during the Ultra DMA transfer. During

data transfer in Ultra DMA mode, the assertion of the STOP

signal asserted by the host later indicates that the transfer has been

suspended.
DIOR- I Read strobe signal from the host to read the device register or data

port
HDMARDY- I Flow control signal for Ultra DMA data In transfer (READ DMA

command). This signal is asserted by the host to inform the

device that the host is ready to receive the Ultra DMA data In

transfer. The host can negate the HDMARDY- signal to suspend

the Ultra DMA data In transfer.
HSTROBE I Data Out Strobe signal from the host during Ultra DMA data Out

transfer (WRITE DMA command). Both the rising and falling

edges of the HSTROBE signal latch data from Data 15-0 into the

device. The host can suspend the inversion of the HSTROBE

signal to suspend the Ultra DMA data Out transfer.
INTRQ O Interrupt signal to the host.

This signal is negated in the following cases:

−

assertion of RESET- signal

−

Reset by SRST of the Device Control register

−

Write to the command register by the host

−

Read of the status register by the host

−

Completion of sector data transfer
(without reading the Status register)

The signal output line has a high impedance when no devices are

selected or interruption is disabled.

5-4 C141-E145-02EN

5.1 Physical Interface

[signal] [I/O] [Description]

CS0- I Chip select signal decoded from the host address bus. This signal

is used by the host to select the command block registers.

CS1- I Chip select signal decoded from the host address bus. This signal

is used by the host to select the control block registers.

DA 0-2 I Binary decoded address signals asserted by the host to access task

file registers.
KEY - Key pin for prevention of erroneous connector insertion
PDIAG- I/O This signal is an input mode for the master device and an output

mode for the slave device in a daisy chain configuration. This

signal indicates that the slave device has been completed self

diagnostics.

This signal is pulled up to +5 V through 10 kΩ resistor at each device.
CBLID- I/O This signal is used to detect the type of cable installed in the

system.

This signal is pulled up to +5 V through 10 kΩ resistor at each device.
DASP- I/O This is a time-multiplexed signal that indicates that the device is

active and a slave device is present.

This signal is pulled up to +5 V through 10 kΩ resistor at each device.
IORDY O This signal requests the host system to delay the transfer cycle

when the device is not ready to respond to a data transfer request

from the host system.
DDMARDY

-

O Flow control signal for Ultra DMA data Out transfer (WRITE

DMA command). This signal is asserted by the device to inform

the host that the device is ready to receive the Ultra DMA data

Out transfer. The device can negate the DDMARDY- signal to

suspend the Ultra DMA data Out transfer.
DSTROBE O Data In Strobe signal from the device during Ultra DMA data In

transfer. Both the rising and falling edges of the DSTROBE

signal latch data from Data 15-0 into the host. The device can

suspend the inversion of the DSTROBE signal to suspend the

Ultra DMA data In transfer.
CSEL I This signal to configure the device as a master or a slave device.

−

When CSEL signal is grounded, the IDD is a master device.

−

When CSEL signal is open, the IDD is a slave device.

This signal is pulled up with 240 kΩ resistor at each device.
DMACK- I The host system asserts this signal as a response that the host

system receive data or to indicate that data is valid.

C141-E145-02EN 5-5

Interface

[signal] [I/O] [Description]

DMARQ O This signal is used for DMA transfer between the host system and

the device. The device asserts this signal when the device
completes the preparation of DMA data transfer to the host
system (at reading) or from the host system (at writing).

The direction of data transfer is controlled by the DIOR and
DIOW signals. This signal hand shakes with the DMACK-signal.
In other words, the device negates the DMARQ signal after the
host system asserts the DMACK signal. When there is other data
to be transferred, the device asserts the DMARQ signal again.

When the DMA data transfer is performed, IOCS16-, CS0- and
CS1- signals are not asserted. The DMA data transfer is a 16-bit

data transfer.
+5 VDC I +5 VDC power supplying to the device.
GND - Grounded signal at each signal wire.

Note:

“I” indicates input signal from the host to the device.

“O” indicates output signal from the device to the host.

“I/O” indicates common output or bi-directional signal between the host
and the device.

5.2 Logical Interface

The device can operate for command execution in either address-specified mode;
cylinder-head-sector (CHS) or Logical block address (LBA) mode. The
IDENTIFY DEVICE information indicates whether the device supports the LBA
mode. When the host system specifies the LBA mode by setting bit 6 in the
Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates
the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder
Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the
start point of LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the
INITIALIZE DEVICE PARAMETER command, the sector LBA address is not
changed.

LBA = [((Cylinder No.) × (Number of head) + (Head No.)) × (Number of
sector/track)] + (Sector No.) − 1

5-6 C141-E145-02EN

5.2.1 I/O registers

Communication between the host system and the device is done through input­output (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to
DA2 from the host system. Table 5.2. shows the coding address and the function
of I/O registers.

5.2 Logical Interface

Table 5.2 I/O registers

DA0DA1DA2CS1–CS0–

I/O registers

Read operation Write operation

Command block registers

LHLLLData Data X’1F0’
L H L L H Error Register Features X’1F1’
L H L H L Sector Count Sector Count X’1F2’
L H L H H Sector Number Sector Number X’1F3’
L H H L L Cylinder Low Cylinder Low X’1F4’
L H H L H Cylinder High Cylinder High X’1F5’
L H H H L Device/Head Device/Head X’1F6’
L H H H H Status Command X’1F7’
L L X X X (Invalid) (Invalid) —

Control block registers

H L H H L Alternate Status Device Control X’3F6’
HLHHH — — X’3F7’

Host I/O

address

Notes:

1. The Data register for read or write operation can be accessed by 16 bit data
bus (DATA0 to DATA15).

2. The registers for read or write operation other than the Data registers can be
accessed by 8 bit data bus (DATA0 to DATA7).

3. When reading the Drive Address register, bit 7 is high-impedance state.

4. H indicates signal level High and L indicates signal level Low.

There are two methods for specifying the LBA mode. One method is to
specify the LBA mode with 28-bit address information, and the other is to
specify it with 48-bit address information (command of EXT system). If
the LBA mode is specified with 28-bit address information, the

C141-E145-02EN 5-7

Interface

Device/Head, Cylinder High, Cylinder Low, Sector Number registers
indicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0,
respectively.

If the LBA mode is specified with 48-bit address information, the Cylinder
High, Cylinder Low, Sector Number registers are set twice. In the first
time, the registers indicate LBA bits 47 to 40, bits 39 to 32, and bits 31 to
24, respectively. In the second time, the registers indicate LBA bits 23 to
16, bits 15 to 8, and bits 7 to 0, respectively.

5.2.2 Command block registers

(1) Data register (X’1F0’)

The Data register is a 16-bit register for data block transfer between the device
and the host system. Data transfer mode is PIO or DMA mode.

(2) Error register (X’1F1’)

The Error register indicates the status of the command executed by the device.
The contents of this register are valid when the ERR bit of the Status register is 1.

This register contains a diagnostic code after power is turned on, a reset , or the
EXECUTIVE DEVICE DIAGNOSTIC command is executed.

[Status at the completion of command execution other than diagnostic command]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ICRC UNC X IDNF X ABRT TK0 NF AMNF

X: Unused

- Bit 7: Interface CRC Error (ICRC). This bit indicates that a CRC error
occurred during Ultra DMA transfer.

- Bit 6: Uncorrectable Data Error (UNC). This bit indicates that an
uncorrectable data error has been encountered.

- Bit 5: Unused

- Bit 4: ID Not Found (IDNF). This bit indicates an error except for bad
sector, uncorrectable error and SB not found.

- Bit 3: Unused

- Bit 2: Aborted Command (ABRT). This bit indicates that the requested
command was aborted due to a device status error (e.g. Not Ready,
Write Fault) or the command code was invalid.

5-8 C141-E145-02EN

5.2 Logical Interface

- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not
found during RECALIBRATE command execution.

- Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not
Found error occurred.

[Diagnostic code]

X’01’: No Error Detected.
X’02’: HDC Register Compare Error
X’03’: Data Buffer Compare Error.
X’05’: ROM Sum Check Error.
X’80’: Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master
and slave) configuration. If the slave device fails, the master device
posts X’80’ OR (the diagnostic code) with its own status (X’01’ to
X’05’).

However, when the host system selects the slave device, the diagnostic
code of the slave device is posted.

(3) Features register (X’1F1’)

The Features register provides specific feature to a command. For instance, it is
used with SET FEATURES command to enable or disable caching.

(4) Sector Count register (X’1F2’)

The Sector Count register indicates the number of sectors of data to be transferred
in a read or write operation between the host system and the device. When the
value in this register is X’00’, the sector count is 256. With the EXT system
command, the sector count is 65536 when value of this register is X'00' in the first
setting and X'00' in the second setting.

When this register indicates X’00’ at the completion of the command execution,
this indicates that the command is completed successfully. If the command is not
completed successfully, this register indicates the number of sectors to be
transferred to complete the request from the host system. That is, this register
indicates the number of remaining sectors that the data has not been transferred
due to the error.

The contents of this register has other definition for the following commands;
INITIALIZE DEVICE PARAMETERS, SET FEATURES, IDLE, STANDBY
and SET MULTIPLE MODE.

C141-E145-02EN 5-9

Interface

(5) Sector Number register (X’1F3’)

The contents of this register indicates the starting sector number for the
subsequent command. The sector number should be between X’01’ and [the
number of sectors per track defined by INITIALIZE DEVICE PARAMETERS
command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

Under the LBA mode of the EXT system command, LBA bits 31 to 24 are set in
the first setting, and LBA bits 7 to 0 are set in the second setting.

(6) Cylinder Low register (X’1F4’)

The contents of this register indicates low-order 8 bits of the starting cylinder
address for any disk-access.

At the end of a command, the contents of this register are updated to the current
cylinder number.

Under the LBA mode, this register indicates LBA bits 15 to 8.

Under the LBA mode of the EXT system command, LBA bits 39 to 32 are set in
the first setting, and LBA bits 15 to 8 are set in the second setting.

(7) Cylinder High register (X’1F5’)

The contents of this register indicates high-order 8 bits of the disk-access start
cylinder address.

At the end of a command, the contents of this register are updated to the current
cylinder number. The high-order 8 bits of the cylinder address are set to the
Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

Under the LBA mode of the EXT system command, LBA bits 47 to 40 are set in
the first setting, and LBA bits 23 to 16 are set in the second setting.

5-10 C141-E145-02EN

(8) Device/Head register (X’1F6’)

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents
of this register defines “the number of heads minus 1” (a maximum head No.).

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X L X DEV HS3 HS2 HS1 HS0

- Bit 7: Unused

- Bit 6: L. 0 for CHS mode and 1 for LBA mode.

- Bit 5: Unused

- Bit 4: DEV bit. 0 for the master device and 1 for the slave device.

- Bit 3: HS3 CHS mode head address 3 (2

under the LBA mode of the EXT command.

- Bit 2: HS2 CHS mode head address 2 (2

under the LBA mode of the EXT command.

- Bit 1: HS1 CHS mode head address 1 (2

under the LBA mode of the EXT command.

- Bit 0: HS0 CHS mode head address 0 (2

under the LBA mode of the EXT command.

5.2 Logical Interface

3

). bit 27 for LBA mode. Unused

2

). bit 26 for LBA mode. Unused

1

). bit 25 for LBA mode. Unused

0

). bit 24 for LBA mode. Unused

(9) Status register (X’1F7’)

The contents of this register indicate the status of the device. The contents of this
register are updated at the completion of each command. When the BSY bit is
cleared, other bits in this register should be validated within 400 ns. When the
BSY bit is 1, other bits of this register are invalid. When the host system reads
this register while an interrupt is pending, it is considered to be the Interrupt
Acknowledge (the host system acknowledges the interrupt). Any pending
interrupt is cleared (negating INTRQ signal) whenever this register is read.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSY DRDY DF DSC DRQ 0 0 ERR

C141-E145-02EN 5-11

Interface

- Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is
accessed. Then this bit is cleared when the command is completed.
However, even if a command is being executed, this bit is 0 while data
transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host
system should not write the command block registers. If the host
system reads any command block register when BSY bit is 1, the
contents of the Status register are posted. This bit is set by the device
under following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the

Device Control register, the BSY bit is set. the BSY bit is cleared,
when the reset process is completed.

The BSY bit is set for no longer than 15 seconds after the IDD
accepts reset.

(b) Within 400 ns from the host system starts writing to the

Command register.

(c) Within 5 µs following transfer of 512 bytes data during execution

of the READ SECTOR(S), WRITE SECTOR(S), or WRITE
BUFFER command.

Within 5 µs following transfer of 512 bytes of data and the
appropriate number of ECC bytes during execution of READ
LONG or WRITE LONG command.

- Bit 6: Device Ready (DRDY) bit. This bit indicates that the device is
capable to respond to a command.

The IDD checks its status when it receives a command. If an error is
detected (not ready state), the IDD clears this bit to 0. This is cleared
to 0 at power-on and it is cleared until the rotational speed of the
spindle motor reaches the steady speed.

- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault
(write fault) condition has been detected.

If a write fault is detected during command execution, this bit is
latched and retained until the device accepts the next command or
reset.

- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device
heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is
completed.

- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to
transfer data of word unit or byte unit between the host system and the
device.

- Bit 2: Always 0.

5-12 C141-E145-02EN

- Bit 1: Always 0.

- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the
previous command was being executed. The Error register indicates
the additional information of the cause for the error.

(10) Command register (X’1F7’)

The Command register contains a command code being sent to the device. After
this register is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table
also lists the necessary parameters for each command which are written to certain
registers before the Command register is written.

5.2.3 Control block registers

(1) Alternate Status register (X’3F6’)

5.2 Logical Interface

The Alternate Status register contains the same information as the Status register
of the command block register.

The only difference from the Status register is that a read of this register does not
imply Interrupt Acknowledge and INTRQ signal is not reset.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSY DRDY DF DSC DRQ 0 0 ERR

C141-E145-02EN 5-13

Interface

(2) Device Control register (X’3F6’)

The Device Control register contains device interrupt and software reset.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

HOBXXXXSRSTnIEN0

- Bit 7: HOB is the selector bit that selects higher-order information or lower­order information of the EXT system command.

If HOB = 1, LBA bits 47 to 24 and the higher-order 8 bits of the sector
count are displayed in the task register.

If HOB = 0, LBA bits 23 to 0 and the lower-order 8 bits of the sector
count are displayed in the task register.

- Bit 2: SRST is the host software reset bit. When this bit is set, the device is
held reset state. When two device are daisy chained on the interface,
setting this bit resets both device simultaneously.

The slave device is not required to execute the DASP- handshake.

- Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the
host. When this bit is 0 and the device is selected, an interruption
(INTRQ signal) can be enabled through a tri-state buffer. When this
bit is 1 or the device is not selected, the INTRQ signal is in the high­impedance state.

5.3 Host Commands

The host system issues a command to the device by writing necessary parameters
in related registers in the command block and writing a command code in the
Command register.

The device can accept the command when the BSY bit is 0 (the device is not in
the busy status).

The host system can halt the uncompleted command execution only at execution
of hardware or software reset.

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data
transfer) and the host system writes to the command register, the correct device
operation is not guaranteed.

5.3.1 Command code and parameters

Table 5.3 lists the supported commands, command code and the registers that
needed parameters are written.

5-14 C141-E145-02EN

5.3 Host Commands

Table 5.3 Command code and parameters ( 1 of 3)

Command code (Bit) Parameters used

Command name

76543210FRSCSNCYDH

READ SECTOR(S) 0 0 1 0 0 0 0 R N Y Y Y Y
READ MULTIPLE 1 1 0 0 0 1 0 0 N Y Y Y Y
READ DMA 1 1 0 0 1 0 0 R N Y Y Y Y
READ VERIFY SECTOR(S) 0 1 0 0 0 0 0 R N Y Y Y Y
WRITE MULTIPLE 1 1 0 0 0 1 0 1 N Y Y Y Y
WRITE DMA 1 1 0 0 1 0 1 R N Y Y Y Y
WRITE VERIFY 00111100NYYYY
WRITE SECTOR(S) 0 0 1 1 0 0 0 R N Y Y Y Y
RECALIBRATE 0 0 0 1 X X X X N N N N D
SEEK 0 1 11XXXXNNYYY
INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y
IDENTIFY DEVICE 11101100NNNND
IDENTIFY DEVICE DMA 1 1 1 0 1 1 0 0 N N N N D
SET FEATURES 11101111YN*NND
SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D
SET MAX 1 1 1 1 1 0 0 1 N Y Y Y Y
READ NATIVE MAX ADDRESS 1 1 1 1 1 0 0 0 N N N N D
EXECUTE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 0 N N N N D*
READ LONG 0010001RNYYYY
WRITE LONG 0011001RNYYYY
READ BUFFER 1 1 1 0 0 1 0 0 N N N N D
WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D
IDLE 1101011000101111NYNND

C141-E145-02EN 5-15

Interface

Table 5.3 Command code and parameters ( 2 of 3)

Command code (Bit) Parameters used

Command name

76543210FRSCSNCYDH

IDLE IMMEDIATE 1101011000100011NNNND

STANDBY 1101011000101100NYNND

STANDBY IMMEDIATE 1101011000100000NNNND

SLEEP 1101011010010110NNNND

CHECK POWER MODE 1101011010010001NNNND

SMART 10110000YYYYD
SECURITY DISABLE PASSWORD 1 1 1 1 0 1 1 0 N N N N D
SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D
SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D
SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D
SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D
SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D
FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D
DEVICE CONFIGURATION 1 0 1 1 0 0 0 1 N N N N D
SET MAX ADDRESS 1 1 1 1 1 0 0 1 N Y Y Y Y
SET MAX SET PASSWORD 1 1 1 1 1 0 0 1 Y N N N Y
SET MAX LOCK 11111001YNNNY
SET MAX UNLOCK 1 1 1 1 1 0 0 1 Y N N N Y
SET MAX FREEZE LOCK 1 1 1 1 1 0 0 1 Y N N N Y
READ NATIVE MAX ADDRESS 1 1 1 1 1 0 0 0 N N N N D
IDENTIFY COMPONENT 11010000NNNYD
DEVICE CONFIGURATION

RESTORE
DEVICE CONFIGURATION

FREEZE LOCK

5-16 C141-E145-02EN

10110001YNNND

10110001YNNND

Table 5.3 Command code and parameters ( 3 of 3)

Command name

5.3 Host Commands

Command code (Bit) Parameters used

76543210FRSCSNCYDH

DEVICE CONFIGURATION

10110001YNNND

IDENTIFY
DEVICE CONFIGURATION SET 1 0 1 1 0 0 0 1 Y N N N D
READ NATIVE MAX ADDRESS

11111000NNNND

EXT
SET MAX ADDRESS EXT 1 1 1 1 1 0 0 1 N Y Y Y Y
FLUSH CACHE EXT 1 1 1 0 0 1 1 1 N N N N D
WRITE DMA EXT 0 0 1 1 0 1 0 1 N Y Y Y D
READ DMA EXT 0 0 1 0 0 1 0 1 N Y Y Y D
WRITE MULTIPLE EXT 0 0 1 1 1 0 0 1 N Y Y Y D
READ MULTIPLE EXT 0 0 1 0 1 0 0 1 N Y Y Y D
WRITE SECTOR (S) EXT 0 0 1 1 0 1 0 0 N Y Y Y D
READ SECTOR (S) EXT 0 0 1 0 0 1 0 0 N Y Y Y D

Notes:
FR: Features Register
CY: Cylinder Registers
SC: Sector Count Register
DH: Drive/Head Register
SN: Sector Number Register
R: Retry at error

1 = Without retry

0 = With retry
Y: Necessary to set parameters
Y*: Necessary to set parameters under the LBA mode.
N: Not necessary to set parameters (The parameter is ignored if it is set.)
N*: May set parameters
D: The device parameter is valid, and the head parameter is ignored.

C141-E145-02EN 5-17

Interface

D*: The command is addressed to the master device, but both the master device

and the slave device execute it.

X: Do not care

5.3.2 Command descriptions

The contents of the I/O registers to be necessary for issuing a command and the
example indication of the I/O registers at command completion are shown as
following in this subsection.

Example: READ SECTOR(S)

At command issuance (I/O registers setting contents)

Bit 76543210

1F7H(CM)00100000
1F6H(DH) x L x DV Head No. / LBA [MSB]

1F5H(CH) Start cylinder address [MSB] / LBA
1F4H(CL) Start cylinder address [LSB] / LBA
1F3H(SN) Start sector No. / LBA [LSB]

1F2H(SC) Transfer sector count
1F1H(FR) xx

At command completion (I/O registers contents to be read)

Bit 76543210

1F7H(ST) Status information

1F6H(DH) x L x DV Head No. / LBA [MSB]

1F5H(CH) End cylinder address [MSB] / LBA
1F4H(CL) End cylinder address [LSB] / LBA
1F3H(SN) End sector No. / LBA [LSB]

1F2H(SC) X’00’

1F1H(ER) Error information

5-18 C141-E145-02EN

5.3 Host Commands

CM: Command register FR: Features register

DH: Device/Head register ST: Status register

CH: Cylinder High register ER: Error register

CL: Cylinder Low register L: LBA (logical block address) setting bit

SN: Sector Number register DV: Device address. bit

SC: Sector Count register x, xx: Do not care (no necessary to set)

Note:

1. When the L bit is specified to 1, the lower 4 bits of the DH register and all

bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH

register are the MSB (most significant bit) and bits of the SN register are

the LSB (least significant bit).

2. At error occurrence, the SC register indicates the remaining sector count of data

transfer.

3. In the table indicating I/O registers contents in this subsection, bit indication is

omitted.

(1) READ SECTOR(S) (X’20’ or X’21’)

This command reads data of sectors specified in the Sector Count register from
the address specified in the Device/Head, Cylinder High, Cylinder Low and
Sector Number registers. Number of sectors can be specified from 1 to 256
sectors. To specify 256 sectors reading, ‘00’ is specified. For the DRQ, INTRQ,
and BSY protocols related to data transfer, see Subsection 5.4.1.

If the head is not on the track specified by the host, the device performs an
implied seek. After the head reaches to the specified track, the device reads the
target sector.

If an error occurs, retry reads are attempted to read the target sector before
reporting an error, irrespective of the R bit setting.

The DRQ bit of the Status register is always set prior to the data transfer
regardless of an error condition.

Upon the completion of the command execution, command block registers
contain the cylinder, head, and sector addresses (in the CHS mode) or logical
block address (in the LBA mode) of the last sector read.

If an unrecoverable error occurs in a sector, the read operation is terminated at the
sector where the error occurred. Command block registers contain the cylinder, the
head, and the sector addresses of the sector (in the CHS mode) or the logical
block address (in the LBA mode) where the error occurred, and remaining
number of sectors of which data was not transferred.

C141-E145-02EN 5-19

Interface

At command issuance (I/O registers setting contents)

1F7H(CM)0010000R
1F6H(DH) x L x DV Start head No. / LBA

[MSB]

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

(R: Retry)

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH) x L x DV End head No. / LBA [MSB]
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(2) READ MULTIPLE (X’C4’)

The READ MULTIPLE Command performs the same as the READ SECTOR(S)

Command except that when the device is ready to transfer data for a block of

sectors, and enters the interrupt pending state only before the data transfer for the

first sector of the block sectors. In the READ MULTIPLE command operation,

the DRQ bit of the Status register is set only at the start of the data block, and is

not set on each sector.

The number of sectors per block is defined by a successful SET MULTIPLE

MODE Command. The SET MULTIPLE MODE command should be executed

prior to the READ MULTIPLE command.

If the number of requested sectors is not divided evenly (having the same number

of sectors [block count]), as many full blocks as possible are transferred, then a

5-20 C141-E145-02EN

5.3 Host Commands

final partial block is transferred. The number of sectors in the partial block to be
transferred is n where n = remainder of (“number of sectors”/”block count”).

If the READ MULTIPLE command is issued before the SET MULTIPLE MODE
command is executed or when the READ MULTIPLE command is disabled, the
device rejects the READ MULTIPLE command with an ABORTED COMMAND
error.

Figure 5.2 shows an example of the execution of the READ MULTIPLE
command.

•

Block count specified by SET MULTIPLE MODE command = 4 (number of
sectors in a block)

•

READ MULTIPLE command specifies;

Number of requested sectors = 9 (Sector Count register = 9)

Figure 5.2 Execution example of READ MULTIPLE command

At command issuance (I/O registers setting contents)

1F7H(CM)11000100
1F6H(DH) x L x DV Start head No. / LBA

[MSB]

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

C141-E145-02EN 5-21

Interface

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH) x L x DV End head No. / LBA [MSB]
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]

(*1)

00
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors for which data was not transferred is set in this register.

(3) READ DMA (X’C8’ or X’C9’)

This command operates similarly to the READ SECTOR(S) command except for

following events.

•

The data transfer starts at the timing of DMARQ signal assertion.

•

The device controls the assertion or negation timing of the DMARQ signal.

•

The device posts a status as the result of command execution only once at
completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command

execution cannot be continued is detected, the data transfer is stopped without

transferring data of sectors after the erred sector. The device generates an

interrupt using the INTRQ signal and posts a status to the host system. The

format of the error information is the same as the READ SECTOR(S) command.

In LBA mode

The logical block address is specified using the start head No., start cylinder No.,

and first sector No. fields. At command completion, the logical block address of

the last sector and remaining number of sectors of which data was not transferred,

like in the CHS mode, are set.

The host system can select the DMA transfer mode by using the SET FEATURES

command.

•

Multiword DMA transfer mode 0 to 2

•

Ultra DMA transfer mode 0 to 5

5-22 C141-E145-02EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7H(CM)1100100R
1F6H(DH) x L x DV Start head No. / LBA

[MSB]

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH) x L x DV End head No. / LBA [MSB]
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(4) READ VERIFY SECTOR(S) (X’40’ or X’41’)

This command operates similarly to the READ SECTOR(S) command except that

the data is not transferred to the host system.

After all requested sectors are verified, the device clears the BSY bit of the Status

register and generates an interrupt. Upon the completion of the command

execution, the command block registers contain the cylinder, head, and sector

number of the last sector verified.

If an unrecoverable error occurs, the verify operation is terminated at the sector

where the error occurred. The command block registers contain the cylinder, the

head, and the sector addresses (in the CHS mode) or the logical block address (in

the LBA mode) of the sector where the error occurred. The Sector Count register

indicates the number of sectors that have not been verified.

C141-E145-02EN 5-23

Interface

At command issuance (I/O registers setting contents)

1F7H(CM)0100000 R
1F6H(DH) x L x DV Start head No. / LBA [MSB]

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH) x L x DV End head No. / LBA [MSB]

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(5) WRITE SECTOR(S) (X’30’ or X’31’)

This command writes data of sectors from the address specified in the
Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the
address specified in the Sector Count register. Number of sectors can be specified
from 1 to 256 sectors. A sector count of 0 requests 256 sectors. Data transfer
begins at the sector specified in the Sector Number register. For the DRQ,
INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.2.

If the head is not on the track specified by the host, the device performs an
implied seek. After the head reaches to the specified track, the device writes the
target sector.

If an error occurs when writing to the target sector, retries are attempted
irrespectively of the R bit setting.

The data stored in the buffer, and CRC code and ECC bytes are written to the data
field of the corresponding sector(s). Upon the completion of the command
execution, the command block registers contain the cylinder, head, and sector
addresses of the last sector written.

5-24 C141-E145-02EN

5.3 Host Commands

If an error occurs during multiple sector write operation, the write operation is

terminated at the sector where the error occurred. Command block registers

contain the cylinder, the head, the sector addresses (in the CHS mode) or the

logical block address (in the LBA mode) of the sector where the error occurred.

At command issuance (I/O registers setting contents)

1F7H(CM)0011000R
1F6H(DH) x L x DV Start head No. / LBA

[MSB]

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

At command completion (I/O registers contents to be read)

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

1F7H(ST) Status information
1F6H(DH) x L x DV End head No. / LBA [MSB]
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

C141-E145-02EN 5-25

Interface

(6) WRITE MULTIPLE (X’C5’)

This command is similar to the WRITE SECTOR(S) command. The device does
not generate interrupts (assertion of the INTRQ) signal) on each sector but on the
transfer of a block which contains the number of sectors for which the number is
defined by the SET MULTIPLE MODE command. The DRQ bit of the Status
register is required to set only at the start of the data block, not on each sector.

The number of sectors per block is defined by a successful SET MULTIPLE
MODE command. The SET MULTIPLE MODE command should be executed
prior to the WRITE MULTIPLE command.

If the number of requested sectors is not divided evenly (having the same number
of sectors [block count]), as many full blocks as possible are transferred, then a
final partial block is transferred. The number of sectors in the partial block to be
transferred is n where n = remainder of (“number of sectors”/”block count”).

If the WRITE MULTIPLE command is issued before the SET MULTIPLE
MODE command is executed or when WRITE MULTIPLE command is disabled,
the device rejects the WRITE MULTIPLE command with an ABORTED
COMMAND error.

Disk errors encountered during execution of the WRITE MULTIPLE command are
posted after attempting to write the block or the partial block that was transferred.
Write operation ends at the sector where the error was encountered even if the sector is
in the middle of a block. If an error occurs, the subsequent block shall not be
transferred. Interrupts are generated when the DRQ bit of the Status register is set at
the beginning of each block or partial block.

The contents of the command block registers related to addresses after the transfer
of a data block containing an erred sector are undefined. To obtain a valid error
information, the host should retry data transfer as an individual request.

5-26 C141-E145-02EN