FUJITSU MB98D81123, MB98D81223-15 DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-30337-2E

FLASH MEMORY CARD

3V-ONLY FLASH MINIATURE CARD

MB98D81123(2MB)/81223(4MB)-15

2M/4M-BYTE 3 V-ONLY FLASH MINIATURE CARD

The Fujitsu Flash Miniature cards conform to “Miniature Card Speciﬁcation” pubulished by MCIF; Miniature Card Implementers Forum.

The Fujitsu Flash Miniature cards are small form factor Flash memory cards targeted various markets; digital photography, audio recording, hand held PCs and other small portable equipments. Miniature cards’ high performance, small size (38 mm × 33 mm × 3.5 mm), low cost and simple interface are ideal f or portable applications that require high speed ﬂash disk drives or eXecute In Place (XIP).

The Flash Miniature cards are 5 V -only oper ational and allow the users to use as ×8 or ×16 organization on low power at high speed.

• Small size: 33.0 mm (length) × 38.0 mm (width) × 3.5 mm (thickness)

• +3.3 V power supply program and erase

• Command control for Automated Program/Automated Erase operation

• Erase Suspend Read/Program Capability

• 128 KB Sector Erase (at ×16 mode)

• Any Combination of Sectors Erase and Full Chip Erase

• Detection of completion of program/erase operation with Data# Polling or Toggle bit.

• Ready/Busy Output with BUSY#

• Reset Function with RESET# pin

• Write protect function with WP switch

• Low VCC Write Inhibit

• AIS (Attribute Information Structure) is available from the address “0000H” of Lower Byte.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric ﬁelds. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

■

MB98D81123/81223-15

PACKAGE

3 V - ONLY FLASH MINIATURE CARD

(CRD-60P-M02)

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DESCRIPTION

DIFFERENCES

MB98D81123 MB98D81223

Density 2 MB 4 MB Memory Device 8 M bit 8 M bit Quantity 2 4 Read 1 B unit Program 1 B unit Chip Erase 1 MB unit 1 MB unit Sector Erase 64 KB unit Number of Sectors 32 64 Erase Suspend Read Yes Yes Erase Suspend Program Yes Yes Address A0 to A19 A0 to A20 RESET# Yes Yes BUSY# Yes Yes

← ←

←

■

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MB98D81123/81223-15

PAD ASSIGNMENTS

Pad No Symbol Pad No Symbol Pad No Symbol Pad No Symbol

1A1816 N.C. 31 A 2A1617 N.C. 32 A 3A

4 N.C. 19 D 5 CEH# 20 D 6A1121 D 7A 8A

9A 10 A 11 A 12 A 13 A

18 OE# 33 A

34 A 35 A 36 RESET# 51 RFU 37 A 38 VS1# 53 VS2# 39 A 40 N.C. 55 D 41 A

22 D 23 D 24 D 25 D 26 D

27 N.C. 42 CEL# 57 D 28 D

43 A

46 CD# 47 N.C. 48 BUSY# 49 WE# 50 D

52 D

54 D

56 D

58 D 14 N.C. 29 N.C. 44 N.C. 59 N.C. 15 N.C. 30 N.C. 45 N.C. 60 A20 *

EX 1 V

EX 2 GND EX 3 CINS#

* :A20 is “N.C.” for MB98D81123.

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MB98D81123/81223-15

PAD DESCRIPTIONS

Symbol I/O Pad Name Symbol I/O Pad Name

A0 to A D0 to D CEL# I Card Enable for Lower Byte VS1#, VS2# O Voltage Sense CEH# I Card Enable for Upper Byte N.C. — Non Connection OE# I Output Enable V WE# I Write Enable GND — Ground RESET# I Hardware Reset CINS# O Card Insertion

* :Take notice that those pads are connected internally.

I Address Input BUSY# O Ready/Busy

I/O Data Input/Output CD# O Card Detect *

— Power Supply

PAD LOCATIONS

Fig. 1 — BOTTOM VIEW

EX 1 EX 3 EX 2

V oltage K e y: See “UNIQUE FEATURES”.

Voltage Key

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BLOCK DIAGRAM

MB98D81123

MB98D81123/81223-15

Fig. 2.1 — BLOCK DIAGRAM

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VCC

GND

Address

RESET#

CEL#

CEH#

OE#

D0 to D7

VCC

Internal circuit

VCC

100K

RESET WE OE CE

Even Flash Memory

8M bit

× 1

Address

I/O

R/B

D8 to D15

WE#

VS1# VS2#

BUSY#

CINS#

CD#

N.C.

VCC

100K

Write Protect Switch

N.C.

VCC

10K

RESET WE OE CE

Odd Flash Memory

8M bit × 1

Address

I/O

R/B

MB98D81123/81223-15

MB98D81223

Fig. 2.2 — BLOCK DIAGRAM

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VCC

GND

Address

RESET#

CEL#

CEH#

OE#

D0 to D7

A20

VCC

Internal circuit

A /G1

Decoder

/G2

100K

VCC

100K

RESET WE OE CE

Address

I/O

R/B

Even Flash Memory

8M bit x 2

D8 to D15

WE#

VS1# VS2#

BUSY#

CINS#

CD#

N.C.

VCC

100K

Write Protect Switch

N.C.

VCC

10K

RESET WE OE CE

Address

I/O

R/B

Odd Flash Memory

8M bit x 2

■

CHIP AND SECTOR DECODING

ERASE SECTOR DECODING TABLE

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MB98D81123/81223-15

Sector Address (SA)

Sector 15 1111 Sector 14 1110 Sector 13 1101

•

Total 16 sectors

per 1 chip

•

Sector 2 0010 Sector 1 0001 Sector 0 0000

■

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MB98D81123/81223-15

CHIP CONFIGURATION

The miniature cards use 2 or 4 pcs of Flash Memory.

• 2 pcs of Flash Memory are operated simultaneously at 16 bit mode and even number of chip is applied to

lower byte and odd number of chip is applied to upper byte. At ×8 bit mode, even address and odd address are selected with CEL# and CEH#.

× 16 bit mode

CEL# = “L”, CEH# = “L”

: :

Odd Number of Chip + Even Number of Chip

• • • • • • • • • • • • • • D0

D15

× 8 bit mode

CEL# = “H”, CEH# = “L”

: :

odd Number of Chip

003h

CEL# = “L”, CEH# = “H”

even Number of Chip

003h

002h

001h

000h

: :

003h

odd Number of Chip

D15

• • • • D8

002h

001h

000h

even Number of Chip

• • • • • D0

002h

001h

000h

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MB98D81123/81223-15

■ FUNCTION DESCRIPTIONS

1. Read Mode

The data in the common can be read with “OE#=VIL” and “WE#=VIH”. The address is selected with A0-A20. And CEL# and CEH# select output mode.

2. Standby Mode

– CEL# and CEH# at “VIH” place the card in Standb y mode. D0-D15 are placed in a high-Z state independent

of the status “OE#” and “WE#”.

3. Output Disable Mode

– The outputs are disabled with OE# and WE# at “VIH”. D0-D15 are placed in high-Z state.

4. Write Mode

1) Common Memory Write

– The card is in Write mode with “OE#=VIH” and “WE# and CE#=VIL”. – Commands can be written at the Write mode. – Two types of the Write mode, “WE# control” and “CE# control” are available.

5. Command Deﬁnitions

– User can select the card operation by writing the speciﬁc address and data sequences into the command

register. If incollect address and data are written or improper sequence is done, the card is reseted to read mode. See “COMMAND DEFINISION TABLE”.

6. Automated Program Capability

– Programming operation can switch the data from “1” to “0”. – The data is programmed on a byte-by-byte or word-by-word basis. – The card will automatically provide adequate internally generated programming pulses and verify the pro-

grammed cell margin by writing four bus cycle operation. The card returns to Common Memory Read mode automatically after the programming is completed.

– Addresses are latched at falling edge of WE# or CE# and data is latched at rising edge of WE# or CE#. The

fourth rising edge of WE# or CE# on the command write cycle begins programming operation.

– We can check whether a b yte (word) programming operation is completed successfully b y sequence ﬂug with

BUSY#, Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.

– Any commands written to the chip during programming operation will be ignored.

7. Automated Chip Erase Capability

– We can ex ecute chip erase operation by 6 bus cycle operation. Chip erase does not require the user to program

the chip prior to erase. Upon executing the Erase command sequence the chip automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required

to provide any controls or timing during these operations. – The card returns to Common Memory Read mode automatically after the chip erasing is completed. – Whether or not chip erase operation is completed successfully can be checked b y sequence ﬂug with BUSY#,

Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”. – Any commands written to the chip during programming operation will be ignored.

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MB98D81123/81223-15

8. Automated Sector Erase Capability

– We can execute the erase operation on any sectors by 6 bus cycle operation. – A time-out of 50 µs (typ.) from the rising edge of the last Sector Erase command will initiate the Sector Erase

command(s). – Multiple sectors in a chip can be erased concurrently . This sequence is follow ed with writes of 30H to addresses

in other sectors desired to be concurrently erased. The time between writes 30H must be less than 50 µs,

otherwise that command will not be accepted. Any command other than Sector Erase or Erase Suspend

during this time-out period will reset the chip to Read mode. The automated sector erase begins after the 50

µs (typ.) time out from the rising edge of WE# pulse for the last Sector Erase command pulse. Whether the

sector erase window is still open can be monitored with D3 and D11. – Sector Erase does not require the user to program the chip prior to erase. The chip automatically programs

“0” to all memory locations in the sector(s) prior to electrical erase. The system is not required to provide any

controls or timing during these operations. – The card returns to Common Memory Read mode automatically after the chip erasing is completed. – Whether or not sector erase operation is completed successfully can be checked by sequence ﬂug with

BUSY#, Data# Polling or Toggle Bit function. The sequence ﬂug must be read from the address of the sector

involved in erase operation. See “WRITE OPERATION STATUS”.

9. Erase Suspend

– Erase Suspend command allows the user to interrupt the sector erase operation and then do data reads or

program from or to a non-busy sector in the chip which has the sector(s) suspended erase. This command

is applicable only during the sector erase operation (including the sector erase time-out period after the sector

erase commands 30H) and will be ignored if written during the chip erase or programming operation. Writing

this command during the time-out will result in immediate termination of the time-out period. The addresses

are “don’t cares” in wrinting the Erase Suspend or Resume commands in the chip. – When the Erase Suspend command is written during a Sector Erase operation, the chip will enter the Erase

Suspend Read mode. User can read the data from other sectors than those in suspention. The read oper ation

from sectors in suspention results D2/D10 toggling. User can prog r am to non-b usy sectors b y writing program

commands. – A read from a sector being erase suspended may result in invalid data.

10. Intelligent Identiﬁer (ID) Read Mode

– Each common memory can execute an Intelligent Identiﬁer operation, initiated by writing Intelligent ID com-

mand (90H). Following the command write, a read cycle from address 00H retrieves the manufacture code,

and a read cycle from address 01H returns the device code as follows. To terminate the operation, it is

necessary to write Read/Reset command.

11. Hardware Reset

– The Card may be reset by driving the RESET# pin to VIL. The RESET# pin must be kept High (VIL) for at

least 500 ns. Any operation in progress will be terminated and the card will be reset to the read mode 20 µs

after the RESET# pin is driven Low. If a hardware reset occurs during a program operation, the data at that

particular location will be indeterminate. – When the RESET# pin is Low and the internal reset is complete, the Card goes to standby mode and cannot

be accessed. Also, note that all the data output pins are High-Z for the duration of the RESET# pulse. Once

the RESET# pin is taken high, the Card requires 500 ns of wake up time until outputs are v alid for read access. – If hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be

used.

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MB98D81123/81223-15

12. Data Protection

– The card has WP (Write Protect) switch for write lockout. – To avoid initiation of a write cycle during V

less than 3.2 V. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are

disabled.

Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC

level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to

prevent unintentional writes when VCC is above 3.2 V. – If VCC would be less than VLKO during program/erase operation, the operation will stop. And after that, the

operation will not resume even if VCC returns recommended voltage le vel. Therefore , program command must

be written again because the data on the address interrupted program operation is invalid. And regarding

interrupting erase operation, there is possibility that the erasing sector(s) cannot be used. – Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.

CC power-up and power-down, a write cycle is locked out for VCC

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MB98D81123/81223-15

■ FUNCTION TRUTH T ABLE

Data Input/Output

Mode RESET# CEH# CEL# OE# WE#

Hardware Reset L X X X X P or NP High-Z High-Z

WPSW *

D8 to D15 D0 to D7

Standby

Read (×8 bit)

Read (×16 bit) L L DOUT DOUT

Write (×8 bit)

Write (×16 bit) L L DIN DIN

Output Disable

H : “H” level, L : “L” level , X : “H” or “L”

Note: *1. WPSW = Write Protect Switch, NP = NON-PROTECT, P = PROTECT

H H X X P or NP High-Z High-Z HL L H DOUT High-Z

HL L H DIN High-Z

HL L H High-Z High-Z L L High-Z High-Z

L H P or NP

High-Z DOUT

High-Z DIN

High-Z High-Z

■ COMMAND DEFINITION TABLE

Command Table for 8-bit Mode

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MB98D81123/81223-15

Command

Read/Reset 1 2

Read/Reset 2 4

Read Intelligent ID Codes

Byte Program 4

Sector Erase 6

Chip Erase 6

Sector Erase Suspend

Bus

Cycle

1st Bus

Write Cycle

Write Read

CA F0H RA RD

Write Write Write Read

CA AAH CA 55H CA F0H RA RD

Write Write Write Read

CA AAH CA 55H CA 90H IA ID

Write Write Write Write

CA AAH CA 55H CA A0H PA PD

Write Write Write Write Write Write

CA AAH CA 55H CA 80H CA AAH CA 55H SA 30H

Write Write Write Write Write Write

CA AAH CA 55H CA 80H CA AAH CA 55H CA 10H

Write

CA B0H

2nd Bus

Write/Read

Cycle

3rd Bus

Write Cycle

4th Bus

Write/Read

Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Sector Erase Resume

Note: CA: Chip Address. (address in chip selected by A20 for MB98D81223)

SA: Sector Address (address in 64 KB selected by A16, A17, A18, A19 and A20) PA: Program Address (address to be programmed) RA: Read Address (address to be read) IA: Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)

PD: Programming data RD: Read data ID: Intelligent Identiﬁer (ID) Code

Write

CA 30H

MB98D81123/81223-15

Command Table for 16-bit Mode

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Command

Read/Reset 1 2

Read/Reset 2 4

Read Intelligent ID Codes

Byte Program 4

Sector Erase 6

Chip Erase 6

Sector Erase Suspend

Bus

Cycle

1st Bus

Write Cycle

Write Read

CA F0F0H RA RD

Write Write Write Read

CA AAAAH CA 5555H CA F0F0H RA RD

Write Write Write Read

CA AAAAH CA 5555H CA 9090H IA ID

Write Write Write Write

CA AAAAH CA 5555H CA A0A0H PA PD

Write Write Write Write Write Write

CA AAAAH CA 5555H CA 8080H CA AAAAH CA 5555H SA 3030H

Write Write Write Write Write Write

CA AAAAH CA 5555H CA 8080H CA AAAAH CA 5555H CA 1010H

Write

CA B0B0H

2nd Bus

Write/Read

Cycle

3rd Bus

Write Cycle

4th Bus

Write/Read

Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Sector Erase Resume

Note: CA: Chip Address. (address in chip selected by A20 for MB98D81223)

SA: Sector Address (address in 128 KB selected by A16, A17, A18, A19 and A20) PA: Program Address (address to be programmed) RA: Read Address (address to be read) IA: Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)

PD: Programming data RD: Read data ID: Intelligent Identiﬁer (ID) Code

Write

CA 3030H

■ WRITE OPERATION STATUS

Hardware Sequence Flag Table

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MB98D81123/81223-15

Status D

Programming D

7, D15 D6, D14 D5, D13 D3, D11 D2, D10 BUSY#

7#, D15# Toggle 0010

Erasing 0 Toggle 0 1 Toggle 0

In Progress

Erase Suspend Read

Erase Suspend Program

(1)1100

Toggle *

(2) Data Data Data Data Data 1

7#, D15#

Toggle *

1, *3

Programming D7#, D15# Toggle 1010

Exceeded Time Limits

Erasing 0 Toggle 1 1 N/A 0 Erase Suspend

Program

D7#, D15# Toggle 1 0 N/A 0

(1): Erase Suspended Sector (2): Non-Erase Suspended Sector

Notes: *1. Performing successive read operations from the erase-suspended sector will cause D

*2. Performing successive read operations from any address will cause D6, D14 to toggle. *3. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic ‘1’ at the D2, D10 bit. However, successive reads from the erase-suspended sector will cause D2, D10 to toggle.

D7, D15 (Data# Polling)

2, D10 to toggle.

The card features Data# Polling as a method to indicate to the host that the Program/Erase Operation are in progress or completed. During the program operation an attempt to read the prog ram address will produce the compliment of the data last written to D7/D15. Upon completion of the progr am operation, an attempt to read the program address will produce the true data last written to D7/D15. During the erase operation, an attempt to read the program address will produce a “0” at the D7/D15 output. Upon completion of the erase operation an attempt to read the device will produce a “1” at the D7/D15 output. For Chip Erase, the Data# Polling is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. F or sector erase, the Data# Polling is valid after the last rising edge of the sector erase WE# pulse. Even if the device has completed the operation and D7/D15 has a valid data, the data outputs on D0 to D6/D8 to D14 may be still invalid. The valid data on D0 to D7/D8 to D15 will be read on the successive read attempts.

The Data# Polling feature is only active during the programming operation, erase operation, sector erase timeout, Erase Suspend Read mode and Erase Supend Program mode.

D6, D14 (Toggle Bit I)

The card also features the “Toggle Bit” as a method to indicate to the host system that the Program/Erase Operation are in progress or completed.

During an Program or Erase cycle, successive attempts to read (OE# or CE# toggling) data from the card will result in D6/D14 toggling between one and zero. Once the Program or Erase cycle is completed, D6/D14 will stop toggling and valid data will be read on the next successiv e attempts. During programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE# pulse . The Toggle Bit is also active during the sector time out. Either CE# or OE# toggling will cause the D6/D14 to toggle.

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MB98D81123/81223-15

D5, D13 (Exceeded Timing Limits)

D5/D13 will indicate if the program or erase time has exceeded the speciﬁed limits (internal pulse count). Under these conditions D cycle was not successfully completed. Data# Polling is the only operating function of the card under this condition. If this failure condition occurs during sector erase operation, it speciﬁes that a particular sector is bad and it may not be reused, howe ver, other sectors are still functional and ma y be used for the program or erase operation. The chip must be reset to use other sectors. Write the Reset command sequence to the chip , and then e xecute Program or Erase command sequence. This allows the system to continue to use the other active sectors in the chip.

If this failure condition occurs during the chip erase operation, it speciﬁes that the entire chip is bad or combination of sectors are bad.

If this failure condition occurs during the byte programming operation, it speciﬁes that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused).

The D5/D13 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the card locks out and never completes the card operation. Hence, the system never reads a valid data on D7/D15 bit and D6/D14 never stops toggling. Once the card has exceeded timing limits, the D5/D13 bit will indicate a “1”. Please note that this is not a device failure condition since the device was incorrectly used.

5/D13 will produce a “1”. This is a failure condition which indicates that the program or erase

D3, D11 (Sector Erase Timer)

After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3/D11 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data# Polling or the Toggle Bit indicates the card has been wr itten with a valid erase command, D3/D11 may be used to determine if the sector erase timer window is still open. If D3/D11 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the card will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If D3/D11 is low (“0”), the card will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of D3/D11 prior to and following each subsequent sector erase command. If D3/D11 were high on the second status check, the command may not have been accepted.

Refer to Table: Hardware Sequence Flags.

D2, D10

This Toggle bit, along with D6, can be used to determine whether the card is in the Erase operation or in Erase Suspend.

Successive reads from the erasing sector will cause D2 to toggle during the Erase operation. If the card is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause D2 to toggle . When the card is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic ‘1’ at the D2 bit.

D6 is different from D2 in that D6 toggles only when the standard Program or Erase , or Er ase Suspend Prog ram operation is in progress.

BUSY#

The card provides a BUSY# open-drain output pin as a wa y to indicate to the system that the prog ram or er ase operation are either in progress or has been completed. If the output is low , the card is busy with either a program or erase operation. If the card is placed in an Erase Suspend mode, the BUSY# output will be high.

During programming, the BUSY# pin is driven low after the rising edge of the fourth WE# pulse . During an erase operation, the BUSY# pin is driven low after the rising edge of the sixth WE# pulse. The BUSY# pin will indicate a busy condition during the RESET# pulse.

■ PROGRAM/ERASE FLOWCHART

Fig. 3 — PROGRAM FLOWCHART

SET ADDRESS

PCMA1, PCMA2 *

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MB98D81123/81223-15

START

SET PA

PD : PROGRAM DATA PA : PROGRAM ADDRESS

INCREMENT PA

WRITE COMMAND

(PCMA1/AAH or AAAAH) *

WRITE COMMAND

(PCMA2/55H or 5555H) *

WRITE COMMAND

(PCMA1/A0H/A0A0H) *

WRITE DATA (PA/PD)

DATA# POLLING,

TOGGLE BIT or

BUSY#

(See Fig. 7, 8, 9, 10)

LAST ADDRESS ?

COMPLETED

*1. See “COMMAND DEFINITION TABLE”.

YES

MB98D81123/81223-15

Fig. 4 — CHIP ERASE FLOWCHART

START

SET CA

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INCREMENT CA

SET ADDRESS

(CCMA1, CCMA2) *

WRITE COMMAND

(CCMA1/AAH or AAAAH) *

WRITE COMMAND

(CCMA2/55H or 5555H) *

WRITE COMMAND

(CCMA1/80H or 8080H) *

WRITE COMMAND

(CCMA1/AAH or AAAAH) *

WRITE COMMAND

(CCMA2/55H or 5555H) *

WRITE COMMAND

(CCMA1/10H or 1010H) *

DATA# POLLING,

TOGGLE BIT or

BUSY#

(See Fig. 7, 8, 9, 10)

CA : CHIP ADDRESS

*1. See “COMMAND DEFINITION TABLE”.

YES

DESIRED OTHER

CHIPS ERASE ?

COMPLETED

MB98D81123/81223-15

Fig. 5 — SECTOR ERASE FLOWCHART

START

SET SA

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SET ADDRESS SCMA1, SCMA2 *

WRITE COMMAND

(SCMA1/AAH or AAAAH) *

WRITE COMMAND

(SCMA2/55H or 5555H) *

WRITE COMMAND

(SCMA1/80H or 8080H) *

WRITE COMMAND

(SCMA1/AAH or AAAAH) *

WRITE COMMAND

(SCMA2/55H or 5555H) *

WRITE COMMAND

(SA/30H or 3030H)

DESIRED OTHER

SECTORS ERASE ?

SA : SECTOR ADDRESS

*1. Possible for the sectors in a chip *2. See “COMMAND DEFINITION TABLE”.

YES

WRITE COMMAND

(SA/30H or 3030H)

DATA# POLLING,

TOGGLE BIT or

BUSY#

(See Fig. 7, 8, 9, 10)

COMPLETED

MB98D81123/81223-15

Fig. 6 — ERASE SUSPEND FLOWCHART

EXECUTING

SECTOR ERASE

WRITE COMMAND

(CA/B0H or B0B0H)

READ DATA (SA) *

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CA : CHIP ADDRESS

SA : SECTOR ADDRESS RA : READ ADDRESS

Yes

Toggle

bit = Toggle? *

Read or Program

STOP Erase

Suspend mode?

WRITE COMMAND (CA/30H or 3030H)

FINISHED

Yes

*1. Detection whether suspend mode is valid

can be done by Data# Polling, Toggle Bit or BUSY# also.

MB98D81123/81223-15

Fig. 7 — DATA# POLLING FLOWCHART: x8 bit mode

*1. User sets the time period ref erring to “PROGRAM

AND ERASE PERFORMANCES”.

START

TIMER START *1

READ (VA) *

*2. Program VA = PA

Chip Erase VA = CA Sector Erase VA = SA

5/D7 are for even chip(s).

*3. D

In the case of odd chip(s),

5 → D13 and D7 → D15 are applied.

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D7 = Data? *

5 = 1 or Time-up?

Yes

READ (VA) *2

7 = Data? *

ERROR

Yes

COMPLETED

MB98D81123/81223-15

Fig. 8 — TOGGLE BIT FLOWCHART: x8 bit mode

START

TIMER START *1

READ (VA) *

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*1. User sets the time period ref erring to “PROGRAM

AND ERASE PERFORMANCES”.

*2. Program VA = PA

Chip Erase VA = CA Sector Erase VA = SA

5/D6 are for even chip(s).

*3. D

In the case of odd chip(s),

5 → D13 and D6 → D14 are applied.

6 = T oggle? *

Yes

5 = 1 or Time-up?

Yes

READ (VA) *2

D6 = T oggle? *

Yes

ERROR

COMPLETED

MB98D81123/81223-15

Fig. 9 — DATA# POLLING FLOWCHART: x16 bit mode

START

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EF = 0

TIMER START *1

READ (VA) *

7 = Data?

5 = 1 or Time-up?

Yes

READ (VA) *

7 = Data?

EF = 1

*1. User sets the time period referring to “PROGRAM

AND ERASE PERFORMANCES”.

*2. Program VA = PA

Chip Erase VA = CA Sector Erase VA = SA

EF: Error Flag EF = 0: Operation Completed EF = 1: Lower Byte Error

Yes

EF = 2: Upper Byte Error EF = 3: Lower/Upper Byte Error

Yes

READ (VA) *

Yes

D15 = Data?

13 = 1 or Time-up?

Yes

READ (VA) *

Yes

15 = Data?

EF = EF+2

EF = 0?

Yes

COMPLETED

ERROR

MB98D81123/81223-15

Fig. 10 — TOGGLE BIT FLOWCHART: x16 bit mode

START

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EF = 0

TIMER START *1

READ (VA) *

6 = T oggle?

Yes

5 = 1 or Time-up?

Yes

READ (VA) *

6 = T oggle?

Yes

EF = 1

*1. User sets the time period referring to “PROGRAM

AND ERASE PERFORMANCES”.

*2. Program VA = PA

Chip Erase VA = CA Sector Erase VA = SA

EF: Error Flag EF = 0: Operation Completed EF = 1: Lower Byte Error EF = 2: Upper Byte Error

EF = 3: Lower/Upper Byte Error

READ (VA) *

14 = T oggle?

Yes

13 = 1 or Time-up?

Yes

READ (VA) *

14 = T oggle?

Yes

EF = EF+2

EF = 0?

Yes

COMPLETED

ERROR

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MB98D81123/81223-15

■ ABSOLUTE MAXIMUM RATINGS *1

Parameter Symbol Value Unit

Supply V oltage VCC –0.5 to +5.5 V Input V oltage VIN –0.5 to VCC +0.5 V Output V oltage VOUT –0.5 to VCC +0.5 V Temperature under Bias TA 0 to +60 °C Storage Temperature T STG –30 to +70 °C

*1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional

operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

■ RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

VCC Supply Voltage VCC 3.135 3.30 3.465 V Ground GND 0 V Ambient Temperature TA 055°C

■ DC CHARACTERISTICS

Parameter Test Conditions Symbol

Min Typ Max

Input Leakage Current * Output Leakage Current *

Standby Current

VCC = VCC max., VIN = GND or VCC ILI ±10 µA

VCC = VCC max., VIN = GND or VCC ILO ±10 µA CEL#, CEH#,

RESET# = V

CC±0.3 V

ISB1 —1070µA

CEL#, CEH#, RESET# = VIH ISB2 5.0 mA

Active Read Current

VCC = VCC max., CEL#, CEH# = VIL Cycle = 150 ns, IOUT = 0 mA

ICC1 50 80 mA

Program Current Program in progress (×16 mode) ICC2 60 100 mA Erase Current Erase in progress (×16 mode) ICC3 60 100 mA Input Low Voltage — VIL –0.5 — 0.6 V

Value

Unit

Input High Voltage — VIH 0.7 VCC —VCC+0.5 V Output Low Voltage IOL = 4.0 mA, VCC = VCC min. VOL 0.45 V Output High Voltage IOH = –2.0 mA, VCC = VCC min. VOH 2.4 V

CC Lock-out Voltage

Low V

—V

LKO 2.3 — 2.5 V

Notes: *1. This value does not apply to CEL#, CEH# and WE#.

*2. This value does not apply to CD# and CINS#.

MB98D81123/81223-15

■ CAPACITANCE (TA = 25°C, f = 1 MHz, VIN = VI/O = GND)

Parameter Symbol Min Max Unit

Input Capacitance * I/O Capacitance *

Notes: *1. This value does not apply to CEL#, CEH# and WE#.

*2. This value does not apply to VS1#, CD# and CINS#.

■ AC TEST CONDITIONS

• Input Pulse Levels: VIH = 3.0 V, VIL = 0.0 V

• Input Pulse Rise and Fall Times: 5 ns

• Timing Reference Levels Input: VIL = 1.5 V, VIH = 1.5 V Output: V OL = 1.5 V, VOH = 1.5 V Output Load: 1TTL +100 pF

CIN 40 pF

CI/O 40 pF

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■ PROGRAM AND ERASE PERFORMANCES

Parameter Min Typ Max Unit

Byte Program Time * Chip Programming Time * Sector Erase Time *

Program/Erase Cycles 100,000 Cycles

Notes: *1. Excludes system-level overhead.

*2. Excludes 00H programming prior to erasure.

8 3600 µs

8.4 T.B.D. Sec. 1 15 Sec.

MB98D81123/81223-15

■ AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)

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READ CYCLE *

Parameter Symbol Min Max Unit

Read Cycle Time t

RC 150 ns

Card Enable Access Time tCE 150 ns Address Access Time tACC 150 ns Output Enable Access Time tOE 75 ns Card Enable to Output in Low-Z * Card Disable to Output in High-Z * Output Enable to Output in Low-Z * Output Disable to Output in High-Z *

Output Hold from Address Change t

tCLZ 5ns tCHZ 75 ns tOLZ 5ns tOHZ 60 ns

OH 0ns

Ready Time from RESET# tRDY 20 µs

Notes: *1. Rise/Fall time < 5 ns.

*2. Transition is measured at the point of ±500 mV from steady state voltage.

MB98D81123/81223-15

PROGRAM/ERASE CYCLE

Parameter Symbol Min Typ Max Unit

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Write Cycle Time t

WC 150 ns

Address Setup Time tAS 20 ns Address Hold Time t

AH 20 ns

Data Setup Time tDS 50 ns Data Hold Time tDH 20 ns Read Recovery Time (WE# control) tGHWL 10 ns Read Recovery Time (CE# control) tGHEL 10 ns Output Enable Hold Time Card Enable Setup Time t

OEH

CS 0ns

10 ns

Card Enable Hold Time tCH 10 ns Write Enable Pulse Width tWP 80 ns Write Enable Setup Time tWS 0ns Write Enable Hold Time tWH 10 ns Card Enable Pulse Width t Duration of Byte Program Operation

(/WE Control) Duration of Erase Operation *

(/WE Control)

CP 100 ns

tWHWH1 8 µs

WHWH2 115s

Duration of Byte Program Operation (/CE Control)

Duration of Erase Operation *

(/CE Control) VCC Setup Time *

Reset Pulse Width t

EHEH1 8 µs

EHEH2 115s

tVCS 50 µs

RP 500 ns

Busy Delay Time tBSY 90 ns

Notes: *1. These do not include the preprogramming time.

*2. Not 100% tested.

MB98D81123/81223-15

■ TIMING DIAGRAM

READ CYCLE TIMING DIAGRAM (WE# = VIH, RESET# = VIH)

READ CYCLE (×8 bit mode): “CEL# = OE# = VIL, CEH# = VIH” or “CEH# = OE# = VIL, CEL# = VIH”

tRC

VIH

Addresses

VIL

tACC

tOH

D0-D7

D8-D15

VOH

PREVIOUS DATA VALID

VOL

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DAT A VALID

READ CYCLE (×16 bit mode): CEL# = CEH# = OE# = VIL

Addresses

VIL

tOH

VOH

D0-D15

VOL

PREVIOUS DATA VALID

tRC

tACC

DAT A VALID

:Undeﬁned

MB98D81123/81223-15

READ CYCLE TIMING DIAGRAM (continued) (WE# = VIH, RESET# = VIH)

READ CYCLE 3: ×8-bit Bus Organization

VIH

Addresses

VIL

tACC

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CE1#

CE2#

OE#

D0-D7

D8-D15

VIH VIL

VOH VOL

High-Z

tCLZ

tCE

tOLZ

tOE

tCHZ

tOHZ

DAT A VALID

:Undeﬁned

MB98D81123/81223-15

READ CYCLE TIMING DIAGRAM (continued) (WE# = VIH, RESET# = VIH)

READ CYCLE 4: CEL# = CEH# = VIL: ×16-bit Bus Organization

Addresses

V VIL

tACC

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tCHZ

CEL#=CEH#

OE#

D0-D15

VIH VIL

VOH VOL

High-Z

tCE

tOHZ

tCLZ

tOE

tOLZ

DATA VALID

:Undeﬁned

MB98D81123/81223-15

PROGRAM CYCLE TIMING DIAGRAM (WE# = CONTROLLED, RESET# = VIH)

To Top / Lineup / Index

Addresses

CE# *

OE#

WE#

VIH VIL

tCS

tGHWL

1st Bus Cycle

PCMA1 *

tWC

tWP

2nd Bus Cycle

PCMA2 *

tAS tAH

tCH

tWPH

tDH

3rd Bus Cycle

PCMA1 *

4th Bus Cycle

PA *

tOEH

tBSY

Data# Polling Cycle

tWHWH1

PA *

tRC

tDS

Data *

VIH/OH VIL/OL

55H

(5555H)

VOH

AAH

(AAAAH)

tVCS

RESET#

VOL

VCC

Notes: *1. See “FUNCTION TRUTH TABLE”.

*2. PCMA1/PCMA2 = Command Address for Program, PA = Program Address, PD = Program Data. See

“COMMAND DEFINITION TABLE”.

A0H

(A0A0H)

PD *

D7#,

PD *

Data

D15#

:Undeﬁned

MB98D81123/81223-15

PROGRAM CYCLE TIMING DIAGRAM (CE# = CONTROLLED, RESET# = VIH)

To Top / Lineup / Index

Addresses

WE#

OE#

CE# *

VIH VIL

tWS

tGHEL

1st Bus Cycle

PCMA1 *

tWC

tCP

2nd Bus Cycle

PCMA2 *

tAS tAH

tWH

tCPH

tDH

3rd Bus Cycle

PCMA1 *

4th Bus Cycle

PA *

tOEH

tBSY

Data# Polling Cycle

tEHEH1

PA *

tRC

tDS

Data *

VIH/OH VIL/OL

AAH

(AAAAH)

tVCS

55H

(5555H)

BUSY#

VOL

VCC

Notes: *1. See “FUNCTION TRUTH TABLE”.

*2. PCMA1/PCMA2 = Command Address for Program, PA = Program Address, PD = Program Data. See

“COMMAND DEFINITION TABLE”.

A0H

(A0A0H)

PD *

D7#,

PD *

Data

D15#

:Undeﬁned

MB98D81123/81223-15

ERASE CYCLE TIMING DIAGRAM (WE# = CONTROLLED, RESET# = VIH)

To Top / Lineup / Index

Addresses

CE# *

OE#

WE#

VIH

VIL

VIH

VIL

VIH VIL

tCS

tGHWL

1st Bus Cycle

CCMA1/ SCMA1 *

tWC

tWP

2nd Bus Cycle

CCMA2/

SCMA2 *

tAS tAH

tCH

tWPH

tDH

3rd Bus Cycle

CCMA1/ SCMA1 *2

4th Bus Cycle

CCMA1/ SCMA1 *2

5th Bus Cycle

CCMA2/ SCMA2 *2

6th Bus Cycle

CCMA1/

SA *

tDS

Data *

VIH/OH

VIL/OL

AAH

(AAAAH)

tVCS

VCC

Notes: *1. See “FUNCTION TRUTH TABLE”.

*2. CCMA1/CCMA2 = Command Address for Chip Erase, SCMA1/SCMA2 = Command Address for Sector

Erase, SA = Sector Address. See “COMMAND DEFINITION TABLE”.

55H

(5555H)

80H

(8080H)

AAH

(AAAAH)

55H

(5555H)

10H/30H

(1010H/3030H)

:Undeﬁned

MB98D81123/81223-15

ERASE CYCLE TIMING DIAGRAM (CE# = CONTROLLED, RESET# = VIH)

To Top / Lineup / Index

Addresses

WE#

OE#

CE# *

VIH VIL

tGHEL

tWS

1st Bus Cycle

CCMA1/ SCMA1 *

tWC

tCP

2nd Bus Cycle

CCMA2/

SCMA2 *

tAS tAH

tWH

tCPH

tDH

3rd Bus Cycle

CCMA1/ SCMA1 *2

4th Bus Cycle

CCMA1/ SCMA1 *2

5th Bus Cycle

CCMA2/ SCMA2 *

6th Bus Cycle

CCMA1/

SA *

tDS

Data *

VIH/OH VIL/OL

AAH

(AAAAH)

55H

(5555H)

tVCS

VCC

Notes: *1. See “FUNCTION TRUTH TABLE”.

*2. CCMA1/CCMA2 = Command Address for Chip Erase, SCMA1/SCMA2 = Command Address for Sector

Erase, SA = Sector Address. See “COMMAND DEFINITION TABLE”.

80H

(8080H)

AAH

(AAAAH)

55H

(5555H)

10H/30H

(1010H/3030H)

:Undeﬁned

MB98D81123/81223-15

DATA# POLLING CYCLE TIMING DIAGRAM (RESET# = VIH)

To Top / Lineup / Index

Addresses

CE# *

OE#

WE#

D7, D15

VIH VIL

IH/OH

VIL/OL

Command Write Cycle

tWC

D7, D15 D7#, D15# D7, D15 Valid Data

tOEH

tWHWH1,2

EHEH1,2) *

tACC

tCE

Data# Polling Read Cycle

VA *

tCHZ

tOE

tOHZ

D0-D6 * D8-D14

VIL/OL

D0-D6, D8-D14

D0-D6, D8-D14 Invalid Data

D0-D6, D8-D14 Valid Data

VIH/OH

Notes: *1. VA = PA for Programming Cycle, VA = SA for Sector Erase, VA = CA for Chip Erase.

*2. See “FUNCTION TRUTH T ABLE”. *3. tEHEH1,2 for CE# Control. *4. Program/Erase operation is ﬁnished.

:Undeﬁned

TOGGLE BIT TIMING DIAGRAM (RESET# = VIH)

Toggle Bit Read Cycle

VA *

tRC

Addresses

CE# *

VIH

Command Write Cycle

VIL

VIH VIL

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MB98D81123/81223-15

VA *

OE#

WE#

Data *

VIH VIL

VIH/OH VIL/OL

tOEH

tOE

D6, D14 Toggle

D6, D14 Stop

Valid Data

Toggling

:Undeﬁned

Notes: *1. VA = PA for Programming Cycle, VA = SA for Sector Erase, VA = CA for Chip Erase.

*2. See “FUNCTION TRUTH T ABLE”. *3. Program/Erase operation is ﬁnished. *4. PD, 10H (1010H) or 30H (3030H)

MB98D81123/81223-15

BUSY# Timing Diagram During Program/Erase Operations

CE#

WE#

To Top / Lineup / Index

BUSY#

RESET# Timing Diagram

RESET#

Entire programming or erase operation

tRSY

Possible next operation

tRP

tRDY

■ UNIQUE FEATURES

Write Protect Switch

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MB98D81123/81223-15

Write Protect Switch

“Protect”

“Non Protect”

Voltage Selection

The Miniature Card voltage is identiﬁed by both a mechanical key and voltage sense signals (VS1#, VS2#). The combination of the two allow the host to determine the proper voltage required to operate the Miniature Card, as well as a physical means to keep cards out of host systems that may damage the cards because of improper operational voltage.

Six different voltage key combinations are deﬁned in “Miniature Card Speciﬁcation”: 5 volt only, 3.3 volt only, x.x volt only, 3V/5V, x.xV/3V, and x.xV/3V/5V. These keys consist of notches in the Miniature Card and corresponding tabs in the socket. The socket tabs are located in the front of the Miniature Card socket and are used to keep out cards that do not contain the corresponding notch. See Voltage Keying Mechanism below. (Now only deﬁned about 5.0V and 3.3V)

Miniature Card

5V Only Host

1 2

5V Only

Miniature Card

1 2

Host

3.3V/5V Host

Miniature Card

1 2 3 4

3.3V/5V

Miniature Card

1 2 3

3.3V Only Host

2 3

MB98D81123/ 81223 is applied for this key

3.3V Only

Miniature Card

2 3

MB98D81123/81223-15

■ ATTRIBUTE INFORMATION STRUCTURE (AIS)

Address Data Attribute

0000 01 [Common Memory device information tuple] 0001 03 Link to next tuple 0002 53 Flash memory with 150 ns access time

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0003

0004 FF End of list

05 - 0D 00 [Nulltuple-ignore]

000E 80 [Vendor unique tuple] 000F F1 Link to next tuple

0010 99 “Miniature Card Identiﬁer” 0011 10 “Level of Compliance” 0012 B5 “AIS Checksum” (B00-A4B=B5) [MB98D81123]

0013 46 “Manufacture Name” (F) 0014 55 (U) 0015 4A (J) 0016 49 (I) 0017 54 (T) 0018 53 (S)

1D 2 MB device size for common memory [MB98D1123] 0E 4 MB device size for common memory [MB98D1223]

B3 “AIS Checksum” (B00-A4D=B3) [MB98D81223]

0019 55 (U) 001A 00 001B 4C (L) 001C 49 (I) 001D 4D (M) 001E 49 (I) 001F 54 (T)

0020 45 (E)

0021 44 (D)

0022 00

0023 00

0024 00

0025 00

MB98D81123/81223-15

■ ATTRIBUTE INFORMATION STRUCTURE (AIS) (continued)

Address Data Attribute

0026 00

0027 4D “Card Name” (M)

0028 42 (B)

0029 39 (9) 002A 38 (8) 002B 44 (D) 002C 38 (8) 002D 30 (0) 002E 30 (0) 002F 32 (2)

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0030 33 (3)

0031 00

0032 73 (s)

0033 65 (e)

0034 72 (r)

0035 69 (i)

0036 65 (e)

0037 73 (s)

0038 00

0039 00 003A 00 003B 01 “Technology Count” (1) 003C 00 “Reserved” 003D 00 “Reserved” 003E 00 “Reserved” 003F 00 “Reserved”

0040 00 “Memory T ype” (Flash)

0041 04 “JEDEC Manufacture ID” (FUJITSU)

0042 38 “JEDEC Component ID” (MBM29LV080)

0043 01 “Memory Size” (2MB) [MB98D81123]

03 “Memory Size” (4MB) [MB98D81223]

0044 00 “x.x V Access time” (Not supported)

MB98D81123/81223-15

■ ATTRIBUTE INFORMATION STRUCTURE (AIS) (continued)

Address Data Attribute

0045 0F “3.3 V Access time” (150 ns)

0046 00 “5.0 V Access time” (Not supported)

0047 00 “x.x V Read/Write” (Not supported)

0048 56 “3.3 V Read/Write” (50 mA/60 mA)

0049 00 “5.0 V Read/Write” (Not supported) 004A 01 “Standby Current” (100 µA) 004B 00 “Reserved” 004C 00 “Reserved” 004D 00 “Reserved” 004E 00 “Reserved”

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004F 00 “Reserved” 00FF 00 “Reserved”

0100 FF End of list

0101 15 [Level 1 version/product-information tuple]

0102 1C Link to next tuple

0103 05

0104 00

0105 46 (F)

0106 55 (U)

0107 4A (J)

0108 49 (I)

0109 54 (T) 010A 53 (S) 010B 55 (U) 010C 00 010D 4D (M)

PC Card Standard, February 1995

010E 42 (B) 010F 39 (9)

0110 38 (8)

0111 44 (D)

0112 38 (8)

0113 30 (0)

MB98D81123/81223-15

■ ATTRIBUTE INFORMATION STRUCTURE (AIS) (continued)

Address Data Attribute

0114 30 (0)

0115 32 (2)

0116 33 (3)

0117 73 (s)

0118 65 (e)

0119 72 (r) 011A 69 (i) 011B 65 (e) 011C 73 (s) 011D 00

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011E FF End of list 011F 18 [JEDEC programming information for Common Memory tuple]

0120 03 Link to next tuple

0121 04 JEDEC Manufacture ID (FUJITSU)

0122 38 JEDEC Device ID (MB29LV080)

0123 FF End of list

0124 1E [Device geometry information for Common Memory device tuple]

0125 07 Link to next tuple

0126 02 System bus width is 2 Bytes

0127 11 Erase block size is 64 KBytes

0128 01 Read block size is 1 Bytes

0129 01 Write block size is 1 Bytes 012A 01 No special partitioning requirements 012B 01 Non interleaved 012C FF End of list 012D 12 [Longlink to Common Memory] 012E 05 Link to next tuple 012F 00

0130 00

Target address; stored as an unsigned long, low-order byte ﬁrst

0131 02

0132 00

0133 FF End of list

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MB98D81123/81223-15

■ ATTRIBUTE INFORMATION STRUCTURE (AIS) (continued)

Address Data Attribute

0134 1C [Other operating conditions device information for Common Memory]

0135 04 Link to next tuple

0136 02 Other Conditions Information: 3.3 V Operation

0137 53 Flash Memory with 150 ns access time

0138 1D 2 MB device size for common memory [MB98D81123]

0E 4 MB device size for common memory [MB98D81223]

0139 FF End of list 013A FF [The end-of-chain tuple]

Notice:AIS is programed from the address “0000H” of Lo wer Byte. This AIS may be deleted on the driv er software

which does not consider AIS.

■ PACKAGE DIMENSIONS

60-PIN MINIATURE CARD

(CASE No.: CRD-60P-M02)

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MB98D81123/81223-15

33.00±0.13(1.299±.005)

2.50

(.098)

12.70(.500)

7.20(.283)

(.138±.005)

2.50(.098)TYP

1996 FUJITSU LIMITED K60002SC-1-1

3.00

(.118)

2.50(.098)MIN

1.52(.060)

"A"

15.24(.600)3.50±0.13

7.62(.300)

38.00±0.13

(1.496±.005)

0.77(.030)

Details of "A" part

0.50(.020)

1.85(.073)

2-R0.50(.020)

5.50(.217)

8.00(.315)

5.50(.217)

R1.00(.039)

TYP

0.85(.033)

2.70

(.106)

18.00 (.709)

1.68(.066)

4.58

(.180)

9.10

(.358)

18˚TYP

3.40±0.05

(.134±.002)

4.25(.167)TYP

3.25(.128)TYP R0.15

(.006)

2.48

(.098)

"B"

Details of "B" part

1.25(.049) MIN

1 PIN

4.125±0.05

(.162±.002)

4.81±0.08

(.189±.003)

33.00±0.13

(1.299±.005)

7.21±0.08

(.283±.003)

5.95(.234)

1.00(.039)TYP

0.50±0.036 (.020±.001)

1.60

(.063)

2.60

0.50±0.05

(.020±.002)

(.102)

Dimension in mm (inches)

MB98D81123/81223-15

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329

North and South America

FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045

Europe

FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122

Asia Paciﬁc

FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220

To Top / Lineup / Index

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

F9703  FUJITSU LIMITED Printed in Japan

If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.

FUJITSU MB98D81123, MB98D81223-15 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

PACKAGE

DESCRIPTION

PAD ASSIGNMENTS

PAD DESCRIPTIONS

PAD LOCATIONS

BLOCK DIAGRAM

MB98D81123

MB98D81223

CHIP AND SECTOR DECODING

CHIP CONFIGURATION

■ FUNCTION DESCRIPTIONS

■ FUNCTION TRUTH T ABLE

■ COMMAND DEFINITION TABLE

■ WRITE OPERATION STATUS

Hardware Sequence Flag Table

D7, D15 (Data# Polling)

D6, D14 (Toggle Bit I)

D5, D13 (Exceeded Timing Limits)

D3, D11 (Sector Erase Timer)

D2, D10

BUSY#

■ PROGRAM/ERASE FLOWCHART

■ RECOMMENDED OPERATING CONDITIONS

■ DC CHARACTERISTICS

■ AC TEST CONDITIONS

■ PROGRAM AND ERASE PERFORMANCES

■ AC CHARACTERISTICS

PROGRAM/ERASE CYCLE

■ TIMING DIAGRAM

DATA# POLLING CYCLE TIMING DIAGRAM (RESET# = VIH)

TOGGLE BIT TIMING DIAGRAM (RESET# = VIH)

RESET# Timing Diagram

■ UNIQUE FEATURES

■ ATTRIBUTE INFORMATION STRUCTURE (AIS)

■ PACKAGE DIMENSIONS