FUJITSU MB98C81013, MB98C81123, MB98C81233, MB98C81333 DATA SHEET

To Top / Lineup / Index

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-30338-2E

FLASH MEMORY CARD

5V-ONLY FLASH MINIATURE CARD

MB98C81013(1MB)/81123(2MB)/81233(4MB)/81333(8MB)-10

1M/2M/4M/8M-BYTE 5 V-ONLY FLASH MINIATURE CARD

The Fujitsu Flash Miniature cards conform to “Miniature Card Speciﬁcation” pubulished by MCIF; Miniature Card Implementers Forum.

The Fujitsu Flash Miniature cards are small form factor Flash memory cards targeted various markets; digital photography, audio recording, hand held PCs and other small portable equipments. Miniature cards’ high performance, small size (38 mm × 33 mm × 3.5 mm), low cost and simple interface are ideal f or portable applications that require high speed ﬂash disk drives or eXecute In Place (XIP).

The Flash Miniature cards are 5 V -only oper ational and allow the users to use as ×8 or ×16 organization on low power at high speed.

• Small size : 33.0 mm (length) × 38.0 mm (width) × 3.5 mm (thickness)

• +5 V ±5% power supply program and erase

• Command control for Automated Program/Automated Erase operation

• Erase Suspend Read/Program Capability (Only Erase Suspend Read is possible for MB98C81013)

• 128 KB Sector Erase (at ×16 mode)

• Any Combination of Sectors Erase and Full Chip Erase

• Detection of completion of program/erase operation with Data# Polling or Toggle bit.

• Ready/Busy Output with BUSY# (Except for MB98C81013)

• Reset Function with RESET# pin (Except for MB98C81013)

• Write protect function with WP switch

• Low VCC Write Inhibit

• AIS (Attribute Information Structure) is available from the address “0000H” of Lower Byte.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric ﬁelds. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

■

MB98C81013/81123/81233/81333-10

PACKAGE

5 V - ONLY FLASH MINIATURE CARD

Flash Memory

M byte

5V OPERATION

(CRD-60P-M01)

WRITE PROTECT

To Top / Lineup / Index

DESCRIPTIONS

DIFFERENCES

MB98C81013 MB98C81123 MB98C81233 MB98C81333

Density 1 MB 2 MB 4 MB 8 MB Memory Device 4 M bit 8 M bit 16 M bit Quantity 2224 Read 1 B unit Program 1 B unit Chip Erase 512 KB unit 1 MB unit 2 MB unit Sector Erase 64 KB unit Number of Sectors 16 32 64 128 Erase Suspend Read Yes Yes Yes Yes Erase Suspend Program No Yes Yes Yes Address A0 to A18 A0 to A19 A0 to A20 A0 to A21 RESET# No Yes Yes Yes BUSY# No Yes Yes Yes

←←← ←←←

←←←

←

MEMORY MAP

4 MW

To Top / Lineup / Index

MB98C81013/81123/81233/81333-10

2 MW

1 MW

512 KW

chip1,0

MB98C81013

4M bit × 2

MB98C81123

8M bit × 2

MB98C81233

16M bit × 2

chip3,2

chip1,0chip1,0chip1,0

MB98C81333

16M bit × 4

■

To Top / Lineup / Index

MB98C81013/81123/81233/81333-10

PAD ASSIGNMENTS

Pad No Symbol Pad No Symbol Pad No Symbol Pad No Symbol

1A1816 N.C. 31 A 2A1617 N.C. 32 A 3A

4 N.C. 19 D 5 CEH# 20 D 6A1121 D 7A 8A

9A 10 A 11 A 12 A 13 A

18 OE# 33 A

34 A 35 A 36 RESET# 51 RFU 37 A 38 VS1# 53 VS2# 39 A 40 N.C. 55 D 41 A

22 D 23 D 24 D 25 D 26 D

27 N.C. 42 CEL# 57 D 28 D

43 A

* 46 CD#

47 A21 * 48 BUSY# 49 WE# 50 D

52 D

54 D

56 D

58 D 14 N.C. 29 N.C. 44 N.C. 59 N.C. 15 N.C. 30 N.C. 45 N.C. 60 A20 *

EX 1 V

EX 2 GND EX 3 CINS#

* :A19, A20, A21 are “N.C.” for each product. See “DESCRIPTIONS”.

■

To Top / Lineup / Index

MB98C81013/81123/81233/81333-10

PAD DESCRIPTIONS

Symbol I/O Pad Name Symbol I/O Pad Name

A0 to A D0 to D CEL# I Card Enable for Lower Byte VS1#, VS2# O Voltage Sense CEH# I Card Enable for Upper Byte N.C. — Non Connection OE# I Output Enable V WE# I Write Enable GND — Ground RESET# I Hardware Reset CINS# O Card Insertion *

* :Take notice that those pads are connected internally.

I Address Input BUSY# O Ready/Busy

I/O Data Input/Output CD# O Card Detect *

— Power Supply

PAD LOCATIONS

Fig. 1 — BOTTOM VIEW

EX 1 EX 3 EX 2

CC Key: See “UNIQUE FEATURES”.

VCC Key

MB98C81013/81123/81233/81333-10

■

BLOCK DIAGRAM

MB98C81013, MB98C81123 and MB98C81233

Fig. 2.1 — BLOCK DIAGRAM

To Top / Lineup / Index

VCC

GND

Address

RESET# *

CEL#

CEH#

OE#

D0 to D7

VCC

Internal circuit

VCC

100K

RESET WE OE CE

Even Flash Memory

4M bit × 1 (MB98C81013) 8M bit × 1 (MB98C81123)

16M bit × 1 (MB98C81233)

Address

I/O

R/B

D8 to D15

VCC

WE#

VS1# VS2#

BUSY# *

CINS#

CD#

100K

Write Protect Switch

N.C.

N.C. N.C.

VCC

10K

* : Except for MB98C81013.

RESET WE OE CE

Odd Flash Memory

4M bit × 1 (MB98C81013) 8M bit × 1 (MB98C81123)

16M bit × 1 (MB98C81233)

Address

I/O

R/B

MB98C81333

To Top / Lineup / Index

MB98C81013/81123/81233/81333-10

Fig. 2.2 — BLOCK DIAGRAM

VCC

GND

Address

RESET#

CEL#

CEH#

OE#

D0 to D7

A21

VCC

Internal circuit

A /G1

Decoder

/G2

100K

VCC

100K

RESET WE OE CE

Even Flash Memory

16M bit × 2 (MB98C81333)

Address

I/O

R/B

D8 to D15

WE#

VS1# VS2#

BUSY#

CINS#

CD#

N.C. N.C.

VCC

100K

Write Protect Switch

N.C.

VCC

10K

RESET WE OE CE

Odd Flash Memory

16M bit × 2 (MB98C81333)

Address

I/O

R/B

MB98C81013/81123/81233/81333-10

■

CHIP AND SECTOR DECODING

ERASE SECTOR DECODING TABLE

Sector Address (SA)

A20 * Sector 31 11111 Sector 30 11110 Sector 29 11101

•

Total 32 sectors *

per 1 chip

1 *2

•

Sector 2 0 0 0 1 0

A19 *

•

A18 A17 A16

•

To Top / Lineup / Index

•

Sector 1 0 0 0 0 1 Sector 0 0 0 0 0 0

Notes: *1. A19 is not availabe for MB98C81013. MB98C81013 has 8 sectors.

*2. A20 is not availabe f or MB98C81013 and MB98C81123. MB98C81013 has 8 sectors and MB98C81123

has 16 sectors.

To Top / Lineup / Index

MB98C81013/81123/81233/81333-10

■ CHIP CONFIGURATION

The miniature cards use 2 or 4 pcs of Flash Memory. 2 pcs of Flash Memory are operated simultaneously at 16 bit mode and even number of chip is applied to lower byte and odd number of chip is applied to upper byte. At ×8 bit mode, even address and odd address are selected with CEL# and CEH#.

× 16 bit mode

CEL# = “L”, CEH# = “L”

: :

Odd Number of Chip + Even Number of Chip

• • • • • • • • • • • • • • D0

D15

× 8 bit mode

CEL# = “H”, CEH# = “L”

: :

odd Number of Chip

003h

CEL# = “L”, CEH# = “H”

even Number of Chip

003h

002h

001h

000h

: :

003h

odd Number of Chip

D15

• • • • D8

002h

001h

000h

even Number of Chip

• • • • • D0

002h

001h

000h

To Top / Lineup / Index

MB98C81013/81123/81233/81333-10

■ FUNCTION DESCRIPTIONS

1. Read Mode

The data in the common can be read with “OE# = VIL ” and “WE# = VIH”. The address is selected with A0-A21. And CEL# and CEH# select output mode.

2. Standby Mode

– CEL# and CEH# at “VIH” place the card in Standby mode. D0-D15 are placed in a high-Z state independent

of the status “OE#” and “WE#”.

3. Output Disable Mode

– The outputs are disabled with OE# and WE# at “VIH”. D0-D15 are placed in high-Z state.

4. Write Mode

– The card is in Write mode with “OE# = VIH” and “WE# and CE# = VIL”. – Commands can be written at the Write mode. – Two types of the Write mode, “WE# control” and “CE# control” are available.

5. Command Deﬁnitions

– User can select the card operation by wr iting the speciﬁc address and data sequences into the command

register. If incollect address and data are written or improper sequence is done, the card is reseted to read mode. See “COMMAND DEFINISION TABLE”.

6. Automated Program Capability

– Programming operation can switch the data from “1” to “0”. – The data is programmed on a byte-by-byte or word-by-word basis. – The card will automatically provide adequate internally generated programming pulses and verify the pro-

grammed cell margin by writing four bus cycle operation. The card returns to Common Memory Read mode automatically after the programming is completed.

– Addresses are latched at falling edge of WE# or CE# and data is latched at rising edge of WE# or CE#. The

fourth rising edge of WE# or CE# on the command write cycle begins programming operation.

– W e can check whether a byte (w ord) programming operation is completed successfully b y sequence ﬂug with

BUSY# (except MB98C81013), Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.

– Any commands written to the chip during programming operation will be ignored.

7. Automated Chip Erase Capability

– W e can execute chip erase operation b y 6 bus cycle operation. Chip erase does not require the user to program

the chip prior to erase. Upon executing the Erase command sequence the chip automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required

to provide any controls or timing during these operations. – The card returns to Common Memory Read mode automatically after the chip erasing is completed. – Whether or not chip erase oper ation is completed successfully can be checked b y sequence ﬂug with BUSY#

(except MB98C81013), Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”. – Any commands written to the chip during programming operation will be ignored.

To Top / Lineup / Index

MB98C81013/81123/81233/81333-10

8. Automated Sector Erase Capability

– We can execute the erase operation on any sectors by 6 bus cycle operation. – A time-out of 50 µs (typ .) from the rising edge of the last Sector Erase command will initiate the Sector Erase

command(s). – Multiple sectors in a chip can be erased concurrently . This sequence is f ollowed with writes of 30H to addresses

in other sectors desired to be concurrently erased. The time between writes 30H must be less than 50 µs,

otherwise that command will not be accepted. Any command other than Sector Erase or Erase Suspend

during this time-out period will reset the chip to Read mode. The automated sector erase begins after the 50

µs (typ.) time out from the rising edge of WE# pulse for the last Sector Erase command pulse. Whether the

sector erase window is still open can be monitored with D3 and D11. – Sector Erase does not require the user to program the chip prior to erase. The chip automatically progr ams

“0” to all memory locations in the sector(s) prior to electrical erase. The system is not required to provide any

controls or timing during these operations. – The card returns to Common Memory Read mode automatically after the chip erasing is completed. – Whether or not sector erase operation is completed successfully can be checked by sequence ﬂug with

BUSY#, Data# Polling or Toggle Bit function. The sequence ﬂug must be read from the address of the sector

involved in erase operation. See “WRITE OPERATION STATUS”.

9. Erase Suspend

– Erase Suspend command allows the user to interrupt the sector erase operation and then do data reads or

program from or to a non-busy sector in the chip which has the sector(s) suspended erase (only data read is

possible for MB98C81013). This command is applicable only during the sector erase operation (including the

sector erase time-out period after the sector erase commands 30H) and will be ignored if written during the

chip erase or programming operation. Writing this command during the time-out will result in immediate

termination of the time-out period. The addresses are “don’t cares” in wrinting the Erase Suspend or Resume

commands in the chip. – When the Erase Suspend command is written during a Sector Erase operation, the chip will enter the Erase

Suspend Read mode. User can read the data from other sectors than those in suspention. The read oper ation

from sectors in suspention results D2/D10 toggling except MB98C81013. User can program to non-busy sectors

by writing program commands except MB98C81013. – A read from a sector being erase suspended may result in invalid data.

10. Intelligent Identiﬁer (ID) Read Mode

– Each common memory can execute an Intelligent Identiﬁer operation, initiated by writing Intelligent ID com-

mand (90H). Following the command write, a read cycle from address 00H retrieves the manufacture code,

and a read cycle from address 01H returns the device code as follows. To terminate the operation, it is

necessary to write Read/Reset command.

11. Hardware Reset (not applied for MB98C81013)

– The Card may be reset by driving the RESET# pin to VIL. The RESET# pin must be kept High (VIL) for at

least 500 ns. Any operation in progress will be terminated and the card will be reset to the read mode 20 µs

after the RESET# pin is driven Low. If a hardware reset occurs during a program operation, the data at that

particular location will be indeterminate. – When the RESET# pin is Low and the internal reset is complete, the Card goes to standb y mode and cannot

be accessed. Also, note that all the data output pins are High-Z for the duration of the RESET# pulse. Once

the RESET# pin is taken high, the Card requires 500 ns of wake up time until outputs are v alid for read access. – If hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be

used.

To Top / Lineup / Index

MB98C81013/81123/81233/81333-10

12. Data Protection

– The card has WP (Write Protect) switch for write lockout. – To avoid initiation of a write cycle during V

less than 3.2 V. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are

disabled.

Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC

level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to

prevent unintentional writes when VCC is above 3.2 V. – If VCC would be less than VLKO during program/erase operation, the operation will stop. And after that, the

operation will not resume even if VCC returns recommended voltage le vel. Therefore , program command must

be written again because the data on the address interrupted program operation is invalid. And regarding

interrupting erase operation, there is possibility that the erasing sector(s) cannot be used. – Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.

CC power-up and power-down, a write cycle is locked out for VCC

MB98C81013/81123/81233/81333-10

■ FUNCTION TRUTH T ABLE

To Top / Lineup / Index

Mode

Hardware Reset L X X X X P or NP High-Z High-Z

Standby

Read (×8 bit)

Read (×16 bit) L L DOUT DOUT

Write (×8 bit)

Write (×16 bit) L L DIN DIN

Output Disable

H : “H” level, L : “L” level , X : “H” or “L”

Notes: *1. WPSW = Write Protect Switch, NP = NON-PROTECT, P = PROTECT

*2. Except for MB98C81013.

RESET# *

CEH# CEL# OE# WE#

H H X X P or NP High-Z High-Z HL

L H DOUT High-Z

L H DIN High-Z

L H High-Z High-Z L L High-Z High-Z

L H P or NP

WPSW *

Data Input/Output

D8 to D15 D0 to D7

High-Z DOUT

High-Z DIN

High-Z High-Z

MB98C81013/81123/81233/81333-10

■ COMMAND DEFINITION TABLE

Command Table for 8-bit Mode

To Top / Lineup / Index

Command

Read/Reset 1 2

Read/Reset 2 4

Read Intelligent ID Codes

Byte Program 4

Sector Erase 6

Chip Erase 6

Sector Erase Suspend

Bus

Cycle

1st Bus

Write Cycle

Write Read

CA F0H RA RD

Write Write Write Read

RCMA1 AAH RCMA2 55H RCMA1 F0H RA RD

Write Write Write Read

ICMA1 AAH ICMA2 55H ICMA1 90H IA ID

Write Write Write Write

PCMA1 AAH PCMA2 55H PCMA1 A0H PA PD

Write Write Write Write Write Write

SCMA1 AAH SCMA2 55H SCMA1 80H SCMA1 AAH SCMA2 55H SA 30H

Write Write Write Write Write Write

CCMA1 AAH CCMA2 55H CCMA1 80H CCMA1 AAH CCMA2 55H CCMA1 10H

Write

CA B0H

2nd Bus

Write/Read

Cycle

3rd Bus

Write Cycle

4th Bus

Write/Read

Cycle

5th Bus

Write Cycle

6th Bus

Sector Erase Resume

Note: CA: Chip Address. (address in chip selected by A21 for MB98C81333)

SA: Sector Address (address in 64 KB selected by A16, A17, A18, A19, A20 and A21) PA: Program Address (address to be programmed) RA: Read Address (address to be read) IA: Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)

PD: Programming data RD: Read data ID: Intelligent Identiﬁer (ID) Code

CCMA1, CCMA2: Command address for chip erase SCMA1, SCMA2: Command address for sector erase PCMA1, PCMA2: Command address for program RCMA1, RCMA2: Command address for Read/Reset ICMA1, ICMA2: Command address for Intelligent ID read

Write

CA 30H

See “Command Address Table for 8-bit Mode” in page 16.

MB98C81013/81123/81233/81333-10

Command Table for 16-bit Mode

To Top / Lineup / Index

Command

Read/Reset 1 2

Read/Reset 2 4

Read Intelligent ID Codes

Byte Program 4

Sector Erase 6

Chip Erase 6

Sector Erase Suspend

Bus

Cycle

1st Bus

Write Cycle

Write Read

CA F0F0H RA RD

Write Write Write Read

RCMA1 AAAAH RCMA2 5555H RCMA1 F0F0H RA RD

Write Write Write Read

ICMA1 AAAAH ICMA2 5555H ICMA1 9090H IA ID

Write Write Write Write

PCMA1 AAAAH PCMA2 5555H PCMA1 A0A0H PA PD

Write Write Write Write Write Write

SCMA1 AAAAH SCMA2 5555H SCMA1 8080H SCMA1 AAAAH SCMA2 5555H SA 3030H

Write Write Write Write Write Write

CCMA1 AAAAH CCMA2 5555H CCMA1 8080H CCMA1 AAAAH CCMA2 5555H CCMA1 1010H

Write

CA B0B0H

2nd Bus

Write/Read

Cycle

3rd Bus

Write Cycle

4th Bus

Write/Read

Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Sector Erase Resume

Note: CA: Chip Address. (address in chip selected by A21 for MB98C81333)

SA: Sector Address (address in 128 KB selected by A16, A17, A18, A19, A20 and A21) PA: Program Address (address to be programmed) RA: Read Address (address to be read) IA: Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)

PD: Programming data RD: Read data ID: Intelligent Identiﬁer (ID) Code

Write

CA 3030H

See “Command Address Table for 16-bit Mode” in page 16.

+ 33 hidden pages