The Fujitsu Flash Miniature cards conform to “Miniature Card Specification” pubulished by MCIF; Miniature Card
Implementers Forum.
The Fujitsu Flash Miniature cards are small form factor Flash memory cards targeted various markets; digital photography, audio recording, hand held PCs and other small portable equipments. Miniature cards’ high performance,
small size (38 mm × 33 mm × 3.5 mm), low cost and simple interface are ideal f or portable applications that require
high speed flash disk drives or eXecute In Place (XIP).
The Flash Miniature cards are 5 V -only oper ational and allow the users to use as ×8 or ×16 organization on low power
at high speed.
• Small size : 33.0 mm (length) × 38.0 mm (width) × 3.5 mm (thickness)
• +5 V ±5% power supply program and erase
• Command control for Automated Program/Automated Erase operation
• Erase Suspend Read/Program Capability (Only Erase Suspend Read is possible for MB98C81013)
• 128 KB Sector Erase (at ×16 mode)
• Any Combination of Sectors Erase and Full Chip Erase
• Detection of completion of program/erase operation with Data# Polling or Toggle bit.
• Ready/Busy Output with BUSY# (Except for MB98C81013)
• Reset Function with RESET# pin (Except for MB98C81013)
• Write protect function with WP switch
• Low VCC Write Inhibit
• AIS (Attribute Information Structure) is available from the address “0000H” of Lower Byte.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
■
■
MB98C81013/81123/81233/81333-10
PACKAGE
5 V - ONLY FLASH MINIATURE CARD
Flash Memory
8
M byte
5V OPERATION
(CRD-60P-M01)
WRITE PROTECT
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DESCRIPTIONS
DIFFERENCES
MB98C81013MB98C81123MB98C81233MB98C81333
Density1 MB2 MB4 MB8 MB
Memory Device4 M bit8 M bit16 M bit
Quantity2224
Read1 B unit
Program1 B unit
Chip Erase512 KB unit1 MB unit2 MB unit
Sector Erase64 KB unit
Number of Sectors163264128
Erase Suspend ReadYesYesYesYes
Erase Suspend ProgramNoYesYesYes
AddressA0 to A18A0 to A19A0 to A20A0 to A21
RESET#NoYesYesYes
BUSY#NoYesYesYes
* :A19, A20, A21 are “N.C.” for each product. See “DESCRIPTIONS”.
4
■
■
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MB98C81013/81123/81233/81333-10
PAD DESCRIPTIONS
SymbolI/OPad NameSymbolI/OPad Name
A0 to A
D0 to D
CEL#ICard Enable for Lower ByteVS1#, VS2#OVoltage Sense
CEH#ICard Enable for Upper ByteN.C.—Non Connection
OE#IOutput EnableV
WE#IWrite EnableGND—Ground
RESET#IHardware ResetCINS#OCard Insertion *
* :Take notice that those pads are connected internally.
Notes: *1. A19 is not availabe for MB98C81013. MB98C81013 has 8 sectors.
*2. A20 is not availabe f or MB98C81013 and MB98C81123. MB98C81013 has 8 sectors and MB98C81123
has 16 sectors.
8
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MB98C81013/81123/81233/81333-10
■ CHIP CONFIGURATION
The miniature cards use 2 or 4 pcs of Flash Memory. 2 pcs of Flash Memory are operated simultaneously at
16 bit mode and even number of chip is applied to lower byte and odd number of chip is applied to upper byte.
At ×8 bit mode, even address and odd address are selected with CEL# and CEH#.
× 16 bit mode
1
CEL# = “L”, CEH# = “L”
:
:
Odd Number of Chip + Even Number of Chip
Odd Number of Chip + Even Number of Chip
Odd Number of Chip + Even Number of Chip
Odd Number of Chip + Even Number of Chip
• • • • • • • • • • • • • • D0
D15
× 8 bit mode
2
CEL# = “H”, CEH# = “L”
:
:
odd Number of Chip
003h
CEL# = “L”, CEH# = “H”
even Number of Chip
003h
002h
001h
000h
:
:
003h
odd Number of Chip
odd Number of Chip
odd Number of Chip
D15
• • • • D8
002h
001h
000h
even Number of Chip
even Number of Chip
even Number of Chip
D7
• • • • • D0
002h
001h
000h
9
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MB98C81013/81123/81233/81333-10
■ FUNCTION DESCRIPTIONS
1. Read Mode
The data in the common can be read with “OE# = VIL ” and “WE# = VIH”. The address is selected with A0-A21.
And CEL# and CEH# select output mode.
2. Standby Mode
– CEL# and CEH# at “VIH” place the card in Standby mode. D0-D15 are placed in a high-Z state independent
of the status “OE#” and “WE#”.
3. Output Disable Mode
– The outputs are disabled with OE# and WE# at “VIH”. D0-D15 are placed in high-Z state.
4. Write Mode
– The card is in Write mode with “OE# = VIH” and “WE# and CE# = VIL”.
– Commands can be written at the Write mode.
– Two types of the Write mode, “WE# control” and “CE# control” are available.
5. Command Definitions
– User can select the card operation by wr iting the specific address and data sequences into the command
register. If incollect address and data are written or improper sequence is done, the card is reseted to read
mode. See “COMMAND DEFINISION TABLE”.
6. Automated Program Capability
– Programming operation can switch the data from “1” to “0”.
– The data is programmed on a byte-by-byte or word-by-word basis.
– The card will automatically provide adequate internally generated programming pulses and verify the pro-
grammed cell margin by writing four bus cycle operation. The card returns to Common Memory Read mode
automatically after the programming is completed.
– Addresses are latched at falling edge of WE# or CE# and data is latched at rising edge of WE# or CE#. The
fourth rising edge of WE# or CE# on the command write cycle begins programming operation.
– W e can check whether a byte (w ord) programming operation is completed successfully b y sequence flug with
BUSY# (except MB98C81013), Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.
– Any commands written to the chip during programming operation will be ignored.
7. Automated Chip Erase Capability
– W e can execute chip erase operation b y 6 bus cycle operation. Chip erase does not require the user to program
the chip prior to erase. Upon executing the Erase command sequence the chip automatically will program
and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timing during these operations.
– The card returns to Common Memory Read mode automatically after the chip erasing is completed.
– Whether or not chip erase oper ation is completed successfully can be checked b y sequence flug with BUSY#
(except MB98C81013), Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.
– Any commands written to the chip during programming operation will be ignored.
10
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MB98C81013/81123/81233/81333-10
8. Automated Sector Erase Capability
– We can execute the erase operation on any sectors by 6 bus cycle operation.
– A time-out of 50 µs (typ .) from the rising edge of the last Sector Erase command will initiate the Sector Erase
command(s).
– Multiple sectors in a chip can be erased concurrently . This sequence is f ollowed with writes of 30H to addresses
in other sectors desired to be concurrently erased. The time between writes 30H must be less than 50 µs,
otherwise that command will not be accepted. Any command other than Sector Erase or Erase Suspend
during this time-out period will reset the chip to Read mode. The automated sector erase begins after the 50
µs (typ.) time out from the rising edge of WE# pulse for the last Sector Erase command pulse. Whether the
sector erase window is still open can be monitored with D3 and D11.
– Sector Erase does not require the user to program the chip prior to erase. The chip automatically progr ams
“0” to all memory locations in the sector(s) prior to electrical erase. The system is not required to provide any
controls or timing during these operations.
– The card returns to Common Memory Read mode automatically after the chip erasing is completed.
– Whether or not sector erase operation is completed successfully can be checked by sequence flug with
BUSY#, Data# Polling or Toggle Bit function. The sequence flug must be read from the address of the sector
involved in erase operation. See “WRITE OPERATION STATUS”.
9. Erase Suspend
– Erase Suspend command allows the user to interrupt the sector erase operation and then do data reads or
program from or to a non-busy sector in the chip which has the sector(s) suspended erase (only data read is
possible for MB98C81013). This command is applicable only during the sector erase operation (including the
sector erase time-out period after the sector erase commands 30H) and will be ignored if written during the
chip erase or programming operation. Writing this command during the time-out will result in immediate
termination of the time-out period. The addresses are “don’t cares” in wrinting the Erase Suspend or Resume
commands in the chip.
– When the Erase Suspend command is written during a Sector Erase operation, the chip will enter the Erase
Suspend Read mode. User can read the data from other sectors than those in suspention. The read oper ation
from sectors in suspention results D2/D10 toggling except MB98C81013. User can program to non-busy sectors
by writing program commands except MB98C81013.
– A read from a sector being erase suspended may result in invalid data.
10. Intelligent Identifier (ID) Read Mode
– Each common memory can execute an Intelligent Identifier operation, initiated by writing Intelligent ID com-
mand (90H). Following the command write, a read cycle from address 00H retrieves the manufacture code,
and a read cycle from address 01H returns the device code as follows. To terminate the operation, it is
necessary to write Read/Reset command.
11. Hardware Reset (not applied for MB98C81013)
– The Card may be reset by driving the RESET# pin to VIL. The RESET# pin must be kept High (VIL) for at
least 500 ns. Any operation in progress will be terminated and the card will be reset to the read mode 20 µs
after the RESET# pin is driven Low. If a hardware reset occurs during a program operation, the data at that
particular location will be indeterminate.
– When the RESET# pin is Low and the internal reset is complete, the Card goes to standb y mode and cannot
be accessed. Also, note that all the data output pins are High-Z for the duration of the RESET# pulse. Once
the RESET# pin is taken high, the Card requires 500 ns of wake up time until outputs are v alid for read access.
– If hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be
used.
11
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MB98C81013/81123/81233/81333-10
12. Data Protection
– The card has WP (Write Protect) switch for write lockout.
– To avoid initiation of a write cycle during V
less than 3.2 V. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are
disabled.
Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC
level is greater than VLKO.It is the users responsibility to ensure that the control pins are logically correct to
prevent unintentional writes when VCC is above 3.2 V.
– If VCC would be less than VLKO during program/erase operation, the operation will stop. And after that, the
operation will not resume even if VCC returns recommended voltage le vel. Therefore , program command must
be written again because the data on the address interrupted program operation is invalid. And regarding
interrupting erase operation, there is possibility that the erasing sector(s) cannot be used.
– Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.
CC power-up and power-down, a write cycle is locked out for VCC
Note: CA: Chip Address.(address in chip selected by A21 for MB98C81333)
SA: Sector Address (address in 64 KB selected by A16, A17, A18, A19, A20 and A21)
PA: Program Address(address to be programmed)
RA: Read Address(address to be read)
IA: Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)
PD: Programming data
RD: Read data
ID: Intelligent Identifier (ID) Code
CCMA1, CCMA2: Command address for chip erase
SCMA1, SCMA2:Command address for sector erase
PCMA1, PCMA2:Command address for program
RCMA1, RCMA2: Command address for Read/Reset
ICMA1, ICMA2:Command address for Intelligent ID read
1
Write
CA30H
See “Command Address Table for 8-bit
Mode” in page 16.
Note: CA: Chip Address.(address in chip selected by A21 for MB98C81333)
SA: Sector Address (address in 128 KB selected by A16, A17, A18, A19, A20 and A21)
PA: Program Address(address to be programmed)
RA: Read Address(address to be read)
IA: Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)
PD: Programming data
RD: Read data
ID: Intelligent Identifier (ID) Code
CCMA1, CCMA2: Command address for chip erase
SCMA1, SCMA2:Command address for sector erase
PCMA1, PCMA2:Command address for program
RCMA1, RCMA2: Command address for Read/Reset
ICMA1, ICMA2:Command address for Intelligent ID read
1
Write
CA3030H
See “Command Address Table for 16-bit
Mode” in page 16.
Notes: *1. Performing successive read operations from the erase-suspended sector will cause D2, D10 to toggle.
*2. Performing successive read operations from any address will cause D6, D14 to toggle.
*3. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic ‘1’ at the D2, D10 bit. However, successive reads from the erase-suspended sector will cause D2,
D10 to toggle.
*4. Not applied for MB98C81013.
D7, D15 (Data# Polling)
The card features Data# Polling as a method to indicate to the host that the Program/Erase Operation are in
progress or completed. During the program operation an attempt to read the prog ram address will produce the
compliment of the data last written to D7/D15. Upon completion of the progr am operation, an attempt to read the
program address will produce the true data last written to D7/D15. During the erase operation, an attempt to read
the program address will produce a “0” at the D7/D15 output. Upon completion of the erase operation an attempt
to read the device will produce a “1” at the D7/D15 output.
For Chip Erase, the Data# Polling is valid after the rising edge of the sixth WE# pulse in the six write pulse
sequence. For sector erase, the Data# Polling is valid after the last rising edge of the sector erase WE# pulse.
Even if the device has completed the operation and D7/D15 has a valid data, the data outputs on D0 to D6/D8 to
D14 may be still invalid. The valid data on D0 to D7/D8 to D15 will be read on the successive read attempts.
The Data# Polling feature is only active during the programming operation, erase operation, sector erase timeout, Erase Suspend Read mode and Erase Supend Program mode.
D6, D14 (Toggle Bit I)
The card also features the “Toggle Bit” as a method to indicate to the host system that the Program/Erase
Operation are in progress or completed.
During an Program or Erase cycle, successive attempts to read (OE# or CE# toggling) data from the card will
result in D6/D14 toggling between one and zero. Once the Program or Erase cycle is completed, D6/D14 will stop
toggling and valid data will be read on the next successiv e attempts. During programming, the Toggle Bit is valid
after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the Toggle Bit is
valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the Toggle
Bit is valid after the last rising edge of the sector erase WE# pulse . The Toggle Bit is also active during the sector
time out.
Either CE# or OE# toggling will cause the D
6/D14 to toggle.
17
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MB98C81013/81123/81233/81333-10
D5, D13 (Exceeded Timing Limits)
D5/D13 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions D
cycle was not successfully completed. Data# Polling is the only operating function of the card under this condition.
If this failure condition occurs during sector erase operation, it specifies that a particular sector is bad and it may
not be reused, however, other sectors are still functional and may be used for the program or erase operation.
The chip must be reset to use other sectors. Write the Reset command sequence to the chip, and then e x ecute
Program or Erase command sequence. This allows the system to continue to use the other active sectors in
the chip.
If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination
of sectors are bad.
If this failure condition occurs during the byte programming operation, it specifies that the entire sector containing
that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused).
The D5/D13 failure condition may also appear if a user tries to program a non blank location without erasing. In
this case the card locks out and never completes the card operation. Hence, the system never reads a valid
data on D7/D15 bit and D6/D14 never stops toggling. Once the card has exceeded timing limits, the D5/D13 bit will
indicate a “1”. Please note that this is not a device failure condition since the device was incorrectly used.
5/D13 will produce a “1”. This is a failure condition which indicates that the program or erase
D3, D11 (Sector Erase Timer)
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3/D11
will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data# Polling or the Toggle Bit indicates the card has been wr itten with a valid erase command, D3/D11 may
be used to determine if the sector erase timer window is still open. If D3/D11 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the card will be ignored until the erase
operation is completed as indicated by Data# Polling or Toggle Bit. If D3/D11 is low (“0”), the card will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of D3/D11 prior to and following each subsequent sector erase command. If D3/D11 were high
on the second status check, the command may not have been accepted.
Refer to Table: Hardware Sequence Flags.
D2, D10 (Toggle Bit II, not applied for MB98C81013)
This Toggle bit, along with D6, can be used to determine whether the card is in the Erase operation or in Erase
Suspend.
Successive reads from the erasing sector will cause D2 to toggle during the Erase operation. If the card is in the
erase-suspended-read mode, successive reads from the erase-suspended sector will cause D2 to toggle . When
the card is in the erase-suspended-program mode, successive reads from the byte address of the non-erase
suspended sector will indicate a logic ‘1’ at the D2 bit.
D6 is different from D2 in that D6 toggles only when the standard Program or Erase , or Er ase Suspend Prog ram
operation is in progress.
BUSY# (Ready/Busy, not applied for MB98C81013)
The card provides a BUSY# open-drain output pin as a wa y to indicate to the system that the prog ram or er ase
operation are either in progress or has been completed. If the output is low , the card is busy with either a program
or erase operation. If the card is placed in an Erase Suspend mode, the BUSY# output will be high.
During programming, the BUSY# pin is driven low after the rising edge of the fourth WE# pulse . During an erase
operation, the BUSY# pin is driven low after the rising edge of the sixth WE# pulse. The BUSY# pin will indicate
a busy condition during the RESET# pulse.
18
MB98C81013/81123/81233/81333-10
■ PROGRAM/ERASE FLOWCHART
Fig. 3 — PROGRAM FLOWCHART
SET ADDRESS
PCMA1, PCMA2 *
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START
SET PA
PD : PROGRAM DATA
PA : PROGRAM ADDRESS
2
INCREMENT PA
WRITE COMMAND
(PCMA1/AAH or AAAAH) *
WRITE COMMAND
(PCMA2/55H or 5555H) *
WRITE COMMAND
(PCMA1/A0H/A0A0H) *
WRITE DATA (PA/PD)
DATA# POLLING,
TOGGLE BIT or
BUSY# *
(See Fig. 7, 8, 9, 10)
NO
LAST ADDRESS ?
COMPLETED
2
*1. Except MB98C81013
*2. See “COMMAND DEFINITION TABLE”.
2
2
1
YES
19
MB98C81013/81123/81233/81333-10
Fig. 4 — CHIP ERASE FLOWCHART
START
SET CA
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INCREMENT CA
SET ADDRESS
(CCMA1, CCMA2) *
2
WRITE COMMAND
(CCMA1/AAH or AAAAH) *
WRITE COMMAND
(CCMA2/55H or 5555H) *
WRITE COMMAND
(CCMA1/80H or 8080H) *
WRITE COMMAND
(CCMA1/AAH or AAAAH) *
WRITE COMMAND
(CCMA2/55H or 5555H) *
WRITE COMMAND
(CCMA1/10H or 1010H) *
DATA# POLLING,
TOGGLE BIT or
BUSY# *
1
(See Fig. 7, 8, 9, 10)
CA : CHIP ADDRESS
2
*1. Except MB98C81013
*2. See “COMMAND DEFINITION TABLE”.
2
2
2
2
2
20
YES
DESIRED OTHER
CHIPS ERASE ?
NO
COMPLETED
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MB98C81013/81123/81233/81333-10
Fig. 5 — SECTOR ERASE FLOWCHART
START
SET SA
SET ADDRESS SCMA1, SCMA2 *
WRITE COMMAND
(SCMA1/AAH or AAAAH) *
WRITE COMMAND
(SCMA2/55H or 5555H) *
WRITE COMMAND
(SCMA1/80H or 8080H) *
WRITE COMMAND
(SCMA1/AAH or AAAAH) *
WRITE COMMAND
(SCMA2/55H or 5555H) *
3
3
3
3
3
WRITE COMMAND
(SA/30H or 3030H)
DESIRED OTHER
SECTORS ERASE ?
2
*
NO
3
SA : SECTOR ADDRESS
*1. Except MB98C81013
*2. Possible for the sectors in a chip
*3. See “COMMAND DEFINITION TABLE”.
YES
WRITE COMMAND
(SA/30H or 3030H)
DATA# POLLING,
TOGGLE BIT or
BUSY# *
1
(See Fig. 7, 8, 9, 10)
COMPLETED
21
MB98C81013/81123/81233/81333-10
Fig. 6 — ERASE SUSPEND FLOWCHART
EXECUTING
SECTOR ERASE
WRITE COMMAND
(CA/B0H or B0B0H)
CA : CHIP ADDRESS
READ DATA (SA) *
1
SA : SECTOR ADDRESS
RA : READ ADDRESS
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Yes
No
Toggle
bit = Toggle? *
Read or Program *
STOP Erase
Suspend mode?
WRITE COMMAND
(CA/30H or 3030H)
FINISHED
1
No
Yes
*1. Detection whether suspend mode is valid
can be done by Data# Polling and BUSY#
also. (MB98C81013 does not have
BUSY#).
*2. Only Read operation for MB98C81013.
2
22
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MB98C81013/81123/81233/81333-10
Fig. 7 — DATA# POLLING FLOWCHART: x8 bit mode
*1. User sets the time period referring to “PROGRAM
AND ERASE PERFORMANCES”.
START
TIMER START *1
READ (VA) *
2
*2. ProgramVA = PA
Chip EraseVA = CA
Sector Erase VA = SA
5/D7 are for even chip(s).
*3. D
In the case of odd chip(s),
5→ D13 and D7→ D15 are applied.
D
No
D7 = Data? *
No
D
5 = 1 or Time-up?
3
*
Yes
READ (VA) *2
7 = Data? *
D
No
ERROR
Yes
3
Yes
3
COMPLETED
23
MB98C81013/81123/81233/81333-10
Fig. 8 — TOGGLE BIT FLOWCHART: x8 bit mode
*1. User sets the time period referring to “PROGRAM
START
TIMER START *1
READ (VA) *
2
AND ERASE PERFORMANCES”.
*2. ProgramVA = PA
Chip EraseVA = CA
Sector Erase VA = SA
5/D6 are for even chip(s).
*3. D
In the case of odd chip(s),
5→ D13 and D6→ D14 are applied.
D
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No
D
6 = T oggle? *
Yes
D
5 = 1 or Time-up?
3
*
Yes
READ (VA) *2
D6 = T oggle? *
Yes
ERROR
No
3
No
3
COMPLETED
24
MB98C81013/81123/81233/81333-10
Fig. 9 — DATA# POLLING FLOWCHART: x16 bit mode
START
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No
EF = 0
TIMER START *1
READ (VA) *
D
7 = Data?
No
D
5 = 1 or Time-up?
Yes
READ (VA) *
7 = Data?
D
No
EF = 1
*1. User sets the time period referring to “PROGRAM
AND ERASE PERFORMANCES”.
*2. ProgramVA = PA
Chip EraseVA = CA
Sector Erase VA = SA
2
EF:Error Flag
EF = 0: Operation Completed
EF = 1: Lower Byte Error
Yes
EF = 2: Upper Byte Error
EF = 3: Lower/Upper Byte Error
1
2
Yes
READ (VA) *
1
Yes
D15 = Data?
No
1
No
D
13 = 1 or Time-up?
Yes
READ (VA) *
2
Yes
15 = Data?
D
No
EF = EF+2
EF = 0?
No
Yes
COMPLETED
ERROR
25
MB98C81013/81123/81233/81333-10
Fig. 10 — TOGGLE BIT FLOWCHART: x16 bit mode
START
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No
EF = 0
TIMER START *1
READ (VA) *
6 = T oggle?
D
Yes
D
5 = 1 or Time-up?
Yes
READ (VA) *
D
6 = T oggle?
Yes
EF = 1
*1. User sets the time period referring to “PROGRAM
AND ERASE PERFORMANCES”.
*2. ProgramVA = PA
Chip EraseVA = CA
Sector Erase VA = SA
2
EF:Error Flag
EF = 0: Operation Completed
EF = 1: Lower Byte Error
EF = 2: Upper Byte Error
No
EF = 3: Lower/Upper Byte Error
1
2
1
READ (VA) *
No
No
14 = T oggle?
D
Yes
26
1
No
D
13 = 1 or Time-up?
Yes
2
READ (VA) *
No
D
14 = T oggle?
Yes
EF = EF+2
EF = 0?
No
Yes
COMPLETED
ERROR
MB98C81013/81123/81233/81333-10
■ ABSOLUTE MAXIMUM RATINGS *1
ParameterSymbolValueUnit
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Supply V oltageV
CC–0.5 to +6.0V
Input V oltageVIN–0.5 to VCC +0.5V
Output V oltageVOUT–0.5 to VCC +0.5V
Temperature under BiasTA0 to +60°C
Storage TemperatureTSTG–30 to +70°C
*1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Card Enable Access TimetCE100ns
Address Access TimetACC100ns
Output Enable Access TimetOE50ns
Card Enable to Output in Low-Z *
Card Disable to Output in High-Z *
Output Enable to Output in Low-Z *
Output Disable to Output in High-Z *
2
2
2
2
Output Hold from Address Changet
tCLZ5ns
tCHZ50ns
tOLZ5ns
tOHZ50ns
OH0ns
Ready Time from RESET#tRDY20µs
Notes: *1. Rise/Fall time < 5 ns.
*2. Transition is measured at the point of ±500 mV from steady state voltage.
29
MB98C81013/81123/81233/81333-10
PROGRAM/ERASE CYCLE
ParameterSymbolMinTypMaxUnit
To Top / Lineup / Index
Write Cycle Timet
WC100ns
Address Setup TimetAS10ns
Address Hold Timet
AH10ns
Data Setup TimetDS40ns
Data Hold TimetDH15ns
Read Recovery Time (WE# control)tGHWL10ns
Read Recovery Time (CE# control)tGHEL10ns
Output Enable Hold Time
Card Enable Setup Time t
OEH
t
CS20ns
20ns
Card Enable Hold TimetCH10ns
Write Enable Pulse WidthtWP60ns
Write Enable Setup TimetWS0ns
Write Enable Hold TimetWH10ns
Card Enable Pulse Widtht
Duration of Byte Program Operation
(/WE Control)
Duration of Erase Operation *
1
(/WE Control)
CP80ns
tWHWH18µs
t
WHWH2115s
Duration of Byte Program Operation
(/CE Control)
Duration of Erase Operation *
1
(/CE Control)
VCC Setup Time *
2
Reset Pulse Widtht
EHEH18µs
t
t
EHEH2115s
tVCS50µs
RP500ns
Busy Delay TimetBSY40ns
Notes: *1. These do not include the preprogramming time.
*2. CCMA1/CCMA2 = Command Address for Chip Erase, SCMA1/SCMA2 = Command Address f or Sector
Erase, SA = Sector Address. See “COMMAND DEFINITION TABLE”.
80H
(8080H)
AAH
(AAAAH)
55H
(5555H)
10H/30H
(1010H/3030H)
:Undefined
37
MB98C81013/81123/81233/81333-10
DATA# POLLING CYCLE TIMING DIAGRAM (RESET# = VIH)
To Top / Lineup / Index
Addresses
2
*
2
CE# *
OE#
WE#
D7, D15
2
*
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
IH/OH
V
VIL/OL
Command Write Cycle
tWC
D7, D15D7#, D15#D7, D15 Valid Data
tOEH
tWHWH1,2
EHEH1,2) *
(t
tACC
tCE
Data# Polling Read Cycle
1
VA *
tCHZ
tOE
4
*
3
tOHZ
D0-D6 *
D8-D14
2
VIL/OL
D0-D6,
D8-D14
D0-D6, D8-D14
Invalid Data
D0-D6, D8-D14
Valid Data
VIH/OH
Notes: *1. VA = PA for Programming Cycle, VA = SA for Sector Erase, VA = CA for Chip Erase.
*2. See “FUNCTION TRUTH TABLE”.
*3. tEHEH1,2 for CE# Control.
*4. Program/Erase operation is finished.
38
:Undefined
MB98C81013/81123/81233/81333-10
TOGGLE BIT TIMING DIAGRAM (RESET# = VIH)
Toggle Bit
Read Cycle
1
VA *
tRC
Addresses
2
*
2
CE# *
VIH
Command Write Cycle
VIL
VIH
VIL
VA *
To Top / Lineup / Index
1
VA *
1
VA *
1
OE#
WE#
Data *
2
VIH
VIL
VIH
VIL
VIH/OH
VIL/OL
tOEH
tOE
3
*
4
*
D6, D14
Toggle
D6, D14
Toggle
D6, D14
Stop
Valid Data
Toggling
:Undefined
Notes: *1. VA = PA for Programming Cycle, VA = SA for Sector Erase, VA = CA for Chip Erase.
*2. See “FUNCTION TRUTH TABLE”.
*3. Program/Erase operation is finished.
*4. PD, 10H (1010H) or 30H (3030H)
39
To Top / Lineup / Index
MB98C81013/81123/81233/81333-10
BUSY# Timing Diagram During Program/Erase Operations (except for MB98C81013)
CE#
WE#
BUSY#
RESET# Timing Diagram (except for MB98C81013)
RESET#
tRP
tRDY
Entire programming or
erase operation
tRSY
Possible next operation
40
■ UNIQUE FEATURES
Write Protect Switch
To Top / Lineup / Index
MB98C81013/81123/81233/81333-10
Write Protect Switch
“Protect”
“Non Protect”
Voltage Selection
The Miniature Card voltage is identified by both a mechanical key and voltage sense signals (VS1#, VS2#).
The combination of the two allow the host to determine the proper voltage required to operate the Miniature
Card, as well as a physical means to keep cards out of host systems that may damage the cards because of
improper operational voltage.
Six different voltage key combinations are defined in “Miniature Card Specification”: 5 volt only, 3.3 volt only,
x.x volt only, 3V/5V, x.xV/3V, and x.xV/3V/5V. These keys consist of notches in the Miniature Card and
corresponding tabs in the socket. The socket tabs are located in the front of the Miniature Card socket and
are used to keep out cards that do not contain the corresponding notch. See Voltage Keying Mechanism
below. (Now only defined about 5.0V and 3.3V)
Miniature Card
5V Only
Host
1
2
MB98C81013/
81123/81233/
81333 is
applied for this
Key
5V Only
Miniature Card
1
2
Host
3.3V/5V
Host
2
Miniature Card
1
2
3
4
1
2
3
4
3.3V/5V
Miniature Card
1
2
3
3.3V Only
Host
2
3
3.3V Only
Miniature Card
2
3
41
MB98C81013/81123/81233/81333-10
■ ATTRIBUTE INFORMATION STRUCTURE (AIS)
AddressDataAttribute
000001[Common Memory device information tuple]
000103Link to next tuple
000254Flash memory with 100ns access time
00030D1MB device size for common memory [MB98C81013]
1D2MB device size for common memory [MB98C81123]
0E4MB device size for common memory [MB98C81223]
1E8MB device size for common memory [MB98C81333]
0004FFEnd of list
05 - 0D00[Nulltuple-ignore]
000E80[Vendor unique tuple]
To Top / Lineup / Index
000FF1Link to next tuple
001099“Miniature Card Identifier”
001110“Level of Compliance”
00122F“AIS Checksum” (B00-AD1=2F) [MB98C81013]
011A69(i)
011B65(e)
011C73(s)
011D00
011EFFEnd of list
011F18[JEDEC programming information for Common Memory tuple]
012003Link to next tuple
012104JEDEC Manufacture ID (FUJITSU)
0122A4JEDEC Device ID (MB29F040A) [MB98C81013]
D5JEDEC Device ID (MB29F080) [MB98C81123]
3DJEDEC Device ID (MB29F017) [MB98C81233, MB98C81333]
0123FFEnd of list
01241E[Device geometry information for Common Memory device tuple]
012507Link to next tuple
45
MB98C81013/81123/81233/81333-10
■ ATTRIBUTE INFORMATION STRUCTURE (AIS) (continued)
AddressDataAttribute
012602System bus width is 2 Bytes
012711Erase block size is 64 KBytes
012801Read block size is 1 Bytes
012901Write block size is 1 Bytes
012A01No special partitioning requirements
012B01Non interleaved
012CFFEnd of list
012D12[Longlink to Common Memory]
012E05Link to next tuple
012F00
To Top / Lineup / Index
013000
013102
013200
0133FFEnd of list
0134FF[The end-of-chain tuple]
Notice:AIS is programed from the address “0000H” of Lo wer Byte. This AIS may be deleted on the driv er software
which does not consider AIS.
Target address; stored as an unsigned long, low-order byte first
46
■ PACKAGE DIMENSIONS
60-PIN MINIATURE CARD
(CASE No.: CRD-60P-M01)
To Top / Lineup / Index
MB98C81013/81123/81233/81333-10
33.00±0.13(1.299±.005)
2.50
(.098)
12.70(.500)
7.20(.283)
(.138±.005)
2.50(.098)TYP
C
1996 FUJITSU LIMITED K60001SC-1-1
3.00
(.118)
2.50(.098)MIN
1.52(.060)
"A"
15.24(.600)3.50±0.13
7.62(.300)
38.00±0.13
(1.496±.005)
0.77(.030)
Details of "A" part
0.50(.020)
1.85(.073)
TYP
2-R0.50(.020)
5.50(.217)
8.00(.315)
8.00(.315)
5.50(.217)
R1.00(.039)
0.85(.033)
2.70
(.106)
18.00
(.709)
1.68(.066)
4.58
(.180)
9.10
(.358)
18˚TYP
3.40±0.05
(.134±.002)
4.25(.167)TYP
3.25(.128)TYP
R0.15
(.006)
2.48
(.098)
"B"
Details of "B" part
1.25(.049)
MIN
1 PIN
4.125±0.05
(.162±.002)
3.81±0.08
(.150±.003)
33.00±0.13
(1.299±.005)
6.21±0.08
(.244±.003)
5.95(.234)
1.00(.039)TYP
0.50±0.036
(.020±.001)
1.60
(.063)
2.60
0.50±0.05
(.020±.002)
(.102)
Dimension mm (in inches)
47
MB98C81013/81123/81233/81333-10
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
To Top / Lineup / Index
F9703
FUJITSU LIMITED Printed in Japan
48
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
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