FUJITSU MB98A51121, MB98A51221, MB98A51321, MB98A51421, MB98A51521-17 DATA SHEET

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查询MB98A51121供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

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DS05-30334-1E

MEMORY

CMOS

MASK ROM CARD

PCMCIA Rel.2/JEIDA Ver.4 conformable

MB98A51121/51221/51321/51421/51521

MASK ROM CARD 2 M/4 M/8 M/16 M/32 M-BYTE

DESCRIPTION

This card is a PCMCIA and JEIDA-compliant 68-pin two-piece Mask ROM card with the 16-bit mask ROM being
installed on the common memory.

However, to use this card as PCMCIA Rel.2, JEIDA Ver.4, the card attribute information has to be stored in the
Mask ROM.

FEATURES

• External dimensions: 85.6 mm × 54.0 mm × 3.3 mm

• +5 V single power supply

• Usable in 8 bits × 16 bits configuration

• Complete static operation

• I/O level TTL compatible

• Output tri-state

• Complete capacitive load without pull-up resistor or pull-down resistor except CE

• 68-pin two-piece connector form

-17

1

and CE

2

.

PACKAGE

(CRD-68P-M04)

■

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MB98A51121

PRODUCT CLASS

Part Number Memory Device

MB98A51121 16-Mbit Mask ROM × 1 pcs 2 M × 8/1 M × 16
MB98A51221 16-Mbit Mask ROM × 2 pcs 4 M × 8/2 M × 16
MB98A51321 16-Mbit Mask ROM × 4 pcs 8 M × 8/4 M × 16
MB98A51421 16-Mbit Mask ROM × 8 pcs 16 M × 8/8 M × 16
MB98A51521 16-Mbit Mask ROM × 16 pcs 32 M × 8/16 M × 16

/

51221/51321/51421/51521

Memory Configuration

(word × bit)

-17

Access Time (ns) (max.)

170

2

■

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MB98A51121

PIN ASSIGNMENTS

(CONNECTOR SIDE)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

(CRD-68P-M02)

• Pin Name

Symbol I/O Pin Name

A0 to A25 I Address input
D0 to D15 I/O Data I/O
CE1, CE2 I Card enable
CD1, CD2 * O Card detection
VS1, VS2 O Voltage sense
REG I Attribute memory space select
OE I Output enable
WE I Write enable
BVD1, BVD2 * O Battery voltage detection
WP * O Write protect
VCC — Supply voltage (+5 V)
GND — Ground
N.C. — No connection

* :Those pins are internally connected; use care when

handling.

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

/

51221/51321/51421/51521

Pin No. Symbol Pin No. Symbol

1 GND 35 GND
2D3 36 CD1
3D4 37 D11
4D5 38 D12
5D6 39 D13
6D7 40 D14
7CE1 41 D15
8A10 42 CE2

9OE 43 VS1 *
10 A11 44 N.C.
11 A9 45 N.C.
12 A8 46 A17
13 A13 47 A18
14 A14 48 A19 *
15 WE/N.C. * 49 A20 *
16 N.C. 50 A21/N.C. *
17 VCC 51 VCC
18 N.C. 52 N.C.
19 A16 53 A22/N.C. *
20 A15 54 A23/N.C. *
21 A12 55 A24/N.C. *
22 A7 56 A25/N.C. *
23 A6 57 VS2 *
24 A5 58 N.C.
25 A4 59 N.C.
26 A3 60 N.C.
27 A2 61 REG/N.C. *
28 A1 62 BVD2
29 A0 63 BVD1
30 D0 64 D8
31 D1 65 D9
32 D2 66 D10
33 WP 67 CD2
34 GND 68 GND

* :Whether a pin is an address pin or N.C. pin depends

on the type of the models. See ■ DIFFERENCE OF
PIN FUNCTIONS.

-17

3

■

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MB98A51121

DIFFERENCE OF PIN FUNCTIONS

Part Name A21 A22 A23 A24 A25 REG WE VS1 VS2

MB98A51121 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
MB98A51221
MB98A51321
MB98A51421

/

51221/51321/51421/51521

21

A

A22

A23MB98A51521 A24

-17

4

MB98A51121/51221/51321/51421/51521-17

■ BLOCK DIAGRAM

1. 16-Mbit Mask ROM × 1/× 2/× 4 Being Mounted

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Symbol

CE
CE2

OE

REG

WE

N.C.

D0 to D7

D8 to D15

A0

A21

A22

A23
A24

A25

WP

A1 to A20

V CC

BVD1
BVD2

VS1
VS2

CD1
CD2

GND

*1

10 kΩ

100 kΩ

I/O buffer

M0

V CC

OE

O1 to O8
O9 to O16

CE

A0 to A19

V SS

*2: 16-Mbit Mask ROM

M1

V CC

OE

O1 to O8
O9 to O16

CE

A0 to A19

V SS

M2

OE

O
O9 to O16

CE

A0 to A19

V CC

1 to O8

V SS

M3

V CC

OE

O1 to O8
O9 to O16

CE

A0 to A19

V SS

100 kΩ

1

*1, *2: Varies with the type of models.

Part Number A21 A22 M0 M1 M2 M3

MB98A51121 N.C. N.C. M0 — — —
MB98A51221 A21 N.C. M0 M1 — —
MB98A51321 A21 A22 M0 M1 M2 M3

5

MB98A51121/51221/51321/51421/51521-17

2. 16-Mbit Mask ROM × 8/× 16

*2: 16-Mbit Mask ROM

Symbol

CE1
CE2

A22
A23
A24

A25

A1 to A21

REG

WE

N.C.

VS1
VS2

100 kΩ

A0

*1

100 kΩ

I/O buffer

M0

V CC

OE

CE

0 to A20

A
O1 to O8

V SS

M1

V CC

M2

V CC

OE

CE

A

0 to A20

O1 to O8

V SS

M3

V CC

M4

V CC

OE

CE

A

0 to A20

O1 to O8

V SS

M5

V CC

M6

V CC

OE

CE

A

0 to A20

O1 to O8

V SS

M7

V CC

M8

V CC

OE

CE

A

0 to A20

O1 to O8

V SS

M9

V CC

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M10

M11

V CC

OE

CE

A

0 to A20

O1 to O8

V SS

V CC

M12

V CC

OE

CE

A

0 to A20

O1 to O8

V SS

M13

V CC

M14

V CC

OE

CE

A

0 to A20

O1 to O8

V SS

M15

V CC

OE

OE

OE

OE

OE

OE

OE

OE

OE

D0 to D7

D8 to D15

WP

I/O buffer

CE

CE

CE

CE

CE

CE

V CC

CE

CE

10 kΩ

BVD1
BVD2

0 to A20

A
O1 to O8

V SS

0 to A20

A
O1 to O8

V SS

0 to A20

A

O1 to O8

V SS

0 to A20

A
O1 to O8

V SS

0 to A20

A
O1 to O8

V SS

0 to A20

A

O1 to O8

V SS

0 to A20

A
O1 to O8

V SS

0 to A20

A
O1 to O8

V SS
CD1
CD2

GND

*1, *2: Varies with the type of models.

Part Number A22 A23 A24 M0/1 M2/3 M4/5 M6/7 M8/9 M10/11 M12/13 M14/15

MB98A51421 A22 A23 N.C. M0/1 M2/3 M4/5 M6/7 — — — —
MB98A51521 A22 A23 A24 M0/1 M2/3 M4/5 M6/7 M8/9 M10/11 M12/13 M14/15

6

MB98A51121/51221/51321/51421/51521-17

■ FUNCTIONAL TRUTH T ABLE

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CE

2 CE1

HH×× Standby High-impedance High-impedance

×××H Output disable High-impedance High-impedance

H L L L Read (× 8 bit) High-impedance

HLHL Read (× 8 bit) High-impedance

LH×L Read (× 8 bit)

LL×L Read (× 16 bit)

H: High level, L: Low level, ×: Don’t care

A0

(BYTE)

OE Operating Mode

Output Pin

(D8 to D15)

Output data
(odd bytes)

Output data
(odd bytes)

Output Pin

(D0 to D7)

Output data

(even bytes)

Output data
(odd bytes)

High-impedance

Output data

(even bytes)

7

MB98A51121/51221/51321/51421/51521-17

■ ABSOLUTE MAXIMUM RATINGS (See WARNING)

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Parameter Symbol

Max. Min.

Supply Voltage * VCC –0.3 +6.0 V
Input V oltage * VIN –0.3 VCC + 0.3 V
Output Voltage * VOUT –0.3 VCC + 0.3 V
Ambient Temperature TA –10 +60 °C

Storage Temperature Tstg –30 +70 °C
* :The voltage values are with reference to GND = 0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Value

Unit

■ RECOMMENDED OPERATING CONDITIONS

Parameter Symbol

Min. Typ. Max.

VCC 4.75 5.0 5.25 V

Supply Voltage *

GND — 0 — V
High Level Input Voltage * VIH 2.4 — VCC + 0.3 V
Low Level Input Voltage * VIL –0.3 — 0.8 V
Ambient Temperature TA 0 — +55 °C

Value

Unit

* :The voltage values are with reference to the GND = 0 V.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.

8

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MB98A51121/51221/51321/51421/51521-17

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

(On the recommended conditions)

Parameter Notes Symbol Test Conditions

I

SB1

Standby Supply Current

ISB2

Averaging Operation Supply
Current

Input Leak Current *1 ILI VIN = 0 V to VCC –40 ±0.1 40 µA
Output Leak Current *2 ILO
High Level Output Voltage *2 VOH IOH = –1 mA 2.4 — — V

Low Level Output Voltage *2 VOL IOL = 2.1 mA — — 0.4 V

ICC

CE1, CE2 VCC –0.2 V
IOUT = 0 mA

CE1, CE2 = VIH
IOUT = 0 mA

Cycle = min.
Duty cycle = 100%
IOUT = 0 mA, OE = VIH
VIN = VIH or VIL

VOUT = 0 V to VCC,
CE1, CE2 = VIH or OE = VIH

≥

Min. Typ. Max.

Value

Unit

— 10 1600 µA

— — 10 mA

— — 220 mA

–10 — 10 µA

Notes: *1. Excluding CE

*2. Excluding WP, BVD1, BVD2, CD

1 and CE2 pins.

1 and CD2 pins.

2. AC Characteristics

(1) Common Memory read cycle

(On the recommended conditions)

Parameter Notes Symbol Test Conditions

Read Cycle Time t
Address Cycle Time tACC
Card Enable Access Time tCE OE = VIL — 170 ns

Output Enable Access Time *1 tOE CEX = VIH, VIL —75ns
Output Disable Time *2 tDF — — 60 ns

Output Hold Time tOH

Notes: *1. The maximum delay of OE is tACC – tOE within the ranges in which the tACC is not affected.

*2. tDF is determined by either CEX or OE, whichever is faster with rise time.

The decision level is determined by the time the output is in a high-impedance state.

RC — 170 — ns

CEX = VIH, VIL
OE = VIL

CEX = VIH, VIL
OE = VIL

Value

Unit

Min. Max.

— 170 ns

0—ns

9

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MB98A51121/51221/51321/51421/51521-17

3. Input/output T erminal Capacitance

(VIN, VOUT = GND, f = 1 MHz, TA = +25°C)

Parameter Notes Symbol

Min. Max.

Input Terminal Capacitance *1 CIN —75pF
Output Terminal Capacitance *2 CI/O —50pF

Value

Unit

Notes: *1. Excluding CE

*2. Excluding WP, BVD1, BVD2, CD1, and CD2 pins.

1 and CE2 pins.

4. AC Characteristics Test Conditions

Input voltage : VIH = 2.6 V, VIL = 0.6 V
Input pulse rise time, fall time : tr, tf = 5 ns (0.8 V to 2.4 V)
Timing measurement reference voltage : Input : VIH = 2.4 V

: VIL = 0.8 V

: Output : VOH = 2.2 V

: VOL = 0.8 V

Output load : 1TTL + CL (100 pF)

• Output load circuit

CL

10

MB98A51121/51221/51321/51421/51521-17

■ TIMING DIAGRAM

1. Common Memory Read Cycle

× 8 bit (CE2 = VIH)

IH

Address

V
VIL

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t RC

t ACC

CE1

OE

Data Output

(D0 to D7)

VIH
VIL

VIH
VIL

OH

V
VOL

tDF is determined by either OE or CE1, whichever is faster with rise time.

*:

The decision level is determined by the time the output is in a high-impedance state.

× 8 bit (CE1 = VIH)

V

Address

CE2

OE

VIL

VIH
VIL

V
VIL

IH

IH

High-impedance state

A0 is ineffective; do not leave it open, however.

t ACC

t CE

t OE

Stabilized output period

t RC

t CE

t OE t DF*

t DF*

t OH

Data Output

(D8 to D15)

OH

V
VOL

tDF is determined by either OE or CE2, whichever is faster with rise time.

*:

The decision level is determined by the time the output is in a high-impedance state.

High-impedance state

Stabilized output period

t OH

(Continued)

11

MB98A51121/51221/51321/51421/51521-17

(Continued)

× 16 bit (CE1CE2)

t RC

V

Address

VIL

IH

A 0 is ineffective; do not leave it open, however.

t ACC

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CE1
CE2

OE

Data Output

(D0 to D15)

VIH
VIL

t CE

V

IH

VIL

t OE t DF *

V

OH

VOL

tDF is determined by either OE or CE1 = CE2, whichever is faster with rise time.

*:

The decision level is determined by the time the output is in a high-impedance state.

High-impedance state

Stabilized output period

t OH

12

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MB98A51121/51221/51321/51421/51521-17

■ DATA RELEASE METHOD

Data release is accepted by the 8-Mbit EPROM (1 Mword × 8 bits).
To prevent erroneous writing of data, provide three samples per piece of data. Also indicate the card memory

address for writing.

• Mapping between release data EPROM address and memory card address
(16 Mbit Mask ROM × 1/ × 2/ × 4 being mounted)

The range of the address for the MB98A51121 is 000000 to 1FFFFF (2 Mbytes).
The range of the address for the MB98A51221 is 000000 to 3FFFFF (4 Mbytes).
The range of the address for the MB98A51321 is 000000 to 7FFFFF (8 Mbytes).

<Byte

address>

3FFFFF

•••

300002
300001
300000

2FFFFF

•••

200002
200001
200000

<Byte

address>

1FFFFF

•••

100002
100001
100000

Mask ROM No.1

FFFFF

•••

8 M
EPROM

00002
00001

No.3

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.2

00000

D7 to D0

D7 to D0

Mask ROM No.0

FFFFF

•••

8 M
EPROM

00002
00001

No.1

00000

0 = H (Upper bytes D15 to D8)

A

A0 = L (Lower bytes D7 to D0)
A0 = H (Upper bytes D15 to D8)
A0 = L (Lower bytes D7 to D0)

A

0 = H (Upper bytes D15 to D8)

A0 = L (Lower bytes D7 to D0)
A0 = H (Upper bytes D15 to D8)
A0 = L (Lower bytes D7 to D0)

0 = H (Upper bytes D15 to D8)

A

A0 = L (Lower bytes D7 to D0)
A0 = H (Upper bytes D15 to D8)
A0 = L (Lower bytes D7 to D0)

7FFFFF

•••

700002
700001
700000

6FFFFF

•••

600002
600001
600000

5FFFFF

•••

500002
500001
500000

Mask ROM No.3

FFFFF

•••

8 M
EPROM

00002
00001

No.7

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.7

00000

D7 to D0

D7 to D0

Mask ROM No.2

FFFFF

•••

8 M
EPROM

00002
00001

No.5

00000

0 = H (Upper bytes D15 to D8)

A

A0 = L (Lower bytes D7 to D0)
A0 = H (Upper bytes D15 to D8)
A0 = L (Lower bytes D7 to D0)

A

0 = H (Upper bytes D15 to D8)

A0 = L (Lower bytes D7 to D0)
A0 = H (Upper bytes D15 to D8)
A0 = L (Lower bytes D7 to D0)

0 = H (Upper bytes D15 to D8)

A

A0 = L (Lower bytes D7 to D0)
A0 = H (Upper bytes D15 to D8)
A0 = L (Lower bytes D7 to D0)

0FFFFF

•••

000002
000001
000000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.0

D7 to D0

D7 to D0

A

0 = H (Upper bytes D15 to D8)

A0 = L (Lower bytes D7 to D0)
A0 = H (Upper bytes D15 to D8)
A0 = L (Lower bytes D7 to D0)

4FFFFF

•••

400002
400001
400000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.4

D7 to D0

D7 to D0

A

0 = H (Upper bytes D15 to D8)

A0 = L (Lower bytes D7 to D0)
A0 = H (Upper bytes D15 to D8)
A0 = L (Lower bytes D7 to D0)

(Continued)

13

MB98A51121/51221/51321/51421/51521-17

• Mapping between release data EPROM address and memory card address
(16 Mbit Mask ROM × 8/× 16 being mounted)

The range of the address for the MB98A51421 is 000000 to FFFFFF (16 Mbytes).
The range of the address for the MB98A51521 is 0000000 to1FFFFFF (32 Mbytes)

To Top / Lineup / Index

<Byte

address>
03FFFFF

•••

0200005
0200003
0200001

01FFFFF

•••

0000005
0000003
0000001

<Byte

address>

Mask ROM No.1

0 = H

A

(Upper bytes D

FFFFF

•••

8 M
EPROM

00002
00001

No.3

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.2

00000

D7 to D0

D7 to D0

Mask ROM No.0

0 = L

A

(Lower bytes D

15 to D8)

05FFFFF

7 to D0)

07FFFFF

•••

0600005
0600003
0600001

•••

0400005
0400003
0400001

Mask ROM No.3

0 = H

A

(Upper bytes D

FFFFF

•••

8 M
EPROM

00002
00001

No.7

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.6

00000

D7 to D0

D7 to D0

Mask ROM No.2

0 = L

A

(Lower bytes D

15 to D8)

0BFFFFF

09FFFFF

7 to D0)

•••

0A00005
0A00003
0A00001

•••

0800005
0800003
0800001

Mask ROM No.5

0 = H

A

(Upper bytes D

FFFFF

•••

8 M
EPROM

00002
00001

No.11

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.10

00000

D7 to D0

D7 to D0

Mask ROM No.4

0 = L

A

(Lower bytes D

15 to D8)

0FFFFFF

0DFFFFF

0C00005
0C00003
0C00001

7 to D0)

•••

0E00005
0E00003
0E00001

•••

Mask ROM No.7

0 = H

A

(Upper bytes D

FFFFF

•••

8 M
EPROM

00002
00001

No.15

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.14

00000

D7 to D0

D7 to D0

Mask ROM No.6

0 = L

A

(Lower bytes D

15 to D8)

7 to D0)

14

03FFFFE

•••

0200004
0200002
0200000

01FFFFE

•••

0000004
0000002
0000000

FFFFF

•••

00002
00001
00000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.1

8 M
EPROM

No.0

D7 to D0

D7 to D0

07FFFFE

•••

0600004
0600002
0600000

05FFFFE

•••

0400004
0400002
0400000

FFFFF

•••

00002
00001
00000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.5

8 M
EPROM

No.4

D7 to D0

D7 to D0

0BFFFFE

•••

0A00004
0A00002
0A00000

09FFFFE

•••

0800004
0800002
0800000

FFFFF

•••

00002
00001
00000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.9

8 M
EPROM

No.8

D7 to D0

D7 to D0

0FFFFFE

•••

0E00004
0E00002
0E00000

0DFFFFE

•••

0C00004
0C00002
0C00000

FFFFF

•••

00002
00001
00000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.13

8 M
EPROM

No.12

D7 to D0

D7 to D0

(Continued)

(Continued)

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MB98A51121/51221/51321/51421/51521-17

<Byte

address>
13FFFFF

•••

1200005
1200003
1200001

11FFFFF

•••

1000005
1000003
1000001

<Byte

address>

Mask ROM No.9

0 = H

A

(Upper bytes D

FFFFF

•••

8 M
EPROM

00002
00001

No.19

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.18

00000

D7 to D0

D7 to D0

Mask ROM No.8

0 = L

A

(Lower bytes D

15 to D8)

7 to D0)

17FFFFF

•••

1600005
1600003
1600001

15FFFFF

•••

1400005
1400003
1400001

Mask ROM No.11

0 = H

A

(Upper bytes D

FFFFF

•••

8 M
EPROM

00002
00001

No.23

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.22

00000

D7 to D0

D7 to D0

Mask ROM No.10

0 = L

A

(Lower bytes D

15 to D8)

1BFFFFF

19FFFFF

7 to D0)

•••

1A00005
1A00003
1A00001

•••

1800005
1800003
1800001

Mask ROM No.13

0 = H

A

(Upper bytes D

FFFFF

•••

8 M
EPROM

00002
00001

No.27

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.26

00000

D7 to D0

D7 to D0

Mask ROM No.12

0 = L

A

(Lower bytes D

15 to D8)

1DFFFFF

7 to D0)

1FFFFFF

•••

1E00005
1E00003
1E00001

•••

1C00005
1C00003
1C00001

Mask ROM No.15

0 = H

A

(Upper bytes D

FFFFF

•••

8 M
EPROM

00002
00001

No.31

00000

FFFFF

•••

8 M
EPROM

00002
00001

No.30

00000

D7 to D0

D7 to D0

Mask ROM No.14

0 = L

A

(Lower bytes D

15 to D8)

7 to D0)

13FFFFE

•••

1200004
1200002
1200000

11FFFFE

•••

1000004
1000002
1000000

FFFFF

•••

00002
00001
00000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.17

8 M
EPROM

No.16

D7 to D0

D7 to D0

17FFFFE

•••

1600004
1600002
1600000

15FFFFE

•••

1400004
1400002
1400000

FFFFF

•••

00002
00001
00000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.21

8 M
EPROM

No.20

D7 to D0

D7 to D0

1BFFFFE

•••

1A00004
1A00002
1A00000

19FFFFE

•••

1800004
1800002
1800000

FFFFF

•••

00002
00001
00000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.25

8 M
EPROM

No.24

D7 to D0

D7 to D0

1FFFFFE

•••

1E00004
1E00002
1E00000

1DFFFFE

•••

1C00004
1C00002
1C00000

FFFFF

•••

00002
00001
00000

FFFFF

•••

00002
00001
00000

8 M
EPROM

No.29

8 M
EPROM

No.28

D7 to D0

D7 to D0

15

To Top / Lineup / Index

MB98A51121/51221/51321/51421/51521-17

■ AUXILIARY CAPABILITIES

1. Card Detection Pins (CD1, CD2)

These pins verify a card is correctly inserted into the system.
The two pins are internally connected to the ground; with the system side connection being pulled up to the VCC,

detection of the voltage of these pins allows the system to check the state of connectivity of a card (See the
diagram below).

V cc

A

V cc

B

System side Card side

CD1

CD2

2. Write Protection Pin (WP)

The Mask ROM Card, whose common memory is write-protected, outputs a high-level write-protection signal.

16

To Top / Lineup / Index

MB98A51121/51221/51321/51421/51521-17

■ DEVICE HANDLING PRECAUTIONS

The device in composed of fine electronic parts, so take care in handling or keeping it as below.

• The card is made fine, so do not keep it in the high temperature nor high humiditly, place line in the direct sun­shine nor near the heater.

• The card should not be bent, scratched, dropped nor be shocked violently.

• This device should never be taken a part. It could destroy the card or your personal computer hardware.

• To help you handle this device safely, request us the device specifications when purchasing this device.

17

MB98A51121/51221/51321/51421/51521-17

■ PACKAGE DIMENSIONS

68-pin Memory Card

(CRD-68P-M02)

Note: Dimensions conform with PCMCIA/JEIDA

To Top / Lineup / Index

1.60±0.05

(.063±.002)

41.91

(1.650)

REF

"A"

1.00±0.05

(.039±.002)

Details of "A" part

1.00±0.05

(.039±.002)

1.00±0.05

(.039±.002)

2-R0.50(.020)

1PIN1.27±0.10(.050±.004)TYP

1.27±0.10

(.050±.004)

85.60±0.20(3.370±.008)

10.50(.413)

10.50(.413)

Details of "B" part Details of "C" part

1.00(.039) 6.00(.236)

"C"

"B"

CONNECTOR PORTION

2-R2.00(.079)

54.00±0.10

(2.126±.004)

3.30±0.20(.130±.008)3.30±0.10(.130±.004)

CARD BODY

18

C

1994 FUJITSU LIMITED K68002SC-5-1

Dimensions in mm (inches)

MB98A51121/51221/51321/51421/51521-17

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: [phone]
Fax: [phone]

North and South America

FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: [phone]
Fax: [phone]

Europe

FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: [phone]
Fax: [phone]

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: [phone]
Fax: [phone]

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All Rights Reserved.

The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

F9704

 FUJITSU LIMITED Printed in Japan

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.

19