Fujitsu MB91401 User Manual

FUJITSU SEMICONDUCTOR

Prelminary

2004.11.12

DATA SHEET

32-Bit Proprietary Microcontroller

LSI Network Security System MB91401

DESCRIPTION

■■■■

The MB91401 is a network security LSI incorporating a Fujitsu’s 32-bit, FR-family RISC microcontroller with 10/ 100Base-T MAC Controller, encr yption function and authentication function. The LSI contains an encryption authentication hardware accelerator that boosts the LSI’ s perf ormance for encryption and authentication communication (IKE/IPsec/SSL) to be demanded further.

The MAC controller has a packet filtering function that reduces the load on the CPU for an increasing amount of packet processing. In addition, the board has the External interface for high-speed data communication with various external hosts, USB ports as general-purpose interfaces, and various card interfaces.

FEATURES

■■■■

••••

Encryption and authentication processing by hardware accelerator function

The LSI performs processing five times f aster than b y the con v entional combination of encryption/authentication hardware macros and software or about 400 times f aster than by softw are only. In addition, CPU processing load factor to be involved in the encryption and the authentication processing can be decreased to 1/5 or less. Also, the LSI uses the embedded accelerator to execute that public-key encr yption algorithm about 100 times faster than by software processing, which generally puts an extremely heavy load microcontrollers.

(Continued)

PACKAGE

■■■■

244-pin plastic FBGA

(BGA-240P-M01)

MB91401

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• For DES-ECB/DES-CBC/3DES-ECB/3DES-CBC mode*

• For MD5/SHA-1/HMAC-MD5/HMAC-SHA-1 mode

• DH group: for 1 (MODP 768 bit) /2 (1024 bit) For the encryption/authentication macros, a software library is available by contacting the Fujitsu sales repre-

sentative as required.

* : Encryption function (DES/3DES)

Method to encrypt, and to decrypt plainte xt in 64 bits with code and decoding ke y to 56 bits . (3DES is repeated three times. The key can be set by 168 bits or less.)

•

Packet filtering function

The internal feature for L3/L4 packet filtering lets specific data pass or halts them based on address (IP/MAC address) settings. Moreover, the function (multicast address filter function) to receive the data is provided in case of the multicast address registered besides my address, too.

• IEEE 802.3 compliant 10/100M MAC

• MII interface (for full-duplex/half-duplex)

• SMI interface for PHY device control

Note : The filtering function of layer 3/4 (mount on hardware).

This feature determines whether to pass or discard packets when this la yer 3 (network layer) IP addresses or layer 4 (tra nsport layer) TCP/UDP port numbers match conditions.

••••

Outside interface with telecommunication facility (EXTERNAL INTERFACE)

MB91401 is equipped it with the register for the communication and with mass sending and receiving FIFO that achieves a large amount of data sending and receiving. Host functions include processing of data stored in a 3 KByte receive buff er and a 1.5 KByte transmit b uff er and stopping of data reception. when the buff ers become full. This enables communication control even during data transmission and reception, thereby improving communication efficiency while reducing the CPU load.

• 8/16 bit data port

• Equipped with sending and receiving data port control function

• Transfer rate : 133 Mbps (Max)

••••

General Purpose IO (GPIO)

The interruption can be generated in the I/O port in eight bits according to changing the input signal. Moreover, the I/O setting can be done in each bit.

••••

Memory Interface

It is possible to connect it with an external memory.

••••

USB Function Controller

It can not operate as host USB.

• For USB FUNCTION Rev2.0FS

• Double Buffer Specification

(Continued)

MB91401

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(Continued)

••••

CARD Interface (CompactFlash)

The CompactFlash interface is a memory and I/O mode correspondence. It corresponds to the I/O of data such as not only the memory card but also the communication cards.

••••

C Interface

• Master/slave sending and receiving

• For standard mode (100 Kbps Max)

MB91401

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PIN ASSIGNMENT

■■■■

INDEX

3 4 5 6 7 8 9 10111213141516171819

A B C D E F G H

W 2122232425262728293031323334353637

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

89 2019

70 135 192

193

194 195 196 197

198

199 200

201

202 203 204

205

152

69 134 191 240

206 153

68 133 190 239

207 154

67 132 189 238

208 155

131

130

188

187

237

236

(TOP-VIEW) (SUB240W)

209

210

156

157

64 129 186 235

211 158

63 128 185 234

212 159

62 127 184

233

213

160

61 126 183 232

214 161 100

60 125 182 231

215 162 101

59 124 181 230

216 163 102

58 123 180

229

228 227 226

225

224 223 222

221

220 219 218

217

164 103

57 122 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 104

56 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38

: signal (204 lines) : PLLVDD (1 line)

: PLLVSS (1 line) : VDDI (12 lines)

: VDDE (9 lines) : VSS (16lins)

199

197 195, 200, 203, 207, 211, 215, 1219, 223

227, 231, 235, 239 83, 196, 202, 208, 214, 220, 226, 232, 238 1, 19, 37, 55, 193, 198, 201, 205, 209

213, 217, 225, 229, 233, 237

■■■■

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MB91401

PIN NUMBER TABLE

Pin Number Pin name Pin Number

1 VSS 61 UDP 121 EXD11 181 SDA 2 CFD15 62 CFWEX 122 EXD14 182 USBINS 3 ICLK 63 CFCE1X 123 CFCD2X 183 UDM 4 ICS0 64 CFIORDX 124 UCLKSEL 184 CFRESET 5 TDI 65 CFA1 125 CFWAITX 185 CFREGX 6 UCLK48 66 CFA5 126 N.C. 186 CFA0 7 TMS 67 CFA8 127 CFOEX 187 CFA3 8 XINI 68 CFD0 128 CFCE2X 188 CFA7

9 PLLBYPAS 69 CFD3 129 CFIOWRX 189 CFA10 10 OSCEB 70 CFD7 130 CFA2 190 CFD2 11 TEST0 71 CFD10 131 CFA6 191 CFD5 12 OSCEA 72 CFD13 132 CFA9 192 CFD9 13 TEST2 73 CFD14 133 CFD1 193 VSS 14 SCK0 74 ICS2 134 CFD4 194 ICD2 15 SIN0 75 ICS1 135 CFD8 195 VDDI 16 INT5 76 BREAKI 136 CFD11 196 VDDE 17 A3 77 CLKSEL 137 CFD12 197 PLLVSS 18 A2 78 TRST 138 ICD0 198 VSS 19 VSS 79 MDI0 139 ICD1 199 PLLVDD 20 A4 80 MDI2 140 ICD3 200 VDDI 21 A7 81 PLLSET0 141 TDO 201 VSS 22 A10 82 TEST1 142 MDI1 202 VDDE 23 A13 83 VDDE 143 VPD 203 VDDI 24 A16 84 TEST3 144 PLLSET1 204 INITXI 25 MCLKO 85 SIN1 145 OSCC 205 VSS 26 A21 86 SOUT0 146 TCK 206 NMIX 27 RDX 87 INT6 147 PLLS 207 VDDI 28 WRX2 88 A6 148 SCK1 208 VDDE 29 CSX0 89 A5 149 SOUT1 209 VSS 30 N.C. 90 A8 150 INT7 210 A0 31 D0 91 A11 151 A9 211 VDDI 32 D2 92 A14 152 A12 212 A1 33 D5 93 A17 153 A15 213 VSS 34 D9 94 A19 154 A18 214 VDDE 35 D12 95 A22 155 A20 215 VDDI 36 D15 96 WRX3 156 A23 216 D8 37 VSS 97 WRX1 157 RDY 217 VSS 38 D17 98 CSX1 158 WRX0 218 D26 39 D18 99 N.C. 159 CSX6 219 VDDI 40 D20 100 D1 160 N.C. 220 VDDE 41 D23 101 D3 161 N.C. 221 VSS 42 D27 102 D6 162 D4 222 MDCLK 43 TXEN 103 D10 163 D7 223 VDDI 44 TXD0 104 D13 164 D11 224 MDIO 45 RXD0 105 D16 165 D14 225 VSS 46 TXCLK 106 D19 166 D22 226 VDDE 47 RXD2 107 D21 167 D25 227 VDDI 48 RXCLK 108 D24 168 D29 228 EXD3/GPIO3 49 EXIS16 109 D28 169 D31 229 VSS 50 EXCSX 110 D30 170 TXD2 230 CFVS1X 51 EXD0/GPIO0 111 TXD1 171 TXD3 231 VDDI 52 EXD4/GPIO4 112 RXD1 172 RXDV 232 VDDE 53 EXD7/GPIO7 113 RXER 173 COL 233 VSS 54 EXD10 114 RXD3 174 DREQRX 234 CFVCC3EX 55 VSS 115 RXCRS 175 DREQTX 235 VDDI 56 EXD12 116 EXA 176 EXWRX 236 CFA4 57 EXD13 117 EXRDX 177 EXD2/GPIO2 237 VSS 58 CFCD1X 118 EXD1/GPIO1 178 EXD6/GPIO6 238 VDDE 59 SCL 119 EXD5/GPIO5 179 EXD9 239 VDDI 60 CFRDY 120 EXD8 180 EXD15 240 CFD6

Pin name

Pin Number

Pin name

Pin Number

Pin name

MB91401

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PIN DESCRIPTION

■■■■

[SYSTEM] [ETHERNET MAC CONTROLLER]

INT7 to INT5 3 RXCLK 1

MDI2 to MDI0 3 RXER 1

[OSCILLATOR]

[PLL CONTROL]

PLLSET1, PLLSET0 2

[ICE]

ICS2 to ICS0 3 EXWRX 1

ICD3 to ICD0 4 DREQTX 1

[JTAG]

[TEST]

TEST3 to TEST0 4 CFA10 to CFA0 11

[UART]

SOUT1, SOUT0 2 CFCD2X, CFCD1X 2

SCK1, SCK0 2 CFVS1X 1

[MEMORY IF]

WRX3 to WRX0 4 CFOEX 1

CSX0, CSX1, CSX6 3 CFWEX 1

XINI 1 TXCLK 1

INITXI 1 TXD3 to TXD0 4

NMIX 1 TXEN 1

OSCEA 1 RXDV 1

OSCC 1 RXCRS 1

OSCEB 1 COL 1

PLLS 1 MDIO 1

PLLBYPAS 1 EXCSX 1

CLKSEL 1 EXA 1

BREAKI 1 EXRDX 1

ICLK 1 DREQRX 1

TCK 1

TRST 1

TMS 1 UCLK48 1

TDI 1 UCLKSEL 1

TDO 1 UDP 1

VPD 1 CFD15 to CFD0 16

SIN1, SIN0 2 CFREGX 1

A23 to A0 24 CFWAITX 1

D31 to D0 32 CFVCC3EX 1

RDX 1 CFRESET 1

RDY 1 CFIORDX 1

MCLKO 1

Signal line

Power Supply/

MB91401

GND N.C.

BGA-240P-M01

196 pin

39 pin

5 pin

[EXTERNAL IF]

[USB IF]

[CARD IF]

C IF]

RXD3 to RXD0 4

MDCLK 1

EXD15 to EXD0/GPIO7 to GPIO0 16

EXIS16 1 USBINS 1

UDM 1

CFCE2X, CFCE1X 2

CFRDY (CFIREQ) 1

CFIOWRX 1 SDA 1

SCL 1

SYSTEM (9 pin)

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Pin name Pin no.

XINI 8  IN D

INITXI 204

NMIX 206

INT7 INT6 INT5

MDI2 MDI1 MDI0

150

87 16

142

Polarity

Nega-

tive

Nega-

tive

 IN D

Circuit

I/O

IN D

MB91401

Function/application

Clock input pin Input pin of clock generated in clock generator. 10 MHz to 50 MHz frequency can be input.

Reset input pin This pin inputs a signal to initialize the LSI. When turning on the power supply, apply “0” to the pin until the clock signal input to the CLKIN pin becomes stable. All built-in registers and external pins are initialized, and the built-in PLL is stopped when “0” is asserted to INITXI.

NMI input pin Non-Maskable Interrupt signal

External interrupt input pins These pins input an external interrupt request signal. For external interrupt detection, set the ENIR, EIRR and ELVR registers of the FR core.

Mode pins These pins determine the operation mode of the LSI. Always set this bit to “001”.

OSCILLATOR (3 pin)

Pin name Pin no.

OSCEA 12  IN G

OSCC 145

OSCEB 10  OUT G

PLL CONTROL (5 pin)

Pin name Pin no.

PLLS 147  IN D

PLLSET1 144  IN D

PLLSET0 81  IN D

PLLBYPAS 9  IN D

CLKSEL 77  IN D

Polarity

Nega-

tive

Polarity

Circuit

I/O

IN D

Circuit

I/O

Function/application

Crystal oscillation input pin Input pin of crystal oscillation cell.

Crystal oscillation control input pin Oscillation control pin of crystal oscillation cell. “0” : Oscillation “1” : Oscillation stop

Crystal oscillation output pin Output pin of crystal oscillation cell.

Function/application

PLL/through mode (reset) switching input pin “0” : PLL through mode (oscillation stop) “1” : PLL oscillation mode

Input clock division ratio select input pin “0” : Input clock direct “1” : Input clock divided by 2

Division ratio select input to PLL FB pin “0” : Two dividing frequency is input to the terminal FB. “1” : Four dividing frequency is input to the terminal FB.

PLL bypass select input pin “0” : PLL used “1” : PLL unused

Input clock switching input pin “0” : XINI (External clock) “1” : Built-in OSC generating clock

MB91401

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ICE (9 pin)

Pin name Pin no.

BREAKI 76  IN D

Polarity

I/O

Circuit

Function/application

Emulator break request pin This pin inputs the emulator break request when an ICE is connected.

ICS2 ICS1 ICS0

ICLK 3  I/O B

ICD3 ICD2 ICD1 ICD0

JTAG (5 pin)

Pin name Pin no.

TCK 146  IN E

TRST 78  IN E

TMS 7  IN E

TDI 5  IN E

74 75

140 194 139 138

 OUT F

 I/O B

Polarity

I/O

Circuit

Emulator chip status pins These pins output the emulator status when an ICE is connected.

Emulator clock pin This pin serves as the emulator clock pin when an ICE is connected.

Emulator data pins These pins serve as the emulator data bus when an ICE is connected.

Function/application

JTAG test clock pin Note : Please input “1” when unused. JTAG test reset pin Note : Please input “0” when unused. TAP controller mode select pin Note : Please input “1” when unused. JTAG test data input pin

JTAG test serial data input pin. Note : Please input “1” when unused.

TEST (5 pin)

TDO 141  OUT F

Pin name Pin no.

VPD 143  IN  TEST3

TEST2 TEST1 TEST0

84 13 82 11

Polarity

 IN D

I/O

Circuit

JTAG test data output pin JTAG test serial data output pin

Function/application

Mode pin Input “0” to this pin.

Test pin Input “0000” to this pin.

Note : Don’t set other than above description.

UART (6 pin)

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Pin name Pin no.

Polarity

I/O

Circuit

MB91401

Function/application

SIN1 SIN0

SOUT1 SOUT0

SCK1 SCK0

MEMORY IF (66 pin)

Pin name Pin no.

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

85 15

149

148

156

95 26

155

154

93 24

153

92 23

152

91 22

151

90 21 88 89 20 17

18 212 210

 IN D

 OUT F

 I/O B

Polarity

 OUT B

I/O

Circuit

Serial data input pins Serial data input pin of UART built-in FR core.

Serial data output pins Serial data output pin of UART built-in FR core.

Serial clock I/O pins Serial clock input/output pin of UART built-in FR core.

Function/application

Address output pins 24 bits address signal pin.

(Continued)

MB91401

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(Continued)

Pin name Pin no.

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

169 110 168 109

42 218 167 108

41 166 107

40 106

38 105

36 165 104

35 164 103

34 216 163 102

33 162 101

32 100

Polarity

 I/O B

I/O

Circuit

Function/application

Data input/output pins 32 bits data input/output signal pin.

CSX6 CSX1 CSX0

RDX 27

WRX3 WRX2 WRX1 WRX0

MCLKO 25  OUT F

RDY 157

159

97 158

Nega-

tive

Nega-

tive

Nega-

tive

Posi-

tive

OUT B

IN D

Chip select output pins 3-bit chip select signal pin. Output the “L” level when accessing to external memory.

Read strobe output pin Read strobing signal pin. Output the “L” level when read accessing.

Write strobing output pins Write strobing signal pin. Output the “L” level when write accessing.

Memory clock output pin Clock for peripheral resources pin.

External RDY input pin

When the external bus is not completed, the bus cycle can be extended by inputting “0”.

ETHERNET MAC CONTROLLER (17 pin)

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Pin name Pin no.

RXCLK 48  IN D

Polarity

I/O

Circuit

MB91401

Function/application

Clock input for reception pin MII sync signal during reception. The frequency is 2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps.

RXER 113

RXDV 172

RXCRS 115

RXD3 RXD2 RXD1 RXD0

COL 173

TXCLK 46  IN D

TXEN 43

TXD3 TXD2 TXD1 TXD0

114

112

171 170 111

Posi-

tive

Posi-

tive

Posi-

tive

 IN D

Posi-

tive

Posi-

tive

 OUT F

IN D

OUT F

Receive error input pin It is recognized that there is an error in the reception packet when “1” is input from the PHY device at receiving.

Receive data valid input pin It is recognized that receive data is effective.

Career sense input pin The state that the reception or the transmission is done is recognized.

Receive data input pins 4-bit data input from PHY device.

Collision detection input pin When TXEN signal is active and “1”, the collision is recognized. The collision is not recognized without these conditions.

Clock input for transfer pin It becomes synchronous of MII when transmitting. The frequency is 2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps.

Transfer enable output pin It is shown that effective data is on the TXD bus. It is output synchronizing with TXCLK.

Transfer data output pins 4-bit data bus sent to the PHY device. It is output synchronizing with TXCLK.

MDCLK 222  OUT F

MDIO 224  I/O B

SMI clock output pin SMI IF clock pin Connect to SMI clock input pin of PHY device.

SMI data input/output pin Connect to SMI data of PHY device.

MB91401

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EXTERNAL IF (23 pin)

Pin name Pin no.

Polarity

I/O

Circuit

Function/application

EXCSX 50

EXA 116  IN D

EXD15 EXD14 EXD13 EXD12 EXD11 EXD10 EXD9 EXD8

EXD7/GPIO7 EXD6/GPIO6 EXD5/GPIO5 EXD4/GPIO4 EXD3/GPIO3 EXD2/GPIO2 EXD1/GPIO1 EXD0/GPIO0

EXRDX 117

180 122

56 121

54 179 120

53 178 119

52 228 177 118

Nega-

tive

 I/O B

Nega-

tive

IN D

External chip select input pin Chip select input pin from external host.

External address input pin Address input pin from external host. “0” : Register select “1” : FIFO data select

External data input/output pins The I/O terminal of data bus bit of bit15 to bit8 with an external host.

External data/GPIO input/output pins The I/O terminal of data bus bit of bit7 to bit0 with an external host. Note : When EXIS16 “0” input, it becomes the I/O terminal of GPIO7 to GPIO0.

External read strobing input pin Read strove input pin from external host

EXWRX 176

EXIS16 49  IN D

DREQRX 174

DREQTX 175

Nega-

tive

Nega-

tive

Nega-

tive

IN D

OUT F

External write strobing input pin Write strove input pin from external host

External data bus width select input pin Bit width select pin of EXD “0” : 8 bit (Note : EXD15 to EXD8 are enabled.) “1” : 16 bit

External reception data request output pin Recordable data to reception FIFO is shown.

External transfer data request output pin It is shown that there are data in transmission register and transmission FIFO.

USB IF (5 pin)

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Pin name Pin no.

UDP 61  I/O C

UDM 183  I/O C

USBINS 182  IN D

UCLK48 6  IN D

Polarity

I/O

Circuit

MB91401

Function/application

USB data D + (differential) pin I/O signal pin on the plus side of the USB data. Use the LSI with 25 Ω to 30 Ω (27 Ω recommended) external series load resistors, 1.5 kΩ pull-up resistors and about 100 kΩ resistors. Input “0” when the USB macro is unused.

USB data D − (differential) pin I/O signal pin on the minus side of the USB data. Use the LSI with 25 Ω to 30 Ω (27 Ω recommended) external series load resistors, 1.5 kΩ pull-up resistors and about 100 kΩ resistors. Input “0” when the USB macro is unused.

USB insert input pin USB socket input detection pin. Be sure to input “0” when not using USB macro.

48 MHz input (external clock input) pin This pin inputs an external 48-MHz clock signal. The USB macro operates based on this clock. Input the clock with high accuracy (as not only LSI but also a device) more than 2500 ppm. Input “0” when the USB macro is unused.

UCLKSEL 124  IN D

USB clock select pin Clock select pin using for USB macro “0” : Using internal clock “1” : Using UCLK48

MB91401

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CARD IF (41 pin)

Pin name Pin no.

CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD0 CFD0

CFA10 CFA9 CFA8 CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

CFCE2X 128

CFCE1X 63

CFREGX 185

CFCD2X 123

2 73 72

137 136

192 135

240 191 134

190 133

189 132

188 131

236 187 130

186

Polarity

 I/O B

 OUT B

Nega-

tive

Nega-

tive

Nega-

tive

Nega-

tive

I/O

OUT B

IN E

Circuit

Function/application

CF data input/output pins I/O data/status/command signal pin to CompactFlash card side

CF address 10 to 0 output pins Address output CFA10 to CFA0 pins to CompactFlash card side

CF card enable output pin Byte access output pin to CompactFlash card side Note : Supported for access to CFD7 to CFD0. When “L” level is output, odd number byte access of the word is shown.

CF card enable output pin Byte access output pin to CompactFlash card side Note : Supported for access to CFD7 to CFD0. When “L” level is output at word access, even number byte access of the word is shown. When the byte is accessed, the even number byte and odd number byte access become possible because CFA0 and CFCE2X are combined and used by it.

CF Attribute/Common switching output pin Attribute/Common switching output pin to CompactFlash card side “H” : Common Memory select “L” : Attribute Memory select

Card connection detect input pin : CFCD2X Checking connection pin of the socket and CompactFlash card. It is shown that the CompactFlash card was connected when this signal and CFCD1X are both input by “0”.

(Continued)

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Pin name Pin no.

CFCD1X 58

CFVS1X 230

CFRDY (CFIREQ)

Polarity

Nega-

tive

Nega-

tive

Posi-

tive

(Nega-

tive)

Circuit

I/O

IN E

MB91401

Function/application

Card connection detect input pin : CFCD1X Checking connection pin of the socket and CompactFlash card. It is shown that the CompactFlash card was connected when this signal and CFCD2X are both input by “0”.

CF side GND input pin GND level detection pin from CompactFlash side. The “0” input to the pin assumes that the CompactFlash card can operate at 3.3 V, setting the CFVCC3EX pin to the “L” level.

CF ready input pin : memory card Ready input pin from CompactFlash memory card side “1” : Ready “0” : Busy (CF interrupt : I/O card) Interrupt request pin of CompactFlash I/O card. It is shown the interrupt request was done from the I/O card when input to this signal by “0”.

CFWAITX 125

CFVCC3EX 234

CFRESET 184

CFOEX 127

CFWEX 62

CFIORDX 64

Nega-

tive

Nega-

tive

Posi-

tive

Nega-

tive

Nega-

tive

Nega-

tive

IN E

OUT B

OUT A

OUT B

Cycle wait input pin during CF execution Cycle wait input pin from CompactFlash card side “0” : It is shown that there is a wait demand at the cycle

under ex ecution.

“1” : It is shown that there is no wait demand at the cycle

under execution.

CF3.3 V power enable output pin Outputs “L” level when the CompactFlash card is operable at 3.3 V. The output signal enables 3.3-volt power supply to the CompactFlash card. The pin outputs “L” level only when the CFVS1X pin detects “0”; otherwise, the pin outputs “H”.

CF reset output pin Reset output pin to CompactFlash card side. CompactFlash is reset at “H” output.

CF read strobe output pin Read strove output pin to CompactFlash card (memory mode and Attribute memory area)

CF register write output pin Write clock output pin to CompactFlash card (register write and Card Configuration Register area). The register write is executed at the rising edge from “L” to “H”.

CFIO read strobing output pin Read strove output pin to CompactFlash card (I/O mode)

CFIOWRX 129

Nega-

tive

OUT B

CFIO write strobing output pin Write strove output pin to CompactFlash card (I/O mode)

MB91401

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C IF (2 pin)

Pin name Pin no.

Polarity

SDA 181  I/O B

I/O

Circuit

Function/application

Serial data line input/output pin

C bus data I/O pin

SCL 59  I/O B

Serial clock line input/output pin

C bus clock I/O pin

Power Supply/GND (39 pin)

Pin name Pin no.

Polarity

PLLVDD 199 

I/O

Power supply

Circuit

V-E

Function/application

APLL dedicated power supply pin This pin is for 1.8 V power supply pin.

PLLVSS 197  GND V-S APLL dedicated GND Pin

83 196 202

VDDE

208 214 220



Power supply

V-E 3.3 V power supply pin

226 232 238

195 200 203 207 211

VDDI

215 219



Power supply

V-E 1.8 V power supply pin

223 227 231 235 239

1 19 37 55

193 198 201

VSS

205 209

 GND V-S GND Pin

213 217 221 225 229 233 237

I/O CIRCUIT TYPE

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■■■■

Type Circuit Remarks

MB91401

Digital output

• With pull/down

• CMOS level output

Digital output

• CMOS level input

• Value of pull-down resistance =

approx. 33 kΩ (Typ)

Digital input

Digital output]

Digital output

• CMOS level output

• CMOS level input

Digital input

input

−

D+

input

Differential input

D−

Full D

output

C USB I/O

−

Full D

output

Low D Low D

output

−

output Direction Speed

(Continued)

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(Continued)

Type Circuit Remarks

D CMOS level input

F CMOS level output

Digital input

Digital output

• With pull-up

• CMOS level input

• Value of pull-up resistance =

approx. 33 kΩ (Typ)

Oscillation output Control

G Oscillation circuit

MB91401

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HANDLING DEVICES

■■■■

Preventing Latch-up

When a voltage that is higher than V and the output terminal in CMOS IC or the voltage that exceeds ratings between V latch-up phenomenon might be caused. If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating during device operation.

Separation of power supply pattern

Analog PLL (APLL at the following) is installed in this LSI. The po wer supply f or VCO and for digital is separ ated in LSI so that the oscillation characteristic of APLL may receive the influence of power supply variation.

Therefore, the power supply is recommended to be separated also on the mounting base.

•••• Separation of power supply pattern (recommended)

Take measures to reduce impedance, for example, by using as wide a power pattern as possible. The recommendation example is shown as follows.

• For two power supplies (for digital and for VCO) It is advisable to provide a digital power-supply (a) and VCO power-supply (b) and connect them to the LSI’s equivalents, respectively.

DDE and a voltage that is lower than VSS are impressed to the input terminal

DDE to VSS is impressed, the

Figure For 2-power supply (for digital and for VCO)

Power

supply

(a)

VDD (for digital)

PLLVDD (for VCO)

Power supply

(b)

PLLVSS

VSS

APLL

Logic part

LSI

• For the common power supply

To share a single power-supply for digital and VCO uses, it is advisable to separate the output into the digital and VCO wiring patternsand connect them to the LSI.

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Figure When you share the power suppl y for digital and for VCO

VDD (for digital)

PLLVDD (for VCO)

Power

supply

(a)

Treatment of the unused pins

Leaving unused input pins open results in a malfunction, so process the pull-up or pull-down.

Treatment of OPEN pins

Be sure to use open pins in open state.

Treatment of output pins

A large current may flow to an output pin left connected to the power-supply, another output pin, or to a high capacitance load. Leaving the output pin that way for an extended period of time degrades the device. Use meticulous care in using the device not to exceed the absolute maximum rating.

PLLVSS

VSS

APLL

Logic part

LSI

About Mode (MDI2 to MDI0, VPD) pin and Test (TEST3 to TEST0) pin

Connect these pins directly to VDDE or VSS. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between individual mode pins and VDDE or VSS on the PC board as possible and connect them with as low an impedance as possible.

About power supply pins

In products with multiple VDDE, VDDI or VSS pins, the pins of the same potential are internally connected in the device to av oid abnormal operations including latch-up. Howe ver you must connect the pins to e xternal power supply and a ground line to lower the electro-magnetic emission level to prevent abnormal operation strobe signals caused by the rise in the ground level, and to conform to the total output current rating.

The power pins should be connected to VDDE, VDDI and VSS of this device at the lowest possible impedance from the current supply source.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VDDE and VSS, and between VDDI and VSS near this device.

Crystal Oscillator Circuit

Noise near the OSCEA terminal may cause the MB91401 to malfunction. Design the circuit board so that OSCEA terminal, OSCEB terminal and the cr ystal oscillator, and the bypass

capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the OSCEA ter minal and OSCEB terminal

surrounded by ground plane because stable operation can be expected with such a layout.

MB91401

Prelminary

2004.11.12

CONNECTED SPECIFICATION OF MB91401 AND ICE

■■■■

Recommended type and circuit configuration of the emulator interface connector mounting on the user system, attention when designing and wiring regulation are shown. When the flat cable is used, the combination of the connectors with housing should be selected.

Recommended connector type

Attached cable Part number Remarks

FPC cable FH10A-30S-1SH (Maker : Hirose Electric Co., Ltd.) With latch

• Circuit composition Please put the dumping resistance 15 Ω in the series in the ICLK terminal signal because of the stability of

operation when connecting it with ICE. Resistance must be mounted near the terminal ICLK of this LSI when you design the printed wiring board.

Emulator interface connector MB2198-0 and MB2197-01 side

UVCC

ICLK

ICS2 to ICS0 ICD3 to ICD0

BREAKI

RST

xRSTIN

(Open)

∗1

FUSE

∗2

Reset output

15 Ω

10 kΩ

MCU for evaluation MB91401

∗3

ICLK ICS2 to ICS0 ICD3 to ICD0

BREAKI INITXI

circuit

GND

VSS

*1 : Use the line (inter connect) to flow the rating current or more. *2 : The change circuit might become necessary, and refer to “Precaution when designing”. *3 : Mount resistance near the terminal ICLK of MB91401.

MB91401

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• Precaution when designing When evaluation MCU on the user system is operated in the state that the emulator is not connected, should

be treated as follow each input terminal of evaluation MCU connected with the emulator interface on the user system.

Therefore, note that the switch circuit etc, might become necessary in the user system when you design. The terminal processing in each emulator interface is shown as follows.

Pin treatment of emulator interface (DSU-3)

Evaluation MCU terminal name Pin treatment

RST Others To open.

Emulator interface wiring regulations

Signal line name Wiring regulations

ICLK ICS2 to ICS0 ICD3 to ICD0 BREAKI

GND • Connect directly with a power supply system pattern such as grandopran.

• Reference document Please match and refer to the following manual for the connection with ICE.

• DSU-FR Emulator MB2198-01 Hardware Manual

• FR20/30 series MB2197-01 Hardware Manual

To be connected the RST terminal with the reset output circuit in the user system.

• The total wiring length of each signal (From evaluation MCU pin to the emulator interface connector pin) is made within 50 mm.

• The difference of the total wiring length of each signal makes within 2 cm and the total wiring length of ICLK is the shortest.

• Wire the pattern with capacity more than the ratings current.

• Each power supply and GND may cause a short-circuit or reverse connec-

tion in between by a wrong connection of a probe. Insert a protection circuit such as a fuse into each power supply pattern to safeguard it.

+ 50 hidden pages

Fujitsu MB91401 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

DESCRIPTION

FEATURES

PACKAGE

PIN ASSIGNMENT

PIN NUMBER TABLE

PIN DESCRIPTION

I/O CIRCUIT TYPE

HANDLING DEVICES

CONNECTED SPECIFICATION OF MB91401 AND ICE