Fujitsu MB86R12 Design Manualline

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB86R12 Application Note

DDR3 Interface

PCB Design Guideline

November, 2011

The 1.0 edition

i

MB86R12 Application Note

DDR3 Interface PCB Design Guideline

FUJITSU SEMICONDUCTOR CONFIDENTIAL

Preface

This guideline describes PCB design restrictions related to MB86R12 DDR3 interface signal wiring.

· The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

· The information, such as descriptions of function and application circuit examples, in this document are
presented solely for the purpose of reference to show examples of operations and uses of FUJITSU
SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR

does not warrant proper operation of the device

with respect to use based on such information. When you develop equipment incorporating the device based

on such information, you must assume any responsibility arising out of such use of the information. FUJITSU

SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the
information.

· Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright,
or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU
SEMICONDUCTOR warrant no n -infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liabilit y for any infringement of the
intellectual property rights or other rights of third parties which would res ult from the use of information
contained herein.

· The products described in this document are designed, developed and manufactured as contemplated for
general use, including without limitation, ordinary industrial use, general office use, personal use, and

household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying

fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public,
and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction
control in nuclear facility, aircraft flig ht control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon sys t em), or (2) for use requiring extremely high r eliability
(i.e., submersible repeater and ar tificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/o r any third party for any
claims or damages arising in connectio n with above-mentioned uses of the products.

· Any semiconductor de vi ces have an inherent chance of failur e. You must protect against injury, damage or
loss from such failures by incorporating safety design measures into your facility and equipment such as
redundancy, fire protection, and p revention of over-current levels and other abnormal operating conditions.

· Exportation/release of any products described in this document may require necessary procedures in
accordance with the

regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US

export control laws.

· The company names and brand names herein are the trademarks or registered trademarks of their respective

owners.

All rights reserved, Copyright FUJITSU SEMICONDUCTOR LIMITED 2011

ii

MB86R12 Application Note

DDR3 Interface PCB Design Guideline

FUJITSU SEMICONDUCTOR CONFIDENTIAL

Revision History

Date

Ver.

Contents

2011/11/29

1.0

Newly issued

iii

MB86R12 Application Note

DDR3 Interface PCB Design Guideline

FUJITSU SEMICONDUCTOR CONFIDENTIAL

Contents

1. Floor plan ............................................................................................................ 1

2. PCB laminating ................................................................................................... 2

3. DDR3_SDRAM specifications ............................................................................ 3

4. Signal design restrictions (DDR3 interface part) ............................................. 4

4.1. Definition of signal li ne group ................................................................................................................ 4

4.2. General wiring restrictions ...................................................................................................................... 5

4.3. Resistance ................................................................................................................................................ 5

4.4. Terminal resistance/Damping resistance/Wire length ............................................................................. 6

4.5. Wiring gap/Crosstalk ............................................................................................................................... 7

4.6. ZQ/ODT setting ...................................................................................................................................... 8

4.7. Wiring topology ...................................................................................................................................... 9

4.7.1. Wiring topology diagram of MCK_Group ...................................................................................... 9

4.7.2. Wiring topology diagram of MDQSx_Group................................................................................ 10

4.7.3. Wiring topology diagram of MDQx_Group ................................................................................... 11

4.7.4. Wiring topology diagram of MCNTL_Group/MCMD_Group ..................................................... 12

5. Power system design restrictions .................................................................. 13

5.1. Number and capacity of bypass capacitor ............................................................................................. 13

5.2. Pull-out wiring condition ...................................................................................................................... 14

1

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB86R12 Application Note

DDR3 Interface PCB Design Guideline

1. Floor plan

Figure 1-1 shows the reference example of t he floor plan of MB86R12 and connected DDR3 SDRAM
devices.

Figure 1-1 Reference example of the floor plan of MB86R12 and DDR3 SDRAM devices

27mm

9mm

27mm

32mm

6mm

9mm

MB86R12

10mm

15.5mm

SDRAM

SDRAM