FUJITSU MB15F72UL DATA SHEET

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

Dual Serial Input PLL Frequency Synthesizer

MB15F72UL

DESCRIPTION

■■■■

The Fujitsu MB15F72UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and a 350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

The BiCMOS process is used, as a result a supply current is typically 2.5 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data. The data fo rmat is the same as the previous one MB15F02SL, MB12F72SP. Fast loc king is achieved for adopting the new circuit.

The new package (BCC20) decreases a mount area of MB15F72UL more than 30% comparing with the former BCC16 (for dual PLL) .

DS04-21367-1E

MB15F72UL is ideally suited for wireless mobile communications, such as CDMA.

FEATURES

■■■■

• High frequency operation : RF synthesizer : 1300 MHz Max. : IF synthesizer : 350 MHz Max.

• Low power supply voltage : V

• Ultra low power supply current : ICC = 2.5 mA Typ.

PACKAGES

■■■■

20-pin plastic TSSOP 20-pad plastic BCC

(FPT-20P-M06) (LCC-20P-M05)

CC = 2.4 to 3.6 V

(VCC = Vp = 2.7 V, SWIF = SWRF = 0, Ta = +25 °C, in IF, RF locking state)

(Continued)

MB15F72UL

(Continued)

• Direct power saving function : Power supply current in power saving mode Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25 °C) Max. 10 µA (V

• Software selectable charge pump current : 1.5 mA/6.0 mA Typ.

• Dual modulus prescaler : 1300 MHz prescaler (64/65 or 128/129 ) /350 MHz prescaler (8/9 or 16/17)

• 23 bit shift resister

• Serial input 14-bit programmable reference divider : R = 3 to 16,383

• Serial input programmable divider consisting of :

- Binary 7-bit swallow counter : 0 to 127

- Binary 11-bit programmable counter : 3 to 2,047

•On−chip phase control for phase comparator

•On−chip phase comparator for fast lock and low noise

• Built-in digital locking detector circuit to detect PLL locking and unlocking.

• Operating temperature : Ta = −40 °C to +85 °C

• Serial data format compatible with MB15F02SL

• Small package BCC20 (3.4 mm × 3.6 mm × 0.6 mm)

PIN ASSIGNMENTS

■■■■

CC = Vp = 2.7 V)

(TSSOP-20)

TOP VIEW

fin

PSIF

VpIF

DoIF

1 2 3

IF

4 5 6 7 8 9

10

OSCIN

GND

XfinIF

GNDIF

VCCIF

LD/fout

(FPT-20P-M06)

20 19 18 17 16 15 14 13 12 11

Clock Data LE fin

RF

XfinRF GNDRF VCCRF PSRF VpRF Do

RF

finIF

XfinIF

GND

VCCIF

PSIF

VpIF

(BCC-20)

TOP VIEW

OSCIN

GND

1

19 18

20 2 3

IF

4 5 6

7

DoIF

LD/fout

(LCC-20P-M05)

8

Clock

9

Do

RF

Data

17

10

VpRF

16 15 14 13 12 11

LE fin

RF

XfinRF GNDRF VCCRF

PSRF

2

PIN DESCRIPTION

■■■■

MB15F72UL

Pin no.

TSSOP BCC

119OSC

Pin name I/O Descriptions

The programmable reference divider input. TCXO should be connected with an

I

IN

AC coupling capacitor.

220GND Ground for OSC input buffer and the shift register circuit. 31fin

42Xfin 53GND 64V

IF

CCIF

Prescaler input pin for the IF-PLL.

I

Connection to an external VCO should be via AC coupling. Prescaler complimentary input pin for the IF-PLL section.

I

This pin should be grounded via a capacitor.

 Ground for the IF-PLL section.

Power supply voltage input pin for the IF-PLL section (except for the charge



pump circuit) , the OSC input buffer and the shift register circuit. Power saving mode control for the IF-PLL section. This pin must be set at “L”

75PS

86Vp 97D

I

IF

 Power supply voltage input pin for the IF-PLL charge pump.

IF

OIF

when the power supply is started up. (Open is prohibited.) PS

= “H” ; Normal mode / PSIF = “L” ; Power saving mode

IF

O Charge pump output pin for the IF-PLL section.

Lock detect signal output (LD) /phase comparator monitoring

10 8 LD/fout O

output (fout) pins.The output signal is selected by LDS bit in the serial data.

LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal 11 9 D 12 10 Vp

ORF

O Charge pump output pin for the RF-PLL section.

 Power supply voltage input pin for the RF-PLL charge pump.

RF

Power saving mode control pin for the RF-PLL section. This pin must be set at 13 11 PS

14 12 V

CCRF

15 13 GND 16 14 Xfin

17 15 fin

RF

I

“L” when the power supply is started up. (Open is prohibited.)

PS

= “H” ; Normal mode / PSRF = “L” ; Power saving mode

RF

Power supply voltage input pin for the RF-PLL section (except for the charge



pump circuit)

 Ground for the RF-PLL section

RF

Prescaler complimentary input pin for the RF-PLL section.

I

This pin should be grounded via a capacitor.

Prescaler input pin for the RF-PLL.

I

Connection to an external VCO should be via AC coupling.

Load enable signal input pin (with the schmitt trigger circuit) 18 16 LE I

When LE is set “H”, data in the shift register is transferred to the

corresponding latch according to the control bit in the serial data.

Serial data input pin (with the schmitt trigger circuit) 19 17 Data I

Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,

RF-ref. counter, RF-prog. counter) according to the control bit in

the serial data. 20 18 Clock I

Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)

One bit of data is shifted into the shift register on a rising edge of the clock.

3

MB15F72UL

■■■■ BLOCK DIA GRAM

PSIF

finIF

XfinIF

OSCIN

finRF

XfinRF

7

(5)

3

(1)

4

(2)

1

(19)

(15)

17 16

( )

14

Intermittent

mode control

(IF-PLL)

Prescaler

(IF-PLL)

(8/9, 16/17

OR

Prescaler

(RF-PLL)

(64/65, 128/129)

3 bit latch

LDS

SWIF

7 bit latch 11 bit latch

Binary 7-bit

swallow counter

FCIF

(IF-PLL)

Binary 11-bit

programmable

counter (IF-PLL)

2 bit latch 14 bit latch 1 bit latch

T1 T2

Binary 14-bit pro-

grammable ref. counter(IF-PLL)

C/P setting

counter

frIF

frRF

T1 T2

Binary 14-bit pro-

grammable ref.

counter (RF-PLL))

C/P setting

counter

2 bit latch 14 bit latch 1 bit latch

VCCIF GNDIF

(4)

6 5

fpIF

Phase comp.

(IF-PLL)

(3)

Lock Det.

(IF-PLL)

LDIF

AND

LD

RF

Lock Det.

(RF-PLL)

VpIF

8

Charge

pump

(IF-PLL)

(6)

Current

Tuning

Selector

LD frIF frRF fpIF fpRF

Switch

Fast lock

(7)

10 (8)

9

DoIF

LD/ fout

PSRF

LE

Data

Clock

13

(11)

18

(16)

(17)

19 20

(18)

Intermittent

mode control

(RF-PLL)

Schmitt

circuit

Schmitt

circuit

Schmitt

circuit

Latch selector

C

N

23-bit shift register

1

2

LDS

SWRF

3 bit latch

Binary 7-bit

swallow counter

FCRF

(RF-PLL)

7 bit latch 11 bit latch

Binary 11-bit

programmable

counter (RF-PLL)

(20)2 14

GND

Phase comp.

(RF-PLL)

fpRF

(12) (13) (10)

V

CCRF

15 12

GNDRF

Tuning

Fast lock

Charge

pump

(RF-PLL)

VpRF

Current

Switch

11 (9)

DoRF

O : TSSOP ( ) : BCC

4

■■■■ ABSOLUTE MAXIMUM RATINGS

MB15F72UL

Parameter Symbol

Unit

Min. Max.

Rating

CC −0.5 4.0 V

V

Power supply voltage

Vp V

Input voltage V

I −0.5 VCC + 0.5 V

CC 4.0 V

LD/fout VO GND VCC V

Output voltage

Do

IF, DoRF VDO GND Vp V

Storage temperature Tstg −55 +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■■■■ RECOMMENDED OPERATING CONDITIONS

Parameter Symbol

Min. Typ. Max.

V

CC 2.4 2.7 3.6 V VCCRF = VCCIF

Power supply voltage

Vp VCC 2.7 3.6 V

Input voltage V

I GND  VCC V

Operating temperature Ta −40 +85 °C

Value

Unit Remarks

Note : • VCCRF, VpRF, VCCIF and VpIF must supply equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V

CCRF, VpRF, VCCIF and VpIF to keep

them equal.

It is recommended that the non-use PLL is controlled by power saving function.

• Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection, observe the f ollowing precautions when handling the device .

• When storing and transporting the device, put it in a conductive case.

• Before handling the de vice, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. Use a conductive sheet on working bench.

• Before fitting the device into or removing it from the socket, turn the power supply off.

• When handling (such as transporting) the device mounted board, protect the leads with a conductive sheet.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

5

MB15F72UL

ELECTRICAL CHARACTERISTICS

■■■■

Parameter

Power supply current

Power saving current

Operating frequency

fin

IF

fin

RF

OSC

Sym-

bol

I

CCIF

I

CCRF

I

PSIF

I

PSRF

*3

finIFIF PLL 50  350 MHz

*3

finRFRF PLL 100  1300 MHz

f

IN

OSC

(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)

Condition

Min. Typ. Max.

finIF = 270 MHz

*1

V

= VpIF = 2.7 V

CCIF

finRF = 910 MHz

*1

V

= VpRF = 2.7 V

CCRF

0.6 1.0 1.7 mA

1.0 1.5 2.5 mA

PSIF = PSRF = “L”  0.1 PSIF = PSRF = “L”  0.1

 3  40 MHz

Value

*2

Unit

10 µA 10 µA

Input sensitivity

“H” level input voltage

fin

IF

fin

RF

OSC Data,

PfinIFIF PLL, 50 Ω system −15 +2dBm

PfinRFRF PLL, 50 Ω system −15 +2dBm

V

IN

LE,

“L” level input voltage V “H” level input voltage

“L” level input voltage V

“H” level input current

Clock PS

IF

PS

RF

Data, LE,

,

I

Clock, PS

,

“L” level input current I

PS

IF RF

“H” level input current

OSC

IN

“L” level input current I “H” level output voltage

V

LD/fout

“L” level output voltage V “H” level output voltage

Do Do

IF RF

V

,

“L” level output voltage V

OSC

V

Schmitt trigger input 0.7 VCC + 0.4 V

IH

Schmitt trigger input 0.3 VCC − 0.4 V

IL

V

IH

IL

*4

IH

*4

IL

I

IH

*4

IL

VCC = Vp = 2.7 V,

OH

I

= −1 mA

OH

OLVCC

DOH

DOL

= Vp = 2.7 V, IOL = 1 mA 0.4 V

VCC = Vp = 2.7 V, I

= −0.5 mA

DOH

VCC = Vp = 2.7 V, I

= 0.5 mA

DOL

 0.5  V

 0.7 V

CC

V

0.3 V

−1.0 +1.0 µA

 0 +100 µA −100  0 µA

− 0.4 V

V

CC

Vp − 0.4 V

0.4 V

CC

VP −

V

P

High impedance cutoff current

Do Do

,

IF RF

“H” level output current

LD/fout

“L” level output current I

6

VCC = Vp = 2.7 V

I

OFF

V

= 0.5 V to Vp − 0.5 V

OFF

*4

I

VCC = Vp = 2.7 V −1.0 mA

OH

VCC = Vp = 2.7 V 1.0 mA

OL

2.5 nA

(Continued)

Parameter Symbol Condition

MB15F72UL

(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)

Value

Unit

Min. Typ. Max.

“H” level output current

“L” level output current

Charge pump current rate

*8

Do

IF

I

Do

RF

Do

IF

Do

RF

I

DOL/IDOHIDOMT

vs. V vs.Ta I

DOH

*8

I

DOL

DOIDOVD

DOTA

VCC = Vp = 2.7 V,

*4

V

= Vp / 2,

DOH

Ta = +25 °C VCC = Vp = 2.7 V,

V

= Vp / 2,

DOL

Ta = +25 °C

*5

VDO = Vp / 2  3 %

*6

0.5 V ≤ VDO ≤ Vp − 0.5 V  10 %

−40 °C ≤ Ta ≤ +85 °C,

*7

V

= Vp / 2

DO

CS bit = “H” −8.2 −6.0 −4.1 mA CS bit = “L” −2.2 −1.5 −0.8 mA CS bit = “H” 4.1 6.0 8.2 mA CS bit = “L” 0.8 1.5 2.2 mA

 5 %

*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “L” in locking state. *2 : V

PS

= VpIF = V

CCIF

= PSRF = GND, VIH = VCC VIL = GND (at CLK, Data, LE)

IF

= VpRF = 2.7 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode

CCRF

*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min. operating frequency. *4 : The symbol “–” (minus) means the direction of current flow. *5 : V *6 : V *7 : V

= Vp = 2.7 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%)

CC

= Vp = 2.7 V, Ta = +25°C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to both l

CC

= Vp = 2.7 V, [||I

CC

DO (+85°C)

| − |I

DO (–40°C)

|| / 2] / [|I

DO (+85°C)

| + |I

DO (–40°C)

| / 2] × 100 (%) (Applied to both I

DOL

*8 : When Charge pump current is measured, set LDS = “L” , T1 = “L” and T2 = “H”.

and l

DOL

)

DOH

and I

DOH

)

I1

IDOL

IDOH

0.5

I3

I4

Vp/2

Charge pump output voltage (V)

I2

I1

VpVp − 0.5

7

MB15F72UL

FUNCTIONAL DESCRIPTION

■■■■

1. Pulse swallow function :

f

= [ (P × N) + A] × f

VCO

f

: Output frequency of external voltage controlled oscillator (VCO)

VCO

P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N) f

: Reference oscillation frequency (OSCIN input frequency)

OSC

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

2. Serial Data Input

The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/ RF-PLL sections, and programmable reference dividers of IF/RF-PLL sections are controlled individually. The serial data of binary data is entered through Data pin. On a rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transf erred to one of latches depending upon the control bit data setting.

OSC

÷ R

The programmable

reference counter

for the IF-PLL

The programmable

reference counter

for the RF-PLL

The programmable

counter and the swallow

counter for the IF-PLL

The programmable

counter and the swallow

counter for the RF-PLL

CN1 0 1 0 1 CN2 0 0 1 1

Shift Register Configuration

(1)

•

Programmable Reference Counter

(LSB)

(MSB)Data Flow

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X X X

CS : Charge pump current select bit R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383) T1, T2 : LD/fout output setting bit. CN1, CN2 : Control bit X : Dummy bits (Set “0” or “1”)

Note : Data input with MSB first.

8

MB15F72UL

•

Programmable Counter

(LSB)

1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23

IF/

CN1 CN2 LDS

SW

RF

IF/

FC

A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11

RF

A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047) LDS : LD/fout signal select bit SW FC

IF/RF

: Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF) : Phase control bit for the phase detector (IF : FCIF, RF : FCRF)

CN1, CN2 : Control bit

Note : Data input with MSB first.

Data Flow

(MSB)

(2) Data setting

• Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14)

Divide ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1

300000000000011 4

•

16383

0

1

0

•

1

0

•

1

0

•

1

0

•

1

0

•

1

0

•

1

0

1

0

•

1

Note : Divide ratio less than 3 is prohibited.

• Binary 11-bit Programmable Counter Data Setting (N1 to N11)

Divide ratio N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1

300000000011 4

•

2047

0

•

1

0

•

1

0

•

1

0

•

1

0

•

1

0

•

1

0

•

1

•

1

0

•

1

Note : Divide ratio less than 3 is prohibited.

• Binary 7-bit Swallow Counter Data Setting (A1 to A7)

Divide ratioA7A6A5A4A3A2A1

0 0 000000

0

•

1

•

127

0

1

•

1

•

1

9