FUJITSU AMILO Pi 1536 Schematic
5
4
3
2
1
D D
P53IA0
Revision History
09/2005
10/2005
RA
RB
Intel Yonah CPU + 945PM / ICH7-M Chipset
PG01 INDEX
PG02 SYSTEM BLOCK DIAGRAM
C C
PG03 POWER DIAGRAM & SEQUENCE
PG04 GPIO & POWER CONSUMPTION
PG05 CPU Yonah-1/2
PG06 CPU Yonah-2/2
PG07 CLOCK GEN ICS9LPR310
PG08 NB 945PM-HOST -1/5
PG09 NB 945PM VGA_PCIEXPR-2/5
PG10 NB 945PM DDR_MEM SYSTEM-3/5
PG11 NB 945PM POWER-4/5
PG12 NB 945PM VSS_NCTF-5/5
PG13 DDR2 CHANNELA,B
PG14 Terminatation / SMP / DC IN
B B
PG15 PWR S/W& LCD/INVERTOR/CRT/TV
PG16 SB ICH7-MDH -1/3
PG17 SB ICH7-MDH -2/3
PG18 SB ICH7-MDH -3/3
PG19 HDD / CD-ROM
PG20 WIRELESS / NEW CARD / EMI
PG21 I/O PORT CON
PG22 AUD PWR / FAN CTL
PG23 GIGA LAN RTL8110SBL
PG24 IEEE1394A TSB43AB22A
PG25 EC IT8510E / BIOS / TP CON
PG26 VGA MXM CON
PG27 CPU_CORE ( ISL6262 )
PG28 1.05V/1.5V/1.8V/2.5V/0.9V
PG29 +3.3V/+5V/+12V
PG30 VCC SW/+1.05VS/+1.5VS
PG31 BATT IN / Charger
PG32 RAID IC VT6421
PG33 Appendix A. Ver. History
A A
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
5
4
3
2
Date: Sheet
P53IA0
INDEX
C
133Friday, September 22, 2006
1
of
5
4
3
2
1
SATA
P53IA0
D D
C C
Amplifier
LM4991
WOOFER
SPK
B B
BLOCK DIAGRAM
CRYSTAL
14.318MHz
Clock Gen
ICS
9LPR310-CLK
AUDIO CODEC
ALC880
AMPLIFIER
TPA6011A4
INTERNAL SPK
EARPHONE
JACK(SPDIF) X 1
MICPHONE JACK X
1
SODIMM1
+1.8VS
IEEE-1394A
TSB43AB22
CRYSTAL
24.576M HZ
DDR2 RAM BUS
533/667MHZ
SODIMM0
+1.8VS
AZALIA
MDC
RJ11
PCI BUS
SATA HDD X2
2.5"
CPU
Yonah
Socket 478
HOST BUS
667
MHZ
North Bridge
INTEL
945PM
DMI
South Bridge
INTEL
ICH7-M
RTC
THERMAL
ADM1032
PCIE
x16
IDE
PCIE X1
PCIE X1
PCIE X1
USBX8
USB CONN x3
ATI
M58
SATA
EC
LVDS
TMDS&CRT
CD-ROM
Vidalia
GIGA LAN
(82573L)
Mini
Card
NEW CARD
Buletooth
+5V
MASTER HDD
SECONDARY HDD
S-Video
LCD
DVI
RJ45
CRYSTAL
25M HZ
CARD READER
SMBus Diagram
+5V
+5V
DC_IN BD X2
LPC BUS
CRYSTAL
MASTER
EC
K/B CONTROLLER
ITE8510
PS/2 & GPIO
A A
FLASH ROM
5
4
T/PINT K/B
3
32.768K
PS/2 & GPIO
REMOTE IR
CHARGERFAN
BATTERY
2
South
Bridge
SMBus 1
KBC
SMBus 2
Title
Size Document Number Rev
3220
Date: Sheet
DDR DIMM
Clock Gen
Thermal Sensor for CPU
BATTERY
UNIWILL COMPUTER CORP.
P53IA0
SYSTEM BLOCK DIAGRAM
1
233Friday, September 22, 2006
of
C
5
4
3
2
1
POWER BLOCK DIAGRAM
VID0
VID1
D D
VID2
VID3
ISL 6262
VID4
VIN
RQA130
RQW220
CPU_CORE
OZ818 RSS090N03
VIN
VID5
+1.8VS
RT9173B
AO4422
+0.9VS
+1.8V
VID6
SI2301
+5VA
+3.3VA
+1.5VS
+1.05VS
+12VS
AO4422
SI4835
AO4422
SI4835
AO4422
AO4422
+5VS
+5V
+3.3VS
+3.3V
RT9173B
+1.5V
+2.5VS
+1.05V
POWER Sequence
+3VA,+5VA,+12VA
PWRSW
.
+3.3VS_ON
+5VS,+12VS
+3.3VS
+1.5VS_ON
.
+1.05VS_ON
.
+1.8V_DDR_ON
.
+1.5VS
+1.05VS
+1.8VS
.
RSMRST#
.
PWRBTN#
.
+5V_ON
+3.3V
+2.5V
.
+1.8V_ON
+1.8V
+1.05V
+1.5V
.
Vcore_ON
Vcore
PWROK
.
H_PWRGD
PCIRST#/PLTRST#
CPURST#
+5V
+3.3VS_ON
+3.3VS_ON
+5V_ON
+5V_ON
+1.8V_ON
+1.8V_ON
+1.8V_ON
120ms
60ms
20ms
100ms
?ms
EC debouns 100ms
880ms
?ms
?ms
5ms
300ms
VIN
RSS090N03
C C
SC1404
+12VA
VIN
RSS090N03
B B
VIN
OZ813
RSS090N03
VIN
RSS090N03
A A
.
EC Control Pin
5
4
3
2
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
C
3220
Date: Sheet
P53IA0
POWER DIAGRAM
1
of
333Friday, September 22, 2006
C
5
4
3
2
1
ICH6-M
GPIO
BM_BUSY#
GPI0
GP7
GP8
EC_EXTSMI#
SMB_ALERT#
GPI11
D D
C C
B B
A A
GPI12
GPI13
GPO18
GPO19
GPO20
GPO21
GPO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
PM_STPPCI_ICH#
PM_STPCPU_ICH#
TPM_EN
SATA0_GP
PNLSW1
PNLSW2
PNLSW0
PM_CLKRUN#
GPCF0
GPCF1
GPCF2
GPCF3
GPCF4
GPCF5
GPCF6
GPCF7
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPH0
GPH1
GPH2
GPH3
GPH4
GPH5
GPH6
GPH7
GPG4
GPG5
GPG6
GPG7
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
GPE0
GPE1
GPE2
GPE3
GPE4
GPE5
GPE6
GPE7
GPD0
GPD1
GPD2
GPD3
GPD4
GPD5
GPD6
GPD7
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
ITE8510E
GPIO
RF_SW#
SILENT#/
IR_PS2CLK1
IR_PS2DAT1
TP_CLK
TP_DATA
MAIL#
BROWSER#
SCROLL#
CAPS#
NUM#
CHG_R_LED#
CHG_G_LED#
SUSLED_LED#
VOLMAX
+1.8V_DDR_ON
+1.8V_ON
+1.05VS_ON
+3.3VS_ON
+5V_ON
SET_V
+1.5VS_ON
VCORE_ON
TP_DISABLE
LCDSW
MUTE#
EXTTS#0
CELERON_VO_DET
CPPE#
PM_RSMRST#
BAT_SMBCLK
BAT_SMBDAT
H_A20GATE
H_RCIN#
RFLED_ON#
NA
CPU_BSEL0
NA
NA
PWRSW
LID#
PCM#
PM_SLP_S3#
ADAP_IN
REMOTE_ON#
PCI_RST#/PLT_RST#
EC_EXTSMI#
PM_SLP_S4#
PM_THROTTLING#
FAN_SPD#
EC_PREST#
BTL_BEEP
EC_VID1
EC_VID2
EC_VID3
EC_VID4
SMP1_EN#
SMP2_EN#
PWRBTN#
GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
ADC0
ADC1
ADC2
ADC3
DAC0
DAC1
DAC2
DAC3
ITE8510E
GPIO
PWROK
BAT2_SMBCLK
BAT2_SMBDAT
SB_ALERT#1
SB_ALERT#2
TP_LED#
CHG_ON
SILENT_LED#
BAT_TEMP
ADAPTOR_I
DDR2_TEMP
VGA_TEMP
BRIGHTADJ
CHG_I
FAN_CTRL0
NA
2.0G
2.2G
2.26G
2.4G
2.5G
2.53G
2.6G
2.66G
2.8G
3.06G
VCC
+3.3V
+3.3VA
+2.5V
+1.5V
+VCCP
+VCC_GMCH_CORE
VCC
+3.3V
+3.3VA
+1.5V
+1.5VA
+3.3VA_RTC
CPU CORE(V)
CPU
ICC(mA)
35.7
1.525
1.525
37.5
38.1
1.525
1.525
39.3
1.525
40
40.4
1.525
41.05
1.525
43.35
1.525
44.86
1.525
55.9
1.525
MCHE
ICC(mA)
108.19
501.3
1390
33.4
10
266
ICH6-M
ICC(mA) W
275
487
27
0.003
W
0.357
1.254
2.502
0.084
0.018
0.452
0.315
0.909
0.876
0.049
0.00001
W
54.3
57.1
58.0
59.8
61.0
61.5
62.6
66.1
68.4
85.2
TEMP( )
70
TEMP( )
70
TEMP( )
69
70
70
71
72
72
72
74
75
81
+3.3V
+3.3V(DVDD)
ITE8510E
ICC(mA)
VCC
+3.3V
300
CLOCK GENERATOR
ICC(mA)
VCC
180
ALC880
VCC
ICC(mA)
71
TPA6011A4
ICC(mA)
VCC
3.3V9630
ADM1032
VCC
ICC
+3.3V
170uA
0.594
0.234
0.099W
0.56mW
W
1
W
W
W
W
TEMP( )
70
TEMP( )
70
TEMP( )
70
TEMP( )
85
TEMP( )
150
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet
3220
P53IA0
GPIO & POWER CONSU
1
C
of
433Friday, September 22, 2006
5
H_A#[31:3]8
D D
H_ADSTB#08
H_REQ#[4:0]8
H_A#[31:3]8
C C
H_STPCLK#16
B B
CPU Thermal Sensor
+3.3V
C451
2200p
A A
H_ADSTB#18
H_A20M#16
H_FERR#16
H_IGNNE#16
H_INTR16
H_NMI16
H_SMI#16
R412 200_1
H_THERMDA
H_THERM#
H_THERMDC
R26 0
C459
2.2U_6.3V_X5R
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
2
4
3
5
Z0505
Z0511
U22
D+
THERM#
D-
1
VDD
GND
5
ADATA
SCLK
ALERT
ADM1032
7
8
6
SMBDAT_EC 7,25
SMBCLK_EC 7,25
PSB533
PSB667
4
H_ADS# 8
H_BNR# 8
H_BPRI# 8
H_DEFER# 8
H_DRDY# 8
H_DBSY# 8
H_BREQ#0 8
H_INIT# 16
H_LOCK# 8
H_CPURST# 8
H_TRDY# 8
H_HIT# 8
H_HITM# 8
PM_THRMTRIP# 9,16
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
4
U4-1
J4
A{3}#
L4
A{4}#
M3
A{5}#
K5
A{6}#
M1
A{7}#
N2
A{8}#
J1
A{9}#
N3
A{10}#
P5
A{11}#
P2
A{12}#
L1
A{13}#
P4
A{14}#
H_RS#[2:0]
P1
A{15}#
R1
A{16}#
L2
ADSTB{0}#
K3
REQ{0}#
H2
REQ{1}#
K2
REQ{2}#
+1.05V
J3
REQ{3}#
L5
REQ{4}#
Y2
A{17}#
R18
U5
A{18}#
R3
A{19}#
56_OP
W6
A{20}#
U4
A{21}#
Y5
A{22}#
U2
A{23}#
R4
A{24}#
T5
A{25}#
T3
A{26}#
W3
A{27}#
W5
A{28}#
Y4
A{29}#
W2
A{30}#
Y1
A{31}#
V4
ADSTB{1}#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
AA1
RSVD{01}
AA4
RSVD{02}
AB2
RSVD{03}
AA3
RSVD{04}
M4
RSVD{05}
N5
RSVD{06}
T2
RSVD{07}
V3
RSVD{08}
B2
RSVD{09}
C3
RSVD{10}
R55 0
B25
RSVD{11}
I24074326
R56 0
R66 0
ADDR GROUP 0 ADDR GROUP 1
H_CPURST#
BSEL2
0
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
H_RS#[2:0] 8
CONTROL
LOCK#
RESET#
RS{0}#
RS{1}#
RS{2}#
TRDY#
HIT#
HITM#
BPM{0}#
BPM{1}#
BPM{2}#
BPM{3}#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
XDP/ITP SIGNALS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
PM_THRMTRIP#
THERM
THERMTRIP#
BCLK{0}
BCLK{1}
H CLK
Close to NB
RSVD{12}
+1.05V
RSVD{13}
RSVD{14}
R96
RSVD{15}
RSVD{16}
RSVD{17}
1K
RESERVED
RSVD{18}
RSVD{19}
RSVD{20}
R100 1K
+1.05V
R111
1K
R110 1K
+1.05V
R107
1K
R108 1K
BSEL1 BSEL0
0
11
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
B1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
A25
C7
A22
A21
T22
D2
F6
D3
C1
AF1
D22
C23
C24
H_IERR#
Z0506
TCK
TDI
TDO
TMS
TRST#
H_PROCHOT#
H_THERMDA
H_THERMDC
10
MHZ
133
166
3
R407
1K_1
R408
2K_1
CLK_BSEL0 7
MCH_BSEL0 9
MCH_BSEL1 9
CLK_BSEL1 7
MCH_BSEL2 9
CLK_BSEL2 7
DK_MXM_THERM#26
3
2
H_D#[63:0]8
H_DSTBN#08
H_DSTBP#08
H_DINV#08
+1.05V
Layout note: 0.5"
max length.
CPU_BSEL125
H_THERM#
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#18
H_DSTBP#18 H_DSTBP#3 8
H_DINV#18
H_GTLREF
R70 1K_OP
R69 51_1
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
PM_THRMTRIP#
R386 1K
R375 0
R374 0
U4-2
E22
D{0}#
F24
D{1}#
E26
D{2}#
H22
D{3}#
F23
D{4}#
G25
D{5}#
E25
D{6}#
E23
D{7}#
K24
D{8}#
G24
D{9}#
J24
D{10}#
J23
D{11}#
H26
D{12}#
F26
D{13}#
K22
D{14}#
H25
D{15}#
H23
DSTBN{0}#
G22
DSTBP{0}#
J26
DINV{0}#
N22
D{16}#
K25
D{17}#
P26
D{18}#
R23
D{19}#
L25
D{20}#
L22
D{21}#
L23
D{22}#
M23
D{23}#
P25
D{24}#
P22
D{25}#
P23
D{26}#
T24
D{27}#
R24
D{28}#
L26
D{29}#
T25
D{30}#
N24
D{31}#
M24
DSTBN{1}#
N25
DSTBP{1}#
M26
DINV{1}#
AD26
GTLREF
TEST1
C26
TEST1
TEST2
D25
TEST2
B22
BSEL{0}
B23
BSEL{1}
C21
BSEL{2}
I24075270
H_DPRSTP# Layout
routing is
ICH-7 -> CPU -> IMVP-6
sequency
CPU_CORE
R385
100K
Z0508
Q55
Z0507
B
2N3904
C433
E C
0.1u_Y5V
+3.3V
R369
R373
100K
100K
Z0510
Q50
Z0509
B
2N3904
C419
E C
0.1u_Y5V
DATA GRP 0
DATA GRP 1
MISC
2
C432
1u/10V
C401
1u/10V
DATA GRP 2
DATA GRP 3
B
B
D{32}#
D{33}#
D{34}#
D{35}#
D{36}#
D{37}#
D{38}#
D{39}#
D{40}#
D{41}#
D{42}#
D{43}#
D{44}#
D{45}#
D{46}#
D{47}#
DSTBN{2}#
DSTBP{2}#
DINV{2}#
D{48}#
D{49}#
D{50}#
D{51}#
D{52}#
D{53}#
D{54}#
D{55}#
D{56}#
D{57}#
D{58}#
D{59}#
D{60}#
D{61}#
D{62}#
D{63}#
DSTBN{3}#
DSTBP{3}#
DINV{3}#
COMP{0}
COMP{1}
COMP{2}
COMP{3}
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
Q54
2N3904
E C
Q51
2N3904
E C
H_D#32
AA23
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
W25
H_D#37
U23
H_D#38
U25
H_D#39
U22
H_D#40
AB25
H_D#41
W22
H_D#42
Y23
H_D#43
AA26
H_D#44
Y26
H_D#45
Y22
H_D#46
AC26
H_D#47
AA24
W24
Y25
V23
H_D#48
AC22
H_D#49
AC23
H_D#50
AB22
H_D#51
AA21
H_D#52
AB21
H_D#53
AC25
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AD24
H_D#58
AE21
H_D#59
AD21
H_D#60
AE25
H_D#61
AF25
H_D#62
AF22
H_D#63
AF26
AD23
AE24
AC20
COMP0
R26
COMP1
U26
COMP2
U1
COMP3
V1
E5
B5
D24
D6
D7
SLP#
AE6
PS1#
AUX_OFF# 29
1
H_D#[63:0] 8
H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8
H_D#[63:0] 8H_D#[63:0]8
H_DSTBN#3 8
H_DINV#3 8
R413 27.4_1
R414 54.9_1
R359 27.4_1
R360 54.9_1
H_DPRSTP# 16,27
H_DPSLP# 16
H_DPWR# 8
H_PWRGD 16
H_CPUSLP# 8,16
H_PSI# 27
For current return path
+1.05V
C74
C70
1000P
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
Date: Sheet
1000P
1000P_0402
H_IERR#
H_PROCHOT#
H_STPCLK#
TDO
TMS
TDI
H_CPURST#
TRST#
TCK
P53IA0
CPU Yonah-1/2
C90
Close
CPU
R61 56
R62 56
R366 150_1
R20 54.9_1_OP
R35 39.2_1_OP
R36 150_1_OP
R23 54.9_1_OP
R38 680
R32 27.4_1
1
+1.05V
533Friday, September 22, 2006
of
C
5
4
3
2
1
CPU_CORE
U4-3
A7
VCC001
A9
VCC002
D D
C C
B B
A10
VCC003
A12
VCC004
A13
VCC005
A15
VCC006
A17
VCC007
A18
VCC008
A20
VCC009
B7
VCC010
B9
VCC011
B10
VCC012
B12
VCC013
B14
VCC014
B15
VCC015
B17
VCC016
B18
VCC017
B20
VCC018
C9
VCC019
C10
VCC020
C12
VCC021
C13
VCC022
C15
VCC023
C17
VCC024
C18
VCC025
D9
VCC026
D10
VCC027
D12
VCC028
D14
VCC029
D15
VCC030
D17
VCC031
D18
VCC032
E7
VCC033
E9
VCC034
E10
VCC035
E12
VCC036
E13
VCC037
E15
VCC038
E17
VCC039
E18
VCC040
E20
VCC041
F7
VCC042
F9
VCC043
F10
VCC044
F12
VCC045
F14
VCC046
F15
VCC047
F17
VCC048
F18
VCC049
F20
VCC050
AA7
VCC051
AA9
VCC052
AA10
VCC053
AA12
VCC054
AA13
VCC055
AA15
VCC056
AA17
VCC057
AA18
VCC058
AA20
VCC059
AB9
VCC060
AC10
VCC061
AB10
VCC062
AB12
VCC063
AB14
VCC064
AB15
VCC065
AB17
VCC066
AB18
VCC067
I24088053
QT1608GRL600 = 200mA
QT1608RL120 = 200mA
QT1608RL600 = 200 mA
QT1608RL030 = 500mA
QT1608RL060 = 500mA
VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099
VCC100
VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCA
VCCSENSE
VSSSENSE
CPU_CORE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
AD6
VID0
AF5
VID1
AE5
VID2
AF4
VID3
AE3
VID4
AF2
VID5
AE2
VID6
AF7
AE7
Z0601
+1.05V
+1.5V
B4
0
Close to Pin
H_VID0 14
H_VID1 14
H_VID2 14
H_VID3 14
H_VID4 14
H_VID5 14
H_VID6 14
VCORE_VCCSENSE 27 VCORE_C- 27
VCORE_VSSSENSE 27
C73
4.7U_10V_0805
0.01u
CPU_CORE
C414
C20
C28
4.7U_10V_0805
4.7U_10V_0805
C411
C55
4.7U_10V_0805
C439
1u/10V
C37
1u/10V
C45
1000P
C425
0.1u_Y5V
C75
C417
C429
+
+
220U_2V_POS_OP
220U_2V_POS
4.7U_10V_0805
C408
1u/10V
C430
1u/10V
C423
1000p
0.1u_Y5V
4.7U_10V_0805
C44
C30
1u/10V
1u/10V
C32
C436
1u/10V
C438
1000p
C397
C427
0.1u_Y5V
JP5 CLOSE
JP6 CLOSE
4.7U_10V_0805
C412
C48
1u/10V
1u/10V
1u/10V
C406
1000p
C399
0.1u_Y5V
12
12
C442
0.1u_Y5V
C54
4.7U_10V_0805
C409
4.7U_10V_0805
C43
1u/10V
C29
1000P
C395
0.1u_Y5V
VCORE_C+ 27
C407
1u/10V
C448
1u/10V
C416
1000p
C62
C40
4.7U_10V_0805
C410
4.7U_10V_0805
C47
1u/10V
C437
1000p
C50
0.1u_Y5V
4.7U_10V_0805
C46
1u/10V
C435
4.7U_10V_0805
C21
1u/10V
C413
1000p
C65
0.1u_Y5V
C24
C25
C31
1000P
1000P
more than P71
Modify 10
U4-4
A4
VSS001
A8
VSS002
A11
VSS003
A14
VSS004
A16
VSS005
A19
VSS006
A23
VSS007
A26
VSS008
B6
VSS009
B8
VSS010
B11
VSS011
B13
VSS012
B16
VSS013
B19
VSS014
B21
VSS015
B24
VSS016
C5
VSS017
C8
VSS018
C11
VSS019
C14
VSS020
C16
VSS021
C19
VSS022
C2
VSS023
C22
VSS024
C25
VSS025
D1
VSS026
D4
VSS027
D8
VSS028
D11
VSS029
D13
VSS030
D16
VSS031
D19
VSS032
D23
VSS033
D26
VSS034
E3
VSS035
E6
VSS036
E8
VSS037
E11
VSS038
E14
VSS039
E16
VSS040
E19
VSS041
E21
VSS042
E24
VSS043
F5
VSS044
F8
VSS045
F11
VSS046
F13
VSS047
F16
VSS048
F19
VSS049
F2
VSS050
F22
VSS051
F25
VSS052
G4
VSS053
G1
VSS054
G23
VSS055
G26
VSS056
H3
VSS057
H6
VSS058
H21
VSS059
H24
VSS060
J2
VSS061
J5
VSS062
J22
VSS063
J25
VSS064
K1
VSS065
K4
VSS066
K23
VSS067
K26
VSS068
L3
VSS069
L6
VSS070
L21
VSS071
L24
VSS072
M2
VSS073
M5
VSS074
M22
VSS075
M25
VSS076
N1
VSS077
N4
VSS078
N23
VSS079
N26
VSS080
P3
VSS081
I24089147
VSS082
VSS083
VSS084
VSS085
VSS086
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
A A
5
4
+1.05V
C183
0.1u_Y5V
C181
0.1u_Y5V
C57
0.1u_Y5V
C58
0.1u_Y5V
C14
0.1u_Y5V
3
C59
0.1u_Y5V
C15
0.1u_Y5V
C16
0.1u_Y5V
C17
0.1u_Y5V
C60
0.1u_Y5V
C19
4.7U_10V_0805
4.7U_10V_0805
C56
C53
4.7U_10V_0805
2
C18
4.7U_10V_0805
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
Date: Sheet
P53IA0
CPU Yonah-2/2
633Friday, September 22, 2006
1
of
C
5
Reserved FOR EMI
R175 2.2K_OP
R171 100
Modify 8
Y2
14.318MHz_DIP
C213
33p
PCI4
PCI3
PCI2
CLK_BSEL1
CLKBSEL0
PCICLK_1394_A24
TEST_PCI25
CLK_PCI_LPC25
CLK_PCI17
PCICLK_LAN23
PCICLK_RAID32
CLK_ICH1417
CLK_USB4817
CLKBSEL2
CLKBSEL1
XTAL_OUT
XTAL_IN
SATA_CLKP16
SATA_CLKN16
MINICARD_CLK_REQ#20
Ce = 2*CL - ( Cs + Ci )
CL = Crystal Load Cap = 20P
Ci = IC internal Cap = 5P
Cs = 2P
Ce = Crystal external Cap = 33P
C194
0.1u_Y5V
R176 33
R168 33
C206 10p_OP
Bsel [0,2]
Vil = 0.3
Vih = 0.7
+3.3V
C212
33p
C598 10p_OP
C208 10p_OP
C201 10p_OP
C198 10p_OP
R513 2.2K
R510 2.2K
R185 10M_OP
D D
SELDOT , 1= Pin 14/15 DOT 96MHZ , Pin 17/18 LCDCLK
0= Pin 14/15 27MHZ Fix/SS Pin 17/18 PCIEX
C C
CLK_BSEL25
CLK_BSEL15
CLK_BSEL05
B B
CLK_VDDA
R161
2.2
VDD_A_CR
C195
4.7U_10V_0805
R512 33
R639 33
R528 33
R179 33
R1059 33
R1060 33
R151 22
R152 22
4
CLKGEN_DATA
CLKGEN_CLK
C187
C185
0.1u_Y5V
PCI-E
Power
PCI4
Z0702
PCI3
PCI2
CLKBSEL2
CLKBSEL1
CLKBSEL0
Z0711
Z0712
XTAL_OUT
XTAL_IN
IREF
R487
4.3K_1
REQ1# = PCI-E 0,6
REQ2# = PCI-E 1,8
REQ3# = PCI-E 2,4
REQ4# = PCI-E 3,5,7
C186
0.1u_Y5V
0.1u_Y5V
0.1u_Y5V
U29
42 56
VDDPCIEX VDDREF
50 45
VDDCPU VDDA
5
PCICLK3
4
PCICLK2_2X
3
PCICLK1_2X
64
PCICLK0_2X
9
SELDOT/ PCICLK_F1
8
PCICLK_F0
61
FLSC/REF1
60
FLSB/REF0
12
FLSA/USB_48M_2X
55
SDATA
54
SCLK
17
LCD_SSCGT/PCIEXOT
18
LCD_SSCGC/PCIEXOC
26
SATACLKT
27
SATACLKC
33
PEREQ4#
32
PEREQ3#
34
PEREQ2#
16
PEREQ1#
57
X2_OUT
58
X1_IN
47
VREF
GND
9LPR310-CLK
261321293753
7
GND
C190
VDDPCI1
GND
GND
4.7U_10V_0805
PCI
Power
1
VDDPCI0
PCI/PCIEX_STOP#
GND
GND
GND
C188
VDD48VDDPCIEX
PLL
Power
GNDA
CPU_STOP#
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
PCIEXT4
PCIEXC4
PCIEXT5
PCIEXC5
PCIEXT6
PCIEXC6
PCIEXT7
PCIEXC7
PCIEXT8
PCIEXC8
DOTT_96M
DOTC_96M
VTT_PWRGD#/PD
GND
59
3
Z0703
Z0704
R180
2.2
1128
CLK_VDDA
46
Z0705
63
Z0706
62
CPU1
49
CPU#1
48
CPU0
52
CPU#0
51
PCIE5
19
PCIE#5
20
PCIE4
22
PCIE#4
23
PCIE3
24
PCIE#3
25
PCIE2
30
PCIE#2
31
Z0707
36
Z0708
35
Z0709
39
Z0710
38
41
40
44
GCLK => PCI-E & DMI (100MHZ)
43
DREFCLK => Dispaly PLLA ( nun- ss 96MHZ)
14
DRESSFCLK => Display LVDS PLLB ( ss 100MHZ)
15
10
0.1u_Y5V
VDD_REF_CR
C203
C199
4.7U_10V_0805_OP
R530 0
R523 0_OP
R497 22
R494 22
R165 22
R163 22
R160 22
R159 22
R493 22
R486 22
R483 22
R481 22
R479 22
R471 22
R480 22
R472 22
R484 22
R482 22
Xtal
Power
0.1u_Y5V
R178
1
Modify 3
C593
C603
C209
4.7U_10V_0805
0.1u_Y5V
C202 0.1u_Y5V
PM_STPPCI# 17
PM_STPCPU# 17
CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8
CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5
GCLK 9
GCLK# 9
CLK_PCIE_NEW_CARD 20
CLK_PCIE_NEW_CARD# 20
CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17
CLK_PCIE_MXM 26
CLK_PCIE_MXM# 26
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_Mini card 20
CLK_PCIE_Mini card# 20
2
B9
QT1608RL600
B10
QT1608RL600
200mA
200mA
+3.3V
1
+3.3V
R502
10K
6262CLK_EN# 27
BSEL2
A A
PSB533
PSB667
PSB533
PSB667
FS3FS4
00
0
00
01
01
BSEL1
FSLC
FSLB
0
01
0
01
1
01
FS3 , FS 4 SEETING BY I2C BUS ??????
5
BSEL0
FSLA
1
1
CPU
PCI
PCI-E
33 100
33
SPREAD %
MHZ
0.5% DOWN
+/- 0.25%
100
CENTER
4
MHZ
MHZ
133
166
133
166
SB_SMB_DATA13,17
SMBDAT_EC5,25
SMBCLK_EC5,25
SB_SMB_CLK13,17
R173 0_OP
R172 0
R169 0
R170 0_OP
3
CLKGEN_DATA
CLKGEN_CLK
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
2
Date: Sheet
P53IA0
CLOCK GEN ICS9LPR310
733Friday, September 22, 2006
1
C
of
5
4
3
2
1
U24J
AT23
VSS_180
AN23
VSS_181
AM23
VSS_182
AH23
VSS_183
AC23
VSS_184
W23
VSS_185
K23
VSS_186
J23
D D
C C
B B
A A
VSS_187
F23
VSS_188
C23
VSS_189
AA22
VSS_190
K22
VSS_191
G22
VSS_192
F22
VSS_193
E22
VSS_194
D22
VSS_195
A22
VSS_196
BA21
VSS_197
AV21
VSS_198
AR21
VSS_199
AN21
VSS_200
AL21
VSS_201
AB21
VSS_202
Y21
VSS_203
P21
VSS_204
K21
VSS_205
J21
VSS_206
H21
VSS_207
C21
VSS_208
AW20
VSS_209
AR20
VSS_210
AM20
VSS_211
AA20
VSS_212
K20
VSS_213
B20
VSS_214
A20
VSS_215
AN19
VSS_216
AC19
VSS_217
W19
VSS_218
K19
VSS_219
G19
VSS_220
C19
VSS_221
AH18
VSS_222
P18
VSS_223
H18
VSS_224
D18
VSS_225
A18
VSS_226
AY17
VSS_227
AR17
VSS_228
AP17
VSS_229
AM17
VSS_230
AK17
VSS_231
AV16
VSS_232
AN16
VSS_233
AL16
VSS_234
J16
VSS_235
F16
VSS_236
C16
VSS_237
AN15
VSS_238
AM15
VSS_239
AK15
VSS_240
N15
VSS_241
M15
VSS_242
L15
VSS_243
B15
VSS_244
A15
VSS_245
BA14
VSS_246
AT14
VSS_247
AK14
VSS_248
AD14
VSS_249
AA14
VSS_250
U14
VSS_251
K14
VSS_252
H14
VSS_253
E14
VSS_254
AV13
VSS_255
AR13
VSS_256
AN13
VSS_257
AM13
VSS_258
AL13
VSS_259
AG13
VSS_260
P13
VSS_261
F13
VSS_262
D13
VSS_263
B13
VSS_264
AY12
VSS_265
AC12
VSS_266
K12
VSS_267
H12
VSS_268
E12
VSS_269
AD11
VSS_270
AA11
VSS_271
Y11
VSS_272
CALISTOGA
VSS
5
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
FSB I/O slew rate compensation
+1.05V
54.9_1
+1.05V
54.9_1
R422
H_YSCOMPH_XSCOMP
R87
Reference Voltage for RCOMP
+1.05V
R91
221_1
H_XSWING
C112
R92
0.1u_Y5V
100_1
+1.05V
R421
221_1
H_YSWING
C510
R420
0.1u_Y5V
100_1
Calibration FSB I/O Buffer
H_XRCOMP
R424
24.9_1
4
H_YRCOMP
R419
24.9_1
H_D#[63:0]5
CLK_MCH_BCLK7
CLK_MCH_BCLK#7
3
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
U24A
F1
H_D#_0
J1
H_D#_1
H1
H_D#_2
J6
H_D#_3
H3
H_D#_4
K2
H_D#_5
G1
H_D#_6
G2
H_D#_7
K9
H_D#_8
K1
H_D#_9
K7
H_D#_10
J8
H_D#_11
H4
H_D#_12
J3
H_D#_13
K11
H_D#_14
G4
H_D#_15
T10
H_D#_16
W11
H_D#_17
T3
H_D#_18
U7
H_D#_19
U9
H_D#_20
U11
H_D#_21
T11
H_D#_22
W9
H_D#_23
T1
H_D#_24
T8
H_D#_25
T4
H_D#_26
W7
H_D#_27
U5
H_D#_28
T9
H_D#_29
W6
H_D#_30
T5
H_D#_31
AB7
H_D#_32
AA9
H_D#_33
W4
H_D#_34
W3
H_D#_35
Y3
H_D#_36
Y7
H_D#_37
W5
H_D#_38
Y10
H_D#_39
AB8
H_D#_40
W2
H_D#_41
AA4
H_D#_42
AA7
H_D#_43
AA2
H_D#_44
AA6
H_D#_45
AA10
H_D#_46
Y8
H_D#_47
AA1
H_D#_48
AB4
H_D#_49
AC9
H_D#_50
AB11
H_D#_51
AC11
H_D#_52
AB3
H_D#_53
AC2
H_D#_54
AD1
H_D#_55
AD9
H_D#_56
AC1
H_D#_57
AD7
H_D#_58
AC6
H_D#_59
AB5
H_D#_60
AD10
H_D#_61
AD4
H_D#_62
AC8
H_D#_63
E1
H_XRCOMP
E2
H_XSCOMP
E4
H_XSWING
Y1
H_YRCOMP
U1
H_YSCOMP
W1
H_YSWING
AG2
H_CLKIN
AG1
H_CLKIN#
CALISTOGA
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_VREF
HOST
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
2
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
J7
W8
U3
AB10
K4
T7
Y5
AC4
K3
T6
AA5
AC5
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
E3
E7
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#_GMCH
H_A#[31:3] 5
+1.05V
C129
H_CPUSLP# 5,16
P53IA0
1
R101
100_1
R98
200_1
833Friday, September 22, 2006
of
H_ADS# 5
H_ADSTB#0 5
H_ADSTB#1 5
H_VREF
H_BNR# 5
H_BPRI# 5
H_BREQ#0 5
H_CPURST# 5
H_DBSY# 5
H_DEFER# 5
H_DPWR# 5
H_DRDY# 5
H_DINV#[3:0] 5
0.1u_Y5V_0402
H_DSTBN#[3:0] 5
H_DSTBP#[3:0] 5
H_HIT# 5
H_HITM# 5
H_LOCK# 5
H_REQ#[4:0] 5
H_RS#[2:0] 5
p71 not mout ,
they mount SB
R90 0
H_TRDY# 5
Title
Size Document Number Rev
Date: Sheet
side
UNIWILL COMPUTER CORP.
NB_945PM-1/5
3220
C
5
DMI_RXP[3:0]17
DMI_RXN[3:0]17
D D
DMI_TXP[3:0]17
DMI_TXN[3:0]17
R468 0
R470 0
R438 0
R441 0
GCLK7
GCLK#7
C C
as short as
possible
R97
40.2_1_OP
40.2_1_OP
B B
+1.8VS
R89
150_1
R88
150_1
+1.8VS
A A
R106
0.05A
MB_ODT313,14
MB_ODT213,14
MA_ODT113,14
MA_ODT013,14
M_OCDCOMP1
M_OCDCOMP0
MB_CS#313,14
MB_CS#213,14
MA_CS#113,14
MA_CS#013,14
MB_CKE313,14
MB_CKE213,14
MA_CKE113,14
MA_CKE013,14
MB_CK#313
MB_CK#413
MA_CK#113
MA_CK#013
MB_CK313
MB_CK413
MA_CK113
MA_CK013
M_VREF_MCH
C105
C169
0.1u_Y5V
0.1u_Y5V
R95
80.6_1
M_RCOMPN
M_RCOMPP
R94
80.6_1
DMI_RXP3
DMI_RXP2
DMI_RXP1
DMI_RXP0
DMI_RXN3
DMI_RXN2
DMI_RXN1
DMI_RXN0
DMI_TXP3
DMI_TXP2
DMI_TXP1
DMI_TXP0
DMI_TXN3
DMI_TXN2
DMI_TXN1
DMI_TXN0
Z0901
Z0902
Z0906
Z0912
M_VREF_MCH
M_RCOMPP
M_RCOMPN
U24B
AG41
DMI_TXP_3
AF37
DMI_TXP_2
AE41
DMI_TXP_1
AC37
DMI_TXP_0
AH41
DMI_TXN_3
AG37
DMI_TXN_2
AF41
DMI_TXN_1
AE37
DMI_TXN_0
AG39
DMI_RXP_3
AF35
DMI_RXP_2
AE39
DMI_RXP_1
AC35
DMI_RXP_0
AH39
DMI_RXN_3
AG35
DMI_RXN_2
AF39
DMI_RXN_1
AE35
DMI_RXN_0
D41
D_REFSSCLKIN
C40
D_REFSSCLKIN#
A26
D_REFCLKIN
A27
D_REFCLKIN#
AG33
G_CLKIN
AF33
G_CLKIN#
AK41
SM_VREF_1
AK1
SM_VREF_0
AT9
SM_RCOMP
AV9
SM_RCOMP#
AU21
SM_ODT_3
AY20
SM_ODT_2
BA12
SM_ODT_1
BA13
SM_ODT_0
AF10
SM_OCDCOMP_1
AL20
SM_OCDCOMP_0
AW21
SM_CS#_3
AY21
SM_CS#_2
AW12
SM_CS#_1
AW13
SM_CS#_0
AY29
SM_CKE_3
BA29
SM_CKE_2
AT20
SM_CKE_1
AU20
SM_CKE_0
AY40
SM_CK#_3
AY7
SM_CK#_2
AT1
SM_CK#_1
AW35
SM_CK#_0
AW40
SM_CK_3
AW7
SM_CK_2
AR1
SM_CK_1
AY35
SM_CK_0
CALISTOGA
Only Base on Discreted VGA
VCCA_DPLLA , VCCA_DPLLB => NC
DREF_CLKP / DREF_SSCLKP = GND
DREF_CLKN / DREF_SSCLKN = GND
VCCA_DPLLA , VCCA_DPLLB =>1.5V
DREF_CLKP / DREF_SSCLKP = 1.5V
DREF_CLKN / DREF_SSCLKN = GND
For MEN bus throttling
+3.3V
R114 10K
R115 10K
DMI CLK
DDR MUXING
Check with S/W
5
NC
SDVO_CTRLDATA
SDVO_CTRLCLK
MISC
PM_THRMTRIP#
PM
CFG
RSVD
PM_EXTTS#1
PM_EXTTS#0
4
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
CLK_REQ#
LT_RESET#
RSTIN#
PWROK
PM_EXTTS#_1
PM_EXTTS#_0
PM_BMBUSY#
CFG_20
CFG_19
CFG_18
CFG_17
CFG_16
CFG_15
CFG_14
CFG_13
CFG_12
CFG_11
CFG_10
CFG_9
CFG_8
CFG_7
CFG_6
CFG_5
CFG_4
CFG_3
CFG_2
CFG_1
CFG_0
RSVD_13
RSVD_12
RSVD_11
RSVD_10
RSVD_9
RSVD_8
RSVD_7
RSVD_6
RSVD_5
RSVD_4
RSVD_3
RSVD_2
RSVD_1
4
A3
A39
A4
A40
AW1
GCLK => PCI-E & DMI (100MHZ)
AW41
DREFCLK => Dispaly PLLA ( nun- ss 96MHZ)
AY1
AY41
DRESSFCLK => Display LVDS PLLB ( ss 100MHZ)
B2
B41
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
NC0
SDVODATA has internal pull down
BA1
0= no DVO device
BA2
BA3
1= DVO device present
BA39
SDVOCLK has internal pull
BA40
down .
BA41
C1
C41
D1
Asserted to control the raw PCI-E clock
Z0907
R117 0_OP
H32
K28
H27
H28
AH34
AH33
G6
H26
F25
G28
J26
K27
J25
H15
G18
H16
C15
K15
G15
D15
E16
G16
D16
D19
E18
F15
E15
F18
J18
K18
K16
D27
D28
A34
A35
A41
J19
H7
AF11
AG11
F7
F3
R32
T32
NB_SYNC# 17
Asserted to synchronize with ICH on fault
Z0911
R157 100
DELAY_VR_PWRGOOD
ICH7_THRMTRIP#
PM_EXTTS#1
R112 0
PM_EXTTS#0
BM_BUSY# 17
GHCH integrated graphics busy
CFG19 12
CFG18 12
R104 1K_OP
R105 1K_OP
CFG10CFG2
1
1
1
CFG16 12
CFG9 12
CFG5 12
MCH_BSEL2 5
MCH_BSEL1 5
MCH_BSEL0 5
Base on
RSTIN#
0
0
Z0903
Z0904
CFG0
Reserve for NB THRMTRIP# ( O/D Vccp )
ICH7_THRMTRIP#
IPU
PM_EXTTS#0 13
+1.5V
A C
Host
Clock
frequency
PLT_RST# 17,19,20,25,26
DELAY_VR_PWRGOOD 17
BAT54D6
+1.05V
533
667
AC
BAT54_OPD5
3
PM_DPRSLPVR 17,27
EXTTS#0 14,25
C196
1000P
PM_THRMTRIP# 5,16
3
+1.05V
+1.5V
Colse to NB
U24C
D32
L_BKLTCTL
J30
L_BKLTEN
H30
L_CLKCTLA
H29
L_CLKCTLB
G26
L_DDC_CLK
G25
L_DDC_DATA
B38
L_IBG
C35
L_VBG
F32
L_VDDEN
C33
L_VREFH
C32
L_VREFL
A33
LA_CLK#
A32
LA_CLK
E27
LB_CLK#
E26
LB_CLK
C37
LA_DATA#_0
B35
LA_DATA#_1
A37
LA_DATA#_2
B37
LA_DATA_0
B34
LA_DATA_1
A36
LA_DATA_2
G30
LB_DATA#_0
D30
LB_DATA#_1
F29
LB_DATA#_2
F30
LB_DATA_0
D29
LB_DATA_1
F28
LB_DATA_2
A16
TV_DACA_OUT
C18
TV_DACB_OUT
A19
TV_DACC_OUT
J20
TV_IREF
B16
TV_IRTNA
B18
TV_IRTNB
B19
TV_IRTNC
K30
TV_DCONSEL0
J29
O/A
TV_DCONSEL1
E23
CRT_BLUE
D23
CRT_BLUE#
C22
CRT_GREEN
B22
CRT_GREEN#
A21
CRT_RED
B21
CRT_RED#
C26
CRT_DDC_CLK
C25
CRT_DDC_DATA
G23
CRT_HSYNC
J22
CRT_IREF
H23
CRT_VSYNC
DELAY_VR_PWRGOOD
C193
0.1u_Y5V
CALISTOGA
2
LVDS
TV
VGA
2
1
PEG_RXN[15..0] 26
PEG_RXP[15..0] 26
PEG_TXN[15..0] 26
PEG_TXP[15..0] 26
1
+1.5V
933Friday, September 22, 2006
of
EXP_A_COMPO
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
PCI-EXPRESS GRAPHICS
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
CFG20 ( IPD ) => 1= Only SDVO or PCI-E
0 = SDVO and PCI-E
CFG7 ( IPU ) => 1= Mobility CPU
0 = Reverse
PEG_RXN0
F34
PEG_RXN1
G38
PEG_RXN2
H34
PEG_RXN3
J38
PEG_RXN4
L34
PEG_RXN5
M38
PEG_RXN6
N34
PEG_RXN7
P38
PEG_RXN8
R34
PEG_RXN9
T38
PEG_RXN10
V34
PEG_RXN11
W38
PEG_RXN12
Y34
PEG_RXN13
AA38
PEG_RXN14
AB34
PEG_RXN15
AC38
PEG_RXP0
D34
PEG_RXP1
F38
PEG_RXP2
G34
PEG_RXP3
H38
PEG_RXP4
J34
PEG_RXP5
L38
PEG_RXP6
M34
PEG_RXP7
N38
PEG_RXP8
P34
PEG_RXP9
R38
PEG_RXP10
T34
PEG_RXP11
V38
PEG_RXP12
W34
PEG_RXP13
Y38
PEG_RXP14
AA34
PEG_RXP15
AB38
PEG_TXN0
F36
PEG_TXN1
G40
PEG_TXN2
H36
PEG_TXN3
J40
PEG_TXN4
L36
PEG_TXN5
M40
PEG_TXN6
N36
PEG_TXN7
P40
PEG_TXN8
R36
PEG_TXN9
T40
PEG_TXN10
V36
PEG_TXN11
W40
PEG_TXN12
Y36
PEG_TXN13
AA40
PEG_TXN14
AB36
PEG_TXN15
AC40
PEG_TXP0
D36
PEG_TXP1
F40
PEG_TXP2
G36
PEG_TXP3
H40
PEG_TXP4
J36
PEG_TXP5
L40
PEG_TXP6
M36
PEG_TXP7
N40
PEG_TXP8
P36
PEG_TXP9
R40
PEG_TXP10
T36
PEG_TXP11
V40
PEG_TXP12
W36
PEG_TXP13
Y40
PEG_TXP14
AA36
PEG_TXP15
AB40
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
Date: Sheet
P53IA0
NB NB DDRCLK_VGA_PCIEXPR-2/5
R469 24.9_1
PEG_COMP
D40
EXP_A_COMPI
D38
C
5
MA_DQ[63:0]13
D D
C C
B B
MA_DQ0
MA_DQ1
MA_DQ2
MA_DQ3
MA_DQ4
MA_DQ5
MA_DQ6
MA_DQ7
MA_DQ8
MA_DQ9
MA_DQ10
MA_DQ11
MA_DQ12
MA_DQ13
MA_DQ14
MA_DQ15
MA_DQ16
MA_DQ17
MA_DQ18
MA_DQ19
MA_DQ20
MA_DQ21
MA_DQ22
MA_DQ23
MA_DQ24
MA_DQ25
MA_DQ26
MA_DQ27
MA_DQ28
MA_DQ29
MA_DQ30
MA_DQ31
MA_DQ32
MA_DQ33
MA_DQ34
MA_DQ35
MA_DQ36
MA_DQ37
MA_DQ38
MA_DQ39
MA_DQ40
MA_DQ41
MA_DQ42
MA_DQ43
MA_DQ44
MA_DQ45
MA_DQ46
MA_DQ47
MA_DQ48
MA_DQ49
MA_DQ50
MA_DQ51
MA_DQ52
MA_DQ53
MA_DQ54
MA_DQ55
MA_DQ56
MA_DQ57
MA_DQ58
MA_DQ59
MA_DQ60
MA_DQ61
MA_DQ62
MA_DQ63
U24D
AJ35
SA_DQ0
AJ34
SA_DQ1
AM31
SA_DQ2
AM33
SA_DQ3
AJ36
SA_DQ4
AK35
SA_DQ5
AJ32
SA_DQ6
AH31
SA_DQ7
AN35
SA_DQ8
AP33
SA_DQ9
AR31
SA_DQ10
AP31
SA_DQ11
AN38
SA_DQ12
AM36
SA_DQ13
AM34
SA_DQ14
AN33
SA_DQ15
AK26
SA_DQ16
AL27
SA_DQ17
AM26
SA_DQ18
AN24
SA_DQ19
AK28
SA_DQ20
AL28
SA_DQ21
AM24
SA_DQ22
AP26
SA_DQ23
AP23
SA_DQ24
AL22
SA_DQ25
AP21
SA_DQ26
AN20
SA_DQ27
AL23
SA_DQ28
AP24
SA_DQ29
AP20
SA_DQ30
AT21
SA_DQ31
AR12
SA_DQ32
AR14
SA_DQ33
AP13
SA_DQ34
AP12
SA_DQ35
AT13
SA_DQ36
AT12
SA_DQ37
AL14
SA_DQ38
AL12
SA_DQ39
AK9
SA_DQ40
AN7
SA_DQ41
AK8
SA_DQ42
AK7
SA_DQ43
AP9
SA_DQ44
AN9
SA_DQ45
AT5
SA_DQ46
AL5
SA_DQ47
AY2
SA_DQ48
AW2
SA_DQ49
AP1
SA_DQ50
AN2
SA_DQ51
AV2
SA_DQ52
AT3
SA_DQ53
AN1
SA_DQ54
AL2
SA_DQ55
AG7
SA_DQ56
AF9
SA_DQ57
AG4
SA_DQ58
AF6
SA_DQ59
AG9
SA_DQ60
AH6
SA_DQ61
AF4
SA_DQ62
AF8
SA_DQ63
Value
AK34
AG34
AF34
AE34
AC34
C34
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
AW33
AV33
AR33
AE33
AB33
Y33
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
DDR SYSTEM MEMORY A
V33
T33
R33
M33
H33
G33
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
F33
D33
B33
AH32
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
4
MA_BA0
AU12
MA_BA1
AV14
MA_BA2
BA20
AY13
MA_DM0
AJ33
MA_DM1
AM35
MA_DM2
AL26
MA_DM3
AN22
MA_DM4
AM14
MA_DM5
AL9
MA_DM6
AR3
MA_DM7
AH4
MA_DQS0
AK33
MA_DQS1
AT33
MA_DQS2
AN28
MA_DQS3
AM22
MA_DQS4
AN12
MA_DQS5
AN8
MA_DQS6
AP3
MA_DQS7
AG5
MA_DQS#0
AK32
MA_DQS#1
AU33
MA_DQS#2
AN27
MA_DQS#3
AM21
MA_DQS#4
AM12
MA_DQS#5
AL8
MA_DQS#6
AN3
MA_DQS#7
AH5
MAA_A0
AY16
MAA_A1
AU14
MAA_A2
AW16
MAA_A3
BA16
MAA_A4
BA17
MAA_A5
AU16
MAA_A6
AV17
MAA_A7
AU17
MAA_A8
AW17
MAA_A9
AT16
MAA_A10
AU13
MAA_A11
AT17
MAA_A12
AV20
MAA_A13
AV12
AW14
Z1001
AK23
Z1002 Z1003
AK24
AY14
SA_WE#
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
MA_BA[2:0] 13,14
MA_CAS# 13,14
MA_DM[7:0] 13
MA_DQS[7:0] 13
MA_DQS#[7:0] 13
MAA_A[13:0] 13,14
MA_RAS# 13,14
TP3
TP4 TP1
MA_WE# 13,14
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
3
MB_DQ[63:0]13
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
MB_DQ0
MB_DQ1
MB_DQ2
MB_DQ3
MB_DQ4
MB_DQ5
MB_DQ6
MB_DQ7
MB_DQ8
MB_DQ9
MB_DQ10
MB_DQ11
MB_DQ12
MB_DQ13
MB_DQ14
MB_DQ15
MB_DQ16
MB_DQ17
MB_DQ18
MB_DQ19
MB_DQ20
MB_DQ21
MB_DQ22
MB_DQ23
MB_DQ24
MB_DQ25
MB_DQ26
MB_DQ27
MB_DQ28
MB_DQ29
MB_DQ30
MB_DQ31
MB_DQ32
MB_DQ33
MB_DQ34
MB_DQ35
MB_DQ36
MB_DQ37
MB_DQ38
MB_DQ39
MB_DQ40
MB_DQ41
MB_DQ42
MB_DQ43
MB_DQ44
MB_DQ45
MB_DQ46
MB_DQ47
MB_DQ48
MB_DQ49
MB_DQ50
MB_DQ51
MB_DQ52
MB_DQ53
MB_DQ54
MB_DQ55
MB_DQ56
MB_DQ57
MB_DQ58
MB_DQ59
MB_DQ60
MB_DQ61
MB_DQ62
MB_DQ63
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
U24H
AK39
SB_DQ0
AJ37
SB_DQ1
AP39
SB_DQ2
AR41
SB_DQ3
AJ38
SB_DQ4
AK38
SB_DQ5
AN41
SB_DQ6
AP41
SB_DQ7
AT40
SB_DQ8
AV41
SB_DQ9
AU38
SB_DQ10
AV38
SB_DQ11
AP38
SB_DQ12
AR40
SB_DQ13
AW38
SB_DQ14
AY38
SB_DQ15
BA38
SB_DQ16
AV36
SB_DQ17
AR36
SB_DQ18
AP36
SB_DQ19
BA36
SB_DQ20
AU36
SB_DQ21
AP35
SB_DQ22
AP34
SB_DQ23
AY33
SB_DQ24
BA33
SB_DQ25
AT31
SB_DQ26
AU29
SB_DQ27
AU31
SB_DQ28
AW31
SB_DQ29
AV29
SB_DQ30
AW29
SB_DQ31
AM19
SB_DQ32
AL19
SB_DQ33
AP14
SB_DQ34
AN14
SB_DQ35
AN17
SB_DQ36
AM16
SB_DQ37
AP15
SB_DQ38
AL15
SB_DQ39
AJ11
SB_DQ40
AH10
SB_DQ41
AJ9
SB_DQ42
AN10
SB_DQ43
AK13
SB_DQ44
AH11
SB_DQ45
AK10
SB_DQ46
AJ8
SB_DQ47
BA10
SB_DQ48
AW10
SB_DQ49
BA4
SB_DQ50
AW4
SB_DQ51
AY10
SB_DQ52
AY9
SB_DQ53
AW5
SB_DQ54
AY5
SB_DQ55
AV4
SB_DQ56
AR5
SB_DQ57
AK4
SB_DQ58
AK3
SB_DQ59
AT4
SB_DQ60
AK5
SB_DQ61
AJ5
SB_DQ62
AJ3
SB_DQ63
CALISTOGA
H25
E25
D25
A25
BA24
AU24
AL24
AW23
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
2
AT24
SB_BS_0
AV23
SB_BS_1
AY28
SB_BS_2
AR24
SB_CAS#
AK36
SB_DM_0
AR38
SB_DM_1
AT36
SB_DM_2
BA31
SB_DM_3
AL17
SB_DM_4
AH8
SB_DM_5
BA5
SB_DM_6
AN4
SB_DM_7
AM39
SB_DQS_0
AT39
SB_DQS_1
AU35
SB_DQS_2
AR29
SB_DQS_3
AR16
SB_DQS_4
AR10
SB_DQS_5
AR7
SB_DQS_6
AN5
SB_DQS_7
AM40
SB_DQS#_0
AU39
SB_DQS#_1
AT35
SB_DQS#_2
AP29
SB_DQS#_3
AP16
SB_DQS#_4
AT10
SB_DQS#_5
AT7
SB_DQS#_6
AP5
SB_DQS#_7
AY23
SB_MA_0
AW24
SB_MA_1
AY24
SB_MA_2
AR28
SB_MA_3
AT27
SB_MA_4
AT28
SB_MA_5
AU27
SB_MA_6
AV28
SB_MA_7
AV27
SB_MA_8
AW27
SB_MA_9
AV24
SB_MA_10
BA27
SB_MA_11
AY27
SB_MA_12
AR23
SB_MA_13
AU23
SB_RAS#
DDR SYSTEM MEMORY B
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
U24I
CALISTOGA
AK16
AK18
AR27
MB_BA0
MB_BA1
MB_BA2
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS0
MB_DQS1
MB_DQS2
MB_DQS3
MB_DQS4
MB_DQS5
MB_DQS6
MB_DQS7
MB_DQS#0
MB_DQS#1
MB_DQS#2
MB_DQS#3
MB_DQS#4
MB_DQS#5
MB_DQS#6
MB_DQS#7
MBA_A0
MBA_A1
MBA_A2
MBA_A3
MBA_A4
MBA_A5
MBA_A6
MBA_A7
MBA_A8
MBA_A9
MBA_A10
MBA_A11
MBA_A12
MBA_A13
Z1004
1
MB_BA[2:0] 13,14
MB_CAS# 13,14
MB_DM[7:0] 13
MB_DQS[7:0] 13
MB_DQS#[7:0] 13
MBA_A[13:0] 13,14
MB_RAS# 13,14
TP2
MB_WE# 13,14
A A
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
5
4
VSS_46
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
VSS
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
3
VSS_96
N35
M35
L35
J35
H35
G35
F35
D35
AN34
2
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
Date: Sheet
P53IA0
NB DDR_MEM SYSTEM-3/5
10 33Friday, September 22, 2006
1
of
C
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