FUJITSU Am29SL800D Service Manual

Am29SL800D

Data Sheet

The following document contains information on Spansion memory products. Although the document is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Fut ure routine revi sions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

Spansion continues to support existing part numbers beginning with “ Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 27546 Revision A Amendment 6 Issue Date January 23, 2007

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29SL800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory

DISTINCTIVE CHARACTERISTICS

 Single Power Supply Operation

— 1.65 to 2.2 V for read, program, and erase

operations

— Ideal for battery-powered applications

 Manufactured on 0.23 µm Process Technology

— Compatible with 0.32 µm Am29SL800C device

 High Performance

— Access times as fast as 90 ns

 Ultra Low Power Consumption (Typical Values at

5 MHz)

— 0.2 µA Automatic Sleep Mode current

— 0.2 µA standby mode current

— 5 mA read current

— 15 mA program/erase current

 Flexible Sector Architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection Features:

A hardware method of locking a sector to prevent any program or erase operations within that sector

Sectors can be locked in-system or via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectors

 Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

 Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

 Minimum 1,000,000 Erase Cycle Guarantee Per

Sector

 20-Year Data Retention at 125°C

 Package Option

— 48-pin TSOP

— 48-ball FBGA

 Compatibility with JEDEC Standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

 Data# Polling and Toggle Bits

— Provides a software method of detecting program

or erase operation completion

 Ready/Busy# Pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

 Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being erased, then resumes the erase operation

 Hardware Reset Pin (RESET#)

— Hardware method to reset the device to reading

array data

 Top or Bottom Boot Block Configurations

Available

This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 27546 Rev: A Amendment/6 Issue Date: January 23, 2007

DATA SHEET

GENERAL DESCRIPTION

The Am29SL800D is an 8 Mbit, 1.8 V volt-only Flashmemory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-pin TSOP and 48ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt V The device can also be programmed in standard EPROM programmers.

The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

supply. No V

is for write or erase operations.

During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low V

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

2 Am29SL800D 27546A6 January 23, 2007

DATA SHEET

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA Packages .................. 5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7

Standard Products .................................................................... 7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29SL800D Device Bus Operations ................................8

Word/Byte Configuration .......................................................... 8

Requirements for Reading Array Data ..................................... 8

Writing Commands/Command Sequences .............................. 8

Program and Erase Operation Status ...................................... 9

Standby Mode .......................................................................... 9

Automatic Sleep Mode ............................................................. 9

RESET#: Hardware Reset Pin ................................................. 9

Output Disable Mode .............................................................. 10

Table 2. Am29SL800DT Top Boot Block Sector Address Table .....10

Table 3. Am29SL800DB Bottom Boot Block Sector Address Table 11

Autoselect Mode ..................................................................... 12

Table 4. Am29SL800D Autoselect Code (High Voltage Method) ...12

Sector Protection/Unprotection ............................................... 12

Temporary Sector Unprotect ..................................................12

Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 13

Figure 2. Temporary Sector Unprotect Operation ........................... 14

Hardware Data Protection ......................................................14

Command Definitions . . . . . . . . . . . . . . . . . . . . . 14

Reading Array Data ................................................................ 14

Reset Command ..................................................................... 14

Autoselect Command Sequence ............................................ 15

Word/Byte Program Command Sequence .............................15

Figure 3. Program Operation .......................................................... 16

Chip Erase Command Sequence ........................................... 16

Sector Erase Command Sequence ........................................ 16

Erase Suspend/Erase Resume Commands ........................... 17

Figure 4. Erase Operation............................................................... 18

Table 5. Am29SL800D Command Definitions ................................19

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 20

DQ7: Data# Polling ................................................................. 20

Figure 5. Data# Polling Algorithm ................................................... 20

RY/BY#: Ready/Busy# ........................................................... 21

DQ6: Toggle Bit I .................................................................... 21

DQ2: Toggle Bit II ................................................................... 21

Reading Toggle Bits DQ6/DQ2 .............................................. 21

Figure 6. Toggle Bit Algorithm......................................................... 22

DQ5: Exceeded Timing Limits ................................................ 22

DQ3: Sector Erase Timer .......................................................22

Table 6. Write Operation Status ..................................................... 23

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24

Figure 7. Maximum Negative Overshoot Waveform ...................... 24

Figure 8. Maximum Positive Overshoot Waveform ........................ 24

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 24

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7. CMOS Compatible ........................................................... 25

Zero Power Flash ...................................................................26

Figure 9. I

Sleep Currents) .............................................................................. 26

Figure 10. Typical I

Current vs. Time (Showing Active and Automatic

CC1

vs. Frequency ........................................... 26

CC1

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11. Test Setup..................................................................... 27

Table 8. Test Specifications ........................................................... 27

Table 9. Key to Switching Waveforms ........................................... 27

Figure 12. Input Waveforms and Measurement Levels ................. 27

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 10. Read Operations ............................................................ 28

Figure 13. Read Operations Timings ............................................. 28

Table 11. Hardware Reset (RESET#) ............................................ 29

Figure 14. RESET# Timings .......................................................... 29

Table 12. Word/Byte Configuration (BYTE#) ................................. 30

Figure 15. BYTE# Timings for Read Operations............................ 30

Figure 16. BYTE# Timings for Write Operations ............................ 30

Table 13. Erase/Program Operations ............................................ 31

Figure 17. Program Operation Timings .......................................... 32

Figure 18. Chip/Sector Erase Operation Timings .......................... 33

Figure 19. Data# Polling Timings (During Embedded Algorithms). 34

Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 34

Figure 21. DQ2 vs. DQ6................................................................. 35

Table 14. Temporary Sector Unprotect .......................................... 35

Figure 22. Temporary Sector Unprotect Timing Diagram .............. 35

Figure 23. Sector Protect/Unprotect Timing Diagram .................... 36

Table 15. Alternate CE# Controlled Erase/Program Operations .... 37

Figure 24. Alternate CE# Controlled Write Operation Timings ...... 38

Erase and Programming Performance . . . . . . . 39

Table 16. Erase and Programming Performance ........................... 39

Table 17. Latchup Characteristics .................................................. 39

Table 18. TSOP Pin Capacitance .................................................. 39

Table 19. Data Retention ............................................................... 39

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40

TS 048—48-Pin Standard TSOP ............................................ 40

FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

8.15 X 6.15 mm Package .......................................................41

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

9 x 8 mm Package .................................................................. 42

VBK048—48 Ball Fine-Pitch Ball Grid Array (FBGA) .............43

8.15 x 6.15 mm ....................................................................... 43

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44

January 23, 2007 27546A6 Am29SL800D 3

DATA SHEET

PRODUCT SELECTOR GUIDE

Family Part Number Am29SL800D

Speed Options

Max access time, ns (t

Max CE# access time, ns (t

Max OE# access time, ns (t

)90 (Note 2) 100 120 150

ACC

)90 (Note 2) 100 120 150

) 30355065

Notes:

1. See “AC Characteristics” for full specifications.

min. = 1.7 V

2. V

BLOCK DIAGRAM

RY/BY#

RESET#

WE#

BYTE#

CE#

OE#

State

Control

Command

(Note 2) 100 120 150

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

DQ0–DQ15 (A-1)

Input/Output

STB

Buffers

Data

Latch

A0–A18

VCC Detector

Timer

STB

Y-Decoder

X-Decoder

Address Latch

Y-Gating

Cell Matrix

4 Am29SL800D 27546A6 January 23, 2007

CONNECTION DIAGRAMS

DATA SHEET

A15 A14 A13 A12 A11 A10

A8 NC NC

WE#

RESET#

NC NC

RY/BY#

A18 A17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Standard TSOP

48-Ball FBGA

(Top View, Balls Facing Down)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A16 BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE#

CE# A0

A6 B6 C6 D6 E6 F6 G6 H6

A5 B5 C5 D5 E5 F5 G5 H5

A4 B4 C4 D4 E4 F4 G4 H4

A3 B3 C3 D3 E3 F3 G3 H3

A2 B2 C2 D2 E2 F2 G2 H2

A1 B1 C1 D1 E1 F1 G1 H1

Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package

BYTE#A16A15A14A12A13

CE#A0A1A2A4A3

DQ15/A-1 V

DQ13 DQ6DQ14DQ7A11A10A8A9

DQ11 DQ3DQ10DQ2NCA18NCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# V

DQ4DQ12DQ5NCNCRESET#WE#

and/or data integrity may be compromised if the package body is exposed to temperatures about 150

°C

for prolonged periods of time.

January 23, 2007 27546A6 Am29SL800D 5

DATA SHEET

PIN CONFIGURATION

A0–A18 = 19 addresses

DQ0–DQ14 = 15 data inputs/outputs

DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

BYTE# = Selects 8-bit or 16-bit mode

CE# = Chip enable

OE# = Output enable

WE# = Write enable

RESET# = Hardware reset pin, active low

RY/BY# = Ready/Busy# output

= 1.65–2.2 V single power supply

NC = Pin not connected internally

= Device ground

LOGIC SYMBOL

A0–A18

CE#

OE#

WE#

RESET#

BYTE# RY/BY#

DQ0–DQ15

(A-1)

16 or 8

6 Am29SL800D 27546A6 January 23, 2007

DATA SHEET

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am29SL800D T -100 E C

TEMPERATURE RANGE

C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-free package I = Industrial (–40 F = Industrial (–40

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

VU = 48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80mm pitch, 8.15 x 6.15 mm package (VBK048)

WA = 48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8.15 x 6.15 mm package (FBA048)

WC = 48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 9 x 8 mm package (FBC048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +85°C) °C to +85°C) with Pb-free package

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29SL800D 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Valid Combinations for TSOP Packages

AM29SL800DT90, AM29SL800DB90

AM29SL800DT100, AM29SL800DB100

EC, EI, ED, EF

AM29SL800DT120, AM29SL800DB120

AM29SL800DT150, AM29SL800DB150

Valid Combinations for FBGA Packages

Order Number Package Marking

WAC, WAD

AM29SL800DT90, AM29SL800DB90

AM29SL800DT100, AM29SL800DB100

AM29SL800DT120, AM29SL800DB120

AM29SL800DT150, AM29SL800DB150

Am29SL800DT120 VUF

WAI, WAF

WCC, WCD,

WCI, WCF

WAC, WAD

WAI, WAF

WCC, WCD,

WCI, WCF

WAC, WAD

WAI, WAF

WCC, WCD,

WCI, WCF

WAC, WAD

WAI, WAF

WCC, WCD,

WCI, WCF

A800DT90U, A800DB90U

A800DT90P, A800DB90P

A800DT10U, A800DB10U

A800DT10P, A800DB10P

A800DT12U, A800DB12U

A800DT12P, A800DB12P

A800DT15U, A800DB15U

A800DT15P, A800DB15P

A800DT12V A800DB12V

C, I, D, F

January 23, 2007 27546A6 Am29SL800D 7

DATA SHEET

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data informa-

tion needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tabl e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Am29SL800D Device Bus Operations

DQ8–DQ15

Operation CE# OE# WE# RESET#

Read L L H H A

Write L H L H A

Standby

Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note) L H L V

Sector Unprotect (Note) L H L V

Temporary Sector Unprotect X X X V

0.2 V

Addresses

(Note 1)

X High-Z High-Z High-Z

Sector Address, A6 =

L, A1 = H,

A0 = L

Sector Address, A6 =

H, A1 = H,

A0 = L

DQ0–

DQ7

OUT

BYTE#

= V

OUT

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment.

BYTE#

= V

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-Z

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V

. The BYTE# pin determines

whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This

. CE# is the power

ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See Reading Array Data‚ on page 14 for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13, on page 28 for the timing diagram. I

in the DC Characteristics table

CC1

represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or

, and OE# to VIH.

8 Am29SL800D 27546A6 January 23, 2007

DATA SHEET

words. Refer to Word/Byte Configuration‚ on page 8 for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The

Word/Byte Program Command Sequence‚ on page 15

has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The Command Definitions‚ on

page 14 has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode‚ on page 12 and Autoselect Command Sequence‚ on page 15 sec- tions for more information.

in the DC Characteristics table represents the

CC2

active current specification for the write mode. AC

Characteristics‚ on page 28 contains timing specifica-

tion tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I

read specifications apply. Refer to Write Operation

Status‚ on page 20 for more information, and to “AC

Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V (Note that this is a more restricted voltage range than V

.) If CE# and RESET# are held at VIH, but not within

± 0.2 V, the device will be in the standby mode, but

the standby current will be greater. The device requires standard access time (t

) for read access when the

device is in either of these standby modes, before it is ready to read data.

± 0.2 V.

The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

in Table 7 on page 25 represents the standby

CC3

current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t

ACC

+ 50 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

in Ta b le 7 o n

CC4

page 25 represents the automatic sleep mode current

specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V draws CMOS standby current (I at V

but not within VSS±0.2 V, the standby current is

±0.2 V, the device

). If RESET# is held

CC4

greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t rithms). The system can read data t RESET# pin returns to V

(not during Embedded Algo-

READY

, the

after the

January 23, 2007 27546A6 Am29SL800D 9

DATA SHEET

Refer to the Table 10 on page 28 for RESET# parame- ters and to Figure 14, on page 29 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Table 2. Am29SL800DT Top Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A18 A17 A16 A15 A14 A13 A12

SA00000XXX 64/32 00000h–0FFFFh 00000h–07FFFh

SA10001XXX 64/32 10000h–1FFFFh 08000h–0FFFFh

SA20010XXX 64/32 20000h–2FFFFh 10000h–17FFFh

SA30011XXX 64/32 30000h–3FFFFh 18000h–1FFFFh

SA40100XXX 64/32 40000h–4FFFFh 20000h–27FFFh

SA50101XXX 64/32 50000h–5FFFFh 28000h–2FFFFh

SA60110XXX 64/32 60000h–6FFFFh 30000h–37FFFh

SA70111XXX 64/32 70000h–7FFFFh 38000h–3FFFFh

SA81000XXX 64/32 80000h–8FFFFh 40000h–47FFFh

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range

(x16)

SA91001XXX 64/32 90000h–9FFFFh 48000h–4FFFFh

SA101010XXX 64/32 A0000h–AFFFFh 50000h–57FFFh

SA111011XXX 64/32 B0000h–BFFFFh 58000h–5FFFFh

SA121100XXX 64/32 C0000h–CFFFFh 60000h–67FFFh

SA131101XXX 64/32 D0000h–DFFFFh 68000h–6FFFFh

SA141110XXX 64/32 E0000h–EFFFFh 70000h–77FFFh

SA1511110XX 32/16 F0000h–F7FFFh 78000h–7BFFFh

SA161111100 8/4 F8000h–F9FFFh 7C000h–7CFFFh

SA171111101 8/4 FA000h–FBFFFh7D000h–7DFFFh

SA18111111X 16/8 FC000h–FFFFFh 7E000h–7FFFFh

10 Am29SL800D 27546A6 January 23, 2007

DATA SHEET

Table 3. Am29SL800DB Bottom Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A18 A17 A16 A15 A14 A13 A12

SA0000000X 16/8 00000h–03FFFh 00000h–01FFFh

SA10000010 8/4 04000h–05FFFh 02000h–02FFFh

SA20000011 8/4 06000h–07FFFh 03000h–03FFFh

SA300001XX 32/16 08000h–0FFFFh 04000h–07FFFh

SA40001XXX 64/32 10000h–1FFFFh 08000h–0FFFFh

SA50010XXX 64/32 20000h–2FFFFh 10000h–17FFFh

SA60011XXX 64/32 30000h–3FFFFh 18000h–1FFFFh

SA70100XXX 64/32 40000h–4FFFFh 20000h–27FFFh

SA80101XXX 64/32 50000h–5FFFFh 28000h–2FFFFh

SA90110XXX 64/32 60000h–6FFFFh 30000h–37FFFh

SA100111XXX 64/32 70000h–7FFFFh 38000h–3FFFFh

SA111000XXX 64/32 80000h–8FFFFh 40000h–47FFFh

SA121001XXX 64/32 90000h–9FFFFh 48000h–4FFFFh

SA131010XXX 64/32 A0000h–AFFFFh 50000h–57FFFh

SA141011XXX 64/32 B0000h–BFFFFh 58000h–5FFFFh

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range

(x16)

SA151100XXX 64/32 C0000h–CFFFFh 60000h–67FFFh

SA161101XXX 64/32 D0000h–DFFFFh 68000h–6FFFFh

SA171110XXX 64/32 E0000h–EFFFFh 70000h–77FFFh

SA181111XXX 64/32 F0000h–FFFFFh 78000h–7FFFFh

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.

January 23, 2007 27546A6 Am29SL800D 11

DATA SHEET

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector

Description Mode CE# OE# WE#

Manufacturer ID: AMD L L H X X V

Device ID:

Am29SL800D

(Top Boot Block)

Device ID:

Am29SL800D

(Bottom Boot Block)

Sector Protection Verification L L H SA X V

Table 4. Am29SL800D Autoselect Code (High Voltage Method)

A11

A18

A10 A9

A12

Word L L H

Byte L L H X EAh

Word L L H

Byte L L H X 6Bh

XXV

address must appear on the appropriate highest order address bits (see Table 2 on page 10 and Tab le 3 on

page 11). Ta bl e 4 shows the remaining address bits

that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5 on page 19. This method does not require VID. See Command

Definitions‚ on page 14 for details on using the autose-

lect mode.

A7 A6

X L X L L X 01h

XLXLH

XLXHL

A2 A1 A0

DQ8

DQ15

22h EAh

22h 6Bh

X 01h (protected)

DQ7

DQ0

00h

(unprotected)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected

through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode‚ on page 12 for details.

sectors. Sector protection/unprotection can be implemented via two methods.

Sector Protection/ Unprotection requires V

on the

RESET# pin only, and can be implemented either insystem or via programming equipment. Figure 1, on

page 13 shows the algorithms and Figure 23, on page 36 shows the timing diagram. For sector unprotect, all

unprotected sectors must first be protected prior to the first sector unprotect write cycle.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V tected sectors can be programmed or erased by selecting the sector addresses. Once V from the RESET# pin, all the previously protected sectors are protected again. Figure 2, on page 14

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting

shows the algorithm, and Figure 22, on page 35 shows the timing diagrams, for this feature.

sectors at its factory prior to shipping the device

. During this mode, formerly pro-

is removed

12 Am29SL800D 27546A6 January 23, 2007

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