FUJITSU Am29SL800D Service Manual

Am29SL800D

Data Sheet

The following document contains information on Spansion memory products. Although the document is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 27546 Revision A Amendment 6 Issue Date January 23, 2007

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29SL800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 1.8 Volt-only Super Low Voltage Flash Memory

DISTINCTIVE CHARACTERISTICS

Single Power Supply Operation

—1.65 to 2.2 V for read, program, and erase operations

—Ideal for battery-powered applications

Manufactured on 0.23 µm Process Technology

—Compatible with 0.32 µm Am29SL800C device

High Performance

—Access times as fast as 90 ns

Ultra Low Power Consumption (Typical Values at 5 MHz)

—0.2 µA Automatic Sleep Mode current

—0.2 µA standby mode current

—5 mA read current

—15 mA program/erase current

Flexible Sector Architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode)

—One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode)

—Supports full chip erase

—Sector Protection Features:

A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectors

Unlock Bypass Program Command

—Reduces overall programming time when issuing multiple program command sequences

Top or Bottom Boot Block Configurations Available

Embedded Algorithms

—Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors

—Embedded Program algorithm automatically writes and verifies data at specified addresses

Minimum 1,000,000 Erase Cycle Guarantee Per Sector

20-Year Data Retention at 125°C

Package Option

—48-pin TSOP

—48-ball FBGA

Compatibility with JEDEC Standards

—Pinout and software compatible with singlepower supply Flash

—Superior inadvertent write protection

Data# Polling and Toggle Bits

—Provides a software method of detecting program or erase operation completion

Ready/Busy# Pin (RY/BY#)

—Provides a hardware method of detecting program or erase cycle completion

Erase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation

Hardware Reset Pin (RESET#)

—Hardware method to reset the device to reading array data

	This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may	Publication# 27546 Rev: A Amendment/6
		Issue Date: January 23, 2007
	be revised by subsequent versions or modifications due to changes in technical specifications.	Issue Date: January 23, 2007

D A T A S H E E T

GENERAL DESCRIPTION

The Am29SL800D is an 8 Mbit, 1.8 V volt-only Flashmemory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-pin TSOP and 48ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt VCC supply. No VPP is for write or erase operations. The device can also be programmed in standard EPROM programmers.

The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation.

During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

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D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA Packages ..................	5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
Ordering Information . . . . . . . . . . . . . . . . . . . . . .	. 7
Standard Products ....................................................................	7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .	8
Table 1. Am29SL800D Device Bus Operations ................................	8
Word/Byte Configuration ..........................................................	8
Requirements for Reading Array Data .....................................	8
Writing Commands/Command Sequences ..............................	8
Program and Erase Operation Status ......................................	9
Standby Mode ..........................................................................	9
Automatic Sleep Mode .............................................................	9
RESET#: Hardware Reset Pin .................................................	9
Output Disable Mode ..............................................................	10
Table 2. Am29SL800DT Top Boot Block Sector Address Table .....	10
Table 3. Am29SL800DB Bottom Boot Block Sector Address Table 11
Autoselect Mode .....................................................................	12
Table 4. Am29SL800D Autoselect Code (High Voltage Method) ...	12
Sector Protection/Unprotection ...............................................	12
Temporary Sector Unprotect ..................................................	12
Figure 1. In-System Sector Protect/Unprotect Algorithms ..............	13
Figure 2. Temporary Sector Unprotect Operation...........................	14
Hardware Data Protection ......................................................	14
Command Definitions . . . . . . . . . . . . . . . . . . . . .	14
Reading Array Data ................................................................	14
Reset Command .....................................................................	14
Autoselect Command Sequence ............................................	15
Word/Byte Program Command Sequence .............................	15
Figure 3. Program Operation ..........................................................	16
Chip Erase Command Sequence ...........................................	16
Sector Erase Command Sequence ........................................	16
Erase Suspend/Erase Resume Commands ...........................	17
Figure 4. Erase Operation...............................................................	18
Table 5. Am29SL800D Command Definitions ................................	19
Write Operation Status . . . . . . . . . . . . . . . . . . . . .	20
DQ7: Data# Polling .................................................................	20
Figure 5. Data# Polling Algorithm ...................................................	20
RY/BY#: Ready/Busy# ...........................................................	21
DQ6: Toggle Bit I ....................................................................	21
DQ2: Toggle Bit II ...................................................................	21
Reading Toggle Bits DQ6/DQ2 ..............................................	21
Figure 6. Toggle Bit Algorithm.........................................................	22
DQ5: Exceeded Timing Limits ................................................	22
DQ3: Sector Erase Timer .......................................................	22

Table 6. Write Operation Status .....................................................	23
Absolute Maximum Ratings . . . . . . . . . . . . . . . .	24
Figure 7. Maximum Negative Overshoot Waveform ......................	24
Figure 8. Maximum Positive Overshoot Waveform........................	24
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . .	24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .	25
Table 7. CMOS Compatible ...........................................................	25
Zero Power Flash ...................................................................	26
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents) ..............................................................................	26
Figure 10. Typical ICC1 vs. Frequency ...........................................	26
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 11. Test Setup.....................................................................	27
Table 8. Test Specifications ...........................................................	27
Table 9. Key to Switching Waveforms ...........................................	27
Figure 12. Input Waveforms and Measurement Levels .................	27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .	28
Table 10. Read Operations ............................................................	28
Figure 13. Read Operations Timings .............................................	28
Table 11. Hardware Reset (RESET#) ............................................	29
Figure 14. RESET# Timings ..........................................................	29
Table 12. Word/Byte Configuration (BYTE#) .................................	30
Figure 15. BYTE# Timings for Read Operations............................	30
Figure 16. BYTE# Timings for Write Operations............................	30
Table 13. Erase/Program Operations ............................................	31
Figure 17. Program Operation Timings..........................................	32
Figure 18. Chip/Sector Erase Operation Timings ..........................	33
Figure 19. Data# Polling Timings (During Embedded Algorithms). 34
Figure 20. Toggle Bit Timings (During Embedded Algorithms)......	34
Figure 21. DQ2 vs. DQ6.................................................................	35
Table 14. Temporary Sector Unprotect ..........................................	35
Figure 22. Temporary Sector Unprotect Timing Diagram ..............	35
Figure 23. Sector Protect/Unprotect Timing Diagram ....................	36
Table 15. Alternate CE# Controlled Erase/Program Operations ....	37
Figure 24. Alternate CE# Controlled Write Operation Timings ......	38
Erase and Programming Performance . . . . . . .	39
Table 16. Erase and Programming Performance ...........................	39
Table 17. Latchup Characteristics ..................................................	39
Table 18. TSOP Pin Capacitance ..................................................	39
Table 19. Data Retention ...............................................................	39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . .	40
TS 048—48-Pin Standard TSOP ............................................	40
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 X 6.15 mm Package .......................................................	41
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
9 x 8 mm Package ..................................................................	42
VBK048—48 Ball Fine-Pitch Ball Grid Array (FBGA) .............	43
8.15 x 6.15 mm .......................................................................	43

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44

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Am29SL800D

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Family Part Number			Am29SL800D

Speed Options	90
Speed Options	(Note 2)	100		120	150
	(Note 2)	100		120	150

Max access time, ns (tACC)	90 (Note 2)	100		120	150

Max CE# access time, ns (tCE)	90 (Note 2)	100		120	150

Max OE# access time, ns (tOE)	30	35		50	65

Notes:

1.See “AC Characteristics” for full specifications.

2.VCC min. = 1.7 V

BLOCK DIAGRAM

	RY/BY#					DQ0–DQ15 (A-1)
	RY/BY#
VCC			Sector Switches
VSS			Sector Switches
VSS
RESET#			Erase Voltage			Input/Output
RESET#			Generator			Buffers
WE#	State
BYTE#	Control
BYTE#
	Command
	Register
		PGM Voltage
		Generator
			Chip Enable			Data
			Chip Enable		STB	Latch
CE#			Output Enable		STB	Latch
CE#				Logic
OE#				Logic
OE#
			STB	Y-Decoder		Y-Gating
			STB
	VCC Detector	Timer	Latch
			Latch
			Address	X-Decoder		Cell Matrix
A0–A18			Address
A0–A18

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27546A6 January 23, 2007

D A T A S H E E T

CONNECTION DIAGRAMS

A15	1		48	A16


A14	2		47	BYTE#


A13	3		46	VSS


A12	4		45	DQ15/A-1


A11	5		44	DQ7


A10	6		43	DQ14


A9	7		42	DQ6


A8	8		41	DQ13


NC	9		40	DQ5


NC	10		39	DQ12


WE#	11	Standard TSOP	38	DQ4


RESET#	12		37	VCC

NC	13		36	DQ11


NC	14		35	DQ3


RY/BY#	15		34	DQ10


A18	16		33	DQ2


A17	17		32	DQ9


A7	18		31	DQ1


A6	19		30	DQ8


A5	20		29	DQ0


A4	21		28	OE#


A3	22		27	VSS


A2	23		26	CE#


A1	24		25	A0

48-Ball FBGA

(Top View, Balls Facing Down)

A6	B6	C6	D6	E6	F6	G6	H6
A13	A12	A14	A15	A16	BYTE#	DQ15/A-1	VSS
A5	B5	C5	D5	E5	F5	G5	H5
A9	A8	A10	A11	DQ7	DQ14	DQ13	DQ6
A4	B4	C4	D4	E4	F4	G4	H4
WE#	RESET#	NC	NC	DQ5	DQ12	VCC	DQ4
A3	B3	C3	D3	E3	F3	G3	H3
RY/BY#	NC	A18	NC	DQ2	DQ10	DQ11	DQ3
A2	B2	C2	D2	E2	F2	G2	H2
A7	A17	A6	A5	DQ0	DQ8	DQ9	DQ1
A1	B1	C1	D1	E1	F1	G1	H1
A3	A4	A2	A1	A0	CE#	OE#	VSS

Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package

and/or data integrity may be compromised if the package body is exposed to temperatures about 150°C for prolonged periods of time.

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Am29SL800D

BYTE#

CE#

OE#

WE#

RESET#

RY/BY# VCC VSS

D A T A S H E E T

PIN CONFIGURATION

A0–A18 = 19 addresses

DQ0–DQ14 = 15 data inputs/outputs

DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)

= Selects 8-bit or 16-bit mode = Chip enable

= Output enable = Write enable

= Hardware reset pin, active low = Ready/Busy# output

= 1.65–2.2 V single power supply = Device ground

= Pin not connected internally

LOGIC SYMBOL

19	A0–A18		16 or 8
19

		DQ0–DQ15


	CE#	(A-1)
		(A-1)


	OE#
	OE#
	WE#
	WE#
	RESET#
	RESET#
	BYTE#	RY/BY#
	BYTE#	RY/BY#

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D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am29SL800D T -100 E C

TEMPERATURE RANGE

C= Commercial (0°C to +70°C)

D= Commercial (0°C to +70°C) with Pb-free package

I	=	Industrial (–40°C to +85°C)
F	=	Industrial (–40°C to +85°C) with Pb-free package

PACKAGE TYPE

E= 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

VU	= 48-ball Fine-Pitch Ball Grid Array (FBGA)
	0.80mm pitch, 8.15 x 6.15 mm package (VBK048)
WA	= 48-Ball Fine-Pitch Ball Grid Array (FBGA)
	0.80 mm pitch, 8.15 x 6.15 mm package (FBA048)
WC	= 48-Ball Fine-Pitch Ball Grid Array (FBGA)
	0.80 mm pitch, 9 x 8 mm package (FBC048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T	=	Top Sector
B	=	Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29SL800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Valid Combinations for TSOP Packages

AM29SL800DT90,

AM29SL800DB90

AM29SL800DT100,

AM29SL800DB100

EC, EI, ED, EF

AM29SL800DT120,

AM29SL800DB120

AM29SL800DT150,

AM29SL800DB150

Valid Combinations for FBGA Packages

Order Number		Package Marking

	WAC, WAD	A800DT90U,
AM29SL800DT90,	WAI, WAF	A800DB90U
AM29SL800DT90,
AM29SL800DB90	WCC, WCD,	A800DT90P,
	WCC, WCD,	A800DT90P,
	WCI, WCF	A800DB90P

	WAC, WAD	A800DT10U,
AM29SL800DT100,	WAI, WAF	A800DB10U
AM29SL800DT100,
AM29SL800DB100	WCC, WCD,	A800DT10P,
	WCC, WCD,	A800DT10P,
	WCI, WCF	A800DB10P

	WAC, WAD	A800DT12U,	C, I,
AM29SL800DT120,	WAI, WAF	A800DB12U	D, F
AM29SL800DT120,
AM29SL800DB120	WCC, WCD,	A800DT12P,
	WCC, WCD,	A800DT12P,
	WCI, WCF	A800DB12P

	WAC, WAD	A800DT15U,
AM29SL800DT150,	WAI, WAF	A800DB15U
AM29SL800DT150,
AM29SL800DB150	WCC, WCD,	A800DT15P,
	WCC, WCD,	A800DT15P,
	WCI, WCF	A800DB15P

Am29SL800DT120	VUF	A800DT12V
Am29SL800DT120	VUF	A800DB12V
		A800DB12V

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D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data informa-

tion needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Am29SL800D Device Bus Operations

								DQ8–DQ15

					Addresses	DQ0–	BYTE#	BYTE#
Operation	CE#	OE#	WE#	RESET#	(Note 1)	DQ7	= VIH	= VIL
Read	L	L	H	H	AIN	DOUT	DOUT	DQ8–DQ14 = High-Z,
Write	L	H	L	H	AIN	DIN	DIN	DQ15 = A-1
Write	L	H	L	H	AIN	DIN	DIN
Standby	VCC ±	X	X	VCC ±	X	High-Z	High-Z	High-Z
	0.2 V			0.2 V
Output Disable	L	H	H	H	X	High-Z	High-Z	High-Z

Reset	X	X	X	L	X	High-Z	High-Z	High-Z

					Sector Address, A6 =
Sector Protect (Note)	L	H	L	VID	L, A1 = H,	DIN	X	X
					A0 = L

					Sector Address, A6 =
Sector Unprotect (Note)	L	H	L	VID	H, A1 = H,	DIN	X	X
					A0 = L

Temporary Sector Unprotect	X	X	X	VID	AIN	DIN	DIN	High-Z

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1.Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).

2.The sector protect and sector unprotect functions may also be implemented via programming equipment.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See Reading Array Data‚ on page 14 for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13, on page 28 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or

Am29SL800D

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D A T A S H E E T

words. Refer to Word/Byte Configuration‚ on page 8 for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The

Word/Byte Program Command Sequence‚ on page 15 has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The Command Definitions‚ on page 14 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode‚ on page 12 and Autoselect Command Sequence‚ on page 15 sections for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. AC Characteristics‚ on page 28 contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status‚ on page 20 for more information, and to “AC Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.2 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.2 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

ICC3 in Table 7 on page 25 represents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 50 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in Table 7 on page 25 represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.2 V, the standby current is greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the

RESET# pin returns to VIH.

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Refer to the Table 10 on page 28 for RESET# parameters and to Figure 14, on page 29 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Table 2. Am29SL800DT Top Boot Block Sector Address Table

								Sector Size	Address Range (in hexadecimal)
								Sector Size
								(Kbytes/	(x8)	(x16)
Sector	A18	A17	A16	A15	A14	A13	A12	Kwords)	Address Range	Address Range

SA0	0	0	0	0	X	X	X	64/32	00000h–0FFFFh	00000h–07FFFh

SA1	0	0	0	1	X	X	X	64/32	10000h–1FFFFh	08000h–0FFFFh

SA2	0	0	1	0	X	X	X	64/32	20000h–2FFFFh	10000h–17FFFh

SA3	0	0	1	1	X	X	X	64/32	30000h–3FFFFh	18000h–1FFFFh

SA4	0	1	0	0	X	X	X	64/32	40000h–4FFFFh	20000h–27FFFh

SA5	0	1	0	1	X	X	X	64/32	50000h–5FFFFh	28000h–2FFFFh

SA6	0	1	1	0	X	X	X	64/32	60000h–6FFFFh	30000h–37FFFh

SA7	0	1	1	1	X	X	X	64/32	70000h–7FFFFh	38000h–3FFFFh

SA8	1	0	0	0	X	X	X	64/32	80000h–8FFFFh	40000h–47FFFh

SA9	1	0	0	1	X	X	X	64/32	90000h–9FFFFh	48000h–4FFFFh

SA10	1	0	1	0	X	X	X	64/32	A0000h–AFFFFh	50000h–57FFFh

SA11	1	0	1	1	X	X	X	64/32	B0000h–BFFFFh	58000h–5FFFFh

SA12	1	1	0	0	X	X	X	64/32	C0000h–CFFFFh	60000h–67FFFh

SA13	1	1	0	1	X	X	X	64/32	D0000h–DFFFFh	68000h–6FFFFh

SA14	1	1	1	0	X	X	X	64/32	E0000h–EFFFFh	70000h–77FFFh

SA15	1	1	1	1	0	X	X	32/16	F0000h–F7FFFh	78000h–7BFFFh

SA16	1	1	1	1	1	0	0	8/4	F8000h–F9FFFh	7C000h–7CFFFh

SA17	1	1	1	1	1	0	1	8/4	FA000h–FBFFFh	7D000h–7DFFFh

SA18	1	1	1	1	1	1	X	16/8	FC000h–FFFFFh	7E000h–7FFFFh

Am29SL800D

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D A T A

S H E E T

Table 3. Am29SL800DB Bottom Boot Block Sector Address Table

Sector Size

Address Range (in hexadecimal)

(Kbytes/

(x8)

(x16)

Sector

A18

A17

A16

A15

A14

A13

A12

Kwords)

Address Range

SA0

16/8

00000h–03FFFh

00000h–01FFFh

SA1

8/4

04000h–05FFFh

02000h–02FFFh

SA2

8/4

06000h–07FFFh

03000h–03FFFh

SA3

32/16

08000h–0FFFFh

04000h–07FFFh

SA4

64/32

10000h–1FFFFh

08000h–0FFFFh

SA5

64/32

20000h–2FFFFh

10000h–17FFFh

SA6

64/32

30000h–3FFFFh

18000h–1FFFFh

SA7

64/32

40000h–4FFFFh

20000h–27FFFh

SA8

64/32

50000h–5FFFFh

28000h–2FFFFh

SA9

64/32

60000h–6FFFFh

30000h–37FFFh

SA10

64/32

70000h–7FFFFh

38000h–3FFFFh

SA11

64/32

80000h–8FFFFh

40000h–47FFFh

SA12

64/32

90000h–9FFFFh

48000h–4FFFFh

SA13

64/32

A0000h–AFFFFh

50000h–57FFFh

SA14

64/32

B0000h–BFFFFh

58000h–5FFFFh

SA15

64/32

C0000h–CFFFFh

60000h–67FFFh

SA16

64/32

D0000h–DFFFFh

68000h–6FFFFh

SA17

64/32

E0000h–EFFFFh

70000h–77FFFh

SA18

64/32

F0000h–FFFFFh

78000h–7FFFFh

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.

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Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector

address must appear on the appropriate highest order address bits (see Table 2 on page 10 and Table 3 on page 11). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5 on page 19. This method does not require VID. See Command Definitions‚ on page 14 for details on using the autoselect mode.

Table 4. Am29SL800D Autoselect Code (High Voltage Method)

A18

A11

DQ8

DQ7

Description

Mode

CE#

OE#

WE#

A12

A10

DQ15

DQ0

Manufacturer ID: AMD

VID

01h

Device ID:

Word

22h

EAh

Am29SL800D

VID

Byte

EAh

(Top Boot Block)

Device ID:

Word

22h

6Bh

Am29SL800D

VID

Byte

6Bh

(Bottom Boot Block)

01h (protected)

Sector Protection Verification

VID

00h

(unprotected)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods.

Sector Protection/ Unprotection requires VID on the RESET# pin only, and can be implemented either insystem or via programming equipment. Figure 1, on page 13 shows the algorithms and Figure 23, on page 36 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode‚ on page 12 for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2, on page 14 shows the algorithm, and Figure 22, on page 35 shows the timing diagrams, for this feature.

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27546A6 January 23, 2007

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