FUJITSU Am29LV128MH-L Service Manual

查询AM29LV128MH103REI供应商

Am29LV128MH/L

Data Sheet

July 2003

The following document specifie s Spansion me mory prod ucts that are no w offere d by both Adv anced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig­inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Futu re routine revisions wi ll occur when appropriate,
and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support exi sting part numbers beg inning with “ Am” an d “MBM”. T o orde r
these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about S pansion
memory solutions.

Publication Number 25270 Revision C Amendment +2 Issue Date September 9, 2003

THIS PAGE LEFT INTENTIONALLY BLANK.

DATASHEET

Am29LV128MH/L

128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit™ 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O

DISTINCTIVE CHARACTERISTICS

™ Control

ARCHITECTURAL ADVANTAGES

■ Single power supply operation

— 3 volt read, erase, and program operations

■ VersatileI/O

— Device generates data output voltages and tolerates

data input voltages on the CE# and DQ
inputs/outputs as determined by the voltage on the
V

■ Manufactured on 0.23 µm MirrorBit process

technology

■ SecSi

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence

— May be programmed and locked at the factory or by

the customer

■ Flexible sector architecture

— Two hundred fifty-six 32 Kword (64 Kbyte) sectors

■ Compatibility with JEDEC standards

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent
write protection

■ Minimum 100,000 erase cycle guarantee per sector

■ 20-year data retention at 125

PERFORMANCE CHARACTERISTICS

■ High performance

— 90 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 15 s typical effective write buffer word programming

time: 16-word/32-byte write buffer reduces overall
programming time for multiple-word updates

™ control

pin; operates from 1.65 to 3.6 V

IO

™ (Secured Silicon) Sector region

°C

— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer

■ Low power consumption (typical values at 3.0 V, 5

MHz)

— 13 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current

■ Package options

— 56-pin TSOP
— 64-ball Fortified BGA

SOFTWARE & HARDWARE FEATURES

■ Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall

multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

■ Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group
— Temporary Sector Group Unprotect: V

of changing code in locked sector groups

— WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

-level method

ID

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 25270 Rev: C Amendment/2
Issue Date: September 9, 2003

DATASHEET

GENERAL DESCRIPTION

The Am29LV128MH/L is a 128 Mbit, 3.0 volt single
power supply flash memory devices organized as
8,388,608 words or 16,777,216 bytes. The device has
a 16-bit wide data bus that can also function as an
8-bit wide data bus by using the BYTE# input. The de­vice can be programmed either in the host system or
in standard EPROM programmers.

An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
specified in the Product Selector Guide and the Order­ing Information sections. The device is offered in a
56-pin TSOP, 64-ball Fortified BGA. Each device has
separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.

Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to

input, a high-voltage accelerated program

a V

CC

(WP#/ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.

The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter­nally latch addresses and data needed for the pro­gramming and erase operations.

The sector erase architecture allows memory sec­tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.

Device programming and erasure are initiated through
command sequences. Once a program or erase oper­ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter­mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.

The VersatileI/O™ (V
tem to set the voltage levels that the device generates

) and an I/O voltage range (VIO), as

CC

) control allows the host sys-

IO

and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V
Refer to the Ordering Information section for valid V

IO

pin.

IO

options.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V

CC

tions during power transitions. The hardware sector
group protection feature disables both program and
erase operations in any combination of sector groups
of memory. This can be achieved in-system or via pro­gramming equipment.

The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The Program Sus-
pend/Program Resume feature enables the host sys­tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.

The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.

The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.

The SecSi

™ (Secured Silicon) Sector provides a

128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.

The Write Protect (WP#/ACC) feature protects the
first or last sector by asserting a logic low on the WP#
pin.

AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec­tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.

RELATED DOCUMENTS

For a comprehensive information on MirrorBit prod­ucts, including migration information, data sheets, ap­plication notes, and software drivers, please see
www.amd.com

→MirrorBit→Flash Information→Technical Docu-

tion

→Flash Memory→Product Informa-

mentation. The following is a partial list of documents
closely related to this product:

2 Am29LV128MH/L September 9, 2003

MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read

Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs

Am29LV256M, 256 Mbit MirrorBit Flash device
(in 64-ball, 18 x 12 mm Fortified BGA package)

DATASHEET

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations ....................................................... 9

Word/Byte Configuration .......................................................... 9

™

VersatileIO

Requirements for Reading Array Data ...................................10

Page Mode Read ............................................................................10

Writing Commands/Command Sequences ............................10

Write Buffer .....................................................................................10

Accelerated Program Operation ......................................................10

Autoselect Functions .......................................................................10

Standby Mode ........................................................................ 10

Automatic Sleep Mode ...........................................................11

RESET#: Hardware Reset Pin ............................................... 11

Output Disable Mode ..............................................................11

Table 2. Sector Address Table........................................................ 12

Autoselect Mode ..................................................................... 18

Table 3. Autoselect Codes, (High Voltage Method) ....................... 18

Sector Group Protection and Unprotection .............................19

Table 4. Sector Group Protection/Unprotection Address Table ..... 19

Write Protect (WP#) ................................................................ 20

Temporary Sector Group Unprotect ....................................... 20

Figure 1. Temporary Sector Group Unprotect Operation ................20

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...21

SecSi (Secured Silicon) Sector Flash Memory Region .......... 22

Table 5. SecSi Sector Contents ...................................................... 22

Figure 3. SecSi Sector Protect Verify ..............................................23

Hardware Data Protection ...................................................... 23

Low VCC Write Inhibit .....................................................................23

Write Pulse “Glitch” Protection ........................................................23

Logical Inhibit ..................................................................................23

Power-Up Write Inhibit ....................................................................23

Common Flash Memory Interface (CFI). . . . . . . 23

Table 6. CFI Query Identification String ..........................................24

Table 7. System Interface String..................................................... 24

Table 8. Device Geometry Definition ..............................................25

Table 9. Primary Vendor-Specific Extended Query ........................26

Command Definitions . . . . . . . . . . . . . . . . . . . . . 27

Reading Array Data ................................................................ 27

Reset Command ..................................................................... 27

Autoselect Command Sequence ............................................ 27

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 28

Word/Byte Program Command Sequence ............................. 28

Unlock Bypass Command Sequence ..............................................28

Write Buffer Programming ...............................................................28

Accelerated Program ......................................................................29

Figure 4. Write Buffer Programming Operation ...............................30

Figure 5. Program Operation ..........................................................31

Program Suspend/Program Resume Command Sequence ... 31

Figure 6. Program Suspend/Program Resume ...............................32

Chip Erase Command Sequence ........................................... 32

Sector Erase Command Sequence ........................................ 32

Figure 7. Erase Operation ...............................................................33

(VIO) Control ....................................................... 9

Erase Suspend/Erase Resume Commands ........................... 33

Command Definitions ............................................................. 34

Table 10. Command Definitions (x16 Mode, BYTE# = VIH) ........... 34

Table 11. Command Definitions (x8 Mode, BYTE# = V

).............. 35

IL

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 36

DQ7: Data# Polling ................................................................. 36

Figure 8. Data# Polling Algorithm .................................................. 36

RY/BY#: Ready/Busy# ............................................................ 37

DQ6: Toggle Bit I .................................................................... 37

Figure 9. Toggle Bit Algorithm ........................................................ 38

DQ2: Toggle Bit II ................................................................... 38

Reading Toggle Bits DQ6/DQ2 ............................................... 38

DQ5: Exceeded Timing Limits ................................................39

DQ3: Sector Erase Timer ....................................................... 39

DQ1: Write-to-Buffer Abort ..................................................... 39

Table 12. Write Operation Status................................................... 40

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 41

Figure 10. Maximum Negative Overshoot Waveform ................... 41

Figure 11. Maximum Positive Overshoot Waveform ..................... 41

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 41

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 12. Test Setup .................................................................... 43

Table 13. Test Specifications......................................................... 43

Key to Switching Waveforms. . . . . . . . . . . . . . . . 43

Figure 13. Input Waveforms and Measurement Levels ................. 43

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44

Read-Only Operations ........................................................... 44

Figure 14. Read Operation Timings ............................................... 44

Figure 15. Page Read Timings ...................................................... 45

Hardware Reset (RESET#) .................................................... 46

Figure 16. Reset Timings ............................................................... 46

Erase and Program Operations .............................................. 47

Figure 17. Reset Timings ............................................................... 48

Figure 18. Program Operation Timings .......................................... 49

Figure 19. Accelerated Program Timing Diagram .......................... 49

Figure 20. Chip/Sector Erase Operation Timings .......................... 50

Figure 21. Data# Polling Timings (During Embedded Algorithms) . 51

Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... 52

Figure 23. DQ2 vs. DQ6 ................................................................. 52

Temporary Sector Group Unprotect ....................................... 53

Figure 24. Temporary Sector Group Unprotect Timing Diagram ... 53
Figure 25. Sector Group Protect and Unprotect Timing Diagram .. 54

Alternate CE# Controlled Erase and Program Operations ..... 55

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings .......................................................................... 56

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 56

Erase And Programming Performance. . . . . . . . 57

TSOP Pin and BGA Package Capacitance . . . . . 58

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 59

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline

Package (TSOP) ..................................................................... 59

LAA064—64-Ball Fortified Ball Grid Array

13 x 11 mm Package .............................................................. 60

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61

September 9, 2003 Am29LV128MH/L 3

PRODUCT SELECTOR GUIDE

Part Number Am29LV128MH/L

Regulated Voltage Range

= 3.0–3.6 V

V

Speed/
Voltage
Option

Max. Access Time (ns)

CC

Full Voltage Range
V

= 2.7–3.6 V

CC

DATASHEET

93R

= 3.0–3.6 V

V

IO

90

103R

VIO = 2.7–3.6 V

(Note 2)

= 2.7–3.6 V

V

IO

113R

VIO = 1.65–3.6 V

103

100 110 120

113

(Note 2)

VIO = 1.65–3.6 V

123R

VIO = 1.65–3.6 V

123

(Note 2)

VIO = 1.65–3.6 V

Max. CE# Access Time (ns)

Max. Page access time (t

Max. OE# Access Time (ns)

Notes:

1. See “AC Characteristics” for full specifications.

PAC C

)

90

25

25

2. Contact factory for availability and ordering information.

BLOCK DIAGRAM

RY/ BY#

V

CC

V

SS

RESET#

WE#

WP#/ACC

BYTE#

CE#

OE#

State

Control

Command

Register

PGM Voltage

Generator

100 110 120

30 30 40 30 40

30 30 40 30 40

DQ0

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

V

IO

STB

Logic

–

DQ15 (A-1)

Input/Output

Buffers

Data

Latch

A22–A0

VCC Detector

Timer

STB

Y-Decoder

X-Decoder

Address Latch

Y-Gating

Cell Matrix

4 Am29LV128MH/L September 9, 2003

CONNECTION DIAGRAMS

1

NC

2

A22

3

A15

4

A14

5

A13

6

A12

7

A11

8

A10

9

A9

10

A8

11

A19

12

A20

13

WE#

A21

A18
A17

A7
A6
A5
A4
A3
A2

A1
NC
NC

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

RESET#

WP#/ACC

RY/BY#

DATASHEET

56-Pin Standard TSOP

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

NC
NC
A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V

SS

CE#
A0
NC
V

IO

NC
NC

A16

BYTE#

V

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2
DQ9
DQ1
DQ8
DQ0

OE#

V

CE#

A0
NC
V

SS

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14

56-Pin Reverse TSOP

15
16
17
18
19
20
21
22
23
24
25
26
27
28

IO

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

NC
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC

September 9, 2003 Am29LV128MH/L 5

CONNECTION DIAGRAMS

DATASHEET

64- Ball Fortified BGA

Top View, Balls Facing Down

A8 C8

A7 C7 D7 E7 F7 G7 H7

A6 C6 D6 E6 F6 G6 H6

A5 C5 D5 E5 F5 G5 H5

A4 C4 D4 E4 F4 G4 H4

A3 C3 D3 E3 F3 G3 H3

A2 C2 D2 E2 F2 G2 H2

A1 C1 D1 E1 F1 G1 H1

B8 D8 E8 F8 G8 H8

NC

V

V

NC

B7

B6

B5

B4

B3

B2

B1

NCA22NC

V

IO

SS

NCNCNCNCNC

NCV

V

IO

NC

DQ15/A-1

DQ13 DQ6DQ14DQ7A11A10A8A9

V

CC DQ4DQ12DQ5A19A21RESET#WE#

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE#

NC

SSBYTE#A16A15A14A12A13

SSCE#A0A1A2A4A3

Special Package Handling Instructions

package body is exposed to temperatures above

°C for prolonged periods of time.

150
Special handling is required for Flash Memory products
in molded packages (TSOP and BGA). The package
and/or data integrity may be compromised if the

6 Am29LV128MH/L September 9, 2003

DATASHEET

PIN DESCRIPTION

A22–A0 = 23 Address inputs

DQ14–DQ0 = 15 Data inputs/outputs

DQ15/A-1 = DQ15 (Data input/output, word mode),

A-1 (LSB Address input, byte mode)

CE# = Chip Enable input

OE# = Output Enable input

WE# = Write Enable input

WP#/ACC = Hardware Write Protect input;

Acceleration input

RESET# = Hardware Reset Pin input

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Ready/Busy output

= 3.0 volt-only single power supply

V

CC

= Output Buffer power

V

IO

V

SS

NC = Pin Not Connected Internally

(see Product Selector Guide for
speed options and voltage
supply tolerances)

= Device Ground

LOGIC SYMBOL

23

A22–A0

CE#

OE#

WE#

WP#/ACC

RESET#

V

IO

BYTE#

16 or 8

DQ15–DQ0

(A-1)

RY/BY#

September 9, 2003 Am29LV128MH/L 7

DATASHEET

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Am29LV128MH/L H 123R PC I

TEMPERATURE RANGE

I = Industrial (–40

PAC KA G E TYPE

E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)
F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056)
PC = 64-Ball Fortified Ball Grid Array (

1.0 mm pitch, 13 x 11 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +85°C)

FBGA),

SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = V

IL

H = Uniform sector device, highest address sector protected
L = Uniform sector device, lowest address sector protected

DEVICE NUMBER/DESCRIPTION

Am29LV128MH/L
128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO™ Control,

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package

Am29LV128MH93R
Am29LV128ML93R

Am29LV128MH103R
Am29LV128ML103R

Am29LV128MH113R
Am29LV128ML113R

Am29LV128MH123R
Am29LV128ML123R

Speed

(ns)

90 3.0–3.6 V

100 2.7–3.6 V

EI,

FI

110 1.65–3.6 V

120 1.65–3.6 V

Valid Combinations

V

IO

Range

V

CC

Range

3.0–3.6 V

Valid Combinations for
Fortified BGA Package

Order Number Package Marking

Am29LV128MH93R
Am29LV128ML93R

Am29LV128MH103R
Am29LV128ML103R

Am29LV128MH113R
Am29LV128ML113R

Am29LV128MH123R
Am29LV128ML123R

PCI

L128MH93N
L128ML93N

L128MH103N
L128ML103N

L128MH113N
L128ML113N

L128MH123N
L128ML123N

I

Speed

(ns)

90

100

110

120

V

IO

Range

3.0–

3.6V

2.7–

3.6 V

1.65–

3.6 V

1.65–

3.6 V

V

CC

Range

3.0–

3.6 V

Valid Combinations list configurations planned to be supported in vol­ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re­leased combinations.

Notes:

1. For 100, 110, and 120 speed option shown in product selector guide, contact AMD for availability and ordering information.

2. To select product with ESN factory-locked into the SecSi Sector: 1) select order number from the valid combinations given above, 2) add designator “N” at the

end of the order number, and 3) modify the speed option indicator as follows [103R = 10R, 113R = 11R, 123R = 12R, 93R, 103, 113, 123 = no change].
Example: Am29LV128MH12RPCIN. For Fortified BGA pacakges, modify the speed option indicator as follows: [103N = 10N, 113N = 11N, 123N = 12N, 93N =
no change]. The designator “N” will also appear at the end of the package marking. Example: L128MH12NIN.

)

8 Am29LV128MH/L September 9, 2003

DATASHEET

DEVICE BUS OPERATIONS

This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca­tion. The register is a latch used to store the com­mands, along with the address and data information
needed to execute the command. The contents of the

Table 1. Device Bus Operations

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

DQ8–DQ15

Addresses

Operation CE# OE# WE# RESET# WP# ACC

Read L L H H

Write (Program/Erase) L H L H (Note 3) X A

Accelerated Program L H L H

±

V

Standby

Output Disable L H H H

Reset X X X L

Sector Group Protect
(Note 2)

Sector Group Unprotect
(Note 2)

Temp orary Sector Grou p
Unprotect

CC

0.3 V

XX

LHL V

LHL V

XXX V

V

CC

0.3 V

±

ID

ID

ID

XX

(Note 3) V

HH

XH

XX

XX

HX

HX

HX A

(Note 2)

SA, A6 =L,

A3=L, A2=L,

A1=H, A0=L

SA, A6=H,

A3=L, A2=L,

A1=H, A0=L

DQ0–

DQ7

A

IN

IN

A

IN

X

X

X

D

(Note 4) (Note 4)

(Note 4) (Note 4)

High-Z High-Z High-Z

High-Z High-Z High-Z

High-Z High-Z High-Z

(Note 4) X X

(Note 4) X X

IN

(Note 4) (Note 4) High-Z

OUT

BYTE#

= V

IH

D

OUT

BYTE#

= V

IL

DQ8–DQ14

= High-Z,

DQ15 = A-1

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

A

IN

= Data Out

OUT

Notes:

1. Addresses are A22:A0 in word mode; A22:A-1 in byte mode. Sector addresses are A22:A15 in both modes.

2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the

“Sector Group Protection and Unprotection” section.

3. If WP# = V

, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as

IL

determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped from the factory (The
SecSi Sector may be factory protected depending on version ordered.)

4. D

IN

or D

as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

OUT

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con­figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

VersatileIO™ (VIO) Control

The VersatileIO™ (VIO) control allows the host system

to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage

level that is asserted on V

options on this device.

for V

IO

. See Ordering Information

IO

September 9, 2003 Am29LV128MH/L 9

DATASHEET

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

. CE# is the power

IL

control and selects the device. OE# is the output con­trol and gates array data to the output pins. WE#
should remain at V

.

IH

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com­mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing speci­fications and to Figure 14 for the timing diagram. Refer
to the DC Characteristics table for the active current
specification on reading array data.

Page Mode Read

The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper­ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad­dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.

The random or initial page access is equal to t

and subsequent page read accesses (as long as

t

CE

ACC

or

the locations specified by the microprocessor falls
within that page) is equivalent to t

. When CE# is

PAC C

deasserted and reasserted for a subsequent access,
the access time is t

or tCE. Fast page mode ac-

ACC

cesses are obtained by keeping the “read-page ad­dresses” constant and changing the “intra-read page”
addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

The device features an Unlock Bypass mode to facili­tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re­quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using

, and OE# to VIH.

IL

both standard and Unlock Bypass command se-

quences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies.

Refer to the DC Characteristics table for the active

current specification for the write mode. The AC Char-

acteristics section contains timing specification tables

and timing diagrams for write operations.

Write Buffer

Write Buffer Programming allows the system write to a

maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming

time than the standard programming algorithms. See

“Write Buffer” for more information.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the system asserts V

on this pin, the device auto-

HH

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sector

groups, and uses the higher voltage on the pin to re-

duce the time required for program operations. The

system would use a two-cycle program command se-

quence as required by the Unlock Bypass mode. Re-

moving V

to normal operation.

not be at V

from the WP#/ACC pin returns the device

HH

Note that the WP#/ACC pin must

for operations other than accelerated

HH

programming, or device damage may result. WP# has

an internal pullup; when unconnected, WP# is at V

.

IH

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V

(Note that this is a more restricted voltage range than

± 0.3 V.

IO

10 Am29LV128MH/L September 9, 2003

DATASHEET

VIH.) If CE# and RESET# are held at VIH, but not within

± 0.3 V, the device will be in the standby mode, but

V

IO

the standby current will be greater. The device re­quires standard access time (t

) for read access

CE

when the device is in either of these standby modes,
before it is ready to read data.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

Refer to the DC Characteristics table for the standby
current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en­ergy consumption. The device automatically enables
this mode when addresses remain stable for t

ACC

+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad­dress access timings provide new data when ad­dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re­setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

RP

, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is
ready to accept another command sequence, to en­sure data integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I

but not within VSS±0.3 V, the standby current will

at V

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.

The RESET# pin may be tied to the system reset cir­cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.

September 9, 2003 Am29LV128MH/L 11

DATASHEET

Table 2. Sector Address Table

8-bit

Sector A22–A15

SA0 00000000 64/32 000000–00FFFF 000000–007FFF

SA1 00000001 64/32 010000–01FFFF 008000–00FFFF

SA2 00000010 64/32 020000–02FFFF 010000–017FFF

SA3 00000011 64/32 030000–03FFFF 018000–01FFFF

SA4 00000100 64/32 040000–04FFFF 020000–027FFF

SA5 00000101 64/32 050000–05FFFF 028000–02FFFF

SA6 00000110 64/32 060000–06FFFF 030000–037FFF

SA7 00000111 64/32 070000–07FFFF 038000–03FFFF

SA8 00001000 64/32 080000–08FFFF 040000–047FFF

SA9 00001001 64/32 090000–09FFFF 048000–04FFFF

SA10 00001010 64/32 0A0000–0AFFFF 050000–057FFF

SA11 00001011 64/32 0B0000–0BFFFF 058000–05FFFF

SA12 00001100 64/32 0C0000–0CFFFF 060000–067FFF

SA13 00001101 64/32 0D0000–0DFFFF 068000–06FFFF

SA14 00001110 64/32 0E0000–0EFFFF 070000–077FFF

SA15 00001111 64/32 0F0000–0FFFFF 078000–07FFFF

SA16 00010000 64/32 100000–10FFFF 080000–087FFF

SA17 00010001 64/32 110000–11FFFF 088000–08FFFF

SA18 00010010 64/32 120000–12FFFF 090000–097FFF

SA19 00010011 64/32 130000–13FFFF 098000–09FFFF

SA20 00010100 64/32 140000–14FFFF 0A0000–0A7FFF

SA21 00010101 64/32 150000–15FFFF 0A8000–0AFFFF

SA22 00010110 64/32 160000–16FFFF 0B0000–0B7FFF

SA23 00010111 64/32 170000–17FFFF 0B8000–0BFFFF

SA24 00011000 64/32 180000–18FFFF 0C0000–0C7FFF

SA25 00011001 64/32 190000–19FFFF 0C8000–0CFFFF

SA26 00011010 64/32 1A0000–1AFFFF 0D0000–0D7FFF

SA27 00011011 64/32 1B0000–1BFFFF 0D8000–0DFFFF

SA28 00011100 64/32 1C0000–1CFFFF 0E0000–0E7FFF

SA29 00011101 64/32 1D0000–1DFFFF 0E8000–0EFFFF

SA30 00011110 64/32 1E0000–1EFFFF 0F0000–0F7FFF

SA31 00011111 64/32 1F0000–1FFFFF 0F8000–0FFFFF

SA32 00100000 64/32 200000–20FFFF 100000–107FFF

SA33 00100001 64/32 210000–21FFFF 108000–10FFFF

SA34 00100010 64/32 220000–22FFFF 110000–117FFF

SA35 00100011 64/32 230000–23FFFF 118000–11FFFF

SA36 00100100 64/32 240000–24FFFF 120000–127FFF

SA37 00100101 64/32 250000–25FFFF 128000–12FFFF

SA38 00100110 64/32 260000–26FFFF 130000–137FFF

SA39 00100111 64/32 270000–27FFFF 138000–13FFFF

SA40 00101000 64/32 280000–28FFFF 140000–147FFF

SA41 00101001 64/32 290000–29FFFF 148000–14FFFF

SA42 00101010 64/32 2A0000–2AFFFF 150000–157FFF

SA43 00101011 64/32 2B0000–2BFFFF 158000–15FFFF

SA44 00101100 64/32 2C0000–2CFFFF 160000–167FFF

SA45 00101101 64/32 2D0000–2DFFFF 168000–16FFFF

SA46 00101110 64/32 2E0000–2EFFFF 170000–177FFF

Sector Size

(Kbytes/Kwords)

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

12 Am29LV128MH/L September 9, 2003

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA47 00101111 64/32 2F0000–2FFFFF 178000–17FFFF

SA48 00110000 64/32 300000–30FFFF 180000–187FFF

SA49 00110001 64/32 310000–31FFFF 188000–18FFFF

SA50 00110010 64/32 320000–32FFFF 190000–197FFF

SA51 00110011 64/32 330000–33FFFF 198000–19FFFF

SA52 00110100 64/32 340000–34FFFF 1A0000–1A7FFF

SA53 00110101 64/32 350000–35FFFF 1A8000–1AFFFF

SA54 00110110 64/32 360000–36FFFF 1B0000–1B7FFF

SA55 00110111 64/32 370000–37FFFF 1B8000–1BFFFF

SA56 00111000 64/32 380000–38FFFF 1C0000–1C7FFF

SA57 00111001 64/32 390000–39FFFF 1C8000–1CFFFF

SA58 00111010 64/32 3A0000–3AFFFF 1D0000–1D7FFF

SA59 00111011 64/32 3B0000–3BFFFF 1D8000–1DFFFF

SA60 00111100 64/32 3C0000–3CFFFF 1E0000–1E7FFF

SA61 00111101 64/32 3D0000–3DFFFF 1E8000–1EFFFF

SA62 00111110 64/32 3E0000–3EFFFF 1F0000–1F7FFF

SA63 00111111 64/32 3F0000–3FFFFF 1F8000–1FFFFF

SA64 01000000 64/32 400000–40FFFF 200000–207FFF

SA65 01000001 64/32 410000–41FFFF 208000–20FFFF

SA66 01000010 64/32 420000–42FFFF 210000–217FFF

SA67 01000011 64/32 430000–43FFFF 218000–21FFFF

SA68 01000100 64/32 440000–44FFFF 220000–227FFF

SA69 01000101 64/32 450000–45FFFF 228000–22FFFF

SA70 01000110 64/32 460000–46FFFF 230000–237FFF

SA71 01000111 64/32 470000–47FFFF 238000–23FFFF

SA72 01001000 64/32 480000–48FFFF 240000–247FFF

SA73 01001001 64/32 490000–49FFFF 248000–24FFFF

SA74 01001010 64/32 4A0000–4AFFFF 250000–257FFF

SA75 01001011 64/32 4B0000–4BFFFF 258000–25FFFF

SA76 01001100 64/32 4C0000–4CFFFF 260000–267FFF

SA77 01001101 64/32 4D0000–4DFFFF 268000–26FFFF

SA78 01001110 64/32 4E0000–4EFFFF 270000–277FFF

SA79 01001111 64/32 4F0000–4FFFFF 278000–27FFFF

SA80 01010000 64/32 500000–50FFFF 280000–287FFF

SA81 01010001 64/32 510000–51FFFF 288000–28FFFF

SA82 01010010 64/32 520000–52FFFF 290000–297FFF

SA83 01010011 64/32 530000–53FFFF 298000–29FFFF

SA84 01010100 64/32 540000–54FFFF 2A0000–2A7FFF

SA85 01010101 64/32 550000–55FFFF 2A8000–2AFFFF

SA86 01010110 64/32 560000–56FFFF 2B0000–2B7FFF

SA87 01010111 64/32 570000–57FFFF 2B8000–2BFFFF

SA88 01011000 64/32 580000–58FFFF 2C0000–2C7FFF

SA89 01011001 64/32 590000–59FFFF 2C8000–2CFFFF

SA90 01011010 64/32 5A0000–5AFFFF 2D0000–2D7FFF

SA91 01011011 64/32 5B0000–5BFFFF 2D8000–2DFFFF

SA92 01011100 64/32 5C0000–5CFFFF 2E0000–2E7FFF

SA93 01011101 64/32 5D0000–5DFFFF 2E8000–2EFFFF

SA94 01011110 64/32 5E0000–5EFFFF 2F0000–2F7FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

September 9, 2003 Am29LV128MH/L 13

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA95 01011111 64/32 5F0000–5FFFFF 2F8000–2FFFFF

SA96 01100000 64/32 600000–60FFFF 300000–307FFF

SA97 01100001 64/32 610000–61FFFF 308000–30FFFF

SA98 01100010 64/32 620000–62FFFF 310000–317FFF

SA99 01100011 64/32 630000–63FFFF 318000–31FFFF

SA100 01100100 64/32 640000–64FFFF 320000–327FFF

SA101 01100101 64/32 650000–65FFFF 328000–32FFFF

SA102 01100110 64/32 660000–66FFFF 330000–337FFF

SA103 01100111 64/32 670000–67FFFF 338000–33FFFF

SA104 01101000 64/32 680000–68FFFF 340000–347FFF

SA105 01101001 64/32 690000–69FFFF 348000–34FFFF

SA106 01101010 64/32 6A0000–6AFFFF 350000–357FFF

SA107 01101011 64/32 6B0000–6BFFFF 358000–35FFFF

SA108 01101100 64/32 6C0000–6CFFFF 360000–367FFF

SA109 01101101 64/32 6D0000–6DFFFF 368000–36FFFF

SA110 01101110 64/32 6E0000–6EFFFF 370000–377FFF

SA111 01101111 64/32 6F0000–6FFFFF 378000–37FFFF

SA112 01110000 64/32 700000–70FFFF 380000–387FFF

SA113 01110001 64/32 710000–71FFFF 388000–38FFFF

SA114 01110010 64/32 720000–72FFFF 390000–397FFF

SA115 01110011 64/32 730000–73FFFF 398000–39FFFF

SA116 01110100 64/32 740000–74FFFF 3A0000–3A7FFF

SA117 01110101 64/32 750000–75FFFF 3A8000–3AFFFF

SA118 01110110 64/32 760000–76FFFF 3B0000–3B7FFF

SA119 01110111 64/32 770000–77FFFF 3B8000–3BFFFF

SA120 01111000 64/32 780000–78FFFF 3C0000–3C7FFF

SA121 01111001 64/32 790000–79FFFF 3C8000–3CFFFF

SA122 01111010 64/32 7A0000–7AFFFF 3D0000–3D7FFF

SA123 01111011 64/32 7B0000–7BFFFF 3D8000–3DFFFF

SA124 01111100 64/32 7C0000–7CFFFF 3E0000–3E7FFF

SA125 01111101 64/32 7D0000–7DFFFF 3E8000–3EFFFF

SA126 01111110 64/32 7E0000–7EFFFF 3F0000–3F7FFF

SA127 01111111 64/32 7F0000–7FFFFF 3F8000–3FFFFF

SA128 10000000 64/32 800000–80FFFF 400000–407FFF

SA129 10000001 64/32 810000–81FFFF 408000–40FFFF

SA130 10000010 64/32 820000–82FFFF 410000–417FFF

SA131 10000011 64/32 830000–83FFFF 418000–41FFFF

SA132 10000100 64/32 840000–84FFFF 420000–427FFF

SA133 10000101 64/32 850000–85FFFF 428000–42FFFF

SA134 10000110 64/32 860000–86FFFF 430000–437FFF

SA135 10000111 64/32 870000–87FFFF 438000–43FFFF

SA136 10001000 64/32 880000–88FFFF 440000–447FFF

SA137 10001001 64/32 890000–89FFFF 448000–44FFFF

SA138 10001010 64/32 8A0000–8AFFFF 450000–457FFF

SA139 10001011 64/32 8B0000–8BFFFF 458000–45FFFF

SA140 10001100 64/32 8C0000–8CFFFF 460000–467FFF

SA141 10001101 64/32 8D0000–8DFFFF 468000–46FFFF

SA142 10001110 64/32 8E0000–8EFFFF 470000–477FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

14 Am29LV128MH/L September 9, 2003

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA143 10001111 64/32 8F0000–8FFFFF 478000–47FFFF

SA144 10010000 64/32 900000–90FFFF 480000–487FFF

SA145 10010001 64/32 910000–91FFFF 488000–48FFFF

SA146 10010010 64/32 920000–92FFFF 490000–497FFF

SA147 10010011 64/32 930000–93FFFF 498000–49FFFF

SA148 10010100 64/32 940000–94FFFF 4A0000–4A7FFF

SA149 10010101 64/32 950000–95FFFF 4A8000–4AFFFF

SA150 10010110 64/32 960000–96FFFF 4B0000–4B7FFF

SA151 10010111 64/32 970000–97FFFF 4B8000–4BFFFF

SA152 10011000 64/32 980000–98FFFF 4C0000–4C7FFF

SA153 10011001 64/32 990000–99FFFF 4C8000–4CFFFF

SA154 10011010 64/32 9A0000–9AFFFF 4D0000–4D7FFF

SA155 10011011 64/32 9B0000–9BFFFF 4D8000–4DFFFF

SA156 10011100 64/32 9C0000–9CFFFF 4E0000–4E7FFF

SA157 10011101 64/32 9D0000–9DFFFF 4E8000–4EFFFF

SA158 10011110 64/32 9E0000–9EFFFF 4F0000–4F7FFF

SA159 10011111 64/32 9F0000–9FFFFF 4F8000–4FFFFF

SA160 10100000 64/32 A00000–A0FFFF 500000–507FFF

SA161 10100001 64/32 A10000–A1FFFF 508000–50FFFF

SA162 10100010 64/32 A20000–A2FFFF 510000–517FFF

SA163 10100011 64/32 A30000–A3FFFF 518000–51FFFF

SA164 10100100 64/32 A40000–A4FFFF 520000–527FFF

SA165 10100101 64/32 A50000–A5FFFF 528000–52FFFF

SA166 10100110 64/32 A60000–A6FFFF 530000–537FFF

SA167 10100111 64/32 A70000–A7FFFF 538000–53FFFF

SA168 10101000 64/32 A80000–A8FFFF 540000–547FFF

SA169 10101001 64/32 A90000–A9FFFF 548000–54FFFF

SA170 10101010 64/32 AA0000–AAFFFF 550000–557FFF

SA171 10101011 64/32 AB0000–ABFFFF 558000–55FFFF

SA172 10101100 64/32 AC0000–ACFFFF 560000–567FFF

SA173 10101101 64/32 AD0000–ADFFFF 568000–56FFFF

SA174 10101110 64/32 AE0000–AEFFFF 570000–577FFF

SA175 10101111 64/32 AF0000–AFFFFF 578000–57FFFF

SA176 10110000 64/32 B00000–B0FFFF 580000–587FFF

SA177 10110001 64/32 B10000–B1FFFF 588000–58FFFF

SA178 10110010 64/32 B20000–B2FFFF 590000–597FFF

SA179 10110011 64/32 B30000–B3FFFF 598000–59FFFF

SA180 10110100 64/32 B40000–B4FFFF 5A0000–5A7FFF

SA181 10110101 64/32 B50000–B5FFFF 5A8000–5AFFFF

SA182 10110110 64/32 B60000–B6FFFF 5B0000–5B7FFF

SA183 10110111 64/32 B70000–B7FFFF 5B8000–5BFFFF

SA184 10111000 64/32 B80000–B8FFFF 5C0000–5C7FFF

SA185 10111001 64/32 B90000–B9FFFF 5C8000–5CFFFF

SA186 10111010 64/32 BA0000–BAFFFF 5D0000–5D7FFF

SA187 10111011 64/32 BB0000–BBFFFF 5D8000–5DFFFF

SA188 10111100 64/32 BC0000–BCFFFF 5E0000–5E7FFF

SA189 10111101 64/32 BD0000–BDFFFF 5E8000–5EFFFF

SA190 10111110 64/32 BE0000–BEFFFF 5F0000–5F7FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

September 9, 2003 Am29LV128MH/L 15

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA191 10111111 64/32 BF0000–BFFFFF 5F8000–5FFFFF

SA192 11000000 64/32 C00000–C0FFFF 600000–607FFF

SA193 11000001 64/32 C10000–C1FFFF 608000–60FFFF

SA194 11000010 64/32 C20000–C2FFFF 610000–617FFF

SA195 11000011 64/32 C30000–C3FFFF 618000–61FFFF

SA196 11000100 64/32 C40000–C4FFFF 620000–627FFF

SA197 11000101 64/32 C50000–C5FFFF 628000–62FFFF

SA198 11000110 64/32 C60000–C6FFFF 630000–637FFF

SA199 11000111 64/32 C70000–C7FFFF 638000–63FFFF

SA200 11001000 64/32 C80000–C8FFFF 640000–647FFF

SA201 11001001 64/32 C90000–C9FFFF 648000–64FFFF

SA202 11001010 64/32 CA0000–CAFFFF 650000–657FFF

SA203 11001011 64/32 CB0000–CBFFFF 658000–65FFFF

SA204 11001100 64/32 CC0000–CCFFFF 660000–667FFF

SA205 11001101 64/32 CD0000–CDFFFF 668000–66FFFF

SA206 11001110 64/32 CE0000–CEFFFF 670000–677FFF

SA207 11001111 64/32 CF0000–CFFFFF 678000–67FFFF

SA208 11010000 64/32 D00000–D0FFFF 680000–687FFF

SA209 11010001 64/32 D10000–D1FFFF 688000–68FFFF

SA210 11010010 64/32 D20000–D2FFFF 690000–697FFF

SA211 11010011 64/32 D30000–D3FFFF 698000–69FFFF

SA212 11010100 64/32 D40000–D4FFFF 6A0000–6A7FFF

SA213 11010101 64/32 D50000–D5FFFF 6A8000–6AFFFF

SA214 11010110 64/32 D60000–D6FFFF 6B0000–6B7FFF

SA215 11010111 64/32 D70000–D7FFFF 6B8000–6BFFFF

SA216 11011000 64/32 D80000–D8FFFF 6C0000–6C7FFF

SA217 11011001 64/32 D90000–D9FFFF 6C8000–6CFFFF

SA218 11011010 64/32 DA0000–DAFFFF 6D0000–6D7FFF

SA219 11011011 64/32 DB0000–DBFFFF 6D8000–6DFFFF

SA220 11011100 64/32 DC0000–DCFFFF 6E0000–6E7FFF

SA221 11011101 64/32 DD0000–DDFFFF 6E8000–6EFFFF

SA222 11011110 64/32 DE0000–DEFFFF 6F0000–6F7FFF

SA223 11011111 64/32 DF0000–DFFFFF 6F8000–6FFFFF

SA224 11100000 64/32 E00000–E0FFFF 700000–707FFF

SA225 11100001 64/32 E10000–E1FFFF 708000–70FFFF

SA226 11100010 64/32 E20000–E2FFFF 710000–717FFF

SA227 11100011 64/32 E30000–E3FFFF 718000–71FFFF

SA228 11100100 64/32 E40000–E4FFFF 720000–727FFF

SA229 11100101 64/32 E50000–E5FFFF 728000–72FFFF

SA230 11100110 64/32 E60000–E6FFFF 730000–737FFF

SA231 11100111 64/32 E70000–E7FFFF 738000–73FFFF

SA232 11101000 64/32 E80000–E8FFFF 740000–747FFF

SA233 11101001 64/32 E90000–E9FFFF 748000–74FFFF

SA234 11101010 64/32 EA0000–EAFFFF 750000–757FFF

SA235 11101011 64/32 EB0000–EBFFFF 758000–75FFFF

SA236 11101100 64/32 EC0000–ECFFFF 760000–767FFF

SA237 11101101 64/32 ED0000–EDFFFF 768000–76FFFF

SA238 11101110 64/32 EE0000–EEFFFF 770000–777FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

16 Am29LV128MH/L September 9, 2003

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA239 11101111 64/32 EF0000–EFFFFF 778000–77FFFF

SA240 11110000 64/32 F00000–F0FFFF 780000–787FFF

SA241 11110001 64/32 F10000–F1FFFF 788000–78FFFF

SA242 11110010 64/32 F20000–F2FFFF 790000–797FFF

SA243 11110011 64/32 F30000–F3FFFF 798000–79FFFF

SA244 11110100 64/32 F40000–F4FFFF 7A0000–7A7FFF

SA245 11110101 64/32 F50000–F5FFFF 7A8000–7AFFFF

SA246 11110110 64/32 F60000–F6FFFF 7B0000–7B7FFF

SA247 11110111 64/32 F70000–F7FFFF 7B8000–7BFFFF

SA248 11111000 64/32 F80000–F8FFFF 7C0000–7C7FFF

SA249 11111001 64/32 F90000–F9FFFF 7C8000–7CFFFF

SA250 11111010 64/32 FA0000–FAFFFF 7D0000–7D7FFF

SA251 11111011 64/32 FB0000–FBFFFF 7D8000–7DFFFF

SA252 11111100 64/32 FC0000–FCFFFF 7E0000–7E7FFF

SA253 11111101 64/32 FD0000–FDFFFF 7E8000–7EFFFF

SA254 11111110 64/32 FE0000–FEFFFF 7F0000–7F7FFF

SA255 11111111 64/32 FF0000–FFFFFF 7F8000–7FFFFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

September 9, 2003 Am29LV128MH/L 17

DATASHEET

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector group protection verifica­tion, through identifier codes output on DQ7–DQ0.
This mode is primarily intended for programming
equipment to automatically match a device to be pro­grammed with its corresponding programming algo­rithm. However, the autoselect codes can also be
accessed in-system through the command register.

When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A3, A2, A1, and A0 must be as shown in Table 3.

In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits (see Table 2). Table 3 shows the remain­ing address bits that are don’t care. When all neces­sary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Tables 10 and 11. This
method does not require V

. Refer to the Autoselect

ID

Command Sequence section for more information.

Table 3. Autoselect Codes, (High Voltage Method)

A22

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X

Cycle 1

Cycle 2 H H L 22 X 12h

Device ID

Cycle 3 H H H 22 X 00h

Sector Group
Protection Verification

SecSi Sector Indicator
Bit (DQ7), WP#
protects highest
address sector

SecSi Sector Indicator
Bit (DQ7), WP#
protects lowest
address sector

LLHXX

LLHSAX

LLHXX

LLHXX

to

A15

A14

to

A9A8toA7A6A5to

A10

V

ID

V

ID

V

ID

V

ID

V

ID

X L X L L L 00 X 01h

XL X

XL X L H L X X

XL X L H H X X

XL X L H H X X

A3

toA2A1 A0

A4

LLH 22 X 7Eh

DQ8 to DQ15

BYTE#

= V

BYTE#

IH

= V

DQ7 to DQ0

IL

01h (protected),

00h (unprotected)

98h (factory locked),

18h (not factory locked)

88h (factory locked),

08h (not factory locked)

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

18 Am29LV128MH/L September 9, 2003

DATASHEET

Sector Group Protection and Unprotection

The hardware sector group protection feature disables
both program and erase operations in any sector
group. The hardware sector group unprotection fea­ture re-enables both program and erase operations in
previously protected sector groups. Sector group pro­tection/unprotection can be implemented via two
methods.

Sector group protection/unprotection requires V
the RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 25 shows the timing
diagram. This method uses standard microprocessor
bus cycle timing. For sector group unprotect, all unpro­tected sector group must first be protected prior to the
first sector group unprotect write cycle.

The device is shipped with all sector groups unpro­tected. AMD offers the option of programming and pro­tecting sector groups at its factory prior to shipping the
device through AMD’s ExpressFlash™ Service. Con­tact an AMD representative for details.

It is possible to determine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.

Table 4. Sector Group Protection/Unprotection

Address Table

Sector Group A22–A15

SA0 00000000

SA1 00000001

SA2 00000010

SA3 00000011

SA4–SA7 000001xx

SA8–SA11 000010xx

SA12–SA15 000011xx

SA16–SA19 000100xx

SA20–SA23 000101xx

SA24–SA27 000110xx

SA28–SA31 000111xx

SA32–SA35 001000xx

SA36–SA39 001001xx

SA40–SA43 001010xx

SA44–SA47 001011xx

SA48–SA51 001100xx

SA52–SA55 001101xx

SA56–SA59 001110xx

SA60–SA63 001111xx

SA64–SA67 010000xx

SA68–SA71 010001xx

SA72–SA75 010010xx

SA76–SA79 010011xx

SA80–SA83 010100xx

on

ID

Sector Group A22–A15

SA84–SA87 010101xx

SA88–SA91 010110xx

SA92–SA95 010111xx

SA96–SA99 011000xx

SA100–SA103 011001xx

SA104–SA107 011010xx

SA108–SA111 011011xx

SA112–SA115 011100xx

SA116–SA119 011101xx

SA120–SA123 011110xx

SA124–SA127 011111xx

SA128–SA131 100000xx

SA132–SA135 100001xx

SA136–SA139 100010xx

SA140–SA143 100011xx

SA144–SA147 100100xx

SA148–SA151 100101xx

SA152–SA155 100110xx

SA156–SA159 100111xx

SA160–SA163 101000xx

SA164–SA167 101001xx

SA168–SA171 101010xx

SA172–SA175 101011xx

SA176–SA179 101100xx

SA180–SA183 101101xx

SA184–SA187 101110xx

SA188–SA191 101111xx

SA192–SA195 110000xx

SA196–SA199 110001xx

SA200–SA203 110010xx

SA204–SA207 110011xx

SA208–SA211 110100xx

SA212–SA215 110101xx

SA216–SA219 110110xx

SA220–SA223 110111xx

SA224–SA227 111000xx

SA228–SA231 111001xx

SA232–SA235 111010xx

SA236–SA239 111011xx

SA240–SA243 111100xx

SA244–SA247 111101xx

SA248–SA251 111110xx

SA252 11111100

SA253 11111101

SA254 11111110

SA255 11111111

September 9, 2003 Am29LV128MH/L 19

DATASHEET

Write Protect (WP#)

The Write Protect function provides a hardware
method of protecting the first or last sector group with­out using V

. Write Protect is one of two functions pro-

ID

vided by the WP#/ACC input.

If the system asserts V

on the WP#/ACC pin, the de-

IL

vice disables program and erase functions in the first
or last sector group independently of whether those
sector groups were protected or unprotected using the
method described in “Sector Group Protection and
Unprotection”. Note that if WP#/ACC is at V

when the

IL

device is in the standby mode, the maximum input
load current is increased. See the table in “DC Char­acteristics”.

If the system asserts V

on the WP#/ACC pin, the de-

IH

vice reverts to whether the first or last sector was pre­viously set to be protected or unprotected using the
method described in “Sector Group Protection and
Unprotection”.

when unconnected, WP# is at V

Note that WP# has an internal pullup;

.

IH

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ­ously protected sector groups to change data in-sys­tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID. During this mode, for­merly protected sector groups can be programmed or
erased by selecting the sector group addresses. Once

is removed from the RESET# pin, all the previously

V

ID

protected sector groups are protected again. Figure 1

shows the algorithm, and Figure 24 shows the timing
diagrams, for this feature.

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector Group

Unprotect Completed

(Note 2)

Notes:

1. All protected sector groups unprotected (If WP# = V
the first or last sector will remain protected).

2. All previously protected sector groups are protected
once again.

ID

IH

,

IL

Figure 1. Temporary Sector Group

Unprotect Operation

20 Am29LV128MH/L September 9, 2003

DATASHEET

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

= 25?

Yes

Device failed

Sector Group

Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

No

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

No

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

Yes

No

START

Protect all sectors:

The indicated portion
of the sector protect

ID

Reset

PLSCNT = 1

Yes

ID

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

No

PLSCNT
= 1000?

Yes

Device failed

Sector Group

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

No

All sectors
protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

No

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up

next sector

address

No

ID

Unprotect

Algorithm

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

September 9, 2003 Am29LV128MH/L 21

DATASHEET

SecSi (Secured Silicon) Sector Flash
Memory Region

The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the secu­rity of the ESN once the product is shipped to the field.

AMD offers the device with the SecSi Sector either
customer lockable (standard shipping option) or fac­tory locked (contact an AMD sales representative for
ordering information). The customer-lockable version
is shipped with the SecSi Sector unprotected, allowing
customers to program the sector after receiving the
device. The customer-lockable version also has the
SecSi Sector Indicator Bit permanently set to a “0.”
The factory-locked version is always protected when
shipped from the factory, and has the SecSi (Secured
Silicon) Sector Indicator Bit permanently set to a “1.”
Thus, the SecSi Sector Indicator Bit prevents cus­tomer-lockable devices from being used to replace de­vices that are factory locked.

function and unlock bypass modes are not available
when the SecSi Sector is enabled.

The SecSi sector address space in this device is allo­cated as follows:

Table 5. SecSi Sector Contents

SecSi Sector

Address Range

000000h–000007h

000008h–00007Fh Unavailable

Customer

Lockable

Determined by

customer

The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se­quence, it may read the SecSi Sector by using the ad­dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is­sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.

Note that the ACC

ESN Factory

Locked

ESN

ExpressFlash

Factory Locked

ESN or

determined by

customer

Determined by

customer

Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory

Unless otherwise specified, the device is shipped such
that the customer may program and protect the
256-byte SecSi sector.

The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass meth­ods, in addition to the standard programming com­mand sequence. See Command Definitions.

Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.

The SecSi Sector area can be protected using one of
the following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex­cept that

RESET# may be at either VIH or V

. This

ID

allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.

■ To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.

Factory Locked: SecSi Sector Programmed and
Protected At the Factory

In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. An ESN Factory
Locked device has an 16-byte random ESN at ad­dresses 000000h–000007h. Please contact your local
AMD sales representative for details on ordering ESN
Factory Locked devices.

Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service (Express
Flash Factory Locked). The devices are then shipped
from AMD’s factory with the SecSi Sector permanently
locked. Contact an AMD representative for details on
using AMD’s ExpressFlash service.

22 Am29LV128MH/L September 9, 2003

DATASHEET

START

RESET# =

or V

V

IH

ID

Wait 1 µs

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove VIH or VID

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Tables 10 and 11
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be

caused by spurious system level signals during V

CC

power-up and power-down transitions, or from system
noise.

Low V

When V
cept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until V

is greater than V

CC

LKO

. The
system must provide the proper signals to the control
pins to prevent unintentional writes when V
greater than V

LKO

.

CC

is

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

V

IL

CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up,

IL

the device does not accept commands on the rising
edge of WE#. The internal state machine is automati­cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out­lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde­pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys­tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 6–9. To terminate reading CFI data,
the system must write the reset command.

The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the
device to reading array data.

For further information, please refer to the CFI Specifi­cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna­tively, contact an AMD representative for copies of
these documents.

September 9, 2003 Am29LV128MH/L 23

DATASHEET

Table 6. CFI Query Identification String

Addresses (x16) Data Description

10h
11h
12h

13h
14h

15h
16h

17h
18h

19h
1Ah

0051h
0052h
0059h

0002h
0000h

0040h
0000h

0000h
0000h

0000h
0000h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Table 7. System Interface String

Addresses (x16) Data Description

Min. (write/erase)

V

1Bh 0027h

1Ch 0036h

1Dh 0000h V

1Eh 0000h V

1Fh 0007h Typical timeout per single byte/word write 2

20h 0007h Typical timeout for Min. size buffer write 2

21h 000Ah Typical timeout per individual block erase 2

22h 0000h Typical timeout for full chip erase 2

23h 0001h Max. timeout for byte/word write 2

24h 0005h Max. timeout for buffer write 2

25h 0004h Max. timeout per individual block erase 2

26h 0000h Max. timeout for full chip erase 2

CC

D7–D4: volt, D3–D0: 100 millivolt

Max. (write/erase)

V

CC

D7–D4: volt, D3–D0: 100 millivolt

Min. voltage (00h = no VPP pin present)

PP

Max. voltage (00h = no VPP pin present)

PP

N

N

N

times typical

N

times typical (00h = not supported)

N

µs

N

µs (00h = not supported)

N

ms

ms (00h = not supported)

times typical

N

times typical

24 Am29LV128MH/L September 9, 2003

DATASHEET

Table 8. Device Geometry Definition

Addresses (x16) Data Description

N

27h 0018h Device Size = 2

byte

28h
29h

2Ah
2Bh

0002h
0000h

0005h
0000h

2Ch 0001h

2Dh
2Eh
2Fh
30h

31h
32h
33h
34h

35h
36h
37h
38h

39h
3Ah
3Bh
3Ch

00FFh
0000h
0000h
0001h

0000h
0000h
0000h
0000h

0000h
0000h
0000h
0000h

0000h
0000h
0000h
0000h

Flash Device Interface description (refer to CFI publication 100)

N

Max. number of byte in multi-byte write = 2
(00h = not supported)

Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)

Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

September 9, 2003 Am29LV128MH/L 25

DATASHEET

Table 9. Primary Vendor-Specific Extended Query

Addresses (x16) Data Description

40h
41h
42h

43h 0031h Major version number, ASCII

44h 0033h Minor version number, ASCII

45h 0008h

46h 0002h

47h 0001h

48h 0001h

49h 0004h

4Ah 0000h

4Bh 0000h

4Ch 0001h

0050h
0052h
0049h

Query-unique ASCII string “PRI”

Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required

Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit

Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect
0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect
00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme
04 = 29LV800 mode

Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank

Burst Mode Type
00 = Not Supported, 01 = Supported

Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh 00B5h

4Eh 00C5h

4Fh

50h 0001h

0004h/

0005h

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top
Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top
WP# protect

Program Suspend

00h = Not Supported, 01h = Supported

26 Am29LV128MH/L September 9, 2003

DATASHEET

COMMAND DEFINITIONS

Writing specific address and data commands or se­quences into the command register initiates device op­erations. Tables 10 and 11 defines the valid register
command sequences.

data values or writing them in the improper sequence
may place the device in an unknown state.

command is then required to return the device to read­ing array data.

All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.

Writing incorrect address and

A reset

the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be­gins, however, the device ignores reset commands
until the operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de­vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.

After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a pro­gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.

must

The system
the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase op­eration, or if the device is in the autoselect mode. See
the next section, Reset Command, for more informa­tion.

See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa­rameters, and Figure 14 shows the timing diagram.

issue the reset command to return

Reset Command

Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).

Note that if DQ1 goes high during a Write Buffer Pro­gramming operation, the system must write the
Write-to-Buffer-Abort Reset command sequence to
reset the device for the next operation.

Autoselect Command Sequence

The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Tables 10 and 11 show the address and data require­ments. This method is an alternative to that shown in
Table 3, which is intended for PROM programmers
and requires V
command sequence may be written to an address that
is either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de­vice is actively programming or erasing.

The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence:

■ A read cycle at address XX00h returns the manu-

facturer code.

■ Three read cycles at addresses 01h, 0Eh, and 0Fh

return the device code.

■ A read cycle to an address containing a sector ad-

dress (SA), and the address 02h on A7–A0 in word
mode returns 01h if the sector is protected, or 00h if
it is unprotected.

The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de­vice was previously in Erase Suspend).

on address pin A9. The autoselect

ID

September 9, 2003 Am29LV128MH/L 27

DATASHEET

Enter SecSi Sector/Exit SecSi Sector
Command Sequence

The SecSi Sector region provides a secured data area
containing an 8-word/16-byte random Electronic Serial
Number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system is­sues the four-cycle Exit SecSi Sector command se­quence. The Exit SecSi Sector command sequence
returns the device to normal operation. Tables 10 and
11 show the address and data requirements for both
command sequences. See also “SecSi (Secured Sili­con) Sector Flash Memory Region” for further informa-

Note that the ACC function and unlock bypass

tion.

modes are not available when the SecSi Sector is en­abled.

Word/Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro­gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-

not

gorithm. The system is
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Tables 10 and 11 show the
address and data requirements for the word program
command sequence.

When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad­dresses are no longer latched. The system can deter­mine the status of the program operation by using
DQ7 or DQ6. Refer to the Write Operation Status sec­tion for information on these status bits.

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.

Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress.

required to provide further

Note that the SecSi

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro­gram words to the device faster than using the stan­dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un­lock cycles. This is followed by a third write cycle con­taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un­lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com­mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program­ming time. Tables 10 and 11 show the requirements
for the command sequence.

During the unlock bypass mode, only the Unlock By­pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com­mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.

Write Buffer Programming

Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. The
Write Buffer Programming command sequence is initi­ated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which pro­gramming will occur. The fourth cycle writes the sector
address and the number of word locations, minus one,
to be programmed. For example, if the system will pro­gram 6 unique address locations, then 05h should be
written to the device. This tells the device how many
write buffer addresses will be loaded with data and
therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot
exceed the size of the write buffer or the operation will
abort.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc­cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”

28 Am29LV128MH/L September 9, 2003

The fifth cycle writes the first address location and
data to be programmed. The write-buffer-page is se­lected by address bits A
dress/data pairs must fall within the
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.

The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be per­formed across multiple write-buffer pages. This also

MAX–A4

. All subsequent ad-

DATASHEET

means that Write Buffer Programming cannot be per­formed across multiple sectors. If the system attempts
to load programming data outside of the selected
write-buffer page, the operation will abort.

Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
system must therefore account for loading a
write-buffer location more than once. The counter dec­rements for each data load operation, not for each
unique write-buffer-address location. Note also that if
an address location is loaded more than once into the
buffer, the final data loaded for that address will be
programmed.

Once the specified number of write buffer locations
have been loaded, the system must then write the Pro­gram Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write
Buffer Programming.

The write-buffer programming operation can be sus­pended using the standard program suspend/resume
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.

The Write Buffer Programming Sequence can be
aborted in the following ways:

■ Load a value that is greater than the page buffer

size during the Number of Locations to Program
step.

■ Write to an address in a sector different than the

one specified during the Write-Buffer-Load com­mand.

■ Write an Address/Data pair to a different

write-buffer-page than the one selected by the
Starting Address during the write buffer data load­ing stage of the operation.

■ Write data other than the Confirm Command after

the specified number of data load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset
command sequence must be written to reset the de­vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-Abort Reset command sequence is re­quired when using Write-Buffer-Programming features
in Unlock Bypass mode.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc­cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”

Accelerated Program

The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts

on the WP#/ACC pin, the device automatically en-

V

HH

ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation.

WP#/

the

ACC pin must not be at VHH for operations

Note that

other than accelerated programming, or device dam­age may result. WP# has an internal pullup; when un­connected, WP# is at V

.

IH

Figure 5 illustrates the algorithm for the program oper­ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 18 for timing diagrams.

September 9, 2003 Am29LV128MH/L 29

Write “Write to Buffer”

command and

Sector Address

DATASHEET

No

Ye s

Ye s

(Note 1)

Write number of addresses

to program minus 1(WC)

and Sector Address

Write first address/data

WC = 0 ?

No

Abort Write to

Buffer Operation?

No

Write next address/data pair

WC = WC - 1

Write program buffer to

flash sector address

Read DQ7 - DQ0 at

Last Loaded Address

DQ7 = Data?

No

No

DQ5 = 1?DQ1 = 1?

Ye s

Ye s

Ye s

Part of “Write to Buffer”
Command Sequence

Write to a different

sector address

Write to buffer ABORTED.
Must write “Write-to-buffer

Abort Reset” command

sequence to return

to read mode.

Notes:

1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.

2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.

3. If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this flowchart
location was reached because DQ1= “1”, then the
Write to Buffer operation was ABORTED. In either
case, the proper reset command must be written
before the device can begin another operation. If
DQ1=1, write the
Write-Buffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset command.

4. See Tables 10 and 11 for command sequences
required for write buffer programming.

Read DQ7 - DQ0 with
address = Last Loaded

Address

(Note 2)

(Note 3)

DQ7 = Data?

No

FAIL or ABORT PASS

Ye s

Figure 4. Write Buffer Programming Operation

30 Am29LV128MH/L September 9, 2003

DATASHEET

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note: See Tables 10 and 11 for program command
sequence.

No

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Figure 5. Program Operation

No

Program Suspend/Program Resume
Command Sequence

The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Sus­pend command is written during a programming pro­cess, the device halts the program operation within 15

µs maximum (5 µs typical) and updates the status bits.

Addresses are not required when writing the Program
Suspend command.

After the programming operation has been sus­pended, the system can read array data from any
non-suspended sector. The Program Suspend com­mand may also be issued during a programming oper­ation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Sus­pend or Program Suspend. If a read is needed from
the SecSi Sector area (One-time Program area), then
user must use the proper command sequences to
enter and exit this region.

The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes
as required. When the device exits the autoselect
mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.

After the Program Resume command is written, the
device reverts to programming. The system can deter­mine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard pro­gram operation. See Write Operation Status for more
information.

The system must write the Program Resume com­mand to exit the Program Suspend mode and continue
the programming operation. The address of the pro­gram-suspended sector is required when writing this
command. Further writes of the Resume command
are ignored. Another Program Suspend command can
be written after the device has resume programming.

September 9, 2003 Am29LV128MH/L 31

Program Operation

r

or Write-to-Buffer

Sequence in Progress

Write address/data

XXXh/B0h

Wait 15 µs

Read data as

required

No

reading?

Done

DATASHEET

Write Program Suspend
Command Sequence

Command is also valid for
Erase-suspended-program
operations

Autoselect and SecSi Sector
read operations are also allowed

Data cannot be read from erase- o
program-suspended sectors

When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2.
Refer to the Write Operation Status section for infor­mation on these status bits.

Any commands written during the chip erase operation
are ignored.However, note that a hardware reset im-
mediately terminates the erase operation. If that oc­curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.

Note that the
SecSi Sector, autoselect, and CFI functions are un­available when an program operation is in progress.

Figure 6 illustrates the algorithm for the erase opera­tion. Refer to the Erase and Program Operations ta­bles in the AC Characteristics section for parameters,
and Figure 20 section for timing diagrams.

Yes

Write address/data

XXXh/30h

Device reverts to
operation prior to

Program Suspend

Write Program Resume
Command Sequence

Figure 6. Program Suspend/Program Resume

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con­trols or timings during these operations. Tables 10 and
11 show the address and data requirements for the
chip erase command sequence.

require the system to

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad­ditional unlock cycles are written, and are then fol­lowed by the address of the sector to be erased, and
the sector erase command. Tables 9 & 10 shows the
address and data requirements for the sector erase
command sequence.

not

The device does
prior to erase. The Embedded Erase algorithm auto­matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase ad­dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en­sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets
the device to the read mode. The system must re-

write the command sequence and any additional ad­dresses and commands.

autoselect, and CFI functions are unavailable when an
erase operation is in progress.

require the system to preprogram

Note that the SecSi Sector,

32 Am29LV128MH/L September 9, 2003

DATASHEET

The system can monitor DQ3 to determine if the sec­tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris­ing edge of the final WE# pulse in the command
sequence.

When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to the Write Opera­tion Status section for information on these status bits.

Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com­mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.

Figure 6 illustrates the algorithm for the erase opera­tion. Refer to the Erase and Program Operations ta­bles in the AC Characteristics section for parameters,
and Figure 20 section for timing diagrams.

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

No

Data = FFh?

Embedded
Erase
algorithm
in progress

Erase Suspend/Erase Resume
Commands

The Erase Suspend command, B0h, allows the sys­tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec­tor erase operation, including the 50 µs time-out pe­riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.

When the Erase Suspend command is written during
the sector erase operation, the device requires a typi­cal of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend com­mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation.

After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys­tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus­pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro­duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor­mation on these status bits.

After an erase-suspended program operation is com­plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Write Operation Status section for more
information.

In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.

Yes

To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writ-

Erasure Completed

ing this command. Further writes of the Resume com­mand are ignored. Another Erase Suspend command

Figure 7. Erase Operation

Notes:

1. See Tables 10 and 11 for erase command sequence.

2. See the section on DQ3 for information on the sector
erase timer.

can be written after the chip has resumed erasing.

September 9, 2003 Am29LV128MH/L 33

DATASHEET

Command Definitions

Table 10. Command Definitions (x16 Mode, BYTE# = VIH)

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001
Device ID (Note 9) 4 555 AA 2AA 55 555 90 X01 227E X0E 2212 X0F 2200

SecSi™ Sector Factory Protect
(Note 10)

Sector Group Protect Verify
(Note 12)

Autoselect (Note 8)

Enter SecSi Sector Region 3 555 AA 2AA 55 555 88
Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00
Program 4 555 AA 2AA 55 555 A0 PA PD

Write to Buffer (Note 11) 3 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD
Program Buffer to Flash 1 SA 29

Write to Buffer Abort Reset (Note 13) 3 555 AA 2AA 55 555 F0
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 14) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Program/Erase Suspend (Note 16) 1 SA B0
Program/Erase Resume (Note 17) 1 SA 30

CFI Query (Note 18) 1 55 98

Legend:

X = Don’t care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 555 AA 2AA 55 555 90 X03 (Note 10)

4 555 AA 2AA 55 555 90 (SA)X02 00/01

Bus Cycles (Notes 2–5)

SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A22–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD, PD, and WC.

5. Unless otherwise noted, address bits A22–A11 are don’t cares.

6. No unlock or command cycles required when device is in read
mode.

7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.

8. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.

9. The device ID must be read in three cycles.

10. If WP# protects the highest address sector, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the

lowest address sector, the data is 88h for factory locked and 08h
for not factor locked.

11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 21.

12. The data is 00h for an unprotected sector and 01h for a protected
sector.

13. Command sequence resets device for next command after
aborted write-to-buffer operation.

14. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.

15. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.

16. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.

17. The Erase Resume command is valid only during the Erase
Suspend mode.

18. Command is valid when device is ready to read array data or when
device is in autoselect mode.

34 Am29LV128MH/L September 9, 2003

DATASHEET

Table 11. Command Definitions (x8 Mode, BYTE# = VIL)

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0

Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 01
Device ID (Note 9) 4 AAA AA 555 55 AAA 90 X02 7E X1C 12 X1E 00
SecSi™ Sector Factory Protect

(Note 10)

Sector Group Protect Verify
(Note 12)

Autoselect (Note 8)

Enter SecSi Sector Region 3 AAA AA 555 55 AAA 88
Exit SecSi Sector Region 4 AAA AA 555 55 AAA 90 XXX 00
Program 4 AAA AA 555 55 AAA A0 PA PD

Write to Buffer (Note 11) 3 AAA AA 555 55 SA 25 SA BC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (Note 13) 3 AAA AA 555 55 AAA F0

Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass Program (Note 14) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30

Program/Erase Suspend (Note 16) 1 SA B0
Program/Erase Resume (Note 17) 1 SA 30

CFI Query (Note 18) 1 AA 98

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 AAA AA 555 55 AAA 90 X06 (Note 10)

4 AAA AA 555 55 AAA 90 (SA)X04 00/01

Legend:

X = Don’t care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of

WE# or CE# pulse, whichever happens first.

Bus Cycles (Notes 2–5)

SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A22–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
BC = Byte Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.

5. Unless otherwise noted, address bits A22–A11 are don’t cares.

6. No unlock or command cycles required when device is in read
mode.

7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.

8. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.

9. The device ID must be read in three cycles.

10. If WP# protects the highest address sector, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the

lowest address sector, the data is 88h for factory locked and 08h
for not factor locked.

11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 37.

12. The data is 00h for an unprotected sector group and 01h for a
protected sector group.

13. Command sequence resets device for next command after
aborted write-to-buffer operation.

14. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.

15. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.

16. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.

17. The Erase Resume command is valid only during the Erase
Suspend mode.

18. Command is valid when device is ready to read array data or when
device is in autoselect mode.

September 9, 2003 Am29LV128MH/L 35

DATASHEET

WRITE OPERATION STATUS

The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 12 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is com­plete or in progress. The device also provides a hard­ware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is
in progress or has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device out­puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac­tive for approximately 1 µs, then the device returns to the
read mode.

valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc­cessive read cycles.

Table 12 shows the outputs for Data# Polling on DQ7.
Figure 8 shows the Data# Polling algorithm. Figure 21
in the AC Characteristics section shows the Data#
Polling timing diagram.

START

Read DQ7–DQ0

Addr = VA

Yes

No

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor­mation on DQ7.

After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll­ing on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected. However, if the sys­tem reads DQ7 at an address within a protected
sector, the status may not be valid.

Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com­pleted the program or erase operation and DQ7 has

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.

Yes

PASS

Figure 8. Data# Polling Algorithm

36 Am29LV128MH/L September 9, 2003

DATASHEET

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

If the output is low (Busy), the device is actively eras­ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or in the erase-suspend-read mode. Table 12
shows the outputs for RY/BY#.

CC

.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com­plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad­dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.

During an Embedded Program or Erase algorithm op­eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi­mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo­rithm erases the unprotected sectors, and ignores the se­lected sectors that are protected.

The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de­vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna­tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).

If a program address falls within a protected sector,
DQ6 toggles for approximately 1
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

Table 12 shows the outputs for Toggle Bit I on DQ6.
Figure 9 shows the toggle bit algorithm. Figure 22 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 23 shows the differences be­tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.

µs after the program

September 9, 2003 Am29LV128MH/L 37

No

START

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

No

DATASHEET

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.

DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era­sure. (The system may use either OE# or CE# to con­trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for sector and
mode information. Refer to Table 12 to compare out­puts for DQ2 and DQ6.

Figure 9 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the RY/BY#: Ready/Busy# sub­section. Figure 22 shows the toggle bit timing diagram.
Figure 23 shows the differences between DQ2 and
DQ6 in graphical form.

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not
Complete, Write
Reset Command

Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.

No

Program/Erase

Operation Complete

Figure 9. Toggle Bit Algorithm

Reading Toggle Bits DQ6/DQ2

Refer to Figure 9 for the following discussion. When­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog­gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol­lowing read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys­tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog­gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de­vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy­cles, determining the status as described in the previ­ous paragraph. Alternatively, it may choose to perform

38 Am29LV128MH/L September 9, 2003

DATASHEET

other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de­termine the status of the operation (top of Figure 9).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program, erase, or
write-to- buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc­cessfully completed.

The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro­grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”

In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi­tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.

After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur­ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys­tem software should check the status of DQ3 prior to
and following each subsequent sector erase com­mand. If DQ3 is high on the second status check, the
last command might not have been accepted.

Table 12 shows the status of DQ3 relative to the other
status bits.

DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“1”. The system must issue the
Write-to-Buffer-Abort-Reset command sequence to re­turn the device to reading array data. See Write Buffer
Programming section for more details.

September 9, 2003 Am29LV128MH/L 39

DATASHEET

Table 12. Write Operation Status

DQ7

Standard

Mode

Program
Suspend

Mode

Erase

Suspend

Mode

Write-to-

Buffer

Status

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle N/A 0

Program­Suspend

Read

Erase-

Suspend

Read

Erase-Suspend-Program
(Embedded Program)

Busy (Note 3) DQ7# Toggle 0 N/A N/A 0 0
Abort (Note 4) DQ7# Toggle 0 N/A N/A 1 0

Program-Suspended
Sector

Non-Program
Suspended Sector

Erase-Suspended
Sector

Non-Erase Suspen ded
Sector

(Note 2) DQ6

1 No toggle 0 N/A Toggle N/A 1

DQ7# Toggle 0 N/A N/A N/A 0

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

DQ5

(Note 1) DQ3

Invalid (not allowed) 1

Data 1

Data 1

DQ2

(Note 2) DQ1 RY/BY#

40 Am29LV128MH/L September 9, 2003

DATASHEET

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65

Ambient Temperature

with Power Applied . . . . . . . . . . . . . . –65

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

V

CC

. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

V

IO

A9, OE#, ACC, and RESET#

(Note 2) . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V

All other pins (Note 1) . . . . . . –0.5 V to V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot V
Maximum DC voltage on input or I/O pins is V
See Figure 10. During voltage transitions, input or I/O
pins may overshoot to V
See Figure 11.

2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot V
periods of up to 20 ns. See Figure 10. Maximum DC
input voltage on pin A9, OE#, ACC, and RESET# is
+12.5 V which may overshoot to +14.0 V for periods up
to 20 ns.

3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.

to –2.0 V for periods of up to 20 ns.

SS

+2.0 V for periods up to 20 ns.

CC

°C to +150°C

°C to +125°C

+0.5 V

CC

+0.5 V.

CC

to –2.0 V for

SS

+0.8 V

–0.5 V

–2.0 V

V

+2.0 V

V

+0.5 V

2.0 V

20 ns

20 ns

Figure 10. Maximum Negative

Overshoot Waveform

20 ns

CC

CC

20 ns

Figure 11. Maximum Positive

Overshoot Waveform

20 ns

20 ns

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . . . . . . –40°C to +85°C

Supply Voltages

V

(regulated voltage range) . . . . . . . . . . . . . . . . 3.0–3.6 V

CC

V

(full voltage range) . . . . . . . . . . . . . . . . . . . . . 2.7–3.6 V

CC

V

(Note 2) . . . . . . . . . . . . . . . . . . . . . . 1.65–3.6 V (Note 3)

IO

Notes:

1. Operating ranges define those limits between which the
functionality of the device is guaranteed.

2. See Ordering Information section for valid VCC/VIO range
combinations. The I/Os will not operate at 3V when V

1.8V.

3. 100R parts have a V

range from 2.7–3.6 V.

IO

September 9, 2003 Am29LV128MH/L 41

=

IO

DC CHARACTERISTICS

CMOS Compatible

DATASHEET

Parameter

Symbol

I

LI

I

LIT

I

LO

I

LR

I

CC1

I

CC2

I

CC3

I

CC4

I

CC5

I

CC6

I

CC7

V

IL1

V

IH1

V

IL2

V

IH2

V

HH

V

ID

V

OL

V

OH1

V

OH2

V

LKO

Parameter Description

(Notes)

= VSS to VCC,

V

Input Load Current (1)

V

IN

= VCC

CC

A9, ACC Input Load Current VCC = V

V

Output Leakage Current

OUT

= V

V

CC

Reset Leakage Current VCC = V

VCC Active Read Current
(2, 3)

CE# = V

Test Conditions Min Typ Max Unit

max

; A9 = 12.5 V 35 µA

CC max

= VSS to VCC,

CC max

; RESET# = 12.5 V 35 µA

CC max

5 MHz 3 34

OE# = VIH,

IL,

1 MHz 13 43

±1.0 µA

±1.0 µA

mA

1 MHz 4 50

V

Initial Page Read Current (2, 3) CE# = V

CC

V

Intra-Page Read Current (2, 3) CE# = V

CC

VCC Active Write Current (3, 4) CE# = V

VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = V

VCC Reset Current (3) RESET# = V

V

Automatic Sleep Mode (3, 5)

IH

WP# = V

= V

OE# = V

IL,

OE# = V

IL,

OE# = V

IL,

± 0.3 V; V

CC

IH

IH

IH

IH

± 0.3 V, WP# = V

SS

= V

IL

SS

10 MHz 3 20

33 MHz 6 40 mA

50 60 mA

IH

IH

± 0.3 V,

15µA

15µA

15µA

mA10 MHz 40 80

Input Low Voltage 1(6, 7) –0.5 0.8 V

+

V

Input High Voltage 1 (6, 7) 1.9

CC

0.5

Input Low Voltage 2 (6, 8) –0.5 0.3 x VIOV

Input High Voltage 2 (6, 8) 1.9 VIO + 0.5 V

Voltage for ACC Program
Acceleration

Voltage for Autoselect and
Temporary Sector Unprotect

Output Low Voltage (10) IOL = 4.0 mA, VCC = V

Output High Voltage

= 2.7–3.6 V 11.5 12.5 V

V

CC

= 2.7–3.6 V 11.5 12.5 V

V

CC

0.15 x
V

= –2.0 mA, VCC = V

I

OH

IOH = –100 µA, VCC = V

CC min

CC min

CC min

= V

= V

= V

IO

IO

IO

0.85 V

IO

VIO–0.4 V

IO

Low VCC Lock-Out Voltage (9) 2.3 2.5 V

V

V

V

Notes:

1. On the WP#/ACC pin only, the maximum input load current when
WP# = V

is ± 5.0 µA.

IL

2. The ICC current listed is typically less than 2 mA/MHz, with OE# at

.

V

IH

3. Maximum I

4. I

active while Embedded Erase or Embedded Program is in

CC

progress.

specifications are tested with VCC = VCCmax.

CC

5. Automatic sleep mode enables the low power mode when
addresses remain stable for t

6. If V

7. V

8. V

< VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO.

IO

Maximum V

voltage requirements.

CC

voltage requirements.

IO

for these connections is VIO + 0.3 V

IH

+ 30 ns.

ACC

9. Not 100% tested.

10. Includes RY/BY#

42 Am29LV128MH/L September 9, 2003

TEST CONDITIONS

DATASHEET

3.3 V

Table 13. Test Specifications

Test Condition All Speeds Unit

Device

Under

Te st

C

L

Note:

Diodes are IN3064 or equivalent

6.2 kΩ

Figure 12. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

2.7 kΩ

Output Load 1 TTL gate

Output Load Capacitance, C
(including jig capacitance)

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement
reference levels (See Note)

Output timing measurement
reference levels

L

30 pF

1.5 V

0.5 V

IO

Note: If VIO < VCC, the reference level is 0.5 VIO.

Steady

Changing from H to L

Changing from L to H

V

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

1.5 V 0.5 V

0.0 V

Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.

Figure 13. Input Waveforms and Measurement Levels

V

IO

OutputMeasurement LevelInput

September 9, 2003 Am29LV128MH/L 43

AC CHARACTERISTICS

Read-Only Operations

DATASHEET

Parameter

JEDEC Std. 93R

t

AVAVtRC

t

AVQ VtACC

t

ELQVtCE

t

GLQVtOE

t

EHQZtDF

t

GHQZtDF

t

AXQXtOH

Description Test Setup

Read Cycle Time (Note 1) Min 90 100 110 120 ns

Address to Output Delay CE#, OE# = VILMax 90 100 110 120 ns

Chip Enable to Output Delay OE# = VILMax 90 100 110 120 ns

t

Page Access Time Max253030403040ns

PAC C

Output Enable to Output Delay Max 25 30 30 40 30 40 ns

Chip Enable to Output High Z (Note 1) Max 16 ns

Output Enable to Output High Z (Note 1) Max 16 ns

Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First

Output Enable Hold Time

t

OEH

(Note 1)

Read Min 0 ns

Toggle and
Data# Polling

Min 0 ns

Min 10 ns

Notes:

1. Not 100% tested.

2. See Figure 12 and Table 13 for test specifications.

3. AC Specifications listed are tested with V

= VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

IO

t

RC

Speed Options

103,

103R 113 113R 123 123R Unit

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

Addresses Stable

t

ACC

t

RH

t

RH

t

OEH

t

OE

t

CE

HIGH Z

Figure 14. Read Operation Timings

t

OH

Output Valid

t

DF

HIGH Z

44 Am29LV128MH/L September 9, 2003

AC CHARACTERISTICS

DATASHEET

A22-A2

-

A0*

A1

t

ACC

Aa

Data Bus

CE#

OE#

* Figure shows word mode. Addresses are A1–A-1 for byte mode.

Figure 15. Page Read Timings

Same Page

t

PAC C

Ad

Ab Ac

t

PAC C

t

PAC C

Qa Qb Qc Qd

September 9, 2003 Am29LV128MH/L 45

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

DATASHEET

Description All Speed Options UnitJEDEC Std.

t

Ready

t

Ready

t

RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)

RESET# Pulse Width Min 500 ns

t

RP

t

Reset High Time Before Read (See Note) Min 50 ns

RH

RESET# Low to Standby Mode Min 20 µs

RPD

t

RY/BY# Recovery Time Min 0 ns

RB

Note:

1. Not 100% tested.

2. AC Specifications listed are tested with V

RY/BY#

CE#, OE#

RESET#

Max 20

Max 500 ns

= VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

IO

t

RH

µs

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

RY/BY#

t

RB

CE#, OE#

RESET#

t

RP

Figure 16. Reset Timings

46 Am29LV128MH/L September 9, 2003

DATASHEET

AC CHARACTERISTICS

Erase and Program Operations

Parameter Speed Options

JEDEC Std. Description 93R 103, 103R 113, 113R 123, 123R Unit

t

t

AVAV

t

AVWL

t

WLAX

t

DVW H

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHDL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation

5. Byte/Word programming specification is based upon a single word/byte programming operation not utilizing the write buffer.

6. AC Specifications listed are tested with V

Write Cycle Time (Note 1) Min 90 100 110 120 ns

WC

t

Address Setup Time Min 0 ns

AS

t

Address Setup Time to OE# low during toggle bit polling Min 15 ns

ASO

t

Address Hold Time Min 45 ns

AH

Address Hold Time From CE# or OE# high

t

AHT

during toggle bit polling

t

Data Setup Time Min 45 ns

DS

t

Data Hold Time Min 0 ns

DH

t

Output Enable High during toggle bit polling Min 20 ns

OEPH

Read Recovery Time Before Write

t

GHWL

(OE# High to WE# Low)

t

CE# Setup Time Min 0 ns

CS

t

CE# Hold Time Min 0 ns

CH

t

Write Pulse Width Min 35 ns

WP

t

Write Pulse Width High Min 30 ns

WPH

Min 0 ns

Min 0 ns

Write Buffer Program Operation (Notes 2, 3) Typ 240 µs

Effective Write Buffer Program Operation
(Notes 2, 4)

Accelerated Effective Write Buffer Program
Operation (Notes 2, 4)

Single Byte Word
Program Operation (Note 2, 5)

Accelerated Single Byte Word Programming
Operation (Note 2, 5)

Per B yte Typ 7. 5 µs

Per Word Typ 15 µs

Per Byte Typ 6.25 µs

Per Word Typ 12.5 µs

Byte Typ 60 µs

Word Typ 60 µs

Byte Typ 54 µs

Word Typ 54 µs

Sector Erase Operation (Note 2) Typ 0.5 sec

t

VHHVHH

t

VCSVCC

t

BUSY

Rise and Fall Time (Note 1) Min 250 ns

Setup Time (Note 1) Min 50 µs

Erase/Program Valid to RY/BY# Delay Min 90 ns

= VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

IO

September 9, 2003 Am29LV128MH/L 47

DATASHEET

.

RY/BY#

CE#, OE#

t

RH

RESET#

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

RY/BY#

CE#, OE#

Ready

t

RB

RESET#

t

RP

Figure 17. Reset Timings

48 Am29LV128MH/L September 9, 2003

AC CHARACTERISTICS

DATASHEET

Addresses

CE#

OE#

WE#

Data

RY/BY#

V

CC

Program Command Sequence (last two cycles)

DH

t

AS

PA PA

t

CH

t

WPH

t

WC

555h

t

CS

t

WP

t

DS

t

A0h

t

VCS

Read Status Data (last two cycles)

PA

t

AH

t

WHWH1

PD

t

BUSY

Status

D

OUT

t

RB

otes:

. PA = program address, PD = program data, D
. Illustration shows device in word mode.

Figure 18. Program Operation Timings

V

HH

V

or V

IL

ACC

IH V

t

VHH

Figure 19. Accelerated Program Timing Diagram

is the true data at the program address.

OUT

t

VHH

IL

or V

IH

September 9, 2003 Am29LV128MH/L 49

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

DATASHEET

t

AS

555h for chip erase

VA

t

AH

VA

Addresses

t

WC

2AAh SA

CE#

t

t

WP

t

DS

55h

CH

t

WPH

t

DH

30h

10 for Chip Erase

t

BUSY

t

WHWH2

In

Progress

Complete

t

OE#

WE#

Data

t

CS

RY/BY#

t

VCS

V

CC

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

RB

50 Am29LV128MH/L September 9, 2003

AC CHARACTERISTICS

Addresses

t

ACC

t

CE#

OE#

WE#

DQ7

t

CH

t

OEH

CE

t

VA

t

RC

OE

DATASHEET

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

Figure 21. Data# Polling Timings (During Embedded Algorithms)

September 9, 2003 Am29LV128MH/L 51

AC CHARACTERISTICS

DATASHEET

Addresses

CE#

WE#

OE#

DQ6/DQ2

RY/BY#

t

DH

Valid Data

t

OEH

t

AHT

t

ASO

t

OEPH

t

OE

Valid

Status

(first read) (second read) (stops toggling)

Valid

Status

t

CEPH

t

t

AHT

AS

Valid

Status

Valid Data

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle

Figure 22. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

WE#

Erase

Erase

Suspend

Suspend Program

Erase Suspend

Read

Enter Erase

Erase
Suspend
Program

Erase Suspend

Read

Erase

Resume

Erase

Erase

Complete

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.

Figure 23. DQ2 vs. DQ6

52 Am29LV128MH/L September 9, 2003

AC CHARACTERISTICS

Temporary Sector Group Unprotect

Parameter

DATASHEET

All Speed OptionsJEDEC Std Description Unit

t

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

RESET# Setup Time for Temporary Sector

t

RSP

Unprotect

Note:

1. Not 100% tested.

2. AC Specifications listed are tested with V

V

ID

RESET#

VSS, VIL,
or V

IH

t

VIDR

CE#

WE#

t

RSP

Min 4 µs

= VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

IO

VSS, VIL,

or V

t

VIDR

Program or Erase Command Sequence

t

RRB

V

ID

IH

RY/BY#

Figure 24. Temporary Sector Group Unprotect Timing Diagram

September 9, 2003 Am29LV128MH/L 53

AC CHARACTERISTICS

V

ID

V

RESET#

IH

DATASHEET

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector Group Protect or Unprotect Verify

Data

60h 60h 40h

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 25. Sector Group Protect and Unprotect Timing Diagram

Status

54 Am29LV128MH/L September 9, 2003

DATASHEET

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter Speed Options

JEDEC Std. Description 93R 103, 103R 113, 113R 123, 123R Unit

t

t

AVAV

t

AVW L

t

ELAX

t

DVE H

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. Byte/Word programming specification is based upon a single word/byte programming operation not utilizing the write buffer.

6. AC Specifications listed are tested with V

Write Cycle Time (Note 1) Min 90 100 110 120 ns

WC

t

Address Setup Time Min 0 ns

AS

t

Address Hold Time Min 45 ns

AH

t

Data Setup Time Min 45 ns

DS

t

Data Hold Time Min 0 ns

DH

Read Recovery Time Before Write

t

GHEL

(OE# High to WE# Low)

t

WE# Setup Time Min 0 ns

WS

t

WE# Hold Time Min 0 ns

WH

t

CE# Pulse Width Min 45 ns

CP

t

CE# Pulse Width High Min 30 ns

CPH

Min 0 ns

Write Buffer Program Operation (Notes 2, 3) Typ 240 µs

Effective Write Buffer Program Operation
(Notes 2, 4)

Accelerated Effective Write Buffer Program
Operation (Notes 2, 4)

Single Byte Word
Program Operation (Note 2, 5)

Accelerated Single Byte Word
Programming Operation (Note 2, 5)

Per Byte Typ 7.5 µs

Per Word Typ 15 µs

Per Byte Typ 6.25 µs

Per Word Typ 12.5 µs

Byte Typ 60 µs

Word Typ 60 µs

Byte Typ 54 µs

Word Typ 54 µs

Sector Erase Operation (Note 2) Typ 0.5 sec

= VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

IO

September 9, 2003 Am29LV128MH/L 55

AC CHARACTERISTICS

DATASHEET

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program
2AA for erase

t

WC

t

WH

t

WS

t

RH

PA for program
SA for sector erase
555 for chip erase

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

BUSY

PD for program
30 for sector erase
10 for chip erase

Data# Polling

t

WHWH1 or 2

PA

DQ7# D

OUT

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D

is the data written to the device.

OUT

4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings

LATCHUP CHARACTERISTICS

Description Min Max

Input voltage with respect to V
(including A9, OE#, and RESET#)

Input voltage with respect to V

V

Current –100 mA +100 mA

CC

Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

on all pins except I/O pins

SS

on all I/O pins –1.0 V VCC + 1.0 V

SS

–1.0 V 12.5 V

56 Am29LV128MH/L September 9, 2003

DATASHEET

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.5 3.5 sec

Chip Erase Time 128 256 sec

Single Byte/Word
Program Time (Note 3)

Accelerated Single Byte/Word
Program Time
(Note 3)

Total Write Buffer Program
Time (Note 4)

Effective Write Buffer Program
Time (Note 5)

Total Accelerated Write Buffer
Program Time (Note 4)

Effective Accelerated Write
Buffer Program Time
(Note 5)

Chip Program Time 126 292 sec

Byte 60 600 µs

Word 60 600 µs

Byte 54 540 µs

Word 54 540 µs

240 1200 µs

Per Byte 7.5 38 µs

Per Word 15 75 µs

200 1040 µs

Per Byte 6.25 33 µs

Per Word 12.5 65 µs

Excludes 00h programming

prior to erasure (Note 6)

Excludes system level

overhead (Note 8)

Notes:

°

1. Typical program and erase times assume the following conditions: 25

C, 3.0 V VCC. Programming specifications assume that

all bits are programmed to 00h.

2. Maximum values are measured at VCC = 3.0, worst case temperature. Maximum values are valid up to and including 100,000
program/erase cycles.

3. Byte/Word programming specification is based upon a single word/byte programming operation not utilizing the write buffer.

4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.

5. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

6. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words
program faster than the maximum program times listed.

7. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

8. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
11 for further information on command definitions.

9. The device has a minimum erase and program cycle endurance of 100,000 cycles.

September 9, 2003 Am29LV128MH/L 57

DATASHEET

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol Parameter Description Test Setup Typ Max Unit

C

IN

Input Capacitance VIN = 0

BGA 4.2 5 pF

TSOP 8.5 12 pF

TSOP 6 7.5 pF

C

OUT

Output Capacitance V

OUT

= 0

BGA 5.4 6.5 pF

TSOP 7.5 9 pF

C

IN2

Control Pin Capacitance VIN = 0

BGA 3.9 4.7 pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Description Test Conditions Min Unit

°C10Years

Minimum Pattern Data Retention Time

150

°C20Years

125

58 Am29LV128MH/L September 9, 2003

DATASHEET

PHYSICAL DIMENSIONS

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package (TSOP)

PACKAGE

JEDEC

SYMBOL

A

A1

A2

b1

b

c1

c

D

D1

E

e

L

O

R

N

TS/TSR 56

MO-142 (B) EC

MIN.

---

0.05

0.95

0.50 BASIC

NOM.

---

---

1.00

0.20 0.230.17

0.22 0.270.17

--- 0.160.10

--- 0.210.10

20.00 20.2019.90

18.40 18.5018.30

14.00 14.1013.90

0.60 0.700.50

3˚ 5˚0˚

--- 0.200.08

56

MAX.

1.20

0.15

1.05

NOTES:

1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)

2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS

DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE

MOLD PROTUSION IS 0.15 mm PER SIDE.

6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.

7 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10 mm AND 0.25 mm FROM THE LEAD TIP.

8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.

9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

3160\38.10A

September 9, 2003 Am29LV128MH/L 59

DATASHEET

PHYSICAL DIMENSIONS

LAA064—64-Ball Fortified Ball Grid Array
13 x 11 mm Package

60 Am29LV128MH/L September 9, 2003

REVISION SUMMARY

Revision A (October 3, 2001)

DATASHEET

Distinctive Characteristics

Initial release as abbreviated Advance Information
data sheet.

Revision A+1 (March 20, 2002)

Distinctive Characteristics

Clarified description of Enhanced VersatileIO control.

Ordering Information

Corrected device density in device number/descrip­tion.

Physical Dimensions

Added drawing that shows both TS056 and TSR056
specifications.

Revision B (July 1, 2002)

Expanded data sheet to full specification version.

Revision B+1 (September 16, 2002)

Distinctive Characteristics, Physical Dimensions

Added 80-Ball Fine-Pitch BGA.

Product Selector Guide

Added 80-Ball Fine-Pitch BGA.

Added Note #1.

Added 103, 108, 113, 118, 123, 128 regulated OPNs.

Changed all OPNs that end with 4 or 9 to 3 or 8.

Program Suspend/Program Resume Command
Sequence

Changed 1ms to 15

µs maximum, with a typical of 5 µs.

Erase Suspend/Erase Resume Commands

Added that the device requires a typical of 5

µs.

Read-Only Operations, Erase Program Operations,
and Alternate CE# Controlled Erase and Program
Operations

Added regulated OPNs.

Changed all OPNs that end with 4 or 9 to 3 or 8.

Revision B+2 (November 11, 2002)

Global

Removed the Enhanced VI/O option and changed it to
VI/O only.

Changed the typical sector erase time to TBD.

Changed the typical write buffer word programming
time to TBD.

Product Selector Guide

Removed the 98R, 108, 108R, 118, 118R, 128, and
128R Speed Options.

Replaced Note #2.

Product Selector Guide and Read Only Operations

Added a 30 ns Page Access time and Output Enable
Access time to the 113R and 123R Speed Options.

Ordering Information

Modified Order numbers and package markings to re­flect the removal of speed options.

Modified the V

ranges.

IO

Added Notes #1 and #2.

Table 4. SecSi Sector Contents

Added x8 and x16

Operating Ranges

Changed the V

Added V

IO

supply range to 1.65–3.6 V.

IO

(regulated voltage range) and VIO (full volt-

age range).

CMOS Compatible

Removed V

, V

V

IL1

, VIH, VOL, and VOH from table and added

IL

, V

, V

IH1

IL2

, VOL, V

IH2

OH1

, and V

from the

OH2

CMOS table in the Am29LV640MH/L datasheet.

Erase and Programming Performance

Changed the typicals and/or maximums of Chip Erase
Time, Sector Erase Time, Effective Write Buffer Pro­gram Time, Program Time, and Accelerated Program
Time to TBD.

Customer Lockable: SecSi Sector NOT
Programmed or Protected at the factory.

Added second bullet, SecSi sector-protect verify text
and figure 3.

SecSi Sector Flash Memory Region, and Enter
SecSi Sector/Exit SecSi Sector Command
Sequence

Noted that the ACC function and unlock bypass modes
are not available when the SecSi sector is enabled.

September 9, 2003 Am29LV128MH/L 61

DATASHEET

Byte/Word Program Command Sequence, Sector
Erase Command Sequence, and Chip Erase Com­mand Sequence

Noted that the SecSi Sector, autoselect, and CFI
functions are unavailable when a program or erase
operation is in progress.

Common Flash Memory Interface (CFI)

Changed wording in last sentence of third paragraph
from, “...the autoselect mode.” to “...reading array
data.”

Changed CFI website address

Revision B+3 (December 2, 2002)

Global

Added sector group protection throughout datasheet
and added Table 4.

Product Selector Guide

Added V

Ordering Information

Corrected typos in V

Removed Notes #1 and 2.

Figure 6. Program Suspend/Program Resume

Change wait time to 15

Operating Ranges

Corrected typos in V

Removed full voltage range.

CMOS Compatible

Changed V

Removed typos in notes.

Read-Only Characteristics

Added a 30 ns option to t
ble.

Added note #3.

s to table and removed Note #2

IO

ranges.

IO

µs.

ranges.

IO

and V

IH1

minimum to 1.9.

IH2

and tOE standard in ta-

PA CC

Product Selector Guide

Removed 93R speed option.

Added note 2.

Ordering Information

Corrected Valid Combination to reflect speed option
changes.

Added Note.

AC Characteristics

Removed 93, 93R speed option.

Added Note

Input values in the t

WHWH

1 and t

2 parameters in

WHWH

the Erase and Program Options table that were previ­ously TBD. Also added notes 5 and 6.

Input values in the t

WHWH

1 and t

2 parameters in

WHWH

the Alternate CE# Controlled Erase and Program Op­tions table that were previously TBD. Also added notes

5.

Erase and Programming Performance

Input values into table that were previously TBD.

Added note 4.

Revision C (May 16, 2003)

Global

Converted to full datasheet version.

Modified SecSi Sector Flash Memory Region section
to include ESN references.

Changed data sheet title to Am29LV128MH/L.

Erase and Programming Performance

Input values into table that were previously TBD.

Modified notes.

Revision C + 1 (June 11, 2003)

Product Selector Guide

Added Note 2 to 113 and 123 speed grades

Hardware Reset, Erase and Program Operations,
Temporary Sector Unprotect, and Alternate CE#
Controlled Erase and Program Operations

Added Note.

Revision B+4 (February 14, 2003)

Ordering Information

Modified speed grade options available, changed
speed grades mentioned in Note.

AC Characteristics, Erase and Program Operations
and Alternate CE# Controlled Erase and Program
Operations

Distinctive Characteristics

Corrected performance characteristics.

Changed t
Program Operations value

Accelerated Effective Write Buffer

WHWH1

62 Am29LV128MH/L September 9, 2003

Revision C + 2 (September 9, 2003)

Global

Added 90 ns speed options and Ordering Part Num­bers

Ordering Information

Added Note regarding Ordering Part Numbers.

Program Suspend/Program Resume Command
Sequence

Modified last paragraph.

Command Definitions, Table 10

Modified First Addr for Program/Erase Suspend and
Resume.

AC Characteristics

Added TRB, TBUSY specs.

Trademarks

Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.