FUJITSU Am29LV128MH-L Service Manual

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Am29LV128MH/L

Data Sheet

July 2003

The following document specifie s Spansion me mory prod ucts that are no w offere d by both Adv anced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig­inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Futu re routine revisions wi ll occur when appropriate,
and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support exi sting part numbers beg inning with “ Am” an d “MBM”. T o orde r
these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about S pansion
memory solutions.

Publication Number 25270 Revision C Amendment +2 Issue Date September 9, 2003

THIS PAGE LEFT INTENTIONALLY BLANK.

DATASHEET

Am29LV128MH/L

128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit™ 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O

DISTINCTIVE CHARACTERISTICS

™ Control

ARCHITECTURAL ADVANTAGES

■ Single power supply operation

— 3 volt read, erase, and program operations

■ VersatileI/O

— Device generates data output voltages and tolerates

data input voltages on the CE# and DQ
inputs/outputs as determined by the voltage on the
V

■ Manufactured on 0.23 µm MirrorBit process

technology

■ SecSi

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence

— May be programmed and locked at the factory or by

the customer

■ Flexible sector architecture

— Two hundred fifty-six 32 Kword (64 Kbyte) sectors

■ Compatibility with JEDEC standards

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent
write protection

■ Minimum 100,000 erase cycle guarantee per sector

■ 20-year data retention at 125

PERFORMANCE CHARACTERISTICS

■ High performance

— 90 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 15 s typical effective write buffer word programming

time: 16-word/32-byte write buffer reduces overall
programming time for multiple-word updates

™ control

pin; operates from 1.65 to 3.6 V

IO

™ (Secured Silicon) Sector region

°C

— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer

■ Low power consumption (typical values at 3.0 V, 5

MHz)

— 13 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current

■ Package options

— 56-pin TSOP
— 64-ball Fortified BGA

SOFTWARE & HARDWARE FEATURES

■ Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall

multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

■ Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group
— Temporary Sector Group Unprotect: V

of changing code in locked sector groups

— WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

-level method

ID

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 25270 Rev: C Amendment/2
Issue Date: September 9, 2003

DATASHEET

GENERAL DESCRIPTION

The Am29LV128MH/L is a 128 Mbit, 3.0 volt single
power supply flash memory devices organized as
8,388,608 words or 16,777,216 bytes. The device has
a 16-bit wide data bus that can also function as an
8-bit wide data bus by using the BYTE# input. The de­vice can be programmed either in the host system or
in standard EPROM programmers.

An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
specified in the Product Selector Guide and the Order­ing Information sections. The device is offered in a
56-pin TSOP, 64-ball Fortified BGA. Each device has
separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.

Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to

input, a high-voltage accelerated program

a V

CC

(WP#/ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.

The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter­nally latch addresses and data needed for the pro­gramming and erase operations.

The sector erase architecture allows memory sec­tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.

Device programming and erasure are initiated through
command sequences. Once a program or erase oper­ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter­mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.

The VersatileI/O™ (V
tem to set the voltage levels that the device generates

) and an I/O voltage range (VIO), as

CC

) control allows the host sys-

IO

and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V
Refer to the Ordering Information section for valid V

IO

pin.

IO

options.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V

CC

tions during power transitions. The hardware sector
group protection feature disables both program and
erase operations in any combination of sector groups
of memory. This can be achieved in-system or via pro­gramming equipment.

The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The Program Sus-
pend/Program Resume feature enables the host sys­tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.

The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.

The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.

The SecSi

™ (Secured Silicon) Sector provides a

128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.

The Write Protect (WP#/ACC) feature protects the
first or last sector by asserting a logic low on the WP#
pin.

AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec­tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.

RELATED DOCUMENTS

For a comprehensive information on MirrorBit prod­ucts, including migration information, data sheets, ap­plication notes, and software drivers, please see
www.amd.com

→MirrorBit→Flash Information→Technical Docu-

tion

→Flash Memory→Product Informa-

mentation. The following is a partial list of documents
closely related to this product:

2 Am29LV128MH/L September 9, 2003

MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read

Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs

Am29LV256M, 256 Mbit MirrorBit Flash device
(in 64-ball, 18 x 12 mm Fortified BGA package)

DATASHEET

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations ....................................................... 9

Word/Byte Configuration .......................................................... 9

™

VersatileIO

Requirements for Reading Array Data ...................................10

Page Mode Read ............................................................................10

Writing Commands/Command Sequences ............................10

Write Buffer .....................................................................................10

Accelerated Program Operation ......................................................10

Autoselect Functions .......................................................................10

Standby Mode ........................................................................ 10

Automatic Sleep Mode ...........................................................11

RESET#: Hardware Reset Pin ............................................... 11

Output Disable Mode ..............................................................11

Table 2. Sector Address Table........................................................ 12

Autoselect Mode ..................................................................... 18

Table 3. Autoselect Codes, (High Voltage Method) ....................... 18

Sector Group Protection and Unprotection .............................19

Table 4. Sector Group Protection/Unprotection Address Table ..... 19

Write Protect (WP#) ................................................................ 20

Temporary Sector Group Unprotect ....................................... 20

Figure 1. Temporary Sector Group Unprotect Operation ................20

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...21

SecSi (Secured Silicon) Sector Flash Memory Region .......... 22

Table 5. SecSi Sector Contents ...................................................... 22

Figure 3. SecSi Sector Protect Verify ..............................................23

Hardware Data Protection ...................................................... 23

Low VCC Write Inhibit .....................................................................23

Write Pulse “Glitch” Protection ........................................................23

Logical Inhibit ..................................................................................23

Power-Up Write Inhibit ....................................................................23

Common Flash Memory Interface (CFI). . . . . . . 23

Table 6. CFI Query Identification String ..........................................24

Table 7. System Interface String..................................................... 24

Table 8. Device Geometry Definition ..............................................25

Table 9. Primary Vendor-Specific Extended Query ........................26

Command Definitions . . . . . . . . . . . . . . . . . . . . . 27

Reading Array Data ................................................................ 27

Reset Command ..................................................................... 27

Autoselect Command Sequence ............................................ 27

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 28

Word/Byte Program Command Sequence ............................. 28

Unlock Bypass Command Sequence ..............................................28

Write Buffer Programming ...............................................................28

Accelerated Program ......................................................................29

Figure 4. Write Buffer Programming Operation ...............................30

Figure 5. Program Operation ..........................................................31

Program Suspend/Program Resume Command Sequence ... 31

Figure 6. Program Suspend/Program Resume ...............................32

Chip Erase Command Sequence ........................................... 32

Sector Erase Command Sequence ........................................ 32

Figure 7. Erase Operation ...............................................................33

(VIO) Control ....................................................... 9

Erase Suspend/Erase Resume Commands ........................... 33

Command Definitions ............................................................. 34

Table 10. Command Definitions (x16 Mode, BYTE# = VIH) ........... 34

Table 11. Command Definitions (x8 Mode, BYTE# = V

).............. 35

IL

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 36

DQ7: Data# Polling ................................................................. 36

Figure 8. Data# Polling Algorithm .................................................. 36

RY/BY#: Ready/Busy# ............................................................ 37

DQ6: Toggle Bit I .................................................................... 37

Figure 9. Toggle Bit Algorithm ........................................................ 38

DQ2: Toggle Bit II ................................................................... 38

Reading Toggle Bits DQ6/DQ2 ............................................... 38

DQ5: Exceeded Timing Limits ................................................39

DQ3: Sector Erase Timer ....................................................... 39

DQ1: Write-to-Buffer Abort ..................................................... 39

Table 12. Write Operation Status................................................... 40

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 41

Figure 10. Maximum Negative Overshoot Waveform ................... 41

Figure 11. Maximum Positive Overshoot Waveform ..................... 41

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 41

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 12. Test Setup .................................................................... 43

Table 13. Test Specifications......................................................... 43

Key to Switching Waveforms. . . . . . . . . . . . . . . . 43

Figure 13. Input Waveforms and Measurement Levels ................. 43

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44

Read-Only Operations ........................................................... 44

Figure 14. Read Operation Timings ............................................... 44

Figure 15. Page Read Timings ...................................................... 45

Hardware Reset (RESET#) .................................................... 46

Figure 16. Reset Timings ............................................................... 46

Erase and Program Operations .............................................. 47

Figure 17. Reset Timings ............................................................... 48

Figure 18. Program Operation Timings .......................................... 49

Figure 19. Accelerated Program Timing Diagram .......................... 49

Figure 20. Chip/Sector Erase Operation Timings .......................... 50

Figure 21. Data# Polling Timings (During Embedded Algorithms) . 51

Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... 52

Figure 23. DQ2 vs. DQ6 ................................................................. 52

Temporary Sector Group Unprotect ....................................... 53

Figure 24. Temporary Sector Group Unprotect Timing Diagram ... 53
Figure 25. Sector Group Protect and Unprotect Timing Diagram .. 54

Alternate CE# Controlled Erase and Program Operations ..... 55

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings .......................................................................... 56

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 56

Erase And Programming Performance. . . . . . . . 57

TSOP Pin and BGA Package Capacitance . . . . . 58

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 59

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline

Package (TSOP) ..................................................................... 59

LAA064—64-Ball Fortified Ball Grid Array

13 x 11 mm Package .............................................................. 60

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61

September 9, 2003 Am29LV128MH/L 3

PRODUCT SELECTOR GUIDE

Part Number Am29LV128MH/L

Regulated Voltage Range

= 3.0–3.6 V

V

Speed/
Voltage
Option

Max. Access Time (ns)

CC

Full Voltage Range
V

= 2.7–3.6 V

CC

DATASHEET

93R

= 3.0–3.6 V

V

IO

90

103R

VIO = 2.7–3.6 V

(Note 2)

= 2.7–3.6 V

V

IO

113R

VIO = 1.65–3.6 V

103

100 110 120

113

(Note 2)

VIO = 1.65–3.6 V

123R

VIO = 1.65–3.6 V

123

(Note 2)

VIO = 1.65–3.6 V

Max. CE# Access Time (ns)

Max. Page access time (t

Max. OE# Access Time (ns)

Notes:

1. See “AC Characteristics” for full specifications.

PAC C

)

90

25

25

2. Contact factory for availability and ordering information.

BLOCK DIAGRAM

RY/ BY#

V

CC

V

SS

RESET#

WE#

WP#/ACC

BYTE#

CE#

OE#

State

Control

Command

Register

PGM Voltage

Generator

100 110 120

30 30 40 30 40

30 30 40 30 40

DQ0

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

V

IO

STB

Logic

–

DQ15 (A-1)

Input/Output

Buffers

Data

Latch

A22–A0

VCC Detector

Timer

STB

Y-Decoder

X-Decoder

Address Latch

Y-Gating

Cell Matrix

4 Am29LV128MH/L September 9, 2003

CONNECTION DIAGRAMS

1

NC

2

A22

3

A15

4

A14

5

A13

6

A12

7

A11

8

A10

9

A9

10

A8

11

A19

12

A20

13

WE#

A21

A18
A17

A7
A6
A5
A4
A3
A2

A1
NC
NC

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

RESET#

WP#/ACC

RY/BY#

DATASHEET

56-Pin Standard TSOP

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

NC
NC
A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V

SS

CE#
A0
NC
V

IO

NC
NC

A16

BYTE#

V

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2
DQ9
DQ1
DQ8
DQ0

OE#

V

CE#

A0
NC
V

SS

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14

56-Pin Reverse TSOP

15
16
17
18
19
20
21
22
23
24
25
26
27
28

IO

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

NC
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC

September 9, 2003 Am29LV128MH/L 5

CONNECTION DIAGRAMS

DATASHEET

64- Ball Fortified BGA

Top View, Balls Facing Down

A8 C8

A7 C7 D7 E7 F7 G7 H7

A6 C6 D6 E6 F6 G6 H6

A5 C5 D5 E5 F5 G5 H5

A4 C4 D4 E4 F4 G4 H4

A3 C3 D3 E3 F3 G3 H3

A2 C2 D2 E2 F2 G2 H2

A1 C1 D1 E1 F1 G1 H1

B8 D8 E8 F8 G8 H8

NC

V

V

NC

B7

B6

B5

B4

B3

B2

B1

NCA22NC

V

IO

SS

NCNCNCNCNC

NCV

V

IO

NC

DQ15/A-1

DQ13 DQ6DQ14DQ7A11A10A8A9

V

CC DQ4DQ12DQ5A19A21RESET#WE#

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE#

NC

SSBYTE#A16A15A14A12A13

SSCE#A0A1A2A4A3

Special Package Handling Instructions

package body is exposed to temperatures above

°C for prolonged periods of time.

150
Special handling is required for Flash Memory products
in molded packages (TSOP and BGA). The package
and/or data integrity may be compromised if the

6 Am29LV128MH/L September 9, 2003

DATASHEET

PIN DESCRIPTION

A22–A0 = 23 Address inputs

DQ14–DQ0 = 15 Data inputs/outputs

DQ15/A-1 = DQ15 (Data input/output, word mode),

A-1 (LSB Address input, byte mode)

CE# = Chip Enable input

OE# = Output Enable input

WE# = Write Enable input

WP#/ACC = Hardware Write Protect input;

Acceleration input

RESET# = Hardware Reset Pin input

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Ready/Busy output

= 3.0 volt-only single power supply

V

CC

= Output Buffer power

V

IO

V

SS

NC = Pin Not Connected Internally

(see Product Selector Guide for
speed options and voltage
supply tolerances)

= Device Ground

LOGIC SYMBOL

23

A22–A0

CE#

OE#

WE#

WP#/ACC

RESET#

V

IO

BYTE#

16 or 8

DQ15–DQ0

(A-1)

RY/BY#

September 9, 2003 Am29LV128MH/L 7

DATASHEET

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Am29LV128MH/L H 123R PC I

TEMPERATURE RANGE

I = Industrial (–40

PAC KA G E TYPE

E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)
F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056)
PC = 64-Ball Fortified Ball Grid Array (

1.0 mm pitch, 13 x 11 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +85°C)

FBGA),

SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = V

IL

H = Uniform sector device, highest address sector protected
L = Uniform sector device, lowest address sector protected

DEVICE NUMBER/DESCRIPTION

Am29LV128MH/L
128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO™ Control,

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package

Am29LV128MH93R
Am29LV128ML93R

Am29LV128MH103R
Am29LV128ML103R

Am29LV128MH113R
Am29LV128ML113R

Am29LV128MH123R
Am29LV128ML123R

Speed

(ns)

90 3.0–3.6 V

100 2.7–3.6 V

EI,

FI

110 1.65–3.6 V

120 1.65–3.6 V

Valid Combinations

V

IO

Range

V

CC

Range

3.0–3.6 V

Valid Combinations for
Fortified BGA Package

Order Number Package Marking

Am29LV128MH93R
Am29LV128ML93R

Am29LV128MH103R
Am29LV128ML103R

Am29LV128MH113R
Am29LV128ML113R

Am29LV128MH123R
Am29LV128ML123R

PCI

L128MH93N
L128ML93N

L128MH103N
L128ML103N

L128MH113N
L128ML113N

L128MH123N
L128ML123N

I

Speed

(ns)

90

100

110

120

V

IO

Range

3.0–

3.6V

2.7–

3.6 V

1.65–

3.6 V

1.65–

3.6 V

V

CC

Range

3.0–

3.6 V

Valid Combinations list configurations planned to be supported in vol­ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re­leased combinations.

Notes:

1. For 100, 110, and 120 speed option shown in product selector guide, contact AMD for availability and ordering information.

2. To select product with ESN factory-locked into the SecSi Sector: 1) select order number from the valid combinations given above, 2) add designator “N” at the

end of the order number, and 3) modify the speed option indicator as follows [103R = 10R, 113R = 11R, 123R = 12R, 93R, 103, 113, 123 = no change].
Example: Am29LV128MH12RPCIN. For Fortified BGA pacakges, modify the speed option indicator as follows: [103N = 10N, 113N = 11N, 123N = 12N, 93N =
no change]. The designator “N” will also appear at the end of the package marking. Example: L128MH12NIN.

)

8 Am29LV128MH/L September 9, 2003

DATASHEET

DEVICE BUS OPERATIONS

This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca­tion. The register is a latch used to store the com­mands, along with the address and data information
needed to execute the command. The contents of the

Table 1. Device Bus Operations

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

DQ8–DQ15

Addresses

Operation CE# OE# WE# RESET# WP# ACC

Read L L H H

Write (Program/Erase) L H L H (Note 3) X A

Accelerated Program L H L H

±

V

Standby

Output Disable L H H H

Reset X X X L

Sector Group Protect
(Note 2)

Sector Group Unprotect
(Note 2)

Temp orary Sector Grou p
Unprotect

CC

0.3 V

XX

LHL V

LHL V

XXX V

V

CC

0.3 V

±

ID

ID

ID

XX

(Note 3) V

HH

XH

XX

XX

HX

HX

HX A

(Note 2)

SA, A6 =L,

A3=L, A2=L,

A1=H, A0=L

SA, A6=H,

A3=L, A2=L,

A1=H, A0=L

DQ0–

DQ7

A

IN

IN

A

IN

X

X

X

D

(Note 4) (Note 4)

(Note 4) (Note 4)

High-Z High-Z High-Z

High-Z High-Z High-Z

High-Z High-Z High-Z

(Note 4) X X

(Note 4) X X

IN

(Note 4) (Note 4) High-Z

OUT

BYTE#

= V

IH

D

OUT

BYTE#

= V

IL

DQ8–DQ14

= High-Z,

DQ15 = A-1

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

A

IN

= Data Out

OUT

Notes:

1. Addresses are A22:A0 in word mode; A22:A-1 in byte mode. Sector addresses are A22:A15 in both modes.

2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the

“Sector Group Protection and Unprotection” section.

3. If WP# = V

, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as

IL

determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped from the factory (The
SecSi Sector may be factory protected depending on version ordered.)

4. D

IN

or D

as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

OUT

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con­figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

VersatileIO™ (VIO) Control

The VersatileIO™ (VIO) control allows the host system

to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage

level that is asserted on V

options on this device.

for V

IO

. See Ordering Information

IO

September 9, 2003 Am29LV128MH/L 9

DATASHEET

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

. CE# is the power

IL

control and selects the device. OE# is the output con­trol and gates array data to the output pins. WE#
should remain at V

.

IH

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com­mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing speci­fications and to Figure 14 for the timing diagram. Refer
to the DC Characteristics table for the active current
specification on reading array data.

Page Mode Read

The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper­ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad­dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.

The random or initial page access is equal to t

and subsequent page read accesses (as long as

t

CE

ACC

or

the locations specified by the microprocessor falls
within that page) is equivalent to t

. When CE# is

PAC C

deasserted and reasserted for a subsequent access,
the access time is t

or tCE. Fast page mode ac-

ACC

cesses are obtained by keeping the “read-page ad­dresses” constant and changing the “intra-read page”
addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

The device features an Unlock Bypass mode to facili­tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re­quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using

, and OE# to VIH.

IL

both standard and Unlock Bypass command se-

quences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies.

Refer to the DC Characteristics table for the active

current specification for the write mode. The AC Char-

acteristics section contains timing specification tables

and timing diagrams for write operations.

Write Buffer

Write Buffer Programming allows the system write to a

maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming

time than the standard programming algorithms. See

“Write Buffer” for more information.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the system asserts V

on this pin, the device auto-

HH

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sector

groups, and uses the higher voltage on the pin to re-

duce the time required for program operations. The

system would use a two-cycle program command se-

quence as required by the Unlock Bypass mode. Re-

moving V

to normal operation.

not be at V

from the WP#/ACC pin returns the device

HH

Note that the WP#/ACC pin must

for operations other than accelerated

HH

programming, or device damage may result. WP# has

an internal pullup; when unconnected, WP# is at V

.

IH

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V

(Note that this is a more restricted voltage range than

± 0.3 V.

IO

10 Am29LV128MH/L September 9, 2003

DATASHEET

VIH.) If CE# and RESET# are held at VIH, but not within

± 0.3 V, the device will be in the standby mode, but

V

IO

the standby current will be greater. The device re­quires standard access time (t

) for read access

CE

when the device is in either of these standby modes,
before it is ready to read data.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

Refer to the DC Characteristics table for the standby
current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en­ergy consumption. The device automatically enables
this mode when addresses remain stable for t

ACC

+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad­dress access timings provide new data when ad­dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re­setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

RP

, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is
ready to accept another command sequence, to en­sure data integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I

but not within VSS±0.3 V, the standby current will

at V

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.

The RESET# pin may be tied to the system reset cir­cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.

September 9, 2003 Am29LV128MH/L 11

DATASHEET

Table 2. Sector Address Table

8-bit

Sector A22–A15

SA0 00000000 64/32 000000–00FFFF 000000–007FFF

SA1 00000001 64/32 010000–01FFFF 008000–00FFFF

SA2 00000010 64/32 020000–02FFFF 010000–017FFF

SA3 00000011 64/32 030000–03FFFF 018000–01FFFF

SA4 00000100 64/32 040000–04FFFF 020000–027FFF

SA5 00000101 64/32 050000–05FFFF 028000–02FFFF

SA6 00000110 64/32 060000–06FFFF 030000–037FFF

SA7 00000111 64/32 070000–07FFFF 038000–03FFFF

SA8 00001000 64/32 080000–08FFFF 040000–047FFF

SA9 00001001 64/32 090000–09FFFF 048000–04FFFF

SA10 00001010 64/32 0A0000–0AFFFF 050000–057FFF

SA11 00001011 64/32 0B0000–0BFFFF 058000–05FFFF

SA12 00001100 64/32 0C0000–0CFFFF 060000–067FFF

SA13 00001101 64/32 0D0000–0DFFFF 068000–06FFFF

SA14 00001110 64/32 0E0000–0EFFFF 070000–077FFF

SA15 00001111 64/32 0F0000–0FFFFF 078000–07FFFF

SA16 00010000 64/32 100000–10FFFF 080000–087FFF

SA17 00010001 64/32 110000–11FFFF 088000–08FFFF

SA18 00010010 64/32 120000–12FFFF 090000–097FFF

SA19 00010011 64/32 130000–13FFFF 098000–09FFFF

SA20 00010100 64/32 140000–14FFFF 0A0000–0A7FFF

SA21 00010101 64/32 150000–15FFFF 0A8000–0AFFFF

SA22 00010110 64/32 160000–16FFFF 0B0000–0B7FFF

SA23 00010111 64/32 170000–17FFFF 0B8000–0BFFFF

SA24 00011000 64/32 180000–18FFFF 0C0000–0C7FFF

SA25 00011001 64/32 190000–19FFFF 0C8000–0CFFFF

SA26 00011010 64/32 1A0000–1AFFFF 0D0000–0D7FFF

SA27 00011011 64/32 1B0000–1BFFFF 0D8000–0DFFFF

SA28 00011100 64/32 1C0000–1CFFFF 0E0000–0E7FFF

SA29 00011101 64/32 1D0000–1DFFFF 0E8000–0EFFFF

SA30 00011110 64/32 1E0000–1EFFFF 0F0000–0F7FFF

SA31 00011111 64/32 1F0000–1FFFFF 0F8000–0FFFFF

SA32 00100000 64/32 200000–20FFFF 100000–107FFF

SA33 00100001 64/32 210000–21FFFF 108000–10FFFF

SA34 00100010 64/32 220000–22FFFF 110000–117FFF

SA35 00100011 64/32 230000–23FFFF 118000–11FFFF

SA36 00100100 64/32 240000–24FFFF 120000–127FFF

SA37 00100101 64/32 250000–25FFFF 128000–12FFFF

SA38 00100110 64/32 260000–26FFFF 130000–137FFF

SA39 00100111 64/32 270000–27FFFF 138000–13FFFF

SA40 00101000 64/32 280000–28FFFF 140000–147FFF

SA41 00101001 64/32 290000–29FFFF 148000–14FFFF

SA42 00101010 64/32 2A0000–2AFFFF 150000–157FFF

SA43 00101011 64/32 2B0000–2BFFFF 158000–15FFFF

SA44 00101100 64/32 2C0000–2CFFFF 160000–167FFF

SA45 00101101 64/32 2D0000–2DFFFF 168000–16FFFF

SA46 00101110 64/32 2E0000–2EFFFF 170000–177FFF

Sector Size

(Kbytes/Kwords)

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

12 Am29LV128MH/L September 9, 2003

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA47 00101111 64/32 2F0000–2FFFFF 178000–17FFFF

SA48 00110000 64/32 300000–30FFFF 180000–187FFF

SA49 00110001 64/32 310000–31FFFF 188000–18FFFF

SA50 00110010 64/32 320000–32FFFF 190000–197FFF

SA51 00110011 64/32 330000–33FFFF 198000–19FFFF

SA52 00110100 64/32 340000–34FFFF 1A0000–1A7FFF

SA53 00110101 64/32 350000–35FFFF 1A8000–1AFFFF

SA54 00110110 64/32 360000–36FFFF 1B0000–1B7FFF

SA55 00110111 64/32 370000–37FFFF 1B8000–1BFFFF

SA56 00111000 64/32 380000–38FFFF 1C0000–1C7FFF

SA57 00111001 64/32 390000–39FFFF 1C8000–1CFFFF

SA58 00111010 64/32 3A0000–3AFFFF 1D0000–1D7FFF

SA59 00111011 64/32 3B0000–3BFFFF 1D8000–1DFFFF

SA60 00111100 64/32 3C0000–3CFFFF 1E0000–1E7FFF

SA61 00111101 64/32 3D0000–3DFFFF 1E8000–1EFFFF

SA62 00111110 64/32 3E0000–3EFFFF 1F0000–1F7FFF

SA63 00111111 64/32 3F0000–3FFFFF 1F8000–1FFFFF

SA64 01000000 64/32 400000–40FFFF 200000–207FFF

SA65 01000001 64/32 410000–41FFFF 208000–20FFFF

SA66 01000010 64/32 420000–42FFFF 210000–217FFF

SA67 01000011 64/32 430000–43FFFF 218000–21FFFF

SA68 01000100 64/32 440000–44FFFF 220000–227FFF

SA69 01000101 64/32 450000–45FFFF 228000–22FFFF

SA70 01000110 64/32 460000–46FFFF 230000–237FFF

SA71 01000111 64/32 470000–47FFFF 238000–23FFFF

SA72 01001000 64/32 480000–48FFFF 240000–247FFF

SA73 01001001 64/32 490000–49FFFF 248000–24FFFF

SA74 01001010 64/32 4A0000–4AFFFF 250000–257FFF

SA75 01001011 64/32 4B0000–4BFFFF 258000–25FFFF

SA76 01001100 64/32 4C0000–4CFFFF 260000–267FFF

SA77 01001101 64/32 4D0000–4DFFFF 268000–26FFFF

SA78 01001110 64/32 4E0000–4EFFFF 270000–277FFF

SA79 01001111 64/32 4F0000–4FFFFF 278000–27FFFF

SA80 01010000 64/32 500000–50FFFF 280000–287FFF

SA81 01010001 64/32 510000–51FFFF 288000–28FFFF

SA82 01010010 64/32 520000–52FFFF 290000–297FFF

SA83 01010011 64/32 530000–53FFFF 298000–29FFFF

SA84 01010100 64/32 540000–54FFFF 2A0000–2A7FFF

SA85 01010101 64/32 550000–55FFFF 2A8000–2AFFFF

SA86 01010110 64/32 560000–56FFFF 2B0000–2B7FFF

SA87 01010111 64/32 570000–57FFFF 2B8000–2BFFFF

SA88 01011000 64/32 580000–58FFFF 2C0000–2C7FFF

SA89 01011001 64/32 590000–59FFFF 2C8000–2CFFFF

SA90 01011010 64/32 5A0000–5AFFFF 2D0000–2D7FFF

SA91 01011011 64/32 5B0000–5BFFFF 2D8000–2DFFFF

SA92 01011100 64/32 5C0000–5CFFFF 2E0000–2E7FFF

SA93 01011101 64/32 5D0000–5DFFFF 2E8000–2EFFFF

SA94 01011110 64/32 5E0000–5EFFFF 2F0000–2F7FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

September 9, 2003 Am29LV128MH/L 13

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA95 01011111 64/32 5F0000–5FFFFF 2F8000–2FFFFF

SA96 01100000 64/32 600000–60FFFF 300000–307FFF

SA97 01100001 64/32 610000–61FFFF 308000–30FFFF

SA98 01100010 64/32 620000–62FFFF 310000–317FFF

SA99 01100011 64/32 630000–63FFFF 318000–31FFFF

SA100 01100100 64/32 640000–64FFFF 320000–327FFF

SA101 01100101 64/32 650000–65FFFF 328000–32FFFF

SA102 01100110 64/32 660000–66FFFF 330000–337FFF

SA103 01100111 64/32 670000–67FFFF 338000–33FFFF

SA104 01101000 64/32 680000–68FFFF 340000–347FFF

SA105 01101001 64/32 690000–69FFFF 348000–34FFFF

SA106 01101010 64/32 6A0000–6AFFFF 350000–357FFF

SA107 01101011 64/32 6B0000–6BFFFF 358000–35FFFF

SA108 01101100 64/32 6C0000–6CFFFF 360000–367FFF

SA109 01101101 64/32 6D0000–6DFFFF 368000–36FFFF

SA110 01101110 64/32 6E0000–6EFFFF 370000–377FFF

SA111 01101111 64/32 6F0000–6FFFFF 378000–37FFFF

SA112 01110000 64/32 700000–70FFFF 380000–387FFF

SA113 01110001 64/32 710000–71FFFF 388000–38FFFF

SA114 01110010 64/32 720000–72FFFF 390000–397FFF

SA115 01110011 64/32 730000–73FFFF 398000–39FFFF

SA116 01110100 64/32 740000–74FFFF 3A0000–3A7FFF

SA117 01110101 64/32 750000–75FFFF 3A8000–3AFFFF

SA118 01110110 64/32 760000–76FFFF 3B0000–3B7FFF

SA119 01110111 64/32 770000–77FFFF 3B8000–3BFFFF

SA120 01111000 64/32 780000–78FFFF 3C0000–3C7FFF

SA121 01111001 64/32 790000–79FFFF 3C8000–3CFFFF

SA122 01111010 64/32 7A0000–7AFFFF 3D0000–3D7FFF

SA123 01111011 64/32 7B0000–7BFFFF 3D8000–3DFFFF

SA124 01111100 64/32 7C0000–7CFFFF 3E0000–3E7FFF

SA125 01111101 64/32 7D0000–7DFFFF 3E8000–3EFFFF

SA126 01111110 64/32 7E0000–7EFFFF 3F0000–3F7FFF

SA127 01111111 64/32 7F0000–7FFFFF 3F8000–3FFFFF

SA128 10000000 64/32 800000–80FFFF 400000–407FFF

SA129 10000001 64/32 810000–81FFFF 408000–40FFFF

SA130 10000010 64/32 820000–82FFFF 410000–417FFF

SA131 10000011 64/32 830000–83FFFF 418000–41FFFF

SA132 10000100 64/32 840000–84FFFF 420000–427FFF

SA133 10000101 64/32 850000–85FFFF 428000–42FFFF

SA134 10000110 64/32 860000–86FFFF 430000–437FFF

SA135 10000111 64/32 870000–87FFFF 438000–43FFFF

SA136 10001000 64/32 880000–88FFFF 440000–447FFF

SA137 10001001 64/32 890000–89FFFF 448000–44FFFF

SA138 10001010 64/32 8A0000–8AFFFF 450000–457FFF

SA139 10001011 64/32 8B0000–8BFFFF 458000–45FFFF

SA140 10001100 64/32 8C0000–8CFFFF 460000–467FFF

SA141 10001101 64/32 8D0000–8DFFFF 468000–46FFFF

SA142 10001110 64/32 8E0000–8EFFFF 470000–477FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

14 Am29LV128MH/L September 9, 2003

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA143 10001111 64/32 8F0000–8FFFFF 478000–47FFFF

SA144 10010000 64/32 900000–90FFFF 480000–487FFF

SA145 10010001 64/32 910000–91FFFF 488000–48FFFF

SA146 10010010 64/32 920000–92FFFF 490000–497FFF

SA147 10010011 64/32 930000–93FFFF 498000–49FFFF

SA148 10010100 64/32 940000–94FFFF 4A0000–4A7FFF

SA149 10010101 64/32 950000–95FFFF 4A8000–4AFFFF

SA150 10010110 64/32 960000–96FFFF 4B0000–4B7FFF

SA151 10010111 64/32 970000–97FFFF 4B8000–4BFFFF

SA152 10011000 64/32 980000–98FFFF 4C0000–4C7FFF

SA153 10011001 64/32 990000–99FFFF 4C8000–4CFFFF

SA154 10011010 64/32 9A0000–9AFFFF 4D0000–4D7FFF

SA155 10011011 64/32 9B0000–9BFFFF 4D8000–4DFFFF

SA156 10011100 64/32 9C0000–9CFFFF 4E0000–4E7FFF

SA157 10011101 64/32 9D0000–9DFFFF 4E8000–4EFFFF

SA158 10011110 64/32 9E0000–9EFFFF 4F0000–4F7FFF

SA159 10011111 64/32 9F0000–9FFFFF 4F8000–4FFFFF

SA160 10100000 64/32 A00000–A0FFFF 500000–507FFF

SA161 10100001 64/32 A10000–A1FFFF 508000–50FFFF

SA162 10100010 64/32 A20000–A2FFFF 510000–517FFF

SA163 10100011 64/32 A30000–A3FFFF 518000–51FFFF

SA164 10100100 64/32 A40000–A4FFFF 520000–527FFF

SA165 10100101 64/32 A50000–A5FFFF 528000–52FFFF

SA166 10100110 64/32 A60000–A6FFFF 530000–537FFF

SA167 10100111 64/32 A70000–A7FFFF 538000–53FFFF

SA168 10101000 64/32 A80000–A8FFFF 540000–547FFF

SA169 10101001 64/32 A90000–A9FFFF 548000–54FFFF

SA170 10101010 64/32 AA0000–AAFFFF 550000–557FFF

SA171 10101011 64/32 AB0000–ABFFFF 558000–55FFFF

SA172 10101100 64/32 AC0000–ACFFFF 560000–567FFF

SA173 10101101 64/32 AD0000–ADFFFF 568000–56FFFF

SA174 10101110 64/32 AE0000–AEFFFF 570000–577FFF

SA175 10101111 64/32 AF0000–AFFFFF 578000–57FFFF

SA176 10110000 64/32 B00000–B0FFFF 580000–587FFF

SA177 10110001 64/32 B10000–B1FFFF 588000–58FFFF

SA178 10110010 64/32 B20000–B2FFFF 590000–597FFF

SA179 10110011 64/32 B30000–B3FFFF 598000–59FFFF

SA180 10110100 64/32 B40000–B4FFFF 5A0000–5A7FFF

SA181 10110101 64/32 B50000–B5FFFF 5A8000–5AFFFF

SA182 10110110 64/32 B60000–B6FFFF 5B0000–5B7FFF

SA183 10110111 64/32 B70000–B7FFFF 5B8000–5BFFFF

SA184 10111000 64/32 B80000–B8FFFF 5C0000–5C7FFF

SA185 10111001 64/32 B90000–B9FFFF 5C8000–5CFFFF

SA186 10111010 64/32 BA0000–BAFFFF 5D0000–5D7FFF

SA187 10111011 64/32 BB0000–BBFFFF 5D8000–5DFFFF

SA188 10111100 64/32 BC0000–BCFFFF 5E0000–5E7FFF

SA189 10111101 64/32 BD0000–BDFFFF 5E8000–5EFFFF

SA190 10111110 64/32 BE0000–BEFFFF 5F0000–5F7FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

September 9, 2003 Am29LV128MH/L 15

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA191 10111111 64/32 BF0000–BFFFFF 5F8000–5FFFFF

SA192 11000000 64/32 C00000–C0FFFF 600000–607FFF

SA193 11000001 64/32 C10000–C1FFFF 608000–60FFFF

SA194 11000010 64/32 C20000–C2FFFF 610000–617FFF

SA195 11000011 64/32 C30000–C3FFFF 618000–61FFFF

SA196 11000100 64/32 C40000–C4FFFF 620000–627FFF

SA197 11000101 64/32 C50000–C5FFFF 628000–62FFFF

SA198 11000110 64/32 C60000–C6FFFF 630000–637FFF

SA199 11000111 64/32 C70000–C7FFFF 638000–63FFFF

SA200 11001000 64/32 C80000–C8FFFF 640000–647FFF

SA201 11001001 64/32 C90000–C9FFFF 648000–64FFFF

SA202 11001010 64/32 CA0000–CAFFFF 650000–657FFF

SA203 11001011 64/32 CB0000–CBFFFF 658000–65FFFF

SA204 11001100 64/32 CC0000–CCFFFF 660000–667FFF

SA205 11001101 64/32 CD0000–CDFFFF 668000–66FFFF

SA206 11001110 64/32 CE0000–CEFFFF 670000–677FFF

SA207 11001111 64/32 CF0000–CFFFFF 678000–67FFFF

SA208 11010000 64/32 D00000–D0FFFF 680000–687FFF

SA209 11010001 64/32 D10000–D1FFFF 688000–68FFFF

SA210 11010010 64/32 D20000–D2FFFF 690000–697FFF

SA211 11010011 64/32 D30000–D3FFFF 698000–69FFFF

SA212 11010100 64/32 D40000–D4FFFF 6A0000–6A7FFF

SA213 11010101 64/32 D50000–D5FFFF 6A8000–6AFFFF

SA214 11010110 64/32 D60000–D6FFFF 6B0000–6B7FFF

SA215 11010111 64/32 D70000–D7FFFF 6B8000–6BFFFF

SA216 11011000 64/32 D80000–D8FFFF 6C0000–6C7FFF

SA217 11011001 64/32 D90000–D9FFFF 6C8000–6CFFFF

SA218 11011010 64/32 DA0000–DAFFFF 6D0000–6D7FFF

SA219 11011011 64/32 DB0000–DBFFFF 6D8000–6DFFFF

SA220 11011100 64/32 DC0000–DCFFFF 6E0000–6E7FFF

SA221 11011101 64/32 DD0000–DDFFFF 6E8000–6EFFFF

SA222 11011110 64/32 DE0000–DEFFFF 6F0000–6F7FFF

SA223 11011111 64/32 DF0000–DFFFFF 6F8000–6FFFFF

SA224 11100000 64/32 E00000–E0FFFF 700000–707FFF

SA225 11100001 64/32 E10000–E1FFFF 708000–70FFFF

SA226 11100010 64/32 E20000–E2FFFF 710000–717FFF

SA227 11100011 64/32 E30000–E3FFFF 718000–71FFFF

SA228 11100100 64/32 E40000–E4FFFF 720000–727FFF

SA229 11100101 64/32 E50000–E5FFFF 728000–72FFFF

SA230 11100110 64/32 E60000–E6FFFF 730000–737FFF

SA231 11100111 64/32 E70000–E7FFFF 738000–73FFFF

SA232 11101000 64/32 E80000–E8FFFF 740000–747FFF

SA233 11101001 64/32 E90000–E9FFFF 748000–74FFFF

SA234 11101010 64/32 EA0000–EAFFFF 750000–757FFF

SA235 11101011 64/32 EB0000–EBFFFF 758000–75FFFF

SA236 11101100 64/32 EC0000–ECFFFF 760000–767FFF

SA237 11101101 64/32 ED0000–EDFFFF 768000–76FFFF

SA238 11101110 64/32 EE0000–EEFFFF 770000–777FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

16 Am29LV128MH/L September 9, 2003

DATASHEET

Table 2. Sector Address Table (Continued)

Sector A22–A15

SA239 11101111 64/32 EF0000–EFFFFF 778000–77FFFF

SA240 11110000 64/32 F00000–F0FFFF 780000–787FFF

SA241 11110001 64/32 F10000–F1FFFF 788000–78FFFF

SA242 11110010 64/32 F20000–F2FFFF 790000–797FFF

SA243 11110011 64/32 F30000–F3FFFF 798000–79FFFF

SA244 11110100 64/32 F40000–F4FFFF 7A0000–7A7FFF

SA245 11110101 64/32 F50000–F5FFFF 7A8000–7AFFFF

SA246 11110110 64/32 F60000–F6FFFF 7B0000–7B7FFF

SA247 11110111 64/32 F70000–F7FFFF 7B8000–7BFFFF

SA248 11111000 64/32 F80000–F8FFFF 7C0000–7C7FFF

SA249 11111001 64/32 F90000–F9FFFF 7C8000–7CFFFF

SA250 11111010 64/32 FA0000–FAFFFF 7D0000–7D7FFF

SA251 11111011 64/32 FB0000–FBFFFF 7D8000–7DFFFF

SA252 11111100 64/32 FC0000–FCFFFF 7E0000–7E7FFF

SA253 11111101 64/32 FD0000–FDFFFF 7E8000–7EFFFF

SA254 11111110 64/32 FE0000–FEFFFF 7F0000–7F7FFF

SA255 11111111 64/32 FF0000–FFFFFF 7F8000–7FFFFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

September 9, 2003 Am29LV128MH/L 17

DATASHEET

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector group protection verifica­tion, through identifier codes output on DQ7–DQ0.
This mode is primarily intended for programming
equipment to automatically match a device to be pro­grammed with its corresponding programming algo­rithm. However, the autoselect codes can also be
accessed in-system through the command register.

When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A3, A2, A1, and A0 must be as shown in Table 3.

In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits (see Table 2). Table 3 shows the remain­ing address bits that are don’t care. When all neces­sary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Tables 10 and 11. This
method does not require V

. Refer to the Autoselect

ID

Command Sequence section for more information.

Table 3. Autoselect Codes, (High Voltage Method)

A22

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X

Cycle 1

Cycle 2 H H L 22 X 12h

Device ID

Cycle 3 H H H 22 X 00h

Sector Group
Protection Verification

SecSi Sector Indicator
Bit (DQ7), WP#
protects highest
address sector

SecSi Sector Indicator
Bit (DQ7), WP#
protects lowest
address sector

LLHXX

LLHSAX

LLHXX

LLHXX

to

A15

A14

to

A9A8toA7A6A5to

A10

V

ID

V

ID

V

ID

V

ID

V

ID

X L X L L L 00 X 01h

XL X

XL X L H L X X

XL X L H H X X

XL X L H H X X

A3

toA2A1 A0

A4

LLH 22 X 7Eh

DQ8 to DQ15

BYTE#

= V

BYTE#

IH

= V

DQ7 to DQ0

IL

01h (protected),

00h (unprotected)

98h (factory locked),

18h (not factory locked)

88h (factory locked),

08h (not factory locked)

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

18 Am29LV128MH/L September 9, 2003