FUJITSU Am29F016D Service Manual

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the docu ment is ma rked with the name o f the comp any that o rig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Am29F016D

Data Sheet

Publication Number 21444 Revision E Amendment +2 Issue Date March 23, 2001

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be revised by subsequent versions or modificat ions due to changes in technical specif ic ations.

Publication# 21444 Rev: E Amendment/+2

Issue Date: March 23, 2001

Am29F016D

16 Megabit (2 M x 8-Bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 V

10%, single power supply operation

— Minimizes system level power requirements

■ Manufactured on 0.23 µm process technology

— Compatible with 0.5 µm Am29F016 and 0.32 µm

Am29F016B devices

■ High performance

— Access times as fast as 70 ns

■ Low power consumption

— 25 mA typical active read current

— 30 mA typical program/erase current

— 1 µA typical standby current (standard access

time to active mode)

■ Flexible sector arc hitecture

— 32 uniform sectors of 64 Kbytes each

— Any combination of sectors can be erased

— Supports full chip erase

— Group sector protection:

A hardware method of locking sector groups to

prevent any program or erase operations within

that sector group

Temporary Sector Group Unprotect allows code

changes in previously locked sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■ Unlock Bypass Program Command

— Reduces overall prog ramming time when issuing

multiple program command sequences

■ Minimum 1,000,000 program/erase cycles per

sector guaranteed

■ 20-year data retention at 125

— Reliable operation for the life of the system

■ Package options

— 48-pin and 40-pin TSOP

— 44-pin SO

— Known Good Die (KGD)

(see publication number 21551)

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detect ing program

or erase cycle completion

■ Ready/Busy# output (RY/ BY#)

— Provides a hardware method for detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends a sector erase operation to read data

from, or program data to, a non-erasing sector,

then resumes the erase operation

■ Hardware reset pin (RESET#)

— Resets internal state machine to the read mode

2 Am29F016D

GENERAL DESCRIPTION

The Am29F016D is a 16 Mbit, 5.0 volt-only Flash mem-

ory organized as 2,09 7,152 bytes. The 8 bits of data

appear on DQ0–DQ7. The Am29F016D is offered in

48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.

The device is also available in Known Good Die ( KGD)

form. For more information, refer to publication number

21551. This device is desi gned to be programmed

in-system with the standard system 5.0 v olt V

supply .

A 12.0 volt V

is not required for program or erase

operations. The device can also be programmed in

standard EPROM programmers.

This device is manufactured using AMD’s 0.23 µm pro-

cess technology, and offers all the features and bene-

fits of the Am29F016, which was manufactured using

0.5 µm process technology.

The standard device off ers access t imes of 70, 90, 120,

and 150 ns, allowing high-speed microprocessors to

operate without wait s tates. To eliminate bus conten-

tion, the device has separate chip enable (CE#), write

enable (WE#), and output enable (OE#) controls.

The device requires only a single 5. 0 v o lt po wer sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microproc essor write timing s. Register contents

serve as input to an internal sta te-machine that co n-

trols the erase and programming circuit ry. Write cycles

also internally latch addresses and data needed f or the

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an in ternal algorithm that auto matically

preprograms the arra y (if it is not already progr ammed)

before e xecuting the er ase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a prog ram or erase cycle has

been completed, the device is ready to read array data

or accept another command.

The sector erase archite cture allo ws m emory sect ors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory . This can be achie v ed via prog ramming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pi n terminates any operation

in progress and resets the internal state machine to

reading array dat a. The RESET# pin ma y be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The system can place the device into the standby

mode. Power consumption is greatly reduced in

this mode.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bi t s w i th i n a

s ect or simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

Am29F016D 3

TABLE OF CONTENTS

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Am29F016D Device Bus Operations.................................. 9

Requirements for Reading Array Data....................... .............. 9

Writing Commands/Command Sequences .................... .. ........ 9

Program and Erase Operation Status .................................... 10

Standby Mode ................... ......................................... ............ 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode.............................................................. 10

Table 2. Sector Address Table........................................................ 11

Autoselect Mode..................................................................... 12

Table 3. Am29F016D Autoselect Codes (High Voltage Method).... 12

Sector Group Protection/Unprot ection................... ................. 12

Table 4. Sector Group Addresses................................................... 12

Temporary Sector Group Unprotect ....................................... 12

Figure 1. Temporary Sector Group Unprotect Operation................ 13

Hardware Data Protection...................................................... 13

Low V

Write Inhibit...................................................................... 13

Write Pulse “Glitch” Protection........................................................ 13

Logical Inhibit. . ......... ...... ... ..... ......... ....... ....... .... ..... ....... ......... ....... .. 13

Power-Up Write Inhibit.................................................................... 13

Common Flash Memory Interface (CFI). . . . . . . 14

Table 5. CFI Query Identification String.......................................... 14

Table 6. System Interface String..................................................... 14

Table 7. Device Geometry Definition.............................................. 15

Table 8. Primary Vendor-Specific Extended Query ........................ 15

Command Definitions . . . . . . . . . . . . . . . . . . . . . 16

Reading Array Data.................... ................. ................. .......... 16

Reset Command..................................................................... 16

Autoselect Command Sequence............. ............................... 16

Byte Program Command Sequence....................................... 16

Unlock Bypass Command Sequence.............................................. 17

Figure 2. Program Operation.......................................................... 17

Chip Erase Command Sequence........................................... 17

Sector Erase Command Sequence........................................ 18

Erase Suspend/Erase Resume Commands........................... 18

Figure 3. Erase Operation............................................................... 19

Command Definitions ............................................................. 20

Table 9. Am29F016D Command Definitions................................... 20

Write Operation Status . . . . . . . . . . . . . . . . . . . . 21

DQ7: Data# Polling................................................................. 21

Figure 4. Data# Polling Algorithm ................................................... 21

RY/BY#: Ready/Busy# ........................................................... 22

DQ6: Toggle Bit I.................................................................... 22

DQ2: Toggle Bit II ................................................................... 22

Reading Toggle Bits DQ6/DQ2 .............................................. 22

DQ5: Exceeded Timing Limits................................................ 23

DQ3: Sector Erase Timer ....................................................... 23

Figure 5. Toggle Bit Algorithm........................................................ 23

Table 10. Write Operation Status................................................... 24

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25

Figure 6. Maximum Negative Overshoot Waveform...................... 25

Figure 7. Maximum Positive Overshoot Waveform........................ 25

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 25

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

TTL/NMOS Compatible .......................................................... 26

CMOS Compatible.................................................................. 26

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8. Test Setup...................................................................... 27

Table 11. Test Specifications......................................................... 27

Key to Switching Waveforms. . . . . . . . . . . . . . . . 27

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Read-only Operations............................................................. 28

Figure 9. Read Operation Timings................................................. 28

Figure 10. RESET# Timings.......................................................... 29

Erase/Program Operations..................................................... 30

Figure 11. Program Operation Timings.......................................... 31

Figure 12. Chip/Sector Erase Operation Timings .......................... 32

Figure 13. Data# Polling Timings (During Embedded Algorithms). 33

Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... 33

Figure 15. DQ2 vs. DQ6................................................................. 34

Figure 16. Temporary Sector Group Unprotect Timings................ 34

Erase and Program Operations............ ................. ................. 35

Alternate CE# Controlled Writes.................................................... 35

Figure 17. Alternate CE# Controlled Write Operation Timings ...... 36

Erase and Programming Performance . . . . . . . 37

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 37

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 37

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38

TS 040—40-Pin Standard Thin Small Outline Package......... 38

TSR040—40-Pin Reverse Thin Small Outline Package......... 39

TS 048—48-Pin Standard Thin Small Outline Package......... 40

TSR048—48-Pin Reverse Thin Small Outline Package......... 41

SO 044—44-Pin Small Outline Package................................ 42

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43

Revision A (May 1997) .............. ............................................. 43

Revision B (January 1998) ..................................................... 43

Revision B+1 (January 1998)........................... .. ................. .. . 43

Revision B+2 (April 1998)....................................................... 43

Revision C (January 1999)......................................... ............ 43

Revision C+1 (March 23, 1999).............................................. 43

Revision C+2 (May 17, 1999)................................................. 43

Revision C+3 (July 2, 1999) ................................................... 43

Revision D (November 16, 1999) ........................................... 43

Revision E (May 19, 2000) ..................................................... 44

Revision E+1 (December 4, 2000) ......................................... 44

Revision E+2 (March 23, 2001).............. ............. ................... 44

4 Am29F016D

PRODUCT SELECTOR GUIDE

Note: See the AC Characteristics section for more information.

BLOCK DIAGRAM

Family Part Number Am29F016D

Speed Options (V

= 5.0 V

10%) -70 -90 -120 -150

Max Access Time (ns) 70 90 120 150

CE# Access (ns) 70 90 120 150

OE# Access (ns) 40 40 50 75

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

Detector

State

Control

Command

WE#

CE#

OE#

STB

DQ0

–

DQ7

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A20

Am29F016D 5

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for

more information.

A19

A18

A17

A16

A15

A14

A13

A12

CE#

RESET#

A11

A10

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

40-Pin Standard TSOP

A19

A18

A17

A16

A15

A14

A13

A12

CE#

RESET#

A11

A10

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

40-Pin Reverse TSOP

6 Am29F016D

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for

more information.

A19

A18

A17

A16

A15

A14

A13

A12

CE#

RESET#

A11

A10

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

48-Pin Standard TSOP

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

A19

A18

A17

A16

A15

A14

A13

A12

CE#

RESET#

A11

A10

48-Pin Reverse TSOP

Am29F016D 7

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for

more information.

PIN CONFIGURATION

A0–A20 = 21 Addresses

DQ0–DQ7 = 8 Data Inputs/Outputs

CE# = Chip Enable

WE# = Write Enable

OE# = Output Enable

RESET# = Hardware Reset Pin, Active Low

RY/BY# = Ready/Busy Output

= +5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply tolerances)

= Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

RESET#

A11

A10

DQ0

DQ1

DQ2

DQ3

CE#

A12

A13

A14

A15

A16

A17

A18

A19

A20

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

DQ0–DQ7

A0–A20

CE#

OE#

WE#

RESET# RY/BY#

8 Am29F016D

ORDERING INFORMATION

Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume f or this device. Consult the local AMD sales

office to confirm av ailability of specific valid combinations and

to check on newly released combinations.

Am29F016D -70 E I

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40

°C to +85°C)

E = Extended (–55

°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)

E4 = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040)

F4 = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040)

S = 44-Pin Small Outline Package (SO 044)

This device is also available in Known Good Die (KGD) form. See publication number

21551 for more information.

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29F016D

16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory

5.0 V Read, Program, and Erase

Valid Combinations

AM29F016D-70

EC, EI, FC, FI,

E4C, E4I, F4C, F4I, SC, SI

AM29F016D-90

EC, EI, EE, FC, FI, FE,

E4C, E4I, E4E, F4C, F4I,

F4E, SC, SI, SE

AM29F016D-120

AM29F016D-150

Am29F016D 9

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal c ommand register. The command register it-

self does not occupy any addressable memory loca-

tion. The register is composed of l atches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control le vels requ ired, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29F016D Device Bus Operations

Legend:

L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5 V, X = Don’t Care, D

= Data In, D

OUT

= Data Out, A

= Address In

Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V

. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

main at V

The internal state machin e is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

command is necessar y in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs

produce valid data on the device data outputs. The

device remains enabled for read access until the

command register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

the timing waveforms. I

CC1

in the DC Characteristics

table represents the active current specification for

reading array data.

Writing Commands/Command Sequences

To wr ite a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V

, and OE# to V

An erase operation can erase one sect or, multiple sec-

tors, or the entire de vice. The Sector Address Tables in-

dicate the address space that each sector occupies. A

“sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the en-

tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

CC2

in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Operation CE# OE# WE# RESET# A0–A20 DQ0–DQ7

Read L L H H A

OUT

Write L H L H A

CMOS Standby V

± 0.5 V X X V

± 0.5 V X High-Z

TTL Standby H X X H X High-Z

Output Disable L H H H X High-Z

Hardware Reset X X X L X High-Z

Temporary Sector Unprotect

(See Note)

XXX V

10 Am29F016D

Program and Erase Operation Status

During an erase or program operation, the system ma y

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,

it can place the device in the standby mode. In this

mode, current consumption is great ly reduc ed, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when CE#

and RESET# pins are both held at V

± 0.5 V. (Note

that this is a more restrict ed voltage range than V

The device enters the TTL standby mode when CE#

and RESET# pins are both held at V

. The device re-

quires standard access time (t

) for read access when

the device is in either of these standb y modes, bef ore it

is ready to read data.

The device also enters the standb y mode when the RE-

SET# pin is driven low. Refer to the next section, “RE-

SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Charac teristics tables, I

CC3

represents the

standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of reset-

ting the device to readi ng arr ay data. When the system

drives the RESET# pin low for at least a period of t

the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration o f the RESET#

pulse. The device also resets the inter nal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is ready

to accept another command sequence, to ensure data

integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V

, the device enters

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode .

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operatio n is complete, which requires a

time of t

READY

(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t

READY

(not during Embe dded Algo-

rithms). The system can read data t

after the RE-

SET# pin returns to V

Refer to the AC Characteristics tables for RESET# pa-

rameters and timing diagram.

Output Disable Mode

When the OE# input is at V

, output from the device is

disabled. The output pins are placed in t he high imped-

ance state.

Am29F016D 11

Table 2. Sector Address Table

Note: All sectors are 64 Kbytes in size.

Sector A20 A19 A18 A17 A16 Address Range

SA0 0 0 0 0 0 000000h-00FFFFh

SA1 0 0 0 0 1 010000h-01FFFFh

SA2 0 0 0 1 0 020000h-02FFFFh

SA3 0 0 0 1 1 030000h-03FFFFh

SA4 0 0 1 0 0 040000h-04FFFFh

SA5 0 0 1 0 1 050000h-05FFFFh

SA6 0 0 1 1 0 060000h-06FFFFh

SA7 0 0 1 1 1 070000h-07FFFFh

SA8 0 1 0 0 0 080000h-08FFFFh

SA9 0 1 0 0 1 090000h-09FFFFh

SA10 0 1 0 1 0 0A0000h-0AFFFFh

SA11 0 1 0 1 1 0B0000h-0BFFFFh

SA12 0 1 1 0 0 0C0000h-0CFFFFh

SA13 0 1 1 0 1 0D0000h-0DFFFFh

SA14 0 1 1 1 0 0E0000h-0EFFFFh

SA15 0 1 1 1 1 0F0000h-0FFFFFh

SA16 1 0 0 0 0 100000h-10FFFFh

SA17 1 0 0 0 1 110000h-11FFFFh

SA18 1 0 0 1 0 120000h-12FFFFh

SA19 1 0 0 1 1 130000h-13FFFFh

SA20 1 0 1 0 0 140000h-14FFFFh

SA21 1 0 1 0 1 150000h-15FFFFh

SA22 1 0 1 1 0 160000h-16FFFFh

SA23 1 0 1 1 1 170000h-17FFFFh

SA24 1 1 0 0 0 180000h-18FFFFh

SA25 1 1 0 0 1 190000h-19FFFFh

SA26 1 1 0 1 0 1A0000h-1AFFFFh

SA27 1 1 0 1 1 1B0000h-1BFFFFh

SA28 1 1 1 0 0 1C0000h-1CFFFFh

SA29 1 1 1 0 1 1D0000h-1DFFFFh

SA30 1 1 1 1 0 1E0000h-1EFFFFh

SA31 1 1 1 1 1 1F0000h-1FFFFFh

12 Am29F016D

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for progr amming equipment

to automatically match a device to be progr ammed with

its correspondi ng programming al gorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

When using programming equipment, the autoselect

mode requires V

(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Autoselect Codes (High Voltage Method) table. In addi-

tion, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order

address bits. Refer to the corresponding Sector Ad-

dress Tables. The Command Definitions ta ble shows

the remaining address bits that are don’t c are. When all

necessary bits have been set as required, the program-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

tions table. This method does not require V

. See

“Command Definitions” for details on using the autose-

lect mode.

Table 3. Am29F016D Autoselect Codes (High Voltage Method)

L = Logic Low = V

, H = Logic High = V

, SA = Sector Address, X = Don’t care.

Sector Group Protection/Unprotection

The hardware sector group protection feature dis-

ables both program and erase operations in any sec-

tor gr o u p. Each sector group consists of four adjacent

sectors. Table 4 shows how the sectors are grouped,

and the address range that each sector group con-

tains. The hardware sector group unprotection fea-

ture re-enables both program and erase operations in

previously protected sector groups.

Sector group protection/unprotection must be imple-

mented using programming equipment. The procedure

requires a high voltage (V

) on address pin A9 and the

control pins. Details on this method are provided in a

supplement, publication number 23922. Contact an

AMD representative to obtain a cop y of the appropriate

document. Note that the sector group protection and

unprotection scheme differs from that used with the

previous versions of this device, namely the

Am29F016B and Am29F016.

The device is shipped with all sector groups unpro-

tected. AMD offers t he optio n of prog r amming a nd pro-

tecting sector groups at it s factory prior t o shipping t he

device through AMD’s ExpressFlash™ Service. Con-

tact an AMD representative for details.

It is possible to determine whether a sector group is

protected or unprotected. See “Autoselect Mode” for

details.

Table 4. Sector Group Addresses

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ-

ously protected sector groups to change data in-sys-

tem. The Sector Group Unprotect mode is activated

by setting the RESET# pin to V

. During this mode,

formerly protected sector g roups can be programmed

or erased by selecting the sector group addresses.

Description CE# OE# WE# A20-A18 A17-A10 A9 A8 -A7 A6 A5-A2 A 1 A0 DQ 7-DQ0

Manufacturer ID:

AMD

LLH X X V

01h

Device ID:

Am29F016D

LLH X X V

ADh

Sector Group

Protection

Verification

LLH

Sector

Group

Address

01h (protected)

00h (unprotected)

Sector

Group A20 A19 A18 Sectors

SGA0 0 0 0 SA0

–

SA3

SGA1 0 0 1 SA4

–

SA7

SGA2 0 1 0 SA8

–

SA11

SGA3 0 1 1 SA12

–

SA15

SGA4 1 0 0 SA16

–

SA19

SGA5 1 0 1 SA20

–

SA23

SGA6 1 1 0 SA24

–

SA27

SGA7 1 1 1 SA28

–

SA31

Am29F016D 13

Once V

is removed from the RESET# pin, all the

previously protected sector groups are

protected again. Figure 1 shows the algorithm, and

the Temporary Sector Group Unprotect diagram (Fig-

ure 16) shows the timing waveforms, for this feature.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection measures pre vent a ccidental eras ure or pro-

gramming, which might otherwise be caused by spuri-

ous system level signals during V

power-up and

power-down transitions, or from system noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not ac-

cept any write cycles. This protects data during V

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V

is greater than V

LKO

. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when V

is greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

= V

, CE# = V

or WE# = V

. To init iate a wr ite cy-

cle, CE# and WE# must be a logical zero while OE#

is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = V

during power up , the

device does not accept commands on the rising edge

of WE#. The internal state mac hine is automatically

reset to reading array data on power-up.

START

Perform Erase or

Program Operations

RESET# = V

Temporary

Sector Group Unprotect

Completed (Note 2)

RESET# = V

(Note 1)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected

once again.

Figure 1. Temporary Sector Group Unprotect

Operation

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