FUJITSU Am29F016D Service Manual

Am29F016D

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the docu ment is ma rked with the name o f the comp any that o rig­inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.

Publication Number 21444 Revision E Amendment +2 Issue Date March 23, 2001

Am29F016D

16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 V ± 10%, single power supply operation

— Minimizes system level power requirements

■ Manufactured on 0.23 µm process technology

— Compatible with 0.5 µm Am29F016 and 0.32 µm

Am29F016B devices

■ High performance

— Access times as fast as 70 ns

■ Low power consumption

— 25 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access

time to active mode)

■ Flexible sector arc hitecture

— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Group sector protection:

A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group

Temporary Sector Group Unprotect allows code
changes in previously locked sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■ Minimum 1,000,000 program/erase cycles per

sector guaranteed

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package options

— 48-pin and 40-pin TSOP
— 44-pin SO
— Known Good Die (KGD)

(see publication number 21551)

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detect ing program

or erase cycle completion

■ Ready/Busy# output (RY/ BY#)

— Provides a hardware method for detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends a sector erase operation to read data

from, or program data to, a non-erasing sector,
then resumes the erase operation

■ Hardware reset pin (RESET#)

— Resets internal state machine to the read mode

■ Unlock Bypass Program Command

— Reduces overall prog ramming time when issuing

multiple program command sequences

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modificat ions due to changes in technical specif ic ations.

Publication# 21444 Rev: E Amendment/+2
Issue Date: March 23, 2001

GENERAL DESCRIPTION

The Am29F016D is a 16 Mbit, 5.0 volt-only Flash mem­ory organized as 2,09 7,152 bytes. The 8 bits of data

appear on DQ0–DQ7. The Am29F016D is offered in
48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.
The device is also available in Known Good Die ( KGD)
form. For more information, refer to publication number

21551. This device is desi gned to be programmed
in-system with the standard system 5.0 v olt V
A 12.0 volt V

is not required for program or erase

PP

operations. The device can also be programmed in
standard EPROM programmers.

This device is manufactured using AMD’s 0.23 µm pro­cess technology, and offers all the features and bene­fits of the Am29F016, which was manufactured using

0.5 µm process technology.
The standard device off ers access t imes of 70, 90, 120,

and 150 ns, allowing high-speed microprocessors to
operate without wait s tates. To eliminate bus conten­tion, the device has separate chip enable (CE#), write
enable (WE#), and output enable (OE#) controls.

The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and write functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microproc essor write timing s. Register contents
serve as input to an internal sta te-machine that co n­trols the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin.

Device erasure occurs by executing the erase com­mand sequence. This initiates the Embedded Erase

supply .

CC

algorithm—an in ternal algorithm that auto matically
preprograms the arra y (if it is not already progr ammed)
before e xecuting the er ase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a prog ram or erase cycle has
been completed, the device is ready to read array data
or accept another command.

The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of mem­ory . This can be achie v ed via prog ramming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bi t s w i th i n a
s ect or simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

2 Am29F016D

TABLE OF CONTENTS

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Am29F016D Device Bus Operations.................................. 9

Requirements for Reading Array Data....................... .............. 9

Writing Commands/Command Sequences .................... .. ........ 9

Program and Erase Operation Status .................................... 10

Standby Mode ................... ......................................... ............ 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode.............................................................. 10

Table 2. Sector Address Table........................................................ 11

Autoselect Mode..................................................................... 12

Table 3. Am29F016D Autoselect Codes (High Voltage Method).... 12

Sector Group Protection/Unprot ection................... ................. 12

Table 4. Sector Group Addresses................................................... 12

Temporary Sector Group Unprotect ....................................... 12

Figure 1. Temporary Sector Group Unprotect Operation................ 13

Hardware Data Protection...................................................... 13

Low VCC Write Inhibit...................................................................... 13

Write Pulse “Glitch” Protection........................................................ 13

Logical Inhibit. . ......... ...... ... ..... ......... ....... ....... .... ..... ....... ......... ....... .. 13

Power-Up Write Inhibit.................................................................... 13

Common Flash Memory Interface (CFI). . . . . . . 14

Table 5. CFI Query Identification String.......................................... 14

Table 6. System Interface String..................................................... 14

Table 7. Device Geometry Definition.............................................. 15

Table 8. Primary Vendor-Specific Extended Query ........................ 15

Command Definitions . . . . . . . . . . . . . . . . . . . . . 16

Reading Array Data.................... ................. ................. .......... 16

Reset Command..................................................................... 16

Autoselect Command Sequence............. ............................... 16

Byte Program Command Sequence....................................... 16

Unlock Bypass Command Sequence.............................................. 17

Figure 2. Program Operation.......................................................... 17

Chip Erase Command Sequence........................................... 17

Sector Erase Command Sequence........................................ 18

Erase Suspend/Erase Resume Commands........................... 18

Figure 3. Erase Operation............................................................... 19

Command Definitions ............................................................. 20

Table 9. Am29F016D Command Definitions................................... 20

Write Operation Status . . . . . . . . . . . . . . . . . . . . 21

DQ7: Data# Polling................................................................. 21

Figure 4. Data# Polling Algorithm ................................................... 21

RY/BY#: Ready/Busy# ........................................................... 22

DQ6: Toggle Bit I.................................................................... 22

DQ2: Toggle Bit II ................................................................... 22

Reading Toggle Bits DQ6/DQ2 .............................................. 22

DQ5: Exceeded Timing Limits................................................ 23

DQ3: Sector Erase Timer ....................................................... 23

Figure 5. Toggle Bit Algorithm........................................................ 23

Table 10. Write Operation Status................................................... 24

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25

Figure 6. Maximum Negative Overshoot Waveform...................... 25

Figure 7. Maximum Positive Overshoot Waveform........................ 25

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 25

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

TTL/NMOS Compatible .......................................................... 26

CMOS Compatible.................................................................. 26

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8. Test Setup...................................................................... 27

Table 11. Test Specifications......................................................... 27

Key to Switching Waveforms. . . . . . . . . . . . . . . . 27

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Read-only Operations............................................................. 28

Figure 9. Read Operation Timings................................................. 28

Figure 10. RESET# Timings.......................................................... 29

Erase/Program Operations..................................................... 30

Figure 11. Program Operation Timings.......................................... 31

Figure 12. Chip/Sector Erase Operation Timings .......................... 32

Figure 13. Data# Polling Timings (During Embedded Algorithms). 33

Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... 33

Figure 15. DQ2 vs. DQ6................................................................. 34

Figure 16. Temporary Sector Group Unprotect Timings................ 34

Erase and Program Operations............ ................. ................. 35

Alternate CE# Controlled Writes.................................................... 35

Figure 17. Alternate CE# Controlled Write Operation Timings ...... 36

Erase and Programming Performance . . . . . . . 37

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 37

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 37

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38

TS 040—40-Pin Standard Thin Small Outline Package......... 38

TSR040—40-Pin Reverse Thin Small Outline Package......... 39

TS 048—48-Pin Standard Thin Small Outline Package......... 40

TSR048—48-Pin Reverse Thin Small Outline Package......... 41

SO 044—44-Pin Small Outline Package................................ 42

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43

Revision A (May 1997) .............. ............................................. 43

Revision B (January 1998) ..................................................... 43

Revision B+1 (January 1998)........................... .. ................. .. . 43

Revision B+2 (April 1998)....................................................... 43

Revision C (January 1999)......................................... ............ 43

Revision C+1 (March 23, 1999).............................................. 43

Revision C+2 (May 17, 1999)................................................. 43

Revision C+3 (July 2, 1999) ................................................... 43

Revision D (November 16, 1999) ........................................... 43

Revision E (May 19, 2000) ..................................................... 44

Revision E+1 (December 4, 2000) ......................................... 44

Revision E+2 (March 23, 2001).............. ............. ................... 44

Am29F016D 3

PRODUCT SELECTOR GUIDE

Family Part Number Am29F016D

Speed Options (V
Max Access Time (ns) 70 90 120 150
CE# Access (ns) 70 90 120 150
OE# Access (ns) 40 40 50 75

= 5.0 V ± 10%) -70 -90 -120 -150

CC

Note: See the AC Characteristics section for more information.

BLOCK DIAGRAM

DQ0

–

DQ7

V

CC

V

SS

RY/BY#

RESET#

WE#

CE#
OE#

State

Control

Command

Register

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Input/Output

Buffers

Data

Latch

A0–A20

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

4 Am29F016D

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for
more information.

A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

NC

RESET#

A11
A10

A9
A8
A7
A6
A5
A4

A20

NC

WE#

OE#

RY/BY#

DQ7
DQ6
DQ5
DQ4

V

V

V
DQ3
DQ2
DQ1
DQ0

CC

A0
A1
A2
A3

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9

CC

SS
SS

10

11

12

13

14

15

16

17

18

19

20

40-Pin Standard TSOP

40-Pin Reverse TSOP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3

A19
A18
A17
A16
A15
A14
A13
A12
CE#
V

CC

NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4

Am29F016D 5

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for
more information.

NC

NC
A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

NC

RESET#

A11
A10

A9
A8
A7
A6
A5

A4
NC
NC

NC
NC

A20

NC

WE#

OE#

RY/BY#

DQ7
DQ6
DQ5
DQ4

V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0

A0
A1
A2
A3

NC
NC

1
2
3
4
5
6
7
8

9
10
11
12

CC

13
14
15
16
17
18
19
20
21
22
23
24

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

24

48-Pin Standard TSOP

48-Pin Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

NC
NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC
NC

NC
NC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V

CC

NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC

6 Am29F016D

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for
more information.

1

NC

A11
A10

A9
A8
A7
A6
A5

A4
NC
NC

A3

A2

A1

A0

DQ0
DQ1
DQ2
DQ3

V

SS

V

SS

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

RESET#

PIN CONFIGURATION

A0–A20 = 21 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
WE# = Write Enable
OE# = Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output

= +5.0 V single power supply

V

CC

(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)

SO

LOGIC SYMBOL

21

44

V

CC

CE#

43

A12

42

A13

41

A14

40

A15

39

A16

38

A17

37

A18

36

A19

35

NC

34

NC

33

A20

32

NC

31

WE#

30

OE#

29

RY/BY#

28

DQ7

27

DQ6

26

DQ5

25

DQ4

24

V

23

CC

A0–A20

DQ0–DQ7

CE#
OE#

WE#
RESET# RY/BY#

8

V

SS

= Device Ground

NC = Pin Not Connected Internally

Am29F016D 7

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Am29F016D -70 E I

DEVICE NUMBER/DESCRIPTION

Am29F016D
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory

5.0 V Read, Program, and Erase

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40

E = Extended (–55

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
E4 = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040)
F4 = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040)
S = 44-Pin Small Outline Package (SO 044)
This device is also available in Known Good Die (KGD) form. See publication number

21551 for more information.

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +85°C)

°C to +125°C)

AM29F016D-70

AM29F016D-90
AM29F016D-120
AM29F016D-150

Valid Combinations

EC, EI, FC, FI,
E4C, E4I, F4C, F4I, SC, SI

EC, EI, EE, FC, FI, FE,
E4C, E4I, E4E, F4C, F4I,
F4E, SC, SI, SE

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume f or this device. Consult the local AMD sales
office to confirm av ailability of specific valid combinations and
to check on newly released combinations.

8 Am29F016D

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29F016D Device Bus Operations

Operation CE# OE# WE# RESET# A0–A20 DQ0–DQ7

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.

Read L L H H A
Write L H L H A
CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z

TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Hardware Reset X X X L X High-Z
Temporary Sector Unprotect

(See Note)

Legend:

L = Logic Low = V

Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D

IL

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re­main at V

.

IH

The internal state machin e is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem­ory content occurs during the power transition. No
command is necessar y in this mode to obtain array
data. Standard microprocessor read cycles that as­sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to the Read Operations Timings diagram for
the timing waveforms. I

in the DC Characteristics

CC1

table represents the active current specification for
reading array data.

. CE# is the power

IL

XXX V

ID

Writing Commands/Command Sequences

To wr ite a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

An erase operation can erase one sect or, multiple sec­tors, or the entire de vice. The Sector Address Tables in­dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini­tions” section for details on erasing a sector or the en­tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.

I

CC2

tive current specification for the write mode. The “AC
Characteristics” section contains timing specification

, and OE# to VIH.

IL

in the DC Characteristics table represents the ac-

OUT

IN

IN

A

IN

= Data Out, AIN = Address In

D

OUT

D

D

IN

IN

tables and timing diagrams for write operations.

Am29F016D 9

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac­teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V
that this is a more restrict ed voltage range than V

± 0.5 V. (Note

CC

IH

The device enters the TTL standby mode when CE#
and RESET# pins are both held at V
quires standard access time (t

CE

. The device re-

IH

) for read access when
the device is in either of these standb y modes, bef ore it
is ready to read data.

The device also enters the standb y mode when the RE­SET# pin is driven low. Refer to the next section, “RE­SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

In the DC Charac teristics tables, I

represents the

CC3

standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of reset­ting the device to readi ng arr ay data. When the system
drives the RESET# pin low for at least a period of t

RP

the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

, the device enters

IL

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode .
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

.)

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operatio n is complete, which requires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
SET# pin returns to V

(not during Embe dded Algo-

READY

.

IH

RH

Refer to the AC Characteristics tables for RESET# pa­rameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

,

SS

after the RE-

±

10 Am29F016D

Table 2. Sector Address Table

Sector A20 A19 A18 A17 A16 Address Range

SA0 0 0 0 0 0 000000h-00FFFFh
SA1 0 0 0 0 1 010000h-01FFFFh
SA2 0 0 0 1 0 020000h-02FFFFh
SA3 0 0 0 1 1 030000h-03FFFFh
SA4 0 0 1 0 0 040000h-04FFFFh
SA5 0 0 1 0 1 050000h-05FFFFh
SA6 0 0 1 1 0 060000h-06FFFFh
SA7 0 0 1 1 1 070000h-07FFFFh
SA8 0 1 0 0 0 080000h-08FFFFh

SA9 0 1 0 0 1 090000h-09FFFFh
SA10 0 1 0 1 0 0A0000h-0AFFFFh
SA11 0 1 0 1 1 0B0000h-0BFFFFh
SA12 0 1 1 0 0 0C0000h-0CFFFFh
SA13 0 1 1 0 1 0D0000h-0DFFFFh
SA14 0 1 1 1 0 0E0000h-0EFFFFh
SA15 0 1 1 1 1 0F0000h-0FFFFFh
SA16 1 0 0 0 0 100000h-10FFFFh
SA17 1 0 0 0 1 110000h-11FFFFh
SA18 1 0 0 1 0 120000h-12FFFFh
SA19 1 0 0 1 1 130000h-13FFFFh
SA20 1 0 1 0 0 140000h-14FFFFh
SA21 1 0 1 0 1 150000h-15FFFFh
SA22 1 0 1 1 0 160000h-16FFFFh
SA23 1 0 1 1 1 170000h-17FFFFh
SA24 1 1 0 0 0 180000h-18FFFFh
SA25 1 1 0 0 1 190000h-19FFFFh
SA26 1 1 0 1 0 1A0000h-1AFFFFh
SA27 1 1 0 1 1 1B0000h-1BFFFFh
SA28 1 1 1 0 0 1C0000h-1CFFFFh
SA29 1 1 1 0 1 1D0000h-1DFFFFh
SA30 1 1 1 1 0 1E0000h-1EFFFFh
SA31 1 1 1 1 1 1F0000h-1FFFFFh

Note: All sectors are 64 Kbytes in size.

Am29F016D 11

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

(11.5 V to 12.5 V) on address pin

ID

A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi­tion, when verifying sector protection, the sector ad-

Table 3. Am29F016D Autoselect Codes (High Voltage Method)

Description CE# OE# WE# A20-A18 A17-A10 A9 A8 -A7 A6 A5-A2 A 1 A0 DQ 7-DQ0

dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad­dress Tables. The Command Definitions ta ble shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding
identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini­tions table. This method does not require V
“Command Definitions” for details on using the autose­lect mode.

. See

ID

Manufacturer ID:
AMD

Device ID:
Am29F016D

Sector Group
Protection
Verification

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

LLH X X V

LLH X X V

Sector

LLH

Group

Address

XV

Sector Group Protection/Unprotection

The hardware sector group protection feature dis­ables both program and erase operations in any sec­tor gr o u p. Each sector group consists of four adjacent
sectors. Table 4 shows how the sectors are grouped,
and the address range that each sector group con­tains. The hardware sector group unprotection fea­ture re-enables both program and erase operations in
previously protected sector groups.

Sector group protection/unprotection must be imple­mented using programming equipment. The procedure
requires a high voltage (V
control pins. Details on this method are provided in a
supplement, publication number 23922. Contact an
AMD representative to obtain a cop y of the appropriate
document. Note that the sector group protection and
unprotection scheme differs from that used with the
previous versions of this device, namely the
Am29F016B and Am29F016.

The device is shipped with all sector groups unpro­tected. AMD offers t he optio n of prog r amming a nd pro­tecting sector groups at it s factory prior t o shipping t he

device through AMD’s ExpressFlash™ Service. Con­tact an AMD representative for details.

) on address pin A9 and the

ID

XVILXVILV

ID

XVILXVILV

ID

XVILXVIHV

ID

It is possible to determine whether a sector group is
protected or unprotected. See “Autoselect Mode” for
details.

Table 4. Sector Group Addresses

Sector
Group A20 A19 A18 Sectors

SGA0 0 0 0 SA0
SGA1 0 0 1 SA4
SGA2 0 1 0 SA8
SGA3 0 1 1 SA12
SGA4 1 0 0 SA16
SGA5 1 0 1 SA20
SGA6 1 1 0 SA24
SGA7 1 1 1 SA28

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ­ously protected sector groups to change data in-sys­tem. The Sector Group Unprotect mode is activated
by setting the RESET# pin to V
formerly protected sector g roups can be programmed
or erased by selecting the sector group addresses.

IL

IH

IL

01h

ADh

01h (protected)

00h (unprotected)

–
–

–

–
–
–
–
–

. During this mode,

ID

SA3
SA7

SA11

SA15
SA19
SA23
SA27
SA31

12 Am29F016D

Once VID is removed from the RESET# pin, all the
previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
the Temporary Sector Group Unprotect diagram (Fig­ure 16) shows the timing waveforms, for this feature.

START

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi­nitions table). In addition, the following hardware data
protection measures pre vent a ccidental eras ure or pro­gramming, which might otherwise be caused by spuri­ous system level signals during V
power-down transitions, or from system noise.

power-up and

CC

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary

Sector Group Unprotect

Completed (Note 2)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected
once again.

ID

IH

Figure 1. Temporary Sector Group Unprotect

Operation

Low V

When V
cept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

CC

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

, CE# = VIH or WE# = VIH. To init iate a wr ite cy-

= V

IL

cle, CE# and WE# must be a logical zero while OE#
is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up , the

IL

device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.

Am29F016D 13

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Inte rface (CFI) specification out­lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire f amilies o f de­vices. Software suppo rt can then be device-indepe n­dent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can s tandardize their existing
interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys­tem writes the CFI Quer y command, 98h, to addres s
55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 5–8. To terminate reading CFI data, the
system must write the reset command.

The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses giv en in Tables 5–8. The sys­tem must write the reset command to return the de v ice
to the autoselect mode.

For further information, please refer to the CFI Specifi­cation and CFI Publication 100, a vailable via the W orld
Wide Web at http://www.amd.com/products/nvd/over­view/cfi.html. Alternatively, contact an AMD represen­tative for copies of these documents.

Table 5. CFI Query Identification String

Addresses Data Description

10h
11h
12h

13h
14h

15h
16h

17h
18h

19h

1Ah

51h
52h
59h

02h
00h

40h
00h

00h
00h

00h
00h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Table 6. System Interface String

Addresses Data Description

Min. (write/erase)

V

1Bh 45h

1Ch 55h

1Dh 00h V
1Eh 00h V
1Fh 03h Typical timeout per single byte/word write 2

20h 00h Typical timeout for Min. size buffer write 2
21h 0Ah Typical timeout per individual block erase 2
22h 00h Typical timeout for full chip erase 2
23h 05h Max. timeout for byte/word write 2
24h 00h Max. timeout for buffer write 2
25h 04h Max. timeout per individual block erase 2
26h 00h Max. timeout for full chip erase 2

CC

D7–D4: volt, D3–D0: 100 millivolt

Max. (write/erase)

V

CC

D7–D4: volt, D3–D0: 100 millivolt

Min. voltage (00h = no VPP pin present)

PP

Max. voltage (00h = no VPP pin present)

PP

N

N

N

times typical

N

times typical (00h = not supported)

N

µs

N

µs (00h = not supported)

N

ms

ms (00h = not supported)

times typical

N

times typical

14 Am29F016D

Table 7. Device Geometry Definition

Addresses Data Description

N

27h 15h Device Size = 2

byte

28h
29h

2Ah
2Bh

00h
00h

00h
00h

Flash Device Interface description (refer to CFI publication 100)

N

Max. number of byte in multi-byte write = 2

(00h = not supported)
2Ch 01h Number of Erase Block Regions within device
2Dh

2Eh
2Fh

30h

1Fh
00h
00h
01h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

Table 8. Primary Vendor-Specific Extended Query

Addresses Data Description

40h
41h
42h

43h 31h Major version number, ASCII
44h 31h Minor version number, ASCII

45h 00h

46h 02h

50h
52h
49h

Query-unique ASCII string “PRI”

Address Sensitive Unlock

0 = Required, 1 = Not Required

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 04h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h 01h Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h 04h

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode
4Ah 00h Simultaneous Operation: 00 = Not Supported, 01 = Supported
4Bh 00h Burst Mode Type: 00 = Not Supported, 01 = Supported

4Ch 00h

Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,

02 = 8 Word Page
4Dh 00h ACC supply minimum
4Eh 00h ACC supply maximum

4Fh 00h

Top/bottom boot sector flag

2 = bottom, 3 = top. If address 2Ch = 01h, ignore this field

Am29F016D 15

COMMAND DEFINITIONS

Writing specific addre ss and data commands or se­quences into the command register initiates device op­erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect

address and data values or writing them in the im-
proper sequence resets the device to reading array

data.
All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Em­bedded Erase algorithm.

After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend mode. The sys­tem can read array data using the standard read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once agai n read arra y
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.

must

The system
able the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame­ters, and Read Operation Timings diagram shows the
timing diagram.

issue the reset command to re-en-

Reset Command

Writing the reset command to the devi ce resets the de­vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

must

Autoselect Command Sequence

The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an a lternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is in tended for PROM program­mers and requires V

The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then en ters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.

A read cycle at address XX00h retrieves the manufac­turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Ad dr e ss ta bles for valid sector addresses.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

on address bit A9.

ID

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro­gram command sequence is initiated by writing two un­lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-

not

gorithm. The system is
controls or timings. The device automatically provides
internally generated program pulses and v erify the pro­grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the program operation b y using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in­formation on these status bits.

required to provide further

16 Am29F016D

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program­ming operation. The program command sequence
should be reinitiated once the de vi ce has reset t o read­ing array data, to ensure data integrity.

Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the op eration was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro­gram bytes or words to the de vice f aster than using the
standard program command sequence. The unloc k b y­pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de­vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the prog ram
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program­ming time. Table 9 shows the r equirements for the com­mand sequence.

During the unlock bypass mode, o nly the Unlock By­pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com­mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Add resses are
don’t care for both cycles. The device then returns to
reading array data.

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note:

See the appropriate Command Definitions table for program
command sequence.

No

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

No

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bu s-cycle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. The Command
Definitions table shows the address and data require­ments for the chip erase command sequence.

require the system to

Am29F016D 17

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a har dware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, t o ensure data int eg rity.

The system can deter mine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for inform ation on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latc hed.

Figure 3 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters , and to the Chip/Sector
Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un­lock cycles, followed by a set-up command. Two addi­tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec­tor erase command sequence.

not

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the sector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begi ns. During the time-out per iod,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all secto rs. The time be­tween these additional cycl es must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.

require the system to preprogram

Once the sector erase operation has begun, on ly the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op­eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addr esses are
no longer latched. The system can determine the sta­tus of the erase operation b y using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa­tion on these status bits.

Figure 3 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagr am for timing
waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows t he syste m to in­terrupt a sector erase ope ration and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase c ommand sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the er ase oper at ion. Ad­dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter­minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasu re. (The de vice “er ase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.

The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sec tor Erase
Timer” section.) The time-out be gins from the rising
edge of the final WE# pulse in the command sequence .

18 Am29F016D

After an erase-suspended program operation is com­plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See “Write Operation Status” for more informa­tion.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operat ion. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de­vice has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

No

Notes:

1. See the appropriate Command Definitions table for erase
command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

Figure 3. Erase Operation

Am29F016D 19

Command Definitions

Table 9. Am29F016D Command Definitions

Bus Cycles (Notes 2–4)

Command
Sequence

(Note 1)

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01

Autoselect

(Note 7)

CFI Query (Note 9) 1 55 98
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 10) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0

Device ID 4 555 AA 2A A 55 555 90 X01 AD

Sector Group Protect
Verify (Note 8)

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

XX00

4 555 AA 2AA 55 555 90

SGA

X02

XX01

Erase Resume (Note 10) 1 XXX 30

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus
cycles are write operations.

4. Address bits A20–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading
array data.

6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5
goes high (while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is
a read cycle.

8. The data is 00h for an unprotected sector group and 01h
for a protected sector group.See “Autoselect Command
Sequence” for more information.

PD = Data to be programmed at location P A. Data latches on
the rising edge of WE# or CE# pulse, whichev er happens f irst.

SA = Address of the sector to be verified (in autoselect mode)
or erased. Address bits A20–A16 select a unique sector.

SGA = Address of the sector group to be verified. Address
bits A20–A18 select a unique sec tor group.

9. Command is valid when device is ready to read array data
or when device is in autoselect mode.

10. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.

11. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the unlock
bypass mode.

12. The system may read and program in non-erasing
sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid
only during a sector erase operation.

13. The Erase Resume command is valid only during the
Erase Suspend mode.

20 Am29F016D

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10 and the following subsections
describe the functions of thes e bits . DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

Table 10 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, in dicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# P olling is v alid after the rising
edge of the final WE# pulse in the program or erase
command sequence.

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 2 µs, then the device returns to reading

array data.
During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al­gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

No

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Yes

Yes

PASS

After an erase command sequence is written, if all s ec­tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll­ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.

Am29F016D 21

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 4. Data# Polling Algorithm

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 10 shows the outputs for RY/BY#. The timing di­agrams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.

CC

.

DQ6: Toggle Bit I

To ggle Bit I on DQ6 indi cates whether an Embedde d
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e op­eration), and during the sector erase time-out.

The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 f or the toggle bit
algorithm, and to the Toggle Bit Timings figu re in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be­tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.

DQ2 toggles w hen the system reads at addresses
within those sector s that have been selected for era­sure. (The system may use either OE# or CE# to con­trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for sector and
mode information. Refer to Table 10 to compare out­puts for DQ2 and DQ6.

During an Embedded Program or Erase algorithm op­eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-

µ

gles for appro xi mately 100
array data. If not all selected sectors are pro tected,
the Embedded Erase algorithm erases the unpro­tected sectors, and ignores the selected sectors that
are protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is activ ely erasing (that is ,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a pro tected sector,

DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

s, then returns to reading

Figure 5 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows t he dif­ferences between DQ2 and DQ6 in graphical f orm.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. When­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note a nd store th e val ue of the to ggle bit
after the first read. After the second read, the system
would compare the ne w v alue of the toggle bit with the
first. If the toggle bit is not to ggling, the device has
completed the program or erase operation. The sys­tem can read arra y data on DQ7–DQ0 on the f ollo wing
read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggli ng, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog­gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully comp leted the
program or erase operation. If it is still toggling, the
device did not complete the oper ation successfully, and

22 Am29F016D

the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through success ive read cycle s, de­termining the status as described in the previous para­graph. Alterna tively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle was
not successfully completed.

erase command. If DQ3 is high on the second status
check, the last command might not have been ac­cepted. Table 10 shows the outputs for DQ3.

START

Read DQ7–DQ0

Read DQ7–DQ0

(Note 1)

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that i s previously pro­grammed to “0.” Only an era se operation can change

a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, t he system must issue the

reset command to return the device to reading array
data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to det ermine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi­tional sectors are selec ted for er asure, th e entire time­out also applies after each add itional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guar antee t hat the time betw een ad­ditional sector erase commands will always be less
than 50 µs. See a lso the “Sector Eras e Command Se­quence” section.

After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Su spend)
are ignored u ntil the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should ch eck the s tatus
of DQ3 prior to and following each subsequent sector

Toggle Bit

= Toggle?

Yes

No

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not
Complete, Write
Reset Command

No

(Notes
1, 2)

No

Program/Erase

Operation Complete

Figure 5. Toggle Bit Algorithm

Am29F016D 23

Table 10. Write Operation Status

DQ7

Standard
Mode

Erase
Suspend
Mode

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 1) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

DQ5

(Note 2) DQ3

DQ2

(Note 1) RY/BY#

24 Am29F016D

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

V

CC

A9, OE#, RESET# (Note 2). . . . .–2.0 V to 12.5 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may overshoot V
for periods of up to 20 ns. See . Maximum DC voltage on
output and I/O pins is V
transitions, outputs may overshoot to V
periods up to 20 ns. See .

2. Minimum DC input voltage on A9, OE#, RESET# pins is
–0.5V. During voltage transitions, A9, OE#, RESET# pins
may overshoot V
See . Maximum DC input voltage on A9, OE#, and
RESET# is 12.5 V which may overshoot to 13.5 V for
periods up to 20 ns.

3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.

SS

+ 0.5 V. During voltage

CC

to –2.0 V for periods of up to 20 ns.

to –2.0 V

SS

+ 2.0 V for

CC

+0.8 V

–0.5 V
–2.0 V

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V

20 ns

20 ns

20 ns

Figure 6. Maximum Negative

Overshoot Waveform

20 ns

20 ns

20 ns

Stresses greater than those listed in this section may cause
permanent da mage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections
of this specification is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods
may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

Supply Voltages

V

CC

for ± 10% de vices. . . . . . . . . . . .+4.5 V to +5.5 V

V

CC

Operating rang es define those limits between which the
functionality of the device is guaranteed.

). . . . . . . . . . . 0°C to +70°C

C

). . . . . . . . . –40°C to +85°C

C

) . . . . . . . . –55°C to +125°C

A

Figure 7. Maximum Positive

Overshoot Waveform

Am29F016D 25

DC CHARACTERISTICS
TTL/NMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

I
I

I

I

V

V

I

LI

I

LIT

I

LO
CC1
CC2

CC3

CC4

V

V
V
V

OL
OH

LKO

Input Load Current VIN = V

A9 Input Load Current V
Output Leakage Current V

CC
OUT

VCC Read Current (Note 1) CE# = V
VCC Write Current (Notes 2, 3) CE# = V
V

Standby Current

CC

(CE# Controlled)
V

Standby Current

CC

(RESET# Controlled)
Input Low Level –0.5 0.8 V

IL

Input High Level 2.0 V

IH

Voltage for Autoselect and Sector

ID

Protect

VCC = VCC Max, CE# = VIH,
RESET#

V

CC

V

CC

Output Low Voltage IOL = 12 mA, V
Output High Level IOH = –2.5 mA V
Low VCC Lock-out Voltage 3.2 4.2 V

to VCC, V

SS

= V

Max, A9 = 12.5 V 50 µA

CC

= V

to VCC, V

SS

OE# = V

IL,

OE# = V

IL,

= VIH

= V

Max, RESET# = V

CC

= VCC Max

CC

= VCC Max

CC

IH

IH

IL

1.0 µA

±

1.0 µA

±

25 40 mA
40 60 mA

0.4 1.0 mA

0.4 1.0 mA

+ 0.5 V

CC

= 5.0 V 11.5 12.5 V

= V

CC

CC

Min 0.45 V

CC

= V

Min 2.4 V

CC

CMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

Input Load Current VIN = V
A9 Input Load Current V
Output Leakage Current V
V

Read Current (Note 1) CE# = V

CC

V

Write Current (Notes 2, 3) CE# = V

CC

V

Standby Current

CC

(CE# Controlled) (Note 4)
V

Standby Current

CC

(RESET# Controlled) (Note 4)
Input Low Level –0.5 0.8 V

IL

Input High Level 0.7x V

IH

Voltage for Autoselect

ID

and Sector Protect

CC
OUT

V

CC = VCC

RESET# = V
V

CC

RESET# = V

V

CC

Output Low Voltage IOL = 12 mA, V

I

Output High Voltage

Low V

Lock-out Voltage 3.2 4.2 V

CC

OH

IOH = –100 µA, V

V
V

V

I
I
I

I

CC1

I

CC2

I

CC3

I

CC4

V

V
V
V

OH1

OH2

LI
LIT
LO

OL

LKO

Notes for DC Characteristics (both tables):

1. The I

2. I

current is typically less than 1 mA/MHz, with OE# at VIH.

CC

active while Embedded Program or Embedded Erase algorithm is in progress.

CC

3. Not 100% tested.
, I

4. For CMOS mode only I

CC3

= 20 µA at extended temperature (>+85°C).

CC4

to VCC, V

SS

= V

Max, A9 = 12.5 V 50 µA

CC

= V

to VCC, V

SS

OE# = V

IL,

OE# = V

IL,

Max, CE# = V

CC

= V

Max,

CC

SS

0.5 V

±

0.5 V

±

CC

IH
IH

CC

= V

CC

= V

CC

Max

CC

0.5 V,

±

Max

1.0 µA

±

1.0 µA

±

25 40 mA
30 40 mA

15µA

15µA

V

CC

+ 0.3 V

CC

= 5.0 V 11.5 12.5 V

= V

CC

= –2.5 mA, V

Min 0.45 V

CC

= V

CC

CC

Min 0.85 V

CC

= V

Min VCC – 0.4 V

CC

CC

V

26 Am29F016D

TEST CONDITIONS

Device

Under

Test

C

L

6.2 k

5.0 V

2.7 k

Ω

Output Load 1 TTL gate
Output Load Capacitance, C

Ω

(including jig capacitance)
Input Rise and Fall Times 20 ns
Input Pulse Levels 0.45–2.4 V

Table 11. Test Specifications

All speed

Test Condition

L

options Unit

100 pF

Note: Diodes are IN3064 or equivalent

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEF OR M INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

0.8 V

2.0 V

KS000010-PAL

Am29F016D 27

AC CHARACTERISTICS
Read-only Operations

Parameter Symbol

Parameter Description

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

t

t

ACC

t
t

t

OEH

t
t

t

t

Ready

Read Cycle Time (Note 1) Min 70 90 120 150 ns

RC

Address to Output Delay

Chip Enable to Output Delay OE# = VILMax 70 90 120 150 ns

CE

Output Enable to Output Delay Max 40 40 50 55 ns

OE

Output Enable Hold
Time (Note 1)

Chip Enable to Output High Z (Note 1) Max 20 20 30 35 ns

DF

Output Enable to Output High Z (Note 1) Max 20 20 30 35 ns

DF

Output Hold Time From Addresses CE#

OH

or OE# Whichever Occurs First
RESET# Pin Low to Read Mode

(Note 1)

Notes:

1. Not 100% tested.

2. Refer to and for test specifications.

Test

Setup

CE# = V
OE# = V

IL

Max 70 90 120 150 ns

IL

Speed Options

UnitJEDEC Std -70 -90 -120 -150

Read Min0000ns
Toggle and

Data# Polling

Min10101010ns

Min0000ns

Max20202020µs

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

t

RC

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 9. Read Operation Ti mi ng s

t

OH

t

DF

HIGH Z

28 Am29F016D

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

t

READY

t

READY

t

RP

t

RH

t

RB

Note:

Not 100% tested.

RY/BY#

CE#, OE#

RESET#

RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

Max 20 µs

Max 500 ns

RESET# Pulse Width Min 500 ns
RESET# High Time Before Read (See Note) Min 50 ns
RY/BY# Recovery Time Min 0 ns

t

RH

t

RP

t

Ready

RY/BY#

CE#, OE#

RESET#

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

t

RP

Figure 10. RESET# Timings

t

RB

Am29F016D 29

AC CHARACTERISTICS
Erase/Program Operations

Parameter

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHWL

t

CS

t

CH

t

WP

t

WPH

Speed Options

Parameter Description

UnitJEDEC Std -70 -90 -120 -150

Write Cycle Time (Note 1) Min 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 40 45 50 50 ns
Data Setup Time Min 40 4 5 50 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recover Time Before Write

(OE# high to WE# low)

Min 0 ns

CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 40 45 50 50 ns
Write Pulse Width High M in 20 ns
Byte Programming Operation (Note 2) Typ 7 µs

Typ 1 sec

Sector Erase Operation (Note 2)

Max 8 sec

t

VCS

t

BUSY

VCC Set Up Time (Note 1) Min 50 µs
WE# to RY/BY# Valid Min 40 40 50 60 ns

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

30 Am29F016D

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

t

WC

Addresses

CE#

555h

t

CH

OE#

t

WP

WE#

t

CS

t

DS

t

DH

Data

A0h

RY/BY#

t

VCS

V

CC

Note: PA = program address, PD = program data, D

Figure 11. Program Operation Timings

Read Status Data (last two cycles)

t

AS

PA PA

t

AH

t

WPH

PD

t

BUSY

is the true data at the program address.

OUT

t

WHWH1

PA

Status

D

OUT

t

RB

Am29F016D 31

AC CHARACTERISTICS

t

AS

555h for chip erase

Addresses

t

WC

2AAh SA

CE#

t

t

WP

t

DS

55h

CH

t

WPH

t

DH

10 for Chip Erase

OE#

WE#

Data

t

CS

RY/BY#

t

VCS

V

CC

Note:

SA = Sector Address. VA = Valid Address for reading status data.

Figure 12. Chip/Sector Erase Operation Timings

VA

t

AH

t

WHWH2

30h

t

BUSY

Progress

VA

In

Complete

t

RB

32 Am29F016D

AC CHARACTERISTICS

Addresses

CE#

t

CH

OE#

t

WE#

DQ7

OEH

t

ACC

t

CE

t
VA

t

RC

OE

t

t

OH

Complement

DF

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High Z

RY/BY#

Note:

V A = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 13. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

t

CH

t

BUSY

t

OEH

High Z

t

ACC

VA

t

CE

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note:

V A = Valid address; not required f or DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.

Figure 14. Toggle Bit Timings (During Embedded Algorithms)

Am29F016D 33

AC CHARACTERISTICS

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Erase

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase
Suspend
Program

Erase Suspend

Read

Erase

Resume

Erase

Erase

Complete

Note:

The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended
sector.

Figure 15. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std Description Unit

t

t

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

RESET# Setup Time for Temporary Sector

RSP

Unprotect

Min 4 µs

Note:

Not 100% tested.

RESET#

CE#

WE#

RY/BY#

12 V

0 or 5 V

t

VIDR

Program or Erase Command Sequence

t

RSP

Figure 16. Temporary Sector Group Unprotect Timings

t

VIDR

0 or 5 V

34 Am29F016D

AC CHARACTERISTICS
Erase and Program Operations

Alternate CE# Controlled Writes

Parameter Symbol

Parameter Description

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1

t

WC

t

AS

t

AH

t

DS

t

DH

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

WHWH1

Write Cycle Time (Note 1) Min 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 40 45 50 50 ns
Data Setup Time Min 40 45 50 50 ns
Address Hold Time Min 0 ns
Read Recover Time Before Write Min 0 ns
CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 40 45 50 50 ns
Write Pulse Width High Min 20 ns
Byte Programming Operation (Note 2) Typ 7 µs

Typ 1 sec

t

WHWH2

t

WHWH2

Sector Erase Operation (Note 2)

Max 8 sec

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Speed Options

UnitJEDEC Std -70 -90 -120 -150

Am29F016D 35

AC CHARACTERISTICS

XXX for program
XXX for erase

PA for program
SA for sector erase
XXX for chip erase

Data# Polling

Addresses

WE#

OE#

CE#

Data

RESET#

RY/BY#

PA

t

WC

t

WH

t

WS

t

RH

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

BUSY

PD for program
30 for sector erase
10 for chip erase

t

WHWH1 or 2

DQ7# D

OUT

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

2. Figure indicates the last two bus cycles of the command sequence.

Figure 17. Alternate CE# Controlled Write Operation Timings

= Array Data.

OUT

36 Am29F016D

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 8 sec
Chip Erase Time 32 256 sec
Byte Programming Time 7 300 µs

Chip Programming Time (Note 3) 14.4 43.2 sec

Excludes 00h programming prior to
erasure (Note 4)

Excludes system-level overhead
(Note 5)

Notes:

°

1. Typical program and erase times assume the following conditions: 25

C, 5.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 4.5 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to ex ecute the four-bus-cycle sequence for programming. See Table 6 f or further
information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Min Max

Input Voltage with respect to V

Current –100 mA +100 mA

V

CC

on I/O pins –1.0 V VCC + 1.0 V

SS

Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

Input Capacitance VIN = 0 6 7.5 pF

IN

Output Capacitance V
Control Pin Capacitance VIN = 0 7.5 9 pF

= 0 8.5 12 pF

OUT

C

C

C

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

Am29F016D 37

PHYSICAL DIMENSIONS

TS 040—40-Pin Standard Thin Small Outline Package

38 Am29F016D

Dwg rev AA; 10/99

PHYSICAL DIMENSIONS (continued)

TSR040—40-Pin Reverse Thin Small Outline Package

Dwg rev AA; 10/99

Am29F016D 39

PHYSICAL DIMENSIONS (continued)

TS 048—48-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

40 Am29F016D

PHYSICAL DIMENSIONS (continued)

TSR048—48-Pin Reverse Thin Small Outline Package

Dwg rev AA; 10/99

Am29F016D 41

PHYSICAL DIMENSIONS (continued)

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

42 Am29F016D

REVISION SUMMARY
Revision A (May 1997)

Initial release of Am29F016B (0.35 µm) device.

Revision B (January 1998)

Global

Made formatting and layout consistent with other data
sheets. Used updated common tables and diagr ams.

Revision B+1 (January 1998)

AC Characteristics—Read-only Operations

Deleted note referring to output driver disable time.

Figure 16—Temporary Sector Group Unprotect
Timings

Corrected title to indicate “sector group. ”

Revision B+2 (April 1998)

Global

Added -70 speed option, deleted -75 speed option.

Distinctive Characteristics

Changed minimum 100K wr ite/erase cycles guaran­teed to 1,000,000.

Ordering Information

Added extended temperature availability to -90, -120,
and -150 speed options.

Operating Ranges

Added extended temperature range.

DC Characteristics, CMOS Compatible

Corrected the CE# and RESET# test conditions for

and I

I

CC3

AC Characteristics

Erase/Program Operations; Erase and Program Oper­ations Alternate CE# Controlled Writes:

notes reference f or t
eters are 100% tested. Corrected the note ref erence for

. This parameter is not 100% tested.

t

VCS

Temporary Sector Unprotect Table

Added note reference for t
100% tested.

Erase and Programming Performance

Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.

to VCC ±0.5 V.

CC4

WHWH1

Corrected the

and t

. This parameter is not

VIDR

WHWH2

. These param-

Revision C (January 1999)

Global

Updated for CS39S process technology.

Distinctive Characteristics

Added:

■ 20-year data retention at 125°C
— Reliable operation for the life of the system

DC Characteristics—CMOS Compatible

I

, I

CC3

I

CC4

: Added Note 4, “For CMOS mode only I

CC4

= 20 µA at extended temperature (>+85°C)”.

CC3

DC Characteristics—TTL/NMOS Compatible and
CMOS Compatible

I

, I

, I

,

I

CC1

CC2

CC3

specifications are tested with VCC = V

I

,

I

CC3

: Deleted VCC = VCCMax.

CC4

: Added Note 2 “Maximum I

CC4

CCmax

”.

CC

Revision C+1 (March 23, 1999)

Operating Ranges

The temperature ranges are now specifi ed as ambient.

Revision C+2 (May 17, 1999)

Product Selector Guide

Corrected the t

specification for the -150 speed op-

OE

tion to 55 ns.

Operating Ranges

VCC Supply Voltages

: Added “V

for ± 5% devices .

CC

+4.75 V to +5.25 V”.

Revision C+3 (July 2, 1999)

Global

Added referenc es to availability of device in K nown
Good Die (KGD) form.

Revision D (November 16, 1999)

AC Characteristics—Figure 11. Program
Operations Timing and Figure 12. Chip/Sector
Erase Operations

Deleted t
high.

Physical Dimensions

Replaced figures with more detailed illustrations.

and changed OE# waveform to start at

GHWL

,

43 Am29F016D

Revision E (May 19, 2000)

Global

Changed part number to Am29F016D . This refl ects the

new 0.23 µm process technology upon which this de­vice will now be built.

The Am29F016D is compatible with the previous 0.32
µm Am29F016B device, with the exception of the sec­tor group protect and unprotect algorithms. Th ese algo­rithms are provided in a seperate document. Contac t
AMD for more information or to request a copy of that
document.

This data sheet will be marked preliminary until the de­vice has been in full production f or a number of months .

The -75 speed option (70 ns, ±5% V
placed by a -70 speed option (70 ns, ±10 V

The burn-in option is no longer available.
The device now has the Unlock Bypass Program fea-

ture.

) has been re-

CC

CC

).

The publication number of the document describing
sector protectio n/unprotection im plementation is now

23922.

Revision E+1 (December 4, 2000)

Global

Added table of contents. Removed Preliminary status
from document.

Revision E+2 (March 23, 2001)

Common Flash Memory Interface (CFI)

Added section.

Table 9, Am29F016D Command Definitions

Corrected the addresses for the three-cycle unlock by­pass command sequence. Added Note 9 and CFI
Query command to table.

Copyright © 2001 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29F016D 44