FUJITSU Am29DL640G Service Manual
Am29DL640G
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new and current designs,
S29JL064H (for TSOP packa ges) and S29PL064J (for FBGA packages) supersed e AM29DL640G as
the factory-recommended migration path. Please refer to each res pective datasheets f or specifica tions and ordering information. Availability of this docum ent is re tained for ref eren ce and historical
purposes only.
April 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the documen t is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional inf ormation about Spansion
memory solutions.
Publication Number 25693 Revision B Amendment 5 Issue Date June 6, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29DL640G
64 Megabit (8 M x 8-Bit/4 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29JL064H (for TSOP packages) and S29PL064J (for FBGA packages) supersede
AM29DL640G as the factory-reco mmended m igration path. Ple ase ref er to ea ch res pectiv e data sheets f or s pecifi cations a nd or deri ng inf ormation. Availability of this document is retained
for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■ Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
TM
■ Flexible Bank
— Read may occur in any of the three banks not being
written or erased.
— Four banks may be grouped by customer to achieve
desired bank divisions.
■ Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
■ Manufactured on 0.17 µm process technology
■ SecSi™ (Secured Silicon ) Sect or : Ext ra 256 Byte
sector
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
— Customer lockable: One-time programmable only.
Once locked, data cannot be changed
■ Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
architecture
PACKAGE OPTIONS
■ 63-ball Fine Pitch BGA
■ 64-ball Fortified BGA
■ 48-pin TSOP
PERFORMANCE CHARACTERISTICS
■ High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate
function
■ Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■ Minimum 1 million erase cycles guaranteed per
sector
■ 20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■ Data Management Softwa re (DM S)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■ Supports Common Flash Memory Interface (CFI)
■ Erase Suspend/Erase Resume
— Suspends erase operations to allow reading from
other sectors in same bank
■ Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■ Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDW ARE FEATURES
■ Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■ Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
■ WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
■ Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing dat a in
protected sectors in-system
Publication# 25693 Rev: B Amendment 5
Issue Date: June 6, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29DL640G is a 64 megabit, 3.0 volt-only flash
memory device, organized as 4,194,304 words of 16
bits each or 8,388,608 bytes of 8 bits each. Word
mode data appears on DQ15–DQ0; byte mode data
appears on DQ7–DQ0. The device is designed to be
programmed in-system with the standard 3.0 volt V
CC
supply, and can also be programmed in standard
EPROM programmers.
The device is available with an access time of 70, 90,
or 120 ns and is offered in 48-pin TSOP, 63-ball
Fine-Pitch BGA , and 64 -bal l Fortifi ed B GA packages.
Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal
read and write operations, and avoid bus contentio n
issues.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally generated and regulate d voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simult aneous R ead/W rite a rchitect ure pr ovides
simultaneous operation by dividing the memory
space into four banks, two 8 Mb banks with small and
large sectors, and two 24 Mb banks of large sectors.
Sector addresse s are fixed, system so ftware can be
used to form user-defined bank groups.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can improve overall system performance by allowing a host
system to program or erase in one bank, then
immediately and simultaneousl y read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The Am29DL64 0G can be orga nized as both a to p
and bottom boot sector configuration.
Bank Megabits Sector Sizes
Bank 1 8 Mb
Bank 2 24 Mb Forty-eight 64 Kbyte/32 Kword
Bank 3 24 Mb Forty-eight 64 Kbyte/32 Kword
Bank 4 8 Mb
Eight 8 Kbyte/4 Kword,
Fifteen 64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
Fifteen 64 Kbyte/32 Kword
Am29DL640G Features
The SecSi™ (Secured Silicon) Sector is an extra
256 byte sector capable of being permanently locked
by AMD or customers. The SecSi Indicator Bit (DQ7)
is permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, cus-
tomer lockable parts can never be used to replace a
factory locked part.
Factory locked part s provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, read ing an d writin g like any
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software) allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file str uctures,
as opposed to single-byte modifications. To write or
update a particular p iece of data ( a phon e number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is an advantage compared to systems where
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software
does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are wr itten to the comma nd
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically re tur ns
to the read mode.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
detector that automatically inhibits write opera-
V
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sector s of memory. This can be achieved in-system or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly reduced in both modes.
2 Am29DL640G June 6, 2005
TABLE OF CONTENTS
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 5
Block Diag ra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for BGA Packages .....................7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29DL640G Device Bus Operati o n s ..............................10
Word/Byte Configuration ........................................................ 10
Requirements for Reading Array Data ...................................10
Writing Commands/Command Sequences ............................11
Accelerat ed P ro g r a m Op era t io n ...... ... .. ................. .. ...............11
Autoselect Functions ..............................................................11
Simultaneous Read/Write Operations with Zero Latency .......11
Standby Mode........................................................................ 11
Automatic Sleep Mode ...........................................................12
RESET#: Hardware Reset Pin ...............................................12
Output Disable Mode ..............................................................12
Table 2. Am29DL640G Sector Architecture ....................................12
Table 3. Bank Address ....................................................................15
Table 4. SecSi
Autoselect Mode..................................................................... 15
Table 5. Am29DL640G Autoselect Codes, (High Voltage Method) 16
Sector/Sector Block Protection and Unprotection.................. 17
Table 6. Am29DL640G Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................................17
Write Protect (WP#) ................................................................17
Table 7. WP#/ACC Modes ..............................................................18
Temporary Sector Unprotect ..................................................18
Figure 1. Temporary Sector Unprotect Operation........................... 18
Figure 2. In-System Sect o r Pr ot e ct/Unprotect Algorithms.............. 19
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 20
Figure 3. SecSi Sector Protect Verify.............................................. 21
Hardware Data Protection ......................................................21
Low VCC Write In h ibi t ................. ................ ... ................ ... .....21
Write Pulse “Glitch” Protection ...............................................21
Logical Inhibit ..........................................................................21
Power-Up Write Inhibit ............................................................21
Common Flash Memory Interface (CFI). . . . . . . 21
Table 8. CFI Query Identification String.......................................... 22
Table 9. System Interface String......................................................22
Table 10. Device Geometry Definit ion.................................... ........ 23
Table 11. Primary Vendor-Specific Extended Query...................... 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................25
Reset Command ............................................ .........................25
Autoselect Command Sequence ....................... .....................25
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence ..............................................................25
Byte/Word Program Command Sequence .............................26
Unlock Bypass Command Sequence .....................................26
Figure 4. Program Operat io n.................................... ...................... 27
Chip Erase Command Sequence ...........................................27
Sector Erase Command Sequence ........................................27
Figure 5. Erase Operation........... ................................... ................. 28
TM
Sector Addresses................................................15
Erase Suspend/Erase Resume Commands ...........................28
Table 12. Am29DL640G Command Definitions............................. 29
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 30
DQ7: Data# Po l lin g ............. .. .. ................. ................ ...............30
Figure 6. Data# Polling Algorithm................. ................................. 30
RY/BY#: Ready/Busy#............................................................ 31
DQ6: Toggle Bit I ....................................................................31
Figure 7. Toggle Bit Algorithm........................................................ 31
DQ2: Toggle Bit II ...................................................................32
Reading Toggle Bits DQ6/DQ2 ...............................................32
DQ5: Exceeded Timing Limits ................................................32
DQ3: Sector Era s e Time r ..................... ... ................ ... ............32
Table 13. Write Operation Sta tus ............. .................................. .... 33
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 34
Figure 8. Maximum Negative Overshoot Waveform...................... 34
Figure 9. Maximum Positi ve Overshoot Waveform........................ 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. I
AutomaticSleep Currents)................................... .......................... 36
Figure 11. Typical I
Current vs. Time (Showing Active and
CC1
vs. Frequency............................................ 36
CC1
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Test Setup.................................................................... 37
Figure 13. Input Waveforms and Measurement Levels................. 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Read-Only Operations ........................................................... 38
Figure 14. Read Operation Timings.. .............................. ............... 38
Hardware Reset (RESET#) .................................... .. ..............39
Figure 15. Reset Timings............................................................... 39
Word/Byte Configuration (BYTE#) ..........................................40
Figure 16. BYTE# Timings for Read Operations............................ 40
Figure 17. BYTE# Timings for Write Operations............................ 40
Erase and Program Operations .............................................. 41
Figure 18. Program Operation Timings.......................................... 42
Figure 19. Accelerated Program Timing Diagram.......................... 42
Figure 20. Chip/Sector Erase Operation Timings .......................... 43
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 44
Figure 22. Data# Polling Timings (During Embedded Algorithms). 44
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 24. DQ2 vs. DQ6.............................................. ................... 45
Temporary Sector Unprotect ..................................................46
Figure 25. Temporary Sector Unprotect Timing Diagram.............. 46
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram............................................................. 47
Alternate CE# Controlled Erase and Program Operations .....48
Figure 27. Alternate CE# Controlled Write (Erase/Program)
OperationTimings.......................................................................... 49
Erase And Programming Performan ce. . . . . . . . 50
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 50
TSOP & BGA Pi n C a pa citance. . . . . . . . . . . . . . . 50
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 52
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
12 x 11 mm package ..............................................................52
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
13 x 11 mm package ..............................................................53
TS 048—48-Pin S ta n dar d TSOP . .. ... ................ ... ................ ...54
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
June 6, 2005 Am29DL640G 3
PRODUCT SELECTOR GUIDE
Part Number Am29DL640G
Speed Option Standard Voltage Range: V
Max Access Time (ns), t
CE# Access (ns), t
OE# Access (ns), t
ACC
CE
OE
BLOCK DIAGRAM
V
CC
V
SS
Mux
A21–A0
A21–A0
RESET#
WE#
CE#
BYTE#
WP#/ACC
DQ0–DQ15
RY/BY#
A21–A0A21–A0
STATE
CONTROL
&
COMMAND
REGISTER
Bank 1 Address
Bank 2 Address
= 2.7–3.6 V 70 90 120
CC
70 90 120
70 90 120
30 35 50
OE# BYTE#
Bank 1
X-Decoder
Y-gate
Bank 2
X-Decoder
Status
Control
X-Decoder
DQ15–DQ0
DQ15–DQ0
DQ15–DQ0
Mux
A21–A0
Mux
Bank 3 Address
Bank 4 Address
Bank 3
X-Decoder
Bank 4
Y-gate
DQ15–DQ0
DQ15–DQ0
4 Am29DL640G June 6, 2005
CONNECTION DIAGRAMS
RESET#
WP#/ACC
RY/BY#
A8 B8
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin Standard TSOP
63-Ball Fine-Pitch BGA (FBGA)
Top View, Balls Facing Down
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
CE#
A0
L8
NC* NC*NC* NC*
SS
CC
SS
M8
C7 D7A7 B7
NC* NC*
C6 D6 E6 F6 G6 H6 J6 K6
C5 D5 E5 F5 G5 H5 J5 K5
C4 D4 E4 F4 G4 H4 J4 K4
C3 D3 E3 F3 G3 H3 J3 K3
A2
A1 B1
NC* NC* NC* NC*
C2 D2 E2 F2 G2 H2 J2 K2
* Balls are shorted together via the substrate but not connected to the die.
E7 F7 G7 H7 J7 K7 L7
BYTE#A16A15A14A12A13
DQ15/A
DQ13 DQ6DQ14DQ7A11A10A8A9
V
CC
DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
CE#A0A1A2A4A3
OE#
V
-
1
DQ4DQ12DQ5A19A21RESET#WE#
V
SS
SS
NC* NC*
L2
NC* NC*NC*
L1
M7
M2
M1
June 6, 2005 Am29DL640G 5
CONNECTION DIAGRAMS
64-Ball Fortified BGA
Top View, Balls Facing Down
A8
NC
A7
A13
A6
A9
A5
WE#
A4
RY/BY#
A3
A7
A2
A3
A1
NC
B8 C8 D8 E8 F8 G8 H8
NCNCNC
B7 C7 D7 E7 F7 G7 H7
B6 C6 D6 E6 F6 G6 H6
B5 C5 D5 E5 F5 G5 H5
B4 C4 D4 E4 F4 G4 H4
B3 C3 D3 E3 F3 G3 H3
B2 C2 D2 E2 F2 G2 H2
B1 C1 D1 E1 F1 G1 H1
SS
DQ15BYTE#A16A15A14A12
DQ13DQ14DQ7A11A10A8
DQ12DQ5A19A21RESET#
CC
OE#CE#A0A1A2A4
NCNCNCV
V
SS
DQ6
DQ4V
DQ3DQ11DQ10DQ2A20A18WP#/ACC
DQ1DQ9DQ8DQ0A5A6A17
V
SS
NCNCNCNCNCNCNC
Special Handling Instructions for BGA
Packages
Special handling is required for Flash Memory products
and/or data integrity may be compromised if th e
package body is exposed to temperatures above
°C for prolonged periods of time.
150
in molded packages (TSOP and BGA). The package
6 Am29DL640G June 6, 2005
PIN DESCRIPTION
A21–A0 = 22 Addresses
DQ14–DQ0 = 15 Data Inputs/Outputs (x16-only de-
vices)
DQ15/A-1 = DQ15 (Data Input/Out put, word mode)
A-1 (LSB Address Input, byte mode)
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
WP#/ACC = Hardware Write Protect/
Acceleration Pin
RESET# = Hardware Reset Pin, Active Low
BYTE# = Selects 8-bit or 16-bit mode
RY/BY# = Ready/Busy Output
= 3.0 volt-only single power supply
V
CC
V
SS
NC = Pin Not Connected Internally
(see Product Selector Guide for speed
options and voltage supply t olerances)
= Devi ce Ground
LOGIC SYMBOL
22
A21–A0
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
16 or 8
DQ15–DQ0
(A-1)
RY/BY#
June 6, 2005 Am29DL640G 7
ORDERING INFORMATION
Standard Pro ducts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29DL640G 70 E I
OPTIONAL PROCESSING
Blank = Standard Processing
N = 16-byte ESN devices
(Contact an AMD representative for more information)
TEMPERATURE RANGE
I = Industrial (–40
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)
PC = 64-Ball Fortified Ball Grid Array
1.0 mm pitch, 13 x 11 mm package (LAA064)
WH = 63-Ball Fine-P itch Ball Grid Array
0.80 mm pitch, 12 x 11 mm package (FBE063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
°C to +85°C)
DEVICE NUMBER/DESCRIPTION
Am29DL640G
64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations for TSOP Packages
Am29DL640G70
Am29DL640G90
Am29DL640G120 EI, EE
Valid Combinations
Valid Combinations list configurations planned to be supported in
volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on
newly released combinations.
EI
Valid Combinations for BGA Packages
Order Number Package Marking
Am29DL640G70
Am29DL640G90
Am29DL640G120
PCI D640G70P I
WHI D640G70V
PCI D640G90P
WHI D640G90V
PCI,
D640G12P
WHI
PCE,
WHE
D640G12V
I, E
8 Am29DL640G June 6, 2005
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addre ssable memor y location. The register is a latch used to store the commands, along with the address and da ta information
needed to execute the command. The contents of the
Table 1. Am29DL640G Device Bus Operations
register serve as in puts to the inter nal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
DQ15–DQ8
Addresses
Operation CE# OE# WE# RESET# WP#/ACC
Read L L H H L/H A
Write L H L H (Note 3) A
±
V
Standby
Output Disable L H H H L/H X High-Z High-Z High-Z
Reset X X X L L/H X High-Z High-Z High-Z
Sector Protect (Note 2) L H L V
Sector Unprotect (Note 2) L H L V
Temporary Sector
Unprotect
CC
0.3 V
XX
XXX V
VCC ±
0.3 V
ID
ID
ID
L/H X High-Z High-Z High-Z
L/H
(Note 3)
(Note 3) A
(Note 2)
IN
IN
SA, A6 = L,
A1 = H, A0 = L
SA, A6 = H,
A1 = H, A0 = L
IN
BYTE#
= V
IH
D
OUT
D
IN
XXD
XXD
D
IN
BYTE#
= V
IL
DQ8–DQ14 =
High-Z, DQ15 = A-1
High-Z D
DQ7–
DQ0
D
OUT
D
IN
IN
IN
IN
Legend: L = Logic Low = VIL, H = Logic Hi g h = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
= Address In, DIN = Data In, D
A
IN
= Data Out
OUT
Notes:
1. Addresses are A21:A0 in word mode (BYTE# = V
), A21:A-1 in byte mode (BYTE# = VIL).
IH
2. The sector prot ect a nd sect or unpr otect functi ons may also be implemented via prog r amming e quipment. See the “Sec tor/Sec tor Block Protection and Unprote ction” secti on.
3. If WP#/ACC = V
, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141
IL
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection
and Unprotection”. If WP#/ACC = V
, all sectors will be unprotected.
HH
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word co nfiguration. If th e
BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and control led by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ14–DQ8 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at V
. The BYTE# pin determines
IH
whether the device outputs array data in words or
bytes.
The internal state machine is set for rea ding arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
. CE# is the power
IL
content occurs during the power transition. No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
June 6, 2005 Am29DL640G 9
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC Read-Only Operations table for timing
specifications and to Figure 14 for the timing diagram.
in the DC Characteristics table represents the ac-
I
CC1
tive current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The
“Byte/Word Program Command Se quence” sec tion
has details on programming data to the device using
both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire de vi ce. Table 2 indicates the address
space that each sector occupies. Similar ly, a “sector
address” is the address bits required to uniquel y select
a sector. The “Com mand D efin itions” sectio n ha s details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
The device address space is divided into four bank s. A
“bank address” is the address bits required to uniquely
select a bank.
I
CC2
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is pr imarily intended to allow faster manufacturing throug hput
at the factory.
If the system as ser t s V
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected s ectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program comman d sequenc e
, and OE# to VIH.
IL
in the DC Characteristics table represents the ac-
on this pin, the device auto-
HH
as required by the Unlock Bypass mode. Removing
from the WP#/ACC pin retur ns the device to nor-
V
HH
mal operation. Note that V
must not be asserted on
HH
WP#/ACC for operations other than accelerated programming, or device damage may result. In addition,
the WP#/ACC pin must not be left floating or un connected; inconsistent behavior of the device may result.
See “Write Protect (WP#)” on page 16 for related information.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mod e. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
Simultaneous Read/Write Operations with
Zero Lat ency
This device is capa ble of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be suspended to read from or program to another location
within the same bank (except the s ector being
erased). Figure 21 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. I
CC6
and I
in the DC Characteristics table
CC7
represent the current specifications for read-while-program and read-while-erase, respectively.
Standby Mode
When the system is no t reading or wr iting to the de vice, it can place the device in the standby mode. In
this mode, current consum ption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricte d voltage range than
.) If CE# and RESET# are held at VIH, but not within
V
IH
± 0.3 V, the device will be in the standby mode,
V
CC
but the standby current will be greater. The device requires standard access time (t
) for read access
CE
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
in the DC Characteristics table represents th e
I
CC3
standby current specification.
± 0.3 V.
CC
10 Am29DL640G June 6, 2005
Automatic Sleep Mode
The automatic sleep mode minimizes Fl ash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses ar e change d. While i n sleep m ode, outpu t
data is latched and always available to the system.
in the DC Character istics table represents the
I
CC5
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of r esetting the device to reading array data. When the RESET# pin is driven low for at least a period of t
device immediately ter minates any operation in
progress, tristates all output pins, and ignores all
read/write com mands for the durati on of the RESE T#
pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
±0.3 V, the device
SS
RP
, the
draws CMOS standby cu rrent ( I
but not within VSS±0.3 V, the standby current will
at V
IL
). If RESET# is held
CC4
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re mains a “0” ( busy) until the
internal reset operation is complete, which requires a
time of t
(during Embedded Algorithms). The sys-
READY
tem can thus monitor RY/BY# to deter mine w hether
the reset operation is c omplete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read d ata t
SET# pin returns to V
(not during Embedde d Algo-
READY
.
IH
after the RE-
RH
Refer to the AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the devic e is
disabled. The output pins are placed in the high
impedance state.
Bank Sector
Bank 1
Table 2. Am29DL640G Sector Architecture
Sector Address
A21–A12
SA0 0000000000 8/4 000000h–001FFFh 00000h–00FFFh
SA1 0000000001 8/4 002000h–003FFFh 01000h–01FFFh
SA2 0000000010 8/4 004000h–005FFFh 02000h–02FFFh
SA3 0000000011 8/4 006000h–007FFFh 03000h–03FFFh
SA4 0000000100 8/4 008000h–009FFFh 04000h–04FFFh
SA5 0000000101 8/4 00A000h–00BFFFh 05000h–05FFFh
SA6 0000000110 8/4 00C000h–00DFFFh 06000h–06FFFh
SA7 0000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh
SA8 0000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh
SA9 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh
SA10 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh
SA11 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh
SA12 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh
SA13 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh
SA14 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh
SA15 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh
SA16 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh
SA17 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh
SA18 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh
SA19 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh
SA20 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh
SA21 0001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh
SA22 0001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
June 6, 2005 Am29DL640G 11
Bank Sector
SA23 0010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh
SA24 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh
SA25 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh
SA26 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh
SA27 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh
SA28 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh
SA29 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh
SA30 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh
SA31 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh
SA32 0011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh
SA33 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA34 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
SA35 0011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7F FFh
SA36 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA37 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
SA38 0011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh
SA39 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh
SA40 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA41 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA42 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA43 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA44 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA45 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
Bank 2
SA46 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA47 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA48 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA49 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA50 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA51 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA52 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA53 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA54 0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
SA55 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA56 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA57 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA58 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA59 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA60 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA61 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA62 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA63 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA64 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA65 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA66 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA67 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA68 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA69 0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA70 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh
Table 2. Am29DL640G Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
12 Am29DL640G June 6, 2005
Bank Sector
SA71 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh
SA72 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh
SA73 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh
SA74 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh
SA75 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh
SA76 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh
SA77 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh
SA78 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh
SA79 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh
SA80 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh
SA81 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh
SA82 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh
SA83 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh
SA84 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh
SA85 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh
SA86 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh
SA87 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh
SA88 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh
SA89 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh
SA90 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh
SA91 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh
SA92 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh
SA93 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh
Bank 3
SA94 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh
SA95 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh
SA96 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh
SA97 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh
SA98 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh
SA99 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh
SA100 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh
SA101 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh
SA102 1011111xxx 64/32 5F0000h–5FFFFFh 2F 8000h–2FFFFFh
SA103 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh
SA104 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh
SA105 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh
SA106 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh
SA107 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh
SA108 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh
SA109 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh
SA110 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh
SA111 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh
SA112 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh
SA113 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh
SA114 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh
SA115 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh
SA116 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh
SA117 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh
SA118 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh
Table 2. Am29DL640G Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
June 6, 2005 Am29DL640G 13
Bank Sector
SA119 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh
SA120 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh
SA121 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh
SA122 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh
SA123 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh
SA124 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh
SA125 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh
SA126 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh
SA127 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh
SA128 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh
SA129 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh
Bank 4
SA130 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh
SA131 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh
SA132 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh
SA133 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh
SA134 1111111000 8/4 7F0000h–7F1FFFh 3F8000h–3F8FFFh
SA135 1111111001 8/4 7F2000h–7F3FFFh 3F9000h–3F9FFFh
SA136 1111111010 8/4 7F4000h–7F5FFFh 3FA000h–3FAFFFh
SA137 1111111011 8/4 7F6000h–7F7FFFh 3FB000h–3FBFFFh
SA138 1111111100 8/4 7F8000h–7F9FFFh 3FC000h–3FCFFFh
SA139 1111111101 8/4 7FA000h–7FBFFFh 3FD000h–3FDFFFh
SA140 1111111110 8/4 7FC000h–7FDFFFh 3FE000h–3FEFFFh
SA141 1111111111 8/4 7FE000h–7FFFFFh 3FF000h–3FFFFFh
Table 2. Am29DL640G Sector Architecture (Continued)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Note: The address range is A21:A-1 in byte mode (BYTE#=VIL) or A21:A0 in word mode (BYTE#=VIH).
Table 3. Bank Address
Bank A21–A19
1 000
2 001, 010, 011
3 100, 101, 110
4 111
TM
Table 4. SecSi
Device Sector Size
Am29DL640G 256 bytes 000000h–0000FFh 00000h–0007Fh
Autoselect Mode
The autoselect mode provides manufacturer and device identification, a nd sector pr otection verificatio n,
through identifier codes output on DQ7–DQ0. This
mode is prima rily intende d for programming equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect
mode requires V
must be as shown in Table 5. In addition, when verifying sector protection, the sector address must appea r
on the appropriate highest order address bits (see
on address pin A9. Address pins
ID
Sector Addresses
(x8)
Address Range
Table 2). Table 5 shows the remaining address bits
that are don’t care. When all necessary bits have been
set as required, the programming equipment ma y then
read the corresponding identifier code on DQ7–DQ0.
However, the autoselect codes can also be accessed
in-system through the command register, for instances
when the Am29DL640 is erased or programmed in a
system without access to high voltage on the A9 pin.
The command sequence is illustrated in Table 12.
Note that if a Bank Address (BA) on address bits A21,
A20, and A19 is asserted during the third write cycle of
the autoselect command, the host system can read
autoselect data from that bank and then immediately
read array data from the other bank, without exit ing the
autoselect mode.
(x16)
Address Range
14 Am29DL640G June 6, 2005
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
does not require V
mand Sequence section for more information.
. Refer to the Autoselect Com-
ID
command register, as shown in Table 12. This method
Table 5. Am29DL640G Autoselect Codes, (High Voltage Method)
A21
A11
to
Description CE# OE# WE#
Manufacturer ID:
AMD
Read Cycle 1
Read Cycle 2 L H H H L 22h 02h
Device I D
Read Cycle 3 L H H H H 22h 01h
Sector Protection
Verification
SecSi Indicator Bit
(DQ7)
Legend:
L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care
LLHBAX
LLHBAX
LLHSAX
LLHBAX
A12
to
A10 A9
A8
to
A7 A6
V
XLXLLLL X X 01h
ID
V
X
ID
V
XLX HL X X
ID
V
XLXLLHH X X
ID
A5
to
A4 A3 A2 A1 A0
L
LLLH22h
X
DQ15 to DQ0
BYTE#
= V
.
IH
BYTE#
= V
X
DQ7
to
IL
DQ0
7Eh
01h (protected),
00h (unprotected)
81h (factory locked),
01h (not factory
locked)
June 6, 2005 Am29DL640G 15
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