Freescale Semiconductor MPC850, MPC850DE, MPC850SR, MPC850DSL User Manual

Freescale Semiconductor
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MPC850 Family User’s Manual
Integrated Communications Microprocessor
Supports MPC850
MPC850UM/D Rev. 1, 1/2001
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Part I—Overview
MPC850 Overview
Memory Map
Part II—PowerPC Microprocessor Module
PowerPC Core
PowerPC Core Register Set
MPC850 Instruction Set
Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
Part III—PowerPC Microprocessor Module
System Interface Unit
Reset
Part IV—Hardware Interface
External Signals
External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
I
1 2
II
3 4 5 6 7 8 9
III
10 11
IV
12 13 14 15 16
III
IV
I
1 2
II
3 4 5 6 7 8 9
10 11
12 13 14 15 16
Part I—Overview
MPC850 Overview Memory Map
Part II—PowerPC Microprocessor Module
PowerPC Core PowerPC Core Register Set MPC850 Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing
Part III—PowerPC Microprocessor Module
System Interface Unit Reset
Part IV—Hardware Interface
External Signals External Bus Interface Clocks and Power Control Memory Controller PCMCIA Interface
Part V—Communications Processor Module
Communications Processor Module and Timers
Communications Processor
SDMA Channels and IDMA Emulation
Serial Interface
SCC Introduction
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC Asynchronous HDLC Mode and IrDA
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
IrDA Mode—SCC2 Only
Serial Management Controllers
Serial Peripheral Interface
Universal Serial Bus Controller
2
I
C Controller
Parallel I/O Ports
CPM Interrupt Controller
Part VI—Asynchronous Transfer Mode
ATM Overview
Buffer Descriptors and Connection Tables
ATM Parameter RAM
ATM Controller
ATM Pace Control
ATM Exceptions
Interface Configuration
UTOPIA Interface
Part VII—System Debugging and Testing Support
System Development and Debugging
IEEE 1149.1 Test Access Port
Byte Ordering
Serial Communication Performance
Register Quick Reference Guide
Instruction Set Listings
MPC850
MPC850DSL
Glossary
Index
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
36 37 38 39 40 41 42 43
43
44 45
43
GLO
IND
V
VI
VII
A B C D E
F
I
V
VI
VII
A B C D E
F
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
36 37 38 39 40 41 42 43
43
44 45
43
GLO
IND
Part V—Communications Processor Module
Communications Processor Module and Timers Communications Processor SDMA Channels and IDMA Emulation Serial Interface SCC Introduction SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode
SCC Transparent Mode IrDA Mode—SCC2 Only Serial Management Controllers Serial Peripheral Interface Universal Serial Bus Controller I2C Controller Parallel I/O Ports CPM Interrupt Controller
Part VI—Asynchronous Transfer Mode
ATM Overview Buffer Descriptors and Connection Tables ATM Parameter RAM ATM Controller ATM Pace Controller ATM Exceptions
Interface Configuration UTOPIA Interface
Part VII—System Debugging and Testing Support
System Development and Debugging IEEE 1149.1 Test Access Port Byte Ordering
Serial Communication Performance Register Quick Reference Guide
Instruction Set Listings
MPC850
MPC850DSL
Glossary
I
Index
CONTENTS
Paragraph Number
Title
Page
Number
Part I
Overview
Chapter 1
Overview
1.1 Features............................................................................................................... 1–2
1.2 Overview of Major Components ........................................................................ 1–7
1.2.1 PowerPC Microprocessor Module.................................................................. 1–8
1.2.2 Configuration and Reset ................................................................................. 1–8
1.2.2.1 System Interface Unit (SIU) ....................................................................... 1–8
1.2.2.2 Resets.......................................................................................................... 1–9
1.2.3 MPC850 Hardware Interface ........................................................................ 1–10
1.2.3.1 Signals....................................................................................................... 1–11
1.2.3.2 Clocking and Power Management............................................................ 1–13
1.2.3.3 Memory Controller ................................................................................... 1–14
1.2.4 Communications Processor Module (CPM) ................................................. 1–15
1.2.5 System Debugging and Testing Support ...................................................... 1–17
1.3 Differences between the MPC850 Family and MPC860.................................. 1–17
Chapter 2
Memory Map
Part II
PowerPC Microprocessor Module
Chapter 3
The PowerPC Core
3.1 The MPC850 Core as a PowerPC Implementation............................................. 3-1
3.2 PowerPC Architecture Overview........................................................................ 3-1
3.2.1 Levels of the PowerPC Architecture .............................................................. 3-3
3.3 Features............................................................................................................... 3-4
3.4 Basic Structure of the Core ................................................................................. 3-5
3.4.1 Instruction Flow.............................................................................................. 3-6
3.4.2 Basic Instruction Pipeline ............................................................................... 3-7
3.4.3 Instruction Unit ............................................................................................... 3-7
3.4.3.1 Branch Operations ...................................................................................... 3-7
3.4.3.2 Dispatching Instructions ............................................................................. 3-9
3.5 Register Set ......................................................................................................... 3-9
3.6 Execution Units................................................................................................... 3-9
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3.6.1 Branch Processing Unit ................................................................................ 3-10
3.6.2 Integer Unit ................................................................................................... 3-10
3.6.3 Load/Store Unit............................................................................................. 3-10
3.6.3.1 Executing Load/Store Instructions ........................................................... 3-12
3.6.3.2 Serializing Load/Store Instructions .......................................................... 3-12
3.6.3.3 Store Accesses .......................................................................................... 3-12
3.6.3.4 Nonspeculative Load Instructions ............................................................ 3-13
3.6.3.5 Unaligned Accesses .................................................................................. 3-13
3.6.3.6 Atomic Update Primitives ........................................................................ 3-14
3.7 The MPC850 and the PowerPC Architecture ................................................... 3-14
Title
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Chapter 4
PowerPC Core Register Set
4.1 MPC850 Register Implementation ..................................................................... 4-1
4.1.1 PowerPC Registers—User Registers .............................................................. 4-2
4.1.1.1 PowerPC User-Level Register Bit Assignments ........................................ 4-2
4.1.1.1.1 Condition Register (CR)......................................................................... 4-2
4.1.1.1.2 Condition Register CR0 Field Definition............................................... 4-3
4.1.1.1.3 XER ........................................................................................................ 4-3
4.1.1.1.4 Time Base Registers ............................................................................... 4-4
4.1.2 PowerPC Registers—Supervisor Registers .................................................... 4-4
4.1.2.1 DAR, DSISR, and BAR Operation............................................................. 4-5
4.1.2.2 Unsupported Registers................................................................................ 4-6
4.1.2.3 PowerPC Supervisor-Level Register Bit Assignments............................... 4-6
4.1.2.3.1 Machine State Register (MSR)............................................................... 4-6
4.1.2.3.2 Processor Version Register..................................................................... 4-8
4.1.3 MPC850-Specific SPRs.................................................................................. 4-8
4.1.3.1 Accessing SPRs ........................................................................................ 4-11
4.2 Register Initialization at Reset .......................................................................... 4-11
Chapter 5
MPC850 Instruction Set
5.1 Operand Conventions.......................................................................................... 5-1
5.1.1 Data Organization in Memory and Data Transfers......................................... 5-1
5.1.2 Aligned and Misaligned Accesses .................................................................. 5-1
5.2 Instruction Set Summary..................................................................................... 5-2
5.2.1 Classes of Instructions .................................................................................... 5-3
5.2.1.1 Definition of Boundedly Undefined ........................................................... 5-4
5.2.1.2 Defined Instruction Class ........................................................................... 5-4
5.2.1.3 Illegal Instruction Class .............................................................................. 5-4
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5.2.1.4 Reserved Instruction Class ......................................................................... 5-5
5.2.2 Addressing Modes .......................................................................................... 5-5
5.2.2.1 Memory Addressing ................................................................................... 5-5
5.2.2.2 Effective Address Calculation .................................................................... 5-6
5.2.2.3 Synchronization .......................................................................................... 5-6
5.2.2.3.1 Context Synchronization ........................................................................ 5-6
5.2.2.3.2 Execution Synchronization..................................................................... 5-7
5.2.2.3.3 Instruction-Related Exceptions............................................................... 5-7
5.2.3 Instruction Set Overview ................................................................................ 5-7
5.2.4 PowerPC UISA Instructions ........................................................................... 5-8
5.2.4.1 Integer Instructions ..................................................................................... 5-8
5.2.4.1.1 Integer Arithmetic Instructions............................................................... 5-8
5.2.4.1.2 Integer Compare Instructions ................................................................. 5-9
5.2.4.1.3 Integer Logical Instructions.................................................................. 5-10
5.2.4.1.4 Integer Rotate and Shift Instructions .................................................... 5-10
5.2.4.2 Load and Store Instructions ...................................................................... 5-11
5.2.4.2.1 Integer Load and Store Address Generation......................................... 5-11
5.2.4.2.2 Register Indirect Integer Load Instructions .......................................... 5-12
5.2.4.2.3 Integer Store Instructions...................................................................... 5-12
5.2.4.2.4 Integer Load and Store with Byte-Reverse Instructions....................... 5-13
5.2.4.2.5 Integer Load and Store Multiple Instructions....................................... 5-13
5.2.4.2.6 Integer Load and Store String Instructions........................................... 5-14
5.2.4.3 Branch and Flow Control Instructions...................................................... 5-14
5.2.4.3.1 Branch Instruction Address Calculation............................................... 5-15
5.2.4.3.2 Branch Instructions............................................................................... 5-15
5.2.4.3.3 Condition Register Logical Instructions............................................... 5-16
5.2.4.4 Trap Instructions....................................................................................... 5-16
5.2.4.5 Processor Control Instructions.................................................................. 5-17
5.2.4.5.1 Move to/from Condition Register Instructions..................................... 5-17
5.2.4.6 Memory Synchronization Instructions—UISA ........................................ 5-17
5.2.5 PowerPC VEA Instructions .......................................................................... 5-19
5.2.5.1 Processor Control Instructions.................................................................. 5-19
5.2.5.2 Memory Synchronization Instructions—VEA ......................................... 5-20
5.2.5.2.1 eieio Behavior....................................................................................... 5-20
5.2.5.2.2 isync Behavior ...................................................................................... 5-20
5.2.5.3 Memory Control Instructions—VEA ....................................................... 5-21
5.2.6 PowerPC OEA Instructions .......................................................................... 5-21
5.2.6.1 System Linkage Instructions..................................................................... 5-22
5.2.6.2 Processor Control Instructions—OEA ..................................................... 5-22
5.2.6.2.1 Move to/from Machine State Register Instructions.............................. 5-22
5.2.6.2.2 Move to/from Special-Purpose Register Instructions........................... 5-22
5.2.6.3 Memory Control Instructions—OEA ....................................................... 5-23
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Chapter 6
Exceptions
6.1 Exceptions........................................................................................................... 6-2
6.1.1 Exception Ordering......................................................................................... 6-3
6.1.2 PowerPC-Defined Exceptions ........................................................................ 6-4
6.1.2.1 System Reset Interrupt (0x00100) .............................................................. 6-5
6.1.2.2 Machine Check Interrupt (0x00200) .......................................................... 6-5
6.1.2.3 DSI Exception (0x00300) ........................................................................... 6-6
6.1.2.4 ISI Exception (0x00400)............................................................................. 6-6
6.1.2.5 External Interrupt Exception (0x00500)..................................................... 6-6
6.1.2.6 Alignment Exception (0x00600) ................................................................ 6-7
6.1.2.6.1 Integer Alignment Exceptions ................................................................ 6-8
6.1.2.7 Program Exception (0x00700).................................................................... 6-9
6.1.2.8 Decrementer Exception (0x00900)........................................................... 6-10
6.1.2.9 System Call Exception (0x00C00) ........................................................... 6-10
6.1.2.10 Trace Exception (0x00D00) ..................................................................... 6-11
6.1.2.11 Floating-Point Assist Exception ............................................................... 6-12
6.1.3 Implementation-Specific Exceptions............................................................ 6-12
6.1.3.1 Software Emulation Exception (0x01000) ............................................... 6-12
6.1.3.2 Instruction TLB Miss Exception (0x01100)............................................. 6-12
6.1.3.3 Data TLB Miss Exception (0x01200)....................................................... 6-13
6.1.3.4 Instruction TLB Error Exception (0x01300) ............................................ 6-13
6.1.3.5 Data TLB Error Exception (0x014000).................................................... 6-14
6.1.3.6 Debug Exceptions (0x01C00–0x01F00) .................................................. 6-15
6.1.4 Implementing the Precise Exception Model................................................. 6-16
6.1.5 Recoverability after an Exception................................................................. 6-17
6.1.6 Exception Latency ........................................................................................ 6-18
6.1.7 Partially Completed Instructions .................................................................. 6-20
Chapter 7
Instruction and Data Caches
7.1 Instruction Cache Organization .......................................................................... 7–2
7.2 Data Cache Organization .................................................................................... 7–4
7.3 Cache Control Registers ..................................................................................... 7–6
7.3.1 Instruction Cache Control Registers ............................................................... 7–6
7.3.1.1 Reading Data and Tags in the Instruction Cache........................................ 7–8
7.3.1.2 IC_CST Commands.................................................................................... 7–9
7.3.1.2.1 Instruction Cache Enable/Disable Commands ....................................... 7–9
7.3.1.2.2 Instruction Cache Load & Lock Cache Block Command ...................... 7–9
7.3.1.2.3 Instruction Cache Unlock Cache Block Command.............................. 7–10
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7.3.1.2.4 Instruction Cache Unlock All Command ............................................. 7–11
7.3.1.2.5 Instruction Cache Invalidate All Command ......................................... 7–11
7.3.2 Data Cache Control Registers....................................................................... 7–11
7.3.2.1 Reading Data Cache Tags and Copyback Buffer ..................................... 7–14
7.3.2.2 DC_CST Commands ................................................................................ 7–15
7.3.2.2.1 Data Cache Enable/Disable Commands ............................................... 7–16
7.3.2.2.2 Data Cache Load & Lock Cache Block Command.............................. 7–16
7.3.2.2.3 Data Cache Unlock Cache Block Command........................................ 7–17
7.3.2.2.4 Data Cache Unlock All Command ....................................................... 7–17
7.3.2.2.5 Data Cache Invalidate All Command................................................... 7–17
7.3.2.2.6 Data Cache Flush Cache Block Command........................................... 7–17
7.4 PowerPC Cache Control Instructions ............................................................... 7–18
7.4.1 Instruction Cache Block Invalidate (
7.4.2 Data Cache Block Touch ( Touch for Store (
7.4.3 Data Cache Block Zero (
7.4.4 Data Cache Block Store (
7.4.5 Data Cache Block Flush (
7.4.6 Data Cache Block Invalidate (
7.5 Instruction Cache Operations............................................................................ 7–20
7.5.1 Instruction Cache Hit .................................................................................... 7–22
7.5.2 Instruction Cache Miss ................................................................................. 7–22
7.5.3 Instruction Fetching on a Predicted Path ...................................................... 7–23
7.5.4 Fetching Instructions from Caching-Inhibited Regions................................ 7–23
7.5.5 Updating Code and Memory Region Attributes ........................................... 7–24
7.6 Data Cache Operation ....................................................................................... 7–24
7.6.1 Data Cache Load Hit..................................................................................... 7–25
7.6.2 Data Cache Read Miss.................................................................................. 7–25
7.6.3 Write-Through Mode.................................................................................... 7–26
7.6.3.1 Data Cache Store Hit in Write-Through Mode......................................... 7–26
7.6.3.2 Data Cache Store Miss in Write-Through Mode...................................... 7–26
7.6.4 Write-Back Mode ......................................................................................... 7–26
7.6.4.1 Data Cache Store Hit in Write-Back Mode .............................................. 7–26
7.6.4.2 Data Cache Store Miss in Write-Back Mode ........................................... 7–27
7.6.5 Data Accesses to Caching-Inhibited Memory Regions ................................ 7–27
7.6.6 Atomic Memory References......................................................................... 7–28
7.7 Cache Initialization after Reset......................................................................... 7–29
7.8 Debug Support .................................................................................................. 7–29
7.8.1 Instruction and Data Cache Operation in Debug Mode................................ 7–30
7.8.2 Instruction and Data Cache Operation with a Software Monitor Debugger. 7–30
dcbtst
Title
icbi
)..................................................... 7–18
dcbt
) and Data Cache Block
) ...........................................................................7–18
dcbz
) ..................................................................... 7–19
dcbst
) ................................................................... 7–19
dcbf
) .................................................................... 7–20
dcbi
) ............................................................. 7–20
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Chapter 8
Memory Management Unit
8.1 Features............................................................................................................... 8–1
8.2 PowerPC Architecture Compliance .................................................................... 8–2
8.3 Address Translation ............................................................................................ 8–3
8.3.1 Translation Disabled ....................................................................................... 8–3
8.3.2 Translation Enabled ........................................................................................ 8–3
8.3.3 TLB Operation................................................................................................ 8–5
8.4 Using Access Protection Groups ........................................................................ 8–6
8.5 Protection Resolution Modes.............................................................................. 8–7
8.6 Memory Attributes.............................................................................................. 8–8
8.7 Translation Table Structure................................................................................. 8–9
8.7.1 Level-One Descriptor ................................................................................... 8–12
8.7.2 Level-Two Descriptor................................................................................... 8–13
8.7.3 Page Size....................................................................................................... 8–14
8.8 Programming Model ......................................................................................... 8–14
8.8.1 IMMU Control Register (MI_CTR) ............................................................. 8–15
8.8.2 DMMU Control Register (MD_CTR) .......................................................... 8–16
8.8.3 IMMU/DMMU Effective Page Number Register (Mx_EPN) ..................... 8–17
8.8.4 IMMU Tablewalk Control Register (MI_TWC) .......................................... 8–18
8.8.5 DMMU Tablewalk Control Register (MD_TWC) ....................................... 8–19
8.8.6 IMMU Real Page Number Register (MI_RPN) ........................................... 8–20
8.8.7 DMMU Real Page Number Register (MD_RPN) ........................................ 8–21
8.8.8 MMU Tablewalk Base Register (M_TWB) ................................................. 8–23
8.8.9 MMU Current Address Space ID Register (M_CASID).............................. 8–23
8.8.10 MMU Access Protection Registers (MI_AP/MD_AP) ................................ 8–24
8.8.11 MMU Tablewalk Special Register (M_TW) ................................................ 8–24
8.8.12 MMU Debug Registers................................................................................. 8–24
8.8.12.1 IMMU CAM Entry Read Register (MI_CAM) ........................................ 8–25
8.8.12.2 IMMU RAM Entry Read Register 0 (MI_RAM0) ................................... 8–26
8.8.12.3 IMMU RAM Entry Read Register 1 (MI_RAM1) ................................... 8–27
8.8.12.4 DMMU CAM Entry Read Register (MD_CAM)..................................... 8–27
8.8.12.5 DMMU RAM Entry Read Register 0 (MD_RAM0)................................ 8–28
8.8.13 DMMU RAM Entry Read Register 1 (MD_RAM1).................................... 8–29
8.9 Memory Management Unit Exceptions ............................................................ 8–31
8.10 TLB Manipulation ............................................................................................ 8–31
8.10.1 TLB Reload................................................................................................... 8–32
8.10.1.1 Translation Reload Examples ................................................................... 8–32
8.10.2 Locking TLB Entries .................................................................................... 8–33
8.10.3 Loading Locked TLB Entries ....................................................................... 8–34
8.10.4 TLB Invalidation........................................................................................... 8–34
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Chapter 9
Instruction Execution Timing
9.1 Instruction Execution Timing Examples ............................................................ 9–1
9.1.1 Data Cache Load with a Data Dependency .................................................... 9–1
9.1.2 Writeback Arbitration ..................................................................................... 9–2
9.1.3 Private Writeback Bus Load ........................................................................... 9–3
9.1.4 Fastest External Load (Data Cache Miss)....................................................... 9–3
9.1.5 A Full Completion Queue............................................................................... 9–4
9.1.6 Branch Instruction Handling........................................................................... 9–4
9.1.7 Branch Prediction ........................................................................................... 9–5
9.2 Instruction Timing List ....................................................................................... 9–6
9.2.1 Load/Store Instruction Timing........................................................................ 9–7
9.2.2 String Instruction Latency .............................................................................. 9–8
9.2.3 Accessing Off-Core SPRs............................................................................... 9–8
Part III
Configuration and Reset
Chapter 10
System Interface Unit
10.1 Features............................................................................................................. 10–2
10.2 System Configuration and Protection ............................................................... 10–2
10.3 Multiplexing SIU Pins ...................................................................................... 10–4
10.4 Programming the SIU ....................................................................................... 10–5
10.4.1 Internal Memory Map Register (IMMR)...................................................... 10–5
10.4.2 SIU Module Configuration Register (SIUMCR).......................................... 10–6
10.4.3 System Protection Control Register (SYPCR) ............................................. 10–8
10.4.4 Transfer Error Status Register (TESR)......................................................... 10–9
10.4.5 Register Lock Mechanism .......................................................................... 10–10
10.5 System Configuration ..................................................................................... 10–11
10.5.1 Interrupt Structure....................................................................................... 10–11
10.5.2 Priority of Interrupt Sources ....................................................................... 10–13
10.5.3 SIU Interrupt Processing............................................................................. 10–14
10.5.3.1 Nonmaskable Interrupts—IRQ0 and SWT............................................. 10–14
10.5.4 Programming the SIU Interrupt Controller................................................. 10–15
10.5.4.1 SIU Interrupt Pending Register (SIPEND) ............................................. 10–15
10.5.4.2 SIU Interrupt Mask Register (SIMASK) ................................................ 10–17
10.5.4.3 SIU Interrupt Edge/Level Register (SIEL) ............................................. 10–18
10.5.4.4 SIU Interrupt Vector Register (SIVEC) ................................................. 10–19
10.6 The Bus Monitor............................................................................................. 10–20
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10.7 The Software Watchdog Timer....................................................................... 10–21
10.7.1 Software Service Register (SWSR) ............................................................ 10–22
10.8 The PowerPC Decrementer............................................................................. 10–23
10.8.1 Decrementer Register (DEC)...................................................................... 10–24
10.9 The PowerPC Timebase.................................................................................. 10–24
10.9.1 Timebase Register (TBU and TBL)............................................................ 10–25
10.9.2 Timebase Reference Registers (TBREFA and TBREFB).......................... 10–26
10.9.3 Timebase Status and Control Register (TBSCR) ....................................... 10–26
10.10 The Real-Time Clock...................................................................................... 10–27
10.10.1 Real-Time Clock Status and Control Register (RTCSC) ........................... 10–28
10.10.2 Real-Time Clock Register (RTC) ............................................................... 10–29
10.10.3 Real-Time Clock Alarm Register (RTCAL) .............................................. 10–29
10.10.4 Real-Time Clock Alarm Seconds Register (RTSEC)................................. 10–30
10.11 The Periodic Interrupt Timer (PIT)................................................................. 10–31
10.11.1 Periodic Interrupt Status and Control Register (PISCR) ............................ 10–32
10.11.2 PIT Count Register (PITC) ......................................................................... 10–33
10.11.3 PIT Register (PITR).................................................................................... 10–33
10.12 General SIU Timers Operation ....................................................................... 10–34
10.12.1 Freeze Operation......................................................................................... 10–34
10.12.2 Low-Power Stop Operation ........................................................................ 10–34
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Chapter 11
Reset
11.1 Types of Reset................................................................................................... 11–1
11.1.1 Power-On Reset ............................................................................................ 11–2
11.1.2 External Hard Reset ...................................................................................... 11–2
11.1.3 Internal Hard Reset ....................................................................................... 11–2
11.1.3.1 PLL Loss of Lock ..................................................................................... 11–3
11.1.3.2 Software Watchdog Reset......................................................................... 11–3
11.1.3.3 Checkstop Reset........................................................................................ 11–3
11.1.4 Debug Port Hard or Soft Reset ..................................................................... 11–3
11.1.5 JTAG Reset................................................................................................... 11–3
11.1.6 Power-On and Hard Reset Sequence ............................................................ 11–4
11.1.7 External Soft Reset ....................................................................................... 11–4
11.1.8 Internal Soft Reset ........................................................................................ 11–4
11.1.9 Soft Reset Sequence...................................................................................... 11–5
11.2 Reset Status Register (RSR) ............................................................................. 11–5
11.3 MPC850 Reset Configuration........................................................................... 11–6
11.3.1 Hard Reset..................................................................................................... 11–7
11.3.1.1 Hard Reset Configuration Word ............................................................... 11–9
11.3.2 Soft Reset.................................................................................................... 11–11
11.4 TRST and Power Mode Considerations ......................................................... 11–11
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Part IV
The Hardware Interface
Chapter 12
External Signals
12.1 System Bus Signals........................................................................................... 12–5
12.2 Active Pull-Up Buffers ................................................................................... 12–18
12.3 Internal Pull-Up and Pull-Down Resistors .................................................... 12–19
12.4 Recommended Basic Pin Connections ........................................................... 12–20
12.4.1 Reset Configuration .................................................................................... 12–20
12.4.1.1 Bus Control Signals and Interrupts ......................................................... 12–20
12.4.2 JTAG and Debug Ports ............................................................................... 12–21
12.4.3 Unused Inputs ............................................................................................. 12–21
12.4.4 Unused Outputs........................................................................................... 12–21
12.5 Signal States during Hardware Reset.............................................................. 12–21
Chapter 13
External Bus Interface
13.1 Features............................................................................................................. 13–1
13.2 Bus Transfer Overview ..................................................................................... 13–1
13.3 Bus Interface Signal Descriptions..................................................................... 13–2
13.4 Bus Operations.................................................................................................. 13–6
13.4.1 Basic Transfer Protocol ................................................................................ 13–6
13.4.2 Single-Beat Transfer ..................................................................................... 13–6
13.4.2.1 Single-Beat Read Flow ............................................................................. 13–7
13.4.2.2 Single-Beat Write Flow .......................................................................... 13–10
13.4.3 Burst Transfers............................................................................................ 13–13
13.4.4 Burst Operations ......................................................................................... 13–14
13.4.5 Alignment and Data Packing on Transfers ................................................. 13–23
13.4.6 Arbitration Phase ........................................................................................ 13–26
13.4.6.1 Bus Request (BR) ................................................................................... 13–27
13.4.6.2 Bus Grant (BG)....................................................................................... 13–27
13.4.6.3 Bus Busy (BB) ........................................................................................ 13–28
13.4.6.4 External Bus Parking .............................................................................. 13–30
13.4.7 Address Transfer Phase-Related Signals .................................................... 13–30
13.4.7.1 Transfer Start (TS) .................................................................................. 13–30
13.4.7.2 Address Bus ............................................................................................ 13–31
13.4.7.3 Transfer Attributes .................................................................................. 13–31
13.4.7.3.1 Read/Write (RD/WR) ......................................................................... 13–31
13.4.7.3.2 Burst Indicator (BURST).................................................................... 13–31
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13.4.7.3.3 Transfer Size (TSIZ)........................................................................... 13–31
13.4.7.3.4 Address Types (AT) ........................................................................... 13–31
13.4.7.3.5 Burst Data in Progress (BDIP) ........................................................... 13–34
13.4.8 Termination Signals.................................................................................... 13–34
13.4.8.1 Transfer Acknowledge (TA)................................................................... 13–34
13.4.8.2 Burst Inhibit (BI) .................................................................................... 13–34
13.4.8.3 Transfer Error Acknowledge (TEA)....................................................... 13–34
13.4.8.4 Termination Signals Protocol ................................................................. 13–34
13.4.9 Memory Reservation................................................................................... 13–35
13.4.9.1 Kill Reservation (KR) ............................................................................. 13–36
13.4.10 Bus Exception Control Cycles.................................................................... 13–37
13.4.10.1 RETRY ................................................................................................... 13–38
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Chapter 14
Clocks and Power Control
14.1 Features............................................................................................................. 14–1
14.2 The Clock Module ............................................................................................ 14–2
14.2.1 External Reference Clocks............................................................................ 14–3
14.2.1.1 Off-Chip Oscillator Input (EXTCLK) ...................................................... 14–4
14.2.1.2 Crystal Oscillator Support (EXTAL and XTAL) ..................................... 14–4
14.2.2 System PLL................................................................................................... 14–5
14.2.2.1 SPLL Reset Configuration........................................................................ 14–6
14.2.2.2 SPLL Output Characteristics and Stability ............................................... 14–7
14.2.2.3 The System Phase-Locked Loop Pins (VDDSYN, VSSSYN,
VSSSYN1, XFC) ..................................................................................14–7
14.2.2.4 Disabling the SPLL................................................................................... 14–8
14.3 Clock Signals .................................................................................................... 14–8
14.3.1 Clocks Derived from the SPLL Output ........................................................ 14–9
14.3.1.1 The Internal General System Clocks (GCLK1C, GCLK2C,
GCLK1, GCLK2) ...............................................................................14–10
14.3.1.2 Memory Controller and External Bus Clocks (GCLK1_50,
GCLK2_50, CLKOUT) ......................................................................14–11
14.3.1.3 CLKOUT Special Considerations: 1:2:1 Mode...................................... 14–14
14.3.1.4 The Baud Rate Generator Clock (BRGCLK) ......................................... 14–14
14.3.1.5 The Synchronization Clock (SYNCCLK, SYNCCLKS) ....................... 14–14
14.3.2 The PIT and RTC Clock (PITRTCLK) ...................................................... 14–15
14.3.3 The Time Base and Decrementer Clock (TMBCLK)................................. 14–16
14.4 Power Distribution.......................................................................................... 14–16
14.4.1 I/O Buffer Power (VDDH) ......................................................................... 14–17
14.4.2 Internal Logic Power (VDDL).................................................................... 14–18
14.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1) ..................... 14–18
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14.4.4 Keep-Alive Power (KAPWR) .................................................................... 14–18
14.5 Power Control (Low-Power Modes)............................................................... 14–18
14.5.1 Normal High Mode..................................................................................... 14–21
14.5.2 Normal Low Mode...................................................................................... 14–21
14.5.3 Doze High Mode......................................................................................... 14–21
14.5.4 Doze Low Mode ......................................................................................... 14–22
14.5.5 Sleep Mode ................................................................................................. 14–23
14.5.6 Deep-Sleep Mode ....................................................................................... 14–23
14.5.7 Power-Down Mode..................................................................................... 14–24
14.5.7.1 Software Initiation of Power-Down Mode, with Automatic Wake-up... 14–24
14.5.7.2 Maintaining the Real-Time Clock (RTC) During
Shutdown or Power Failure ................................................................14–26
14.5.7.3 Register Lock Mechanism: Protecting SIU
Registers in Power-Down Mode..........................................................14–26
14.5.8 TMIST: Facilitating Nesting of SIU Timer Interrupts................................ 14–27
14.6 Clock and Power Control Registers................................................................ 14–27
14.6.1 System Clock and Reset Control Register (SCCR) .................................... 14–27
14.6.2 PLL, Low-Power, and Reset Control Register (PLPRCR)......................... 14–29
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Chapter 15
Memory Controller
15.1 Features............................................................................................................. 15–1
15.2 Basic Architecture............................................................................................. 15–4
15.3 Chip-Select Programming Common to the GPCM and UPM .......................... 15–6
15.3.1 Address Space Programming........................................................................ 15–7
15.3.2 Register Programming Order........................................................................ 15–7
15.3.3 Memory Bank Write Protection.................................................................... 15–7
15.3.4 Address Type Protection............................................................................... 15–7
15.3.5 8-, 16-, and 32-Bit Port Size Configuration.................................................. 15–7
15.3.6 Parity Configuration ..................................................................................... 15–8
15.3.7 Memory Bank Protection Status ................................................................... 15–8
15.3.8 UPM-Specific Registers ............................................................................... 15–8
15.3.9 GPCM-Specific Registers............................................................................. 15–8
15.4 Register Descriptions ........................................................................................ 15–9
15.4.1 Base Registers (BRx).................................................................................... 15–9
15.4.2 Option Registers (ORx) .............................................................................. 15–10
15.4.3 Memory Status Register (MSTAT) ............................................................ 15–13
15.4.4 Machine A Mode Register/Machine B Mode Registers (MxMR) ............. 15–13
15.4.5 Memory Command Register (MCR) .......................................................... 15–15
15.4.6 Memory Data Register (MDR) ................................................................... 15–16
15.4.7 Memory Address Register (MAR) ............................................................. 15–17
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15.4.8 Memory Periodic Timer Prescaler Register (MPTPR)............................... 15–18
15.5 General-Purpose Chip-Select Machine (GPCM)............................................ 15–18
15.5.1 Timing Configuration ................................................................................. 15–19
15.5.1.1 Chip-Select Assertion Timing ................................................................ 15–20
15.5.1.2 Chip-Select and Write Enable Deassertion Timing ................................ 15–21
15.5.1.3 Relaxed Timing ...................................................................................... 15–23
15.5.1.4 Output Enable (OE) Timing ................................................................... 15–26
15.5.1.5 Programmable Wait State Configuration................................................ 15–26
15.5.1.6 Extended Hold Time on Read Accesses ................................................. 15–26
15.5.2 Boot Chip-Select Operation........................................................................ 15–28
15.5.3 External Asynchronous Master Support ..................................................... 15–29
15.5.4 Special Case: Bursting with External Transfer Acknowledge: .................. 15–30
15.6 User-Programmable Machines (UPMs).......................................................... 15–31
15.6.1 Requests ...................................................................................................... 15–32
15.6.1.1 Internal/External Memory Access Requests........................................... 15–32
15.6.1.2 UPM Periodic Timer Requests ............................................................... 15–33
15.6.1.3 Software Requests—MCR run Command.............................................. 15–33
15.6.1.4 Exception Requests................................................................................. 15–33
15.6.2 Programming the UPM............................................................................... 15–34
15.6.3 Control Signal Generation Timing ............................................................. 15–34
15.6.4 The RAM Array.......................................................................................... 15–37
15.6.4.1 RAM Words............................................................................................ 15–37
15.6.4.2 Chip-Select Signals (CSTx).................................................................... 15–41
15.6.4.3 Byte-Select Signals (BSTx) .................................................................... 15–42
15.6.4.4 General-Purpose Signals (GxTx, G0x) ................................................... 15–43
15.6.4.5 Loop Control (LOOP)............................................................................. 15–44
15.6.4.6 Exception Pattern Entry (EXEN)............................................................ 15–45
15.6.4.7 Address Multiplexing (AMX) ................................................................ 15–45
15.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3) .......... 15–50
15.6.4.9 Disable Timer Mechanism (TODT) ....................................................... 15–51
15.6.4.10 The Last Word (LAST) .......................................................................... 15–51
15.6.4.11 The Wait Mechanism (WAEN) .............................................................. 15–51
15.6.4.11.1 Internal and External Synchronous Masters ....................................... 15–51
15.6.4.11.2 External Asynchronous Masters ......................................................... 15–52
15.7 Handling Devices with Slow or Variable Access Times ................................ 15–53
15.7.1 Hierarchical Bus Interface Example ........................................................... 15–54
15.7.2 Slow Devices Example ............................................................................... 15–54
15.8 External Master Support ................................................................................. 15–54
15.8.1 Synchronous External Masters ................................................................... 15–54
15.8.2 Asynchronous External Masters ................................................................. 15–55
15.8.3 Special Case: Address Type Signals for External Masters......................... 15–55
15.8.4 UPM Features Supporting External Masters .............................................. 15–55
15.8.4.1 Address Incrementing for External Synchronous Bursting Masters ...... 15–55
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15.8.4.2 Handshake Mechanism for Asynchronous External Masters ................. 15–56
15.8.4.3 Special Signal for External Address Multiplexer Control ...................... 15–56
15.8.5 External Master Examples .......................................................................... 15–56
15.8.5.1 External Masters and the GPCM ............................................................ 15–56
15.8.5.2 External Masters and the UPM ............................................................... 15–58
15.9 Memory System Interface Examples .............................................................. 15–63
15.9.1 Page-Mode DRAM Interface Example....................................................... 15–63
15.9.2 Page Mode Extended Data-Out Interface Example.................................... 15–74
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Chapter 16
PCMCIA Interface
16.1 System Configuration ....................................................................................... 16–1
16.2 PCMCIA Module Signal Definitions................................................................ 16–1
16.2.1 PCMCIA Cycle Control Signals................................................................... 16–3
16.2.2 PCMCIA Input Port Signals ......................................................................... 16–4
16.2.3 PCMCIA Output Port Signals (OP[0–4]) ..................................................... 16–5
16.2.4 Other PCMCIA Signals ................................................................................ 16–5
16.3 Operation Description....................................................................................... 16–5
16.3.1 Memory-Only Cards ..................................................................................... 16–6
16.3.2 I/O Cards....................................................................................................... 16–6
16.3.3 Interrupts....................................................................................................... 16–6
16.3.4 Power Control ............................................................................................... 16–7
16.3.5 Reset and Three-State Control...................................................................... 16–7
16.3.6 DMA ............................................................................................................. 16–7
16.4 Programming Model ......................................................................................... 16–8
16.4.1 PCMCIA Interface Input Pins Register (PIPR) ............................................ 16–8
16.4.2 PCMCIA Interface Status Changed Register (PSCR) .................................. 16–9
16.4.3 PCMCIA Interface Enable Register (PER) ................................................ 16–10
16.4.4 PCMCIA Interface General Control Register B (PGCRB) ........................ 16–11
16.4.5 PCMCIA Base Registers 0–7 (PBR0–PBR7)............................................. 16–12
16.4.6 PCMCIA Option Register 0–7 (POR0–POR7) .......................................... 16–12
16.5 PCMCIA Controller Timing Examples .......................................................... 16–16
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Part V
Communications Processor Module
Chapter 17
Communications Processor Module and CPM Timers
17.1 Features............................................................................................................. 17–1
17.2 CPM General-Purpose Timers.......................................................................... 17–4
17.2.1 Features......................................................................................................... 17–5
17.2.2 CPM Timer Operation .................................................................................. 17–6
17.2.2.1 Timer Clock Source .................................................................................. 17–6
17.2.2.2 Timer Reference Count............................................................................. 17–6
17.2.2.3 Timer Capture ........................................................................................... 17–6
17.2.2.4 Timer Gating (Timers 1 and 2 only) ......................................................... 17–7
17.2.2.5 Cascaded Mode......................................................................................... 17–7
17.2.2.6 Timer 1 and SPKROUT............................................................................ 17–8
17.2.3 CPM Timer Register Set............................................................................... 17–8
17.2.3.1 Timer Global Configuration Register (TGCR)......................................... 17–8
17.2.4 Timer Mode Registers (TMR1–TMR4) ....................................................... 17–9
17.2.4.1 Timer Reference Registers (TRR1–TRR4) ............................................ 17–10
17.2.4.2 Timer Capture Registers (TCR1–TCR4) ................................................ 17–10
17.2.4.3 Timer Counter Registers (TCN1–TCN4) ............................................... 17–11
17.2.4.4 Timer Event Registers (TER1–TER4).................................................... 17–11
17.2.5 Timer Initialization Examples .................................................................... 17–12
Chapter 18
Communications Processor
18.1 Features............................................................................................................. 18–1
18.2 Communicating with the Core.......................................................................... 18–2
18.3 Communicating with the Peripherals................................................................ 18–2
18.4 CP Microcode Revision Number ...................................................................... 18–3
18.5 CP Register Set and CP Commands ................................................................. 18–4
18.5.1 RISC Controller Configuration Register (RCCR) ........................................ 18–4
18.5.2 RISC Microcode Development Support Control Register (RMDS) ............ 18–5
18.5.3 CP Command Register (CPCR).................................................................... 18–6
18.5.4 CP Commands .............................................................................................. 18–7
18.5.4.1 CP Command Examples ........................................................................... 18–9
18.5.4.2 CP Command Execution Latency............................................................. 18–9
18.6 Dual-Port RAM................................................................................................. 18–9
18.6.1 System RAM and Microcode Packages...................................................... 18–11
18.6.2 The Buffer Descriptor (BD)........................................................................ 18–12
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18.6.3 Parameter RAM .......................................................................................... 18–12
18.7 The RISC Timer Table.................................................................................... 18–13
18.7.1 RISC Timer Table Scan Algorithm ............................................................ 18–14
18.7.2 The set timer Command.............................................................................. 18–14
18.7.3 RISC Timer Table Parameter RAM and Timer Table Entries ................... 18–14
18.7.3.1 RISC Timer Command Register (TM_CMD) ........................................ 18–15
18.7.3.2 RISC Timer Table Entries ...................................................................... 18–16
18.7.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)................... 18–16
18.7.5 PWM Mode................................................................................................. 18–16
18.7.6 RISC Timer Initialization ........................................................................... 18–17
18.7.7 RISC Timer Interrupt Handling.................................................................. 18–18
18.7.8 Using the RISC Timers to Track CP Loading ............................................ 18–18
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Chapter 19
SDMA Channels and IDMA Emulation
19.1 SDMA Channels ............................................................................................... 19–1
19.1.1 SDMA Transfers........................................................................................... 19–2
19.1.2 U-Bus Arbitration and the SDMA Channels ................................................ 19–2
19.2 SDMA Registers ............................................................................................... 19–3
19.2.1 SDMA Configuration Register (SDCR) ....................................................... 19–3
19.2.2 SDMA Status Register (SDSR) .................................................................... 19–4
19.2.3 SDMA Mask Register (SDMR).................................................................... 19–5
19.2.4 SDMA Address Register (SDAR) ................................................................ 19–5
19.3 IDMA Emulation .............................................................................................. 19–5
19.3.1 IDMA Features ............................................................................................. 19–6
19.3.2 IDMA Parameter RAM ................................................................................ 19–6
19.3.3 IDMA Registers............................................................................................ 19–7
19.3.3.1 DMA Channel Mode Registers (DCMR) ................................................. 19–7
19.3.3.2 IDMA Status Registers (IDSR1 and IDSR2) ........................................... 19–8
19.3.3.3 IDMA Mask Registers (IDMR1 and IDMR2).......................................... 19–9
19.3.4 IDMA Buffer Descriptors (BD).................................................................... 19–9
19.3.4.1 Function Code Registers—SFCR and DFCR......................................... 19–11
19.3.4.2 Auto-Buffering and Buffer-Chaining ..................................................... 19–12
19.3.5 IDMA CP Commands................................................................................. 19–12
19.3.6 IDMA Channel Operation .......................................................................... 19–13
19.3.6.1 Activating an IDMA Channel................................................................. 19–13
19.3.6.2 Suspending an IDMA Channel ............................................................... 19–13
19.3.7 IDMA Interface Signals—DREQ and SDACK.......................................... 19–13
19.3.7.1 IDMA Requests for Memory/Memory Transfers ................................... 19–14
19.3.7.2 IDMA Requests for Peripheral/Memory Transfers ................................ 19–14
19.3.7.2.1 Level-Sensitive Requests.................................................................... 19–14
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19.3.7.2.2 Edge-Sensitive Requests..................................................................... 19–15
19.3.8 IDMA Transfers—Dual-Address and Single-Address ............................... 19–15
19.3.8.1 Dual-Address (Dual-Cycle) Transfer ..................................................... 19–15
19.3.8.2 Single-Address (Single-Cycle) Transfer (Fly-By).................................. 19–16
19.3.9 Single-Buffer Mode on IDMA1—A Special Case ..................................... 19–18
19.3.9.1 IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode) ......... 19–19
19.3.9.2 IDMA1 Status Register (IDSR1) (Single-Buffer Mode) ........................ 19–19
19.3.9.3 IDMA1 Mask Register (IDMR1) (Single-Buffer Mode) ....................... 19–20
19.3.9.4 Burst Timing (Single-Buffer Mode) ....................................................... 19–20
19.3.10 External Recognition of an IDMA Transfer ............................................... 19–21
19.3.11 Interrupts During an IDMA Bus Transfer .................................................. 19–22
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Chapter 20
Serial Interface
20.1 SI Features ........................................................................................................ 20–2
20.2 The Time-Slot Assigner (TSA)......................................................................... 20–3
20.2.1 TSA Signals .................................................................................................. 20–7
20.2.2 Enabling Connections to the TSA ................................................................ 20–7
20.2.3 SI RAM......................................................................................................... 20–8
20.2.3.1 Disabling and Reenabling the TSA .......................................................... 20–8
20.2.3.2 TDMa Channel with Static Frames .......................................................... 20–8
20.2.3.3 SI RAM Dynamic Changes ...................................................................... 20–8
20.2.3.4 TDMa Channel with Dynamic Frames ................................................... 20–10
20.2.3.5 Programming the SI RAM...................................................................... 20–11
20.2.3.6 SI RAM Programming Example ............................................................ 20–13
20.2.4 The SI Registers.......................................................................................... 20–14
20.2.4.1 SI Global Mode Register (SIGMR) ........................................................ 20–14
20.2.4.2 SI Mode Register (SIMODE) ................................................................. 20–14
20.2.4.3 SI Clock Route Register (SICR) ............................................................. 20–20
20.2.4.4 SI Command Register (SICMR)............................................................. 20–22
20.2.4.5 SI Status Register (SISTR) ..................................................................... 20–22
20.2.4.6 SI RAM Pointer Register (SIRP)............................................................ 20–23
20.2.5 IDL Bus Implementation ............................................................................ 20–24
20.2.5.1 ISDN Terminal Adaptor Application ..................................................... 20–25
20.2.5.2 Programming the IDL Interface.............................................................. 20–27
20.2.6 GCI Bus Implementation ............................................................................ 20–28
20.2.6.1 GCI Activation/Deactivation .................................................................. 20–30
20.2.6.2 Programming the GCI Interface ............................................................. 20–30
20.2.6.2.1 Normal Mode...................................................................................... 20–30
20.2.6.2.2 SCIT Mode ......................................................................................... 20–30
20.2.6.3 GCI Interface (SCIT Mode) Programming Example ............................. 20–31
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20.3 NMSI Configuration ....................................................................................... 20–32
20.4 Baud Rate Generators (BRGs)........................................................................ 20–34
20.4.1 Baud Rate Generator Configuration Registers (BRGCn)........................... 20–36
20.4.2 Autobaud Operation on the SCC UART .................................................... 20–37
20.4.3 UART Baud Rate Examples ....................................................................... 20–38
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Chapter 21
Serial Communications Controllers
21.1 Features............................................................................................................. 21–2
21.2 SCC Registers ................................................................................................... 21–3
21.2.1 General SCC Mode Register (GSMR).......................................................... 21–3
21.2.2 Protocol-Specific Mode Register (PSMR) ................................................... 21–9
21.2.3 Data Synchronization Register (DSR).......................................................... 21–9
21.2.4 Transmit-on-Demand Register (TODR)..................................................... 21–10
21.3 SCC Buffer Descriptors (BDs) ....................................................................... 21–11
21.4 SCC Parameter RAM...................................................................................... 21–13
21.4.1 Function Code Registers (RFCR and TFCR) ............................................. 21–15
21.4.2 Handling SCC Interrupts ............................................................................ 21–15
21.4.3 SCC Initialization ....................................................................................... 21–16
21.4.4 Controlling SCC Timing with RTS, CTS, and CD..................................... 21–17
21.4.4.1 Synchronous Protocols ........................................................................... 21–17
21.4.4.2 Asynchronous Protocols ......................................................................... 21–20
21.4.5 Digital Phase-Locked Loop (DPLL) Operation.......................................... 21–21
21.4.5.1 Encoding Data with a DPLL................................................................... 21–23
21.4.6 Clock Glitch Detection ............................................................................... 21–24
21.4.7 Reconfiguring the SCCs ............................................................................. 21–25
21.4.7.1 General Reconfiguration Sequence for an SCC Transmitter.................. 21–25
21.4.7.2 Reset Sequence for an SCC Transmitter ................................................ 21–26
21.4.7.3 General Reconfiguration Sequence for an SCC Receiver ...................... 21–26
21.4.7.4 Reset Sequence for an SCC Receiver ..................................................... 21–26
21.4.7.5 Switching Protocols ................................................................................ 21–26
21.4.8 Saving Power .............................................................................................. 21–26
Chapter 22
SCC UART Mode
22.1 Features............................................................................................................. 22–2
22.2 Normal Asynchronous Mode............................................................................ 22–3
22.3 Synchronous Mode ........................................................................................... 22–3
22.4 SCC UART Parameter RAM............................................................................ 22–4
22.5 Data-Handling Methods: Character- or Message-Based .................................. 22–5
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22.6 Error and Status Reporting................................................................................ 22–6
22.7 SCC UART Commands.................................................................................... 22–6
22.8 Multidrop Systems and Address Recognition................................................... 22–7
22.9 Receiving Control Characters ........................................................................... 22–7
22.10 Hunt Mode (Receiver) ...................................................................................... 22–9
22.11 Inserting Control Characters into the Transmit Data Stream............................ 22–9
22.12 Sending a Break (Transmitter)........................................................................ 22–10
22.13 Sending a Preamble (Transmitter) .................................................................. 22–10
22.14 Fractional Stop Bits (Transmitter) .................................................................. 22–10
22.15 Handling Errors in the SCC UART Controller............................................... 22–11
22.16 UART Mode Register (PSMR)....................................................................... 22–12
22.17 SCC UART Receive Buffer Descriptor (RxBD) ............................................ 22–14
22.18 SCC UART Transmit Buffer Descriptor (TxBD)........................................... 22–17
22.19 SCC UART Event Register (SCCE) and Mask Register (SCCM) ................. 22–18
22.20 SCC UART Status Register (SCCS)............................................................... 22–20
22.21 SCC UART Programming Example............................................................... 22–21
22.22 S-Records Loader Application........................................................................ 22–22
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Chapter 23
SCC HDLC Mode
23.1 SCC HDLC Features......................................................................................... 23–2
23.2 SCC HDLC Channel Frame Transmission ....................................................... 23–2
23.3 SCC HDLC Channel Frame Reception ............................................................ 23–3
23.4 SCC HDLC Parameter RAM............................................................................ 23–3
23.5 Programming the SCC HDLC Controller......................................................... 23–5
23.6 SCC HDLC Commands.................................................................................... 23–5
23.7 Handling Errors in the SCC HDLC Controller................................................. 23–6
23.8 HDLC Mode Register (PSMR)......................................................................... 23–7
23.9 SCC HDLC Receive Buffer Descriptor (RxBD) .............................................. 23–8
23.10 SCC HDLC Transmit Buffer Descriptor (TxBD)........................................... 23–11
23.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) .................... 23–12
23.12 SCC HDLC Status Register (SCCS)............................................................... 23–14
23.13 SCC HDLC Programming Examples ............................................................. 23–14
23.13.1 SCC HDLC Programming Example #1...................................................... 23–14
23.13.2 SCC HDLC Programming Example #2...................................................... 23–16
23.14 HDLC Bus Mode with Collision Detection.................................................... 23–16
23.14.1 HDLC Bus Features.................................................................................... 23–19
23.14.2 Accessing the HDLC Bus ........................................................................... 23–19
23.14.3 Increasing Performance .............................................................................. 23–20
23.14.4 Delayed RTS Mode .................................................................................... 23–20
23.14.5 Using the Time-Slot Assigner (TSA) ......................................................... 23–22
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23.14.6 HDLC Bus Protocol Programming............................................................. 23–22
23.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol .............. 23–22
23.14.6.2 HDLC Bus Controller Programming Example....................................... 23–23
Title
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Chapter 24
SCC AppleTalk Mode
24.1 Operating the LocalTalk Bus ............................................................................ 24–1
24.2 Features............................................................................................................. 24–2
24.3 Connecting to AppleTalk.................................................................................. 24–3
24.4 Programming the SCC in AppleTalk Mode...................................................... 24–3
24.4.1 Programming the GSMR .............................................................................. 24–3
24.4.2 Programming the PSMR............................................................................... 24–4
24.4.3 Programming the TODR............................................................................... 24–4
24.4.4 SCC AppleTalk Programming Example....................................................... 24–4
Chapter 25
SCC Asynchronous HDLC Mode and IrDA
25.1 Asynchronous HDLC Features ......................................................................... 25–1
25.2 Asynchronous HDLC Frame Transmission Processing ................................... 25–2
25.3 Asynchronous HDLC Frame Reception Processing......................................... 25–2
25.4 Transmitter Transparency Encoding................................................................. 25–3
25.5 Receiver Transparency Decoding ..................................................................... 25–3
25.6 Exceptions to RFC 1549 ................................................................................... 25–4
25.7 Asynchronous HDLC Channel Implementation............................................... 25–5
25.8 Asynchronous HDLC Mode Parameter RAM.................................................. 25–5
25.9 Configuring GSMR and DSR for Asynchronous HDLC ................................. 25–6
25.9.1 General SCC Mode Register (GSMR).......................................................... 25–7
25.9.2 Data Synchronization Register
25.10 Programming the Asynchronous HDLC Controller ......................................... 25–7
25.11 Asynchronous HDLC Commands .................................................................... 25–7
25.12 Handling Errors in the Asynchronous HDLC Controller ................................. 25–8
25.13 SCC Asynchronous HDLC Registers ............................................................... 25–9
25.13.1 Asynchronous HDLC Event Register (SCCE)/Asynchronous
HDLC Mask Register (SCCM) ................................................................25–9
25.13.2 SCC Asynchronous HDLC Status Register (SCCS) .................................. 25–10
25.13.3 Asynchronous HDLC Mode Register (PSMR) .......................................... 25–11
25.14 SCC Asynchronous HDLC RxBDs ................................................................ 25–11
25.15 SCC Asynchronous HDLC TxBDs ................................................................ 25–13
25.16 Differences between HDLC and Asynchronous HDLC................................. 25–14
25.17 SCC Asynchronous HDLC Programming Example....................................... 25–15
(DSR).......................................................... 25–7
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Chapter 26
SCC BISYNC Mode
26.1 Features............................................................................................................. 26–2
26.2 SCC BISYNC Channel Frame Transmission ................................................... 26–2
26.3 SCC BISYNC Channel Frame Reception......................................................... 26–3
26.4 SCC BISYNC Parameter RAM........................................................................ 26–4
26.5 SCC BISYNC Commands ................................................................................ 26–5
26.6 SCC BISYNC Control Character Recognition ................................................. 26–6
26.7 BISYNC SYNC Register (BSYNC)................................................................. 26–7
26.8 SCC BISYNC DLE Register (BDLE) .............................................................. 26–8
26.9 Sending and Receiving the Synchronization Sequence .................................... 26–9
26.10 Handling Errors in the SCC BISYNC .............................................................. 26–9
26.11 BISYNC Mode Register (PSMR)................................................................... 26–10
SCC
26.12
26.13 SCC BISYNC Transmit BD (TxBD).............................................................. 26–13
26.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)............. 26–15
26.15 SCC Status Registers (SCCS)......................................................................... 26–16
26.16 Programming the SCC BISYNC Controller................................................... 26–16
26.17 SCC BISYNC Programming Example ........................................................... 26–17
BISYNC Receive BD (RxBD)............................................................... 26–12
Chapter 27
SCC Ethernet Mode
27.1 Ethernet on the MPC850................................................................................... 27–2
27.2 Features............................................................................................................. 27–3
27.3 Learning Ethernet on the MPC850 ................................................................... 27–4
27.4 Connecting the MPC850 to Ethernet ................................................................ 27–4
27.5 SCC Ethernet Channel Frame Transmission .................................................... 27–6
27.6 SCC Ethernet Channel Frame Reception.......................................................... 27–6
27.7 SCC Ethernet Parameter RAM ......................................................................... 27–7
27.8 Programming the Ethernet Controller............................................................. 27–10
27.9 SCC Ethernet Commands ............................................................................... 27–10
27.10 SCC Ethernet Address Recognition................................................................ 27–11
27.11 Hash Table Algorithm..................................................................................... 27–12
27.12 Interpacket Gap Time ..................................................................................... 27–13
27.13 Handling Collisions ........................................................................................ 27–13
27.14 Internal and External Loopback...................................................................... 27–13
27.15 Full-Duplex Ethernet Support......................................................................... 27–14
27.16 Handling Errors in the Ethernet Controller..................................................... 27–14
27.17 Ethernet Mode Register (PSMR) .................................................................... 27–15
27.18 SCC Ethernet Receive Buffer Descriptor ....................................................... 27–16
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27.19 SCC Ethernet Transmit Buffer Descriptor...................................................... 27–18
27.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ..................... 27–20
27.21 SCC Ethernet Programming Example ............................................................ 27–21
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Chapter 28
SCC Transparent Mode
28.1 Features............................................................................................................. 28–1
28.2 SCC Transparent Channel Frame Transmission Process.................................. 28–2
28.3 SCC Transparent Channel Frame Reception Process....................................... 28–2
28.4 Achieving Synchronization in Transparent Mode ............................................ 28–3
28.4.1 Synchronization in NMSI Mode................................................................... 28–3
28.4.1.1 In-Line Synchronization Pattern ............................................................... 28–3
28.4.1.2 External Synchronization Signals ............................................................. 28–4
28.4.1.2.1 External Synchronization Example ...................................................... 28–4
28.4.1.3 Transparent Mode without Explicit Synchronization ............................... 28–5
28.4.1.4 End of Frame Detection ............................................................................ 28–5
28.4.2 Synchronization and the TSA ....................................................................... 28–5
28.4.2.1 In-line Synchronization Pattern ................................................................ 28–5
28.4.2.2 Inherent Synchronization .......................................................................... 28–6
28.5 CRC Calculation in Transparent Mode............................................................. 28–6
28.6 SCC Transparent Parameter RAM.................................................................... 28–6
28.7 SCC Transparent Commands............................................................................ 28–6
28.8 Handling Errors in the Transparent Controller ................................................. 28–7
28.9 Transparent Mode and the PSMR..................................................................... 28–8
28.10 SCC Transparent Receive Buffer Descriptor (RxBD)...................................... 28–8
28.11 SCC Transparent Transmit Buffer Descriptor (TxBD) .................................. 28–10
28.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM) ............... 28–11
28.13 SCC Status Register in Transparent Mode (SCCS)........................................ 28–12
28.14 SCC2 Transparent Programming Example..................................................... 28–13
Chapter 29
IrDA Mode—SCC2 Only
29.1 Low-Speed IrDA Protocol ................................................................................ 29–2
29.2 Middle-Speed IrDA Protocol............................................................................ 29–2
29.3 High-Speed IrDA Protocol ............................................................................... 29–3
29.3.1 4PPM Data Encoding Definition .................................................................. 29–3
29.3.2 Data Link Layer ............................................................................................ 29–4
29.3.3 Serial Infrared Interaction Pulses.................................................................. 29–5
29.4 IrDA Registers .................................................................................................. 29–6
29.4.1 Infrared Mode Register (IRMODE) ............................................................. 29–6
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29.4.2 Infrared Serial Interaction Control Register (IRSIP).................................... 29–7
29.5 Low-Speed IrDA Programming........................................................................ 29–8
29.6 Middle-Speed IrDA Programming ................................................................... 29–9
29.7 High-Speed IrDA Programming Example...................................................... 29–10
Title
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Chapter 30
Serial Management Controllers (SMCs)
30.1 SMC Features.................................................................................................... 30–2
30.2 Common SMC Settings and Configurations..................................................... 30–3
30.2.1 SMC Mode Registers (SMCMRn) ............................................................... 30–3
30.2.2 SMC Buffer Descriptors (BDs) .................................................................... 30–5
30.2.3 SMC Parameter RAM................................................................................... 30–6
30.2.3.1 SMC Function Code Registers (RFCR/TFCR) ........................................ 30–7
30.2.4 Disabling SMCs On-the-Fly ......................................................................... 30–8
30.2.4.1 SMC Transmitter Full Sequence .............................................................. 30–8
30.2.4.2 SMC Transmitter Shortcut Sequence ....................................................... 30–9
30.2.4.3 SMC Receiver Full Sequence ................................................................... 30–9
30.2.4.4 SMC Receiver Shortcut Sequence ............................................................ 30–9
30.2.4.5 Changing SMC Protocols ......................................................................... 30–9
30.2.5 Saving Power ................................................................................................ 30–9
30.2.6 Handling Interrupts In the SMC ................................................................... 30–9
30.3 SMC in UART Mode...................................................................................... 30–10
30.3.1 SMC UART Features.................................................................................. 30–10
30.3.2 SMC UART-Specific Parameter RAM ...................................................... 30–11
30.3.3 SMC UART Channel Transmission Process .............................................. 30–11
30.3.4 SMC UART Channel Reception Process ................................................... 30–12
30.3.5 Data Handling Modes: Character- and Message-Oriented ......................... 30–12
30.3.6 SMC UART Commands............................................................................. 30–13
30.3.7 Sending a Break .......................................................................................... 30–13
30.3.8 Sending a Preamble .................................................................................... 30–13
30.3.9 Handling Errors in the SMC UART Controller.......................................... 30–14
30.3.10 SMC UART Receive BD (RxBD).............................................................. 30–14
30.3.11 SMC UART Transmit BD (TxBD) ............................................................ 30–17
30.3.12 SMC UART Event Register (SMCE)/Mask Register (SMCM)................. 30–18
30.3.13 SMC UART Controller Programming Example ........................................ 30–19
30.4 SMC in Transparent Mode.............................................................................. 30–20
30.4.1 SMC Transparent Mode Features ............................................................... 30–21
30.4.2 SMC Transparent-Specific Parameter RAM .............................................. 30–21
30.4.3 SMC Transparent Channel Transmission Process...................................... 30–21
30.4.4 SMC Transparent Channel Reception Process ........................................... 30–22
30.4.5 Using SMSYN for Synchronization ........................................................... 30–22
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30.4.6 Using TSA for Synchronization ................................................................. 30–23
30.4.7 SMC Transparent Commands..................................................................... 30–25
30.4.8 Handling Errors in the SMC Transparent Controller.................................. 30–26
30.4.9 SMC Transparent Receive BD (RxBD)...................................................... 30–26
30.4.10 SMC Transparent Transmit BD (TxBD) .................................................... 30–27
30.4.11 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)......... 30–29
30.4.12 SMC Transparent NMSI Programming Example....................................... 30–29
30.4.13 SMC Transparent TSA Programming Example ......................................... 30–30
30.5 SMC in GCI Mode.......................................................................................... 30–31
30.5.1 SMC GCI Parameter RAM......................................................................... 30–32
30.5.2 Handling the GCI Monitor Channel ........................................................... 30–32
30.5.2.1 SMC GCI Monitor Channel Transmission Process ................................ 30–32
30.5.2.1.1 SMC GCI Monitor Channel Reception Process ................................. 30–32
30.5.3 Handling the GCI C/I Channel ................................................................... 30–33
30.5.3.1 SMC GCI C/I Channel Transmission Process ........................................ 30–33
30.5.3.2 SMC GCI C/I Channel Reception Process ............................................. 30–33
30.5.4 SMC GCI Commands................................................................................. 30–33
30.5.5 SMC GCI Monitor Channel RxBD ............................................................ 30–33
30.5.6 SMC GCI Monitor Channel TxBD............................................................. 30–34
30.5.7 SMC GCI C/I Channel RxBD .................................................................... 30–35
30.5.8 SMC GCI C/I Channel TxBD..................................................................... 30–35
30.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)..................... 30–36
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Chapter 31
Serial Peripheral Interface (SPI)
31.1 Features............................................................................................................. 31–2
31.2 SPI Clocking and Signal Functions .................................................................. 31–2
31.3 Configuring the SPI Controller......................................................................... 31–3
31.3.1 The SPI as a Master Device.......................................................................... 31–3
31.3.2 The SPI as a Slave Device ............................................................................ 31–5
31.3.3 The SPI in Multi-master Operation .............................................................. 31–5
31.4 SPI Registers..................................................................................................... 31–7
31.4.1 SPI Mode Register (SPMODE) .................................................................... 31–7
31.4.1.1 SPI Transfers with Different Clocking Modes ......................................... 31–8
31.4.1.2 SPI Examples with Different SPMODE[LEN] Values ............................ 31–9
31.4.2 SPI Event/Mask Registers (SPIE/SPIM) .................................................... 31–10
31.4.3 SPI Command Register (SPCOM) ............................................................. 31–10
31.5 SPI Parameter RAM ....................................................................................... 31–11
31.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR) ...................... 31–12
31.6 SPI Commands................................................................................................ 31–13
31.7 The SPI Buffer Descriptor (BD) Table........................................................... 31–13
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31.7.1 SPI Buffer Descriptors (BDs) ..................................................................... 31–13
31.7.1.1 SPI Receive BD (RxBD) ........................................................................ 31–14
31.7.1.2 SPI Transmit BD (TxBD) ....................................................................... 31–15
31.8 SPI Master Programming Example ................................................................ 31–16
31.9 SPI Slave Programming Example................................................................... 31–17
31.10 Handling Interrupts in the SPI ........................................................................ 31–18
Chapter 32
Universal Serial Bus Controller
32.1 Overview........................................................................................................... 32–1
32.2 Features............................................................................................................. 32–2
32.3 Host Controller Limitations .............................................................................. 32–3
32.4 USB Controller Signal Functions and Clocking............................................... 32–3
32.5 Sending and Receiving ..................................................................................... 32–5
32.6 USB Parameter RAM ....................................................................................... 32–7
32.7 USB Registers................................................................................................. 32–10
32.7.1 USB Mode Register (USMOD).................................................................. 32–10
32.7.2 USB Slave Address Register (USADR) ..................................................... 32–11
32.7.3 USB Endpoint Configuration Registers 0–3 (USEPn) ............................... 32–11
32.7.4 USB Command Register (USCOM)........................................................... 32–12
32.7.5 USB Event Register (USBER)/Mask Register (USBMR) ......................... 32–13
32.7.6 USB Status Register (USBS)...................................................................... 32–14
32.8 USB Buffer Descriptor Tables........................................................................ 32–15
32.8.1 USB Receive Buffer Descriptor (RxBD).................................................... 32–17
32.8.2 USB Transmit Buffer Descriptor (TxBD) .................................................. 32–18
32.9 USB CP Commands........................................................................................ 32–20
32.10 USB Controller Errors .................................................................................... 32–21
32.11 Programming the USB Host Controller.......................................................... 32–22
32.11.1 USB Host Controller Initialization Example .............................................. 32–23
32.12 USB Function Controller Initialization Example ........................................... 32–24
Chapter 33
2
I
C Controller
33.1 I2C Features...................................................................................................... 33–2
33.2 I2C Controller Clocking and Signal Functions................................................. 33–2
33.3 I2C Controller Transfers ................................................................................... 33–3
33.3.1 I
33.3.2 I
33.3.3 I
33.3.4 I
2
C Master Write (Slave Read)..................................................................... 33–3
2
C Loopback Testing................................................................................... 33–4
2
C Master Read (Slave Write)..................................................................... 33–4
2
C Multi-Master Considerations ................................................................. 33–5
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33.4 I2C Registers..................................................................................................... 33–6
33.4.1 I
33.4.2 I
33.4.3 I
33.4.4 I
33.4.5 I
2
C Mode Register (I2MOD)........................................................................ 33–6
2
C Address Register (I2ADD)..................................................................... 33–7
2
C Baud Rate Generator Register (I2BRG)................................................. 33–7
2
C Event/Mask Registers (I2CER/I2CMR)................................................. 33–8
2
C Command Register (I2COM)................................................................. 33–8
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33.5 I2C Parameter RAM ......................................................................................... 33–9
33.6 I2C Commands ............................................................................................... 33–11
33.7 I2C Buffer Descriptor (BD) Tables ................................................................ 33–11
33.7.1 I
33.7.1.1 I
33.7.1.2 I
2
C Buffer Descriptors (BDs) ..................................................................... 33–12
2
C Receive Buffer Descriptor (RxBD).................................................. 33–12
2
C Transmit Buffer Descriptor (TxBD) ................................................ 33–13
Chapter 34
Parallel I/O Ports
34.1 Features............................................................................................................. 34–1
34.2 Port A................................................................................................................ 34–2
34.2.1 Port A Registers ............................................................................................ 34–3
34.2.1.1 Port A Open-Drain Register (PAODR) .................................................... 34–3
34.2.1.2 Port A Data Register (PADAT) ................................................................ 34–3
34.2.1.3 Port A Data Direction Register (PADIR) ................................................. 34–4
34.2.1.4 Port A Pin Assignment Register (PAPAR) .............................................. 34–4
34.2.2 Port A Configuration Examples.................................................................... 34–5
34.2.3 Port A Functional Block Diagrams............................................................... 34–5
34.3 Port B ................................................................................................................ 34–7
34.3.1 The Port B Registers ..................................................................................... 34–8
34.3.1.1 Port B Open-Drain Register (PBODR)..................................................... 34–8
34.3.1.2 Port B Data Register (PBDAT) ................................................................ 34–9
34.3.1.3 Port B Data Direction Register (PBDIR).................................................. 34–9
34.3.1.4 Port B Pin Assignment Register (PBPAR) ............................................. 34–10
34.4 Port C .............................................................................................................. 34–11
34.4.1 Port C Registers .......................................................................................... 34–13
34.4.1.1 Port C Data Register (PCDAT) .............................................................. 34–13
34.4.1.2 Port C Data Direction Register (PCDIR)................................................ 34–14
34.4.1.3 Port C Pin Assignment Register (PCPAR) ............................................. 34–14
34.4.1.4 Port C Special Options Register (PCSO)................................................ 34–15
34.4.1.5 Port C Interrupt Control Register (PCINT) ............................................ 34–16
34.5 Port D.............................................................................................................. 34–16
34.5.1 Port D Registers .......................................................................................... 34–17
34.5.1.1 Port D Data Register ............................................................................... 34–17
34.5.1.2 Port D Data Direction Register (PDDIR) ............................................... 34–18
34.5.1.3 Port D Pin Assignment Register (PDPAR) ............................................ 34–18
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Chapter 35
CPM Interrupt Controller
35.1 Features............................................................................................................. 35–1
35.2 CPM Interrupt Source Priorities ....................................................................... 35–3
35.2.1 Programming Relative Priority (Grouping and Spreading).......................... 35–3
35.2.2 Highest Priority Interrupt.............................................................................. 35–4
35.2.3 Nested Interrupts........................................................................................... 35–4
35.3 Masking Interrupt Sources in the CPM ............................................................ 35–4
35.4 Generating and Calculating Interrupt Vectors .................................................. 35–5
35.5 CPIC Registers.................................................................................................. 35–6
35.5.1 CPM Interrupt Configuration Register (CICR) ............................................ 35–7
35.5.2 CPM Interrupt Pending Register (CIPR) ...................................................... 35–8
35.5.3 CPM Interrupt Mask Register....................................................................... 35–9
35.5.4 CPM Interrupt In-Service Register (CISR) .................................................. 35–9
35.5.5 CPM Interrupt Vector Register (CIVR)...................................................... 35–10
35.6 Interrupt Handler Example—Single-Event Interrupt Source ......................... 35–10
35.7 Interrupt Handler Example—Multiple-Event Interrupt Source...................... 35–11
Part VI
Asynchronous Transfer Mode (ATM)
Chapter 36
ATM Overview
36.1 ATM Capabilities.............................................................................................. 36–1
36.2 MPC850SR and MPC850 Differences ............................................................. 36–1
36.2.1 Parameter RAM Conflicts ............................................................................ 36–1
36.2.2 IDMA2 Restriction ....................................................................................... 36–2
36.2.3 UTOPIA Conflicts ........................................................................................ 36–2
36.2.4 The ATM Pace Controller (APC) and APC Timer....................................... 36–2
36.3 ATM Features ................................................................................................... 36–2
36.4 MPC850SR Application Example .................................................................... 36–4
36.5 Overview of ATM Operation............................................................................ 36–4
36.6 UTOPIA Operation........................................................................................... 36–5
36.6.1 UTOPIA Transmit Overview........................................................................ 36–5
36.6.2 UTOPIA Receive Overview ......................................................................... 36–6
36.6.3 Expanded Cells ............................................................................................. 36–7
36.7 Serial ATM Operation ...................................................................................... 36–7
36.7.1 Serial ATM Transmit Overview ................................................................... 36–8
36.7.2 Serial ATM Receive Overview..................................................................... 36–8
36.7.2.1 Cell Delineation ........................................................................................ 36–9
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36.7.3 Cell Payload Scrambling/Descrambling....................................................... 36–9
36.8 ATM Pace Control (APC) .............................................................................. 36–10
36.9 Internal and External Channels (Extended Channel Mode) ........................... 36–10
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Chapter 37
Buffer Descriptors and Connection Tables
37.1 ATM Buffer Descriptors (BDs) ........................................................................ 37–1
37.1.1 AAL5 Buffers ............................................................................................... 37–2
37.1.2 AAL0 Buffers ............................................................................................... 37–3
37.1.3 ATM Receive Buffer Descriptors (RxBDs) ................................................. 37–3
37.1.4 ATM Transmit Buffer Descriptors (TxBDs) ................................................ 37–7
37.2 Receive and Transmit Connection Tables(RCTs and TCTs) ........................... 37–9
37.2.1 Receive Connection Table (RCT)............................................................... 37–10
37.2.2 Transmit Connection Table (TCT) ............................................................. 37–12
Chapter 38
ATM Parameter RAM
38.1 SAR Receive Function Code Register (SRFCR).............................................. 38–5
38.2 SAR Receive State Register (SRSTATE)......................................................... 38–6
38.3 SAR Transmit Function Code Register (STFCR) ............................................ 38–7
38.4 SAR Transmit State Register (STSTATE) ....................................................... 38–7
38.5 Address Match Parameters (AM1–AM5)......................................................... 38–8
38.6 APC State Register (APCST) ......................................................................... 38–11
38.7 Serial Cell Synchronization Status Register (ASTATUS).............................. 38–12
Chapter 39
ATM Controller
39.1 Address Mapping.............................................................................................. 39–1
39.1.1 Internal Look-up Mechanism (SRSTATE[EXT] = 0).................................. 39–1
39.1.1.1 Adding a New Internal Channel ............................................................... 39–2
39.1.1.2 Removing an Internal Channel ................................................................. 39–2
39.1.2 Address Compression (SRSTATE[EXT,ACP] = 11)................................... 39–2
39.1.2.1 First-Level Addressing Table (FLT) ........................................................ 39–3
39.1.2.2 Second-Level Addressing Tables (SLTs) ................................................. 39–3
39.1.2.3 Address Compression Example ................................................................ 39–4
39.1.2.4 Preventing Channel Aliasing .................................................................... 39–4
39.1.2.5 OAM Screening ........................................................................................ 39–5
39.1.3 CAM Address Mapping (SRSTATE[EXT,ACP] = 10) ............................... 39–5
39.2 Multi-PHY Configuration (MPHY).................................................................. 39–5
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39.2.1 Setting Multi-PHY mode .............................................................................. 39–5
39.2.2 Receive Multi-PHY Operation ..................................................................... 39–6
39.2.2.1 Look-up Table MPHY Support ................................................................ 39–6
39.2.2.2 Address Compression Multi-PHY Support .............................................. 39–7
39.2.2.3 CAM Multi-PHY Support ........................................................................ 39–7
39.2.3 Transmit Multi-PHY Operation.................................................................... 39–7
39.2.4 APC Multi-PHY Parameters......................................................................... 39–7
39.3 ATM Commands .............................................................................................. 39–7
Title
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Chapter 40
ATM Pace Control
40.1 APC Algorithm ................................................................................................. 40–1
40.1.1 APC Implementation .................................................................................... 40–2
40.1.2 APC Parameters............................................................................................ 40–3
40.1.3 Programming APC Scheduling Table Size and NCITS ............................... 40–4
40.1.4 Defining APC Slot Time............................................................................... 40–5
40.1.5 Programming Rates for Channels ................................................................ 40–5
40.1.6 APC Initialization and Operating Considerations ........................................ 40–6
40.1.7 Modifying Channel Transmit Pace ............................................................... 40–6
40.1.8 Minimizing Cell Delay Variation ................................................................. 40–6
40.2 Direct Scheduling of Cells ................................................................................ 40–7
40.3 Using the APC with Multiple ATM Ports ........................................................ 40–7
40.4 Using the APC Without Using UTOPIA.......................................................... 40–8
40.5 APC Scheduling Tables .................................................................................... 40–9
40.6 PHY Transmit Queues .................................................................................... 40–10
40.7 APC Priority Levels........................................................................................ 40–10
Chapter 41
ATM Exceptions
41.1 ATM Event Registers ....................................................................................... 41–2
41.1.1 UTOPIA Event Register (IDSR1) ................................................................ 41–2
41.1.2 Serial ATM Event Register (SCCE)............................................................. 41–3
41.2 Interrupt Queue Entry ....................................................................................... 41–4
41.3 Interrupt Queue Mask (IMASK)....................................................................... 41–6
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Chapter 42
Interface Configuration
42.1 General ATM Registers .................................................................................... 42–1
42.1.1 Port D Pin Assignment Register (PDPAR)................................................... 42–1
42.1.2 APC Timer (CPM Timer 4) .......................................................................... 42–2
42.1.3 RISC Timer................................................................................................... 42–2
42.2 UTOPIA Mode Registers.................................................................................. 42–2
42.2.1 System Clock Control Register (SCCR)....................................................... 42–2
42.2.2 Port B Multiplexing ...................................................................................... 42–4
42.2.3 Port C- TxClav and RxClav Signals ............................................................. 42–4
42.2.4 Port D—UTOPIA Data and Control Signals................................................ 42–4
42.2.5 RISC Controller Configuration Register (RCCR) ........................................ 42–5
42.2.6 UTOPIA Mode Initialization ........................................................................ 42–5
42.3 Serial ATM Configuration................................................................................ 42–6
42.3.1 RISC Controller Configuration Register (RCCR) ........................................ 42–6
42.3.2 SCC Configuration for Serial ATM.............................................................. 42–6
42.3.2.1 General SCC Mode Register (GSMR) ..................................................... 42–6
42.3.2.2 Serial ATM Mode Register (PSMR) ........................................................ 42–6
42.3.3 SI Configuration for Serial ATM.................................................................. 42–7
Chapter 43
UTOPIA Interface
43.1 MPC850SR UTOPIA Interface Signals............................................................ 43–1
43.2 UTOPIA Single-PHY ....................................................................................... 43–3
43.2.1 Receive Cell Transfer Operation .................................................................. 43–4
43.2.2 Transmit Cell Transfer Operation................................................................. 43–5
43.2.2.1 UTOPIA Bus and SOC Drive ................................................................... 43–5
43.3 UTOPIA Multi-PHY Operations ...................................................................... 43–6
43.3.1 Setting up PHSEL and PHREQ Pins ............................................................ 43–7
43.3.2 Receive Cell Transfer Operation .................................................................. 43–7
43.3.3 Transmit Cell Transfer Operation................................................................. 43–8
43.3.4 Example MPHY Implementation ................................................................. 43–8
43.4 UTOPIA Interface Transfer Timing ............................................................... 43–10
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Part VII
System Debugging and Testing Support
Chapter 44
System Development and Debugging
44.1 Tracking Program Flow .................................................................................... 44–1
44.1.1 Program Trace Functional Description......................................................... 44–2
44.1.2 Instruction Fetch Show Cycle Control.......................................................... 44–3
44.1.3 Program Trace Signals.................................................................................. 44–3
44.1.4 Program Trace Special Cases ....................................................................... 44–4
44.1.4.1 Queue Flush Information Special Case .................................................... 44–4
44.1.4.2 Program Trace When In Debug Mode...................................................... 44–5
44.1.4.3 Sequential Instructions Marked as Indirect Branch .................................. 44–5
44.1.5 Reconstructing Program Trace ..................................................................... 44–5
44.1.5.1 Back Trace ................................................................................................ 44–5
44.1.5.2 Window Trace .......................................................................................... 44–6
44.1.5.2.1 Synchronizing the Trace Window to Internal Core Events .................. 44–6
44.1.5.3 Detecting the Trace Window Start Address ............................................. 44–6
44.1.5.4 Detecting the Assertion/Negation of VSYNC .......................................... 44–7
44.1.5.5 Detecting the Trace Window End Address .............................................. 44–7
44.1.5.6 Efficient Trace Information Capture ........................................................ 44–7
44.2 Watchpoints and Breakpoints Support.............................................................. 44–8
44.2.1 Key Features ................................................................................................. 44–9
44.2.2 Internal Watchpoints and Breakpoints Logic ............................................. 44–10
44.2.3 Functional Description................................................................................ 44–11
44.2.3.1 Instruction Support Detailed Description ............................................... 44–11
44.2.3.2 Load/Store Support Detailed Description............................................... 44–12
44.2.3.3 The Counters........................................................................................... 44–14
44.2.3.4 Trap Enable Programming...................................................................... 44–15
44.2.4 Operation Details ........................................................................................ 44–15
44.2.4.1 Restrictions ............................................................................................. 44–15
44.2.4.2 Byte and Half Word Working Modes..................................................... 44–15
44.2.4.2.1 Examples ............................................................................................ 44–16
44.2.4.3 Context Dependent Filter........................................................................ 44–17
44.2.4.4 Ignore First Match .................................................................................. 44–17
44.2.4.5 Generating Six Compare Types .............................................................. 44–18
44.2.5 Load/Store Breakpoint Example................................................................. 44–18
44.3 Development System Interface ....................................................................... 44–19
44.3.1 Debug Mode Operation .............................................................................. 44–21
44.3.1.1 Debug Mode Enable vs. Debug Mode Disable ...................................... 44–22
44.3.1.2 Entering Debug Mode............................................................................. 44–23
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44.3.1.3 Debug Mode Indication .......................................................................... 44–24
44.3.1.4 Checkstop State and Debug Mode.......................................................... 44–24
44.3.1.5 Saving Machine State when Entering Debug Mode ............................... 44–25
44.3.1.6 Running in Debug Mode ........................................................................ 44–25
44.3.1.7 Exiting Debug Mode............................................................................... 44–25
44.3.2 Development Port Communication ............................................................ 44–26
44.3.2.1 Development Port Pins ........................................................................... 44–26
44.3.2.1.1 Development Serial Clock (DSCK).................................................... 44–26
44.3.2.1.2 Development Serial Data In (DSDI)................................................... 44–26
44.3.2.1.3 Development Serial Data Out (DSDO) .............................................. 44–26
44.3.2.1.4 Freeze.................................................................................................. 44–27
44.3.2.2 Development Port Registers ................................................................... 44–27
44.3.2.2.1 Development Port Shift Register ........................................................ 44–27
44.3.2.2.2 Trap Enable Control Register (TECR) ............................................... 44–28
44.3.2.2.3 Development Port Registers Decode .................................................. 44–28
44.3.2.3 Development Port Serial Communications–Clock Mode....................... 44–28
44.3.2.3.1 Asynchronous Clocked Mode—Using DSCK ................................... 44–28
44.3.2.3.2 Synchronous Self-Clocked Mode—Using CLKOUT ........................ 44–29
44.3.2.3.3 Selection of Development Port Clock Mode ...................................... 44–30
44.3.2.4 Development Port Serial Communications–Trap Enable Mode ............ 44–30
44.3.2.4.1 Serial Data Into Development Port..................................................... 44–31
44.3.2.4.2 Serial Data Out of Development Port ................................................. 44–31
44.3.2.5 Development Port Serial Communications–Debug Mode ..................... 44–32
44.3.2.5.1 Serial Data Into Development Port..................................................... 44–32
44.3.2.5.2 Serial Data Out of Development Port ................................................. 44–33
44.3.2.5.3 Fast Download Procedure................................................................... 44–34
44.4 Software Monitor Debugger Support.............................................................. 44–35
44.4.1 Freeze Indication......................................................................................... 44–35
44.5 Development Support Programming Model................................................... 44–35
44.5.1 Development Support Registers ................................................................. 44–37
44.5.1.1 Comparator A–H Value Registers (CMPA–CMPH).............................. 44–37
44.5.1.2 Breakpoint Address Register (BAR) ...................................................... 44–38
44.5.1.3 Instruction Support Control Register (ICTRL)....................................... 44–39
44.5.1.4 Load/Store Support Comparators Control Register (LCTRL1) ............. 44–40
44.5.1.5 Load/Store Support AND-OR Control Register (LCTRL2) .................. 44–41
44.5.1.6 Breakpoint Counter Value and Control Registers
(COUNTA/COUNTB) .......................................................................44–43
44.5.2 Debug Mode Registers................................................................................ 44–44
44.5.2.1 Interrupt Cause Register (ICR) ............................................................... 44–44
44.5.2.2 Debug Enable Register (DER)................................................................ 44–45
44.5.2.3 Development Port Data Register (DPDR) .............................................. 44–47
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Chapter 45
IEEE 1149.1 Test Access Port
45.1 Overview........................................................................................................... 45–1
45.2 TAP Controller.................................................................................................. 45–2
45.3 Boundary Scan Register.................................................................................... 45–3
45.4 Instruction Register........................................................................................... 45–6
45.4.1 EXTEST........................................................................................................ 45–6
45.4.2 SAMPLE/PRELOAD ................................................................................... 45–6
45.4.3 BYPASS ....................................................................................................... 45–7
45.4.4 CLAMP......................................................................................................... 45–7
45.4.5 HI–Z.............................................................................................................. 45–7
45.5 TAP Usage Considerations ............................................................................... 45–8
45.6 Recommended TAP Configuration................................................................... 45–8
45.7 Motorola MPC850 BSDL Description ............................................................. 45–8
Appendix A
Byte Ordering
A.1 Byte Ordering Overview.................................................................................... A-1
A.2 MPC850 Byte-Ordering Mechanisms................................................................ A-1
A.3 BE Mode ............................................................................................................ A-2
A.4 TLE Mode.......................................................................................................... A-2
A.4.1 TLE Mode System Examples ........................................................................ A-4
A.5 PPC-LE Mode.................................................................................................... A-6
A.5.1 I/O Addressing in PPC-LE Mode .................................................................. A-8
A.6 Setting the Endian Mode Of Operation ............................................................. A-8
Appendix B
Serial Communications Performance
B.1 Serial Clocking (Peak Rate Limitation) .............................................................. B-1
B.2 Bus Utilization .................................................................................................... B-2
B.3 CPM Bandwidth (Average Rate Limitation) ...................................................... B-2
B.3.1 Performance of Serial Channels ..................................................................... B-3
B.3.2 IDMA Considerations..................................................................................... B-4
B.3.3 Performance Calculations ............................................................................... B-5
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Appendix C
Register Quick Reference Guide
C.1 PowerPC Registers—User Registers .................................................................. C-1
C.2 PowerPC Registers—Supervisor Registers ........................................................ C-2
C.3 MPC850-Specific SPRs ...................................................................................... C-3
Appendix D
Instruction Set Listings
D.1 Instructions Sorted by Mnemonic...................................................................... D-1
D.2 Instructions Sorted by Opcode........................................................................... D-9
D.3 Instructions Grouped by Functional Categories .............................................. D-17
D.4 Instructions Sorted by Form............................................................................. D-27
D.5 Instruction Set Legend ..................................................................................... D-41
Appendix E
MPC850
E.1 MPC850 Overview ............................................................................................ E–1
E.1.1 Unimplemented Signals ................................................................................. E–2
E.1.2 Serial Interface ............................................................................................... E–3
E.1.3 SCC General Set-Up ...................................................................................... E–3
E.1.4 ATM............................................................................................................... E–3
Appendix F
MPC850DSL
F.1 MPC850DSL Overview..................................................................................... F–1
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1-1 MPC850SR Family Microprocessor Block Diagram ...................................................1–3
1-2 MPC850 Functional Signal Diagram..........................................................................1–12
3-1 Block Diagram of the Core ........................................................................................... 3-4
3-2 Instruction Flow Conceptual Diagram.......................................................................... 3-6
3-3 Basic Instruction Pipeline Timing ................................................................................ 3-7
3-4 Sequencer Data Path ..................................................................................................... 3-8
3-5 LSU Functional Block Diagram ................................................................................. 3-11
4-1 Condition Register (CR) ............................................................................................... 4-2
4-2 XER Register ................................................................................................................ 4-3
4-3 Machine State Register (MSR) ..................................................................................... 4-7
6-1 Exception Latency ...................................................................................................... 6-18
7-1 MPC850 Instruction Cache Organization.....................................................................7–3
7-2 MPC850 Data Cache Organization...............................................................................7–5
7-3 Instruction Cache Control and Status Register (IC_CST) ............................................7–6
7-4 Instruction Cache Address Register (IC_ADR)............................................................7–7
7-5 Instruction Cache Data Port Register (IC_DAT)..........................................................7–8
7-6 Data Cache Control and Status Register (DC_CST) ..................................................7–12
7-7 Data Cache Address Register (DC_ADR)..................................................................7–13
7-8 Data Cache Data Port Register (DC_DAT) ................................................................7–14
7-9 Instruction Cache Data Path........................................................................................7–21
8-1 Read/Instruction Fetch Flow Diagram..........................................................................8–4
8-2 Flow of Load/Store Access...........................................................................................8–5
8-3 Effective-to-Physical Address Translation for 4-Kbyte Pages Block Diagram............8–6
8-4 Two-Level Translation Table (MD_CTR[TWAM] = 1)..............................................8–9
8-5 Two-Level Translation Table (MD_CTR[TWAM] = 0)............................................8–11
8-6 IMMU Control Register (MI_CTR) ...........................................................................8–15
8-7 DMMU Control Register (MD_CTR) ........................................................................8–16
8-8 IMMU/DMMU Effective Page Number Register (Mx_EPN)....................................8–17
8-9 IMMU Tablewalk Control Register (MI_TWC) ........................................................8–18
8-10 DMMU Tablewalk Control Register (MD_TWC) .....................................................8–19
8-11 IMMU Real Page Number Register (MI_RPN) .........................................................8–20
8-12 DMMU Real Page Number Register (MD_RPN) ......................................................8–22
8-13 MMU Tablewalk Base Register (M_TWB) ...............................................................8–23
8-14 MMU Current Address Space ID Register (M_CASID)............................................8–23
8-15 MMU Access Protection Registers (MI_AP/MD_AP)...............................................8–24
8-16 MMU Tablewalk Special Register (M_TW) ..............................................................8–24
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8-17 IMMU CAM Entry Read Register (MI_CAM) ..........................................................8–25
8-18 IMMU RAM Entry Read Register 0 (MI_RAM0) .....................................................8–26
8-19 IMMU RAM Entry Read Register 1 (MI_RAM1) .....................................................8–27
8-20 DMMU CAM Entry Read Register (MD_CAM).......................................................8–28
8-21 DMMU RAM Entry Read Register 0 (MD_RAM0)..................................................8–29
8-22 DMMU RAM Entry Read Register 1 (MD_RAM1)..................................................8–30
8-23 DTLB Reload Code Example .....................................................................................8–32
8-24 ITLB Reload Code Example.......................................................................................8–33
8-25 Configuring the TLB Replacement COunter..............................................................8–33
9-1 Data Cache Load Timing ..............................................................................................9–2
9-2 Writeback Arbitration Timing—Example 1 .................................................................9–2
9-3 Writeback Arbitration Timing—Example 2 .................................................................9–2
9-4 Private Writeback Bus Load Timing ............................................................................9–3
9-5 External Load Timing ...................................................................................................9–3
9-6 Full Completion Queue Timing....................................................................................9–4
9-7 Branch Folding Timing.................................................................................................9–5
9-8 Branch Prediction Timing.............................................................................................9–5
9-9 Bus Latency for String Instructions ..............................................................................9–8
10-1 System Configuration and Protection Logic...............................................................10–3
10-2 Internal Memory Map Register (IMMR)....................................................................10–5
10-3 SIU Module Configuration Register (SIUMCR)........................................................10–6
10-4 System Protection Control Register (SYPCR) ...........................................................10–8
10-5 Transfer Error Status Register (TESR) .......................................................................10–9
10-6 Register Lock Mechanism ........................................................................................10–11
10-7 MPC850 Interrupt Structure .....................................................................................10–12
10-8 SIU Interrupt Processing...........................................................................................10–14
10-9 I
10-10 SIU Interrupt Pending Register (SIPEND) ...............................................................10–15
10-11 SIU Interrupt Mask Register (SIMASK) ..................................................................10–17
10-12 SIU Interrupt Edge/Level Register (SIEL) ...............................................................10–18
10-13 SIU Interrupt Vector Register (SIVEC)....................................................................10–19
10-14 Interrupt Table Handling Example ...........................................................................10–20
10-15 Software Watchdog Timer Service State Diagram...................................................10–21
10-16 Software Watchdog Timer Block Diagram ..............................................................10–22
10-17 Software Service Register (SWSR) ..........................................................................10–22
10-18 Decrementer Register (DEC)....................................................................................10–24
10-19 Timebase Upper Register (TBU) ..............................................................................10–25
10-20 Timebase Lower Register (TBL) ..............................................................................10–25
10-21 Timebase Reference Registers (TBREFA and TBREFB) ........................................10–26
10-22 Timebase Status and Control Register (TBSCR)......................................................10–26
10-23 Real-Time Clock Block Diagram .............................................................................10–28
10-24 Real-Time Clock Status and Control Register (RTCSC) .........................................10–28
10-25 Real-Time Clock Register (RTC) .............................................................................10–29
RQ0 Logical Representation ...................................................................................10–14
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10-26 Real-Time Clock Alarm Register (RTCAL).............................................................10–30
10-27 Real-Time Clock Alarm Seconds Register (RTSEC)...............................................10–30
10-28 Periodic Interrupt Timer Block Diagram..................................................................10–31
10-29 Periodic Interrupt Status and Control Register (PISCR) ..........................................10–32
10-30 PIT Count Register (PITC) .......................................................................................10–33
10-31 PIT Register (PITR)..................................................................................................10–34
11-1 Power-On and Hard Reset Sequence ..........................................................................11–4
11-2 Soft Reset Sequence....................................................................................................11–5
11-3 Reset Status Register (RSR) .......................................................................................11–5
11-4 Data Bus Configuration Input Circuit.........................................................................11–7
11-5 Reset Configuration Sampling for Short PORESET Assertion..................................11–8
11-6 Reset Configuration Sampling for Long PORESET Assertion ..................................11–8
11-7 Reset Configuration Sampling Timing Requirements................................................11–9
11-8 Hard Reset Configuration Word .................................................................................11–9
12-1 MPC850 Signals Group ..............................................................................................12–2
12-2 MPC850 Signals and Pin Numbers (Part 1) ...............................................................12–3
12-3 MPC850 Signals and Pin Numbers (Part 2) ...............................................................12–4
12-4 Three-State Buffers and Active Pull-Up Buffers......................................................12–19
13-1 Input Sample Window ................................................................................................13–2
13-2 MPC850 Bus Signals ..................................................................................................13–3
13-3 Basic Transfer Protocol...............................................................................................13–6
13-4 Basic Flow Diagram of a Single-Beat Read Cycle.....................................................13–7
13-5 Basic Timing: Single-Beat Read Cycle, Zero Wait States .........................................13–8
13-6 Basic Timing: Single-Beat Read Cycle, One Wait State............................................13–9
13-7 Basic Flow of a Single-Beat Write Cycle .................................................................13–10
13-8 Basic Timing: Single-Beat Write Cycle, Zero Wait States.......................................13–11
13-9 Basic Timing: Single-Beat Write Cycle, One Wait State .........................................13–12
13-10 Basic Timing: Single-Beat, 32-Bit Data Write Cycle, 16-Bit Port Size...................13–13
13-11 Basic Flow of a Burst-Read Cycle............................................................................13–16
13-12 Burst-Read Cycle: 32-Bit Port Size, Zero Wait State...............................................13–17
13-13 Burst-Read Cycle: 32-Bit Port Size, One Wait State................................................13–18
13-14 Burst-Read Cycle: 32-Bit Port Size, Wait States between Beats..............................13–19
13-15 Burst-Read Cycle: 16-Bit Port Size, One Wait State between Beats .......................13–20
13-16 Basic Flow of a Burst Write Cycle ...........................................................................13–21
13-17 Burst-Write Cycle: 32-Bit Port Size, Zero Wait States ............................................13–22
13-18 Burst-Inhibit Cycle: 32-Bit Port Size........................................................................13–23
13-19 Internal Operand Representation ..............................................................................13–24
13-20 Interface to Different Port Size Devices ...................................................................13–25
13-21 Bus Arbitration Flowchart ........................................................................................13–27
13-22 Bus Busy (BB) and Transfer Start (TS) Connection Example .................................13–28
13-23 Bus Arbitration Timing Diagram..............................................................................13–29
13-24 Internal Bus Arbitration State Machine ....................................................................13–30
13-25 Termination Signals Protocol Basic Connection ......................................................13–35
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Figure Number
13-26 Termination Signals Protocol Timing Diagram........................................................13–35
13-27 Reservation on Multilevel Bus Hierarchy.................................................................13–37
13-28 Retry Transfer Timing–Internal Arbiter ...................................................................13–38
13-29 Retry Transfer Timing–External Arbiter ..................................................................13–39
13-30 Retry on Burst Cycle.................................................................................................13–40
14-1 Clock Source and Distribution....................................................................................14–2
14-2 Clock Module Components ........................................................................................14–3
14-3 Crystal Circuit Examples ............................................................................................14–5
14-4 SPLL Block Diagram..................................................................................................14–5
14-5 Clock Dividers ..........................................................................................................14–10
14-6 Low-power dividers for GCLKx ..............................................................................14–10
14-7 Divided System Clocks (GCLKx) Timing Diagram ................................................14–11
14-8 Memory Controller and External Bus Clocks Timing
Diagram for EBDF=0 and EBDF=1 .........................................................................14–12
14-9 Memory Controller and External Bus Clocks Timing
Diagram for (CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0).........................14–13
14-10 BRGCLK Divider .....................................................................................................14–14
14-11 SYNCCLK Divider...................................................................................................14–15
14-12 MPC850 Power Rails................................................................................................14–17
14-13 MPC850 Low-Power Mode Flowchart.....................................................................14–20
14-14 Software-Initiated Power-Down Configuration........................................................14–25
14-15 System Clock and Reset Control Register (SCCR) ..................................................14–27
14-16 PLL, Low-Power, and Reset Control Register (PLPRCR).......................................14–30
15-1 Memory Controller Block Diagram ...........................................................................15–3
15-2 Memory Controller Machine Selection ......................................................................15–4
15-3 Simple System Configuration.....................................................................................15–5
15-4 Basic Memory Controller Operation ..........................................................................15–6
15-5 Base Registers (BRx)..................................................................................................15–9
15-6 BR0 Reset Defaults.....................................................................................................15–9
15-7 Option Registers (ORx) ............................................................................................15–11
15-8 OR0 Reset Defaults...................................................................................................15–11
15-9 Memory Status Register (MSTAT) ..........................................................................15–13
15-10 Machine A Mode Register/Machine B Mode Registers (MxMR)............................15–14
15-11 Memory Command Register (MCR) ........................................................................15–16
15-12 Memory Data Register (MDR) .................................................................................15–17
15-13 Memory Address Register (MAR)............................................................................15–17
15-14 Memory Periodic Timer Prescaler Register (MPTPR).............................................15–18
15-15 GPCM-to-SRAM Conguration...............................................................................15–19
15-16 GPCM Peripheral Device Interface ..........................................................................15–21
15-17 GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0).......................15–21
15-18 GPCM Memory Device Interface.............................................................................15–22
15-19 GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0).............15–22
15-20 GPCM Memory Device Basic Timing (ACS 00, CSNT = 1, TRLX = 0).............15–23
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15-21 GPCM Relaxed Timing Read (ACS = 1x, SCY = 1,
CSNT = 0, and TRLX = 1) .......................................................................................15–23
15-22 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1).........15–24
15-23 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1)..........15–25
15-24 GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX =1)..........15–25
15-25 GPCM Read Followed by Write (EHTR = 0) ..........................................................15–26
15-26 GPCM Read Followed by Write (EHTR = 1) ..........................................................15–27
15-27 GPCM Read Followed by Read from Different Banks (EHTR = 1)........................15–27
15-28 GPCM Read Followed by Read from Same Bank (EHTR = 1) ...............................15–28
15-29 Asynchronous External Master Configuration for GPCM-Handled
Memory Devices.......................................................................................................15–29
15-30 Asynchronous External Master, GPCM-Handled Memory
Access Timing (TRLX = 0) ......................................................................................15–30
15-31 User-Programmable Machine Block Diagram..........................................................15–31
15-32 RAM Array Indexing................................................................................................15–32
15-33 Memory Periodic Timer Request Block Diagram ....................................................15–33
15-34 UPM Clock Scheme One (Division Factor = 1) .......................................................15–34
15-35 UPM Clock Scheme Two (Division Factor = 2) ......................................................15–35
15-36 UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) ..................15–36
15-37 UPM Signals Timing Example Two (Division Factor = 2, EBDF = 01) .................15–36
15-38 RAM Array and Signal Generation ..........................................................................15–37
15-39 The RAM Word ........................................................................................................15–38
15-40 CSx Signal Selection.................................................................................................15–41
15-41 BSx Signal Selection.................................................................................................15–42
15-42 Early GPL5 Control ..................................................................................................15–43
15-43 Address Multiplex Timing........................................................................................15–46
15-44 UPM Read Access Data Sampling ...........................................................................15–51
15-45 Wait Mechanism Timing for Internal and External Synchronous Masters ..............15–52
15-46 Wait Mechanism Timing for an External Asynchronous Master .............................15–53
15-47 Synchronous External Master Access.......................................................................15–57
15-48 Asynchronous External Master Access ....................................................................15–58
15-49 Synchronous External Master Interconnect Example...............................................15–59
15-50 Synchronous External Master: Burst Read Access to Page Mode DRAM ..............15–60
15-51 Asynchronous External Master Interconnect Example.............................................15–61
15-52 Asynchronous External Master Timing Example.....................................................15–62
15-53 Page-Mode DRAM Interface Connection ................................................................15–63
15-54 Single-Beat Read Access to Page-Mode DRAM......................................................15–65
15-55 Single-Beat Write Access to Page Mode DRAM .....................................................15–66
15-56 Burst Read Access to Page-Mode DRAM (No LOOP)............................................15–67
15-57 Burst Read Access to Page-Mode DRAM (LOOP)..................................................15–68
15-58 Burst Write Access to Page-Mode DRAM (No LOOP)...........................................15–69
15-59 Burst Write Access to Page-Mode DRAM (LOOP).................................................15–70
15-60 Refresh Cycle (CAS before RAS) to Page-Mode DRAM........................................15–71
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Figure Number
15-61 Exception Cycle........................................................................................................15–72
15-62 Optimized DRAM Burst Read Access .....................................................................15–73
15-63 EDO DRAM Interface Connection...........................................................................15–74
15-64 EDO DRAM Single-Beat Read Access....................................................................15–76
15-65 EDO DRAM Single-Beat Write Access ...................................................................15–77
15-66 EDO DRAM Burst Read Access ..............................................................................15–78
15-67 EDO DRAM Burst Write Access .............................................................................15–79
15-68 EDO DRAM Refresh Cycle (CAS before RAS) ......................................................15–80
15-69 EDO DRAM Exception Cycle..................................................................................15–81
15-70 Blank Work Sheet for a UPM...................................................................................15–82
16-1 System with PCMCIA Socket ....................................................................................16–2
16-2 Internal DMA Request Logic......................................................................................16–7
16-3 PCMCIA Interface Input Pins Register (PIPR) ..........................................................16–8
16-4 PCMCIA Interface Status Changed Register (PSCR) ................................................16–9
16-5 PCMCIA Interface Enable Register (PER)...............................................................16–10
16-6 PCMCIA Interface General Control Register B (PGCRB) ......................................16–11
16-7 PCMCIA Base Register (PBR).................................................................................16–12
16-8 PCMCIA Option Register 0–7 (POR0–POR7).........................................................16–13
16-9 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 1..............16–16
16-10 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 2 PSL = 4 PSHT = 1..............16–17
16-11 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 0..............16–18
16-12 PCMCIA Single-Beat Write Cycle PRS = 2 PSST = 1 PSL = 3 PSHT = 1.............16–19
16-13 PCMCIA Single-Beat Write Cycle PRS = 3 PSST = 1 PSL = 4 PSHT = 3.............16–20
16-14 PCMCIA Single-Beat Write with Wait PRS = 3 PSST = 1
PSL = 3 PSHT = 0 ....................................................................................................16–21
16-15 PCMCIA Single-Beat Read with Wait PRS = 3 PSST = 1
PSL = 3 PSHT =1 .....................................................................................................16–22
16-16 PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0........................16–23
16-17 PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0........................16–24
16-18 PCMCIA DMA Read Cycle PRS = 4 PSST = 1 PSL = 3 PSHT = 0 .......................16–25
17-1 CPM Block Diagram...................................................................................................17–2
17-2 MPC850Application Design Example........................................................................17–4
17-3 CPM Timer Block Diagram........................................................................................17–5
17-4 Timer Cascaded Mode Block Diagram.......................................................................17–7
17-5 Timer Global Configuration Register (TGCR)...........................................................17–8
17-6 Timer Mode Registers (TMR1–TMR4)......................................................................17–9
17-7 Timer Reference Registers (TRR1–TRR4) ..............................................................17–10
17-8 Timer Capture Registers (TCR1–TCR4) ..................................................................17–10
17-9 Timer Counter Registers (TCN1–TCN4) .................................................................17–11
17-10 Timer Event Registers (TER1–TER4)......................................................................17–11
18-1 Communications Processor (CP) Block Diagram.......................................................18–2
18-2 RISC Controller Configuration Register (RCCR) ......................................................18–4
18-3 RISC Microcode Development Support Control Register (RMDS)...........................18–5
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18-4 CP Command Register (CPCR)..................................................................................18–6
18-5 Dual-Port RAM Block Diagram ...............................................................................18–10
18-6 Dual-Port RAM Memory Map..................................................................................18–11
18-7 RISC Timer Table RAM Usage................................................................................18–14
18-8 RISC Timer Command Register (TM_CMD) ..........................................................18–15
18-9 RISC Timer Event Register (RTER)/Mask Register (RTMR) .................................18–16
19-1 MPC850 SDMA Data Paths .......................................................................................19–1
19-2 SDMA U-Bus Arbitration (Cycle Steal).....................................................................19–3
19-3 SDMA Configuration Register (SDCR) .....................................................................19–4
19-4 SDMA Status Register (SDSR) ..................................................................................19–4
19-5 DMA Channel Mode Register (DCMR).....................................................................19–7
19-6 IDMA Status Registers (IDSR1/IDSR2) ....................................................................19–8
19-7 IDMAx Channel’s BD Table ......................................................................................19–9
19-8 IDMA Buffer Descriptor Structure...........................................................................19–10
19-9 Function Code Registers—SFCR and DFCR...........................................................19–11
19-10 SDACK Timing Diagram: Single-Address
Peripheral Write, Externally-Generated TA .............................................................19–16
19-11 SDACK Timing Diagram: Single-Address
Peripheral Write, Internally-Generated TA ..............................................................19–17
19-12 SDACK Timing Diagram: Single-Address
Peripheral Read, Internally-Generated TA ...............................................................19–18
19-13 IDMA Channel Mode Register (DCMR) (Single-Buffer Mode) .............................19–19
19-14 IDMA1 Status Register (IDSR1) (Single-Buffer Mode) ..........................................19–20
19-15 Single-Address IDMA1 Burst Timing (Single-Buffer Mode)..................................19–21
20-1 MPC850 SI Block Diagram........................................................................................20–2
20-2 Various Configurations of a TDM Channel................................................................20–5
20-3 Enabling Connections through the SI .........................................................................20–7
20-4 SI RAM Partitioning Using TDMa with Static Frames..............................................20–8
20-5 SI RAM Dynamic Changes with TDMa...................................................................20–10
20-6 SI RAM Partitioning Using TDMa with Dynamic Frames ......................................20–11
20-7 SIRAM Entry............................................................................................................20–11
20-8 Example Using SI RAMn[SWTR] ...........................................................................20–12
20-9 SI Global Mode Register (SIGMR) ..........................................................................20–14
20-10 SI Mode Register (SIMODE) ...................................................................................20–15
20-11 One Clock Delay from Sync to Data (xFSD = 01) ...................................................20–17
20-12 No Delay from Sync to Data (xFSD = 00) ...............................................................20–17
20-13 Falling Edge (FE) Effect When CE = 1 and xFSD = 01...........................................20–17
20-14 Falling Edge (FE) Effect When CE = 0 and xFSD = 01...........................................20–18
20-15 Falling Edge (FE) Effect When CE = 1 and xFSD = 00...........................................20–19
20-16 Falling Edge (FE) Effect When CE = 0 and xFSD = 00...........................................20–20
20-17 SI Clock Route Register (SICR) ...............................................................................20–21
20-18 SI Command Register (SICMR)...............................................................................20–22
20-19 SI Status Register (SISTR) .......................................................................................20–22
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Illustrations xlvii
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20-20 SI RAM Pointer Register (SIRP)..............................................................................20–23
20-21 IDL Bus Application Example..................................................................................20–25
20-22 ISDN Terminal Adaptor Using IDL .........................................................................20–25
20-23 IDL Bus Signals........................................................................................................20–26
20-24 GCI Bus Signals........................................................................................................20–29
20-25 Bank-of-Clocks Selection Logic for NMSI ..............................................................20–33
20-26 Baud Rate Generator (BRG) Block Diagram ...........................................................20–35
20-27 Baud Rate Generator Configuration Registers (BRGCn).........................................20–36
21-1 SCC Block Diagram ...................................................................................................21–2
21-2 GSMR_H—General SCC Mode Register (High Order) ............................................21–4
21-3 GSMR_L—General SCC Mode Register (Low Order)..............................................21–6
21-4 Data Synchronization Register (DSR) ......................................................................21–10
21-5 Transmit-on-Demand Register (TODR) ...................................................................21–10
21-6 SCC Buffer Descriptors (BDs) .................................................................................21–11
21-7 SCCx Buffer Descriptor and Buffer Structure..........................................................21–12
21-8 Function Code Registers (RFCR and TFCR) ...........................................................21–15
21-9 Output Delay from RTS Asserted for Synchronous Protocols .................................21–18
21-10 Output Delay from CTS Asserted for Synchronous Protocols .................................21–18
21-11 CTS Lost in Synchronous Protocols.........................................................................21–19
21-12 Using CD to Control Synchronous Protocol Reception ...........................................21–20
21-13 DPLL Receiver Block Diagram................................................................................21–21
21-14 DPLL Transmitter Block Diagram ...........................................................................21–22
21-15 DPLL Encoding Examples .......................................................................................21–24
22-1 UART Character Format.............................................................................................22–1
22-2 Two UART Multidrop Configurations .......................................................................22–7
22-3 Control Character Table, RCCM, and RCCR.............................................................22–8
22-4 Transmit Out-of-Sequence Register (TOSEQ)...........................................................22–9
22-5 Data Synchronization Register (DSR) ......................................................................22–11
22-6 Protocol-Specific Mode Register for UART (PSMR) ..............................................22–13
22-7 SCC UART Receiving using RxBDs .......................................................................22–15
22-8 SCC UART RxBD....................................................................................................22–16
22-9 SCC UART Transmit Buffer Descriptor (TxBD).....................................................22–17
22-10 SCC UART Interrupt Event Example.......................................................................22–19
22-11 SCC UART Event Register (SCCE) and Mask Register (SCCM) ...........................22–19
22-12 SCC Status Register for UART Mode (SCCS).........................................................22–20
23-1 HDLC Framing Structure ...........................................................................................23–2
23-2 HDLC Address Recognition .......................................................................................23–5
23-3 HDLC Mode Register (PSMR)...................................................................................23–7
23-4 SCC HDLC Receive Buffer Descriptor (RxBD) ........................................................23–8
23-5 SCC HDLC Receiving using RxBDs .......................................................................23–10
23-6 SCC HDLC Transmit Buffer Descriptor (TxBD).....................................................23–11
23-7 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ..............................23–12
23-8 SCC HDLC Interrupt Event Example.......................................................................23–13
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23-9 SCC HDLC Status Register (SCCS).........................................................................23–14
23-10 Typical HDLC Bus Multimaster Configuration .......................................................23–18
23-11 Typical HDLC Bus Single-Master Configuration ....................................................23–18
23-12 Detecting an HDLC Bus Collision ...........................................................................23–19
23-13 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance .........................23–20
23-14 HDLC Bus Transmission Line Configuration ..........................................................23–21
23-15 Delayed RTS Mode...................................................................................................23–21
23-16 HDLC Bus TDM Transmission Line Configuration ................................................23–22
24-1 LocalTalk Frame Format ............................................................................................24–1
24-2 Connecting the MPC850to LocalTalk ........................................................................24–3
25-1 Asynchronous HDLC Frame Structure.......................................................................25–2
25-2 Receive Flowchart ......................................................................................................25–4
25-3 TXCTL_TBL/RXCTL_TBL ......................................................................................25–6
25-4 Asynchronous HDLC Event Register (SCCE)/Asynchronous
HDLC Mask Register (SCCM)...................................................................................25–9
25-5 SCC Status Register for Asynchronous HDLC Mode (SCCS) ................................25–10
25-6 Asynchronous HDLC Mode Register (PSMR).........................................................25–11
25-7 SCC Asynchronous HDLC RxBDs ..........................................................................25–12
25-8 SCC Asynchronous HDLC TxBDs ..........................................................................25–13
26-1 Classes of BISYNC Frames........................................................................................26–1
26-2 Control Character Table and RCCM ..........................................................................26–6
26-3 BISYNC SYNC (BSYNC) .........................................................................................26–7
26-4 BISYNC DLE (BDLE) ...............................................................................................26–8
26-5 Protocol-Specific Mode Register for BISYNC (PSMR) ..........................................26–10
26-6 SCC BISYNC RxBD ................................................................................................26–12
26-7 SCC BISYNC TxBD ................................................................................................26–13
26-8 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM).......................26–15
26-9 SCC Status Registers (SCCS)...................................................................................26–16
27-1 Ethernet Frame Structure ............................................................................................27–1
27-2 Ethernet Block Diagram .............................................................................................27–2
27-3 Connecting the MPC850 to Ethernet ..........................................................................27–5
27-4 Ethernet Address Recognition Flowchart .................................................................27–12
27-5 Ethernet Mode Register (PSMR) ..............................................................................27–15
27-6 SCC Ethernet RxBD .................................................................................................27–16
27-7 Ethernet Receiving using RxBDs .............................................................................27–18
27-8 SCC Ethernet TxBD .................................................................................................27–19
27-9 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ...............................27–20
27-10 Ethernet Interrupt Events Example...........................................................................27–21
28-1 Sending Transparent Frames between MPC850.........................................................28–4
28-2 SCC Transparent Receive Buffer Descriptor (RxBD)................................................28–9
28-3 SCC Transparent Transmit Buffer Descriptor (TxBD) ............................................28–10
28-4 SCC Transparent Event Register (SCCE)/Mask Register (SCCM) .........................28–12
28-5 SCC Status Register in Transparent Mode (SCCS)..................................................28–13
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29-1 Serial Infrared (SIR) Link...........................................................................................29–1
29-2 Low-Speed IrDA Data Format....................................................................................29–2
29-3 Middle Speed Packet Format ......................................................................................29–2
29-4 Middle-Speed IrDA Data Format ...............................................................................29–3
29-5 One Complete Symbol................................................................................................29–3
29-6 High-Speed Packet Format .........................................................................................29–4
29-7 Preamble Field Symbol Format ..................................................................................29–4
29-8 Start Flag Symbol Format...........................................................................................29–4
29-9 Stop Flag Symbol Format ...........................................................................................29–5
29-10 High-Speed IrDA Data Format...................................................................................29–5
29-11 Serial Infrared Interaction Pulse Waveform ...............................................................29–5
29-12 Infrared Mode Register (IRMODE)............................................................................29–6
29-13 Infrared Serial Interaction Control Register (IRSIP) ..................................................29–7
30-1 SMC Block Diagram...................................................................................................30–2
30-2 SMC Mode Registers (SMCMRn)..............................................................................30–3
30-3 SMC Memory Structure..............................................................................................30–5
30-4 SMC Function Code Registers (RFCR/TFCR)...........................................................30–8
30-5 SMC UART Frame Format ......................................................................................30–10
30-6 SMC UART Receive BD (RxBD)............................................................................30–14
30-7 SMC UART Receiving using RxBDs.......................................................................30–16
30-8 SMC UART Transmit BD (TxBD)...........................................................................30–17
30-9 SMC UART Event Register (SMCE)/Mask Register (SMCM) ...............................30–18
30-10 SMC UART Interrupts Example ..............................................................................30–19
30-11 Synchronization with SMSYNx ...............................................................................30–23
30-12 Synchronization with the TSA..................................................................................30–24
30-13 SMC Transparent Receive BD (RxBD)....................................................................30–26
30-14 SMC Transparent Transmit BD (TxBD) ..................................................................30–27
30-15 SMC Transparent Event Register (SMCE)/Mask Register (SMCM).......................30–29
30-16 SMC GCI Monitor Channel RxBD...........................................................................30–33
30-17 SMC GCI Monitor Channel TxBD...........................................................................30–34
30-18 SMC C/I Channel RxBD ..........................................................................................30–35
30-19 SMC C/I Channel TxBD...........................................................................................30–35
30-20 SMC GCI Event Register (SMCE)/Mask Register (SMCM) ...................................30–36
31-1 SPI Block Diagram .....................................................................................................31–1
31-2 Single-Master/Multi-Slave Configuration ..................................................................31–4
31-3 Multimaster Configuration..........................................................................................31–6
31-4 SPI Mode Register (SPMODE) ..................................................................................31–7
31-5 SPI Transfer Format with SPMODE[CP] = 0 ............................................................31–8
31-6 SPI Transfer Format with SPMODE[CP] = 1 ............................................................31–8
31-7 SPI Event/Mask Registers (SPIE/SPIM) ..................................................................31–10
31-8 SPI Command Register (SPCOM)............................................................................31–10
31-9 Receive/Transmit Function Code Registers (RFCR/TFCR).....................................31–12
31-10 SPI Memory Structure ..............................................................................................31–13
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31-11 SPI Receive BD (RxBD) ..........................................................................................31–14
31-12 SPI Transmit BD (TxBD) .........................................................................................31–15
32-1 USB Controller Block Diagram..................................................................................32–2
32-2 USB Interface..............................................................................................................32–4
32-3 USB Controller Operation Flow .................................................................................32–5
32-4 Endpoint Pointer Registers (EPnPTR)........................................................................32–8
32-5 Frame Number (FRAME_N)......................................................................................32–9
32-6 Transmit/Receive Function Code Registers (TFCR/RFCR).......................................32–9
32-7 USB Mode Register (USMOD) ................................................................................32–10
32-8 USB Slave Address Register (USADR) ...................................................................32–11
32-9 USB Endpoint Registers 0–3 (USEPn).....................................................................32–11
32-10 USB Command Register (USCOM).........................................................................32–12
32-11 USB Event Register (USBER)/ Mask Register (USBMR).......................................32–13
32-12 USB Status Register (USBS)....................................................................................32–14
32-13 USB Memory Structure ............................................................................................32–16
32-14 USB Receive Buffer Descriptor (RxBD)..................................................................32–17
32-15 USB Transmit Buffer Descriptor (TxBD) ................................................................32–18
32-16 USB Command Format of the CPCR .......................................................................32–20
33-1 I2C Controller Block Diagram....................................................................................33–1
33-2 I2C Master/Slave General Configuration ...................................................................33–2
33-3 I2C Transfer Timing ...................................................................................................33–3
33-4 I2C Master Write Timing............................................................................................33–4
33-5 I2C Master Read Timing ............................................................................................33–5
33-6 I2C Mode Register (I2MOD)......................................................................................33–6
33-7 I2C Address Register (I2ADD) ..................................................................................33–7
33-8 I2C Baud Rate Generator Register (I2BRG) ..............................................................33–7
33-9 I2C Event/Mask Registers (I2CER/I2CMR) ..............................................................33–8
33-10 I2C Command Register (I2COM) ..............................................................................33–9
33-11 I2C Function Code Registers (RFCR/TFCR)...........................................................33–10
33-12 I
33-13 I2C Receive Buffer Descriptor (RxBD) ...................................................................33–13
33-14 I2C Transmit Buffer Descriptor (TxBD) ..................................................................33–13
34-1 Port A Open-Drain Register (PAODR) ......................................................................34–3
34-2 Port A Data Register (PADAT) ..................................................................................34–3
34-3 Port A Data Direction Register (PADIR) ...................................................................34–4
34-4 Port A Pin Assignment Register (PAPAR).................................................................34–4
34-5 Block Diagram for PA15 (True for all Non-Open-Drain Port Signals)......................34–6
34-6 Block Diagram for PA14 (True for all Open-Drain Port Signals)..............................34–6
34-7 Port B Open-Drain Register (PBODR).......................................................................34–8
34-8 Port B Data Register (PBDAT)...................................................................................34–9
34-9 Port B Data Direction Register (PBDIR)..................................................................34–10
34-10 Port B Pin Assignment Register (PBPAR) ...............................................................34–10
34-11 Port C Data Register (PCDAT).................................................................................34–13
2
C Memory Structure ..............................................................................................33–12
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34-12 Port C Data Direction Register (PCDIR)..................................................................34–14
34-13 Port C Pin Assignment Register (PCPAR) ...............................................................34–14
34-14 Port C Special Options Register (PCSO)..................................................................34–15
34-15 Port C Interrupt Control Register (PCINT) ..............................................................34–16
34-16 Port D Data Register (PDDAT) ................................................................................34–17
34-17 Port D Data Direction Register (PDDIR) .................................................................34–18
34-18 Port D Pin Assignment Register (PDPAR)...............................................................34–18
35-1 MPC850 Interrupt Structure .......................................................................................35–2
35-2 Interrupt Request Masking..........................................................................................35–5
35-3 CPM Interrupt Configuration Register (CICR) ..........................................................35–7
35-4 CPM Interrupt Pending/Mask/In-Service Registers (CIPR/CIMR/CISR) .................35–8
35-5 CPM Interrupt Vector Register (CIVR)....................................................................35–10
36-1 MPC850SR Application Example ..............................................................................36–4
36-2 Expanded Cell Structure .............................................................................................36–7
37-1 Transmit Buffer and TxBD Table Example................................................................37–2
37-2 AAL0 Buffer Structure ...............................................................................................37–3
37-3 ATM RxBD ................................................................................................................37–3
37-4 ATM RxBD in Expanded Cell Mode (UTOPIA Only) ..............................................37–4
37-5 ATM TxBD.................................................................................................................37–7
37-6 ATM TxBD in Expanded Cell Mode (UTOPIA Only) ..............................................37–7
37-7 Connection Tables in Dual-port RAM and External Memory..................................37–10
37-8 Receive Connection Table (RCT).............................................................................37–10
37-9 Transmit Connection Table (TCT) ...........................................................................37–13
38-1 SAR Receive Function Code Register (SRFCR)........................................................38–5
38-2 SAR Receive State Register (SRSTATE)...................................................................38–6
38-3 SAR Transmit Function Code Register (STFCR) ......................................................38–7
38-4 SAR Transmit State Register (STSTATE) .................................................................38–7
38-5 HMASK Cell Header Mask Fields .............................................................................38–9
38-6 FLMASK ..................................................................................................................38–10
38-7 APC State Register (APCST) ...................................................................................38–11
38-8 Serial Cell Synchronization Status Register (ASTATUS)........................................38–12
39-1 Address Mapping Tables for Internal Channels .........................................................39–2
39-2 Address Compression .................................................................................................39–4
39-4 Address Mapping Tables for Multi-PHY Operations.................................................39–6
39-3 Multi-PHY Pointing Table Entry................................................................................39–6
39-5 CP Command Register (CPCR) (ATM-Specific).......................................................39–8
40-1 APC in UTOPIA Mode—Transmit Flow ...................................................................40–2
40-2 Example of Single PHY and Single Serial APC Configuration .................................40–8
40-3 Example of Maximum Multi-PHY and Multi-Serial APC Configuration..................40–8
40-4 APC Scheduling Tables ..............................................................................................40–9
40-5 PHY Transmit Queue................................................................................................40–10
41-1 ATM Interrupt Queue .................................................................................................41–1
41-2 UTOPIA Event Register (IDSR1) and Mask Register (IDMR1) ...............................41–2
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41-3 Serial ATM Event Register (SCCE) and Mask Register (SCCM) .............................41–3
41-4 Interrupt Queue Entry .................................................................................................41–4
41-5 Interrupt Queue Mask (IMASK).................................................................................41–6
42-1 Port D Pin Assignment Register (PDPAR).................................................................42–1
42-2 System Clock Control Register (SCCR).....................................................................42–3
42-3 Serial ATM Mode Register (PSMR) ..........................................................................42–6
43-1 MPC850SR UTOPIA Interface ..................................................................................43–3
43-2 UTOPIA Receiver Start of Cell ..................................................................................43–4
43-3 UTOPIA Receiver End of Cell ...................................................................................43–5
43-4 UTOPIA Transmitter Start of Cell..............................................................................43–6
43-5 UTOPIA Transmitter End of Cell...............................................................................43–6
43-6 Multi-PHY Implementation Example.........................................................................43–9
43-7 UTOPIA Receiver Multi-PHY Example ..................................................................43–10
43-8 UTOPIA Transmitter Multi-PHY Example..............................................................43–10
44-1 Watchpoints and Breakpoint Support in the Core ......................................................44–9
44-2 Instruction Support General Structure ......................................................................44–12
44-3 Load/Store Support General Structure......................................................................44–13
44-4 Partially Supported Watchpoints/Breakpoint Example ............................................44–17
44-5 Functional Diagram of the MPC850 Debug Mode Support .....................................44–20
44-6 Debug Mode Logic Diagram ....................................................................................44–21
44-7 Debug Mode Reset Configuration Timing Diagram ................................................44–22
44-8 Development Port/BDM Connector Pinout Options ................................................44–27
44-9 Asynchronous Clocked Serial Communications ......................................................44–29
44-10 Synchronous Self-Clocked Serial Communications.................................................44–29
44-11 Enabling Clock Mode after Reset .............................................................................44–30
44-12 Download Procedure Code Example ........................................................................44–34
44-13 Fast and Slow Download Procedure Loops ..............................................................44–35
44-14 Comparator A–D Value Register (CMPA–CMPD) .................................................44–37
44-15 Comparator E–F Value Registers (CMPE–CMPF) ..................................................44–38
44-16 Comparator G–H Value Registers (CMPG–CMPH)................................................44–38
44-17 Breakpoint Address Register (BAR) ........................................................................44–38
44-18 Instruction Support Control Register (ICTRL).........................................................44–39
44-19 Load/Store Support Comparators Control Register (LCTRL1)................................44–40
44-20 Load/Store Support AND-OR Control Register (LCTRL2).....................................44–41
44-21 Breakpoint Counter Value and Control Registers (COUNTA/COUNTB)...............44–43
44-22 Interrupt Cause Register (ICR) .................................................................................44–44
44-23 Debug Enable Register (DER)..................................................................................44–46
45-1 Test Logic Block Diagram..........................................................................................45–2
45-2 TAP Controller State Machine....................................................................................45–3
45-3 Output Signal Boundary Scan Cell (Output Cell).......................................................45–4
45-4 Observe-Only Input Signal Boundary Scan Cell (Input Cell) ....................................45–4
45-5 Input/Output Control Boundary Scan Cell (I/O Control Cell)....................................45–5
45-6 Bidirectional (I/O) Signal Boundary Scan Cell ..........................................................45–5
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45-7 Bypass Register...........................................................................................................45–7
A-1 TLE Mode Mechanisms............................................................................................... A-3
A-2 Byte Swapping............................................................................................................. A-4
A-3 PPC-LE Mode Mechanisms......................................................................................... A-7
E-1 MPC850 Block Diagram.............................................................................................. E–2
F-1 MPC850DSL Block Diagram ...................................................................................... F–2
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TABLES
Tabl e Number
1-1 MPC850 Functionality Matrix......................................................................................1–2
2-1 MPC850 Internal Memory Map.................................................................................... 2-1
3-1 Static Branch Prediction ............................................................................................... 3-9
3-2 Bus Cycles Needed for Single-Register Load/Store Accesses ................................... 3-13
3-3 UISA-Level Features .................................................................................................. 3-15
3-4 VEA-Level Features ................................................................................................... 3-16
3-5 OEA-Level Features ................................................................................................... 3-17
4-1 User-Level PowerPC Registers..................................................................................... 4-2
4-2 User-Level PowerPC SPRs........................................................................................... 4-2
4-3 Bit Settings for CR0 Field of CR.................................................................................. 4-3
4-4 XER Field Definitions ..................................................................................................4-4
4-5 Supervisor-Level PowerPC Registers........................................................................... 4-4
4-6 Supervisor-Level PowerPC SPRs ................................................................................. 4-5
4-7 Value Summary of the DAR, BAR, and DSISR Registers........................................... 4-6
4-8 MSR Field Descriptions................................................................................................ 4-7
4-9 MPC850-Specific Supervisor-Level SPRs ................................................................... 4-9
4-10 MPC850-Specific Debug-Level SPRs........................................................................ 4-10
4-11 Addresses of SPRs Located Outside of the Core........................................................ 4-11
5-1 Memory Operands ........................................................................................................ 5-2
5-2 Integer Arithmetic Instructions ..................................................................................... 5-8
5-3 Integer Compare Instructions........................................................................................ 5-9
5-4 Integer Logical Instructions ........................................................................................ 5-10
5-5 Integer Rotate Instructions.......................................................................................... 5-11
5-6 Integer Shift Instructions............................................................................................. 5-11
5-7 Integer Load Instructions ............................................................................................ 5-12
5-8 Integer Store Instructions............................................................................................ 5-13
5-9 Integer Load and Store with Byte-Reverse Instructions ............................................ 5-13
5-10 Integer Load and Store Multiple Instructions ............................................................. 5-14
5-11 Integer Load and Store String Instructions ................................................................. 5-14
5-12 Branch Instructions ..................................................................................................... 5-16
5-13 Condition Register Logical Instructions ..................................................................... 5-16
5-14 Trap Instructions ......................................................................................................... 5-16
5-15 Move to/from Condition Register Instructions ........................................................... 5-17
5-16 Memory Synchronization Instructions—UISA .......................................................... 5-17
5-17 Move from Time Base Instruction.............................................................................. 5-19
5-18 Memory Synchronization Instructions—VEA ........................................................... 5-20
5-19 User-Level Cache Instructions.................................................................................... 5-21
5-20 System Linkage Instructions....................................................................................... 5-22
5-21 Move to/from Machine State Register Instructions .................................................... 5-22
5-22 Move to/from Special-Purpose Register Instructions ................................................. 5-22
6-1 Offset of First Instruction by Exception Type .............................................................. 6-2
6-2 Instruction-Related Exception Detection Order............................................................ 6-4
6-3 Exception Priority ......................................................................................................... 6-4
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TABLES
Tabl e Number
6-4 Register Settings after a System Reset Interrupt Exception ......................................... 6-5
6-5 Register Settings after a Machine Check Interrupt Exception...................................... 6-5
6-6 Register Settings after an External Interrupt................................................................. 6-7
6-7 Register Settings after an Alignment Exception........................................................... 6-8
6-8 Register Settings after a Program Exception ................................................................ 6-9
6-9 Register Settings after a Decrementer Exception ....................................................... 6-10
6-10 Register Settings after a System Call Exception......................................................... 6-11
6-11 Register Settings after a Trace Exception................................................................... 6-11
6-12 Register Settings after a Software Emulation Exception............................................ 6-12
6-13 Register Settings after an Instruction TLB Miss Exception ....................................... 6-13
6-14 Register Settings after a Data TLB Miss Exception ................................................... 6-13
6-15 Register Settings after an Instruction TLB Error Exception....................................... 6-14
6-16 Register Settings after a Data TLB Error Exception .................................................. 6-14
6-17 Register Settings after a Debug Exception ................................................................. 6-15
6-18 Additional SPRs that Affect MSR Bits....................................................................... 6-17
6-19 Exception Latency ...................................................................................................... 6-19
6-20 Before and After Exceptions....................................................................................... 6-20
7-1 Instruction Cache Control and Status Register—IC_CST............................................7–7
7-2 Instruction Cache Address Register—IC_ADR ...........................................................7–8
7-3 Instruction Cache Data Port Register—IC_DAT .........................................................7–8
7-4 IC_ADR Fields for Cache Read Commands ................................................................7–8
7-5 IC_DAT Format for a Tag Read (IC_ADR[18] = 0)...................................................7–9
7-6 Data Cache Control and Status Register—DC_CST ..................................................7–12
7-7 Data Cache Address Register—DC_ADR..................................................................7–14
7-8 Data Cache Data Port Register—DC_DAT................................................................7–14
7-9 DC_ADR Fields for Cache Read Commands.............................................................7–14
7-10 DC_DAT Format for a Tag Read (DC_ADR[18] = 0)..............................................7–15
7-11 Copyback Buffer Select Field (DC_ADR[23–27]) Encoding ....................................7–15
8-1 Identical Entries Required in Level-One/Level-Two Tables......................................8–10
8-2 Number of Replaced EA Bits per Page Size...............................................................8–11
8-3 Level-One Segment Descriptor Format ......................................................................8–12
8-4 Level-Two (Page) Descriptor Format.........................................................................8–13
8-5 Page Size Selection .....................................................................................................8–14
8-6 MPC850-Specific MMU SPRs...................................................................................8–14
8-7 MI_CTR Field Descriptions .......................................................................................8–16
8-8 MD_CTR Field Descriptions......................................................................................8–17
8-9 Mx_EPN Field Descriptions.......................................................................................8–18
8-10 MI_TWC Field Descriptions ......................................................................................8–18
8-11 MD_TWC Field Descriptions.....................................................................................8–19
8-12 MI_RPN Field Descriptions .......................................................................................8–21
8-13 MD_RPN Field Descriptions......................................................................................8–22
8-14 M_TWB Field Descriptions........................................................................................8–23
8-15 M_CASID Field Descriptions.....................................................................................8–23
Title
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8-16 MI_AP/MD_AP Field Descriptions ...........................................................................8–24
8-17 MI_CAM Field Descriptions ......................................................................................8–25
8-18 MI_RAM0 Field Descriptions ....................................................................................8–26
8-19 MI_RAM1 Field Descriptions ....................................................................................8–27
8-20 MD_CAM Field Descriptions.....................................................................................8–28
8-21 MD_RAM0 Field Descriptions...................................................................................8–29
8-22 MD_RAM1 Field Descriptions...................................................................................8–30
8-23 MPC850-Specific MMU Exceptions..........................................................................8–31
9-1 Instruction Execution Timing .......................................................................................9–6
9-2 Load/Store Instructions Timing ....................................................................................9–7
10-1 Multiplexing Control ..................................................................................................10–4
10-2 MMR Field Descriptions ............................................................................................10–5
10-3 SIUMCR Field Descriptions.......................................................................................10–6
10-4 SYPCR Field Descriptions .........................................................................................10–8
10-5 TESR Field Descriptions ............................................................................................10–9
10-6 Key Registers............................................................................................................10–10
10-7 Priority of SIU Interrupt Sources..............................................................................10–13
10-8 IRQ0 Versus IRQx Operation...................................................................................10–15
10-9 SIPEND Field Descriptions ......................................................................................10–16
10-10 SIMASK Field Descriptions.....................................................................................10–17
10-11 SIEL Field Descriptions............................................................................................10–18
10-12 SIVEC Field Descriptions.........................................................................................10–19
10-13 SWSR Field Descriptions .........................................................................................10–22
10-14 Decrementer Timeout Values ...................................................................................10–23
10-15 DEC Field Descriptions ............................................................................................10–24
10-16 TBU Field Descriptions ............................................................................................10–25
10-17 TBL Field Descriptions.............................................................................................10–25
10-18 TBREFA/TBREFB Field Descriptions.....................................................................10–26
10-19 TBSCR Field Descriptions .......................................................................................10–27
10-20 RTCSC Field Descriptions .......................................................................................10–28
10-21 RTC Field Description..............................................................................................10–29
10-22 RTCAL Field Descriptions.......................................................................................10–30
10-23 RTSEC Field Descriptions........................................................................................10–31
10-24 PISCR Field Descriptions.........................................................................................10–32
10-25 PITC Field Descriptions ...........................................................................................10–33
10-26 PITR Field Descriptions ...........................................................................................10–34
11-1 MPC850 Reset Responses ..........................................................................................11–1
11-2 Reset Status Register Bit Settings...............................................................................11–6
11-3 Hard Reset Configuration Word Field Descriptions...................................................11–9
12-1 Signal Descriptions .....................................................................................................12–5
12-2 Active Pull-Up Resistors Enabled as Outputs ..........................................................12–19
12-3 Signal States during Hardware Reset........................................................................12–22
13-1 MPC850 Signal Overview ..........................................................................................13–3
Title
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13-2 Data Bus Requirements for Read Cycles..................................................................13–25
13-3 Data Bus Contents for Write Cycles.........................................................................13–26
13-4 BURST/TSIZ Encoding............................................................................................13–31
13-5 Address Types Definition .........................................................................................13–32
13-6 Termination Signals Protocol ...................................................................................13–41
14-1 Power-On Reset SPLL Configuration ........................................................................14–6
14-2 XFC Capacitor Values Based on PLPRCR[MF] ........................................................14–8
14-3 Functionality Summary of the Clocks ........................................................................14–9
14-4 PITRTCLK Configuration at PORESET..................................................................14–16
14-5 TMBCLK Configuration ..........................................................................................14–16
14-6 MPC850 Modules vs. Power Rails ...........................................................................14–17
14-7 MPC850 Low-Power Modes ....................................................................................14–19
14-8 SCCR Field Descriptions..........................................................................................14–28
14-9 PLPRCR Field Descriptions .....................................................................................14–30
14-10 PLPRCR[CSR] and DER[CHSTPE] Bit Combinations...........................................14–31
15-1 Memory Controller Register Usage ............................................................................15–6
15-2 Access Granularities for Predefined Port Sizes ..........................................................15–8
15-3 BRx Field Descriptions.............................................................................................15–10
15-4 ORx Field Descriptions.............................................................................................15–12
15-5 MSTAT Field Descriptions.......................................................................................15–13
15-6 MxMR Field Descriptions ........................................................................................15–14
15-7 MCR Field Descriptions ...........................................................................................15–16
15-8 MDR Field Descriptions...........................................................................................15–17
15-9 MAR Field Description.............................................................................................15–18
15-10 MPTPR Field Descriptions.......................................................................................15–18
15-11 GPCM Strobe Signal Behavior.................................................................................15–19
15-12 Boot Bank Field Values after Reset..........................................................................15–29
15-13 UPM Start Address Locations ..................................................................................15–37
15-14 RAM Word Bit Settings............................................................................................15–38
15-15 Enabling Byte-Selects...............................................................................................15–42
15-16 GPL_X5 Signal Behavior .........................................................................................15–44
15-17 MxMR Loop Field Usage .........................................................................................15–45
15-18 Address Multiplexing................................................................................................15–46
15-19 AMA/AMB Definition for DRAM Interface............................................................15–47
15-20 UPMA Register Settings...........................................................................................15–64
15-21 UPMB Register Settings...........................................................................................15–75
16-1 PCMCIA Cycle Control Signals.................................................................................16–3
16-2 PCMCIA Input Port Signals .......................................................................................16–4
16-3 PCMCIA Output Port Signals.....................................................................................16–5
16-4 Other PCMCIA Signals ..............................................................................................16–5
16-5 Host Programming for Memory Cards .......................................................................16–6
16-6 Host Programming For I/O Cards...............................................................................16–6
16-7 PCMCIA Registers .....................................................................................................16–8
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16-8 PIPR Field Descriptions..............................................................................................16–9
16-9 PSCR Field Descriptions ............................................................................................16–9
16-10 PER Field Descriptions.............................................................................................16–10
16-11 PGCRB Field Descriptions.......................................................................................16–12
16-12 PBR Field Descriptions.............................................................................................16–12
16-13 POR Field Descriptions ............................................................................................16–13
17-1 TGCR Field Descriptions ...........................................................................................17–8
17-2 TMR1–TMR4 Field Descriptions...............................................................................17–9
17-3 TER Field Descriptions.............................................................................................17–11
18-1 Peripheral Prioritization ..............................................................................................18–3
18-2 CP Microcode Revision Number ................................................................................18–4
18-3 RCCR Field Descriptions ...........................................................................................18–4
18-4 RMDS Field Descriptions...........................................................................................18–6
18-5 CPCR Field Descriptions............................................................................................18–6
18-6 CP Command Opcodes...............................................................................................18–7
18-7 CP Commands ............................................................................................................18–8
18-8 General BD Structure................................................................................................18–12
18-9 Parameter RAM Memory Map ................................................................................18–12
18-10 I2C and SPI Parameter RAM Relocation .................................................................18–13
18-11 RISC Timer Table Parameter RAM Memory Map ..................................................18–15
18-12 TM_CMD Field Descriptions...................................................................................18–15
18-13 PWM Channel Pin Assignments...............................................................................18–17
19-1 U-Bus Arbitration IDs.................................................................................................19–2
19-2 SDCR Bit Settings ......................................................................................................19–4
19-3 SDSR Field Descriptions ............................................................................................19–5
19-4 IDMA Parameter RAM Memory Map .......................................................................19–6
19-5 DCMR Field Descriptions ..........................................................................................19–8
19-6 IDSR1/IDSR2 Field Descriptions...............................................................................19–8
19-7 IDMA BD Status and Control Bits ...........................................................................19–10
19-8 SFCR and DFCR Field Descriptions .......................................................................19–11
19-9 Single-Buffer Mode IDMA1 Parameter RAM Map.................................................19–18
19-10 DCMR Field Descriptions (Single-Buffer Mode) ....................................................19–19
20-1 TSA Signals ................................................................................................................20–7
20-2 SIRAM Field Descriptions .......................................................................................20–11
20-3 Example SI RAM Entry Settings for an IDL Bus.....................................................20–13
20-4 SIGMR Field Descriptions .......................................................................................20–14
20-5 SIMODE Field Descriptions.....................................................................................20–15
20-6 SICR Field Descriptions ...........................................................................................20–21
20-7 SICMR Field Descriptions........................................................................................20–22
20-8 SISTR Field Descriptions .........................................................................................20–22
20-9 SIRP Field Descriptions............................................................................................20–24
20-10 SIRP Pointer Values ................................................................................................20–24
20-11 SI RAM Settings for IDL Interface ..........................................................................20–28
Title
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20-12 SI RAM Settings for GCI Interface (SCIT Mode)....................................................20–31
20-13 BRGCn Field Descriptions .......................................................................................20–36
20-14 Typical Baud Rates for Asynchronous Communication ..........................................20–38
21-1 GSMR_H Field Descriptions......................................................................................21–4
21-2 GSMR_L Field Descriptions ......................................................................................21–6
21-3 TODR Field Descriptions .........................................................................................21–10
21-4 SCC Parameter RAM Map for All Protocols ...........................................................21–13
21-5 RFCRx /TFCRx Field Descriptions..........................................................................21–15
21-6 SCCx Event, Mask, and Status Registers ................................................................21–16
21-7 Preamble Requirements ............................................................................................21–23
21-8 DPLL Codings ..........................................................................................................21–24
22-1 UART-Specific SCC Parameter RAM Memory Map ................................................22–4
22-2 Transmit Commands...................................................................................................22–6
22-3 Receive Commands ....................................................................................................22–6
22-4 Control Character Table, RCCM, and RCCR Descriptions .......................................22–8
22-5 TOSEQ Field Descriptions .......................................................................................22–10
22-6 DSR Fields Descriptions...........................................................................................22–11
22-7 Transmission Errors ..................................................................................................22–12
22-8 Reception Errors .......................................................................................................22–12
22-9 PSMR UART Field Descriptions..............................................................................22–13
22-10 SCC UART RxBD Status and Control Field Descriptions.......................................22–16
22-11 SCC UART TxBD Status and Control Field Descriptions.......................................22–17
22-12 SCCE/SCCM Field Descriptions for UART Mode..................................................22–20
22-13 UART SCCS Field Descriptions ..............................................................................22–21
22-14 UART Control Characters for S-Records Example..................................................22–23
23-1 HDLC-Specific SCC Parameter RAM Memory Map ................................................23–4
23-2 Transmit Commands...................................................................................................23–5
23-3 Receive Commands ...................................................................................................23–6
23-4 Transmit Errors .........................................................................................................23–6
23-5 Receive Errors.............................................................................................................23–6
23-6 PSMR HDLC Field Descriptions................................................................................23–7
23-7 SCC HDLC RxBD Status and Control Field Descriptions.........................................23–9
23-8 SCC HDLC TxBD Status and Control Field Descriptions.......................................23–11
23-9 SCCE/SCCM Field Descriptions..............................................................................23–12
23-10 HDLC SCCS Field Descriptions ..............................................................................23–14
25-1 Asynchronous HDLC-Specific SCC Parameter RAM Memory Map ........................25–5
25-2 Asynchronous HDLC-Specific GSMR Field Descriptions ........................................25–7
25-3 Transmit Commands...................................................................................................25–8
25-4 Receive Commands ...................................................................................................25–8
25-5 Transmit Errors ...........................................................................................................25–8
25-6 Receive Errors.............................................................................................................25–9
25-7 SCCE/SCCM Field Descriptions..............................................................................25–10
25-8 Asynchronous HDLC SCCS Field Descriptions ......................................................25–11
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25-9 PSMR Field Descriptions .........................................................................................25–11
25-10 Asynchronous HDLC RxBD Status and Control Field Descriptions .......................25–12
25-11 Asynchronous HDLC TxBD Status and Control Field Descriptions .......................25–13
26-1 SCC BISYNC Parameter RAM Memory Map...........................................................26–4
26-2 Transmit Commands...................................................................................................26–5
26-3 Receive Commands ....................................................................................................26–5
26-4 Control Character Table and RCCM Field Descriptions............................................26–7
26-5 BSYNC Field Descriptions.........................................................................................26–8
26-6 BDLE Field Descriptions............................................................................................26–8
26-7 Receiver SYNC Pattern Lengths of the DSR .............................................................26–9
26-8 Transmit Errors ...........................................................................................................26–9
26-9 Receive Errors...........................................................................................................26–10
26-10 PSMR Field Descriptions .........................................................................................26–11
26-11 SCC BISYNC RxBD Status and Control Field Descriptions...................................26–12
26-12 SCC BISYNC TxBD Status and Control Field Descriptions ...................................26–14
26-13 SCCE/SCCM Field Descriptions..............................................................................26–15
26-14 SCCS Field Descriptions ..........................................................................................26–16
26-15 Control Characters ....................................................................................................26–17
27-1 SCC Ethernet Parameter RAM Memory Map ............................................................27–8
27-2 Transmit Commands.................................................................................................27–10
27-3 Receive Commands ..................................................................................................27–10
27-4 Transmission Errors ..................................................................................................27–14
27-5 Reception Errors .......................................................................................................27–15
27-6 PSMR Field Descriptions .........................................................................................27–15
27-7 SCC Ethernet RxBD Status and Control Field Descriptions ....................................27–17
27-8 SCC Ethernet TxBD Status and Control Field Descriptions ....................................27–19
27-9 SCCE/SCCM Field Descriptions..............................................................................27–20
28-1 Receiver SYNC Pattern Lengths of the DSR .............................................................28–3
28-2 SCC Transparent Parameter RAM Memory Map ......................................................28–6
28-3 Transmit Commands...................................................................................................28–7
28-4 Receive Commands ....................................................................................................28–7
28-5 Transmit Errors ...........................................................................................................28–8
28-6 Receive Errors.............................................................................................................28–8
28-7 SCC Transparent RxBD Status and Control Field Descriptions ................................28–9
28-8 SCC Transparent Tx BD Status and Control Field Descriptions..............................28–10
28-9 SCCE/SCCM Field Descriptions..............................................................................28–12
28-10 SCCS Field Descriptions ..........................................................................................28–13
29-1 4PPM Encoding ..........................................................................................................29–4
29-2 IRMODE Field Descriptions ......................................................................................29–6
29-3 IRSIP Field Descriptions ............................................................................................29–7
30-1 SMCMR Field Descriptions .......................................................................................30–3
30-2 SMC UART and Transparent Parameter RAM Memory Map ..................................30–6
30-3 RFCR/TFCR Field Descriptions.................................................................................30–8
Title
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TABLES
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30-4 SMC UART-Specific Parameter RAM Memory Map .............................................30–11
30-5 Transmit Commands.................................................................................................30–13
30-6 Receive Commands ..................................................................................................30–13
30-7 SMC UART Errors ...................................................................................................30–14
30-8 SMC UART RxBD Status and Control Field Descriptions......................................30–15
30-9 SMC UART TxBD Status and Control Field Descriptions ......................................30–17
30-10 SMCE/SMCM Field Descriptions ............................................................................30–18
30-11 SMC Transparent Transmit Commands ...................................................................30–25
30-12 SMC Transparent Receive Commands.....................................................................30–25
30-13 SMC Transparent Error Conditions ..........................................................................30–26
30-14 SMC Transparent RxBD Field Descriptions ............................................................30–26
30-15 SMC Transparent TxBD Field Descriptions.............................................................30–28
30-16 SMCE/SMCM Field Descriptions ............................................................................30–29
30-17 SMC GCI Parameter RAM Memory Map...............................................................30–32
30-18 SMC GCI Commands...............................................................................................30–33
30-19 SMC Monitor Channel RxBD Field Descriptions....................................................30–34
30-20 SMC Monitor Channel TxBD Field Descriptions ....................................................30–34
30-21 SMC C/I Channel RxBD Field Descriptions............................................................30–35
30-22 SMC C/I Channel TxBD Field Descriptions ............................................................30–35
30-23 SMCE/SMCM Field Descriptions ............................................................................30–36
31-1 SPMODE Field Descriptions......................................................................................31–7
31-2 Example Conventions .................................................................................................31–9
31-3 SPIE/SPIM Field Descriptions .................................................................................31–10
31-4 SPCOM Field Descriptions.......................................................................................31–11
31-5 SPI Parameter RAM Memory Map ..........................................................................31–11
31-6 RFCR/TFCR Field Descriptions...............................................................................31–12
31-7 SPI Commands..........................................................................................................31–13
31-8 SPI RxBD Status and Control Field Descriptions ....................................................31–15
31-9 SPI TxBD Status and Control Field Descriptions.....................................................31–16
32-1 USB Signal Functions.................................................................................................32–4
32-2 USB Tokens................................................................................................................32–6
32-3 USB Parameter RAM Memory Map ..........................................................................32–7
32-4 Endpoint Parameter Block ..........................................................................................32–8
32-5 FRAME_N Field Descriptions ...................................................................................32–9
32-6 TFCR/RFCR Field Descriptions...............................................................................32–10
32-7 USMOD Field Descriptions......................................................................................32–10
32-8 USADR Field Descriptions.......................................................................................32–11
32-9 USEPn Field Descriptions ........................................................................................32–12
32-10 USCOM Field Descriptions......................................................................................32–13
32-11 USBER/USBMR Field Descriptions ........................................................................32–13
32-12 USBS Field Descriptions ..........................................................................................32–14
32-13 RxBD Status and Control Field Descriptions ...........................................................32–17
32-14 TxBD Status and Control Field Descriptions ...........................................................32–19
Title
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32-15 USB Command Format Field Descriptions ..............................................................32–20
32-16 USB Controller Transmission Errors........................................................................32–21
32-17 USB Controller Reception Errors .............................................................................32–22
33-1 I2MOD Field Descriptions .........................................................................................33–6
33-2 I2ADD Field Descriptions ..........................................................................................33–7
33-3 I2BRG Field Descriptions...........................................................................................33–8
33-4 I2CER/I2CMR Field Descriptions..............................................................................33–8
33-5 I2COM Field Descriptions..........................................................................................33–9
33-6 I
33-7 RFCR/TFCR Field Descriptions...............................................................................33–11
33-8 I2C Transmit/Receive Commands............................................................................33–11
33-9 I2C RxBD Status and Control Bits ...........................................................................33–13
33-10 I2C TxBD Status and Control Bits ...........................................................................33–14
34-1 Port A Pin Assignment................................................................................................34–2
34-2 PAODR Bit Descriptions............................................................................................34–3
34-3 PADAT Bit Descriptions ............................................................................................34–4
34-4 PADIR Bit Descriptions .............................................................................................34–4
34-5 PAPAR Bit Descriptions.............................................................................................34–5
34-6 Port B Pin Assignment................................................................................................34–7
34-7 PBODR Bit Descriptions ............................................................................................34–8
34-8 PBDAT Bit Descriptions ............................................................................................34–9
34-9 PBDIR Bit Descriptions............................................................................................34–10
34-10 PBPAR Bit Descriptions...........................................................................................34–11
34-11 Port C Pin Assignment..............................................................................................34–11
34-12 PCDAT Bit Descriptions ..........................................................................................34–14
34-13 PCDIR Bit Descriptions............................................................................................34–14
34-14 PCPAR Bit Descriptions...........................................................................................34–15
34-15 PCSO Bit Descriptions .............................................................................................34–15
34-16 PCINT Bit Descriptions............................................................................................34–16
34-17 Port D Pin Assignment..............................................................................................34–17
34-18 PDDAT Bit Descriptions ..........................................................................................34–18
34-19 PDDIR Bit Descriptions ...........................................................................................34–18
34-20 PDPAR Bit Descriptions...........................................................................................34–19
35-1 Prioritization of CPM Interrupt Sources .....................................................................35–3
35-2 Interrupt Vector Encodings.........................................................................................35–6
35-3 CICR Field Descriptions.............................................................................................35–7
35-4 CIVR Field Descriptions...........................................................................................35–10
37-1 ATM RxBD Field Descriptions..................................................................................37–5
37-2 ATM TxBD Field Descriptions ..................................................................................37–8
37-3 RCT Field Descriptions ............................................................................................37–11
37-4 TCT Field Descriptions.............................................................................................37–13
38-1 Serial ATM and UTOPIA Interface Parameter RAM Map ........................................38–1
38-2 Serial ATM Parameter RAM Map..............................................................................38–4
2
C Parameter RAM Memory Map ............................................................................33–9
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38-3 SRFCR Field Descriptions..........................................................................................38–5
38-4 SRSTATE Field Descriptions.....................................................................................38–6
38-5 STFCR Field Descriptions..........................................................................................38–7
38-6 STSTATE Field Descriptions .....................................................................................38–8
38-7 AM1–AM5 Parameters for the Internal Look-up Table .............................................38–9
38-8 HMASK Field Descriptions........................................................................................38–9
38-9 AM1–AM5 Parameters for Extended Channel Address Compression.....................38–10
38-10 FLMASK Field Descriptions....................................................................................38–10
38-11 AM1–AM5 Parameters for Extended Channel CAM Operation..............................38–11
38-12 APCST Field Descriptions........................................................................................38–11
38-13 ASTATUS Register Field Descriptions....................................................................38–12
39-1 CPCR ATM-Specific Field Descriptions....................................................................39–8
39-2 ATM Commands ........................................................................................................39–9
40-1 APC Priority Levels..................................................................................................40–10
40-2 APC Priority Level Parameter Descriptions .............................................................40–11
41-1 UTOPIA Event Register (IDSR1) Field Descriptions ................................................41–2
41-2 Serial ATM Event Register (SCCE) Field Descriptions.............................................41–3
41-3 Interrupt Queue Entry Field Descriptions...................................................................41–4
42-1 PDPAR Field Descriptions .........................................................................................42–1
42-2 SCCR Field Descriptions for the UTOPIA Clock ......................................................42–3
42-3 Port D Pin Assignment ...............................................................................................42–5
42-4 PSMR Serial ATM Field Descriptions .......................................................................42–7
43-1 MPC850SAR Signal Functions ..................................................................................43–1
43-2 UTOPIA Interface Transfer Timing .........................................................................43–11
44-1 Fetch Show Cycles Control ........................................................................................44–3
44-2 Status Pin Groupings...................................................................................................44–3
44-3 VF Pins Encoding: Instruction Queue Flushes ...........................................................44–4
44-4 VF Pins Encoding: Instruction Fetch Types ...............................................................44–4
44-5 Detecting the Trace Buffer Start Point........................................................................44–7
44-6 Instruction Watchpoints Programming Options .......................................................44–12
44-7 Load/Store Data Events ............................................................................................44–14
44-8 Load/Store Watchpoints Programming Options.......................................................44–14
44-9 Checkstop State and Debug Mode............................................................................44–24
44-10 Trap Enable Data Shifted into Development Port Shift Register .............................44–31
44-11 Debug Port Command Shifted Into Development Port Shift Register .....................44–31
44-12 Status/Data Shifted Out of Development Port Shift Register...................................44–32
44-13 Debug Instructions/Data Shifted Into Development Port Shift Register ..................44–33
44-14 MPC850-Specific Development Support and Debug SPRs .....................................44–36
44-15 Development Support/Debug Registers Protection ..................................................44–37
44-16 CMPA–CMPD Field Descriptions ...........................................................................44–37
44-17 CMPE–CMPF Field Descriptions.............................................................................44–38
44-18 CMPG–CMPH Field Descriptions ...........................................................................44–38
44-19 BAR Field Descriptions............................................................................................44–39
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44-20 ICTRL Field Descriptions.........................................................................................44–39
44-21 LCTRL1 Field Descriptions .....................................................................................44–41
44-22 LCTRL2 Field Descriptions .....................................................................................44–42
44-23 COUNTA/COUNTB Field Descriptions..................................................................44–44
44-24 ICR Field Descriptions .............................................................................................44–44
44-25 DER Field Descriptions ............................................................................................44–46
45-1 Instruction Register Decoding ....................................................................................45–6
A-1 Byte-Ordering Parameters ........................................................................................... A-2
A-2 TLE 2-bit Munging...................................................................................................... A-3
A-3 Little-Endian Program/Data Path Between the Register and 32-Bit Memory............. A-5
A-4 Little-Endian Program/Data Path Between the Register and 16-Bit Memory............. A-5
A-5 Little-Endian Program/Data Path between the Register and 8-Bit Memory ............... A-6
A-6 PPC-LE 3-bit Munging................................................................................................ A-7
B-1 MPC850 Serial Performance at 25 MHz ......................................................................B-4
B-2 IDMA Performance at 25 MHz ....................................................................................B-5
C-1 User-Level PowerPC Registers.....................................................................................C-1
C-2 User-Level PowerPC SPRs...........................................................................................C-1
C-3 Supervisor-Level PowerPC Registers ...........................................................................C-2
C-4 Supervisor-Level PowerPC SPRs .................................................................................C-2
C-5 MPC850-Specific Supervisor-Level SPRs ...................................................................C-3
C-6 MPC850-Specific Debug-Level SPRs ..........................................................................C-4
D-1 Complete Instruction List Sorted by Mnemonic.......................................................... D-1
D-2 Complete Instruction List Sorted by Opcode............................................................... D-9
D-3 Integer Arithmetic Instructions .................................................................................. D-17
D-4 Integer Compare Instructions..................................................................................... D-18
D-5 Integer Logical Instructions ....................................................................................... D-18
D-6 Integer Rotate Instructions......................................................................................... D-18
D-7 Integer Shift Instructions............................................................................................ D-19
D-8 Floating-Point Arithmetic Instructions6 .................................................................... D-19
D-9 Floating-Point Multiply-Add Instructions6 ............................................................... D-20
D-10 Floating-Point Rounding and Conversion Instructions6............................................ D-20
D-11 Floating-Point Compare Instructions6....................................................................... D-20
D-12 Floating-Point Status and Control Register Instructions6 ......................................... D-20
D-13 Integer Load Instructions ........................................................................................... D-21
D-14 Integer Store Instructions........................................................................................... D-22
D-15 Integer Load and Store with Byte-Reverse Instructions ............................................ D-22
D-16 Integer Load and Store Multiple Instructions ............................................................ D-22
D-17 Integer Load and Store String Instructions ................................................................ D-23
D-18 Memory Synchronization Instructions....................................................................... D-23
D-19 Floating-Point Load Instructions6 ............................................................................. D-23
D-20 Floating-Point Store Instructions6 ............................................................................. D-24
D-21 Floating-Point Move Instructions6 ............................................................................ D-24
D-22 Branch Instructions .................................................................................................... D-24
Title
Page
Number
Tables lxv
TABLES
Tabl e Number
D-23 Condition Register Logical Instructions .................................................................... D-24
D-24 System Linkage Instructions...................................................................................... D-25
D-25 Trap Instructions ........................................................................................................ D-25
D-26 Processor Control Instructions................................................................................... D-25
D-27 Cache Management Instructions................................................................................ D-26
D-28 Segment Register Manipulation Instructions............................................................. D-26
D-29 Lookaside Buffer Management Instructions.............................................................. D-26
D-30 External Control Instructions..................................................................................... D-26
D-31 I-Form ........................................................................................................................ D-27
D-32 B-Form....................................................................................................................... D-27
D-33 SC-Form..................................................................................................................... D-27
D-34 D-Form....................................................................................................................... D-27
D-35 DS-Form .................................................................................................................... D-30
D-36 X-Form....................................................................................................................... D-30
D-37 XL-Form .................................................................................................................... D-34
D-38 XFX-Form.................................................................................................................. D-35
D-39 XFL-Form.................................................................................................................. D-35
D-40 XS-Form .................................................................................................................... D-35
D-41 XO-Form.................................................................................................................... D-35
D-42 A-Form....................................................................................................................... D-36
D-43 M-Form...................................................................................................................... D-37
D-44 MD-Form ................................................................................................................... D-37
D-45 MDS-Form................................................................................................................. D-39
D-46 Instruction Set Legend ............................................................................................... D-41
Title
Page
Number
MPC850 Family User’s Manual
About This Book
The primary objective of this manual is to help communications system designers build systems using the Motorola MPC850 and to help software designers provide operating systems and user-level applications to take fullest advantage of the MPC850.
Although this book describes aspects regarding the PowerPC™ architecture that are critical for understanding the MPC850 core, it does not contain a complete description of the architecture. Where additional information might help the reader, references are made to The PowerPC Microprocessor Family: The Programming Environments. Ordering information for this book are provided in the section, “PowerPC Documentation.”
The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are using the most recent version of the documentation. Contact your sales representative for more information.
Before Using This Manual
Before using this manual, determine whether it is the latest revision and if there are errata or addenda. To locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/SPS/RISC/netcomm..
Note that this manual supports all members of the MPC850 family, however it is written from the perspective of the MPC850DE, which is the superset of the basic MPC850 device. References to the MPC850 actually refer to the MPC850DE unless otherwise specifically stated. The full family functionality is listed in Table 0-i. Refer to this table to determine the functionality of each MPC850.
. MPC850 Functionality Matrix
Part USB Support SCC Support ATM Support
MPC850 One USB port One SCC (SCC2) - includes Ethernet support
MPC850DE One USB port Two SCCs; both support Ethernet
MPC850SR One USB port Two SCCs: both support Ethernet, multi-channel HDLC, and serial
MPC850DSL One USB port SCC2 supports Ethernet only, SCC3 supports UART only.
Table 0-i MPC850 Family Functionality Matrix
AT M
Time slot assigner, SMC2 and I
2
C are not supported.
UTOPIA interface
UTOPIA interface
About This Book
Audience
This manual is intended for software and hardware developers and application programmers who want to develop products for the MPC850. It is assumed that the reader has a basic understanding of computer networking, OSI layers, and RISC architecture. In addition, it is assumed that the reader has a basic understanding of the communications protocols described here. Where it is considered useful, additional sources are provided that provide in-depth discussions of such topics.
Organization
Following is a summary and a brief description of the chapters of this manual:
Part I, “Overview,” provides a high-level description of the MPC850MPC850, describing general operation and listing basic features.
— Chapter 1, “Overview, ” provides a high-level description of MPC850 functions
and features. It roughly follows the structure of this book, summarizing the relevant features and providing references for the reader who needs additional information.
— Chapter 2, “Memory Map,” presents a table showing where MPC850 registers
are mapped in memory. It includes cross references that indicate where each register is described in detail.
Part II, “PowerPC Microprocessor Module,” describes the PowerPC microprocessor core embedded in the MPC850. These chapters provide details concerning the processor core as an implementation of the PowerPC architecture.
— Chapter 3, “The PowerPC Core,” provides an overview of the MPC850 core,
summarizing topics described in further detail in subsequent chapters in Part II.
— Chapter 4, “PowerPC Core Register Set,” describes the hardware registers
accessible to the MPC850 core. These include both architecturally-dened and MPC850-specic registers.
— Chapter 5, “MPC850 Instruction Set,” describes the PowerPC instructions
implemented by the MPC850. These instructions are organized by the level of architecture in which they are implemented—UISA, VEA, and OEA.
— Chapter 6, “Exceptions,” describes the PowerPC exception model as it is
implemented on the MPC850.
— Chapter 7, “Instruction and Data Caches,” describes the organization of the
on-chip instruction and data caches, cache control, various cache operations, and the interaction between the caches, the load/store unit (LSU), the instruction sequencer, and the system interface unit (SIU).
— Chapter 8, “Memory Management Unit” describes how the PowerPC MMU
model is implemented on the MPC850. Although the MPC850 MMU is based on the PowerPC MMU model, it differs greatly in many respects, which are described in this chapter.
MPC850 Family User’s Manual
— Chapter 9, “Instruction Execution Timing,” describes the MPC850 instruction
unit, and provides ways to make greatest advantage of its RISC architecture characteristics, such as pipelining and parallel execution. It includes a table of instruction latencies and lists dependencies and potential bottlenecks.
Part III, “Conguration and Reset,” describes start-up behavior of the MPC850.
— Chapter 10, “System Interface Unit,” describes the SIU, which controls system
start-up, initialization and operation, protection, as well as the external system bus.
— Chapter 11, “Reset,” describes the behavior of the MPC850 at reset and start-up.
Part IV, “The Hardware Interface,” describes external signals, clocking, memory control, and power management of the MPC850.
— Chapter 12, “External Signals,” provides a detailed description of the external
signals that comprise the MPC850 external interface.
— Chapter 13, “External Bus Interface,” describes interactions among signals
described in the previous chapter, including numerous examples and timing diagrams.
— Chapter 14, “Clocks and Power Control,” describes on-chip and external
devices, including the phase-locked loop circuitry and frequency dividers that generate programmable clock timing for baud-rate generators, timers, and a variety of low-power mode options.
— Chapter 15, “Memory Controller,” describes the memory controller, which
controlling a maximum of eight memory banks shared between a general-purpose chip-select machine (GPCM) and a pair of user-programmable machines (UPMs).
— Chapter 16, “PCMCIA Interface,” describes the PCMCIA host adapter module,
which provides all control logic for a PCMCIA socket interface and requires only additional external analog power switching logic and buffering.
Part V, “Communications Processor Module,” describes the conguration, clocking, and operation of the various communications protocols supported by the MPC850.
— Chapter 17, “Communications Processor Module and CPM Timers,” provides a
brief overview of the MPC850 CPM and a detailed discussion of the clocking mechanisms supported.
— Chapter 18, “Communications Processor,” describes the RISC communications
processor (CP), which handles the low-level communications tasks, freeing the core for higher-level tasks.
— Chapter 19, “SDMA Channels and IDMA Emulation,” describes the two
physical serial DMA (SDMA) channels on the MPC850 with which the CP implements fourteenvirtual SDMA channels.
— Chapter 20, “Serial Interface,” describes the serial interface (SI) in which the
physical interface to all SCCs and SMCs is implemented.
— Chapter 21, “Serial Communications Controllers,” describes thetwo serial
About This Book
communications controllers (SCC), which can be congured independently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks.
— Chapter 22, “SCC UART Mode,” describes the MPC850 implementation of
universal asynchronous receiver transmitter (UART) protocol, used for sending low-speed data between devices.
— Chapter 23, “SCC HDLC Mode,” describes the MPC850 implementation of
HDLC protocol.
— Chapter 24, “SCC AppleTalk Mode,” describes the MPC850 implementation of
AppleTalk, a set of protocols developed by Apple Computer, Inc. to provide a LAN service between Macintosh computers and printers.
— Chapter 25, “SCC Asynchronous HDLC Mode and IrDA,” describes the
asynchronous HDLC and IrDA use of HDLC framing techniques with UART-type characters.
— Chapter 26, “SCC BISYNC Mode,” describes the MPC850 implementation of
byte-oriented BISYNC protocol developed by IBM for use in networking products.
— Chapter 27, “SCC Ethernet Mode,” describes the MPC850 implementation of
Ethernet protocol.
— Chapter 28, “SCC Transparent Mode,” describes the MPC850 implementation of
transparent mode (also called totally transparent mode), which provides a clear channel on which the SCC can send or receive serial data without bit-level manipulation.
— Chapter 29, “IrDA Mode—SCC2 Only,” describes the implementation of a
serial infrared link using the SCC2’s IrDA encoder/decoder module and an external IrDA transducer module.
— Chapter 30, “Serial Management Controllers (SMCs),” describes two serial
management controllers, full-duplex ports that can be congured independently to support one of three protocols—UART, transparent, or general-circuit interface (GCI).
— Chapter 31, “Serial Peripheral Interface (SPI),” describes the serial peripheral
interface, which allows the MPC850 to exchange data between other MPC850 chips, the MC68360, the MC68302, the M68HC11 and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters.
— Chapter 32, “Universal Serial Bus Controller,” describes the MPC850
implementation of the universal serial bus, an industry-standard extension to the PC architecture that supports data exchange between the MPC850 and a PC host and a wide range of simultaneously accessible peripherals.
— Chapter 33, “I2C Controller,” describes the MPC850 implementation of the
inter-integrated circuit (I
2
other I
C devices, such as microcontrollers, EEPROMs, real-time clock devices,
2
C®) controller, which allows data to be exchanged with
and A/D converters.
MPC850 Family User’s Manual
— Chapter 34, “Parallel I/O Ports,” describes the four general-purpose I/O
ports—A, B, C, and D. Each signal in the I/O ports can be congured as a general-purpose I/O signal or as a signal dedicated to supporting communications devices, such as SMCs and SCCs.
— Chapter 35, “CPM Interrupt Controller,” describes how the CPM interrupt
controller (CPIC) accepts and prioritizes the internal and external interrupt requests from the CPM blocks and passes them to the system interface unit (SIU). The CPIC also provides a vector during the core interrupt acknowledge cycle.
Part VI, “Asynchronous Transfer Mode (ATM),” describes the MPC850SR and MPC850DSL ATM implementation. It consists of the following chapters:
— Chapter 36, “ATM Overview,” gives a high-level description of the MPC850SR
and MPC850 DSL ATM implementation, which includes support for aUTOPIA level 1 interface.
— Chapter 37, “Buffer Descriptors and Connection Tables,” describes the structure
and conguration of the buffer descriptors (BDs) and the transmit and receive connection tables (TCTs and RCTs) used with ATM.
— Chapter 38, “ATM Parameter RAM,” describes how the parameter RAM is used
to congure the SCC for serial ATM and the UTOPIA interface. The CP also uses parameter RAM to store operational and temporary values used during SAR activities.
— Chapter 39, “ATM Controller,” describes the address mapping mechanisms of
the ATM controller to support connection tables for single-PHY interfaces, and the commands provided to control ATM transmit and receive operations on a channel-by-channel basis.
— Chapter 40, “ATM Pace Control,” describes how the ATM pace control unit
(APC) processes trafc parameters of each channel and denes the multiplex timing for all the channels.
— Chapter 41, “ATM Exceptions,” describes how the circular ATM interrupt queue
operates with an event register (SCCE or IDSR1) to provide an interrupt model for ATM operations.
— Chapter 42, “Interface Conguration,” describes the programming of registers
and parameters for ATM operations through both the UTOPIA and serial interfaces.
— Chapter 43, “UTOPIA Interface,” describes the SAR MPHY ATM operation,
including the UTOPIA modes and the signals provided for UTOPIA support.
About This Book
Part VII, “System Debugging and Testing Support,” describes how to use the MPC850 facilities for debugging and system testing.
— Chapter 44, “System Development and Debugging,” describes support provided
for program ow tracking, internal watchpoint and breakpoint generation, and emulation systems control.
— Chapter 45, “IEEE 1149.1 Test Access Port,” describes the dedicated
user-accessible test access port (TAP), which is fully compatible with the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture.
Appendix A, “Byte Ordering,” discusses the MPC850 implementation of little- and big-endian byte mapping.
Appendix B, “Serial Communications Performance,”provides guidelines for maximizing performance of MPC850-based systems.
Appendix C, “Register Quick Reference Guide,” contains a quick reference guide to the MPC850- registers.
Appendix D, “Instruction Set Listings,” contains tables of the PowerPC instructions supported by the MPC850.
Appendix E, “MPC850,” describes characteristics specic to the actual MPC850.
Appendix F, “MPC850DSL,” describes characteristics specic to the MPC850DSL.
This manual also includes a glossary and an index.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture.
MPC8xx Documentation
Supporting documentation for the MPC850 can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical specications, reference materials, and detailed applications notes.
PowerPC Documentation
The PowerPC documentation is organized in the following types of documents:
User’s manuals—These books provide details about individual PowerPC implementations and are intended to be used in conjunction with The Programming Environments Manual. These include the following:
PowerPC 603e™ RISC Microprocessor User’s Manual with Supplement for
PowerPC 603™ Microprocessor (Motorola order #: MPC603EUM/AD)
PowerPC 604™ RISC Microprocessor User’s Manual
(Motorola order #: MPC604UM/AD)
MPC850 Family User’s Manual
Programming environments manuals—These books provide information about resources dened by the PowerPC architecture that are common to PowerPC processors. There are two versions, one that describes the functionality of the combined 32- and 64-bit architecture models and one that describes only the 32-bit model.
PowerPC Microprocessor Family: The Programming Environments, Rev 1
(Motorola order #: MPCFPE/AD)
PowerPC Microprocessor Family: The Programming Environments for 32-Bit
Microprocessors, Rev. 1 (Motorola order #: MPCFPE32B/AD)
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
(Motorola order #: MPCBUSIF/AD) provides a detailed functional description of the 60x bus interface, as implemented on the PowerPC 601™, 603, and 604 family of PowerPC microprocessors. This document is intended to help system and chip set developers by providing a centralized reference source to identify the bus interface presented by the 60x family of PowerPC microprocessors.
PowerPC Microprocessor Family: The Programmer’s Reference Guide (Motorola order #: MPCPRG/D) is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set.
PowerPC Microprocessor Family: The Programmer’s Pocket Reference Guide (Motorola order #: MPCPRGREF/D). This feedlot card provides an overview of the PowerPC registers, instructions, and exceptions for 32-bit implementations.
Application notes—These short documents contain useful information about specic design issues useful to programmers and engineers working with PowerPC processors.
For a current list of PowerPC documentation, refer to the world-wide web at http://www.mot.com/SPS/PowerPC/.
Conventions
This document uses the following notational conventions:
Bold
mnemonics Instruction mnemonics are shown in lowercase bold.
italics Italics indicate variable command parameters, for example, bcctrx.
0x0 Prex to denote hexadecimal number
0b0 Prex to denote binary number
rA, rB Instruction syntax used to identify a source GPR
Bold entries in gures and tables showing registers and parameter RAM should be initialized by the user.
Book titles in text are set in italics.
About This Book
rD Instruction syntax used to identify a destination GPR
REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are
shown in uppercase text. Specic bits, elds, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.
x In certain contexts, such as in a signal encoding or a bit eld,
indicates a don’t care.
n Used to express an undened numerical value
¬ NOT logical operator
& AND logical operator
| OR logical operator
Acronyms and Abbreviations
Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious.
Table i. Acronyms and Abbreviated Terms
Term Meaning
A/D Analog-to-digital
ALU Arithmetic logic unit
ATM Asynchronous transfer mode
BD Buffer descriptor
BIST Built-in self test
BPU Branch processing unit
BRI Basic rate interface.
BUID Bus unit ID
CAM Content-addressable memory
CEPT Conference des administrations Europeanes des Postes et Telecommunications (European
CP Communications processor
CPM Communications processor module
CR Condition register
CRC Cyclic redundancy check
CTR Count register
DABR Data address breakpoint register
Conference of Postal and Telecommunications Administrations).
MPC850 Family User’s Manual
Table i. Acronyms and Abbreviated Terms (Continued)
Term Meaning
DAR Data address register
DEC Decrementer register
DMA Direct memory access
DPLL Digital phase-locked loop
DRAM Dynamic random access memory
DSISR Register used for determining the source of a DSI exception
DTLB Data translation lookaside buffer
EA Effective address
EEST Enhanced Ethernet serial transceiver
EPROM Erasable programmable read-only memory
FPR Floating-point register
FPSCR Floating-point status and control register
FPU Floating-point unit
GCI General circuit interface
GPCM General-purpose chip-select machine
GPR General-purpose register
GUI Graphical user interface
HDLC High-level data link control
2
I
C Inter-integrated circuit
IDL Inter-chip digital link
IEEE Institute of Electrical and Electronics Engineers
IrDA Infrared Data Association
ISDN Integrated services digital network
ITLB Instruction translation lookaside buffer
IU Integer unit
JTAG Joint test action group
LIFO Last-in-first-out
LR Link register
LRU Least recently used
LSB Least-significant byte
lsb Least-significant bit
LSU Load/store unit
About This Book
Table i. Acronyms and Abbreviated Terms (Continued)
Term Meaning
MAC Multiply accumulate
MESI Modified/exclusive/shared/invalid—cache coherency protocol
MMU Memory management unit
MSB Most-significant byte
msb Most-significant bit
MSR Machine state register
NaN Not a number
NIA Next instruction address
NMSI Nonmultiplexed serial interface
No-op No operation
OEA Operating environment architecture
OSI Open systems interconnection
PCI Peripheral component interconnect
PCMCIA Personal Computer Memory Card International Association
PIR Processor identification register
PRI Primary rate interface
PVR Processor version register
RISC Reduced instruction set computing
RTOS Real-time operating system
RWITM Read with intent to modify
Rx Receive
SCC Serial communications controller
SCP Serial control por t
SDLC Synchronous Data Link Control
SDMA Serial DMA
SI Serial interface
SIMM Signed immediate value
SIU System interface unit
SMC Serial management controller
SNA Systems network architecture
SPI Serial peripheral interface
SPR Special-purpose register
MPC850 Family User’s Manual
Table i. Acronyms and Abbreviated Terms (Continued)
Term Meaning
SPRGn Registers available for general purposes
SRAM Static random access memory
SRR0 Machine status save/restore register 0
SRR1 Machine status save/restore register 1
TAP Test access port
TB Time base register
TDM Time-division multiplexed
TLB Translation lookaside buffer
TSA Time-slot assigner
Tx Transmit
UART Universal asynchronous receiver/transmitter
UIMM Unsigned immediate value
UISA User instruction set architecture
UPM User-programmable machine
USART Universal synchronous/asynchronous receiver/transmitter
USB Universal serial bus
VA Virtual address
VEA Virtual environment architecture
XER Register used primarily for indicating conditions such as carries and overflows for integer operations
PowerPC Architecture Terminology Conventions
Table ii lists certain terms used in this manual that differ from the architecture terminology conventions.
Table ii. Terminology Conventions
The Architecture Specication This Manual
Data storage interrupt (DSI) DSI exception
Extended mnemonics Simplified mnemonics
Instruction storage interrupt (ISI) ISI exception
Interrupt Exception
Privileged mode (or privileged state) Supervisor-level privilege
Problem mode (or problem state) User-level privilege
About This Book
Table ii. Terminology Conventions (Continued)
The Architecture Specication This Manual
Real address Physical address
Relocation Translation
Storage (locations) Memory
Storage (the act of) Access
Table iii describes instruction eld notation conventions used in this manual.
Table iii. Instruction Field Conventions
The Architecture Specication Equivalent to:
BA, BB, BT crbA, crbB, crbD (respectively)
BF, BFA crfD, crfS (respectively)
Dd
DS ds
FLM FM
FXM CRM
RA, RB, RT, RS rA, rB, rD, rS (respectively)
SI SIMM
U IMM
UI UIMM
/, //, /// 0...0 (shaded)
MPC850 Family User’s Manual
Part I
Overview
Intended Audience
Part I is intended for anyone who needs a high-level understanding of the MPC850 Family of PowerQuicc devices.
Contents
Part I provides an overview of the features and functions of the MPC850. It includes the following chapters:
Chapter 1, “Overview, ” provides a high-level description of MPC850 Family functions and features. It roughly follows the structure of this book, summarizing the relevant features and providing references for the reader who needs additional information.
Chapter 2, “Memory Map,” presents a table showing where MPC850 registers are mapped in memory. It includes cross references that indicate where each register is described in detail.
Conventions
Part I uses the following notational conventions:
mnemonics Instruction mnemonics are shown in lowercase bold.
italics Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
0x0 Prex to denote hexadecimal number
0b0 Prex to denote binary number
rA, rB Instruction syntax used to identify a source GPR
rD Instruction syntax used to identify a destination GPR
Part I. Overview
REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are
shown in uppercase text. Specic bits, elds, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.
x In certain contexts, such as in a signal encoding or a bit eld,
indicates a don’t care.
n Indicates an undened numerical value
Acronyms and Abbreviations
Table i contains acronyms and abbreviations that are used in this document.
Table i. Acronyms and Abbreviated Terms
Term Meaning
BD Buffer descriptor
BPU Branch processing unit
CP Communications processor
CPM Communications processor module
DMA Direct memory access
DPLL Digital phase-locked loop
DRAM Dynamic random access memory
DTLB Data translation lookaside buffer
EA Effective address
GPCM General-purpose chip-select machine
GPR General-purpose register
HDLC High-level data link control
2
I
C Inter-integrated circuit
IEEE Institute of Electrical and Electronics Engineers
IrDA Infrared Data Association
ISDN Integrated services digital network
ITLB Instruction translation lookaside buffer
IU Integer unit
JTAG Joint Test Action Group
LRU Least recently used (cache replacement algorithm)
LSU Load/store unit
MMU Memory management unit
MPC850 Family User’s Manual
Table i. Acronyms and Abbreviated Terms (Continued)
Term Meaning
MSR Machine state register
NMSI Nonmultiplexed serial interface
OEA Operating environment architecture
OSI Open systems interconnection
PCI Peripheral component interconnect
PCMCIA Personal Computer Memory Card International Association
RISC Reduced instruction set computing
RTOS Real-time operating system
Rx Receive
SCC Serial communications controller
SDLC Synchronous data link control
SDMA Serial DMA
SI Serial interface
SIU System interface unit
SMC Serial management controller
SPI Serial peripheral interface
SPR Special-purpose register
SRAM Static random access memory
TB Time base register
TDM Time-division multiplexed
TLB Translation lookaside buffer
TSA Time-slot assigner
Tx Transmit
UART Universal asynchronous receiver/transmitter
UISA User instruction set architecture
UPM User-programmable machine
VEA Virtual environment architecture
Part I. Overview
MPC850 Family User’s Manual
Chapter 1 Overview
This chapter provides an overview of the MPC850 family of integrated communications microprocessors, describing major functions and features. It includes a block diagram and a comparison between the MPC850 and the MPC860.
NOTE:
Unless otherwise specically stated, references to the MCP850 refer to the MPC850DE, which is the superset of the basic MPC850 device. The MPC850SR is the superset of the MPC850 family.
The MPC850 is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products. The MPC850, which includes support for Ethernet, is specically designed for cost-sensitive, remote-access, and telecommunications applications. It is provides functions similar to the MPC860, with system enhancements such as universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM. The MPC850SR and MPC850DSL also provide support for ATM and a UTOPIA interface.
In addition to a high-performance embedded PowerPC core, the MPC850 integrates system functions such as a versatile memory controller and a communications processor module (CPM) that incorporates a specialized, independent RISC communications processor (referred to as the CP). This separate processor off-loads peripheral tasks from the embedded PowerPC core.
The CPM of the MPC850 supports up to seven serial channels, as follows:
One or two serial communications controllers (SCCs). The SCCs support Ethernet, ATM (MPC850SR and MPC850DSL), HDLC and a number of other protocols, along with a transparent mode of operation. Up to 64 logical HDLC channels can be supported on a single SCC.
One USB channel
Two serial management controllers (SMCs)
One I
One serial peripheral interface (SPI).
2
C port
Chapter 1. Overview
Features
Table 1-1 shows the functionality differences among the members of the MPC850 family:
Table 1-1. MPC850 Functionality Matrix
Part SCC Support ATM Support Reference
MPC850 One SCC—SCC2 Appendix F
MPC850DE Two SCCs; both support Ethernet This manual
MPC850SR Two SCCs; both support Ethernet, multi-channel HDLC, and serial
MPC850DSL SCC2 supports Ethernet only, SCC3 supports UART only. Time slot
ATM.
assigner, SMC2 and I
2
C are not supported.
UTOPIA interface
UTOPIA interface
Part VI ATM
Part VI ATM & Appendix G

1.1 Features

Figure 1-1 is the block diagram of the MPC850SR, the superset of the MPC850 family, showing the major components and the relationships among those components:
MPC850 Family User’s Manual
Features
Embedded
PowerPC
Core
Baud Rate
Generators
Parallel I/O
Ports
UTOPIA
TDMa
SCC2
2-Kbyte I Cache
Instruction
Bus
Load/Store
Bus
Timers
Processor (CP) and Program ROM
Timer
Instruction
MMU
1-Kbyte
D Cache
Data
MMU
Four
Interrupt
Controller
32-Bit RISC Communications
SCC3
Time Slot Assigner
SMC1 SMC2
Dual-Port
RAM
Unified Bus
Peripheral Bus
USB
14 Virtual
Serial DMA
Channels
and
2 Virtual
IDMA
Channels
SPI
System Interface Unit
Memory Controller
Bus Interface Unit
System Functions
Real-Time Clock
PCMCIA Interface
Communications
Processor
Module
2
C
I
Non-Multiplexed Serial Interface
Figure 1-1. MPC850SR Family Microprocessor Block Diagram
The following list summarizes the main features of the MPC850 Family:
Embedded PowerPC core
— Single-issue, 32-bit version of the embedded PowerPC core (fully compatible
with PowerPC user instruction set architecture denition) with 32 x 32-bit integer registers
— Performs branch folding and branch prediction with conditional prefetch, but
without conditional execution
— 2-Kbyte data cache and 1-Kbyte instruction cache (Harvard architecture)
– Caches are two-way, set-associative
– Physically addressed
Chapter 1. Overview
Features
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
— Memory management units (MMUs) with 8-entry translation lookaside buffers
(TLBs) and fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512
Kbytes, and 8 Mbytes; 16 virtual address spaces and eight protection groups
Advanced on-chip emulation debug mode
Data bus dynamic bus sizing for 8-, 16-, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and PowerPC
little-endian memory systems
— Twenty-six external address lines
Completely static design (0–80 MHz operation)
System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— PowerPC decrementer
— Real-time clock and PowerPC time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs),
synchronous DRAM (SDRAM), static random-access memory (SRAM), electrically programmable read-only memory (EPROM), ash EPROM, etc.
— Memory controller programmable to support most size and speed memory
interfaces
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes, 32 Kbyte to 256 Mbyte
— Selectable write protection
— On-chip bus arbitration supports external bus master
— Special features for burst mode support
MPC850 Family User’s Manual
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
Interrupts
— Eight external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— Fifteen internal interrupt sources
— Programmable priority among SCCs and USBs
— Programmable highest-priority request
Single socket PCMCIA-ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PCMCIA socket
— Supports eight memory or I/O windows
Communications processor module (CPM)
— 32-bit, Harvard architecture, scalar RISC communications processor (CP)
— Protocol-specic command sets (for example,
GRACEFUL STOP TRANSMIT stops
transmission after the current frame is nished or immediately if no frame is being sent and
CLOSE RXBD closes the receive buffer descriptor)
— Up to 384 buffer descriptors (BDs)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— Fourteen serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Four independent baud-rate generators (BRGs)
— Can be connected to any SCC, SMC, or USB
— Allow changes during operation
— Autobaud support option
Up to two SCCs (serial communications controllers)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC™
(all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk™
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
Features
Chapter 1. Overview
Features
— Serial infrared (IrDA)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
QUICC multichannel controller (QMC) microcode features
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
— Supports either transparent or HDLC protocols for each channel
— Independent TxBDs/Rx and event/interrupt reporting for each channel
Up to two serial management controllers (SMCs)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division-multiplexed (TDM) channel
One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multimaster operation on the same bus
2C®
One I
(interprocessor-integrated circuit) port
— Supports master and slave modes
— Supports multimaster environment
Time slot assigner
— Allows SCCs and SMCs to run in multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate,
user-dened
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame syncs, clocking
— Allows dynamic changes
— Can be internally connected to four serial channels (two SCCs and two SMCs)
Low-power support
— Full high: all units fully powered at high clock frequency
— Full low: all units fully powered at low clock frequency
— Doze: core functional units disabled except time base, decrementer, PLL,
memory controller, real-time clock, and CPM in low-power standby
— Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL
is active for fast wake-up
— Deep sleep: all units disabled including PLL, except the real-time clock and
periodic interrupt timer
MPC850 Family User’s Manual
Overview of Major Components
— Low-power stop: to provide lower power dissipation
— Separate power supply input to operate internal logic at 2.2 V when operating at
or below 25 MHz
— Can be dynamically shifted between high frequency (3.3 V internal) and low
frequency (2.2 V internal) operation
Debug interface
— Eight comparators: four operate on instruction address, two operate on data
address, and two operate on data
— The MPC850 can compare using the =, , <, and > conditions to generate
watchpoints
— Each watchpoint can generate a breakpoint internally
3.3-V operation (No support for 5V I/O).

1.2 Overview of Major Components

As shown in Figure 1-1, the MPC850 adopts a dual-processor design, providing a high-performance embedded PowerPC core for application programming use and a communications processor module that contains a special-purpose 32-bit scalar RISC communications processor (CP).
Components of the MPC850 family are described in the following sections following the organizational structure of this manual.
Part II, “PowerPC Microprocessor Module,” describes the PowerPC microprocessor core embedded in the MPC850. These chapters provide details concerning the processor core as an implementation of the PowerPC architecture. This is summarized in Section 1.2.1.
Part III, “Conguration and Reset,” describes start-up behavior of the MPC850. This is summarized in Section 1.2.2.
Part IV, “The Hardware Interface,” describes external signals, clocking, memory control, and power management of the MPC850. This is summarized in Section
1.2.3.
Part V, “Communications Processor Module,” describes the conguration, clocking, and operation of the various communications protocols supported by the MPC850. This is summarized in Section 1.2.4.
Part VI, “Asynchronous Transfer Mode (ATM), describes the functionality and implementation of ATM and the Utopia interface on the MPC850SR and MPC850DSL devices.
Part VII, “System Debugging and Testing Support,” describes how to use the MPC850 facilities for debugging and system testing. This is summarized in Section 1.2.5.
Chapter 1. Overview
Overview of Major Components
1.2.1 PowerPC Microprocessor Module
The PowerPC core has a fully-static design. It executes all integer and load/store operations directly on the hardware. The core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. Its interface to the internal and external buses is 32 bits. The core uses a two-instruction load/store queue, four-instruction prefetch queue, and a six-instruction history buffer.
The core performs branch folding and branch prediction with conditional prefetch, but without conditional execution. The core can operate on 32-bit external operands with one bus cycle. The PowerPC integer block supports thirty-two 32-bit general-purpose registers (GPRs), which are used as source and destination operands for instruction execution.
The integer unit typically can execute one integer instruction on each clock cycle. Each element in the integer block is clocked only when valid data is present in the data queue and ready for operation, which reduces power consumption to the amount needed for an operation.
The PowerPC processor is integrated with the MMUs and 2-Kbyte instruction and 1-Kbyte data caches. The MMUs provide an 8-entry, fully-associative instruction and data TLB, with multiple page sizes of 4 Kbytes (1-Kbyte protection), 16 Kbytes, 512 Kbytes, and 8 Mbytes. It supports 16 virtual address spaces with eight protection groups. Three special-purpose registers are provided to support software table searching and updating page translations.
The 2-Kbyte instruction cache is two-way, set associative with physical addressing. It allows single-cycle access on hits with no added latency for miss. It has four words per line and supports burst linell using an LRU replacement algorithm. The instruction cache can be locked on a line-by-line basis for application-critical routines.
The 1-Kbyte data cache is two-way, set associative with physical addressing. It allows single-cycle access on hit with one added clock latency for miss. It has four words per line and supports burst linell using an LRU replacement algorithm. The data cache can also be locked on a line-by-line basis for application-critical routines. It can be programmed to support copy-back or write-through via the MMU. Cache-inhibit mode can be programmed on a per-page basis.
1.2.2 Conguration and Reset
The MPC850 conguration is handled through the system interface unit (SIU), which is described in Section 1.2.2.1, “System Interface Unit (SIU).” The MPC850 provides many different kinds of reset, as described in Section 1.2.2.2, “Resets.”
1.2.2.1 System Interface Unit (SIU)
The SIU controls system start-up, initialization, operation, protection, and the external system bus. The system conguration and protection function controls the overall system
MPC850 Family User’s Manual
Overview of Major Components
and provides various monitors and timers, including the bus monitor, software watchdog timer, periodic interrupt timer (PIT), PowerPC decrementer, timebase, and real-time clock. The clock synthesizer generates the clock signals for other modules and external devices that the SIU interfaces with. The SIU supports various low-power modes that supply different ranges of power consumption, functionality, and wake-up time. The clock scheme supports low-power modes for applications that use baud rate generators and/or serial ports in standby mode. The main system clock can be changed dynamically; the baud rate generators and serial ports work with a xed frequency.
Although the PowerPC core is a 32-bit device internally, it can be congured to operate with an 8-, 16-, or 32-bit data bus. Regardless of system bus size, dynamic bus sizing is supported, which allows 8-, 16-, and 32-bit peripherals and memory to coexist on the 32-bit system bus. The SIU supports traditional 68000 big-endian memory systems, traditional x86 little-endian memory systems, and PowerPC little-endian memory systems.
The memory controller supports up to eight memory banks with glueless interfaces to DRAM, SRAM, PSRAM, EPROM, ash EPROM, SDRAM, EDO, and other peripherals with two-clock initial access to external SRAM and bursting support. It provides variable block sizes from 32 Kbytes to 256 Mbytes. The memory controller provides 0 to 15 wait states for each bank of memory and can use address type matching to qualify each memory bank access. It provides four byte-enable signals for varying width devices, one output enable signal, and one boot chip-select available at reset.
The DRAM interface supports 8-, 16-, and 32-bit ports. It uses a programmable state machine to support almost any memory interface. Memory banks can be dened in depths of 256 or 512 Kbytes or 1, 2, 4, 8, 16, 32, or 64 Mbytes for all port sizes. In addition, the memory depth can be dened as 64 Kbytes and 128 Kbytes for 8-bit memory or 128 Mbytes and 256 Mbytes for 32-bit memory. The DRAM controller supports page mode access for successive transfers within bursts. The MPC850 supports a glueless interface to one bank of DRAM, while external buffers are required for additional memory banks. The refresh unit provides CAS
before RAS, a programmable refresh timer, active refresh during external reset, the ability to disable refresh, and stacking for a maximum of seven refresh cycles.
The PCMCIA-ATA interface is a master controller that is compliant with release 2.1. The interface supports one independent PCMCIA socket with external transceivers or buffers required. It provides eight memory or I/O windows that can be allocated to the socket. If the PCMCIA port is not being used as a card interface, it can be used as a general-purpose input with interrupt capability.
1.2.2.2 Resets
The reset block has reset control logic that determines the cause of reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O signals are initialized only on hard reset. Soft reset initializes the internal logic while maintaining the system conguration.
Chapter 1. Overview
Overview of Major Components
The MPC850 has several sources of input to the reset logic:
Power-on reset
External hard reset
Internal hard reset
— Loss of lock — Software watchdog reset — Checkstop reset — Debug port hard reset
JTAG reset
External soft reset
Internal soft reset (debug port soft reset)
All of these reset sources are fed into the reset controller and, depending on the source of the reset, different actions are taken. The reset status register reects the last source to cause a reset.
1.2.3 MPC850 Hardware Interface
The MPC850 bus is a synchronous, burstable bus that can support multiple masters. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The MPC850 architecture supports byte, half-word, and word operands allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles controlled by the size outputs (TSIZ0, TSIZ1). Access to 16- and 8-bit ports is done for slaves controlled by the memory controller.
The MPC850 bus interface features are listed as follows:
26-bit address bus with transfer size indication
32-bit data bus
Dynamic bus sizing to 32-, 16-, or 8-bit ports accessed through the memory controller
TTL-compatible interface
Bus arbitration supported optionally by internal or external logic
Bus arbitration logic on-chip supports an external master with programmable priority
Compatible with PowerPC architecture
Easy to interface to slave devices
Bus is synchronous (all signals are referenced to rising edge of bus clock)
Contains support for data parity
The PCMCIA host adapter module provides all control logic for a PCMCIA socket interface, and requires only additional external analog power switching logic and buffering.
MPC850 Family User’s Manual
Overview of Major Components
1.2.3.1 Signals
Figure 1-2 shows MPC850 signals grouped by function. Note that many of these signals are multiplexed and this gure does not indicate how these signals are multiplexed. For signals available on the MPC850SR and MPC850DSL, refer to Part VI ATM.
NOTE:
A bar over a signal name indicates that the signal is active low—for example, BB referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as TSIZ[0–1] (transfer size signals) are referred to as asserted when they are high and negated when they are low.
(bus busy). Active-low signals are
Chapter 1. Overview
Overview of Major Components
Communications
Processor
Module
USB
SMC1/2
SCC2/3
IDMA
Serial
Interface
SPI
2
C
PCMCIA
Clocks
USBRXD 1
USBOE 11↔ BG USBRXP 11↔ BB USBRXN 11↔ TS Address Start
USBTXP 126↔ A[6–31]
SMRXD1/2 21← KR
SMTXD1/2 22↔ TSIZ[0–1]
SMSYN1/2 21↔ B
RXD2/3 21→ BDIP
TXD2/3 21↔ BI RTS2/3 232↔ D[0–31]
CD2/3 21↔ RD/WR
DREQ[1–2] 21↔ T
SDACK[1–2] 21→ TEA
L1TXDA 14↔ AT[0–3] External
L1TCLKA 11→ STS
L1TSYNCA 18→ CS[0–7] Chip Selects
L1RSYNCA 14→ WE[0–3}
L1RCLKA 11← AS
L1ST[1–8] 86→ GPL_A[0–5]
L1RQA 16→ GPL_B[0–5] SPIMISO 14→ BS_AB[0–3] SPIMOSI 11← UPWAITA
SPISEL 11← UPWAITB SPICLK 112↔ PA[4–15] I2CSDA 114↔ PB[16–19, 22–31] I2CSCL 117↔ PC[4–15]
IP_B[0–7] 813↔ PD[3–15]
PCWE 18← IRQ[0–7]
PCOE 11← HRESET
REG 11← SRESET
IOIS16_B 11← PORESET
IORD 11← RSTCONF
IOWR 11← TMS CE1_B 11← TDI/DSDI CE2_B 11← TCK/DSCK
OP[2–3] 21← TRST WAIT_B 11→ TDO
ALE_B 11← DSCK
XTAL 11← DSDI
EXTAL 11→ DSDO
XFC 11→ FRZ
CLKOUT 11→ PTR
TEXP 13→ VF[0–2]
TOUT[1–2] 23→ IWP[0–2]
CLK[1–4] 43→ LWP[0–2]
BRGO[1–3] 31← VDDSYN
TIN[1–4] 41← VBSSSYN
TGATE1 11← VSSSYN1
MODCK[1–2] 21← KAPWR
SPKROUT 11← VDDH
1 BR
URST
A Data Transfer
M
P
C
8 5 0
1 VDDL 1 VSS
Figure 1-2. MPC850 Functional Signal Diagram
Address Bus
Arbitration
Address BusUSBTXN 11↔ RSV
Transfer
Attribute
Data TransferCTS2/3 24↔ DP[0–3]
Termination
Interface
GPCML1RXDA 11→ OE
UPMA/UPMB
Parallel I/OI
Interrupts/
Resets
JTAG
Development
Por t
Program TraceEXTCLK 12→ VFLS[0–1]
Watchpoints
Powe r
External
Bus
Memory
Controller
JTAG,
Debug,
Trace
MPC850 Family User’s Manual
Overview of Major Components
1.2.3.2 Clocking and Power Management
The MPC850 clock system provides many different clocking options for all on-chip and external devices. For its clock sources, the MPC850 contains phase-locked loop and crystal oscillator support circuitry. The phase-locked loop circuitry can be used to provide a high-frequency system clock from a low-frequency external source. Also, to enable flexible power control, the MPC850 provides frequency dividers and a variety of low-power mode options.
The MPC850 allows a system to optimize power utilization by providing performance on-demand. This is implemented through a variety of programmable power-saving modes with automatic wake-up features.
The main features of the MPC850 clocks and power control system are as follows:
Contains system PLL (SPLL)
Supports crystal oscillator circuits
Clock dividers are provided for low-power modes and internal clocks
Contains ve major power-saving modes
— Normal (high and low)
— Doze (high and low)
— Sleep
— Deep sleep
— Power down
The MPC850 supports a wide range of power management features including full-high, full-low, doze, sleep, deep-sleep, and low-power stop. These modes progressively reduce power consumption, as follows:
In full-high mode, the MPC850 is fully powered with all internal units operating at the full processor speed.
Full-low mode is the same as full-high, but operates at a lower frequency. A gear mode determined by a clock divider allows the operating system to reduce the operational frequency of the processor.
Doze mode disables core functional units except the time base, decrementer, PLL, memory controller, real-time clock, and places the CPM in low-power standby mode.
Sleep mode is the next lower power mode. It disables everything except the real-time clock and periodic interrupt timer, leaving the PLL active for quick wake-up.
Deep-sleep mode disables the PLL for lower power, but slower wake-up.
Low-power stop disables all logic in the processor except the minimum logic required to restart the device, and provides the lowest power consumption but requires the longest wake-up time.
Chapter 1. Overview
Overview of Major Components
1.2.3.3 Memory Controller
The memory controller is responsible for controlling a maximum of eight memory banks shared between a general-purpose chip-select machine (GPCM) and a pair of sophisticated user-programmable machines (UPMs). It supports a glueless interface to SRAM, EPROM, ash EPROM, regular DRAM devices, self-refresh DRAMs, extended data output DRAM devices, synchronous DRAMs, and other peripherals. This exible memory controller allows the implementation of memory systems with very specic timing requirements.
The GPCM provides interfacing for simpler, lower-performance memory resources and memory-mapped devices. The GPCM has inherently lower performance because it does not support bursting. For this reason, GPCM-controlled banks are used primarily for boot-loading and access to nonburstable memory-mapped peripherals.
The UPM provides both more features and, because it supports bursting, higher performance. Therefore it is typically used to interface with higher-performance run-time memory such as DRAM and bursting SRAM.
The UPM supports address multiplexing of the external bus, periodic timers, and generation of programmable control signals for row address and column address strobes to allow for a glueless interface to DRAM devices. The periodic timers allow refresh cycles to be initiated while the address multiplexing provides row and column addresses.
Different timing patterns can be generated for the control signals that govern a memory device. These patterns dene how the external control signals behave in read-access, write-access, burst read-access, or burst write-access requests. Periodic timers are also available to periodically generate user-dened refresh cycles.
The following is a list of the memory controller’s main features:
Eight memory banks
— 32-bit address decode with mask
— Variable block sizes (32 Kbytes to 4 Gbytes)
— Byte parity generation/checking
— Write-protection capability
— Address types protection for memory bank accesses by internal masters
— Control signal generation machine selection on a per-bank basis
— Support for external master access to memory banks
— Synchronous and asynchronous external masters support
General-purpose chip-select machine (GPCM)
— Compatible with SRAM, EPROM, FEPROM, and peripherals
— Global (boot) chip-select available at system reset
— Boot chip-select support for 8-, 16-, and 32-bit devices
— Minimum two clock accesses to external device
MPC850 Family User’s Manual
Overview of Major Components
— Four byte write enable signals (WE)
— Output enable signal (OE
)
Two user-programmable machines (UPMs)
— Programmable-array-based machine controls external signal timing with a
granularity of one quarter of an external bus clock period
— User-specied control-signal patterns run when an internal or external
synchronous master requests a single-beat or burst read or write access.
— User-specied control-signal patterns run when an external asynchronous master
requests a single-beat read or write access.
— UPM periodic timer runs a user-specied control signal pattern to support
refresh
— User-specied control-signal patterns can be initiated by software
— Each UPM can be dened to support DRAM devices with depths of 64, 128, 256,
and 512 Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes
— Each UPM provides programmable timing for the following signals:
– Four byte-select lines
– Six external general-purpose lines
— Supports 8-, 16-, and 32-bit DRAM port sizes
— Glueless interface to one bank of DRAM (only external buffers are required for
additional SIMM banks)
— Page mode support for successive transfers within a burst for all on-chip and
external synchronous devices
— Internal address multiplexing for all on-chip bus masters supporting 64-, 128-,
256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page banks
— Glueless interface to EDO, self refresh, and synchronous DRAM devices
1.2.4 Communications Processor Module (CPM)
The CPM provides a exible and integrated approach to communications-intensive environments. To reduce system frequency and save power, the CPM has its own independent RISC communications processor (CP) that is optimized for serial communications. The CP services several integrated communications channels, performing low-level protocol processing and controlling DMA.
The CPM supports multiple communications channels and protocols, and it has flexible rmware programmability. The CPM frees the core of many computational tasks in the following ways:
By reducing the interrupt rate. The core is interrupted only upon frame reception or transmission, instead of on a per-character basis.
Chapter 1. Overview
Overview of Major Components
By implementing some of the OSI layer-2 processing, which provides more core bandwidth for higher layer processing.
By supporting multibuffer memory data structures that are convenient for software handling.
The CPMs are similar in the MPC850 and MPC860; both are derived from the CPM in the MC68360 QUICC; see the MC68360 Quad Integrated Communications Controller (QUICC) User’s Manual.
The following lists the CPM’s main features:
Communications processor (CP)
— Dual-port RAM — Internal ROM — Two physical serial DMA (SDMA) controllers implement fourteen SDMA
channels, which provide two channels each for the SCCs, SMCs, USB channel, SPI, and I
2
C.
— Two independent DMA (IDMA) channels for memory-to-memory transfers or
interfacing external peripherals.
— RISC timer tables
Two full-duplex serial communications controllers (SCC2 and SCC3) that support the following:
— UART protocol (asynchronous or synchronous) — HDLC protocol — AppleTalk protocol — Asynchronous HDLC protocol — BISYNC protocol — Transparent protocol — Infrared protocol (IrDA) — IEEE 802.3/Ethernet protocol — Serial ATM
Two full-duplex serial management controllers (SMCs)
— UART protocol — Transparent protocol — GCI protocol for monitor and C/I channels (for ISDN)
A universal serial bus (USB) controller
— Supports slave mode at a maximum of 12 Mbps with four USB endpoints
Serial peripheral interface (SPI) support for master or slave modes
Inter-integrated circuit (I
2
C) bus controller
A serial interface (SI) with a time-slot assigner (TSA) that supports multiplexing of data from SCCs and SMCs onto one time-division multiplexed (TDMa) interface
MPC850 Family User’s Manual
Differences between the MPC850 Family and MPC860
Four independent baud rate generators (BRGs)
Four general-purpose 16-bit timers or two 32-bit timers
CPM interrupt controller (CPIC)
General-purpose I/O ports
1.2.5 System Debugging and Testing Support
The MPC850 contains an advanced debug interface that provides superior debug capabilities without degrading operation speed. It supports six watchpoint pins that can be combined with eight internal comparators, four of which operate on the effective address on the address bus. The other four comparators are split—two comparators operate on the effective address on the data bus and two comparators operate on the data on the data bus. The MPC850 can compare using the =, , <, and > conditions to generate watchpoints. Each watchpoint can then generate a breakpoint that can be programmed to trigger on a programmable number of events.
The MPC850 provides a dedicated user-accessible test access port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The MPC850 implementation supports circuit-board test strategies based on this standard.
The TAP consists of ve dedicated signals, a 16-state TAP controller, and two test data registers. A boundary scan register links all device signals into a single shift register. The test logic, implemented using static logic design, operates independently of the device system logic. The MPC850 TAP implementation provides the capability to:
Perform boundary scan operations to check circuit-board electrical continuity.
Bypass the MPC850 for a given circuit-board test by effectively reducing the boundary scan register to a single cell.
Sample the MPC850 system signals during operation and transparently shift out the result in the boundary scan register.
Disable the output drive to signals during circuit-board testing.

1.3 Differences between the MPC850 Family and MPC860

Ways in which the MPC850 differs from the MPC860 are summarized as follows.
One USB (12-Mbyte slave) port added
Dual-port RAM increased to 8 Kbytes
One or two SCCs instead of four
Chapter 1. Overview
Differences between the MPC850 Family and MPC860
Smaller caches (2-Kbyte instruction cache and 1-Kbyte data cache)
Smaller MMUs (eight entries instead of 32)
Only one PCMCIA slot is supported
Only one TDM port is supported (TDMa)
PIP (Centronics™ port) is not supported
DSP library functions are removed
Serial ATM and Utopia interface added (MPC850SR and MPC850DSL)
MPC850 Family User’s Manual
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