Freescale Semiconductor MPC5607B Reference Manual Addendum

Freescale Semiconductor

MPC5607BRMAD

Reference Manual Addendum

MPC5607B Microcontroller
Reference Manual Addendum

by: Microcontroller Solutions Group

Rev. 1, 05/2012

This addendum document describes corrections to the
MPC5607B Microcontroller Reference Manual, order
number MPC5607BRM. For convenience, the addenda
items are grouped by revision. Please check our website
at http://www.freescale.com/powerarchitecture for the
latest updates.

The current version available of the MPC5607B
Microcontroller Reference Manual is Revision 7.1.

Table of Contents

1 Addendum List for Revision 7.1 . . . . . . . . . . . . . . 2

2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 10

© Freescale Semiconductor, Inc., 2012. All rights reserved.

Addendum List for Revision 7.1

1 Addendum List for Revision 7.1

Table 1. MPC5607BRM Rev 7.1 Addenda

Location Description

Chapter 1, Preface, page 22 In Table 1-1, Guide to this reference manual, Line 12 WKUP, change the description to read:

Always-active analog bloc k. Details configuration of 2 internal (API/RTC) and 27 external (pin)
low power mode wakeup sources.

Chapter 1, Preface, page 23 In Table 1 (Guide to this reference manual), Line 17, eDMA Channel Multiplexer (DMA_MUX),

change the description to read:
“Operation and configuration information for the eDMA multiplexer, which ta kes the 59

possible eDMA sources (triggers from the DSPI, eMIOS, I
multiplexes them onto the 16 eDMA channels.” (59 sources, 16 channels)

Chapter 1, Preface, page 27 In Section 1.6.1, The MPC5607B document set, remove bullet item

“e200z4 Power Architecture Core Reference Man ual.”

Chapter 1, Preface, page 27 In Section 1.6.1, The MPC5607B document set, change bullet item “Configuring CPU memory,

branch and cache optimizations” to “Configuring CPU memory and branch optimizations.”

Chapter 1, Preface, page 30 In Section 1.7.3, Software design, remov e the paragraph “The MMU translates physical memory

addresses for use by the CPU and it must be configured before any peripherals or memories
are available f or use by the CPU. See the e200z4 P ow er Architecture Core Reference Manual
for details on how to configure the MMU.”

Chapter 6, Clock Description,

page 132

Chapter 9, Reset Generation

Module (MC_RGM), page
232

Add Note: to Section 6.8.4.1, Crystal clock monitor:

Note: Functional FXOSC monitoring can only be guaranteed when the FXOSC frequency is
greater than (FIRC / 2

Add Note: to Section 6.8.4.2, FMPLL clock monitor:

Note: Functional FMPLL monitoring can only be guaranteed when the FMPLL frequency is
greater than (FIRC / 4) + 0.5 MHz.

Replaced Section 9.4.7, Boot Mode Capturing, with the following:

The MC_RGM samples P A[9:8] whenev er RESET is asserted until five FIRC (16 MHz internal
RC oscillator) clock cycles before its deassertion edge. The result of the sampling is used at
the beginning of reset PHASE3 for boot mode selection and is retained after RESET has been
deasserted for subsequent boots after reset sequences during which RESET is not asserted.

RCDIV

)+0.5MHz.

2

C, ADC and LINFlexD) and

Note: In order to ensure that the boot mode is correctly captured, the application needs to
apply the valid boot mode value the entire time that RESET is asserted.

RESET can be asserted as a consequence of the internal reset generation. This will force
re-sampling of the boot mode pins. (See Table 9-12 for details.)

Chapter 13, Real Time Clock /
Autonomous Periodic
Interrupt (RTC/API), page 270

In Table 13-3 (RTCC field descriptions), update the Note in the RTCC[APIVAL] field description:

Note: API functionality starts only when APIVAL is nonzero. The first API interrupt takes two
more cycles because of synchronization of APIVAL to the RTC cloc k, and APIVAL + 1 cycles
for subsequent occurrences. After that, interrupts are periodic in nature. Because of
synchronization issues, the minimum supported value of APIVAL is 4.

MPC5607B Reference Manual Errata, Rev. 1

Freescale Semiconductor2

Table 1. MPC5607BRM Rev 7.1 Addenda (continued)

Table 16-24. Coherency model for a dynamic channel link request

Step Action

1 Write 1b to the TCD.major.e_link bit.
2 Read back the TCD.major.e_link bit.
3 Test the TCD.major.e_link request status:

• If TCD.major.e_link = 1b, the dynamic link attempt was successful.

• If TCD.major .e_link = 0b , the attempted dynamic link did not succeed (the channel
was already retiring).

Location Description

Addendum List for Revision 7.1

Chapter 16, Enhanced Direct

Memory Access (eDMA),
page 330

Replace Section 16.5.8, Dynamic programming, with the following:

16.5.8 Dynamic programming

16.5.8.1

Dynamic channel linking is the process of setting the TCD.major.e_link bit
during channel execution. This bit is read from the TCD local memory at the
end of channel execution, thus allowing the user to enable the feature during
channel execution.

Because the user is allowed to change the configuration during execution, a
coherency model is needed. Consider the scenario where the user attempts to
execute a dynamic channel link by enabling the TCD.major.e_link bit at the
same time the eDMA engine is retiring the channel. The TCD.major.e_link
would be set in the programmer’s model, but it would be unclear whether the
actual link was made before the channel retired.

The coherency model in Table 16-24 is recommended when executing a
dynamic channel link request.

Dynamic channel linking

For this request, the TCD local memory controller forces the TCD.major .e_link
bit to zero on any writes to a channel’s TCD.word7 after that channel’s
TCD.done bit is set, indicating the major loop is complete.

Freescale Semiconductor 3

NOTE

The user must clear the TCD.done bit before
writing the TCD.major .e_link bit. The TCD.done
bit is cleared automatically by the eDMA engine
after a channel begins execution.

MPC5607B Reference Manual Errata, Rev. 1