1.2.2.3Universal Serial Bus ( USB ) .........................................................................................................................1-7
1.2.2.4Infrared Support ............................................................................................................................................1-7
1.2.4Byte Data Link Controller - Digital BDLC-D ....................................................................................................1-8
1.2.6SDRAM Controller and Interface .......................................................................................................................1-9
1.2.7Multi-Function External LocalPlus Bus .............................................................................................................1-9
1.2.9Systems Debug and Test ...................................................................................................................................1-10
3.3.1MPC5200 Internal Register Space ......................................................................................................................3-3
3.3.2.1SDRAM Bus .................................................................................................................................................3-3
3.3.2.2LocalPlus Bus ...............................................................................................................................................3-4
3.3.3Memory Map Space Register Description ..........................................................................................................3-4
3.3.3.1Memory Address Base Register —MBAR + 0x0000 ..................................................................................3-4
3.3.3.2Boot and Chip Select Addresses ...................................................................................................................3-5
5.2Clock Distribution Module (CDM) ...........................................................................................................................5-1
5.4.3603e G2_LE Core Power Modes ........................................................................................................................5-9
5.4.3.1Dynamic Power Mode ................................................................................................................................5-10
5.4.4.1Entering Deep Sleep ...................................................................................................................................5-11
5.4.4.2Exiting Deep Sleep .....................................................................................................................................5-11
7.2.4.10ICTL Critical Interrupt Status All Register—MBAR + 0x0528 ................................................................7-15
7.2.4.11ICTL Main Interrupt Status All Register—MBAR + 0x052C ...................................................................7-16
7.2.4.12ICTL Peripheral Interrupt Status All Register—MBAR + 0x0530 ............................................................7-17
7.2.4.13ICTL Peripheral Interrupt Status All Register—MBAR + 0x0538 ...........................................................
7.2.4.14ICTL Main Interrupt Emulation All Register—MBAR + 0x0540 .............................................................7-19
7.2.4.15ICTL Peripheral Interrupt Emulation All Register—MBAR + 0x0544 .....................................................7-20
7.2.4.16ICTL IRQ Interrupt Emulation All Register—MBAR + 0x0548 ..............................................................7-21
7.3General Purpose I / O ( GPIO ) ..................................................................................................................................7-21
7.3.1.9Dedicated GPIO Port ..................................................................................................................................7-27
7.3.2GPIO Programmer’s Model ..............................................................................................................................7-27
7.3.2.1GPIO Standard Registers—MBAR+0x0B00 ............................................................................................7-27
7.3.2.1.1GPS Port Configuration Register—MBAR + 0x0B00 ........................................................................7-28
C ...............................................................................................................................................................7-26
.7-18
MPC5200B Users Guide, Rev. 1
Freescale SemiconductorTOC-3
Tab l e Of C o nte n t s
ParagraphPage
NumberNumber
7.3.2.1.16GPS GPIO Simple Interrupt Status Register—MBAR + 0x0B3C ......................................................7-44
8.2Terminology and Notation ........................................................................................................................................8-1
8.4.4.2Precharge All Banks Command .................................................................................................................8-14
MPC5200B Users Guide, Rev. 1
TOC-4Freescale Semiconductor
Table of Contents
ParagraphPage
NumberNumber
8.4.4.3Bank Active Command ..............................................................................................................................8-14
8.6Programming the SDRAM Controller ....................................................................................................................8-17
8.8Address Bus Mapping .............................................................................................................................................8-25
9.4Modes of Operation ...................................................................................................................................................9-4
9.7Programmer’s Model ...............................................................................................................................................9-11
9.7.1Interrupt and Bus Errors ....................................................................................................................................9-11
10.2.1PCI_AD[31:0] - Address/Data Bus ..................................................................................................................10-3
10.2.10PCI_SERR - System Error ................................................................................................................................10-3
10.3.1PCI Controller Type 0 Configuration Space .....................................................................................................10-6
10.3.1.1Device ID/ Vendor ID Registers PCIIDR(R) —MBAR + 0x0D00 ...........................................................10-7
10.4.1PCI Bus Protocol .............................................................................................................................................10-41
10.4.1.1PCI Bus Background ................................................................................................................................10-41
10.4.1.2Basic Transfer Control ..............................................................................................................................10-42
10.4.1.4PCI Bus Commands ..................................................................................................................................10-44
10.4.1.5.1Memory space addressing .............................................................................................
10.4.1.5.2I/O space addressing ..........................................................................................................................10-46
10.4.1.5.3Configuration space addressing and transactions ..............................................................................10-46
10.4.4XL bus Initiator Interface ................................................................................................................................10-48
10.4.5XL bus Target Interface .................................................................................................................................10-54
10.4.5.1Reads from Local Memory .......................................................................................................................10-55
10.4.6.5Restart and Reset ......................................................................................................................................10-58
10.4.8.1PCI Bus Interrupts ....................................................................................................................................10-59
10.6Application Information ........................................................................................................................................10-60
10.6.1XL bus Initiated Transaction Mapping ...........................................................................................................10-60
10.6.3XL bus Arbitration Priority .............................................................................................................................10-64
11.2BestComm Key Features .........................................................................................................................................11-1
11.4.1PIO State Machine ..........................................................................................................................................11-21
11.4.2DMA State Machine .......................................................................................................................................11-22
11.5Signals and Connections .......................................................................................................................................11-23
11.7ATA Bus Background ...........................................................................................................................................11-26
12.2Data Transfer Types ................................................................................................................................................12-1
13.11Context Save Area ...................................................................................................................................................13-3
13.14Programming Model ..............................................................................................................................................13-26
14.2Modes of Operation .................................................................................................................................................14-3
14.2.1Full- and Half-Duplex Operation ......................................................................................................................14-3
14.2.210Mbps and 100Mbps MII Interface Operation ...............................................................................................14-3
14.3I/O Signal Overview ...............................................................................................................................................14-3
14.3.1Detailed Signal Descriptions .............................................................................................................................14-4
14.3.1.2.1MII Management Register Set .............................................................................................................14-6
14.4FEC Memory Map and Registers ............................................................................................................................14-6
14.4.2Control and Status (CSR) Memory Map ..........................................................................................................14-7
14.9.3Frame Control/Status Words ..........................................................................................................................14-35
14.9.3.1Receive Frame Status Word .....................................................................................................................14-35
14.9.3.2Transmit Frame Control Word .................................................................................................................14-36
14.9.7Full-Duplex Flow Control ...............................................................................................................................14-42
14.9.8Inter-Packet Gap Time ....................................................................................................................................14-43
14.9.10Internal and External Loopback ......................................................................................................................14-44
15.2.16Input Port Register (0x34)—IP .......................................................................................................................15-23
15.2.17Output Port 1 Bit Set (0x38)—OP1 ................................................................................................................15-24
15.2.18Output Port 0 Bit Set (0x3C)—OP0 ...............................................................................................................15-24
15.2.19Serial Interface Control Register (0x40)—SICR ............................................................................................15-25
15.2.20Infrared Control 1 (0x44)—IRCR1 ................................................................................................................15-27
15.2.21Infrared Control 2 (0x48)—IRCR2 ................................................................................................................15-28
15.2.22Infrared SIR Divide Register (0x4C)—IRSDR ..............................................................................................15-29
15.2.23Infrared MIR Divide Register (0x50)—IRMDR ............................................................................................15-30
15.2.24Infrared FIR Divide Register (0x54)—IRFDR ..............................................................................
15.2.25Rx FIFO Number of Data (0x58)—RFNUM .................................................................................................15-33
15.2.26Tx FIFO Number of Data (0x5C)—TFNUM .................................................................................................15-33
15.2.27Rx FIFO Data (0x60)—RFDATA ..................................................................................................................15-33
15.2.28Rx FIFO Status (0x64)—RFSTAT .................................................................................................................15-33
15.2.29Rx FIFO Control (0x68)—RFCNTL ..............................................................................................................15-34
15.2.33Rx FIFO Last Read Frame (0x7A)—RFLRFPTR ..........................................................................................15-35
15.2.34Rx FIFO Last Write Frame PTR (0x7C)—RFLWFPTR ................................................................................15-36
15.2.35Tx FIFO Data (0x80)—TFDATA .............................................................................................
15.2.36Tx FIFO Status (0x84)—TFSTAT .................................................................................................................15-36
15.2.37Tx FIFO Control (0x88)—TFCNTL ..............................................................................................................15-37
15.3.1PSC in UART Mode .......................................................................................................................................15-39
15.3.1.1Block Diagram and Signal Definition for UART Mode ..........................................................................15-39
15.3.1.3Transmitting in UART Mode ...................................................................................................................15-41
15.3.1.4Receiver in UART Mode ..........................................................................................................................15-42
15.3.1.5Configuration Sequence for UART Mode ................................................................................................15-43
15.3.2PSC in Codec Mode ........................................................................................................................................15-44
15.3.2.1Block Diagram and Signal Definition for Codec Mode ...........................................................................15-45
15.3.2.2Codec Clock and Frame Generation .........................................................................................................15-46
15.3.2.2.1BitClk and Frame in “normal” Codec and I2S Mode ........................................................................15-47
15.3.2.2.2BitClk and Frame in “Cell Phone” Mode ..........................................................................................15-47
15.3.2.2.3BitClk and Frame in SPI Mode ..........................................................................................................15-48
15.3.2.3Transmitting and Receiving in Codec Mode ............................................................................................15-49
15.3.2.4Configuration Sequence Examples for Codec Modes ..............................................................................15-50
15.3.2.4.1PSC1 in 16-bit “soft Modem” Slave Mode ..............................................................................
15.3.2.4.2PSC2 in 32-bit “soft Modem” Master Mode ......................................................................................15-51
15.3.2.4.3PSC 1 in Cell Phone Master Mode, PSC2 is Cell Phone Slave .........................................................15-51
15.3.2.4.4PSC2 in SPI Slave Mode ....................................................................................................................15-52
15.3.2.4.5PSC3 in SPI Master Mode .................................................................................................................15-53
15.3.2.4.6PSC1 in I2S Master Mode ..................................................................................................................15-54
15.3.3PSC in AC97 Mode ........................................................................................................................................15-55
15.3.3.1Block Diagram and Signal Definition for AC97 Mode ............................................................................15-56
15.3.3.2Transmitting and Receiving in AC97 Mode .............................................................................................15-57
15.3.3.4Configuration Sequence for AC97 Mode .................................................................................................15-58
15.3.4PSC in SIR Mode ............................................................................................................................................15-58
15.3.4.1Block Diagram and Signal Definition for SIR Mode ...............................................................................15-58
15.3.4.2Transmitting and Receiving in SIR Mode ................................................................................................15-59
15.3.4.3Configuration Sequence Example for SIR Mode .....................................................................................15-59
15.3.5PSC in MIR Mode ..........................................................................................................................................15-60
15.3.5.1Block Diagram and Signal Definition for MIR Mode ..............................................................................15-60
15.3.5.2Transmitting and Receiving in MIR Mode ...............................................................................................15-61
15.3.5.4Configuration Sequence Example for MIR Mode ....................................................................................15-62
15.3.6PSC in FIR Mode ............................................................................................................................................15-63
15.3.6.1Block Diagram and Signal Definition for FIR Mode ...............................................................................15-63
15.3.6.2Transmitting and Receiving in FIR Mode ................................................................................................15-63
15.3.6.3Configuration Sequence Example for FIR Mode .....................................................................................15-64
15.3.7PSC FIFO System ...........................................................................................................................................15-64
16.1.1.2Bus Grant Mechanism ................................................................................................................................16-2
16.1.1.2.1Bus Grant .............................................................................................................................................16-2
17.1.2Modes of Operation ..........................................................................................................................................17-1
17.2SPI Signal Description ............................................................................................................................................17-2
17.2.1Master In/Slave Out (MISO ) ...........................................................................................................................17-2
17.2.2Master Out/Slave In (MOSI ) ...........................................................................................................................17-2
18.2.1START Signal ...................................................................................................................................................18-2
18.2.2STOP Signal ......................................................................................................................................................18-2
18.2.2.2Data Transfer ..............................................................................................................................................18-3
18.2.2.5Clock Synchronization and Arbitration ......................................................................................................18-4
18.5Transfer Initiation and Interrupt ............................................................................................................................18-11
C Controller ..........................................................................................................................................................18-2
2
C Interface Registers ............................................................................................................................................18-5
2
C Address Register (MADR)—MBAR + 0x3D00 ........................................................................................18-5
2
C Frequency Divider Register (MFDR)—MBAR + 0x3D04 ........................................................................18-6
2
C Control Register (MCR)—MBAR + 0x3D08 ............................................................................................18-7
2
C Status Register (MSR)—MBAR + 0x3D0C ..............................................................................................18-8
2
C Data I/O Register (MDR)—MBAR+ x3D10 ..........................................................................................18-10
2
C Interrupt Control Register—MBAR + 0x3D20 ........................................................................................18-10
19.3.1RXCAN — CAN Receiver Input Pin ...............................................................................................................19-2
19.3.2TXCAN — CAN Transmitter Output Pin ........................................................................................................19-2
19.4CAN System ............................................................................................................................................................19-2
19.5.17MSCAN ID Acceptance Registers (CANIDAR0-7)—MBAR + 0x0915 ......................................................19-17
19.5.18MSCAN ID Mask Register (CANIDMR0-7)—MBAR + 0x0928 .................................................................19-19
19.6Programmer’s Model of Message Storage ............................................................................................................19-21
19.7.5Clock System ..................................................................................................................................................19-31
19.7.6Timer Link ......................................................................................................................................................19-33
19.7.7Modes of Operation ........................................................................................................................................19-33
19.7.8Low Power Options ........................................................................................................................................19-33
19.7.8.1CPU Run Mode ........................................................................................................................................19-34
19.7.8.3CPU Deep Sleep Mode .............................................................................................................................19-34
19.7.8.6MSCAN Power Down Mode ....................................................................................................................19-36
19.7.8.7Programmable Wake-Up Function ...........................................................................................................19-36
19.7.9Description of Interrupt Operation ..................................................................................................................19-36
19.7.11Recovery from STOP or WAIT ......................................................................................................................19-37
20.3Modes of Operation .................................................................................................................................................20-1
20.6.1Detailed Signal Descriptions .............................................................................................................................20-5
20.7Memory Map and Registers ....................................................................................................................................20-5
20.8.1.1J1850 Frame Format .................................................................................................................................20-16
20.8.1.4J1850 Bus Errors ......................................................................................................................................20-26
20.8.4Transmitting A Message ................................................................................................................................20-30
20.8.4.1BDLC Transmission Control Bits ............................................................................................................20-30
20.8.4.3Aborting a Transmission ..........................................................................................................................20-32
20.8.5Receiving A Message ....................................................................................................................................20-33
20.8.5.1BDLC Reception Control Bits ..................................................................................................................20-34
20.8.5.2Receiving a Message with the BDLC module ..........................................................................................20-34
20.8.5.3Filtering Received Messages ....................................................................................................................20-34
20.8.6Transmitting An In-Frame Response (IFR) ...................................................................................................20-36
20.8.6.1IFR Types Supported by the BDLC module ............................................................................................20-37
20.8.6.2BDLC IFR Transmit Control Bits ........................................................................................
20.8.6.3Transmit Single Byte IFR .........................................................................................................................20-38
20.8.9.2Initializing the Configuration Bits ............................................................................................................20-48
20.8.9.3Exiting Loopback Mode and Enabling the BDLC module ......................................................................20-48
21.2TAP Link Module (TLM) and Slave TAP Implementation ....................................................................................21-1
21.3TLM and TAP Signal Descriptions .........................................................................................................................21-4
21.3.4Test Data In (TDI) ............................................................................................................................................21-4
21.3.5Test Data Out (TDO) ........................................................................................................................................21-5
21.4Slave Test Reset (STRST ) ......................................................................................................................................21-5
21.4.2Select DR Link—SEL[0: n ] .............................................................................................................................21-5
21.4.3Slave Test Data Out—STDO[0:n] ..................................................................................................................21-5
21.5TAP State Machines ................................................................................................................................................21-5
21.6G2_LE Core JTAG/COP Serial Interface ...............................................................................................................21-6
21.7TLM Link DR Instructions ......................................................................................................................................21-7
21.8TLM Test Instructions .............................................................................................................................................21-8
21.8.1.1Device ID Register .....................................................................................................................................21-8
2-4PSC1 Port Map—5 Pins ..........................................................................................................................................2-31
2-5PSC2 Port Map—5 Pins ..........................................................................................................................................2-34
2-6PSC3 Port Map—10 Pins ........................................................................................................................................2-37
2-7USB Port Map—10 Pins .........................................................................................................................................2-43
2-8Ethernet Output Port Map—8 Pins .........................................................................................................................2-46
2-9Ethernet Input / Control Port Map—10 Pins ..........................................................................................................2-47
2-10Timer Port Map—8 Pins .....................................................................................................
2-11PSC6 Port Map—4 Pins ..........................................................................................................................................2-65
4-3Internal Hard Reset vs External HRESET Assertion ................................................................................................4-3
8-3Address Bus Mapping .............................................................................................................................................8-25
9-3Output Enable Signal .................................................................................................................................................9-4
11-4ATA Sector Format ...............................................................................................................................................11-29
12-1USB Focus Areas ....................................................................................................................................................12-1
2
C Port Map—4 Pins (two pins each, for two I2Cs) .............................................................................................2-67
12-3Typical List Structure ..............................................................................................................................................12-3
12-3Interrupt ED Structure .............................................................................................................................................12-4
15-3Signal configuration for a PSC / RS-232 interface .................................................................................................15-41
15-8PSC Codec Interface in Slave Mode .....................................................................................................................15-45
15-9Clock Generation Diagram for Codec Mode ........................................................................................................15-46
15-10Clock distribution network in cell phone mode ....................................................................................................15-48
15-14I2S Data Transmission ..........................................................................................................................................15-55
15-18PSC SIR Block Diagram .......................................................................................................................................15-59
15-19Data Format in SIR Mode .....................................................................................................................................15-59
15-20PSC MIR and FIR Block Diagram ........................................................................................................................15-61
15-22Data Format in FIR Mode .....................................................................................................................................15-63
15-23PSC FIFO System .................................................................................................................................................15-66
C Module .................................................................................................................................18-2
18-2Timing Diagram—Start, Address Transfer and Stop Signal ...................................................................................18-3
18-3Timing Diagram—Data Transfer ............................................................................................................................18-3
18-5Data Transfer, Combined Format ............................................................................................................................18-4
19-2The CAN System .....................................................................................................................................................19-3
19-3User Model for Message Buffer Organization ......................................................................................................19-26
19-8Segments within the Bit Time ...............................................................................................................................19-32
20-3Types of In-Frame Response .................................................................................................................................20-10
20-4J1850 Bus Message Format (VPW) ......................................................................................................................20-16
20-7J1850 VPW EOF and IFS Symbols ......................................................................................................................20-23
20-8J1850 VPW Active Symbols .................................................................................................................................20-24
20-9J1850 VPW BREAK Symbol ................................................................................................................................20-24
20-15Transmitting A Type 1 IFR ...................................................................................................................................20-40
20-16Transmitting A Type 2 IFR ...................................................................................................................................20-41
20-17Transmitting A Type 3 IFR ...................................................................................................................................20-43
20-18Receiving An IFR With the BDLC module ..........................................................................................................20-45
21-2Generic TAP Link Module ( TLM ) Diagram ..........................................................................................................21-3
21-3Generic Slave TAP ..................................................................................................................................................21-4
2-1Signals by Ball/Pin ...................................................................................................................................................2-4
2-2Signals by Signal Name ............................................................................................................................................2-9
2-3LocalPlus Bus Address / Data Pin Assignments .....................................................................................................2-13
2-5LocalPlus Bus Address / Data Signals ....................................................................................................................2-16
2-10PSC1 Functions by Pin ............................................................................................................................................2-32
2-12PSC2 Functions by Pin ............................................................................................................................................2-35
2-15PSC3 Functions by Pin ............................................................................................................................................2-38
2-20Ethernet Output Functions by Pin ...........................................................................................................................2-49
2-21Ethernet Input / Control Functions by Pin ...............................................................................................................2-57
2-23Timer Functions by Pin ...........................................................................................................................................2-63
2-25PSC6 Functions by Pin ............................................................................................................................................2-66
2-26I2C Functions by Pin ...............................................................................................................................................2-67
2-27SDRAM Bus Pin Functions ....................................................................................................................................2-68
2-28JTAG Access Port Pin .............................................................................................................................................2-71
2-30Dedicated GPIO Pin Function .................................................................................................................................2-72
2-31Systems Integration Unit Pin Functions ..................................................................................................................2-72
4-1Module Specific Reset Signals ..................................................................................................................................4-3
4-2Reset Configuration Word Source Pins .....................................................................................................................4-4
5-1Clock Distribution Module ........................................................................................................................................5-1
5-4Typical System Clock Frequencies ...........................................................................................................................5-5
5-5603e G2_LE Core Frequencies vs. XLB Frequencies ..............................................................................................5-6
5-8CDM JTAG ID Number Register ...........................................................................................................................5-12
5-9CDM Power On Reset Configuration Register .......................................................................................................5-12
5-17CDM System PLL Status Register ..........................................................................................................................5-19
7-13ICTL Critical Interrupt Status All Register .............................................................................................................7-15
7-14ICTL Main Interrupt Status All Register ................................................................................................................7-16
7-15ICTL Peripheral Interrupt Status All Register ........................................................................................................7-17
7-16ICTL Bus Error Status Register ..............................................................................................................................7-18
7-17ICTL Main Interrupt Emulation All Register ..........................................................................................................7-19
7-18ICTL Peripheral Interrupt Emulation All Register ..................................................................................................7-20
7-19ICTL IRQ Interrupt Emulation All Register ...........................................................................................................7-21
7-20GPIO Pin List ..........................................................................................................................................................7-22
7-21GPS Port Configuration Register ............................................................................................................................7-28
7-23GPS Simple GPIO Open Drain Type Register ........................................................................................................7-32
7-24GPS Simple GPIO Data Direction Register ............................................................................................................7-33
7-25GPS Simple GPIO Data Output Values Register ....................................................................................................7-36
7-26GPS Simple GPIO Data Input Values Register .......................................................................................................7-37
7-31GPS GPIO Simple Interrupt Data Direction Register .............................................................................................7-41
7-32GPS GPIO Simple Interrupt Data Value Out Register ............................................................................................7-42
7-38GPW WakeUp GPIO Open Drain Emulation Register ...........................................................................................7-46
7-39GPW WakeUp GPIO Data Direction Register ........................................................................................................7-47
7-40GPW WakeUp GPIO Data Value Out Register ......................................................................................................7-48
7-50GPT 0 Status Register .............................................................................................................................................7-60
7-52SLT 0 Control Register ...........................................................................................................................................7-62
7-53SLT 0 Count Value Register ...................................................................................................................................7-63
7-54SLT 0 Timer Status Register ...................................................................................................................................7-64
7-56RTC Time Set Register ...........................................................................................................................................7-66
7-57RTC Date Set Register ............................................................................................................................................7-67
7-58RTC New Year and Stopwatch Register .................................................................................................................7-68
7-59RTC Alarm and Interrupt Enable Register ..............................................................................................................7-68
7-60RTC Current Time Register ....................................................................................................................................7-69
7-61RTC Current Date Register .....................................................................................................................................7-70
7-62RTC Alarm and Stopwatch Interrupt Register ........................................................................................................7-70
7-63RTC Periodic Interrupt and Bus Error Register ......................................................................................................7-71
7-64RTC Test Register/Divides Register .......................................................................................................................7-72
8-5Memory Controller Control Register ......................................................................................................................8-19
9-3Non-Muxed Aligned Data Transfers .........................................................................................................................9-5
9-5Non-Muxed Aligned Data Transfers .........................................................................................................................9-8
9-9Chip Select Control Register ...................................................................................................................................9-17
9-10Chip Select Status Register .....................................................................................................................................9-18
9-11Chip Select Burst Control Register .........................................................................................................................9-19
9-12Chip Select Deadcycle Control Register .................................................................................................................9-22
9-15SCLPC Control Register .........................................................................................................................................9-25
9-17SCLPC Bytes Done Status Register ........................................................................................................................9-27
9-18LPC Rx/ Tx FIFO Data Word Register ...................................................................................................................9-28
9-19LPC Rx/ Tx FIFO Status Register ...........................................................................................................................9-28
9-20LPC Rx/ Tx FIFO Control Register .........................................................................................................................9-29
10-5PCI Bus Commands ..............................................................................................................................................10-44
10-6PCI I/O space byte decoding .................................................................................................................................10-46
10-7 XLB bus to PCI Byte Lanes for Memory Transactions .......................................................................................10-49
10-8Type 0 Configuration Device Number to IDSEL Translation ..............................................................................10-52
10-11Aligned PCI to XL bus Transfers ..........................................................................................................................10-55
10-12Non-contiguous PCI to XL bus Transfers (require two XLB bus accesses) .........................................................10-56
10-13Comm bus to PCI Byte Lanes for Memory Transactions .....................................................................................10-57
11-2ATA Host Status Register .......................................................................................................................................11-3
11-3ATA PIO Timing 1 Register ...................................................................................................................................11-3
11-4ATA PIO Timing 2 Register ...................................................................................................................................11-4
11-13ATA Rx/Tx FIFO Data Word Register ..................................................................................................................11-9
11-14ATA Rx/Tx FIFO Status Register ..........................................................................................................................11-9
11-15ATA Rx/Tx FIFO Control Register ......................................................................................................................11-10
11-19ATA Drive Device Control Register .....................................................................................................................11-12
11-20ATA Drive Alternate Status Register ....................................................................................................................11-13
11-21ATA Drive Data Register ......................................................................................................................................11-13
11-22ATA Drive Features Register ................................................................................................................................11-14
11-39Redefinition of Signal Lines for Ultra DMA Protocol ..........................................................................................11-36
12-1USB HC Revision Register .....................................................................................................................................12-6
12-2USB HC Control Register .......................................................................................................................................12-6
12-3USB HC Command Status Register ........................................................................................................................12-8
12-4USB HC Interrupt Status Register ...........................................................................................................................12-9
12-5USB HC Interrupt Enable Register .......................................................................................................................12-10
12-6USB HC Interrupt Disable Register ......................................................................................................................12-11
12-7USB HC HCCA Register ......................................................................................................................................12-13
..................................11-23
MPC5200B Users Guide, Rev. 1
LOT-4Freescale Semiconductor
List of Tables
TablePage
NumberNumber
12-8USB HC Period Current Endpoint Descriptor Register ........................................................................................12-13
12-9USB HC Control Head Endpoint Descriptor Register ..........................................................................................12-14
12-10USB HC Control Current Endpoint Descriptor Register ......................................................................................12-14
12-11USB HC Bulk Head Endpoint Descriptor Register ...............................................................................................12-15
12-12USB HC Bulk Current Endpint Descriptor Register .............................................................................................12-15
12-13USB HC Done Head Register ...............................................................................................................................12-16
12-14USB HC Frame Interval Register ..........................................................................................................................12-16
12-15USB HC Frame Remaining Register .....................................................................................................................12-17
12-16USB HC Frame Number Register .........................................................................................................................12-17
12-17USB HC Periodic Start Register ...........................................................................................................................12-18
12-18USB HC LS Threshold Register ...........................................................................................................................12-18
12-19USB HC Rh Descriptor A Register .......................................................................................................................12-19
12-20USB HC Rh Descriptor B Register .......................................................................................................................12-21
12-21USB HC Rh Status Register ..................................................................................................................................12-21
12-22USB HC Rh Port1 Status Register ........................................................................................................................12-23
12-23USB HC Rh Port2 Status Register ........................................................................................................................12-26
13-1SDMA Task Bar Register ........................................................................................................................................13-4
13-2SDMA Current Pointer Register .............................................................................................................................13-4
13-3SDMA End Pointer Register ...................................................................................................................................13-5
13-8SDMA Tas k Control 0 Register .............................................................................................................................13-8
13-9SDMA Task Control 2 Register ..............................................................................................................................13-9
13-10SDMA Task Control 4 Register ............................................................................................................................13-10
13-11SDMA Task Control 6 Register ............................................................................................................................13-10
13-12SDMA Task Control 8 Register ............................................................................................................................13-11
13-13SDMA Task Control A Register ...........................................................................................................................13-11
13-14SDMA Task Control C Register ...........................................................................................................................13-12
13-15SDMA Task Control E Register ............................................................................................................................13-12
13-32SDMA Debug Module Control Register ...............................................................................................................13-23
13-33Comparator 1 Type Bit Encoding .........................................................................................................................13-24
13-34Comparator 2 Type Bit Encoding .........................................................................................................................13-25
13-36SDMA Debug Module Status Register .................................................................................................................13-25
13-37Behavior of Task Table Control Bits ....................................................................................................................13-28
13-38Variable Table per Task ........................................................................................................................................13-29
14-2MII: Valid Encoding of TxD, Tx_EN and Tx_ER ..................................................................................................14-5
14-3MII: Valid Encoding of RxD, Rx_ER and Rx_DV .................................................................................................14-5
14-4MMI Format Definitions .........................................................................................................................................14-6
14-5MII Management Register Set ................................................................................................................................14-6
14-8FEC ID Register ....................................................................................................................................................14-11
14-11FEC Rx Descriptor Active Register ......................................................................................................................14-15
14-12FEC Tx Descriptor Active Register ......................................................................................................................14-15
14-13FEC Ethernet Control Register ..............................................................................................................................14-16
14-14FEC MII Management Frame Register .................................................................................................................14-17
14-15FEC MII Speed Control Register ..........................................................................................................................14-18
14-16Programming Examples for MII_SPEED Register ...............................................................................................14-19
14-17FEC MIB Control Register ....................................................................................................................................14-19
14-18FEC Receive Control Register ..............................................................................................................................14-20
14-20FEC Tx Control Register .......................................................................................................................................14-21
14-37FEC Reset Control Register ..................................................................................................................................14-33
14-42Receive Frame Status Word Format .....................................................................................................................14-35
14-43Transmit Frame Control Word Format .................................................................................................................14-36
14-44Destination Address to 6-Bit Hash ........................................................................................................................14-41
14-45PAUSE Frame Field Specification ........................................................................................................................14-43
15-3Mode Register 1 (0x00) for UART Mode ...............................................................................................................15-5
15-4Mode Register 1 (0x00) for SIR Mode ...................................................................................................................15-5
15-5Mode Register 1 (0x00) for other Modes ................................................................................................................15-5
15-6Parity Mode/Parity Type Definitions ......................................................................................................................15-6
15-7Mode Register 2 (0x00) for UART / SIR Mode .....................................................................................................15-6
15-8Mode Register 2 (0x00) for other Modes ................................................................................................................15-6
15-10Status Register (0x04) for UART Mode .................................................................................................................15-8
15-11Status Register (0x04) for SIR Mode ......................................................................................................................15-8
15-12Status Register (0x04) for MIR / FIR Mode ...........................................................................................................15-8
15-13Status Register (0x04) for other Modes ..................................................................................................................15-8
15-14Clock Select Register (0x04) for UART / SIR Mode ...........................................................................................15-11
15-15Clock Select Register (0x04) for other Modes ......................................................................................................15-11
15-16Command Register (0x08) for all Modes ..............................................................................................................15-11
15-17 Rx Buffer Register (0x0C) for UART/SIR/MIR/FIR/ Codec8/16/32 ..................................................................15-14
15-18 Rx Buffer Register (0x0C) for AC97 ...................................................................................................................15-14
15-19 Rx Buffer Register (0x0C) for Codec24 ..............................................................................................................15-14
15-20Tx Buffer Register (0x0C) for UART/SIR/MIR/FIR/Codec8/16/32 Modes ........................................................15-15
15-21TX Buffer Register (0x0C) for AC97) Modes ......................................................................................................15-15
15-22Tx Buffer Register (0x0c) for Codec24 ................................................................................................................15-16
15-23Input Port Change Register (0x10) for UART/SIR/MIR/FIR Modes ...................................................................15-16
15-24PSC 1 Auxiliary Control Register (0x10) for all Modes ....................................................................
15-25Interrupt Status Register (0x14) for UART / SIR Mode .......................................................................................15-18
15-26Interrupt Status Register (0x14) other Modes .......................................................................................................15-18
15-27Interrupt Mask Register (0x14) for UART / SIR Mode ........................................................................................15-19
15-28Interrupt Mask Register (0x14) for other Modes ..................................................................................................15-19
15-29Counter Timer Upper Register (0x18) for all Modes ............................................................................................15-20
15-30Counter Timer Lower Register (0x1C) for all Modes ...........................................................................................15-20
15-31Codec Clock Register (0x20)—CCR for Codec Mode .........................................................................................15-21
15-32Codec Clock Register (0x20)—CCR for MIR/FIR Mode ....................................................................................15-21
15-33Codec Clock Register (0x20)—CCR for other Modes .........................................................................................15-22
15-34Interrupt Vector Register (0x30) for all Modes .....................................................................................................15-23
15-35Input Port Register (0x34) for UART/SIR/MIR/FIR Modes ................................................................................15-23
15-36Input Port Register (0x34) for Codec Mode ..........................................................................................................15-23
15-37Input Port Register (0x34) for AC97 Mode ..........................................................................................................15-23
15-38Output Port 1 Bit Set Register (0x38) for all Modes ......................................................................
15-39Output Port 0 Bit Set Register (0x3C) for all Modes ............................................................................................15-24
15-40Serial Interface Control Register (0x40) for all Modes .........................................................................................15-25
15-41Infrared Control 1 (0x44) for SIR Mode ...............................................................................................................15-28
15-42Infrared Control 1 (0x44) for MIR/FIR Modes .....................................................................................................15-28
15-43Infrared Control 2 (0x48) for MIR/FIR Modes .....................................................................................................15-28
15-44Infrared Control 2 (0x48) for other Modes ...........................................................................................................15-28
15-45Infrared SIR Divide Register (0x48) for SIR Mode ..............................................................................................15-29
15-46Infrared SIR Divide Register (0x48) for other Modes ..........................................................................................15-29
15-47Infrared MIR Divide Register (0x50) for MIR Mode ...........................................................................................15-30
15-48Infrared MIR Divide Register (0x50) for other Modes .........................................................................................15-30
15-49Frequency Selection in MIR Mode .......................................................................................................................15-31
15-50Infrared FIR Divide Register (0x54) for MIR Mode .........................................................................
15-51Infrared FIR Divide Register (0x54) for other Modes ..........................................................................................15-31
15-52Frequency Selection for FIR Mode .......................................................................................................................15-32
15-53RX FIFO Number of DATA (0x58) ......................................................................................................................15-33
15-54Tx FIFO Number of Data (0x5C) ..........................................................................................................................15-33
15-55Rx FIFO Status (0x64) ..........................................................................................................................................15-33
15-56Rx FIFO Control (0x68) ........................................................................................................................................15-34
15-60Rx FIFO Last Read Frame (0x7A) ........................................................................................................................15-35
15-61Rx FIFO Last Write Frame PTR (0x7C) ...............................................................................................................15-36
15-62Tx FIFO STAT (0x84) ..........................................................................................................................................15-36
...................15-17
.......................15-24
...................15-31
MPC5200B Users Guide, Rev. 1
Freescale SemiconductorLOT-7
List of Tables
TablePage
NumberNumber
15-63Tx FIFO Control (0x88) ........................................................................................................................................15-37
15-70Clock Short Cuts ...................................................................................................................................................15-39
15-71PSC Signal Description for UART Mode .............................................................................................................15-40
15-72General Configuration Sequence for UART mode ...............................................................................................15-43
15-73Signal Definition for all Codec Modes ..................................................................................................................15-44
15-74PSC Signal Description for Codec Mode ..............................................................................................................15-46
15-7724-Bit Cell Phone Master Mode for PSC1 ............................................................................................................15-52
15-7824-Bit Cell Phone Slave Mode for PSC2 ..............................................................................................................15-52
15-798-bit SPI Slave mode for PSC2 .............................................................................................................................15-53
15-8032-bit SPI Master mode for PSC3 .........................................................................................................................15-53
15-8132-bit I2S Master Mode for PSC1 .........................................................................................................................15-54
15-82PSC Signal Description for AC97Mode ...............................................................................................................15-56
15-83General Configuration Sequence for AC97 Mode ................................................................................................15-58
15-84Signal Description for IrDa Mode .........................................................................................................................15-58
15-85Configuration Sequence Example for SIR Mode ..................................................................................................15-60
15-86Configuration Sequence Example for MIR Mode ................................................................................................15-62
15-87Configuration Sequence Example for FIR Mode ..................................................................................................15-64
16-2Arbiter Version Register .........................................................................................................................................16-5
16-3Arbiter Status Register ............................................................................................................................................16-5
16-6Arbiter Bus Signal Capture Register .......................................................................................................................16-8
17-1SPI External Signal Descriptions ............................................................................................................................17-2
17-2SPI Control Register 1 .............................................................................................................................................17-3
17-4SPI Control Register 2 .............................................................................................................................................17-4
17-8SPI Status Register ..................................................................................................................................................17-6
17-9SPI Data Register ....................................................................................................................................................17-7
17-10SPI Port Data Register .............................................................................................................................................17-7
17-11SPI Data Direction Register ....................................................................................................................................17-7
18-1I
18-2I
18-3I
18-4I
2
C Terminology ......................................................................................................................................................18-2
2
C Address Register ...............................................................................................................................................18-5
2
C Frequency Divider Register ..............................................................................................................................18-6
2
C Tap and Prescale Values ...................................................................................................................................18-6
MPC5200B Users Guide, Rev. 1
LOT-8Freescale Semiconductor
List of Tables
TablePage
NumberNumber
18-5I2C Control Register ................................................................................................................................................18-7
18-6I
18-7I
18-8I
2
C Status Register ..................................................................................................................................................18-8
2
C Data I/O Register ............................................................................................................................................18-10
2
C Interrupt Control Register ...............................................................................................................................18-10
19-3MSCAN Control Register 0 ....................................................................................................................................19-5
19-4MSCAN Control Register 1 ....................................................................................................................................19-6
19-5MSCAN Bus Timing Register 0 .............................................................................................................................19-8
19-10MSCAN Receiver Flag Register ...........................................................................................................................19-10
19-12MSCAN Transmitter Flag Register .......................................................................................................................19-12
19-17MSCAN ID Acceptance Control Register ............................................................................................................19-15
19-18Identifier Acceptance Hit Indication .....................................................................................................................19-15
20-2BDLC Control Register 1 ........................................................................................................................................20-6
20-3BDLC State Vector Register ...................................................................................................................................20-7
20-4BDLC Control Register 2 ........................................................................................................................................20-8
20-5BDLC Data Register .............................................................................................................................................20-12
20-6BDLC Analog Round Trip Delay Register ...........................................................................................................20-13
20-7BARD Values vs. Transceiver Delay and Transmitter Timing Adjustment .........................................................20-13
20-9BDLC Rate Selection for Binary Frequencies [CLKS = 1] ..................................................................................20-15
20-10BDLC Rate Selection for Integer Frequencies [CLKS = 0] ..................................................................................20-15
20-11BDLC Control Register .........................................................................................................................................20-15
20-12BDLC Status Register ...........................................................................................................................................20-16
20-13BDLC Transmitter VPW Symbol Timing for Integer Frequencies ......................................................................20-19
20-14BDLC Transmitter VPW Symbol Timing for Binary Frequencies .......................................................................20-20
20-15BDLC Receiver VPW Symbol Timing for Integer Frequencies ...........................................................................20-20
MPC5200B Users Guide, Rev. 1
Freescale SemiconductorLOT-9
List of Tables
TablePage
NumberNumber
20-16BDLC Receiver VPW Symbol Timing for Binary Frequencies ...........................................................................20-21
20-17BDLC Receiver VPW 4X Symbol Timing for Integer Frequencies .....................................................................20-21
20-18BDLC Receiver VPW 4X Symbol Timing for Binary Frequencies .....................................................................20-21
20-20IFR Control Bit Priority Encoding ........................................................................................................................20-38
21-2TLM Test Instruction Encoding ..............................................................................................................................21-8
21-3Device ID Register = 0001101D hex ......................................................................................................................21-8
0.203MAY2005AECross refs, hyperlinks, TOC, Verso, and fonts.
112AUG2005AE, TB, PL, CM, ASMinor updates.
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor1
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
Overview
Chapter 1
Introduction
1.1Overview
The digital communication networking and consumer markets require significant processor performance to enable operating systems and
applications such as VxWorks™, QNX™, JAVA and soft modems. High integration is essential to reducing device and systems costs. The
MPC5200B is specifically designed to meet these market needs while building on the family of microprocessors that use PowerPC™
architecture. For more information on PowerPC architecture, see “The Programming Environments Manual for 32-bit Implementations of the PowerPC Architecture”.
The MPC5200B integrates a high performance e300 core with a rich set of peripheral functions focused on communications and systems
integration. The e300 core design is based on the PowerPC™ core architecture. The MPC5200B incorporates an innovative I/O subsystem,
which isolates routine maintenance of peripheral functions from the embedded e300 core.
The MPC5200B supports a dual external bus architecture. It has a high speed SDRAM Bus interface that connects directly to the e300 core.
In addition, the MPC5200B has a LocalPlus Bus used as a generalized interface to system level peripheral devices and debug environments.
1.1.1Features
Key features are shown below.
•e300 core
— Superscalar architecture
— 760MIPS at 400MHz (-40 to +85
— 16k Instruction cache, 16k Data cache
— Double precision FPU
— Instruction and Data MMU
— Standard & Critical interrupt capability
•SDRAM / DDR Memory Interface
— up to 132MHz operation
— SDRAM and DDR SDRAM support
— 256-MByte addressing range per Chip Select (Two CS lines available)
— 32-bit data bus
— Built-in initialization and refresh
•Flexible multi-function External Bus Interface
— Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices
— 8 programmable Chip Selects
— Non multiplexed data access using 8/16/32 bit databus with up to 26 bit address
— Short or Long Burst capable
— Multiplexed data access using 8/16/32 bit databus with up to 25 bit address
– Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a variety of interrupt/ Wake Up
capabilities.
– 8 GPIO pins with timer capability supporting input capture, output compare and pulse width modulation (PWM) functions
— Real-time Clock with 1 second resolution
— Systems Protection (watch dog timer, bus monitor)
— Individual control of functional block clock sources
— Power management: Nap, Doze, Sleep, Deep Sleep modes
— Support of Wake Up from low power modes by different sources (GPIO, RTC, CAN)
•Test/Debug features
— JTAG (IEEE 1149.1 test access port)
— Common On-Chip Processor (COP) debug port
•On-board PLL and clock generation
•Software
— QNX
— VXWorks
— Linux
— Software Modem capable
— J AVA
2
C)
1.2Architecture
The following areas comprise the MPC5200B system architecture:
•Embedded e300 Core
•BestComm I/O Subsystem
•Controller Area Network (CAN)
•Byte Data Link Controller - Digital BDLC-D
•System Level Interfaces
•SDRAM Controller and Interface
•Multi-Function External LocalPlus Bus
•Power Management
•Systems Debug and Test
•Physical Characteristics
MPC5200B Users Guide, Rev. 1
1-2Freescale Semiconductor
Architecture
A dynamically managed external pin multiplexing scheme minimizes overall pin count. The result is low cost packaging and board assembly
costs.
Figure 1-1 shows a simplified MPC5200B block diagram.
Bus
Local
MSCAN
2x
J1850
USB
2x
SDRAM / DDR
SPI
Real-Time Clock
System Functions
Interrupt Controller
Systems Interface Unit (SIU )
GPIO/Timers
LocalPlus Controller
PCI Bus Controller
ATA Host Controller
I2C
2x
BestComm DMA
Ethernet
SDRAM / DDR
Memory Controller
SRAM 16K
PSC
6x
CommBus
e300 Core
Interface
JTAG / COP
Generation
Reset / Clock
Figure 1-1. Simplified Block Diagram—MPC5200B
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor1-3
Architecture
The MPC5200B supports a dual external bus architecture consisting of:
1.an SDRAM Bus
2.a multi-function LocalPlus Bus
The SDRAM Bus has a Memory Controller interface which supports standard SDRAM and Double Data Rate (DDR ) SDRAM devices. The
Memory Controller has 13 Memory Address (MA) lines multiplexed with 32 Data Bus lines. Standard SDRAM control signals are included.
The high-speed Memory Controller SDRAM interface connects directly to the microprocessor, allowing optimized instruction and data
bursting. The dedicated memory interface, coupled with on-chip 16Kilobyte instruction and 16Kilobyte data caches, enables high
performance for computer intensive applications, such as Java and soft modems. Still, plenty of processing power remains for peripheral
management and system control tasks.
The LocalPlus Bus provides for connection of external peripheral devices, disk storage, and slower speed memory. The LocalPlus Bus also
supports an external Boot ROM/ FLASH / SRAM interface.
The MPC5200B integrates a high performance e300 core with an I/ O subsystem containing an intelligent Direct Memory Access (DMA)
unit, BestComm. The BestComm unit is capable of:
•responding to peripheral interrupts, independent of the e300 core.
•providing low level peripheral management, protocol processing, and peripheral data movement functions.
The MPC5200B has an optimized peripheral mix to support today’s embedded automotive and telematics requirements.
Figure 1-2 shows an MPC5200B-based system.
MPC5200B Users Guide, Rev. 1
1-4Freescale Semiconductor
Architecture
SDRAM/DDR Controller
MPC5200
Embedded
e300 Core
(MPC603e)
ControlSRAM
PSC1
PSC2
PSC3
Memory
Controller
DMA
PSC4
PSC5
ATA Interface
SRAM Interface
PSC6
ENET
SIU
PCI Bus
USB
2
C1
I
Demodulator
Transport &
Video Decoder/
Encoder
Graphics
Flash,
Boot ROM
IDE Disk
Interface
Audio
Video
SDRAM
SDRAM
IC Control
AC97
Debug Interface
Codec
UART
UART
Ethernet
IrDA Rx/Tx
Printer or I/O port
Figure 1-2. MPC5200B-Based System
1.2.1Embedded e300 Core
The MPC5200B embedded e300 core is derived from Freescale’s (formerly Motorola) MPC603e family of Reduced Instruction Set Computer
(RISC) microprocessors. The e300 core is a high-performance, low-power implementation of the PowerPC superscalar architecture. The
MPC5200B e300 core contains:
•16KBytes of instruction cache
•16KBytes of data cache
Caches are 4-way set associative and use the Least Recently Used ( LRU ) replacement algorithm.
Four independent execution units are used:
1.Branch Processing Unit (BPU )
2.Integer Unit (IU)
3.Load/Store Unit (LSU )
4.System Register Unit (SRU)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor1-5
Architecture
Up to 3 instructions can be issued and retired per clock. Most instructions execute in a single cycle. The core contains an integrated Floating
Point Unit (FPU), a Data Cache Memory Management Unit and an Instruction Cache Memory Management Unit.. The core implements the
32-bit portion of the PowerPC architecture, which provides 32-bit effective addressing and integer data types of 8-, 16-, and 32-bits.
Enhancements in this core version, specific to embedded automotive/telematics include:
•Improved interrupt latency (critical interrupt)
•New MMU with additional 8 BAT ( 16 total ) registers and 1KByte page management
The e300 core performance for SPEC95 benchmark integer operations, ranges between 4.4 and 5.1 at 200MHz. In Drystone 2.1 MIPS, the
e300 core is 280MIPS at 200MHz.
1.2.2BestComm I/O Subsystem
BestComm contains an intelligent DMA unit. This unit provides a front-line interrupt control and data movement interface via a separate
peripheral bus to the on-chip peripheral functions. This leaves the e300 core free for higher level activities. The concurrent operation enables
a significant boost in overall systems performance.
BestComm supports up to 16 simultaneously enabled DMA tasks from up to 32 DMA requestors. Also included is:
•a hardware logic unit
•a hardware CRC unit
BestComm uses internal buffers for prefetched reads and post writes. Bursting is used whenever possible. This optimizes both internal and
external bus activity.
1.2.2.1Programmable Serial Controllers ( PSCs )
The MPC5200B supports six PSCs. Each can be configured to operate in different modes. PSCs support both synchronous and asynchronous
protocols. They are used to interface to external full-function modems or external CODECs for soft modem support. 8, 16, 24 and 32-bit data
widths are supported. PSCs can be configured to support 1200 baud POTS modem, SPI, I
interface supports connection to an external terminal/computer for debug support.
2
S, V.34 or V.90 protocols. The standard UART
1.2.2.210/100 Ethernet Controller
The Ethernet Controller supports the following standard MAC-PHY interfaces:
•100Mbps IEEE 802.3 MII
•10Mbps IEEE 802.3 MII
•10Mbps 7-wire interface
The controller is full duplex, supports a programmable maximum frame length and retransmission from the Tx FIFO following a collision.
1.2.2.3Universal Serial Bus (USB)
The MPC5200B supports two USB channels. The USB Controller implements the USB Host Controller/Root Hub in compliance with the
USB1.1 specification. The user may choose to have either one or two USB ports on the root hub, each of which can interface to an off-chip
USB transceiver. The Host Controller supports the Open Host Controller Interface (OHCI) standard.
1.2.2.4Infrared Support
The MPC5200B supports the IrDA format. All three IrDA modes are supported (SIR, MIR, FIR) to 4.0Mbps. The required 48MHz clock can
be generated internally or supplied externally on an input pin.
1.2.2.5Inter-Integrated Circuit (I2C)
The MPC5200B supports two I2C channels. Both master and slave interfaces can be controlled directly by the processor or can use the
BestComm Controller to buffer Tx/ Rx data when the I
2
C data rate is high.
1.2.2.6Serial Peripheral Interface (SPI )
The SPI module allows full-duplex, synchronous, serial communication between the MPC5200B and peripheral devices. It supports master
and slave mode, double-buffered operation and can operate in a polling or interrupt driven environment.
1.2.3Controller Area Network (CAN )
The MPC5200B supports two CAN channels. The CAN is an asynchronous communications protocol used in automotive and industrial
control systems. It is a high speed, short distance, priority based protocol that runs on a variety of mediums. For example, transmission media
of fiber optic cable or unshielded twisted wire pairs can be used.
MPC5200B Users Guide, Rev. 1
1-6Freescale Semiconductor
Architecture
MSCAN supports both standard and extended identifier (ID) message formats specified in BOSCH CAN protocol specification, revision 2.0,
part B. Each MSCAN module contains:
•4 receive buffers (with FIFO storage scheme )
•3 transmit buffers
•flexible maskable identifier filters
1.2.4Byte Data Link Controller - Digital BDLC-D
The MPC5200B supports J1850 Class B data communication network interface compatible and ISO compatible for low speed (<125kbps)
serial data communications in automotive applications.
•Hardware cyclical redundancy check (CRC) generation and checking
•Two power saving modes with automatic wake up on network activity
•Polling and CPU interrupt available
•Block mode receive/transmit supported
•Supports 4X mode, 41.6 kbps
•In-frame response (IFR) types 0, 1, 2, and 3 supported
•Wake up on J1850 message
1.2.5System Level Interfaces
System Level Interfaces are listed below and described in the sections that follow:
•Chip Selects
•Interrupt Controller
•Timers
•General Purpose Input/Outputs ( GPIO )
•Functional Pin Multiplexing
•Real-Time Clock (RTC)
1.2.5.1Chip Selects
The MPC5200B integrates the most common system integration interfaces and signals. There are 8 fully programmable external chip selects,
which are independent of the SDRAM interface. LP_CS0 has special features to support a Boot ROM. Two of the chip selects may be used
by the IDE disk drive interface, when enabled.
1.2.5.2Interrupt Controller
The Interrupt Controller has 4 external interrupt signals and manages both external and internal interrupts. All interrupt levels and priorities
are programmable.
The Interrupt Controller takes advantage of the new critical interrupt feature defined by the PowerPC architecture. This allows e300 core
interrupts outside operating system boundaries, for critical functions such as real-time packet processing.
1.2.5.3Timers
MPC5200B integrates several timer functions required by most embedded systems:
•Two internal Slice timers can create short-cycle periodic interrupts.
•A WatchDog timer can interrupt the processor if not regularly serviced, catching software hang-ups.
A bus monitor monitors bus cycles and provides an interrupt if transactions take longer than a prescribed time.
1.2.5.4General Purpose Input/Outputs (GPIO)
A total of 56 pins on the MPC5200B can be programmed as GPIOs.
•8 pins can interrupt the processor.
•8 pins can support a “Wake Up” capability that brings the MPC5200B out of low power modes.
•8 pins are “output only” GPIOs.
The remaining GPIO pins support a simple “set the output level” or “detect the input level” type GPIO function. Eight I/Os can be connected
to one of eight general purpose timers to support input capture, output compare or pulse width modulation functions.
The number of GPIOs available in the various modes depends on the peripheral functionality required. See pin descriptions and I/O port maps
below for more information.
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor1-7
Architecture
1.2.5.5Functional Pin Multiplexing
Many serial/parallel port pins serve multiple functions, allowing flexibility in optimizing the system to meet a specific set of integration
requirements. For example, when PSC3 interfaces to a full function external modem, 10 pins are required:
•PSC3_TXD—Transmit Data
•PSC3_RXD—Receive Data
•PSC3_
•PSC3_CTS—Clear to Send
•PSC3_CD—Carrier Detect
•MODEM_RI—Ring Indicator
•MODEM_DSR—Hook Switch
•MODEM_IO—Control I/ O ( A0 gain )
•MODEM_IO—Control I/ O ( Mode 1 )
•MODEM_IO—Control I/ O ( Mode 2 )
If PSC3 connects to a simple UART, only the first four signals (shown above) are required. The remaining 6 signals can be used as GPIOs.
If a 7-wire Ethernet connection is adequate, the additional 11 Ethernet I/ Os can be used as GPIOs.
RTS —Ready to Send
1.2.5.6Real-Time Clock (RTC)
An RTC is included on the MPC5200B. The RTC provides a 2-pin interface to an external 32.768KHz crystal. This allows internal
time-of-day/calendar tracking, as well as clock based periodic interrupts.
1.2.6SDRAM Controller and Interface
The MPC5200B high speed SDRAM Controller supports both standard SDRAM and Double Data Rate (DDR ) SDRAM devices. It supports
up to 256MBytes per chip select (2 Chip Select lines available) with a 32-bit interface. Memory sizes of 64-Mbit, 128-Mbit, 256-Mbit and
512-Mbit are supported.
1.2.7Multi-Function External LocalPlus Bus
The MPC5200B supports a multi-function external LocalPlus Bus to allow connections to PCI and ATA compliant devices, as well as external
ROM/SRAM.
The MPC5200B integrates a 3.3V, PCI V2.2 compatible external LocalPlus Bus controller and interface. This bus is a 32-bit multiplexed
address/ data bus.
The external LocalPlus Bus provides support for an ATA disk drive interface. ATA control signals (chip selects, write/read, etc.) are provided
independent of the PCI control signals. This prevents bus contention. However, the 32-bit data bus is shared. When The MPC5200B
recognizes an external LocalPlus Bus access meant for the ATA Controller, ATA control logic arbitrates for PCI interface control. The 32-bit
address/ data bus function is transformed into 16bits of ATA data and 3bits of ATA address.
The external LocalPlus Bus also allows connection to external memory or peripheral devices that adhere to a ROM or SRAM-like interface.
These devices occupy a separate location in the memory map and have independent control signals. When an internal access is decoded to
fall in the SRAM/ ROM memory space, the 32-bit PCI address/data bus is transformed into either:
•24bits of address and 8bits of data
•16bits of address and 16bits of data.
The MPC5200B supports a reset configuration mode common on the family of processors that use the PowerPC architecture. 16 bits of
configuration information is driven and sampled during reset to establish the initial processor configuration.
1.2.8Power Management
The MPC5200B is processed in a low-power static CMOS technology. In addition, it supports the dynamic power management modes
available on the MPC52xx series processors using the e300 core. These modes include:
•nap
•dose
•sleep
•deep sleep
In deep sleep, all internal clocks can be disabled, thus, reducing the power draw to CMOS leakage levels.
MPC5200B Users Guide, Rev. 1
1-8Freescale Semiconductor
Architecture
A Wake Up capability is supported by CAN, RTC, several GPIOs and the interrupt lines. Therefore, the MPC5200B can be shut down to a
low-power standby mode, then re-enabled by one of the Wake Up inputs without resetting the MPC5200B.
1.2.9Systems Debug and Test
The MPC5200B supports the Common On-chip Processor (COP) debug capability common on other microprocessors that use the PowerPC
architecture. The COP interface supports features such as:
•memory down load
•single step instruction execution
•break/ watch point capability
•access to internal registers
•pipeline tracking, etc.
The MPC5200B also supports a JTAG IEEE 1149.1 controller and test access port (TAP ).
1.2.10Physical Characteristics
•1.5V internal, 3.3V external operation ( 2.5 v for DDR interface )
•TTL compatible I / O pins
•272-pin Plastic Ball Grid Array (PBGA )
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor1-9
Architecture
MPC5200B Users Guide, Rev. 1
1-10Freescale Semiconductor
Overview
Chapter 2
Signal Descriptions
2.1Overview
The MPC5200B contains a e300 core, an internal DMA engine, BestComm, multiple functional blocks and associated I/O ports. There are
two external data/address bus structures, the LocalPlus bus and SDRAM bus. A block diagram of the MPC5200B structure is shown in Figure
1-1.
In general, the LocalPlus bus connects to external SRAM, FLASH, peripheral devices, etc. The LocalPlus bus is capable of executing standard
memory cycles, PCI cycles and ATA cycles. In addition to the data and address bus pins on the LocalPlus bus, there are pins specifically
dedicated to ATA transactions, PCI transactions and standard memory transactions. When the MPC5200B is released from reset, Chip Select
0 is the only active chip select. Program execution must always start from the “boot device” on the LocalPlus bus. There are 8 chip select
signals associated with the LocalPlus bus. It’s possible to execute from every CS. Also every CS can address “data space”.
The SDRAM bus interfaces to Synchronous DRAM. Both Single Data Rate and Double Data Rate DRAMs are supported. Executable
programs are generally loaded into memory residing on the SDRAM bus. The SDRAM bus has a 32-bit wide data/address bus structure and
is capable of burst accesses. It is possible to execute program code over the LocalPlus bus. However, the data transfer rate on the SDRAM
bus is many times faster than LocalPlus.
There are 16 peripheral functional blocks on the MPC5200B. These are General Purpose I/O, I2C, TIMER, PSC1, PSC2, PSC3, PSC4, PSC5,
PSC6, Ethernet, USB, MSCAN, SPI and J1850. Each of these functional blocks are routed to one or more I/O ports through a system of
multiplexers. A functional block can only be routed to one I/O port at a time and in many cases, several functional blocks can be routed to the
same I/O port.
2
The I/O ports are Dedicated GPIO Group, I
and the USB Group.
Figures 2-2 through 2-10 present detailed on the multiplexing options for each I/O port.
MPC5200B is packaged in a 272-pin Plastic Ball Gate Array (PBGA). Package ball locations are shown in Figure 2-1. See Appendix D, for
case diagram.
Note: Tab le 2-1 and Table 2- 2 give the signals on each pin/ball.
A20 signal:
mem_dqm_2
Figure 2-1. 272-Pin PBGA Pin Detail
Tab le 2- 1 gives a list of MPC5200B I/O signals sorted by package ball name. Tab le 2- 2 gives the same list sorted by signal name.
Many signal pins can have multiple functions depending on internal register settings. These additional functions are described in Table 2-3
through Table 2-31.
Table Loc.
bit = 0: 0000 0100 (hex)
bit = 1: fff0 0100 (hex)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor2-51
Pinout Tables
Table 2-20. Ethernet Output Functions by Pin (continued)
PIN / BALL NUMBERFunction
Pin ETH_3 Ball J01
GPIOhi - zGPIO
USB2hi - zUSB2_PrtPWR
ETH7 Wirehi - zGPIO
ETH7 Wire / USB2hi - zUSB2_PrtPWR
ETH18 Wire w/o MDhi - zETH_TXD_2
ETH18 Wire w/ MDhi - zETH_TXD_2
EHT7 Wire, UART4e, J1850hi - zUART_4_TXD
ETH7 Wire, J1850hi - zGPIO
UART_4, UART5e, J1850hi - zUART_4_TXD
UART5e, J1850hi - zGPIO
J1850hi - zGPIO
RESET Config.hi - zbit 11 -- boot_rom_wait
Reset
Value
Description
Simple General Purpose Output
USB Port Power
Simple General Purpose Output
USB Port Power
Ethernet Transmit Data Output
Ethernet Transmit Data Output
Uart Transmit Data
Simple General Purpose Output
Uart Transmit Data
Simple General Purpose Output
Simple General Purpose Output
bit = 0: 4 IPbus clocks of waitstate*
bit = 1: 48 IPbus clocks of waitstate*
MPC5200B Users Guide, Rev. 1
2-52Freescale Semiconductor
Table 2-20. Ethernet Output Functions by Pin (continued)
Pinout Tables
PIN / BALL NUMBERFunction
Pin ETH_4 Ball J02
GPIOhi - zGPIO
USB2hi - zUSB2_Speed
ETH7 Wirehi - zGPIO
ETH7 Wire / USB2hi - zUSB2_Speed
ETH18 Wire w/o MDhi - zETH_TXD_3
ETH18 Wire w/ MDhi - zETH_TXD_3
EHT7 Wire, UART4e, J1850hi - zJ1850_TX
ETH7 Wire, J1850hi - zJ1850_TX
UART_4, UART5e, J1850hi - zJ1850_TX
UART5e, J1850hi - zJ1850_TX
J1850hi - zJ1850_TX
RESET Config.hi - zbit 12 -- boot_rom_swap
Reset
Value
Description
Simple General Purpose Output
USB Speed
Simple General Purpose Output
USB Speed
Ethernet Transmit Data Output
Ethernet Transmit Data Output
J1850 Transmit Data
J1850 Transmit Datat
J1850 Transmit Data
J1850 Transmit Data
J1850 Transmit Data
bit = 0: no byte lane swap - same endian ROM
image
bit = 1: byte lane swap - different endian ROM image
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor2-53
Pinout Tables
Table 2-20. Ethernet Output Functions by Pin (continued)
PIN / BALL NUMBERFunction
Pin ETH_5 Ball L03
GPIOhi - zGPIO
USB2hi - zUSB2_Suspend
ETH7 Wirehi - zGPIO
ETH7 Wire / USB2hi - zUSB2_Suspend
ETH18 Wire w/o MDhi - zETH_TXERR
ETH18 Wire w/ MDhi - zETH_TXERR
EHT7 Wire, UART4e, J1850hi - zUART_4_RTS
ETH7 Wire, J1850hi - zGPIO
UART_4, UART5e, J1850hi - zUART_4_RTS
UART5e, J1850hi - zGPIO
J1850hi - zGPIO
RESET Config.hi - zbit 13 -- boot_rom_size For “non-muxed” boot
Reset
Value
Description
Simple General Purpose Output
USB Suspend
Simple General Purpose Output
USB Suspend
Ethernet Transmit Error Output
Ethernet Transmit Error Output
Uart Ready To Send
Simple General Purpose Output
Uart Ready To Send
Simple General Purpose Output
Simple General Purpose Output
ROMs
bit = 0: 8-bit boot ROM data bus / 24-bit boot ROM
address
bit = 1: 16-bit boot ROM data bus / 16-bit boot ROM
address
For "muxed" boot ROMs boot ROM addr is max 25
significant bits during address tenure.
bit = 0: 16-bit ROM data bus
bit = 1: 32-bit ROM data bus
For "large flash" boot case boot Flash addr is 25
bits.
bit = 0: 8-bit Flash data bus
bit = 1: 16-bit Flash data bus
MPC5200B Users Guide, Rev. 1
2-54Freescale Semiconductor
Table 2-20. Ethernet Output Functions by Pin (continued)
Pinout Tables
PIN / BALL NUMBERFunction
Pin ETH_6 Ball N02
GPIOhi - zGPIO
USB2hi - zUSB2_OE
ETH7 Wirehi - zGPIO
ETH7 Wire / USB2hi - zUSB2__OE
ETH18 Wire w/o MDhi - zGPIO
ETH18 Wire w/ MDhi - zETH_MDC
EHT7 Wire, UART4e, J1850hi - zGPIO
ETH7 Wire, J1850hi - zGPIO
UART_4, UART5e, J1850hi - zGPIO
UART5e, J1850hi - zGPIO
J1850hi - zGPIO
RESET Config.hi - zbit 14 -- boot_rom_type
Reset
Value
Description
Simple General Purpose Output
USB Output Enable
Simple General Purpose Output
USB Output Enable
Simple General Purpose Output
Ethernet Transmit Error Output
Simple General Purpose Output
Simple General Purpose Output
Simple General Purpose Output
Simple General Purpose Output
Simple General Purpose Output
bit = 0: non-muxed boot ROM bus, single tenure
transfer.
bit = 1: muxed boot ROM bus, PPC like with address
& data tenures,
ALE_b & TS_b active.
Note 3.
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor2-55
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.