Freescale Semiconductor MPC5200 Application Note
Freescale Semiconductor
Application Note
MPC5200 ATA Interface
by: Martin Nykodym
Transportation Standard Products Group
AN3223
Rev. 0, 2/2006
1 Introduction
This application note describes initialization, general
rules, programming model and performance analysis for
the MPC5200 ATA interface, mainly from a software
perspective. The main focus is to help system architects
understand which mode under what circumstances is
optimal for the final product. Detailed software examples
can be found on the publicly available CD with sample
code for the MPC5200. The MPC5200B microcontroller
is based on an e300
instruction set.
The ATA interface is used to connect:
• Hard disks
•CD-ROMs
• DVDs
• Flash storage devices
The MPC5200 ATA interface is fully compatible with
AT A/AT API-4 specification (A T Attachment with Packet
Interface Extension, ANSI NCITS 317-1998) supporting
all three groups of modes:
1
core using the PowerPC
TM
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 ATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Electrical Characteristics . . . . . . . . . . . . . . . . 3
2.2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 IO Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Byte Ordering. . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Register Addressing . . . . . . . . . . . . . . . . . . . 5
2.6 Sector Addressing . . . . . . . . . . . . . . . . . . . . . 6
2.7 ATA Programming Model . . . . . . . . . . . . . . . 6
2.8 Host Initialization . . . . . . . . . . . . . . . . . . . . . . 9
2.9 Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Performance Analysis . . . . . . . . . . . . . . . . . . . . . 14
4 Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Appendix A MPC5200 ATA Register Summary
1. e300, 603e, and G2LE are synonymous.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
ATA Interface
• PIO (from PIO-0 to PIO-4) – up to 16.7 MBytes/sec
• Multiword DMA (from MDMA-0 to MDMA-2) – up to 16.7 MBytes/sec
• Ultra DMA (from UDMA-0 to UDMA-2) – up to 33 MBytes/sec
MPC5200 supports 27-bit and 48-bit LBA addressing on every device.
2ATA Interface
The MPC5200 ATA interface includes three groups of registers:
• AT A host registers – host configuration, timing values for all modes (from PIO, MDMA, UDMA)
• ATA FIFO registers – control ATA FIFO for DMA modes (MDMA, UDMA)
• ATA drive registers – access to the registers physically located on the ATA drive
Figure 1 illustrates basic components of the MPC5200 ATA interface internal to the MPC5200. Data
transfer is driven either by MPC5200 core (PIO) or by the BestComm DMA engine (MDMA, UDMA).
BestComm is designed to offload the MPC5200 core and can transfer data to/from different peripherals
simultaneously. The MPC5200 ATA interface is clocked by the IPBI clock of the MPC5200 processor
(66/132 MHz). MPC5200 acts as an ATA host and can control up to two ATA devices as defined in
ATA/ATAPI-4 specification. Pin ATA_ISOLATION of the MPC5200 (not defined as a signal by
ATA/ATAPI-4 spec) connects to the transceiver’s OE pin to control the direction (high = write to drive,
low = read from drive) of the transfer.
BestComm
(higher priority)
IPBI
(lower priority)
ATA device 0
(e.g. DVD drive)
MPC5200
ATA Rx/Tx FIFO
Interface
(MDMA/UDMA)
Arbiter
IPBI Interface
IPBI clock (66/132 MHz)
ATA 40-pin cable
(PIO)
ATA
Line
Drivers
3.3 V – 5 V
ATA Host Interface
ATA_ISOLATION
ATA device 1
(e.g. CompactFlash)
Figure 1. ATA Architecture
MPC5200 ATA Interface, Rev. 0
Freescale Semiconductor2
ATA Interface
2.1 Electrical Characteristics
AT A is a vo ltage level interface and the table below defines the voltage levels fo r logical ones and zeroes
or input and output values.
Table 1. ATA DC Characteristics
Description Min Max
Driver sink current1
I
oL
I
V
V
V
V
NOTES:
1
IoL for DASP shall be 12 mA minimum to meet legacy timing and signal integrity.
2
IoH value at 400 mA is insufficient in the case of DMARQ that is typically pulled low by a 5.6 kW
resistor.
Driver source current
oH
Voltage input high (logical one) 2.0 Vdc —
iH
Voltage input low (logical zero) — 0.8 Vdc
iL
Voltage output high (IoH=-400 µA, logical one) 2.4 Vdc —
oH
Voltage output low (IoL= 12 mA, logical zero) — 0.5 Vdc
oL
2.2 Signals
ATA Signal ATA Acronym MPC5200 Pin Direction
Cable select CSEL — > 28
Chip select 0 CS0- ATA_CSB0 > 37
Chip select 1 CS1- ATA_CSB1 > 38
Data bus bit 0 DD0 ATA_DATA_0 <> 17
Data bus bit 1 DD1 ATA_DATA_1 <> 15
2
Table 2. ATA Signals
4mA —
400 µA—
40-Pin
ATA Cable
Data bus bit 2 DD2 ATA_DATA_2 <> 13
Data bus bit 3 DD3 ATA_DATA_3 <> 11
Data bus bit 4 DD4 ATA_DATA_4 <> 9
Data bus bit 5 DD5 ATA_DATA_5 <> 7
Data bus bit 6 DD6 ATA_DATA_6 <> 4
Data bus bit 7 DD7 ATA_DATA_7 <> 3
Data bus bit 8 DD8 ATA_DATA_8 <> 4
Data bus bit 9 DD9 ATA_DATA_9 <> 6
Data bus bit 10 DD10 ATA_DATA_10 <> 8
Data bus bit 11 DD11 ATA_DATA_11 <> 10
Data bus bit 12 DD12 ATA_DATA_12 <> 12
Data bus bit 13 DD13 ATA_DATA_13 <> 14
MPC5200 ATA Interface, Rev. 0
Freescale Semiconductor 3
ATA Interface
Table 2. ATA Signals (continued)
ATA Signal ATA Acronym MPC5200 Pin Direction
Data bus bit 14 DD13 ATA_DATA_14 <> 16
Data bus bit 15 DD14 ATA_DATA_15 <> 18
Device active or slave (Device 1)
present
Device address bit 0 DA0 ATA_SA_0 > 35
Device address bit 1 DA1 ATA_SA_1 > 33
Device address bit 2 DA2 ATA_SA_2 > 36
DMA acknowledge DMACK- ATA_DACK_B > 29
DMA request DMARQ ATA_DRQ < 21
Interrupt request INTRQ ATA_INTRQ < 31
I/O read
DMA ready during Ultra DMA data in
bursts
Data strobe during Ultra DMA data
out bursts
I/O ready
DMA ready during Ultra DMA data
out bursts
Data strobe during Ultra DMA data in
bursts
I/O write
Stop during Ultra DMA data bursts
Passed diagnostics
Cable assembly type identifier
DASP- — > 39
DIOR-
HDMARDY-
HSTROBE
IORDY-
DDMARDY-
DSTROBE
DIOW-
STOP
PDIAGCBLID-
ATA _IO R _ B >
>
>
ATA_IOCHRDY <
<
<
ATA _ IO W _B >
>
-<>34
40-Pin
ATA Cable
25
27
23
Reset RESET- HRESET_B > 1
Ground GND 2,19,22,24,
26,
30,40
2.3 IO Cable
The cable specification impacts system integrity and the maximum length that shall be supported in any
application. Cable total length shall not exceed 0.46 m (18 in.). Cable capacitance shall not exceed 35 pF.
80-pin grounded cable helps to avoid problems with noise and inductance although 40-pin cable is
sufficient for modes up to UDMA-2 as in the ATA/ATAPI-4 spec. Also ATA/ATAPI-4 compliant
termination is a must; otherwise, CRC checksum error may randomly occur.
MPC5200 ATA Interface, Rev. 0
Freescale Semiconductor4
ATA Interface
2.4 Byte Ordering
Assuming a block of data contains "n" bytes of information, the bytes are labeled Byte(0) through
Byte(n-1), where Byte(0) is the first byte of the block, and Byte(n-1) is the last byte of the block. Table 3
shows the order of the bytes on the ATA interface.
Table 3. ATA Byte Ordering
DD15DD14DD13DD12DD11DD10DD9DD8DD7DD6DD5DD4DD3DD2DD1DD
0
First transfer Byte (1) Byte (0)
Second transfer Byte (3) Byte (2)
...
Last transfer Byte (n-1) Byte (n-2)
2.5 Register Addressing
This section describes the generation of the actual address (CSn-, DAn) that is present on the physical A TA
interface to address an ATA drive register by means of operations on internal registers of the MPC5200.
Table 4 shows how internal registers are decoded to ATA bus operations.
Table 4. ATA Register Address/Chip Select Decoding
.
Addresses Functions
MPC5200
register
address
— 1 1 x x x Data bus high impedance Not used
— 1 0 0 x x Data bus high impedance Not used
— 1 0 1 0 x Data bus high impedance Not used
0x3A5C 1 0 1 1 0 Drive alternate status Drive device control
— 1 0 1 1 1 Obsolete Not used
0x3A60 0 1 0 0 0 Drive data Drive data
0x3A64 0 1 0 0 1 Drive error Drive features
0x3A68 0 1 0 1 0 Drive sector count Drive sector count
0x3A6c 0 1 0 1 1 Drive sector number Drive sector number
0x3A70 0 1 1 0 0 Drive cylinder low Drive cylinder low
0x3A74 0 1 1 0 1 Drive cylinder high Drive cylinder high
CS0- CS1- DA2 DA1 DA0
READ (DIOR-) WRITE (DIOW-)
Control Block Registers
Drive LBA bits 0-7* Drive LBA bits 0-7*
Drive LBA bits 8-15* Drive LBA bits 8-15*
Drive LBA bits 16-23* Drive LBA bits 16-23*
Freescale Semiconductor 5
MPC5200 ATA Interface, Rev. 0
ATA Interface
Table 4. ATA Register Address/Chip Select Decoding (continued)
0x3A78 0 1 1 1 0 Drive device/head Drive device/head
Drive LBA bits 24-27* Drive LBA bits 24-27*
0x3A7C 0 1 1 1 1 Drive device status Drive command
— 0 0 x x x Invalid address Invalid address
*Mapping of registers in LBA mode
2.6 Sector Addressing
The addressing of data sectors recorded on the device's media is performed by a logical sector address.
Two modes are supported:
• Cylinder/head/sector addressing (CHS)
• Logical block addressing (LBA)
The MPC5200 host system may select either CHS translation addressing or LBA addressing on a
command-by-command basis by using the LBA bit in the ATA drive device/head register. The LBA bit
must be set if the host uses LBA addressing mode. The MPC5200 allows 27-bit LBA addressing per
device.
2.7 ATA Programming Model
Figure 2 describes the typical structure and sequence of steps needed to initialize and issue ATA
commands for MPC5200.
MPC5200 ATA Interface, Rev. 0
Freescale Semiconductor6
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