Freescale Semiconductor MCF5480, MCF5481, MCF5482, MCF5483, MCF5485 User Manual

MCF548x Reference Manual

Devices Supported:

MCF5485 MCF5482
MCF5484 MCF5481
MCF5483 MCF5480

Document Number: MCF5485RM

Rev. 3

01/2006

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© Freescale Semiconductor, Inc. 2006. All rights reserved.

MCF5485RM
Rev. 3
01/2006

Overview

1

Signal Descriptions

ColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)

Memory Management Unit (MMU)

Floating-Point Unit (FPU)

Local Memory

Debug Support

System Integration Unit (SIU)

Internal Clocks and Bus Architecture

General Purpose Timers (GPT)

Slice Timers (SLT)

Interrupt Controller (INTC)

Edge Port Module (EPORT)

General Purpose I/O (GPIO)

2
3
4
5
6
7
8

9
10
11

12
13
14
15

System SRAM

FlexBus

SDRAM Controller (SDRAMC)

PCI Bus Controller (PCI)

PCI Bus Arbiter (PCIARB)

FlexCAN

Integrated Secuity Engine (SEC)

IEEE 1149.1 Test Access Port (JTAG)

Multichannel DMA (MCD)

Comm Timer Module (CTM)

Programmable Serial Controller (PSC)

2

C interface

I

DMA Serial Peripheral Interface (DSPI)

USB 2.0 Device Controller

16
17
18
19
20
21
22
23
24
25
26
27
28
29

Fast Ethernet Controller (FEC)

Mechanical Data

Register Memory Map Quick Reference

Index

30
31

A

IND

1

Overview

2
3
4
5
6
7
8
9

10
11

12
13
14
15

Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Memory Management Unit (MMU)
Floating-Point Unit (FPU)
Local Memory
Debug Support
System Integration Unit (SIU)
Internal Clocks and Bus Architecture
General Purpose Timers (GPT)
Slice Timers (SLT)
Interrupt Controller (INTC)
Edge Port Module (EPORT)

General Purpose I/O (GPIO)

16
17
18
19
20
21
22
23
24
25
26
27
28
29

System SRAM

FlexBus

SDRAM Controller (SDRAMC)

PCI Bus Controller (PCI)

PCI Bus Arbiter (PCIARB)

FlexCAN

Integrated Secuity Engine (SEC)

IEEE 1149.1 Test Access Port (JTAG)

Multichannel DMA (MCD)

Comm Timer Module (CTM)

Programmable Serial Controller (PSC)

2

C interface

I

DMA Serial Peripheral Interface (DSPI)

USB 2.0 Device Controller

30
31

A

IND

Fast Ethernet Controller (FEC)

Mechanical Data

Register Memory Map Quick Reference

Index

Contents

Paragraph
Number

Title

Page

Number

Chapter 1

Overview

1.1 MCF548x Family Overview ........................................................................................... 1-1

1.2 MCF548x Block Diagram .............................................................................................. 1-2

1.3 MCF548x Family Products ............................................................................................. 1-3

1.4 MCF548x Family Features ............................................................................................. 1-3

1.4.1 ColdFire V4e Core Overview ..................................................................................... 1-5

1.4.2 Debug Module (BDM) ................................................................................................ 1-6

1.4.3 JTAG ........................................................................................................................... 1-6

1.4.4 On-Chip Memories ..................................................................................................... 1-7

1.4.4.1 Caches ..................................................................................................................... 1-7

1.4.4.2 System SRAM ........................................................................................................ 1-7

1.4.5 PLL and Chip Clocking Options ................................................................................ 1-7

1.4.6 Communications I/O Subsystem ................................................................................ 1-8

1.4.6.1 DMA Controller ...................................................................................................... 1-8

1.4.6.2 10/100 Fast Ethernet Controller (FEC) ................................................................... 1-8

1.4.6.3 USB 2.0 Device (Universal Serial Bus) ................................................................. 1-8

1.4.6.4 Programmable Serial Controllers (PSCs) ............................................................... 1-9

1.4.6.5 I2C (Inter-Integrated Circuit) ................................................................................. 1-9

1.4.6.6 DMA Serial Peripheral Interface (DSPI) ................................................................ 1-9

1.4.6.7 Controller Area Network (CAN) .......................................................................... 1-10

1.4.7 DDR SDRAM Memory Controller ........................................................................... 1-10

1.4.8 Peripheral Component Interconnect (PCI) ............................................................... 1-10

1.4.9 Flexible Local Bus (FlexBus) ................................................................................... 1-10

1.4.10 Security Encryption Controller (SEC) ...................................................................... 1-11

1.4.11 System Integration Unit (SIU) .................................................................................. 1-11

1.4.11.1 Timers ................................................................................................................... 1-11

1.4.11.2 Interrupt Controller ............................................................................................... 1-12

1.4.11.3 General Purpose I/O ............................................................................................. 1-12

Chapter 2

Signal Descriptions

2.1 Introduction ..................................................................................................................... 2-1

2.1.1 Block Diagram ............................................................................................................ 2-1

2.2 MCF548x External Signals ........................................................................................... 2-16

2.2.1 FlexBus Signals ........................................................................................................ 2-16

2.2.1.1 Address/Data Bus (AD[31:0]) .............................................................................. 2-16

2.2.1.2 Chip Select (FBCS

2.2.1.3 Address Latch Enable (ALE) ................................................................................ 2-17

Freescale Semiconductor v

[5:0]) ....................................................................................... 2-17

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2.2.1.4 Read/Write (R/W) ................................................................................................. 2-17

2.2.1.5 Transfer Burst (TBST

) .......................................................................................... 2-17

2.2.1.6 Transfer Size (TSIZ[1:0]) ..................................................................................... 2-17

2.2.1.7 Byte Selects (BE

/BWE[3:0]) ................................................................................ 2-18

2.2.1.8 Output Enable (OE) .............................................................................................. 2-18

2.2.1.9 Transfer Acknowledge (TA) ................................................................................. 2-18

2.2.2 SDRAM Controller Signals ...................................................................................... 2-18

2.2.2.1 SDRAM Data Bus (SDDATA[31:0]) ................................................................... 2-18

2.2.2.2 SDRAM Address Bus (SDADDR[12:0]) ............................................................. 2-18

2.2.2.3 SDRAM Bank Addresses (SDBA[1:0]) ............................................................... 2-19

2.2.2.4 SDRAM Row Address Strobe (RAS) ................................................................... 2-19

2.2.2.5 SDRAM Column Address Strobe (CAS) ............................................................. 2-19

2.2.2.6 SDRAM Chip Selects (SDCS[3:0]) ...................................................................... 2-19

2.2.2.7 SDRAM Write Data Byte Mask (SDDM[3:0]) .................................................... 2-19

2.2.2.8 SDRAM Data Strobe (SDDQS[3:0]) .................................................................... 2-19

2.2.2.9 SDRAM Clock (SDCLK[1:0]) ............................................................................. 2-19

2.2.2.10 Inverted SDRAM Clock (SDCLK[1:0]) ............................................................... 2-19

2.2.2.11 SDRAM Write Enable (SDWE) ........................................................................... 2-19

2.2.2.12 SDRAM Clock Enable (SDCKE) ......................................................................... 2-19

2.2.2.13 SDR SDRAM Data Strobe (SDRDQS) ................................................................ 2-19

2.2.2.14 SDRAM Reference Voltage (VREF) ................................................................... 2-20

2.2.3 PCI Controller Signals .............................................................................................. 2-20

2.2.3.1 PCI Address/Data Bus (PCIAD[31:0]) ................................................................. 2-20

2.2.3.2 Command/Byte Enables (PCICXBE[3:0]) ........................................................... 2-20

2.2.3.3 Device Select (PCIDEVSEL) ............................................................................... 2-20

2.2.3.4 Frame (PCIFRM) .................................................................................................. 2-20

2.2.3.5 Initialization Device Select (PCIIDSEL) .............................................................. 2-20

2.2.3.6 Initiator Ready (PCIIRDY) ................................................................................... 2-20

2.2.3.7 Parity (PCIPAR) ................................................................................................... 2-20

2.2.3.8 Parity Error (PCIPERR) ....................................................................................... 2-20

2.2.3.9 Reset (PCIRESET) ............................................................................................... 2-21

2.2.3.10 System Error (PCISERR) ..................................................................................... 2-21

2.2.3.11 Stop (PCISTOP) ................................................................................................... 2-21

2.2.3.12 Target Ready (PCITRDY) .................................................................................... 2-21

2.2.3.13 External Bus Grant (PCIBG[4:1]) ........................................................................ 2-21

2.2.3.14 External Bus Grant/Request Output (PCIBG0

/PCIREQOUT) ............................ 2-21

2.2.3.15 External Bus Request (PCIBR[4:0]) ..................................................................... 2-21

2.2.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN) .......................................... 2-21

2.2.4 Interrupt Control Signals .......................................................................................... 2-21

2.2.4.1 Interrupt Request (IRQ

[7:1]) ................................................................................ 2-21

2.2.5 Clock and Reset Signals ........................................................................................... 2-22

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2.2.5.1 Reset In (RSTI) ..................................................................................................... 2-22

2.2.5.2 Reset Out (RSTO) ................................................................................................. 2-22

2.2.5.3 Clock In (CLKIN) ................................................................................................. 2-22

2.2.6 Reset Configuration Pins .......................................................................................... 2-22

2.2.6.1 AD[12:8]—CLKIN to SDCLK Ratio (CLKCONFIG[4:0]) ................................ 2-22

2.2.6.2 AD5—FlexBus Size Configuration (FBSIZE) ..................................................... 2-23

2.2.6.3 AD4—32-bit FlexBus Configuration (FBMODE) ............................................... 2-23

2.2.6.4 AD3—Byte Enable Configuration (BECONFIG) ................................................ 2-23

2.2.6.5 AD2—Auto Acknowledge Configuration (AACONFIG) .................................... 2-24

2.2.6.6 AD[1:0]—Port Size Configuration (PSCONFIG) ................................................ 2-24

2.2.7 Ethernet Module Signals ........................................................................................... 2-24

2.2.7.1 Management Data (E0MDIO, E1MDIO) ............................................................. 2-24

2.2.7.2 Management Data Clock (E0MDC, E1MDC) ...................................................... 2-25

2.2.7.3 Transmit Clock (E0TXCLK, E1TXCLK) ............................................................ 2-25

2.2.7.4 Transmit Enable (E0TXEN, E1TXEN) ................................................................ 2-25

2.2.7.5 Transmit Data 0 (E0TXD0, E1TXD0) ................................................................. 2-25

2.2.7.6 Collision (E0COL, E1COL) ................................................................................. 2-25

2.2.7.7 Receive Clock (E0RXCLK, E1RXCLK) ............................................................. 2-25

2.2.7.8 Receive Data Valid (E0RXDV, E1RXDV) .......................................................... 2-25

2.2.7.9 Receive Data 0 (E0RXD0, E1RXD0) .................................................................. 2-25

2.2.7.10 Carrier Receive Sense (E0CRS, E1CRS) ............................................................. 2-25

2.2.7.11 Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1]) .................................................. 2-25

2.2.7.12 Transmit Error (E0TXER, E1TXER) ................................................................... 2-26

2.2.7.13 Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1]) ................................................... 2-26

2.2.7.14 Receive Error (E0RXER, E1RXER) .................................................................... 2-26

2.2.8 Universal Serial Bus (USB) ...................................................................................... 2-26

2.2.8.1 USB Differential Data (USBD+, USBD–) ........................................................... 2-26

2.2.8.2 USBVBUS ............................................................................................................ 2-26

2.2.8.3 USBRBIAS ........................................................................................................... 2-26

2.2.8.4 USBCLKIN .......................................................................................................... 2-26

2.2.8.5 USBCLKOUT ...................................................................................................... 2-26

2.2.9 DMA Serial Peripheral Interface (DSPI) Signals ..................................................... 2-26

2.2.9.1 DSPI Synchronous Serial Data Output (DSPISOUT) .......................................... 2-26

2.2.9.2 DSPI Synchronous Serial Data Input (DSPISIN) ................................................. 2-27

2.2.9.3 DSPI Serial Clock (DSPISCK) ............................................................................. 2-27

2.2.9.4 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 2-27

2.2.9.5 DSPI Chip Selects (DSPICS[2:3]) ........................................................................ 2-27

2.2.9.6 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 2-27

2.2.10 FlexCAN Signals ...................................................................................................... 2-27

2.2.10.1 FlexCAN Transmit (CANTX0, CANTX1) .......................................................... 2-27

2.2.10.2 FlexCAN Receive (CANRX0, CANRX1) ........................................................... 2-27

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2.2.11 I2C I/O Signals .......................................................................................................... 2-27

2.2.11.1 Serial Clock (SCL) ............................................................................................... 2-28

2.2.11.2 Serial Data (SDA) ................................................................................................. 2-28

2.2.12 PSC Module Signals ................................................................................................. 2-28

2.2.12.1 Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD) .. 2-28

2.2.12.2 Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD) ..... 2-28

2.2.12.3 Clear-to-Send (PSCnCTS/PSCBCLK) ................................................................. 2-28

2.2.12.4 Request-to-Send (PSCnRTS/PSCFSYNC) ........................................................... 2-28

2.2.13 DMA Controller Module Signals ............................................................................. 2-28

2.2.13.1 DMA Request (DREQ[1:0]) ................................................................................. 2-28

2.2.13.2 DMA Acknowledge (DACK[1:0]) ....................................................................... 2-28

2.2.14 Timer Module Signals .............................................................................................. 2-29

2.2.14.1 Timer Inputs (TIN[3:0]) ....................................................................................... 2-29

2.2.14.2 Timer Outputs (TOUT[3:0]) ................................................................................. 2-29

2.2.15 Debug Support Signals ............................................................................................. 2-29

2.2.15.1 Processor Clock Output (PSTCLK) ...................................................................... 2-29

2.2.15.2 Processor Status Debug Data (PSTDDATA[7:0]) ............................................... 2-29

2.2.15.3 Development Serial Clock/Test Reset (DSCLK/TRST) ...................................... 2-29

2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS) ........................................................ 2-30

2.2.15.5 Development Serial Input/Test Data Input (DSI/TDI) ......................................... 2-30

2.2.15.6 Development Serial Output/Test Data Output (DSO/TDO) ................................. 2-30

2.2.15.7 Test Clock (TCK) ................................................................................................. 2-30

2.2.16 Test Signals ............................................................................................................... 2-30

2.2.16.1 Test Mode (MTMOD[3:0]) .................................................................................. 2-30

2.2.17 Power and Reference Pins ........................................................................................ 2-31

2.2.17.1 Positive Pad Supply (EVDD) ............................................................................... 2-31

2.2.17.2 Positive Core Supply (IVDD) ............................................................................... 2-31

2.2.17.3 Ground (VSS) ....................................................................................................... 2-31

2.2.17.4 USB Power (USBVDD) ....................................................................................... 2-31

2.2.17.5 USB Oscillator Power (USB_OSCVDD) ............................................................. 2-31

2.2.17.6 USB PHY Power (USB_PHYVDD) .................................................................... 2-31

2.2.17.7 USB Oscillator Analog Power (USB_OSCAVDD) ............................................. 2-31

2.2.17.8 USB PLL Analog Power (USB_PLLVDD) ......................................................... 2-31

2.2.17.9 SDRAM Memory Supply (SDVDD) .................................................................... 2-31

2.2.17.10 PLL Analog Power (PLLVDD) ............................................................................ 2-31

2.2.17.11 PLL Analog Ground (PLLVSS) ........................................................................... 2-31

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Chapter 3

ColdFire Core

3.1 Core Overview ................................................................................................................ 3-1

3.2 Features ........................................................................................................................... 3-1

3.2.1 Enhanced Pipelines ..................................................................................................... 3-2

3.2.1.1 Instruction Fetch Pipeline (IFP) .............................................................................. 3-3

3.2.1.2 Operand Execution Pipeline (OEP) ........................................................................ 3-4

3.2.1.3 Harvard Memory Architecture ............................................................................... 3-6

3.2.2 Debug Module Enhancements .................................................................................... 3-6

3.3 Programming Model ....................................................................................................... 3-7

3.3.1 User Programming Model .......................................................................................... 3-9

3.3.1.1 Data Registers (D0–D7) ......................................................................................... 3-9

3.3.1.2 Address Registers (A0–A6) .................................................................................... 3-9

3.3.2 User Stack Pointer (A7) ............................................................................................. 3-9

3.3.2.1 Program Counter (PC) ............................................................................................ 3-9

3.3.2.2 Condition Code Register (CCR) ............................................................................. 3-9

3.3.3 EMAC Programming Model .................................................................................... 3-10

3.3.4 FPU Programming Model ......................................................................................... 3-10

3.3.5 Supervisor Programming Model ............................................................................... 3-11

3.3.5.1 Status Register (SR) .............................................................................................. 3-12

3.3.5.2 Vector Base Register (VBR) ................................................................................ 3-12

3.3.5.3 Cache Control Register (CACR) .......................................................................... 3-13

3.3.5.4 Access Control Registers (ACR0–ACR3) ............................................................ 3-13

3.3.5.5 RAM Base Address Registers (RAMBAR0 and RAMBAR1) ............................ 3-13

3.3.5.6 Module Base Address Register (MBAR) ............................................................. 3-13

3.3.6 Programming Model Table ....................................................................................... 3-13

3.4 Data Format Summary .................................................................................................. 3-15

3.4.1 Data Organization in Registers ................................................................................. 3-15

3.4.1.1 Integer Data Format Organization in Registers .................................................... 3-15

3.4.1.2 Integer Data Format Organization in Memory ..................................................... 3-16

3.4.2 EMAC Data Representation ..................................................................................... 3-17

3.4.2.1 Floating-Point Data Formats and Types ............................................................... 3-17

3.5 Addressing Mode Summary ......................................................................................... 3-18

3.6 Instruction Set Summary .............................................................................................. 3-19

3.6.1 Additions to the Instruction Set Architecture ........................................................... 3-19

3.6.2 Instruction Set Summary .......................................................................................... 3-22

3.7 Instruction Execution Timing ....................................................................................... 3-27

3.7.1 MOVE Instruction Execution Timing ...................................................................... 3-28

3.7.2 One-Operand Instruction Execution Timing ............................................................ 3-30

3.7.3 Two-Operand Instruction Execution Timing ............................................................ 3-31

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Freescale Semiconductor ix

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3.7.4 Miscellaneous Instruction Execution Timing ........................................................... 3-32

3.7.5 Branch Instruction Execution Timing ....................................................................... 3-33

3.7.6 EMAC Instruction Execution Times ........................................................................ 3-34

3.7.7 FPU Instruction Execution Times ............................................................................. 3-35

3.8 Exception Processing Overview ................................................................................... 3-36

3.8.1 Exception Stack Frame Definition ............................................................................ 3-38

3.8.2 Processor Exceptions ................................................................................................ 3-39

3.9 Precise Faults ................................................................................................................ 3-42

Title

Page

Number

Chapter 4

Enhanced Multiply-Accumulate Unit (EMAC)

4.1 Introduction ..................................................................................................................... 4-1

4.1.1 MAC Overview ........................................................................................................... 4-2

4.1.2 General Operation ....................................................................................................... 4-2

4.2 Memory Map/Register Definition .................................................................................. 4-5

4.2.1 MAC Status Register (MACSR) ................................................................................. 4-5

4.2.1.1 Fractional Operation Mode ..................................................................................... 4-8

4.2.2 Mask Register (MASK) ............................................................................................ 4-10

4.3 EMAC Instruction Set Summary .................................................................................. 4-11

4.3.1 EMAC Instruction Execution Timing ....................................................................... 4-11

4.3.2 Data Representation .................................................................................................. 4-12

4.3.3 EMAC Opcodes ........................................................................................................ 4-13

Chapter 5

Memory Management Unit (MMU)

5.1 Features ........................................................................................................................... 5-1

5.2 Virtual Memory Management Architecture ................................................................... 5-1

5.2.1 MMU Architecture Features ....................................................................................... 5-1

5.2.2 MMU Architecture Location ...................................................................................... 5-2

5.2.3 MMU Architecture Implementation ........................................................................... 5-3

5.2.3.1 Precise Faults ..........................................................................................................5-4

5.2.3.2 MMU Access .......................................................................................................... 5-4

5.2.3.3 Virtual Mode ........................................................................................................... 5-4

5.2.3.4 Virtual Memory References ................................................................................... 5-4

5.2.3.5 Instruction and Data Cache Addresses ................................................................... 5-4

5.2.3.6 Supervisor/User Stack Pointers .............................................................................. 5-5

5.2.3.7 Access Error Stack Frame ...................................................................................... 5-5

5.2.3.8 Expanded Control Register Space .......................................................................... 5-5

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5.2.3.9 Changes to ACRs and CACR ................................................................................. 5-5

5.2.3.10 ACR Address Improvements .................................................................................. 5-6

5.2.3.11 Supervisor Protection .............................................................................................. 5-7

5.3 Debugging in a Virtual Environment .............................................................................. 5-7

5.4 Virtual Memory Architecture Processor Support ........................................................... 5-7

5.4.1 Precise Faults .............................................................................................................. 5-7

5.4.2 Supervisor/User Stack Pointers ................................................................................. 5-7

5.4.3 Access Error Stack Frame Additions .......................................................................... 5-8

5.5 MMU Definition ............................................................................................................. 5-9

5.5.1 Effective Address Attribute Determination ................................................................ 5-9

5.5.2 MMU Functionality .................................................................................................. 5-10

5.5.3 MMU Organization ................................................................................................... 5-10

5.5.3.1 MMU Base Address Register (MMUBAR) ......................................................... 5-10

5.5.3.2 MMU Memory Map ............................................................................................. 5-11

5.5.3.3 MMU Control Register (MMUCR) ..................................................................... 5-11

5.5.3.4 MMU Operation Register (MMUOR) .................................................................. 5-12

5.5.3.5 MMU Status Register (MMUSR) ......................................................................... 5-14

5.5.3.6 MMU Fault, Test, or TLB Address Register (MMUAR) ..................................... 5-15

5.5.3.7 MMU Read/Write Tag and Data Entry Registers (MMUTR and MMUDR) ...... 5-16

5.5.4 MMU TLB ................................................................................................................ 5-18

5.5.5 MMU Operation ....................................................................................................... 5-19

5.6 MMU Implementation .................................................................................................. 5-20

5.6.1 TLB Address Fields .................................................................................................. 5-20

5.6.2 TLB Replacement Algorithm ................................................................................... 5-21

5.6.3 TLB Locked Entries .................................................................................................. 5-22

5.7 MMU Instructions ......................................................................................................... 5-23

Chapter 6

Floating-Point Unit (FPU)

6.1 Introduction ..................................................................................................................... 6-1

6.1.1 Overview ..................................................................................................................... 6-1

6.1.1.1 Notational Conventions .......................................................................................... 6-1

6.2 Operand Data Formats and Types .................................................................................. 6-3

6.2.1 Signed-Integer Data Formats ...................................................................................... 6-3

6.2.2 Floating-Point Data Formats ....................................................................................... 6-3

6.2.3 Floating-Point Data Types .......................................................................................... 6-4

6.2.3.1 Normalized Numbers .............................................................................................. 6-4

6.2.3.2 Zeros ....................................................................................................................... 6-4

6.2.3.3 Infinities .................................................................................................................. 6-4

6.2.3.4 Not-A-Number ........................................................................................................ 6-5

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6.2.3.5 Denormalized Numbers .......................................................................................... 6-5

6.3 Register Definition .......................................................................................................... 6-7

6.3.1 Floating-Point Data Registers (FP0–FP7) .................................................................. 6-7

6.3.2 Floating-Point Control Register (FPCR) .................................................................... 6-7

6.3.3 Floating-Point Status Register (FPSR) ....................................................................... 6-9

6.3.4 Floating-Point Instruction Address Register (FPIAR) .............................................. 6-10

6.4 Floating-Point Computational Accuracy ...................................................................... 6-11

6.4.1 Intermediate Result ................................................................................................... 6-11

6.4.2 Rounding the Result .................................................................................................. 6-12

6.5 Floating-Point Post-Processing ..................................................................................... 6-14

6.5.1 Underflow, Round, and Overflow ............................................................................ 6-14

6.5.2 Conditional Testing ................................................................................................... 6-15

6.6 Floating-Point Exceptions ............................................................................................. 6-17

6.6.1 Floating-Point Arithmetic Exceptions ...................................................................... 6-18

6.6.1.1 Branch/Set on Unordered (BSUN) ....................................................................... 6-19

6.6.1.2 Input Not-A-Number (INAN) ............................................................................... 6-20

6.6.1.3 Input Denormalized Number (IDE) ...................................................................... 6-20

6.6.1.4 Operand Error (OPERR) ....................................................................................... 6-21

6.6.1.5 Overflow (OVFL) ................................................................................................. 6-21

6.6.1.6 Underflow (UNFL) ............................................................................................... 6-22

6.6.1.7 Divide-by-Zero (DZ) ............................................................................................ 6-22

6.6.1.8 Inexact Result (INEX) .......................................................................................... 6-23

6.6.2 Floating-Point State Frames ...................................................................................... 6-23

6.7 Instructions .................................................................................................................... 6-25

6.7.1 Floating-Point Instruction Overview ........................................................................ 6-25

6.7.2 Floating-Point Instruction Execution Timing ........................................................... 6-27

6.7.3 Key Differences between ColdFire and M68000 FPU Programming Models ......... 6-28

Chapter 7

Local Memory

7.1 Interactions between Local Memory Modules ............................................................... 7-1

7.2 SRAM Overview ............................................................................................................ 7-1

7.3 SRAM Operation ............................................................................................................ 7-2

7.4 SRAM Register Definition ............................................................................................. 7-2

7.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1) ....................................... 7-2

7.5 SRAM Initialization ........................................................................................................ 7-4

7.5.1 SRAM Initialization Code .......................................................................................... 7-5

7.6 Power Management ........................................................................................................ 7-6

7.7 Cache Overview ..............................................................................................................7-6

7.8 Cache Organization ......................................................................................................... 7-7

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7.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified ......................... 7-8

7.8.2 The Cache at Start-Up ................................................................................................. 7-8

7.9 Cache Operation ........................................................................................................... 7-10

7.9.1 Caching Modes ......................................................................................................... 7-12

7.9.1.1 Cacheable Accesses .............................................................................................. 7-12

7.9.1.2 Cache-Inhibited Accesses ..................................................................................... 7-13

7.9.2 Cache Protocol .......................................................................................................... 7-14

7.9.2.1 Read Miss ............................................................................................................. 7-14

7.9.2.2 Write Miss (Data Cache Only) ............................................................................. 7-14

7.9.2.3 Read Hit ................................................................................................................7-15

7.9.2.4 Write Hit (Data Cache Only) ................................................................................ 7-15

7.9.3 Cache Coherency (Data Cache Only) ....................................................................... 7-15

7.9.4 Memory Accesses for Cache Maintenance ............................................................... 7-15

7.9.4.1 Cache Filling ......................................................................................................... 7-15

7.9.4.2 Cache Pushes ........................................................................................................ 7-16

7.9.5 Cache Locking .......................................................................................................... 7-17

7.10 Cache Register Definition ............................................................................................. 7-19

7.10.1 Cache Control Register (CACR) .............................................................................. 7-19

7.10.2 Access Control Registers (ACR0–ACR3) ................................................................ 7-22

7.11 Cache Management ....................................................................................................... 7-23

7.12 Cache Operation Summary ........................................................................................... 7-26

7.12.1 Instruction Cache State Transitions .......................................................................... 7-26

7.12.2 Data Cache State Transitions .................................................................................... 7-27

7.13 Cache Initialization Code .............................................................................................. 7-30

Chapter 8

Debug Support

8.1 Introduction ..................................................................................................................... 8-1

8.1.1 Overview ..................................................................................................................... 8-1

8.2 Signal Descriptions .........................................................................................................8-2

8.2.1 Processor Status/Debug Data (PSTDDATA[7:0]) ..................................................... 8-3

8.3 Real-Time Trace Support ................................................................................................ 8-5

8.3.1 Begin Execution of Taken Branch (PST = 0x5) ......................................................... 8-6

8.3.2 Processor Stopped or Breakpoint State Change (PST = 0xE) .................................... 8-7

8.3.3 Processor Halted (PST = 0xF) .................................................................................... 8-8

8.4 Memory Map/Register Definition .................................................................................. 8-9

8.4.1 Revision A Shared Debug Resources ....................................................................... 8-11

8.4.2 Configuration/Status Register (CSR) ........................................................................ 8-11

8.4.3 PC Breakpoint ASID Control Register (PBAC) ....................................................... 8-14

8.4.4 BDM Address Attribute Register (BAAR) ............................................................... 8-15

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8.4.5 Address Attribute Trigger Registers (AATR, AATR1) ............................................ 8-16

8.4.6 Trigger Definition Register (TDR) ........................................................................... 8-17

8.4.7 Program Counter Breakpoint and Mask Registers (PBRn, PBMR) ......................... 8-20

8.4.8 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) ........................... 8-21

8.4.9 Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1) .................... 8-22

8.4.10 PC Breakpoint ASID Register (PBASID) ................................................................ 8-24

8.4.11 Extended Trigger Definition Register (XTDR) ........................................................ 8-25

8.4.11.1 Resulting Set of Possible Trigger Combinations .................................................. 8-27

8.5 Background Debug Mode (BDM) ................................................................................ 8-28

8.5.1 CPU Halt ................................................................................................................... 8-28

8.5.2 BDM Serial Interface ................................................................................................ 8-30

8.5.2.1 Receive Packet Format ......................................................................................... 8-30

8.5.2.2 Transmit Packet Format ........................................................................................ 8-31

8.5.3 BDM Command Set .................................................................................................. 8-31

8.5.3.1 ColdFire BDM Command Format ........................................................................ 8-33

8.5.3.2 Command Sequence Diagrams ............................................................................. 8-33

8.5.3.3 Command Set Descriptions .................................................................................. 8-35

8.6 Real-Time Debug Support ............................................................................................ 8-51

8.6.1 Theory of Operation .................................................................................................. 8-51

8.6.1.1 Emulator Mode ..................................................................................................... 8-53

8.6.2 Concurrent BDM and Processor Operation .............................................................. 8-53

8.7 Debug C Definition of PSTDDATA Outputs .............................................................. 8-54

8.7.1 User Instruction Set .................................................................................................. 8-54

8.7.2 Supervisor Instruction Set ......................................................................................... 8-60

8.8 ColdFire Debug History ................................................................................................ 8-61

8.8.1 ColdFire Debug Classic: The Original Definition .................................................... 8-61

8.8.2 ColdFire Debug Revision B ...................................................................................... 8-62

8.8.3 ColdFire Debug Revision C ...................................................................................... 8-62

8.8.3.1 Debug Interrupts and Interrupt Requests (Emulator Mode) ................................. 8-62

8.9 Freescale-Recommended BDM Pinout ........................................................................ 8-63

Chapter 9

System Integration Unit (SIU)

9.1 Introduction ..................................................................................................................... 9-1

9.2 Features ........................................................................................................................... 9-1

9.3 Memory Map/Register Definition .................................................................................. 9-1

9.3.1 Module Base Address Register (MBAR) ................................................................... 9-2

9.3.1.1 System Breakpoint Control Register (SBCR) ........................................................ 9-3

9.3.1.2 SEC Sequential Access Control Register (SECSACR) ......................................... 9-4

9.3.1.3 Reset Status Register (RSR) ................................................................................... 9-5

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9.3.1.4 JTAG Device Identification Number (JTAGID) .................................................... 9-5

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Chapter 10

Internal Clocks and Bus Architecture

10.1 Introduction ................................................................................................................... 10-1

10.1.1 Block Diagram .......................................................................................................... 10-1

10.1.2 Clocking Overview ................................................................................................... 10-2

10.1.3 Internal Bus Overview .............................................................................................. 10-2

10.1.4 XL Bus Features ....................................................................................................... 10-3

10.1.5 Internal Bus Transaction Summaries ........................................................................ 10-3

10.1.6 XL Bus Interface Operations .................................................................................... 10-3

10.1.6.1 Basic Transfer Protocol ........................................................................................ 10-3

10.1.6.2 Address Pipelines .................................................................................................. 10-4

10.2 PLL ............................................................................................................................... 10-5

10.2.1 PLL Memory Map/Register Descriptions ................................................................. 10-5

10.2.2 System PLL Control Register (SPCR) ..................................................................... 10-5

10.3 XL Bus Arbiter ............................................................................................................. 10-6

10.3.1 Features ..................................................................................................................... 10-6

10.3.2 Arbiter Functional Description ................................................................................. 10-6

10.3.2.1 Prioritization ......................................................................................................... 10-6

10.3.2.2 Bus Grant Mechanism .......................................................................................... 10-7

10.3.2.3 Watchdog Functions ............................................................................................. 10-8

10.3.3 XLB Arbiter Register Descriptions .......................................................................... 10-8

10.3.3.1 Arbiter Configuration Register (XARB_CFG) .................................................... 10-9

10.3.3.2 Arbiter Version Register (XARB_VER) ............................................................ 10-10

10.3.3.3 Arbiter Status Register (XARB_SR) .................................................................. 10-11

10.3.3.4 Arbiter Interrupt Mask Register (XARB_IMR) ................................................. 10-11

10.3.3.5 Arbiter Address Capture Register (XARB_ADRCAP) ...................................... 10-13

10.3.3.6 Arbiter Bus Signal Capture Register (XARB_SIGCAP) ................................... 10-13

10.3.3.7 Arbiter Address Tenure Time Out Register (XARB_ADRTO) ......................... 10-14

10.3.3.8 Arbiter Data Tenure Time Out Register (XARB_DATTO) ............................... 10-15

10.3.3.9 Arbiter Bus Activity Time Out Register (XARB_BUSTO) ............................... 10-16

10.3.3.10 Arbiter Master Priority Enable Register (XARB_PRIEN) ................................. 10-16

10.3.3.11 Arbiter Master Priority Register (XARB_PRI) .................................................. 10-17

Chapter 11

General Purpose Timers (GPT)

11.1 Introduction ................................................................................................................... 11-1

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11.1.1 Overview ................................................................................................................... 11-1

11.1.2 Modes of Operation .................................................................................................. 11-1

11.2 External Signals ............................................................................................................ 11-2

11.3 Memory Map/Register Definition ................................................................................ 11-2

11.3.1 GPT Enable and Mode Select Register (GMSn) ...................................................... 11-3

11.3.2 GPT Counter Input Register (GCIRn) ...................................................................... 11-5

11.3.3 GPT PWM Configuration Register (GPWMn) ........................................................ 11-6

11.3.4 GPT Status Register (GSRn) .................................................................................... 11-7

11.4 Functional Description .................................................................................................. 11-8

11.4.1 Timer Configuration Method .................................................................................... 11-8

11.4.2 Programming Notes .................................................................................................. 11-8

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Chapter 12

Slice Timers (SLT)

12.1 Introduction ................................................................................................................... 12-1

12.1.1 Overview ................................................................................................................... 12-1

12.2 Memory Map/Register Definition ................................................................................ 12-1

12.2.1 SLT Terminal Count Register (STCNTn) ................................................................ 12-2

12.2.2 SLT Control Register (SCRn) ................................................................................... 12-2

12.2.3 SLT Timer Count Register (SCNTn) ........................................................................ 12-3

12.2.4 SLT Status Register (SSRn) ..................................................................................... 12-4

Chapter 13

Interrupt Controller

13.1 Introduction ................................................................................................................... 13-1

13.1.1 68K/ColdFire Interrupt Architecture Overview ....................................................... 13-1

13.1.1.1 Interrupt Controller Theory of Operation ............................................................. 13-2

13.2 Memory Map/Register Descriptions ............................................................................. 13-4

13.2.1 Register Descriptions ................................................................................................ 13-5

13.2.1.1 Interrupt Pending Registers (IPRH, IPRL) ........................................................... 13-5

13.2.1.2 Interrupt Mask Register (IMRH, IMRL) .............................................................. 13-7

13.2.1.3 Interrupt Force Registers (INTFRCH, INTFRCL) ............................................... 13-8

13.2.1.4 Interrupt Request Level Register (IRLR) ........................................................... 13-10

13.2.1.5 Interrupt Acknowledge Level and Priority Register (IACKLPR) ...................... 13-10

13.2.1.6 Interrupt Control Registers 1–63 (ICRn) ............................................................ 13-11

13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) ......... 13-13

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Chapter 14

Edge Port Module (EPORT)

14.1 Introduction ................................................................................................................... 14-1

14.2 Interrupt/General-Purpose I/O Pin Descriptions ........................................................... 14-1

14.3 Memory Map/Register Definition ................................................................................ 14-2

14.3.1 Memory Map ............................................................................................................ 14-2

14.3.2 Register Descriptions ................................................................................................ 14-2

14.3.2.1 EPORT Pin Assignment Register (EPPAR) ......................................................... 14-3

14.3.2.2 EPORT Data Direction Register (EPDDR) .......................................................... 14-3

14.3.2.3 Edge Port Interrupt Enable Register (EPIER) ...................................................... 14-4

14.3.2.4 Edge Port Data Register (EPDR) .......................................................................... 14-4

14.3.2.5 Edge Port Pin Data Register (EPPDR) ................................................................. 14-5

14.3.2.6 Edge Port Flag Register (EPFR) ........................................................................... 14-5

Chapter 15

GPIO

15.1 Introduction ................................................................................................................... 15-1

15.1.1 Overview ................................................................................................................... 15-2

15.1.2 Features ..................................................................................................................... 15-3

15.2 External Pin Description ............................................................................................... 15-3

15.3 Memory Map/Register Definition ................................................................................ 15-7

15.3.1 Register Overview .................................................................................................... 15-7

15.3.2 Register Descriptions ................................................................................................ 15-8

15.3.2.1 Port x Output Data Registers (PODR_x) .............................................................. 15-8

15.3.2.2 Port

15.3.2.3 Port x Pin Data/Set Data Registers (PPDSDR_x) ............................................. 15-14

15.3.2.4 Port x Clear Output Data Registers (PCLRR_x) ................................................ 15-18

15.3.2.5 Port x Pin Assignment Registers (PAR_x) ......................................................... 15-21

15.3.2.6 FlexBus Chip Select Pin Assignment Register (PAR_FBCS) ........................... 15-22

15.3.2.7 DMA Pin Assignment Register (PAR_DMA) ................................................... 15-23

15.3.2.8 FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ) ........................... 15-23

15.3.2.9 PCI Grant Pin Assignment Register (PAR_PCIBG) .......................................... 15-25

15.3.2.10 PCI Request Pin Assignment Register (PAR_PCIBR) ...................................... 15-26

15.3.2.11 PSC3 Pin Assignment Register (PAR_PSC3) .................................................... 15-27

15.3.2.12 PSC2 Pin Assignment Register (PAR_PSC2) .................................................... 15-28

15.3.2.13 PSC1 Pin Assignment Register (PAR_PSC1) .................................................... 15-28

15.3.2.14 PSC0 Pin Assignment Register (PAR_PSC0) .................................................... 15-29

15.3.2.15 DSPI Pin Assignment Register (PAR_DSPI) ..................................................... 15-30

15.3.2.16 General Purpose Timer Pin Assignment Register (PAR_TIMER) .................... 15-31

x Data Direction Registers (PDDR_x) ........................................................ 15-11

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15.4 Functional Description ................................................................................................ 15-32

15.4.1 Overview ................................................................................................................. 15-32

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Chapter 16

32-Kbyte System SRAM

16.1 Introduction ................................................................................................................... 16-1

16.1.1 Block Diagram .......................................................................................................... 16-1

16.1.2 Features ..................................................................................................................... 16-2

16.1.3 Overview ................................................................................................................... 16-2

16.2 Memory Map/Register Definition ................................................................................ 16-2

16.2.1 System SRAM Configuration Register (SSCR) ....................................................... 16-3

16.2.2 Transfer Count Configuration Register (TCCR) ..................................................... 16-4

16.2.3 Transfer Count Configuration Register—DMA Read Channel (TCCRDR) ............ 16-5

16.2.4 Transfer Count Configuration Register—DMA Write Channel (TCCRDW) .......... 16-6

16.2.5 Transfer Count Configuration Register—SEC (TCCRSEC) .................................... 16-7

16.3 Functional Description .................................................................................................. 16-8

Chapter 17

FlexBus

17.1 Introduction ................................................................................................................... 17-1

17.1.1 Overview ................................................................................................................... 17-1

17.1.2 Features ..................................................................................................................... 17-1

17.1.3 Modes of Operation .................................................................................................. 17-1

17.2 Byte Lanes .................................................................................................................... 17-2

17.3 Address Latch ............................................................................................................... 17-2

17.4 External Signals ............................................................................................................ 17-3

17.4.1 Chip-Select (FBCS

17.4.2 Address/Data Bus (AD[31:0]) .................................................................................. 17-4

17.4.3 Address Latch Enable (ALE) .................................................................................... 17-4

17.4.4 Read/Write (R/W) ..................................................................................................... 17-4

17.4.5 Transfer Burst (TBST

17.4.6 Transfer Size (TSIZ[1:0]) ......................................................................................... 17-4

17.4.7 Byte Selects (BE

17.4.8 Output Enable (OE

17.4.9 Transfer Acknowledge (TA

17.5 Chip-Select Operation ................................................................................................... 17-6

17.5.1 General Chip-Select Operation ................................................................................. 17-6

17.5.1.1 8-, 16-, and 32-Bit Port Sizing .............................................................................. 17-6

[5:0]) .......................................................................................... 17-4

) .............................................................................................. 17-4

/BWE[3:0]) .................................................................................... 17-5

) .................................................................................................. 17-5

) ..................................................................................... 17-5

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17.5.1.2 Global Chip-Select Operation ............................................................................... 17-6

17.5.2 Chip-Select Registers ................................................................................................ 17-7

17.5.2.1 Chip-Select Address Registers (CSAR0–CSAR5) ............................................... 17-8

17.5.2.2 Chip-Select Mask Registers (CSMR0–CSMR5) .................................................. 17-9

17.5.2.3 Chip-Select Control Registers (CSCR0–CSCR5) .............................................. 17-10

17.6 Functional Description ................................................................................................ 17-12

17.6.1 Data Transfer Operation ......................................................................................... 17-12

17.6.2 Data Byte Alignment and Physical Connections .................................................... 17-12

17.6.3 Address/Data Bus Multiplexing .............................................................................. 17-13

17.6.4 Bus Cycle Execution ............................................................................................... 17-13

17.6.4.1 Data Transfer Cycle States ................................................................................. 17-14

17.6.5 FlexBus Timing Examples ...................................................................................... 17-15

17.6.5.1 Basic Read Bus Cycle ......................................................................................... 17-15

17.6.5.2 Basic Write Bus Cycle ........................................................................................ 17-16

17.6.5.3 Bus Cycle Multiplexing ...................................................................................... 17-17

17.6.5.4 Timing Variations ............................................................................................... 17-21

17.6.6 Burst Cycles ............................................................................................................ 17-26

17.6.7 Misaligned Operands .............................................................................................. 17-31

17.6.8 Bus Errors ............................................................................................................... 17-32

Chapter 18

SDRAM Controller (SDRAMC)

18.1 Introduction ................................................................................................................... 18-1

18.2 Overview ....................................................................................................................... 18-1

18.2.1 Features ..................................................................................................................... 18-1

18.2.2 Terminology .............................................................................................................. 18-1

18.2.3 Block Diagram .......................................................................................................... 18-2

18.3 External Signal Description .......................................................................................... 18-2

18.3.1 SDRAM Data Bus (SDDATA[31:0]) ....................................................................... 18-2

18.3.2 SDRAM Address Bus (SDADDR[12:0]) ................................................................. 18-2

18.3.3 SDRAM Bank Addresses (SDBA[1:0]) ................................................................... 18-2

18.3.4 SDRAM Row Address Strobe (RAS) ....................................................................... 18-3

18.3.5 SDRAM Column Address Strobe (CAS

18.3.6 SDRAM Chip Selects (SDCS

[3:0]) .......................................................................... 18-3

18.3.7 SDRAM Write Data Byte Mask (SDDM[3:0]) ........................................................ 18-3

18.3.8 SDRAM Data Strobe (SDDQS[3:0]) ........................................................................ 18-3

18.3.9 SDRAM Clock (SDCLK[1:0]) ................................................................................. 18-3

18.3.10 Inverted SDRAM Clock (SDCLK[1:0]) ................................................................... 18-3

18.3.11 SDRAM Write Enable (SDWE

) ............................................................................... 18-3

18.3.12 SDRAM Clock Enable (SDCKE) ............................................................................. 18-4

) ................................................................. 18-3

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18.3.13 SDR SDRAM Data Strobe (SDRDQS) .................................................................... 18-4

18.3.14 SDRAM Memory Supply (SDVDD) ........................................................................ 18-4

18.3.15 SDRAM Reference Voltage (VREF) ....................................................................... 18-4

18.4 Interface Recommendations ......................................................................................... 18-4

18.4.1 Supported Memory Configurations .......................................................................... 18-4

18.4.2 SDRAM SDR Connections ...................................................................................... 18-6

18.4.3 SDRAM DDR Component Connections .................................................................. 18-6

18.4.4 SDRAM DDR DIMM Connections ......................................................................... 18-7

18.4.5 DDR SDRAM Layout Considerations ..................................................................... 18-8

18.4.5.1 Termination Example ........................................................................................... 18-9

18.5 SDRAM Overview ....................................................................................................... 18-9

18.5.1 SDRAM Commands ................................................................................................. 18-9

18.5.1.1 Row and Bank Active Command (ACTV) ......................................................... 18-10

18.5.1.2 Read Command (READ) .................................................................................... 18-10

18.5.1.3 Write Command (WRITE) ................................................................................. 18-10

18.5.1.4 Precharge All Banks Command (PALL) ............................................................ 18-11

18.5.1.5 Load Mode/Extended Mode Register Command (LMR, LEMR) ...................... 18-11

18.5.1.6 Auto Refresh Command (REF) .......................................................................... 18-13

18.5.1.7 Self-Refresh (SREF) and Power-Down (PDWN) Commands ........................... 18-13

18.5.2 Power-Up Initialization ........................................................................................... 18-13

18.5.2.1 SDR Initialization ............................................................................................... 18-14

18.5.2.2 DDR Initialization .............................................................................................. 18-14

18.6 Functional Overview ................................................................................................... 18-15

18.6.1 Page Management ................................................................................................... 18-15

18.6.2 Transfer Size ........................................................................................................... 18-15

18.7 Memory Map/Register Definition .............................................................................. 18-16

18.7.1 SDRAM Drive Strength Register (SDRAMDS) .................................................... 18-17

18.7.2 SDRAM Chip Select Configuration Registers (CSnCFG) ..................................... 18-18

18.7.3 SDRAM Mode/Extended Mode Register (SDMR) ................................................ 18-19

18.7.4 SDRAM Control Register (SDCR) ......................................................................... 18-20

18.7.5 SDRAM Configuration Register 1 (SDCFG1) ....................................................... 18-21

18.7.6 SDRAM Configuration Register 2 (SDCFG2) ....................................................... 18-23

18.8 SDRAM Example ....................................................................................................... 18-24

18.8.1 SDRAM Signal Drive Strength Settings ................................................................ 18-25

18.8.2 SDRAM Chip Select Settings ................................................................................. 18-25

18.8.3 SDRAM Configuration 1 Register Settings ............................................................ 18-26

18.8.4 SDRAM Configuration 2 Register Settings ............................................................ 18-27

18.8.5 SDRAM Control Register Settings and PALL command ...................................... 18-27

18.8.6 Set the Extended Mode Register ............................................................................. 18-29

18.8.7 Set the Mode Register and Reset DLL ................................................................... 18-29

18.8.8 Issue a PALL command .......................................................................................... 18-30

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18.8.9 Perform Two Refresh Cycles .................................................................................. 18-31

18.8.10 Clear the Reset DLL Bit in the Mode Register ...................................................... 18-32

18.8.11 Enable Automatic Refresh and Lock Mode Register ............................................ 18-33

18.8.12 Initialization Code ................................................................................................... 18-34

Chapter 19

PCI Bus Controller

19.1 Introduction ................................................................................................................... 19-1

19.1.1 Block Diagram .......................................................................................................... 19-1

19.1.2 Overview ................................................................................................................... 19-1

19.1.3 Features ..................................................................................................................... 19-1

19.2 External Signal Description .......................................................................................... 19-2

19.2.1 Address/Data Bus (PCIAD[31:0]) ............................................................................ 19-2

19.2.2 Command/Byte Enables (PCICXBE[3:0]) ............................................................... 19-2

19.2.3 Device Select (PCIDEVSEL) ................................................................................... 19-3

19.2.4 Frame (PCIFRAME) ................................................................................................. 19-3

19.2.5 Initialization Device Select (PCIIDSEL) .................................................................. 19-3

19.2.6 Initiator Ready (PCIIRDY) ....................................................................................... 19-3

19.2.7 Parity (PCIPAR) ....................................................................................................... 19-3

19.2.8 PCI Clock (CLKIN) .................................................................................................. 19-3

19.2.9 Parity Error (PCIPERR) ............................................................................................ 19-3

19.2.10 Reset (PCIRESET) .................................................................................................. 19-3

19.2.11 System Error (PCISERR) ........................................................................................ 19-3

19.2.12 Stop (PCISTOP) ...................................................................................................... 19-3

19.2.13 Target Ready (PCITRDY) ....................................................................................... 19-4

19.3 Memory Map/Register Definition ................................................................................ 19-4

19.3.1 PCI Type 0 Configuration Registers ......................................................................... 19-6

19.3.1.1 Device ID/Vendor ID Register (PCIIDR)—PCI Dword Addr 0 .......................... 19-7

19.3.1.2 PCI Status/Command Register (PCISCR)—PCI Dword Addr 1 ......................... 19-7

19.3.1.3 Revision ID/Class Code Register (PCICCRIR)—PCI Dword 3 .......................... 19-9

19.3.1.4 Configuration 1 Register (PCICR1)—PCI Dword 3 .......................................... 19-10

19.3.1.5 Base Address Register 0 (PCIBAR0)—PCI Dword 4 ........................................ 19-11

19.3.1.6 Base Address Register 1 (PCIBAR1)—PCI Dword 5 ........................................ 19-12

19.3.1.7 CardBus CIS Pointer Register PCICCPR—PCI Dword A ................................ 19-12

19.3.1.8 Subsystem ID/Subsystem Vendor ID Registers PCISID—PCI Dword B .......... 19-12

19.3.1.9 Expansion ROM Base Address PCIERBAR—PCI Dword C ............................ 19-13

19.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR—PCI Dword D ................................... 19-13

19.3.1.11 Configuration 2 Register (PCICR2)—PCI Dword F .......................................... 19-13

19.3.2 General Control/Status Registers ............................................................................ 19-13

19.3.2.1 Global Status/Control Register (PCIGSCR) ....................................................... 19-14

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19.3.2.2 Target Base Address Translation Register 0 (PCITBATR0) ............................. 19-15

19.3.2.3 Target Base Address Translation Register 1 (PCITBATR1) ............................. 19-16

19.3.2.4 Target Control Register (PCITCR) ..................................................................... 19-16

19.3.2.5 Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR) ......... 19-17

19.3.2.6 Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR) ......... 19-18

19.3.2.7 Initiator Window 2 Base/Translation Address Register (PCIIW2BTAR) ......... 19-19

19.3.2.8 Initiator Window Configuration Register (PCIIWCR) ....................................... 19-19

19.3.2.9 Initiator Control Register (PCIICR) ................................................................... 19-20

19.3.2.10 Initiator Status Register (PCIISR) ...................................................................... 19-21

19.3.2.11 Configuration Address Register (PCICAR) ....................................................... 19-22

19.3.3 Communication Subsystem Interface Registers ..................................................... 19-23

19.3.3.1 Comm Bus FIFO Transmit Interface .................................................................. 19-23

19.3.3.2 Comm Bus FIFO Receive Interface ................................................................... 19-35

19.4 Functional Description ................................................................................................ 19-48

19.4.1 PCI Bus Protocol .................................................................................................... 19-48

19.4.1.1 PCI Bus Background .......................................................................................... 19-48

19.4.1.2 Basic Transfer Control ........................................................................................ 19-49

19.4.1.3 PCI Transactions ................................................................................................. 19-49

19.4.1.4 PCI Bus Commands ............................................................................................ 19-51

19.4.1.5 Addressing .......................................................................................................... 19-52

19.4.2 Initiator Arbitration ................................................................................................. 19-55

19.4.2.1 Priority Scheme .................................................................................................. 19-56

19.4.3 Configuration Interface ........................................................................................... 19-56

19.4.4 XL Bus Initiator Interface ....................................................................................... 19-56

19.4.4.1 Endian Translation .............................................................................................. 19-58

19.4.4.2 Configuration Mechanism .................................................................................. 19-60

19.4.4.3 Interrupt Acknowledge Transactions .................................................................. 19-62

19.4.4.4 Special Cycle Transactions ................................................................................. 19-62

19.4.4.5 Transaction Termination ..................................................................................... 19-63

19.4.5 XL Bus Target Interface ........................................................................................ 19-63

19.4.5.1 Reads from Local Memory ................................................................................. 19-64

19.4.5.2 Local Memory Writes ......................................................................................... 19-64

19.4.5.3 Data Translation .................................................................................................. 19-64

19.4.5.4 Target Abort ........................................................................................................ 19-66

19.4.5.5 Latrule Disable .................................................................................................... 19-66

19.4.6 Communication Subsystem Initiator Interface ....................................................... 19-66

19.4.6.1 Access Width ...................................................................................................... 19-67

19.4.6.2 Addressing .......................................................................................................... 19-67

19.4.6.3 Data Translation .................................................................................................. 19-68

19.4.6.4 Initialization ........................................................................................................ 19-68

19.4.6.5 Restart and Reset ................................................................................................ 19-68

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19.4.6.6 PCI Commands ................................................................................................... 19-69

19.4.6.7 FIFO Considerations ........................................................................................... 19-69

19.4.6.8 Alarms ................................................................................................................. 19-69

19.4.6.9 Bus Errors ........................................................................................................... 19-70

19.4.7 PCI Clock Scheme .................................................................................................. 19-70

19.4.8 Interrupts ................................................................................................................. 19-70

19.4.8.1 PCI Bus Interrupts .............................................................................................. 19-70

19.4.8.2 Internal Interrupt ................................................................................................. 19-70

19.5 Application Information ............................................................................................. 19-70

19.5.1 XL Bus-Initiated Transaction Mapping .................................................................. 19-70

19.5.2 Address Maps ......................................................................................................... 19-71

19.5.2.1 Address Translation ............................................................................................ 19-72

19.6 XL Bus Arbitration Priority ........................................................................................ 19-75

Chapter 20

PCI Bus Arbiter Module

20.1 Introduction ................................................................................................................... 20-1

20.1.1 Block Diagram .......................................................................................................... 20-1

20.1.2 Overview ................................................................................................................... 20-1

20.1.3 Features ..................................................................................................................... 20-2

20.2 External Signal Description .......................................................................................... 20-2

20.2.1 Frame (PCIFRM) ...................................................................................................... 20-2

20.2.2 Initiator Ready (PCIIRDY) ....................................................................................... 20-2

20.2.3 PCI Clock (CLKIN) .................................................................................................. 20-2

20.2.4 External Bus Grant (PCIBG[4:1]) ............................................................................ 20-2

20.2.5 External Bus Grant/Request Output (PCIBG0

/PCIREQOUT) ................................ 20-3

20.2.6 External Bus Request (PCIBR[4:1]) ......................................................................... 20-3

20.2.7 External Request/Grant Input (PCIBR0/PCIGNTIN) .............................................. 20-3

20.3 Register Definition ........................................................................................................ 20-3

20.3.1 PCI Arbiter Control Register (PACR) ...................................................................... 20-3

20.3.2 PCI Arbiter Status Register (PASR) ......................................................................... 20-5

20.4 Functional Description .................................................................................................. 20-5

20.4.1 External PCI Requests .............................................................................................. 20-5

20.4.2 Arbitration ................................................................................................................. 20-6

20.4.2.1 Hidden Bus Arbitration ......................................................................................... 20-6

20.4.2.2 Arbitration Scheme ............................................................................................... 20-6

20.4.2.3 Arbitration Latency ............................................................................................... 20-7

20.4.2.4 Arbitration Examples ............................................................................................ 20-7

20.4.3 Master Time-Out ....................................................................................................... 20-9

20.5 Reset ............................................................................................................................ 20-10

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20.6 Interrupts ..................................................................................................................... 20-10

Chapter 21

FlexCAN

21.1 Introduction ................................................................................................................... 21-1

21.1.1 Block Diagram .......................................................................................................... 21-1

21.1.2 The CAN System ...................................................................................................... 21-2

21.1.3 Features ..................................................................................................................... 21-3

21.1.4 Modes of Operation .................................................................................................. 21-3

21.1.4.1 Normal Mode ........................................................................................................ 21-3

21.1.4.2 Freeze Mode ......................................................................................................... 21-3

21.1.4.3 Module Disabled Mode ........................................................................................ 21-4

21.1.4.4 Loop-Back Mode .................................................................................................. 21-4

21.1.4.5 Listen-Only Mode ................................................................................................. 21-4

21.2 External Signals ............................................................................................................ 21-5

21.2.1 CANTX[1:0] ............................................................................................................. 21-5

21.2.2 CANRX[1:0] ............................................................................................................. 21-5

21.3 Memory Map/Register Definition ................................................................................ 21-5

21.3.1 FlexCAN Memory Map ............................................................................................ 21-5

21.3.2 Register Descriptions ................................................................................................ 21-6

21.3.2.1 FlexCAN Module Configuration Register (CANMCR) ....................................... 21-6

21.3.2.2 FlexCAN Control Register (CANCTRL) ............................................................. 21-8

21.3.2.3 FlexCAN Timer Register (TIMER) .................................................................... 21-10

21.3.2.4 Rx Mask Registers .............................................................................................. 21-11

21.3.2.5 FlexCAN Error Counter Register (ERRCNT) .................................................... 21-14

21.3.2.6 FlexCAN Error and Status Register (ERRSTAT) .............................................. 21-15

21.3.2.7 Interrupt Mask Register (IMASK) ...................................................................... 21-17

21.3.2.8 Interrupt Flag Register (IFLAG) ........................................................................ 21-18

21.4 Functional Overview ................................................................................................... 21-19

21.4.1 Message Buffer Structure ....................................................................................... 21-19

21.4.2 Message Buffer Memory Map ................................................................................ 21-22

21.4.3 Transmit Process ..................................................................................................... 21-23

21.4.4 Arbitration Process ................................................................................................. 21-24

21.4.5 Receive Process ...................................................................................................... 21-24

21.4.5.1 Self-Received Frames ......................................................................................... 21-25

21.4.6 Message Buffer Handling ....................................................................................... 21-25

21.4.6.1 Serial Message Buffers (SMBs) ......................................................................... 21-26

21.4.6.2 Transmit Message Buffer Deactivation .............................................................. 21-26

21.4.6.3 Receive Message Buffer Deactivation ................................................................ 21-26

21.4.6.4 Locking and Releasing Message Buffers ........................................................... 21-27

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21.4.7 CAN Protocol Related Frames ............................................................................... 21-27

21.4.7.1 Remote Frames ................................................................................................... 21-27

21.4.7.2 Overload Frames ................................................................................................. 21-28

21.4.8 Time Stamp ............................................................................................................. 21-28

21.4.9 Bit Timing ............................................................................................................... 21-28

21.4.9.1 Configuring the FlexCAN Bit Timing ................................................................ 21-29

21.4.10 FlexCAN Error Counters ....................................................................................... 21-30

21.5 FlexCAN Initialization Sequence ............................................................................... 21-31

21.5.1 Interrupts ................................................................................................................. 21-31

Chapter 22

Integrated Security Engine (SEC)

22.1 Features ......................................................................................................................... 22-1

22.2 ColdFire Security Architecture ..................................................................................... 22-1

22.3 Block Diagram .............................................................................................................. 22-2

22.4 Overview ....................................................................................................................... 22-2

22.4.1 Bus Interface ............................................................................................................. 22-2

22.4.2 SEC Controller Unit .................................................................................................. 22-3

22.4.2.1 Static EU Access ................................................................................................... 22-3

22.4.2.2 Dynamic EU Access ............................................................................................. 22-3

22.4.3 Crypto-Channels ....................................................................................................... 22-3

22.4.4 Execution Units (EUs) .............................................................................................. 22-4

22.4.4.1 Data Encryption Standard Execution Unit (DEU) ................................................ 22-4

22.4.4.2 Arc Four Execution Unit (AFEU) ........................................................................ 22-5

22.4.4.3 Advanced Encryption Standard Execution Unit (AESU) ..................................... 22-6

22.4.4.4 Message Digest Execution Unit (MDEU) ............................................................ 22-6

22.4.4.5 Random Number Generator (RNG) ...................................................................... 22-8

22.5 Memory Map/Register Definition ................................................................................ 22-8

22.6 Controller .................................................................................................................... 22-10

22.6.1 EU Access ............................................................................................................... 22-11

22.6.2 Multiple EU Assignment ........................................................................................ 22-11

22.6.3 Multiple Channels ................................................................................................... 22-11

22.6.4 Controller Registers ................................................................................................ 22-11

22.6.4.1 EU Assignment Control Registers (EUACRH and EUACRL) .......................... 22-11

22.6.4.2 EU Assignment Status Registers (EUASRH and EUASRL) ............................. 22-13

22.6.4.3 SEC Interrupt Mask Registers (SIMRH and SIMRL) ........................................ 22-14

22.6.4.4 SEC Interrupt Status Registers (SISRH and SISRL) .......................................... 22-14

22.6.4.5 SEC Interrupt Control Registers (SICRH and SICRL) ...................................... 22-14

22.6.4.6 SEC ID Register (SIDR) ..................................................................................... 22-16

22.6.4.7 SEC Master Control Register (SMCR) ............................................................... 22-17

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22.6.4.8 Master Error Address Register (MEAR) ............................................................ 22-18

22.7 Channels ...................................................................................................................... 22-18

22.7.1 Crypto-Channel Registers ....................................................................................... 22-19

22.7.1.1 Crypto-Channel Configuration Registers (CCCRn) ........................................... 22-19

22.7.1.2 Crypto-Channel Pointer Status Registers (CCPSRHn and CCPSRLn) .............. 22-21

22.7.1.3 Crypto-Channel Current Descriptor Pointer Register (CDPRn) ........................ 22-27

22.7.1.4 Fetch Register (FRn) ........................................................................................... 22-27

22.7.1.5 Data Packet Descriptor Buffer (CDBUFn) ......................................................... 22-28

22.8 ARC Four Execution Unit (AFEU) ............................................................................ 22-28

22.8.1 AFEU Register Map ............................................................................................... 22-28

22.8.2 AFEU Reset Control Register (AFRCR) ................................................................ 22-28

22.8.3 AFEU Status Register (AFSR) ............................................................................... 22-29

22.8.4 AFEU Interrupt Status Register (AFISR) ............................................................... 22-31

22.8.5 AFEU Interrupt Mask Register (AFIMR) .............................................................. 22-32

22.9 Data Encryption Standard Execution Units (DEU) .................................................... 22-34

22.9.1 DEU Register Map .................................................................................................. 22-34

22.9.2 DEU Reset Control Register (DRCR) .................................................................... 22-34

22.9.3 DEU Status Register (DSR) .................................................................................... 22-35

22.9.4 DEU Interrupt Status Register (DISR) ................................................................... 22-37

22.9.5 DEU Interrupt Mask Register (DIMR) ................................................................... 22-39

22.10 Message Digest Execution Unit (MDEU) .................................................................. 22-40

22.10.1 MDEU Register Map .............................................................................................. 22-40

22.10.2 MDEU Reset Control Register (MDRCR) ............................................................. 22-41

22.10.3 MDEU Status Register (MDSR) ............................................................................. 22-41

22.10.4 MDEU Interrupt Status Register (MDISR) ............................................................ 22-43

22.10.5 MDEU Interrupt Mask Register (MDIMR) ............................................................ 22-44

22.11 RNG Execution Unit (RNG) ...................................................................................... 22-46

22.11.1 RNG Register Map ................................................................................................. 22-46

22.11.2 RNG Reset Control Register (RNGRCR) .............................................................. 22-46

22.11.3 RNG Status Register (RNGSR) .............................................................................. 22-47

22.11.4 RNG Interrupt Status Register (RNGISR) .............................................................. 22-48

22.11.5 RNG Interrupt Mask Register (RNGIMR) ............................................................. 22-49

22.12 Advanced Encryption Standard Execution Units (AESU) ....................................... 22-50

22.12.1 AESU Register Map ............................................................................................... 22-50

22.12.2 AESU Reset Control Register (AESRCR) ............................................................. 22-50

22.12.3 AESU Status Register (AESSR) ............................................................................. 22-51

22.12.4 AESU Interrupt Status Register (AESISR) ............................................................ 22-53

22.12.5 AESU Interrupt Mask Register (AESIMR) ............................................................ 22-54

22.13 Descriptors .................................................................................................................. 22-56

22.13.1 Descriptor Structure ................................................................................................ 22-56

22.13.1.1 Descriptor Header ............................................................................................... 22-57

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22.13.1.2 Descriptor Length and Pointer Fields ................................................................. 22-60

22.13.1.3 Null Fields .......................................................................................................... 22-61

22.13.1.4 Next Descriptor Pointer ...................................................................................... 22-61

22.13.2 Descriptor Chaining ................................................................................................ 22-61

22.13.3 Descriptor Type Formats ....................................................................................... 22-62

22.13.4 Descriptor Classes ................................................................................................... 22-64

22.13.4.1 Dynamic Descriptors .......................................................................................... 22-64

22.13.4.2 Static Descriptors ................................................................................................ 22-65

22.14 EU Specific Data Packet Descriptors ........................................................................ 22-67

22.14.1 AFEU Mode Options and Data Packet Descriptors ................................................ 22-67

22.14.1.1 Dynamically Assigned AFEU ............................................................................ 22-68

22.14.1.2 Statically Assigned AFEU .................................................................................. 22-69

22.14.2 DEU Mode Options and Data Packet Descriptors .................................................. 22-72

22.14.2.1 Dynamically Assigned DEU ............................................................................... 22-73

22.14.2.2 Statically Assigned DEU .................................................................................... 22-74

22.14.3 MDEU Mode Options and Data Packet Descriptors .............................................. 22-77

22.14.3.1 Recommended Settings for MDEU Mode Register ........................................... 22-78

22.14.3.2 Dynamically Assigned MDEU ........................................................................... 22-78

22.14.3.3 Statically Assigned MDEU ................................................................................ 22-79

22.14.4 RNG Data Packet Descriptors ................................................................................ 22-82

22.14.5 AESU Mode Options and Data Packet Descriptors ................................................ 22-83

22.14.5.1 Dynamically Assigned AESU ............................................................................ 22-84

22.14.5.2 Statically Assigned AESU .................................................................................. 22-85

22.14.5.3 AESU-CCM Mode Descriptor ........................................................................... 22-88

22.14.6 Multi-Function Data Packet Descriptors ................................................................ 22-90

22.14.6.1 Snooping ............................................................................................................. 22-91

22.14.6.2 Dynamic Multi-Function Descriptor Formats .................................................... 22-91

22.14.6.3 Static Multi-Function Descriptor Formats .......................................................... 22-95

22.14.6.4 SSLv3.1/TLS 1.0 Processing Descriptors ........................................................ 22-102

Chapter 23

IEEE 1149.1 Test Access Port (JTAG)

23.1 Introduction ................................................................................................................... 23-1

23.1.1 Block Diagram .......................................................................................................... 23-1

23.1.2 Features ..................................................................................................................... 23-2

23.1.3 Modes of Operation .................................................................................................. 23-2

23.2 External Signal Description .......................................................................................... 23-2

23.2.1 Detailed Signal Description ...................................................................................... 23-2

23.2.1.1 Test Mode 0 (MTMOD0) ..................................................................................... 23-2

23.2.1.2 Test Clock Input (TCK) ........................................................................................ 23-3

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23.2.1.3 Test Mode Select/Breakpoint (TMS/BKPT) ........................................................ 23-3

23.2.1.4 Test Data Input/Development Serial Input (TDI/DSI) ......................................... 23-3

23.2.1.5 Test Reset/Development Serial Clock (TRST/DSCLK) ...................................... 23-4

23.2.1.6 Test Data Output/Development Serial Output (TDO/DSO) ................................. 23-4

23.3 Memory Map/Register Definition ................................................................................ 23-4

23.3.1 Memory Map ............................................................................................................ 23-4

23.3.2 Register Descriptions ................................................................................................ 23-4

23.3.2.1 Instruction Shift Register (IR) .............................................................................. 23-4

23.3.2.2 IDCODE Register ................................................................................................. 23-4

23.3.2.3 Bypass Register .................................................................................................... 23-5

23.3.2.4 JTAG_CFM_CLKDIV Register ........................................................................... 23-5

23.3.2.5 TEST_CTRL Register .......................................................................................... 23-5

23.3.2.6 Boundary Scan Register ....................................................................................... 23-6

23.4 Functional Description .................................................................................................. 23-6

23.4.1 JTAG Module ........................................................................................................... 23-6

23.4.2 TAP Controller ......................................................................................................... 23-6

23.4.3 JTAG Instructions ..................................................................................................... 23-7

23.4.3.1 External Test Instruction (EXTEST) .................................................................... 23-8

23.4.3.2 IDCODE Instruction ............................................................................................. 23-8

23.4.3.3 SAMPLE/PRELOAD Instruction ......................................................................... 23-8

23.4.3.4 ENABLE_TEST_CTRL Instruction .................................................................... 23-9

23.4.3.5 HIGHZ Instruction ................................................................................................ 23-9

23.4.3.6 CLAMP Instruction .............................................................................................. 23-9

23.4.3.7 BYPASS Instruction ............................................................................................. 23-9

23.5 Initialization/Application Information .......................................................................... 23-9

23.5.1 Restrictions ............................................................................................................... 23-9

23.5.2 Nonscan Chain Operation ......................................................................................... 23-9

Chapter 24

Multichannel DMA

24.1 Introduction ................................................................................................................... 24-1

24.1.1 Block Diagram .......................................................................................................... 24-1

24.1.2 Overview ................................................................................................................... 24-2

24.1.2.1 Master DMA Engine (MDE) ................................................................................ 24-2

24.1.2.2 Address and Data Sequencer (ADS) ..................................................................... 24-2

24.1.2.3 Priority-Task Decoder (PTD) ............................................................................... 24-2

24.1.2.4 Logic Unit with Redundancy Check (LURC) ...................................................... 24-2

24.1.2.5 Debug Unit ............................................................................................................ 24-2

24.1.3 Features ..................................................................................................................... 24-2

24.2 External Signals ............................................................................................................ 24-3

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24.2.1 DREQ[1:0] ............................................................................................................... 24-3

24.2.2 DACK[1:0] .............................................................................................................. 24-3

24.3 Memory Map/Register Definitions ............................................................................... 24-3

24.3.1 DMA Task Memory .................................................................................................. 24-3

24.3.1.1 Task Table ............................................................................................................ 24-3

24.3.1.2 Task Descriptor Table ........................................................................................... 24-3

24.3.1.3 Variable Table ...................................................................................................... 24-4

24.3.1.4 Function Descriptor Table .................................................................................... 24-4

24.3.1.5 Context Save Space .............................................................................................. 24-4

24.3.2 Memory Structure ..................................................................................................... 24-4

24.3.3 DMA Registers ......................................................................................................... 24-5

24.3.3.1 DMA Register Map .............................................................................................. 24-5

24.3.3.2 Task Base Address Register (TaskBAR) .............................................................. 24-6

24.3.3.3 Current Pointer (CP) ............................................................................................. 24-7

24.3.3.4 End Pointer (EP) ................................................................................................... 24-8

24.3.3.5 Variable Pointer (VP) ........................................................................................... 24-8

24.3.3.6 PTD Control (PTD) .............................................................................................. 24-9

24.3.3.7 DMA Interrupt Pending (DIPR) ......................................................................... 24-10

24.3.3.8 DMA Interrupt Mask Register (DIMR) .............................................................. 24-10

24.3.3.9 Task Control Registers (TCRn) .......................................................................... 24-11

24.3.3.10 Priority Registers (PRIORn) ............................................................................... 24-12

24.3.3.11 Initiator Mux Control Register (IMCR) ............................................................. 24-13

24.3.3.12 Task Size Registers (TSKSZ[0:1]) ..................................................................... 24-14

24.3.3.13 Debug Comparator Registers (DBGCOMPn) .................................................... 24-16

24.3.3.14 Debug Control (DBGCTL) ................................................................................. 24-16

24.3.3.15 Debug Status (DBGSTAT) ................................................................................. 24-18

24.3.3.16 PTD Debug Registers ......................................................................................... 24-19

24.3.4 External Request Module Registers ........................................................................ 24-20

24.3.4.1 External Request Module Register Map ............................................................. 24-20

24.3.4.2 External Request Base Address Register (EREQBAR) ..................................... 24-20

24.3.4.3 External Request Address Mask Register (EREQMASK) ................................. 24-21

24.3.4.4 External Request Control Register (EREQCTRL) ............................................. 24-21

24.4 Functional Description ................................................................................................ 24-22

24.4.1 Tasks ....................................................................................................................... 24-22

24.4.2 Descriptors .............................................................................................................. 24-23

24.4.3 Task Initialization ................................................................................................... 24-23

24.4.4 Initiators .................................................................................................................. 24-23

24.4.5 Prioritization ........................................................................................................... 24-24

24.4.6 Context Switch ........................................................................................................ 24-24

24.4.7 Data Movement ....................................................................................................... 24-24

24.4.8 Data Manipulation .................................................................................................. 24-24

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24.4.8.1 LURC Features ................................................................................................... 24-25

24.4.9 Line Buffers ............................................................................................................ 24-26

24.4.9.1 Combine Write Enable ....................................................................................... 24-26

24.4.9.2 Read Line Enable ................................................................................................ 24-26

24.4.9.3 Speculative Prefetch ........................................................................................... 24-26

24.4.10 Termination of Loop ............................................................................................... 24-27

24.4.11 Interrupts ................................................................................................................. 24-27

24.4.12 Debug Unit .............................................................................................................. 24-27

24.5 Programming Model ................................................................................................... 24-27

24.5.1 Register Initialization .............................................................................................. 24-27

24.5.2 Task Memory .......................................................................................................... 24-28

24.5.2.1 Task Table .......................................................................................................... 24-28

24.6 Timing Diagrams ........................................................................................................ 24-30

24.6.1 Level-Triggered Requests ....................................................................................... 24-30

24.6.2 Edge-Triggered Requests ........................................................................................ 24-30

24.6.3 Pipelined Requests .................................................................................................. 24-31

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Chapter 25

Comm Timer Module (CTM)

25.1 Introduction ................................................................................................................... 25-1

25.1.1 Block Diagrams ........................................................................................................ 25-1

25.1.2 Overview ................................................................................................................... 25-2

25.1.3 Comm Timer External Clock[7:0] ............................................................................ 25-3

25.2 Memory Map/Register Definition ................................................................................ 25-3

25.2.1 Timer Module Register Map ..................................................................................... 25-3

25.2.2 Register Descriptions ................................................................................................ 25-4

25.2.2.1 Comm Timer Configuration Register (CTCRn)—Fixed Timer Channel ............. 25-4

25.2.2.2 Comm Timer Configuration Register (CTCRn)—Variable Timer Channel ........ 25-5

25.3 Functional Description .................................................................................................. 25-7

25.3.1 Variable Timer in Baud Clock Generator Mode ...................................................... 25-7

25.3.2 Fixed Timer in Initiator Mode .................................................................................. 25-7

25.3.2.1 Fixed Timer in Initiator Mode Example ............................................................... 25-7

25.3.3 Variable Timer in Initiator Mode .............................................................................. 25-8

25.3.3.1 Variable Timer in Initiator Mode Example .......................................................... 25-8

Chapter 26

Programmable Serial Controller (PSC)

26.1 Introduction ................................................................................................................... 26-1

MCF548x Reference Manual, Rev. 3

xxx Freescale Semiconductor