Freescale Semiconductor MCF5480, MCF5481, MCF5482, MCF5483, MCF5485 User Manual

MCF548x Reference Manual

Devices Supported:

MCF5485 MCF5482
MCF5484 MCF5481
MCF5483 MCF5480

Document Number: MCF5485RM

Rev. 3

01/2006

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© Freescale Semiconductor, Inc. 2006. All rights reserved.

MCF5485RM
Rev. 3
01/2006

Overview

1

Signal Descriptions

ColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)

Memory Management Unit (MMU)

Floating-Point Unit (FPU)

Local Memory

Debug Support

System Integration Unit (SIU)

Internal Clocks and Bus Architecture

General Purpose Timers (GPT)

Slice Timers (SLT)

Interrupt Controller (INTC)

Edge Port Module (EPORT)

General Purpose I/O (GPIO)

2
3
4
5
6
7
8

9
10
11

12
13
14
15

System SRAM

FlexBus

SDRAM Controller (SDRAMC)

PCI Bus Controller (PCI)

PCI Bus Arbiter (PCIARB)

FlexCAN

Integrated Secuity Engine (SEC)

IEEE 1149.1 Test Access Port (JTAG)

Multichannel DMA (MCD)

Comm Timer Module (CTM)

Programmable Serial Controller (PSC)

2

C interface

I

DMA Serial Peripheral Interface (DSPI)

USB 2.0 Device Controller

16
17
18
19
20
21
22
23
24
25
26
27
28
29

Fast Ethernet Controller (FEC)

Mechanical Data

Register Memory Map Quick Reference

Index

30
31

A

IND

1

Overview

2
3
4
5
6
7
8
9

10
11

12
13
14
15

Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Memory Management Unit (MMU)
Floating-Point Unit (FPU)
Local Memory
Debug Support
System Integration Unit (SIU)
Internal Clocks and Bus Architecture
General Purpose Timers (GPT)
Slice Timers (SLT)
Interrupt Controller (INTC)
Edge Port Module (EPORT)

General Purpose I/O (GPIO)

16
17
18
19
20
21
22
23
24
25
26
27
28
29

System SRAM

FlexBus

SDRAM Controller (SDRAMC)

PCI Bus Controller (PCI)

PCI Bus Arbiter (PCIARB)

FlexCAN

Integrated Secuity Engine (SEC)

IEEE 1149.1 Test Access Port (JTAG)

Multichannel DMA (MCD)

Comm Timer Module (CTM)

Programmable Serial Controller (PSC)

2

C interface

I

DMA Serial Peripheral Interface (DSPI)

USB 2.0 Device Controller

30
31

A

IND

Fast Ethernet Controller (FEC)

Mechanical Data

Register Memory Map Quick Reference

Index

Contents

Paragraph
Number

Title

Page

Number

Chapter 1

Overview

1.1 MCF548x Family Overview ........................................................................................... 1-1

1.2 MCF548x Block Diagram .............................................................................................. 1-2

1.3 MCF548x Family Products ............................................................................................. 1-3

1.4 MCF548x Family Features ............................................................................................. 1-3

1.4.1 ColdFire V4e Core Overview ..................................................................................... 1-5

1.4.2 Debug Module (BDM) ................................................................................................ 1-6

1.4.3 JTAG ........................................................................................................................... 1-6

1.4.4 On-Chip Memories ..................................................................................................... 1-7

1.4.4.1 Caches ..................................................................................................................... 1-7

1.4.4.2 System SRAM ........................................................................................................ 1-7

1.4.5 PLL and Chip Clocking Options ................................................................................ 1-7

1.4.6 Communications I/O Subsystem ................................................................................ 1-8

1.4.6.1 DMA Controller ...................................................................................................... 1-8

1.4.6.2 10/100 Fast Ethernet Controller (FEC) ................................................................... 1-8

1.4.6.3 USB 2.0 Device (Universal Serial Bus) ................................................................. 1-8

1.4.6.4 Programmable Serial Controllers (PSCs) ............................................................... 1-9

1.4.6.5 I2C (Inter-Integrated Circuit) ................................................................................. 1-9

1.4.6.6 DMA Serial Peripheral Interface (DSPI) ................................................................ 1-9

1.4.6.7 Controller Area Network (CAN) .......................................................................... 1-10

1.4.7 DDR SDRAM Memory Controller ........................................................................... 1-10

1.4.8 Peripheral Component Interconnect (PCI) ............................................................... 1-10

1.4.9 Flexible Local Bus (FlexBus) ................................................................................... 1-10

1.4.10 Security Encryption Controller (SEC) ...................................................................... 1-11

1.4.11 System Integration Unit (SIU) .................................................................................. 1-11

1.4.11.1 Timers ................................................................................................................... 1-11

1.4.11.2 Interrupt Controller ............................................................................................... 1-12

1.4.11.3 General Purpose I/O ............................................................................................. 1-12

Chapter 2

Signal Descriptions

2.1 Introduction ..................................................................................................................... 2-1

2.1.1 Block Diagram ............................................................................................................ 2-1

2.2 MCF548x External Signals ........................................................................................... 2-16

2.2.1 FlexBus Signals ........................................................................................................ 2-16

2.2.1.1 Address/Data Bus (AD[31:0]) .............................................................................. 2-16

2.2.1.2 Chip Select (FBCS

2.2.1.3 Address Latch Enable (ALE) ................................................................................ 2-17

Freescale Semiconductor v

[5:0]) ....................................................................................... 2-17

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2.2.1.4 Read/Write (R/W) ................................................................................................. 2-17

2.2.1.5 Transfer Burst (TBST

) .......................................................................................... 2-17

2.2.1.6 Transfer Size (TSIZ[1:0]) ..................................................................................... 2-17

2.2.1.7 Byte Selects (BE

/BWE[3:0]) ................................................................................ 2-18

2.2.1.8 Output Enable (OE) .............................................................................................. 2-18

2.2.1.9 Transfer Acknowledge (TA) ................................................................................. 2-18

2.2.2 SDRAM Controller Signals ...................................................................................... 2-18

2.2.2.1 SDRAM Data Bus (SDDATA[31:0]) ................................................................... 2-18

2.2.2.2 SDRAM Address Bus (SDADDR[12:0]) ............................................................. 2-18

2.2.2.3 SDRAM Bank Addresses (SDBA[1:0]) ............................................................... 2-19

2.2.2.4 SDRAM Row Address Strobe (RAS) ................................................................... 2-19

2.2.2.5 SDRAM Column Address Strobe (CAS) ............................................................. 2-19

2.2.2.6 SDRAM Chip Selects (SDCS[3:0]) ...................................................................... 2-19

2.2.2.7 SDRAM Write Data Byte Mask (SDDM[3:0]) .................................................... 2-19

2.2.2.8 SDRAM Data Strobe (SDDQS[3:0]) .................................................................... 2-19

2.2.2.9 SDRAM Clock (SDCLK[1:0]) ............................................................................. 2-19

2.2.2.10 Inverted SDRAM Clock (SDCLK[1:0]) ............................................................... 2-19

2.2.2.11 SDRAM Write Enable (SDWE) ........................................................................... 2-19

2.2.2.12 SDRAM Clock Enable (SDCKE) ......................................................................... 2-19

2.2.2.13 SDR SDRAM Data Strobe (SDRDQS) ................................................................ 2-19

2.2.2.14 SDRAM Reference Voltage (VREF) ................................................................... 2-20

2.2.3 PCI Controller Signals .............................................................................................. 2-20

2.2.3.1 PCI Address/Data Bus (PCIAD[31:0]) ................................................................. 2-20

2.2.3.2 Command/Byte Enables (PCICXBE[3:0]) ........................................................... 2-20

2.2.3.3 Device Select (PCIDEVSEL) ............................................................................... 2-20

2.2.3.4 Frame (PCIFRM) .................................................................................................. 2-20

2.2.3.5 Initialization Device Select (PCIIDSEL) .............................................................. 2-20

2.2.3.6 Initiator Ready (PCIIRDY) ................................................................................... 2-20

2.2.3.7 Parity (PCIPAR) ................................................................................................... 2-20

2.2.3.8 Parity Error (PCIPERR) ....................................................................................... 2-20

2.2.3.9 Reset (PCIRESET) ............................................................................................... 2-21

2.2.3.10 System Error (PCISERR) ..................................................................................... 2-21

2.2.3.11 Stop (PCISTOP) ................................................................................................... 2-21

2.2.3.12 Target Ready (PCITRDY) .................................................................................... 2-21

2.2.3.13 External Bus Grant (PCIBG[4:1]) ........................................................................ 2-21

2.2.3.14 External Bus Grant/Request Output (PCIBG0

/PCIREQOUT) ............................ 2-21

2.2.3.15 External Bus Request (PCIBR[4:0]) ..................................................................... 2-21

2.2.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN) .......................................... 2-21

2.2.4 Interrupt Control Signals .......................................................................................... 2-21

2.2.4.1 Interrupt Request (IRQ

[7:1]) ................................................................................ 2-21

2.2.5 Clock and Reset Signals ........................................................................................... 2-22

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2.2.5.1 Reset In (RSTI) ..................................................................................................... 2-22

2.2.5.2 Reset Out (RSTO) ................................................................................................. 2-22

2.2.5.3 Clock In (CLKIN) ................................................................................................. 2-22

2.2.6 Reset Configuration Pins .......................................................................................... 2-22

2.2.6.1 AD[12:8]—CLKIN to SDCLK Ratio (CLKCONFIG[4:0]) ................................ 2-22

2.2.6.2 AD5—FlexBus Size Configuration (FBSIZE) ..................................................... 2-23

2.2.6.3 AD4—32-bit FlexBus Configuration (FBMODE) ............................................... 2-23

2.2.6.4 AD3—Byte Enable Configuration (BECONFIG) ................................................ 2-23

2.2.6.5 AD2—Auto Acknowledge Configuration (AACONFIG) .................................... 2-24

2.2.6.6 AD[1:0]—Port Size Configuration (PSCONFIG) ................................................ 2-24

2.2.7 Ethernet Module Signals ........................................................................................... 2-24

2.2.7.1 Management Data (E0MDIO, E1MDIO) ............................................................. 2-24

2.2.7.2 Management Data Clock (E0MDC, E1MDC) ...................................................... 2-25

2.2.7.3 Transmit Clock (E0TXCLK, E1TXCLK) ............................................................ 2-25

2.2.7.4 Transmit Enable (E0TXEN, E1TXEN) ................................................................ 2-25

2.2.7.5 Transmit Data 0 (E0TXD0, E1TXD0) ................................................................. 2-25

2.2.7.6 Collision (E0COL, E1COL) ................................................................................. 2-25

2.2.7.7 Receive Clock (E0RXCLK, E1RXCLK) ............................................................. 2-25

2.2.7.8 Receive Data Valid (E0RXDV, E1RXDV) .......................................................... 2-25

2.2.7.9 Receive Data 0 (E0RXD0, E1RXD0) .................................................................. 2-25

2.2.7.10 Carrier Receive Sense (E0CRS, E1CRS) ............................................................. 2-25

2.2.7.11 Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1]) .................................................. 2-25

2.2.7.12 Transmit Error (E0TXER, E1TXER) ................................................................... 2-26

2.2.7.13 Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1]) ................................................... 2-26

2.2.7.14 Receive Error (E0RXER, E1RXER) .................................................................... 2-26

2.2.8 Universal Serial Bus (USB) ...................................................................................... 2-26

2.2.8.1 USB Differential Data (USBD+, USBD–) ........................................................... 2-26

2.2.8.2 USBVBUS ............................................................................................................ 2-26

2.2.8.3 USBRBIAS ........................................................................................................... 2-26

2.2.8.4 USBCLKIN .......................................................................................................... 2-26

2.2.8.5 USBCLKOUT ...................................................................................................... 2-26

2.2.9 DMA Serial Peripheral Interface (DSPI) Signals ..................................................... 2-26

2.2.9.1 DSPI Synchronous Serial Data Output (DSPISOUT) .......................................... 2-26

2.2.9.2 DSPI Synchronous Serial Data Input (DSPISIN) ................................................. 2-27

2.2.9.3 DSPI Serial Clock (DSPISCK) ............................................................................. 2-27

2.2.9.4 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 2-27

2.2.9.5 DSPI Chip Selects (DSPICS[2:3]) ........................................................................ 2-27

2.2.9.6 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 2-27

2.2.10 FlexCAN Signals ...................................................................................................... 2-27

2.2.10.1 FlexCAN Transmit (CANTX0, CANTX1) .......................................................... 2-27

2.2.10.2 FlexCAN Receive (CANRX0, CANRX1) ........................................................... 2-27

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2.2.11 I2C I/O Signals .......................................................................................................... 2-27

2.2.11.1 Serial Clock (SCL) ............................................................................................... 2-28

2.2.11.2 Serial Data (SDA) ................................................................................................. 2-28

2.2.12 PSC Module Signals ................................................................................................. 2-28

2.2.12.1 Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD) .. 2-28

2.2.12.2 Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD) ..... 2-28

2.2.12.3 Clear-to-Send (PSCnCTS/PSCBCLK) ................................................................. 2-28

2.2.12.4 Request-to-Send (PSCnRTS/PSCFSYNC) ........................................................... 2-28

2.2.13 DMA Controller Module Signals ............................................................................. 2-28

2.2.13.1 DMA Request (DREQ[1:0]) ................................................................................. 2-28

2.2.13.2 DMA Acknowledge (DACK[1:0]) ....................................................................... 2-28

2.2.14 Timer Module Signals .............................................................................................. 2-29

2.2.14.1 Timer Inputs (TIN[3:0]) ....................................................................................... 2-29

2.2.14.2 Timer Outputs (TOUT[3:0]) ................................................................................. 2-29

2.2.15 Debug Support Signals ............................................................................................. 2-29

2.2.15.1 Processor Clock Output (PSTCLK) ...................................................................... 2-29

2.2.15.2 Processor Status Debug Data (PSTDDATA[7:0]) ............................................... 2-29

2.2.15.3 Development Serial Clock/Test Reset (DSCLK/TRST) ...................................... 2-29

2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS) ........................................................ 2-30

2.2.15.5 Development Serial Input/Test Data Input (DSI/TDI) ......................................... 2-30

2.2.15.6 Development Serial Output/Test Data Output (DSO/TDO) ................................. 2-30

2.2.15.7 Test Clock (TCK) ................................................................................................. 2-30

2.2.16 Test Signals ............................................................................................................... 2-30

2.2.16.1 Test Mode (MTMOD[3:0]) .................................................................................. 2-30

2.2.17 Power and Reference Pins ........................................................................................ 2-31

2.2.17.1 Positive Pad Supply (EVDD) ............................................................................... 2-31

2.2.17.2 Positive Core Supply (IVDD) ............................................................................... 2-31

2.2.17.3 Ground (VSS) ....................................................................................................... 2-31

2.2.17.4 USB Power (USBVDD) ....................................................................................... 2-31

2.2.17.5 USB Oscillator Power (USB_OSCVDD) ............................................................. 2-31

2.2.17.6 USB PHY Power (USB_PHYVDD) .................................................................... 2-31

2.2.17.7 USB Oscillator Analog Power (USB_OSCAVDD) ............................................. 2-31

2.2.17.8 USB PLL Analog Power (USB_PLLVDD) ......................................................... 2-31

2.2.17.9 SDRAM Memory Supply (SDVDD) .................................................................... 2-31

2.2.17.10 PLL Analog Power (PLLVDD) ............................................................................ 2-31

2.2.17.11 PLL Analog Ground (PLLVSS) ........................................................................... 2-31

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Chapter 3

ColdFire Core

3.1 Core Overview ................................................................................................................ 3-1

3.2 Features ........................................................................................................................... 3-1

3.2.1 Enhanced Pipelines ..................................................................................................... 3-2

3.2.1.1 Instruction Fetch Pipeline (IFP) .............................................................................. 3-3

3.2.1.2 Operand Execution Pipeline (OEP) ........................................................................ 3-4

3.2.1.3 Harvard Memory Architecture ............................................................................... 3-6

3.2.2 Debug Module Enhancements .................................................................................... 3-6

3.3 Programming Model ....................................................................................................... 3-7

3.3.1 User Programming Model .......................................................................................... 3-9

3.3.1.1 Data Registers (D0–D7) ......................................................................................... 3-9

3.3.1.2 Address Registers (A0–A6) .................................................................................... 3-9

3.3.2 User Stack Pointer (A7) ............................................................................................. 3-9

3.3.2.1 Program Counter (PC) ............................................................................................ 3-9

3.3.2.2 Condition Code Register (CCR) ............................................................................. 3-9

3.3.3 EMAC Programming Model .................................................................................... 3-10

3.3.4 FPU Programming Model ......................................................................................... 3-10

3.3.5 Supervisor Programming Model ............................................................................... 3-11

3.3.5.1 Status Register (SR) .............................................................................................. 3-12

3.3.5.2 Vector Base Register (VBR) ................................................................................ 3-12

3.3.5.3 Cache Control Register (CACR) .......................................................................... 3-13

3.3.5.4 Access Control Registers (ACR0–ACR3) ............................................................ 3-13

3.3.5.5 RAM Base Address Registers (RAMBAR0 and RAMBAR1) ............................ 3-13

3.3.5.6 Module Base Address Register (MBAR) ............................................................. 3-13

3.3.6 Programming Model Table ....................................................................................... 3-13

3.4 Data Format Summary .................................................................................................. 3-15

3.4.1 Data Organization in Registers ................................................................................. 3-15

3.4.1.1 Integer Data Format Organization in Registers .................................................... 3-15

3.4.1.2 Integer Data Format Organization in Memory ..................................................... 3-16

3.4.2 EMAC Data Representation ..................................................................................... 3-17

3.4.2.1 Floating-Point Data Formats and Types ............................................................... 3-17

3.5 Addressing Mode Summary ......................................................................................... 3-18

3.6 Instruction Set Summary .............................................................................................. 3-19

3.6.1 Additions to the Instruction Set Architecture ........................................................... 3-19

3.6.2 Instruction Set Summary .......................................................................................... 3-22

3.7 Instruction Execution Timing ....................................................................................... 3-27

3.7.1 MOVE Instruction Execution Timing ...................................................................... 3-28

3.7.2 One-Operand Instruction Execution Timing ............................................................ 3-30

3.7.3 Two-Operand Instruction Execution Timing ............................................................ 3-31

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Freescale Semiconductor ix

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3.7.4 Miscellaneous Instruction Execution Timing ........................................................... 3-32

3.7.5 Branch Instruction Execution Timing ....................................................................... 3-33

3.7.6 EMAC Instruction Execution Times ........................................................................ 3-34

3.7.7 FPU Instruction Execution Times ............................................................................. 3-35

3.8 Exception Processing Overview ................................................................................... 3-36

3.8.1 Exception Stack Frame Definition ............................................................................ 3-38

3.8.2 Processor Exceptions ................................................................................................ 3-39

3.9 Precise Faults ................................................................................................................ 3-42

Title

Page

Number

Chapter 4

Enhanced Multiply-Accumulate Unit (EMAC)

4.1 Introduction ..................................................................................................................... 4-1

4.1.1 MAC Overview ........................................................................................................... 4-2

4.1.2 General Operation ....................................................................................................... 4-2

4.2 Memory Map/Register Definition .................................................................................. 4-5

4.2.1 MAC Status Register (MACSR) ................................................................................. 4-5

4.2.1.1 Fractional Operation Mode ..................................................................................... 4-8

4.2.2 Mask Register (MASK) ............................................................................................ 4-10

4.3 EMAC Instruction Set Summary .................................................................................. 4-11

4.3.1 EMAC Instruction Execution Timing ....................................................................... 4-11

4.3.2 Data Representation .................................................................................................. 4-12

4.3.3 EMAC Opcodes ........................................................................................................ 4-13

Chapter 5

Memory Management Unit (MMU)

5.1 Features ........................................................................................................................... 5-1

5.2 Virtual Memory Management Architecture ................................................................... 5-1

5.2.1 MMU Architecture Features ....................................................................................... 5-1

5.2.2 MMU Architecture Location ...................................................................................... 5-2

5.2.3 MMU Architecture Implementation ........................................................................... 5-3

5.2.3.1 Precise Faults ..........................................................................................................5-4

5.2.3.2 MMU Access .......................................................................................................... 5-4

5.2.3.3 Virtual Mode ........................................................................................................... 5-4

5.2.3.4 Virtual Memory References ................................................................................... 5-4

5.2.3.5 Instruction and Data Cache Addresses ................................................................... 5-4

5.2.3.6 Supervisor/User Stack Pointers .............................................................................. 5-5

5.2.3.7 Access Error Stack Frame ...................................................................................... 5-5

5.2.3.8 Expanded Control Register Space .......................................................................... 5-5

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5.2.3.9 Changes to ACRs and CACR ................................................................................. 5-5

5.2.3.10 ACR Address Improvements .................................................................................. 5-6

5.2.3.11 Supervisor Protection .............................................................................................. 5-7

5.3 Debugging in a Virtual Environment .............................................................................. 5-7

5.4 Virtual Memory Architecture Processor Support ........................................................... 5-7

5.4.1 Precise Faults .............................................................................................................. 5-7

5.4.2 Supervisor/User Stack Pointers ................................................................................. 5-7

5.4.3 Access Error Stack Frame Additions .......................................................................... 5-8

5.5 MMU Definition ............................................................................................................. 5-9

5.5.1 Effective Address Attribute Determination ................................................................ 5-9

5.5.2 MMU Functionality .................................................................................................. 5-10

5.5.3 MMU Organization ................................................................................................... 5-10

5.5.3.1 MMU Base Address Register (MMUBAR) ......................................................... 5-10

5.5.3.2 MMU Memory Map ............................................................................................. 5-11

5.5.3.3 MMU Control Register (MMUCR) ..................................................................... 5-11

5.5.3.4 MMU Operation Register (MMUOR) .................................................................. 5-12

5.5.3.5 MMU Status Register (MMUSR) ......................................................................... 5-14

5.5.3.6 MMU Fault, Test, or TLB Address Register (MMUAR) ..................................... 5-15

5.5.3.7 MMU Read/Write Tag and Data Entry Registers (MMUTR and MMUDR) ...... 5-16

5.5.4 MMU TLB ................................................................................................................ 5-18

5.5.5 MMU Operation ....................................................................................................... 5-19

5.6 MMU Implementation .................................................................................................. 5-20

5.6.1 TLB Address Fields .................................................................................................. 5-20

5.6.2 TLB Replacement Algorithm ................................................................................... 5-21

5.6.3 TLB Locked Entries .................................................................................................. 5-22

5.7 MMU Instructions ......................................................................................................... 5-23

Chapter 6

Floating-Point Unit (FPU)

6.1 Introduction ..................................................................................................................... 6-1

6.1.1 Overview ..................................................................................................................... 6-1

6.1.1.1 Notational Conventions .......................................................................................... 6-1

6.2 Operand Data Formats and Types .................................................................................. 6-3

6.2.1 Signed-Integer Data Formats ...................................................................................... 6-3

6.2.2 Floating-Point Data Formats ....................................................................................... 6-3

6.2.3 Floating-Point Data Types .......................................................................................... 6-4

6.2.3.1 Normalized Numbers .............................................................................................. 6-4

6.2.3.2 Zeros ....................................................................................................................... 6-4

6.2.3.3 Infinities .................................................................................................................. 6-4

6.2.3.4 Not-A-Number ........................................................................................................ 6-5

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6.2.3.5 Denormalized Numbers .......................................................................................... 6-5

6.3 Register Definition .......................................................................................................... 6-7

6.3.1 Floating-Point Data Registers (FP0–FP7) .................................................................. 6-7

6.3.2 Floating-Point Control Register (FPCR) .................................................................... 6-7

6.3.3 Floating-Point Status Register (FPSR) ....................................................................... 6-9

6.3.4 Floating-Point Instruction Address Register (FPIAR) .............................................. 6-10

6.4 Floating-Point Computational Accuracy ...................................................................... 6-11

6.4.1 Intermediate Result ................................................................................................... 6-11

6.4.2 Rounding the Result .................................................................................................. 6-12

6.5 Floating-Point Post-Processing ..................................................................................... 6-14

6.5.1 Underflow, Round, and Overflow ............................................................................ 6-14

6.5.2 Conditional Testing ................................................................................................... 6-15

6.6 Floating-Point Exceptions ............................................................................................. 6-17

6.6.1 Floating-Point Arithmetic Exceptions ...................................................................... 6-18

6.6.1.1 Branch/Set on Unordered (BSUN) ....................................................................... 6-19

6.6.1.2 Input Not-A-Number (INAN) ............................................................................... 6-20

6.6.1.3 Input Denormalized Number (IDE) ...................................................................... 6-20

6.6.1.4 Operand Error (OPERR) ....................................................................................... 6-21

6.6.1.5 Overflow (OVFL) ................................................................................................. 6-21

6.6.1.6 Underflow (UNFL) ............................................................................................... 6-22

6.6.1.7 Divide-by-Zero (DZ) ............................................................................................ 6-22

6.6.1.8 Inexact Result (INEX) .......................................................................................... 6-23

6.6.2 Floating-Point State Frames ...................................................................................... 6-23

6.7 Instructions .................................................................................................................... 6-25

6.7.1 Floating-Point Instruction Overview ........................................................................ 6-25

6.7.2 Floating-Point Instruction Execution Timing ........................................................... 6-27

6.7.3 Key Differences between ColdFire and M68000 FPU Programming Models ......... 6-28

Chapter 7

Local Memory

7.1 Interactions between Local Memory Modules ............................................................... 7-1

7.2 SRAM Overview ............................................................................................................ 7-1

7.3 SRAM Operation ............................................................................................................ 7-2

7.4 SRAM Register Definition ............................................................................................. 7-2

7.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1) ....................................... 7-2

7.5 SRAM Initialization ........................................................................................................ 7-4

7.5.1 SRAM Initialization Code .......................................................................................... 7-5

7.6 Power Management ........................................................................................................ 7-6

7.7 Cache Overview ..............................................................................................................7-6

7.8 Cache Organization ......................................................................................................... 7-7

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7.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified ......................... 7-8

7.8.2 The Cache at Start-Up ................................................................................................. 7-8

7.9 Cache Operation ........................................................................................................... 7-10

7.9.1 Caching Modes ......................................................................................................... 7-12

7.9.1.1 Cacheable Accesses .............................................................................................. 7-12

7.9.1.2 Cache-Inhibited Accesses ..................................................................................... 7-13

7.9.2 Cache Protocol .......................................................................................................... 7-14

7.9.2.1 Read Miss ............................................................................................................. 7-14

7.9.2.2 Write Miss (Data Cache Only) ............................................................................. 7-14

7.9.2.3 Read Hit ................................................................................................................7-15

7.9.2.4 Write Hit (Data Cache Only) ................................................................................ 7-15

7.9.3 Cache Coherency (Data Cache Only) ....................................................................... 7-15

7.9.4 Memory Accesses for Cache Maintenance ............................................................... 7-15

7.9.4.1 Cache Filling ......................................................................................................... 7-15

7.9.4.2 Cache Pushes ........................................................................................................ 7-16

7.9.5 Cache Locking .......................................................................................................... 7-17

7.10 Cache Register Definition ............................................................................................. 7-19

7.10.1 Cache Control Register (CACR) .............................................................................. 7-19

7.10.2 Access Control Registers (ACR0–ACR3) ................................................................ 7-22

7.11 Cache Management ....................................................................................................... 7-23

7.12 Cache Operation Summary ........................................................................................... 7-26

7.12.1 Instruction Cache State Transitions .......................................................................... 7-26

7.12.2 Data Cache State Transitions .................................................................................... 7-27

7.13 Cache Initialization Code .............................................................................................. 7-30

Chapter 8

Debug Support

8.1 Introduction ..................................................................................................................... 8-1

8.1.1 Overview ..................................................................................................................... 8-1

8.2 Signal Descriptions .........................................................................................................8-2

8.2.1 Processor Status/Debug Data (PSTDDATA[7:0]) ..................................................... 8-3

8.3 Real-Time Trace Support ................................................................................................ 8-5

8.3.1 Begin Execution of Taken Branch (PST = 0x5) ......................................................... 8-6

8.3.2 Processor Stopped or Breakpoint State Change (PST = 0xE) .................................... 8-7

8.3.3 Processor Halted (PST = 0xF) .................................................................................... 8-8

8.4 Memory Map/Register Definition .................................................................................. 8-9

8.4.1 Revision A Shared Debug Resources ....................................................................... 8-11

8.4.2 Configuration/Status Register (CSR) ........................................................................ 8-11

8.4.3 PC Breakpoint ASID Control Register (PBAC) ....................................................... 8-14

8.4.4 BDM Address Attribute Register (BAAR) ............................................................... 8-15

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8.4.5 Address Attribute Trigger Registers (AATR, AATR1) ............................................ 8-16

8.4.6 Trigger Definition Register (TDR) ........................................................................... 8-17

8.4.7 Program Counter Breakpoint and Mask Registers (PBRn, PBMR) ......................... 8-20

8.4.8 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) ........................... 8-21

8.4.9 Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1) .................... 8-22

8.4.10 PC Breakpoint ASID Register (PBASID) ................................................................ 8-24

8.4.11 Extended Trigger Definition Register (XTDR) ........................................................ 8-25

8.4.11.1 Resulting Set of Possible Trigger Combinations .................................................. 8-27

8.5 Background Debug Mode (BDM) ................................................................................ 8-28

8.5.1 CPU Halt ................................................................................................................... 8-28

8.5.2 BDM Serial Interface ................................................................................................ 8-30

8.5.2.1 Receive Packet Format ......................................................................................... 8-30

8.5.2.2 Transmit Packet Format ........................................................................................ 8-31

8.5.3 BDM Command Set .................................................................................................. 8-31

8.5.3.1 ColdFire BDM Command Format ........................................................................ 8-33

8.5.3.2 Command Sequence Diagrams ............................................................................. 8-33

8.5.3.3 Command Set Descriptions .................................................................................. 8-35

8.6 Real-Time Debug Support ............................................................................................ 8-51

8.6.1 Theory of Operation .................................................................................................. 8-51

8.6.1.1 Emulator Mode ..................................................................................................... 8-53

8.6.2 Concurrent BDM and Processor Operation .............................................................. 8-53

8.7 Debug C Definition of PSTDDATA Outputs .............................................................. 8-54

8.7.1 User Instruction Set .................................................................................................. 8-54

8.7.2 Supervisor Instruction Set ......................................................................................... 8-60

8.8 ColdFire Debug History ................................................................................................ 8-61

8.8.1 ColdFire Debug Classic: The Original Definition .................................................... 8-61

8.8.2 ColdFire Debug Revision B ...................................................................................... 8-62

8.8.3 ColdFire Debug Revision C ...................................................................................... 8-62

8.8.3.1 Debug Interrupts and Interrupt Requests (Emulator Mode) ................................. 8-62

8.9 Freescale-Recommended BDM Pinout ........................................................................ 8-63

Chapter 9

System Integration Unit (SIU)

9.1 Introduction ..................................................................................................................... 9-1

9.2 Features ........................................................................................................................... 9-1

9.3 Memory Map/Register Definition .................................................................................. 9-1

9.3.1 Module Base Address Register (MBAR) ................................................................... 9-2

9.3.1.1 System Breakpoint Control Register (SBCR) ........................................................ 9-3

9.3.1.2 SEC Sequential Access Control Register (SECSACR) ......................................... 9-4

9.3.1.3 Reset Status Register (RSR) ................................................................................... 9-5

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9.3.1.4 JTAG Device Identification Number (JTAGID) .................................................... 9-5

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Chapter 10

Internal Clocks and Bus Architecture

10.1 Introduction ................................................................................................................... 10-1

10.1.1 Block Diagram .......................................................................................................... 10-1

10.1.2 Clocking Overview ................................................................................................... 10-2

10.1.3 Internal Bus Overview .............................................................................................. 10-2

10.1.4 XL Bus Features ....................................................................................................... 10-3

10.1.5 Internal Bus Transaction Summaries ........................................................................ 10-3

10.1.6 XL Bus Interface Operations .................................................................................... 10-3

10.1.6.1 Basic Transfer Protocol ........................................................................................ 10-3

10.1.6.2 Address Pipelines .................................................................................................. 10-4

10.2 PLL ............................................................................................................................... 10-5

10.2.1 PLL Memory Map/Register Descriptions ................................................................. 10-5

10.2.2 System PLL Control Register (SPCR) ..................................................................... 10-5

10.3 XL Bus Arbiter ............................................................................................................. 10-6

10.3.1 Features ..................................................................................................................... 10-6

10.3.2 Arbiter Functional Description ................................................................................. 10-6

10.3.2.1 Prioritization ......................................................................................................... 10-6

10.3.2.2 Bus Grant Mechanism .......................................................................................... 10-7

10.3.2.3 Watchdog Functions ............................................................................................. 10-8

10.3.3 XLB Arbiter Register Descriptions .......................................................................... 10-8

10.3.3.1 Arbiter Configuration Register (XARB_CFG) .................................................... 10-9

10.3.3.2 Arbiter Version Register (XARB_VER) ............................................................ 10-10

10.3.3.3 Arbiter Status Register (XARB_SR) .................................................................. 10-11

10.3.3.4 Arbiter Interrupt Mask Register (XARB_IMR) ................................................. 10-11

10.3.3.5 Arbiter Address Capture Register (XARB_ADRCAP) ...................................... 10-13

10.3.3.6 Arbiter Bus Signal Capture Register (XARB_SIGCAP) ................................... 10-13

10.3.3.7 Arbiter Address Tenure Time Out Register (XARB_ADRTO) ......................... 10-14

10.3.3.8 Arbiter Data Tenure Time Out Register (XARB_DATTO) ............................... 10-15

10.3.3.9 Arbiter Bus Activity Time Out Register (XARB_BUSTO) ............................... 10-16

10.3.3.10 Arbiter Master Priority Enable Register (XARB_PRIEN) ................................. 10-16

10.3.3.11 Arbiter Master Priority Register (XARB_PRI) .................................................. 10-17

Chapter 11

General Purpose Timers (GPT)

11.1 Introduction ................................................................................................................... 11-1

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11.1.1 Overview ................................................................................................................... 11-1

11.1.2 Modes of Operation .................................................................................................. 11-1

11.2 External Signals ............................................................................................................ 11-2

11.3 Memory Map/Register Definition ................................................................................ 11-2

11.3.1 GPT Enable and Mode Select Register (GMSn) ...................................................... 11-3

11.3.2 GPT Counter Input Register (GCIRn) ...................................................................... 11-5

11.3.3 GPT PWM Configuration Register (GPWMn) ........................................................ 11-6

11.3.4 GPT Status Register (GSRn) .................................................................................... 11-7

11.4 Functional Description .................................................................................................. 11-8

11.4.1 Timer Configuration Method .................................................................................... 11-8

11.4.2 Programming Notes .................................................................................................. 11-8

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Chapter 12

Slice Timers (SLT)

12.1 Introduction ................................................................................................................... 12-1

12.1.1 Overview ................................................................................................................... 12-1

12.2 Memory Map/Register Definition ................................................................................ 12-1

12.2.1 SLT Terminal Count Register (STCNTn) ................................................................ 12-2

12.2.2 SLT Control Register (SCRn) ................................................................................... 12-2

12.2.3 SLT Timer Count Register (SCNTn) ........................................................................ 12-3

12.2.4 SLT Status Register (SSRn) ..................................................................................... 12-4

Chapter 13

Interrupt Controller

13.1 Introduction ................................................................................................................... 13-1

13.1.1 68K/ColdFire Interrupt Architecture Overview ....................................................... 13-1

13.1.1.1 Interrupt Controller Theory of Operation ............................................................. 13-2

13.2 Memory Map/Register Descriptions ............................................................................. 13-4

13.2.1 Register Descriptions ................................................................................................ 13-5

13.2.1.1 Interrupt Pending Registers (IPRH, IPRL) ........................................................... 13-5

13.2.1.2 Interrupt Mask Register (IMRH, IMRL) .............................................................. 13-7

13.2.1.3 Interrupt Force Registers (INTFRCH, INTFRCL) ............................................... 13-8

13.2.1.4 Interrupt Request Level Register (IRLR) ........................................................... 13-10

13.2.1.5 Interrupt Acknowledge Level and Priority Register (IACKLPR) ...................... 13-10

13.2.1.6 Interrupt Control Registers 1–63 (ICRn) ............................................................ 13-11

13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) ......... 13-13

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Chapter 14

Edge Port Module (EPORT)

14.1 Introduction ................................................................................................................... 14-1

14.2 Interrupt/General-Purpose I/O Pin Descriptions ........................................................... 14-1

14.3 Memory Map/Register Definition ................................................................................ 14-2

14.3.1 Memory Map ............................................................................................................ 14-2

14.3.2 Register Descriptions ................................................................................................ 14-2

14.3.2.1 EPORT Pin Assignment Register (EPPAR) ......................................................... 14-3

14.3.2.2 EPORT Data Direction Register (EPDDR) .......................................................... 14-3

14.3.2.3 Edge Port Interrupt Enable Register (EPIER) ...................................................... 14-4

14.3.2.4 Edge Port Data Register (EPDR) .......................................................................... 14-4

14.3.2.5 Edge Port Pin Data Register (EPPDR) ................................................................. 14-5

14.3.2.6 Edge Port Flag Register (EPFR) ........................................................................... 14-5

Chapter 15

GPIO

15.1 Introduction ................................................................................................................... 15-1

15.1.1 Overview ................................................................................................................... 15-2

15.1.2 Features ..................................................................................................................... 15-3

15.2 External Pin Description ............................................................................................... 15-3

15.3 Memory Map/Register Definition ................................................................................ 15-7

15.3.1 Register Overview .................................................................................................... 15-7

15.3.2 Register Descriptions ................................................................................................ 15-8

15.3.2.1 Port x Output Data Registers (PODR_x) .............................................................. 15-8

15.3.2.2 Port

15.3.2.3 Port x Pin Data/Set Data Registers (PPDSDR_x) ............................................. 15-14

15.3.2.4 Port x Clear Output Data Registers (PCLRR_x) ................................................ 15-18

15.3.2.5 Port x Pin Assignment Registers (PAR_x) ......................................................... 15-21

15.3.2.6 FlexBus Chip Select Pin Assignment Register (PAR_FBCS) ........................... 15-22

15.3.2.7 DMA Pin Assignment Register (PAR_DMA) ................................................... 15-23

15.3.2.8 FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ) ........................... 15-23

15.3.2.9 PCI Grant Pin Assignment Register (PAR_PCIBG) .......................................... 15-25

15.3.2.10 PCI Request Pin Assignment Register (PAR_PCIBR) ...................................... 15-26

15.3.2.11 PSC3 Pin Assignment Register (PAR_PSC3) .................................................... 15-27

15.3.2.12 PSC2 Pin Assignment Register (PAR_PSC2) .................................................... 15-28

15.3.2.13 PSC1 Pin Assignment Register (PAR_PSC1) .................................................... 15-28

15.3.2.14 PSC0 Pin Assignment Register (PAR_PSC0) .................................................... 15-29

15.3.2.15 DSPI Pin Assignment Register (PAR_DSPI) ..................................................... 15-30

15.3.2.16 General Purpose Timer Pin Assignment Register (PAR_TIMER) .................... 15-31

x Data Direction Registers (PDDR_x) ........................................................ 15-11

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15.4 Functional Description ................................................................................................ 15-32

15.4.1 Overview ................................................................................................................. 15-32

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Chapter 16

32-Kbyte System SRAM

16.1 Introduction ................................................................................................................... 16-1

16.1.1 Block Diagram .......................................................................................................... 16-1

16.1.2 Features ..................................................................................................................... 16-2

16.1.3 Overview ................................................................................................................... 16-2

16.2 Memory Map/Register Definition ................................................................................ 16-2

16.2.1 System SRAM Configuration Register (SSCR) ....................................................... 16-3

16.2.2 Transfer Count Configuration Register (TCCR) ..................................................... 16-4

16.2.3 Transfer Count Configuration Register—DMA Read Channel (TCCRDR) ............ 16-5

16.2.4 Transfer Count Configuration Register—DMA Write Channel (TCCRDW) .......... 16-6

16.2.5 Transfer Count Configuration Register—SEC (TCCRSEC) .................................... 16-7

16.3 Functional Description .................................................................................................. 16-8

Chapter 17

FlexBus

17.1 Introduction ................................................................................................................... 17-1

17.1.1 Overview ................................................................................................................... 17-1

17.1.2 Features ..................................................................................................................... 17-1

17.1.3 Modes of Operation .................................................................................................. 17-1

17.2 Byte Lanes .................................................................................................................... 17-2

17.3 Address Latch ............................................................................................................... 17-2

17.4 External Signals ............................................................................................................ 17-3

17.4.1 Chip-Select (FBCS

17.4.2 Address/Data Bus (AD[31:0]) .................................................................................. 17-4

17.4.3 Address Latch Enable (ALE) .................................................................................... 17-4

17.4.4 Read/Write (R/W) ..................................................................................................... 17-4

17.4.5 Transfer Burst (TBST

17.4.6 Transfer Size (TSIZ[1:0]) ......................................................................................... 17-4

17.4.7 Byte Selects (BE

17.4.8 Output Enable (OE

17.4.9 Transfer Acknowledge (TA

17.5 Chip-Select Operation ................................................................................................... 17-6

17.5.1 General Chip-Select Operation ................................................................................. 17-6

17.5.1.1 8-, 16-, and 32-Bit Port Sizing .............................................................................. 17-6

[5:0]) .......................................................................................... 17-4

) .............................................................................................. 17-4

/BWE[3:0]) .................................................................................... 17-5

) .................................................................................................. 17-5

) ..................................................................................... 17-5

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17.5.1.2 Global Chip-Select Operation ............................................................................... 17-6

17.5.2 Chip-Select Registers ................................................................................................ 17-7

17.5.2.1 Chip-Select Address Registers (CSAR0–CSAR5) ............................................... 17-8

17.5.2.2 Chip-Select Mask Registers (CSMR0–CSMR5) .................................................. 17-9

17.5.2.3 Chip-Select Control Registers (CSCR0–CSCR5) .............................................. 17-10

17.6 Functional Description ................................................................................................ 17-12

17.6.1 Data Transfer Operation ......................................................................................... 17-12

17.6.2 Data Byte Alignment and Physical Connections .................................................... 17-12

17.6.3 Address/Data Bus Multiplexing .............................................................................. 17-13

17.6.4 Bus Cycle Execution ............................................................................................... 17-13

17.6.4.1 Data Transfer Cycle States ................................................................................. 17-14

17.6.5 FlexBus Timing Examples ...................................................................................... 17-15

17.6.5.1 Basic Read Bus Cycle ......................................................................................... 17-15

17.6.5.2 Basic Write Bus Cycle ........................................................................................ 17-16

17.6.5.3 Bus Cycle Multiplexing ...................................................................................... 17-17

17.6.5.4 Timing Variations ............................................................................................... 17-21

17.6.6 Burst Cycles ............................................................................................................ 17-26

17.6.7 Misaligned Operands .............................................................................................. 17-31

17.6.8 Bus Errors ............................................................................................................... 17-32

Chapter 18

SDRAM Controller (SDRAMC)

18.1 Introduction ................................................................................................................... 18-1

18.2 Overview ....................................................................................................................... 18-1

18.2.1 Features ..................................................................................................................... 18-1

18.2.2 Terminology .............................................................................................................. 18-1

18.2.3 Block Diagram .......................................................................................................... 18-2

18.3 External Signal Description .......................................................................................... 18-2

18.3.1 SDRAM Data Bus (SDDATA[31:0]) ....................................................................... 18-2

18.3.2 SDRAM Address Bus (SDADDR[12:0]) ................................................................. 18-2

18.3.3 SDRAM Bank Addresses (SDBA[1:0]) ................................................................... 18-2

18.3.4 SDRAM Row Address Strobe (RAS) ....................................................................... 18-3

18.3.5 SDRAM Column Address Strobe (CAS

18.3.6 SDRAM Chip Selects (SDCS

[3:0]) .......................................................................... 18-3

18.3.7 SDRAM Write Data Byte Mask (SDDM[3:0]) ........................................................ 18-3

18.3.8 SDRAM Data Strobe (SDDQS[3:0]) ........................................................................ 18-3

18.3.9 SDRAM Clock (SDCLK[1:0]) ................................................................................. 18-3

18.3.10 Inverted SDRAM Clock (SDCLK[1:0]) ................................................................... 18-3

18.3.11 SDRAM Write Enable (SDWE

) ............................................................................... 18-3

18.3.12 SDRAM Clock Enable (SDCKE) ............................................................................. 18-4

) ................................................................. 18-3

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18.3.13 SDR SDRAM Data Strobe (SDRDQS) .................................................................... 18-4

18.3.14 SDRAM Memory Supply (SDVDD) ........................................................................ 18-4

18.3.15 SDRAM Reference Voltage (VREF) ....................................................................... 18-4

18.4 Interface Recommendations ......................................................................................... 18-4

18.4.1 Supported Memory Configurations .......................................................................... 18-4

18.4.2 SDRAM SDR Connections ...................................................................................... 18-6

18.4.3 SDRAM DDR Component Connections .................................................................. 18-6

18.4.4 SDRAM DDR DIMM Connections ......................................................................... 18-7

18.4.5 DDR SDRAM Layout Considerations ..................................................................... 18-8

18.4.5.1 Termination Example ........................................................................................... 18-9

18.5 SDRAM Overview ....................................................................................................... 18-9

18.5.1 SDRAM Commands ................................................................................................. 18-9

18.5.1.1 Row and Bank Active Command (ACTV) ......................................................... 18-10

18.5.1.2 Read Command (READ) .................................................................................... 18-10

18.5.1.3 Write Command (WRITE) ................................................................................. 18-10

18.5.1.4 Precharge All Banks Command (PALL) ............................................................ 18-11

18.5.1.5 Load Mode/Extended Mode Register Command (LMR, LEMR) ...................... 18-11

18.5.1.6 Auto Refresh Command (REF) .......................................................................... 18-13

18.5.1.7 Self-Refresh (SREF) and Power-Down (PDWN) Commands ........................... 18-13

18.5.2 Power-Up Initialization ........................................................................................... 18-13

18.5.2.1 SDR Initialization ............................................................................................... 18-14

18.5.2.2 DDR Initialization .............................................................................................. 18-14

18.6 Functional Overview ................................................................................................... 18-15

18.6.1 Page Management ................................................................................................... 18-15

18.6.2 Transfer Size ........................................................................................................... 18-15

18.7 Memory Map/Register Definition .............................................................................. 18-16

18.7.1 SDRAM Drive Strength Register (SDRAMDS) .................................................... 18-17

18.7.2 SDRAM Chip Select Configuration Registers (CSnCFG) ..................................... 18-18

18.7.3 SDRAM Mode/Extended Mode Register (SDMR) ................................................ 18-19

18.7.4 SDRAM Control Register (SDCR) ......................................................................... 18-20

18.7.5 SDRAM Configuration Register 1 (SDCFG1) ....................................................... 18-21

18.7.6 SDRAM Configuration Register 2 (SDCFG2) ....................................................... 18-23

18.8 SDRAM Example ....................................................................................................... 18-24

18.8.1 SDRAM Signal Drive Strength Settings ................................................................ 18-25

18.8.2 SDRAM Chip Select Settings ................................................................................. 18-25

18.8.3 SDRAM Configuration 1 Register Settings ............................................................ 18-26

18.8.4 SDRAM Configuration 2 Register Settings ............................................................ 18-27

18.8.5 SDRAM Control Register Settings and PALL command ...................................... 18-27

18.8.6 Set the Extended Mode Register ............................................................................. 18-29

18.8.7 Set the Mode Register and Reset DLL ................................................................... 18-29

18.8.8 Issue a PALL command .......................................................................................... 18-30

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18.8.9 Perform Two Refresh Cycles .................................................................................. 18-31

18.8.10 Clear the Reset DLL Bit in the Mode Register ...................................................... 18-32

18.8.11 Enable Automatic Refresh and Lock Mode Register ............................................ 18-33

18.8.12 Initialization Code ................................................................................................... 18-34

Chapter 19

PCI Bus Controller

19.1 Introduction ................................................................................................................... 19-1

19.1.1 Block Diagram .......................................................................................................... 19-1

19.1.2 Overview ................................................................................................................... 19-1

19.1.3 Features ..................................................................................................................... 19-1

19.2 External Signal Description .......................................................................................... 19-2

19.2.1 Address/Data Bus (PCIAD[31:0]) ............................................................................ 19-2

19.2.2 Command/Byte Enables (PCICXBE[3:0]) ............................................................... 19-2

19.2.3 Device Select (PCIDEVSEL) ................................................................................... 19-3

19.2.4 Frame (PCIFRAME) ................................................................................................. 19-3

19.2.5 Initialization Device Select (PCIIDSEL) .................................................................. 19-3

19.2.6 Initiator Ready (PCIIRDY) ....................................................................................... 19-3

19.2.7 Parity (PCIPAR) ....................................................................................................... 19-3

19.2.8 PCI Clock (CLKIN) .................................................................................................. 19-3

19.2.9 Parity Error (PCIPERR) ............................................................................................ 19-3

19.2.10 Reset (PCIRESET) .................................................................................................. 19-3

19.2.11 System Error (PCISERR) ........................................................................................ 19-3

19.2.12 Stop (PCISTOP) ...................................................................................................... 19-3

19.2.13 Target Ready (PCITRDY) ....................................................................................... 19-4

19.3 Memory Map/Register Definition ................................................................................ 19-4

19.3.1 PCI Type 0 Configuration Registers ......................................................................... 19-6

19.3.1.1 Device ID/Vendor ID Register (PCIIDR)—PCI Dword Addr 0 .......................... 19-7

19.3.1.2 PCI Status/Command Register (PCISCR)—PCI Dword Addr 1 ......................... 19-7

19.3.1.3 Revision ID/Class Code Register (PCICCRIR)—PCI Dword 3 .......................... 19-9

19.3.1.4 Configuration 1 Register (PCICR1)—PCI Dword 3 .......................................... 19-10

19.3.1.5 Base Address Register 0 (PCIBAR0)—PCI Dword 4 ........................................ 19-11

19.3.1.6 Base Address Register 1 (PCIBAR1)—PCI Dword 5 ........................................ 19-12

19.3.1.7 CardBus CIS Pointer Register PCICCPR—PCI Dword A ................................ 19-12

19.3.1.8 Subsystem ID/Subsystem Vendor ID Registers PCISID—PCI Dword B .......... 19-12

19.3.1.9 Expansion ROM Base Address PCIERBAR—PCI Dword C ............................ 19-13

19.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR—PCI Dword D ................................... 19-13

19.3.1.11 Configuration 2 Register (PCICR2)—PCI Dword F .......................................... 19-13

19.3.2 General Control/Status Registers ............................................................................ 19-13

19.3.2.1 Global Status/Control Register (PCIGSCR) ....................................................... 19-14

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19.3.2.2 Target Base Address Translation Register 0 (PCITBATR0) ............................. 19-15

19.3.2.3 Target Base Address Translation Register 1 (PCITBATR1) ............................. 19-16

19.3.2.4 Target Control Register (PCITCR) ..................................................................... 19-16

19.3.2.5 Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR) ......... 19-17

19.3.2.6 Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR) ......... 19-18

19.3.2.7 Initiator Window 2 Base/Translation Address Register (PCIIW2BTAR) ......... 19-19

19.3.2.8 Initiator Window Configuration Register (PCIIWCR) ....................................... 19-19

19.3.2.9 Initiator Control Register (PCIICR) ................................................................... 19-20

19.3.2.10 Initiator Status Register (PCIISR) ...................................................................... 19-21

19.3.2.11 Configuration Address Register (PCICAR) ....................................................... 19-22

19.3.3 Communication Subsystem Interface Registers ..................................................... 19-23

19.3.3.1 Comm Bus FIFO Transmit Interface .................................................................. 19-23

19.3.3.2 Comm Bus FIFO Receive Interface ................................................................... 19-35

19.4 Functional Description ................................................................................................ 19-48

19.4.1 PCI Bus Protocol .................................................................................................... 19-48

19.4.1.1 PCI Bus Background .......................................................................................... 19-48

19.4.1.2 Basic Transfer Control ........................................................................................ 19-49

19.4.1.3 PCI Transactions ................................................................................................. 19-49

19.4.1.4 PCI Bus Commands ............................................................................................ 19-51

19.4.1.5 Addressing .......................................................................................................... 19-52

19.4.2 Initiator Arbitration ................................................................................................. 19-55

19.4.2.1 Priority Scheme .................................................................................................. 19-56

19.4.3 Configuration Interface ........................................................................................... 19-56

19.4.4 XL Bus Initiator Interface ....................................................................................... 19-56

19.4.4.1 Endian Translation .............................................................................................. 19-58

19.4.4.2 Configuration Mechanism .................................................................................. 19-60

19.4.4.3 Interrupt Acknowledge Transactions .................................................................. 19-62

19.4.4.4 Special Cycle Transactions ................................................................................. 19-62

19.4.4.5 Transaction Termination ..................................................................................... 19-63

19.4.5 XL Bus Target Interface ........................................................................................ 19-63

19.4.5.1 Reads from Local Memory ................................................................................. 19-64

19.4.5.2 Local Memory Writes ......................................................................................... 19-64

19.4.5.3 Data Translation .................................................................................................. 19-64

19.4.5.4 Target Abort ........................................................................................................ 19-66

19.4.5.5 Latrule Disable .................................................................................................... 19-66

19.4.6 Communication Subsystem Initiator Interface ....................................................... 19-66

19.4.6.1 Access Width ...................................................................................................... 19-67

19.4.6.2 Addressing .......................................................................................................... 19-67

19.4.6.3 Data Translation .................................................................................................. 19-68

19.4.6.4 Initialization ........................................................................................................ 19-68

19.4.6.5 Restart and Reset ................................................................................................ 19-68

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19.4.6.6 PCI Commands ................................................................................................... 19-69

19.4.6.7 FIFO Considerations ........................................................................................... 19-69

19.4.6.8 Alarms ................................................................................................................. 19-69

19.4.6.9 Bus Errors ........................................................................................................... 19-70

19.4.7 PCI Clock Scheme .................................................................................................. 19-70

19.4.8 Interrupts ................................................................................................................. 19-70

19.4.8.1 PCI Bus Interrupts .............................................................................................. 19-70

19.4.8.2 Internal Interrupt ................................................................................................. 19-70

19.5 Application Information ............................................................................................. 19-70

19.5.1 XL Bus-Initiated Transaction Mapping .................................................................. 19-70

19.5.2 Address Maps ......................................................................................................... 19-71

19.5.2.1 Address Translation ............................................................................................ 19-72

19.6 XL Bus Arbitration Priority ........................................................................................ 19-75

Chapter 20

PCI Bus Arbiter Module

20.1 Introduction ................................................................................................................... 20-1

20.1.1 Block Diagram .......................................................................................................... 20-1

20.1.2 Overview ................................................................................................................... 20-1

20.1.3 Features ..................................................................................................................... 20-2

20.2 External Signal Description .......................................................................................... 20-2

20.2.1 Frame (PCIFRM) ...................................................................................................... 20-2

20.2.2 Initiator Ready (PCIIRDY) ....................................................................................... 20-2

20.2.3 PCI Clock (CLKIN) .................................................................................................. 20-2

20.2.4 External Bus Grant (PCIBG[4:1]) ............................................................................ 20-2

20.2.5 External Bus Grant/Request Output (PCIBG0

/PCIREQOUT) ................................ 20-3

20.2.6 External Bus Request (PCIBR[4:1]) ......................................................................... 20-3

20.2.7 External Request/Grant Input (PCIBR0/PCIGNTIN) .............................................. 20-3

20.3 Register Definition ........................................................................................................ 20-3

20.3.1 PCI Arbiter Control Register (PACR) ...................................................................... 20-3

20.3.2 PCI Arbiter Status Register (PASR) ......................................................................... 20-5

20.4 Functional Description .................................................................................................. 20-5

20.4.1 External PCI Requests .............................................................................................. 20-5

20.4.2 Arbitration ................................................................................................................. 20-6

20.4.2.1 Hidden Bus Arbitration ......................................................................................... 20-6

20.4.2.2 Arbitration Scheme ............................................................................................... 20-6

20.4.2.3 Arbitration Latency ............................................................................................... 20-7

20.4.2.4 Arbitration Examples ............................................................................................ 20-7

20.4.3 Master Time-Out ....................................................................................................... 20-9

20.5 Reset ............................................................................................................................ 20-10

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20.6 Interrupts ..................................................................................................................... 20-10

Chapter 21

FlexCAN

21.1 Introduction ................................................................................................................... 21-1

21.1.1 Block Diagram .......................................................................................................... 21-1

21.1.2 The CAN System ...................................................................................................... 21-2

21.1.3 Features ..................................................................................................................... 21-3

21.1.4 Modes of Operation .................................................................................................. 21-3

21.1.4.1 Normal Mode ........................................................................................................ 21-3

21.1.4.2 Freeze Mode ......................................................................................................... 21-3

21.1.4.3 Module Disabled Mode ........................................................................................ 21-4

21.1.4.4 Loop-Back Mode .................................................................................................. 21-4

21.1.4.5 Listen-Only Mode ................................................................................................. 21-4

21.2 External Signals ............................................................................................................ 21-5

21.2.1 CANTX[1:0] ............................................................................................................. 21-5

21.2.2 CANRX[1:0] ............................................................................................................. 21-5

21.3 Memory Map/Register Definition ................................................................................ 21-5

21.3.1 FlexCAN Memory Map ............................................................................................ 21-5

21.3.2 Register Descriptions ................................................................................................ 21-6

21.3.2.1 FlexCAN Module Configuration Register (CANMCR) ....................................... 21-6

21.3.2.2 FlexCAN Control Register (CANCTRL) ............................................................. 21-8

21.3.2.3 FlexCAN Timer Register (TIMER) .................................................................... 21-10

21.3.2.4 Rx Mask Registers .............................................................................................. 21-11

21.3.2.5 FlexCAN Error Counter Register (ERRCNT) .................................................... 21-14

21.3.2.6 FlexCAN Error and Status Register (ERRSTAT) .............................................. 21-15

21.3.2.7 Interrupt Mask Register (IMASK) ...................................................................... 21-17

21.3.2.8 Interrupt Flag Register (IFLAG) ........................................................................ 21-18

21.4 Functional Overview ................................................................................................... 21-19

21.4.1 Message Buffer Structure ....................................................................................... 21-19

21.4.2 Message Buffer Memory Map ................................................................................ 21-22

21.4.3 Transmit Process ..................................................................................................... 21-23

21.4.4 Arbitration Process ................................................................................................. 21-24

21.4.5 Receive Process ...................................................................................................... 21-24

21.4.5.1 Self-Received Frames ......................................................................................... 21-25

21.4.6 Message Buffer Handling ....................................................................................... 21-25

21.4.6.1 Serial Message Buffers (SMBs) ......................................................................... 21-26

21.4.6.2 Transmit Message Buffer Deactivation .............................................................. 21-26

21.4.6.3 Receive Message Buffer Deactivation ................................................................ 21-26

21.4.6.4 Locking and Releasing Message Buffers ........................................................... 21-27

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21.4.7 CAN Protocol Related Frames ............................................................................... 21-27

21.4.7.1 Remote Frames ................................................................................................... 21-27

21.4.7.2 Overload Frames ................................................................................................. 21-28

21.4.8 Time Stamp ............................................................................................................. 21-28

21.4.9 Bit Timing ............................................................................................................... 21-28

21.4.9.1 Configuring the FlexCAN Bit Timing ................................................................ 21-29

21.4.10 FlexCAN Error Counters ....................................................................................... 21-30

21.5 FlexCAN Initialization Sequence ............................................................................... 21-31

21.5.1 Interrupts ................................................................................................................. 21-31

Chapter 22

Integrated Security Engine (SEC)

22.1 Features ......................................................................................................................... 22-1

22.2 ColdFire Security Architecture ..................................................................................... 22-1

22.3 Block Diagram .............................................................................................................. 22-2

22.4 Overview ....................................................................................................................... 22-2

22.4.1 Bus Interface ............................................................................................................. 22-2

22.4.2 SEC Controller Unit .................................................................................................. 22-3

22.4.2.1 Static EU Access ................................................................................................... 22-3

22.4.2.2 Dynamic EU Access ............................................................................................. 22-3

22.4.3 Crypto-Channels ....................................................................................................... 22-3

22.4.4 Execution Units (EUs) .............................................................................................. 22-4

22.4.4.1 Data Encryption Standard Execution Unit (DEU) ................................................ 22-4

22.4.4.2 Arc Four Execution Unit (AFEU) ........................................................................ 22-5

22.4.4.3 Advanced Encryption Standard Execution Unit (AESU) ..................................... 22-6

22.4.4.4 Message Digest Execution Unit (MDEU) ............................................................ 22-6

22.4.4.5 Random Number Generator (RNG) ...................................................................... 22-8

22.5 Memory Map/Register Definition ................................................................................ 22-8

22.6 Controller .................................................................................................................... 22-10

22.6.1 EU Access ............................................................................................................... 22-11

22.6.2 Multiple EU Assignment ........................................................................................ 22-11

22.6.3 Multiple Channels ................................................................................................... 22-11

22.6.4 Controller Registers ................................................................................................ 22-11

22.6.4.1 EU Assignment Control Registers (EUACRH and EUACRL) .......................... 22-11

22.6.4.2 EU Assignment Status Registers (EUASRH and EUASRL) ............................. 22-13

22.6.4.3 SEC Interrupt Mask Registers (SIMRH and SIMRL) ........................................ 22-14

22.6.4.4 SEC Interrupt Status Registers (SISRH and SISRL) .......................................... 22-14

22.6.4.5 SEC Interrupt Control Registers (SICRH and SICRL) ...................................... 22-14

22.6.4.6 SEC ID Register (SIDR) ..................................................................................... 22-16

22.6.4.7 SEC Master Control Register (SMCR) ............................................................... 22-17

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22.6.4.8 Master Error Address Register (MEAR) ............................................................ 22-18

22.7 Channels ...................................................................................................................... 22-18

22.7.1 Crypto-Channel Registers ....................................................................................... 22-19

22.7.1.1 Crypto-Channel Configuration Registers (CCCRn) ........................................... 22-19

22.7.1.2 Crypto-Channel Pointer Status Registers (CCPSRHn and CCPSRLn) .............. 22-21

22.7.1.3 Crypto-Channel Current Descriptor Pointer Register (CDPRn) ........................ 22-27

22.7.1.4 Fetch Register (FRn) ........................................................................................... 22-27

22.7.1.5 Data Packet Descriptor Buffer (CDBUFn) ......................................................... 22-28

22.8 ARC Four Execution Unit (AFEU) ............................................................................ 22-28

22.8.1 AFEU Register Map ............................................................................................... 22-28

22.8.2 AFEU Reset Control Register (AFRCR) ................................................................ 22-28

22.8.3 AFEU Status Register (AFSR) ............................................................................... 22-29

22.8.4 AFEU Interrupt Status Register (AFISR) ............................................................... 22-31

22.8.5 AFEU Interrupt Mask Register (AFIMR) .............................................................. 22-32

22.9 Data Encryption Standard Execution Units (DEU) .................................................... 22-34

22.9.1 DEU Register Map .................................................................................................. 22-34

22.9.2 DEU Reset Control Register (DRCR) .................................................................... 22-34

22.9.3 DEU Status Register (DSR) .................................................................................... 22-35

22.9.4 DEU Interrupt Status Register (DISR) ................................................................... 22-37

22.9.5 DEU Interrupt Mask Register (DIMR) ................................................................... 22-39

22.10 Message Digest Execution Unit (MDEU) .................................................................. 22-40

22.10.1 MDEU Register Map .............................................................................................. 22-40

22.10.2 MDEU Reset Control Register (MDRCR) ............................................................. 22-41

22.10.3 MDEU Status Register (MDSR) ............................................................................. 22-41

22.10.4 MDEU Interrupt Status Register (MDISR) ............................................................ 22-43

22.10.5 MDEU Interrupt Mask Register (MDIMR) ............................................................ 22-44

22.11 RNG Execution Unit (RNG) ...................................................................................... 22-46

22.11.1 RNG Register Map ................................................................................................. 22-46

22.11.2 RNG Reset Control Register (RNGRCR) .............................................................. 22-46

22.11.3 RNG Status Register (RNGSR) .............................................................................. 22-47

22.11.4 RNG Interrupt Status Register (RNGISR) .............................................................. 22-48

22.11.5 RNG Interrupt Mask Register (RNGIMR) ............................................................. 22-49

22.12 Advanced Encryption Standard Execution Units (AESU) ....................................... 22-50

22.12.1 AESU Register Map ............................................................................................... 22-50

22.12.2 AESU Reset Control Register (AESRCR) ............................................................. 22-50

22.12.3 AESU Status Register (AESSR) ............................................................................. 22-51

22.12.4 AESU Interrupt Status Register (AESISR) ............................................................ 22-53

22.12.5 AESU Interrupt Mask Register (AESIMR) ............................................................ 22-54

22.13 Descriptors .................................................................................................................. 22-56

22.13.1 Descriptor Structure ................................................................................................ 22-56

22.13.1.1 Descriptor Header ............................................................................................... 22-57

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22.13.1.2 Descriptor Length and Pointer Fields ................................................................. 22-60

22.13.1.3 Null Fields .......................................................................................................... 22-61

22.13.1.4 Next Descriptor Pointer ...................................................................................... 22-61

22.13.2 Descriptor Chaining ................................................................................................ 22-61

22.13.3 Descriptor Type Formats ....................................................................................... 22-62

22.13.4 Descriptor Classes ................................................................................................... 22-64

22.13.4.1 Dynamic Descriptors .......................................................................................... 22-64

22.13.4.2 Static Descriptors ................................................................................................ 22-65

22.14 EU Specific Data Packet Descriptors ........................................................................ 22-67

22.14.1 AFEU Mode Options and Data Packet Descriptors ................................................ 22-67

22.14.1.1 Dynamically Assigned AFEU ............................................................................ 22-68

22.14.1.2 Statically Assigned AFEU .................................................................................. 22-69

22.14.2 DEU Mode Options and Data Packet Descriptors .................................................. 22-72

22.14.2.1 Dynamically Assigned DEU ............................................................................... 22-73

22.14.2.2 Statically Assigned DEU .................................................................................... 22-74

22.14.3 MDEU Mode Options and Data Packet Descriptors .............................................. 22-77

22.14.3.1 Recommended Settings for MDEU Mode Register ........................................... 22-78

22.14.3.2 Dynamically Assigned MDEU ........................................................................... 22-78

22.14.3.3 Statically Assigned MDEU ................................................................................ 22-79

22.14.4 RNG Data Packet Descriptors ................................................................................ 22-82

22.14.5 AESU Mode Options and Data Packet Descriptors ................................................ 22-83

22.14.5.1 Dynamically Assigned AESU ............................................................................ 22-84

22.14.5.2 Statically Assigned AESU .................................................................................. 22-85

22.14.5.3 AESU-CCM Mode Descriptor ........................................................................... 22-88

22.14.6 Multi-Function Data Packet Descriptors ................................................................ 22-90

22.14.6.1 Snooping ............................................................................................................. 22-91

22.14.6.2 Dynamic Multi-Function Descriptor Formats .................................................... 22-91

22.14.6.3 Static Multi-Function Descriptor Formats .......................................................... 22-95

22.14.6.4 SSLv3.1/TLS 1.0 Processing Descriptors ........................................................ 22-102

Chapter 23

IEEE 1149.1 Test Access Port (JTAG)

23.1 Introduction ................................................................................................................... 23-1

23.1.1 Block Diagram .......................................................................................................... 23-1

23.1.2 Features ..................................................................................................................... 23-2

23.1.3 Modes of Operation .................................................................................................. 23-2

23.2 External Signal Description .......................................................................................... 23-2

23.2.1 Detailed Signal Description ...................................................................................... 23-2

23.2.1.1 Test Mode 0 (MTMOD0) ..................................................................................... 23-2

23.2.1.2 Test Clock Input (TCK) ........................................................................................ 23-3

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23.2.1.3 Test Mode Select/Breakpoint (TMS/BKPT) ........................................................ 23-3

23.2.1.4 Test Data Input/Development Serial Input (TDI/DSI) ......................................... 23-3

23.2.1.5 Test Reset/Development Serial Clock (TRST/DSCLK) ...................................... 23-4

23.2.1.6 Test Data Output/Development Serial Output (TDO/DSO) ................................. 23-4

23.3 Memory Map/Register Definition ................................................................................ 23-4

23.3.1 Memory Map ............................................................................................................ 23-4

23.3.2 Register Descriptions ................................................................................................ 23-4

23.3.2.1 Instruction Shift Register (IR) .............................................................................. 23-4

23.3.2.2 IDCODE Register ................................................................................................. 23-4

23.3.2.3 Bypass Register .................................................................................................... 23-5

23.3.2.4 JTAG_CFM_CLKDIV Register ........................................................................... 23-5

23.3.2.5 TEST_CTRL Register .......................................................................................... 23-5

23.3.2.6 Boundary Scan Register ....................................................................................... 23-6

23.4 Functional Description .................................................................................................. 23-6

23.4.1 JTAG Module ........................................................................................................... 23-6

23.4.2 TAP Controller ......................................................................................................... 23-6

23.4.3 JTAG Instructions ..................................................................................................... 23-7

23.4.3.1 External Test Instruction (EXTEST) .................................................................... 23-8

23.4.3.2 IDCODE Instruction ............................................................................................. 23-8

23.4.3.3 SAMPLE/PRELOAD Instruction ......................................................................... 23-8

23.4.3.4 ENABLE_TEST_CTRL Instruction .................................................................... 23-9

23.4.3.5 HIGHZ Instruction ................................................................................................ 23-9

23.4.3.6 CLAMP Instruction .............................................................................................. 23-9

23.4.3.7 BYPASS Instruction ............................................................................................. 23-9

23.5 Initialization/Application Information .......................................................................... 23-9

23.5.1 Restrictions ............................................................................................................... 23-9

23.5.2 Nonscan Chain Operation ......................................................................................... 23-9

Chapter 24

Multichannel DMA

24.1 Introduction ................................................................................................................... 24-1

24.1.1 Block Diagram .......................................................................................................... 24-1

24.1.2 Overview ................................................................................................................... 24-2

24.1.2.1 Master DMA Engine (MDE) ................................................................................ 24-2

24.1.2.2 Address and Data Sequencer (ADS) ..................................................................... 24-2

24.1.2.3 Priority-Task Decoder (PTD) ............................................................................... 24-2

24.1.2.4 Logic Unit with Redundancy Check (LURC) ...................................................... 24-2

24.1.2.5 Debug Unit ............................................................................................................ 24-2

24.1.3 Features ..................................................................................................................... 24-2

24.2 External Signals ............................................................................................................ 24-3

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24.2.1 DREQ[1:0] ............................................................................................................... 24-3

24.2.2 DACK[1:0] .............................................................................................................. 24-3

24.3 Memory Map/Register Definitions ............................................................................... 24-3

24.3.1 DMA Task Memory .................................................................................................. 24-3

24.3.1.1 Task Table ............................................................................................................ 24-3

24.3.1.2 Task Descriptor Table ........................................................................................... 24-3

24.3.1.3 Variable Table ...................................................................................................... 24-4

24.3.1.4 Function Descriptor Table .................................................................................... 24-4

24.3.1.5 Context Save Space .............................................................................................. 24-4

24.3.2 Memory Structure ..................................................................................................... 24-4

24.3.3 DMA Registers ......................................................................................................... 24-5

24.3.3.1 DMA Register Map .............................................................................................. 24-5

24.3.3.2 Task Base Address Register (TaskBAR) .............................................................. 24-6

24.3.3.3 Current Pointer (CP) ............................................................................................. 24-7

24.3.3.4 End Pointer (EP) ................................................................................................... 24-8

24.3.3.5 Variable Pointer (VP) ........................................................................................... 24-8

24.3.3.6 PTD Control (PTD) .............................................................................................. 24-9

24.3.3.7 DMA Interrupt Pending (DIPR) ......................................................................... 24-10

24.3.3.8 DMA Interrupt Mask Register (DIMR) .............................................................. 24-10

24.3.3.9 Task Control Registers (TCRn) .......................................................................... 24-11

24.3.3.10 Priority Registers (PRIORn) ............................................................................... 24-12

24.3.3.11 Initiator Mux Control Register (IMCR) ............................................................. 24-13

24.3.3.12 Task Size Registers (TSKSZ[0:1]) ..................................................................... 24-14

24.3.3.13 Debug Comparator Registers (DBGCOMPn) .................................................... 24-16

24.3.3.14 Debug Control (DBGCTL) ................................................................................. 24-16

24.3.3.15 Debug Status (DBGSTAT) ................................................................................. 24-18

24.3.3.16 PTD Debug Registers ......................................................................................... 24-19

24.3.4 External Request Module Registers ........................................................................ 24-20

24.3.4.1 External Request Module Register Map ............................................................. 24-20

24.3.4.2 External Request Base Address Register (EREQBAR) ..................................... 24-20

24.3.4.3 External Request Address Mask Register (EREQMASK) ................................. 24-21

24.3.4.4 External Request Control Register (EREQCTRL) ............................................. 24-21

24.4 Functional Description ................................................................................................ 24-22

24.4.1 Tasks ....................................................................................................................... 24-22

24.4.2 Descriptors .............................................................................................................. 24-23

24.4.3 Task Initialization ................................................................................................... 24-23

24.4.4 Initiators .................................................................................................................. 24-23

24.4.5 Prioritization ........................................................................................................... 24-24

24.4.6 Context Switch ........................................................................................................ 24-24

24.4.7 Data Movement ....................................................................................................... 24-24

24.4.8 Data Manipulation .................................................................................................. 24-24

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24.4.8.1 LURC Features ................................................................................................... 24-25

24.4.9 Line Buffers ............................................................................................................ 24-26

24.4.9.1 Combine Write Enable ....................................................................................... 24-26

24.4.9.2 Read Line Enable ................................................................................................ 24-26

24.4.9.3 Speculative Prefetch ........................................................................................... 24-26

24.4.10 Termination of Loop ............................................................................................... 24-27

24.4.11 Interrupts ................................................................................................................. 24-27

24.4.12 Debug Unit .............................................................................................................. 24-27

24.5 Programming Model ................................................................................................... 24-27

24.5.1 Register Initialization .............................................................................................. 24-27

24.5.2 Task Memory .......................................................................................................... 24-28

24.5.2.1 Task Table .......................................................................................................... 24-28

24.6 Timing Diagrams ........................................................................................................ 24-30

24.6.1 Level-Triggered Requests ....................................................................................... 24-30

24.6.2 Edge-Triggered Requests ........................................................................................ 24-30

24.6.3 Pipelined Requests .................................................................................................. 24-31

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Chapter 25

Comm Timer Module (CTM)

25.1 Introduction ................................................................................................................... 25-1

25.1.1 Block Diagrams ........................................................................................................ 25-1

25.1.2 Overview ................................................................................................................... 25-2

25.1.3 Comm Timer External Clock[7:0] ............................................................................ 25-3

25.2 Memory Map/Register Definition ................................................................................ 25-3

25.2.1 Timer Module Register Map ..................................................................................... 25-3

25.2.2 Register Descriptions ................................................................................................ 25-4

25.2.2.1 Comm Timer Configuration Register (CTCRn)—Fixed Timer Channel ............. 25-4

25.2.2.2 Comm Timer Configuration Register (CTCRn)—Variable Timer Channel ........ 25-5

25.3 Functional Description .................................................................................................. 25-7

25.3.1 Variable Timer in Baud Clock Generator Mode ...................................................... 25-7

25.3.2 Fixed Timer in Initiator Mode .................................................................................. 25-7

25.3.2.1 Fixed Timer in Initiator Mode Example ............................................................... 25-7

25.3.3 Variable Timer in Initiator Mode .............................................................................. 25-8

25.3.3.1 Variable Timer in Initiator Mode Example .......................................................... 25-8

Chapter 26

Programmable Serial Controller (PSC)

26.1 Introduction ................................................................................................................... 26-1

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26.1.1 Block Diagram .......................................................................................................... 26-1

26.1.2 Overview ................................................................................................................... 26-1

26.1.3 Features ..................................................................................................................... 26-1

26.1.4 Modes of Operation .................................................................................................. 26-1

26.2 Signal Description ......................................................................................................... 26-2

26.2.1 PSCnCTS/PSCBCLK ............................................................................................... 26-2

26.2.2 PScnrts/pscfsync ....................................................................................................... 26-2

26.2.3 PSCnrxd .................................................................................................................... 26-2

26.2.4 pscntxd ...................................................................................................................... 26-3

26.2.5 Signal Properties in Each Mode ................................................................................ 26-3

26.3 Memory Map/Register Definition ................................................................................ 26-3

26.3.1 Overview ................................................................................................................... 26-3

26.3.2 Module Memory Map ............................................................................................... 26-3

26.3.3 Register Descriptions ................................................................................................ 26-5

26.3.3.1 Mode Register 1(PSCMR1n) ................................................................................ 26-5

26.3.3.2 Mode Register 2 (PSCMR2n) ............................................................................... 26-6

26.3.3.3 Status Register (PSCSRn) ..................................................................................... 26-8

26.3.3.4 Clock Select Register (PSCCSRn) ..................................................................... 26-10

26.3.3.5 Command Register (PSCCRn) ........................................................................... 26-11

26.3.3.6 Receiver Buffer (PSCRBn) and Transmitter Buffer (PSCTBn) ......................... 26-14

26.3.3.7 Input Port Change Register (PSCIPCRn) ........................................................... 26-17

26.3.3.8 Auxiliary Control Register (PSCACRn) ............................................................ 26-18

26.3.3.9 Interrupt Status Register (PSCISRn) .................................................................. 26-18

26.3.3.10 Interrupt Mask Register (PSCIMRn) .................................................................. 26-19

26.3.3.11 Counter Timer Registers (PSCCTURn, PSCCTLRn) ........................................ 26-21

26.3.3.12 Input Port (PSCIPn) ............................................................................................ 26-21

26.3.3.13 Output Port Bit Set (PSCOPSETn) ..................................................................... 26-22

26.3.3.14 Output Port Bit Reset (PSCOPRESETn) ............................................................ 26-22

26.3.3.15 PSC/IrDA Control Register (PSCSICRn) .......................................................... 26-23

26.3.3.16 Infrared Control Register 1 (PSCIRCR1n) ......................................................... 26-24

26.3.3.17 Infrared Control Register 2 (PSCIRCR2n) ......................................................... 26-24

26.3.3.18 Infrared SIR Divide Register (PSCIRSDRn) ..................................................... 26-25

26.3.3.19 Infrared MIR Divide Register (PSCIRMDRn) ................................................... 26-25

26.3.3.20 Infrared FIR Divide Register (PSCIRFDRn) ..................................................... 26-26

26.3.3.21 Rx and Tx FIFO Counter Register (PSCRFCNTn, PSCTFCNTn) .................... 26-27

26.3.3.22 Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn) .............................. 26-27

26.3.3.23 Rx and Tx FIFO Status Register (PSCRFSRn, PSCTFSRn) ............................. 26-28

26.3.3.24 Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn) .......................... 26-30

26.3.3.25 Rx and Tx FIFO Alarm Register (PSCRFARn, PSCTFARn) ............................ 26-32

26.3.3.26 Rx and Tx FIFO Read Pointer (PSCRFRPn, PSCTFRPn) ................................. 26-32

26.3.3.27 Rx and Tx FIFO Write Pointer (PSCRFWPn, PSCTFWPn) .............................. 26-33

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26.3.3.28 Rx and Tx FIFO Last Read Frame Pointer (PSCRLRFPn, PSCTLRFPn) ......... 26-33

26.3.3.29 Rx and Tx FIFO Last Write Frame Pointer (PSCRLWFPn, PSCTLWFPn) ...... 26-34

26.4 Functional Description ................................................................................................ 26-35

26.4.1 UART Mode ........................................................................................................... 26-35

26.4.2 Multidrop Mode ...................................................................................................... 26-36

26.4.3 Modem8 Mode ........................................................................................................ 26-37

26.4.4 Modem16 Mode ...................................................................................................... 26-38

26.4.5 AC97 Mode ............................................................................................................. 26-39

26.4.5.1 Transmitter .......................................................................................................... 26-40

26.4.5.2 Receiver .............................................................................................................. 26-40

26.4.5.3 Low Power Mode ............................................................................................... 26-40

26.4.6 SIR Mode ................................................................................................................ 26-41

26.4.7 MIR Mode ............................................................................................................... 26-41

26.4.7.1 Data Format ........................................................................................................ 26-41

26.4.7.2 Serial Interaction Pulse (SIP) .............................................................................. 26-42

26.4.8 FIR Mode ................................................................................................................ 26-42

26.4.8.1 Data Format ........................................................................................................ 26-42

26.4.9 PSC FIFO System ................................................................................................... 26-43

26.4.9.1 RX FIFO ............................................................................................................. 26-44

26.4.9.2 TX FIFO ............................................................................................................. 26-45

26.4.10 Looping Modes ....................................................................................................... 26-46

26.4.10.1 Automatic Echo Mode ........................................................................................ 26-46

26.4.10.2 Local Loopback Mode ........................................................................................ 26-46

26.4.10.3 Remote Loopback Mode ..................................................................................... 26-47

26.5 Resets .......................................................................................................................... 26-47

26.5.1 General .................................................................................................................... 26-47

26.5.2 Description of Reset Operation ............................................................................... 26-47

26.5.2.1 Reset ................................................................................................................... 26-47

26.5.2.2 CRSRX ............................................................................................................... 26-47

26.5.2.3 CRSTX ............................................................................................................... 26-47

26.5.2.4 CRSES ................................................................................................................ 26-47

26.6 Interrupts ..................................................................................................................... 26-48

26.6.1 Description of Interrupt Operation ......................................................................... 26-48

26.6.1.1 Processor Interrupt .............................................................................................. 26-48

26.7 Software Environment ................................................................................................ 26-48

26.7.1 General .................................................................................................................... 26-48

26.7.2 Configuration .......................................................................................................... 26-49

26.7.2.1 UART Mode ....................................................................................................... 26-49

26.7.2.2 Modem8 Mode .................................................................................................... 26-50

26.7.2.3 Modem16 Mode .................................................................................................. 26-51

26.7.2.4 AC97 Mode ........................................................................................................ 26-51

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26.7.2.5 SIR Mode ............................................................................................................ 26-52

26.7.2.6 MIR Mode .......................................................................................................... 26-53

26.7.2.7 FIR Mode ............................................................................................................ 26-54

26.7.3 Programming .......................................................................................................... 26-55

26.7.3.1 MIR Mode .......................................................................................................... 26-55

26.7.3.2 FIR Mode ............................................................................................................ 26-56

Chapter 27

DMA Serial Peripheral Interface (DSPI)

27.1 Overview ....................................................................................................................... 27-1

27.2 Features ......................................................................................................................... 27-1

27.3 Block Diagram .............................................................................................................. 27-2

27.4 Modes of Operation ...................................................................................................... 27-2

27.4.1 Master Mode ............................................................................................................. 27-2

27.4.2 Slave Mode ............................................................................................................... 27-2

27.5 Signal Description ......................................................................................................... 27-3

27.5.1 Overview ................................................................................................................... 27-3

27.5.2 Detailed Signal Descriptions .................................................................................... 27-3

27.5.2.1 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 27-3

27.5.2.2 DSPI Peripheral Chip Selects 2–3 (DSPICS[2:3]) ............................................... 27-3

27.5.2.3 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 27-3

27.5.2.4 DSPI Serial Input (DSPISIN) ............................................................................... 27-4

27.5.2.5 DSPI Serial Output (DSPISOUT) ........................................................................ 27-4

27.5.2.6 DSPI Serial Clock (DSPISCK) ............................................................................. 27-4

27.6 Memory Map and Registers .......................................................................................... 27-4

27.6.1 DSPI Module Configuration Register (DMCR) ....................................................... 27-5

27.6.2 DSPI Transfer Count Register (DTCR) .................................................................... 27-7

27.6.3 DSPI Clock and Transfer Attributes Registers 0–7 (DCTARn) ............................... 27-7

27.6.4 DSPI Status Register (DSR) ................................................................................... 27-11

27.6.5 DSPI DMA/Interrupt Request Select Register (DIRSR) ........................................ 27-13

27.6.6 DSPI Tx FIFO Register (DTFR) ............................................................................ 27-15

27.6.7 DSPI Rx FIFO Register (DRFR) ............................................................................ 27-16

27.6.8 DSPI Tx FIFO Debug Registers 0–3 (DTFDRn) ................................................... 27-17

27.6.9 DSPI Rx FIFO Debug Registers 0–3 (DRFDRn) ................................................... 27-17

27.7 Functional Description ................................................................................................ 27-18

27.7.1 Start and Stop of DSPI Transfers ............................................................................ 27-19

27.7.2 Serial Peripheral Interface (SPI) ............................................................................ 27-20

27.7.2.1 Master Mode ....................................................................................................... 27-20

27.7.2.2 Slave Mode ......................................................................................................... 27-20

27.7.2.3 FIFO Disable Operation ..................................................................................... 27-21

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27.7.2.4 Tx FIFO Buffering Mechanism .......................................................................... 27-21

27.7.2.5 Rx FIFO Buffering Mechanism .......................................................................... 27-22

27.7.3 DSPI Baud Rate and Clock Delay Generation ....................................................... 27-22

27.7.3.1 Baud Rate Generator ........................................................................................... 27-23

27.7.3.2 CS to SCK Delay (tCSC) .................................................................................... 27-23

27.7.3.3 After DSPISCK Delay (tASC) ........................................................................... 27-23

27.7.3.4 Delay after Transfer (tDT) ................................................................................... 27-23

27.7.3.5 Peripheral Chip Select Strobe Enable (PCSS) .................................................... 27-24

27.7.4 Transfer Formats ..................................................................................................... 27-25

27.7.4.1 Classic SPI Transfer Format (CPHA = 0) .......................................................... 27-25

27.7.4.2 Classic SPI Transfer Format (CPHA = 1) .......................................................... 27-26

27.7.4.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0) .................................... 27-27

27.7.4.4 Modified SPI Transfer Format (MTFE = 1, CPHA = 1) .................................... 27-28

27.7.4.5 Continuous Selection Format ............................................................................. 27-29

27.7.5 Continuous Serial Communications Clock ............................................................. 27-30

27.7.6 Interrupts/DMA Requests ....................................................................................... 27-31

27.7.6.1 End of Queue Interrupt Request ......................................................................... 27-32

27.7.6.2 Transmit FIFO Fill Interrupt or DMA Request .................................................. 27-32

27.7.6.3 Transfer Complete Interrupt Request ................................................................. 27-32

27.7.6.4 Transmit FIFO Underflow Interrupt Request ..................................................... 27-32

27.7.6.5 Receive FIFO Drain Interrupt or DMA Request ................................................ 27-32

27.7.6.6 Receive FIFO Overflow Interrupt Request ......................................................... 27-32

27.8 Initialization and Application Information ................................................................. 27-33

27.8.1 How to Change Queues .......................................................................................... 27-33

27.8.2 Baud Rate Settings .................................................................................................. 27-33

27.8.3 Delay Settings ......................................................................................................... 27-34

27.8.4 Calculation of FIFO Pointer Addresses .................................................................. 27-35

27.8.4.1 Address Calculation for the First-in Entry and Last-in Entry in the Tx FIFO ... 27-36

27.8.4.2 Address Calculation for the First-in Entry and Last-in Entry in the Rx FIFO ... 27-36

Chapter 28

2

I

C Interface

28.1 Introduction ................................................................................................................... 28-1

28.1.1 Block Diagram .......................................................................................................... 28-1

28.1.2 I2C Overview ............................................................................................................ 28-2

28.1.3 Features ..................................................................................................................... 28-2

28.2 External Signals ............................................................................................................ 28-2

28.3 Memory Map/Register Definition ................................................................................ 28-3

28.3.1 I2C Register Map ...................................................................................................... 28-3

28.3.2 Register Descriptions ................................................................................................ 28-3

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28.3.2.1 I2C Address Register (I2ADR) ............................................................................. 28-3

28.3.2.2 I2C Frequency Divider Register (I2FDR) ............................................................ 28-4

2

28.3.2.3 I

28.3.2.4 I

C Control Register (I2CR) ................................................................................. 28-5

2

C Status Register (I2SR) .................................................................................... 28-5

28.3.2.5 I2C Data I/O Register (I2DR) ............................................................................... 28-7

2

28.3.2.6 I

C Interrupt Control Register (I2ICR) ................................................................ 28-7

28.4 Functional Description .................................................................................................. 28-8

28.4.1 START Signal ........................................................................................................... 28-9

28.4.2 Slave Address Transmission ..................................................................................... 28-9

28.4.3 STOP Signal ............................................................................................................. 28-9

28.4.4 Data Transfer ............................................................................................................ 28-9

28.4.5 Acknowledge .......................................................................................................... 28-10

28.4.6 Repeated Start ......................................................................................................... 28-11

28.4.7 Clock Synchronization and Arbitration .................................................................. 28-11

28.4.8 Handshaking and Clock Stretching ......................................................................... 28-12

28.5 Initialization Sequence ................................................................................................ 28-12

28.5.1 Transfer Initiation and Interrupt ............................................................................. 28-13

28.5.2 Post-Transfer Software Response ........................................................................... 28-14

28.5.3 Generation of STOP ................................................................................................ 28-15

28.5.4 Generation of Repeated START ............................................................................. 28-16

28.5.5 Slave Mode ............................................................................................................. 28-16

28.5.6 Arbitration Lost ....................................................................................................... 28-18

28.5.7 Flow Control ........................................................................................................... 28-18

Chapter 29

USB 2.0 Device Controller

29.1 Introduction ................................................................................................................... 29-1

29.1.1 Overview ................................................................................................................... 29-1

29.1.2 Features ..................................................................................................................... 29-1

29.1.3 Block Diagram .......................................................................................................... 29-2

29.1.3.1 Controller and Synchronization ............................................................................ 29-2

29.1.3.2 Descriptor RAM ................................................................................................... 29-2

29.1.3.3 FIFO Controller .................................................................................................... 29-3

29.1.3.4 FIFO RAM Manager ............................................................................................ 29-3

29.1.3.5 Integrated USB 2.0 Transceiver ........................................................................... 29-3

29.2 Memory Map/Register Definition ................................................................................ 29-4

29.2.1 USB Memory Map .................................................................................................... 29-4

29.2.2 USB Request, Control, and Status Registers ............................................................ 29-9

29.2.2.1 USB Status Register (USBSR) ............................................................................. 29-9

29.2.2.2 USB Control Register (USBCR) ........................................................................ 29-10

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29.2.2.3 USB Descriptor RAM Control Register (DRAMCR) ........................................ 29-12

29.2.2.4 USB Descriptor RAM Data Register (DRAMDR) ............................................ 29-13

29.2.2.5 USB Interrupt Status Register (USBISR) ........................................................... 29-14

29.2.2.6 USB Interrupt Mask Register (USBIMR) .......................................................... 29-15

29.2.2.7 USB Application Interrupt Status Register (USBAISR) .................................... 29-16

29.2.2.8 USB Application Interrupt Mask Register (USBAIMR) .................................... 29-17

29.2.2.9 Endpoint Info Register (EPINFO) ...................................................................... 29-18

29.2.2.10 USB Configuration Value Register (CFGR) ...................................................... 29-19

29.2.2.11 USB Configuration Attribute Register (CFGAR) .............................................. 29-19

29.2.2.12 USB Device Speed Register (SPEEDR) ............................................................. 29-20

29.2.2.13 USB Frame Number Register (FRMNUMR) ..................................................... 29-21

29.2.2.14 USB Endpoint Transaction Number Register (EPTNR) .................................... 29-21

29.2.2.15 USB Application Interface Update Register (IFUR) .......................................... 29-22

29.2.2.16 USB Configuration Interface Register (IFRn) .................................................... 29-22

29.2.3 USB Counter Registers ........................................................................................... 29-23

29.2.3.1 USB Packet Passed Count Register (PPCNT) .................................................... 29-23

29.2.3.2 USB Dropped Packet Counter Register (DPCNT) ............................................. 29-24

29.2.3.3 USB CRC Error Counter Register (CRCECNT) ................................................ 29-24

29.2.3.4 USB Bitstuffing Error Counter Register (BSECNT) .......................................... 29-24

29.2.3.5 USB PID Error Counter Register (PIDECNT) ................................................... 29-25

29.2.3.6 USB Framing Error Counter Register (FRMECNT) .......................................... 29-25

29.2.3.7 USB Transmitted Packet Counter Register (TXPCNT) ..................................... 29-26

29.2.3.8 USB Counter Overflow Register (CNTOVR) .................................................... 29-26

29.2.4 Endpoint Context Registers .................................................................................... 29-27

29.2.4.1 Endpoint n Attribute Control Register (EP0ACR, EPnOUTACR, EPnINACR) 29-27

29.2.4.2 Endpoint n Max Packet Size Register (EP0MPSR, EPnOUTMPSR, EPnINMPSR)

......................................................................................................................... 29-28

29.2.4.3 Endpoint n Interface Number Register (EP0IFR, EPnOUTIFR, EPnINIFR) .... 29-29

29.2.4.4 Endpoint

29.2.4.5 bmRequest Type Register (BMRTR) ................................................................. 29-31

29.2.4.6 bRequest Type Register (BRTR) ........................................................................ 29-32

29.2.4.7 wValue Register (WVALUER) .......................................................................... 29-32

29.2.4.8 wIndex Register (WINDEXR) ........................................................................... 29-33

29.2.4.9 wLength Register (WLENGTHR) ...................................................................... 29-33

29.2.4.10 Endpoint n Sync Frame Register (EPnOUTSFR, EPnINSFR) .......................... 29-33

29.2.5 USB Endpoint FIFO Registers ............................................................................... 29-34

29.2.5.1 USB Endpoint

29.2.5.2 USB Endpoint

29.2.5.3 USB Endpoint n Interrupt Mask Register (EPnIMR) ......................................... 29-37

29.2.5.4 USB Endpoint

29.2.5.5 USB Endpoint n FIFO Data Register (EPnFDR) ............................................... 29-39

n Status Register (EP0SR, EPnOUTSR, EPnINSR) ........................... 29-30

n Status and Control Register (EPnSTAT) ................................ 29-34

n Interrupt Status Register (EPnISR) ......................................... 29-35

n FIFO RAM Configuration Register (EPnFRCFGR) .............. 29-38

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29.2.5.6 USB Endpoint n FIFO Status Register (EPnFSR) ............................................. 29-40

29.2.5.7 USB Endpoint n FIFO Control Register (EPnFCR) ........................................... 29-42

29.2.5.8 USB Endpoint

29.2.5.9 USB Endpoint

29.2.5.10 USB Endpoint n FIFO Write Pointer (EPnFWP) ............................................... 29-45

29.2.5.11 USB Endpoint

29.2.5.12 USB Endpoint

29.3 Functional Description ................................................................................................ 29-47

29.3.1 Interrupts ................................................................................................................. 29-47

29.4 Software Interface ....................................................................................................... 29-47

29.4.1 Device Initialization ................................................................................................ 29-47

29.4.1.1 USB Descriptor Download ................................................................................. 29-48

29.4.1.2 USB Interrupt Register ....................................................................................... 29-49

29.4.1.3 Endpoint Registers .............................................................................................. 29-49

29.4.1.4 FIFO Sizes ......................................................................................................... 29-50

29.4.1.5 Enable the Device ............................................................................................... 29-50

29.4.2 Exception Handling ................................................................................................ 29-50

29.4.2.1 Unable to Fill or Empty FIFO Due to Temporary Problem ............................... 29-50

29.4.2.2 Catastrophic Error ............................................................................................... 29-50

29.4.3 Data Transfer Operations ........................................................................................ 29-50

29.4.3.1 USB Packets ....................................................................................................... 29-51

29.4.3.2 Sending Packets .................................................................................................. 29-51

29.4.3.3 Receiving Packets ............................................................................................... 29-51

29.4.3.4 USB Transfers .................................................................................................... 29-52

29.4.3.5 Control Transfers ................................................................................................ 29-53

29.4.3.6 Bulk Traffic ........................................................................................................ 29-54

29.4.3.7 Interrupt Traffic .................................................................................................. 29-54

29.4.3.8 Isochronous Operations ...................................................................................... 29-55

n FIFO Alarm Register (EPnFAR) ............................................ 29-44

n FIFO Read Pointer (EPnFRP) ................................................. 29-45

n Last Read Frame Pointer (EPnLRFP) ..................................... 29-46

n Last Write Frame Pointer (EPnLWFP) ................................... 29-47

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Chapter 30

Fast Ethernet Controller (FEC)

30.1 Introduction ................................................................................................................... 30-1

30.1.1 MCF548

30.1.2 Block Diagram .......................................................................................................... 30-1

30.1.3 Overview ................................................................................................................... 30-2

30.1.4 Features ..................................................................................................................... 30-3

30.1.5 Modes of Operation .................................................................................................. 30-3

30.1.5.1 Full and Half Duplex Operation ........................................................................... 30-3

30.1.5.2 Interface Options .................................................................................................. 30-3

30.1.5.3 Address Recognition Options ............................................................................... 30-4

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x Family Products ....................................................................................... 30-1

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30.1.5.4 Internal Loopback ................................................................................................. 30-4

30.2 External Signals ............................................................................................................ 30-4

30.2.1 Transmit Clock (EnTXCLK) .................................................................................... 30-4

30.2.2 Receive Clock (EnRXCLK) ..................................................................................... 30-4

30.2.3 Transmit Enable (EnTXEN) ..................................................................................... 30-4

30.2.4 Transmit Data[3:0] (EnTXD[3:0]) ............................................................................ 30-4

30.2.5 Transmit Error (EnTXER) ........................................................................................ 30-5

30.2.6 Receive Data Valid (EnRXDV) ................................................................................ 30-5

30.2.7 Receive Data[3:0] (EnRXD[3:0]) ............................................................................. 30-5

30.2.8 Receive Error (EnRXER) ......................................................................................... 30-5

30.2.9 Carrier Sense (EnCRS) ............................................................................................. 30-5

30.2.10 Collision (EnCOL) .................................................................................................... 30-5

30.2.11 Management Data Clock (EnMDC) ......................................................................... 30-5

30.2.12 Management Data (EnMDIO) .................................................................................. 30-5

30.3 Memory Map/Register Definition ................................................................................ 30-6

30.3.1 Top Level Module Memory Map ............................................................................. 30-6

30.3.2 Detailed Memory Map (Control/Status Registers) ................................................... 30-7

30.3.3 MIB Block Counters Memory Map .......................................................................... 30-8

30.3.3.1 Ethernet Interrupt Event Register (EIR) ............................................................. 30-10

30.3.3.2 Interrupt Mask Register (EIMR) ........................................................................ 30-12

30.3.3.3 Ethernet Control Register (ECR) ........................................................................ 30-13

30.3.3.4 MII Management Frame Register (MMFR) ....................................................... 30-14

30.3.3.5 MII Speed Control Register (MSCR) ................................................................. 30-15

30.3.3.6 MIB Control Register (MIBC) ........................................................................... 30-17

30.3.3.7 Receive Control Register (RCR) ........................................................................ 30-17

30.3.3.8 Receive Hash Register (RHR) ............................................................................ 30-18

30.3.3.9 Transmit Control Register (TCR) ....................................................................... 30-19

30.3.3.10 Physical Address Low Register (PALR) ............................................................ 30-20

30.3.3.11 Physical Address High Register (PAHR) ........................................................... 30-21

30.3.3.12 Opcode/Pause Duration Register (OPD) ............................................................ 30-22

30.3.3.13 Individual Address Upper Register (IAUR) ....................................................... 30-22

30.3.3.14 Individual Address Lower Register (IALR) ....................................................... 30-23

30.3.3.15 Group Address Upper Register (GAUR) ............................................................ 30-24

30.3.3.16 Group Address Lower Register (GALR) ............................................................ 30-24

30.3.3.17 FEC Transmit FIFO Watermark Register (FECTFWR) .................................... 30-25

30.3.3.18 FEC Receive FIFO Data Register (FECRFDR) ................................................. 30-26

30.3.3.19 FEC Receive FIFO Status Register (FECRFSR) ................................................ 30-26

30.3.3.20 FEC Receive FIFO Control Register (FECRFCR) ............................................. 30-28

30.3.3.21 FEC Receive FIFO Last Read Frame Pointer Register (FECRLRFP) ............... 30-30

30.3.3.22 FEC Receive FIFO Last Write Frame Pointer Register (FECRLWFP) ............. 30-30

30.3.3.23 FEC Receive FIFO Alarm Register (FECRFAR) .............................................. 30-31

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30.3.3.24 FEC Receive FIFO Read Pointer Register (FECRFRP) ..................................... 30-32

30.3.3.25 FEC Receive FIFO Write Pointer Register (FECRFWP) ................................... 30-33

30.3.3.26 FEC Transmit FIFO Data Register (FECTFDR) ................................................ 30-33

30.3.3.27 FEC Transmit FIFO Status Register (FECTFSR) .............................................. 30-34

30.3.3.28 FEC Transmit FIFO Control Register (FECTFCR) ........................................... 30-36

30.3.3.29 FEC Transmit FIFO Last Read Frame Pointer Register (FECTLRFP) .............. 30-37

30.3.3.30 FEC Transmit FIFO Last Write Frame Pointer Register (FECTLWFP) ............ 30-38

30.3.3.31 FEC Transmit FIFO Alarm Register (FECTFAR) ............................................. 30-39

30.3.3.32 FEC Transmit FIFO Read Pointer Register (FECTFRP) ................................... 30-40

30.3.3.33 FEC Transmit FIFO Write Pointer Register (FECTFWP) ................................. 30-40

30.3.3.34 FEC FIFO Reset Register (FECFRST) ............................................................... 30-41

30.3.3.35 FEC CRC and Transmit Frame Control Word Register (FECCTCWR) ............ 30-42

30.4 Functional Description ................................................................................................ 30-43

30.4.1 Initialization Sequence ............................................................................................ 30-43

30.4.1.1 Hardware Controlled Initialization ..................................................................... 30-43

30.4.1.2 User Initialization (Prior to Asserting ECR[ETHER_EN]) ................................ 30-43

30.4.2 Frame Control/Status Words .................................................................................. 30-44

30.4.2.1 Receive Frame Status Word (RFSW) ................................................................. 30-44

30.4.2.2 Transmit Frame Control Word (TFCW) ............................................................. 30-45

30.4.3 Network Interface Options ...................................................................................... 30-46

30.4.4 FEC Frame Transmission ....................................................................................... 30-46

30.4.5 FEC Frame Reception ............................................................................................. 30-47

30.4.6 Ethernet Address Recognition ................................................................................ 30-48

30.4.7 Hash Algorithm ....................................................................................................... 30-49

30.4.8 Full Duplex Flow Control ....................................................................................... 30-52

30.4.9 Inter-Packet Gap (IPG) Time .................................................................................. 30-53

30.4.10 Collision Handling .................................................................................................. 30-53

30.4.11 Internal and External Loopback .............................................................................. 30-53

30.4.12 Ethernet Error-Handling Procedure ........................................................................ 30-54

30.4.12.1 Transmission Errors ............................................................................................ 30-54

30.4.12.2 Reception Errors ................................................................................................. 30-55

30.4.13 MII Data Frame ...................................................................................................... 30-55

30.4.14 MII Management Frame Structure ......................................................................... 30-56

Chapter 31

Mechanical Data

31.1 Package ......................................................................................................................... 31-1

31.2 Pinout ............................................................................................................................ 31-1

31.3 Mechanical Diagrams ................................................................................................... 31-8

31.3.1 MCF5485/5484 Mechanical Diagram ...................................................................... 31-8

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor xxxix

Contents

Paragraph
Number

Title

Page

Number

31.3.2 MCF5483/5482 Mechanical Diagram .................................................................... 31-12

31.4 MCF5481/5480 Mechanical Diagram ........................................................................ 31-16

31.5 Mechanicals 388-pin PBGA Package Outline ............................................................ 31-20

31.6 Case Drawing .............................................................................................................. 31-20

Appendix A

MCF548x Memory Map

MCF548x Reference Manual, Rev. 3

xl Freescale Semiconductor

About This Book

The primary objective of this reference manual is to define the functionality of the MCF548x processors
for use by software and hardware developers.

The information in this book is subject to change without notice, as described in the disclaimers on the title
page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are
using the most recent version of the documentation.

To locate any published errata or updates for this document, refer to the world-wide web at

http://www.freescale.com/coldfire.

Audience

This manual is intended for system software and hardware developers and applications programmers who
want to develop products for the MCF548x. It is assumed that the reader understands operating systems,
microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire
architecture.

Organization

Following is a summary and a brief description of the major sections of this manual:

• Chapter 1, “Overview,” includes general descriptions of the modules and features incorporated in
the MCF548x, focussing in particular on new features.

• Chapter 2, “Signal Descriptions,” provides an alphabetical listing of MCF548x signals, including
which are inputs or outputs, how they are multiplexed, and the state of each signal at reset.

• Part I, “Processor Core,” is intended for system designers who need to understand the operation of
the MCF548x ColdFire core and its enhanced multiply/accumulate (EMAC) execution unit. It
describes the programming and exception models, Harvard memory implementation, and debug
module. Part 1 contains the following chapters:

— Chapter 3, “ColdFire Core,” provides an overview of the microprocessor core of the

MCF548x. The chapter begins with a description of enhancements from the V3 ColdFire core,
and then fully describes the V4e programming model as it is implemented on the MCF548x. It
also includes a full description of exception handling, data formats, an instruction set summary,
and a table of instruction timings.

— Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC),” describes the MCF548x

enhanced multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and
miscellaneous register instructions. The EMAC is integrated into the operand execution
pipeline (OEP).

— Chapter 5, “Memory Management Unit (MMU),” describes describes the ColdFire virtual

memory management unit (MMU), which provides virtual-to-physical address translation and
memory access control.

— Chapter 6, “Floating-Point Unit (FPU),” describes instructions implemented in the

floating-point unit (FPU) designed for use with the ColdFire family of microprocessors.

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor xli

— Chapter 7, “Local Memory,” describes the MCF548x implementation of the ColdFire V4e

local memory specification.

— Chapter 8, “Debug Support,” describes the Revision C enhanced hardware debug support in the

MCF548x. This revision of the ColdFire debug architecture encompasses earlier revisions.

• Part II, “System Integration Unit,” describes the system integration unit, which provides overall
control of the bus and serves as the interface between the ColdFire core processor complex and
internal peripheral devices. It includes a general description of the SIU and individual chapters that
describe components of the SIU, such as the interrupt controller, general purpose timers, slice
timers, and GPIOs. Part II contains the following chapters:

— Chapter 9, “System Integration Unit (SIU),” describes the SIU programming model, bus

arbitration, and system-protection functions for the MCF548x.

— Chapter 10, “Internal Clocks and Bus Architecture,” describes the clocking and internal buses

of the MCF548x and discusses the main functional blocks controlling the XL bus and the XL
bus arbiter.

— Chapter 11, “General Purpose Timers (GPT),” describes the functionality of the four general

purpose timers, GPT0–GPT3.

— Chapter 12, “Slice Timers (SLT),” describes the two slice timers, shorter term periodic

interrupts, used in the MCF548x.

— Chapter 13, “Interrupt Controller,” describes operation of the interrupt controller portion of the

SIU. Includes descriptions of the registers in the interrupt controller memory map and the

interrupt priority scheme.
— Chapter 14, “Edge Port Module (EPORT),” describes EPORT module functionality.
— Chapter 15, “GPIO,” describes the operation and programming model of the parallel port pin

assignment, direction-control, and data registers.

• Part III, “On-Chip Integration,” describes the on-chip integration for the MCF548x device. It
includes descriptions of the system SRAM, FlexBus interface, SDRAM controller, PCI, and SEC
cryptography accelerator. Part III contains the following chapters:

— Chapter 16, “32-Kbyte System SRAM,” describes the MCF548x on-chip system SRAM

implementation. It covers general operations, configuration, and initialization.

— Chapter 17, “FlexBus,” describes data transfer operations, error conditions, and reset

operations. It describes transfers initiated by the MCF548x and by an external master, and
includes detailed timing diagrams showing the interaction of signals in supported bus
operations.

— Chapter 18, “SDRAM Controller (SDRAMC),” describes configuration and operation of the

synchronous DRAM controller component of the SIU. It includes a description of signals
involved in DRAM operations, including chip select signals and their address, mask, and
control registers.

— Chapter 19, “PCI Bus Controller,” details the operation of the PCI bus controller for the

MCF548x.

— Chapter 20, “PCI Bus Arbiter Module,” describes the MCF548x PCI bus arbiter module,

including timing for request and grant handshaking, the arbitration process, and the register in
the PCI bus arbiter programing model.

MCF548x Reference Manual, Rev. 3

xlii Freescale Semiconductor

Suggested Reading

— Chapter 21, “FlexCAN,” describes the MCF548 implementation of the controller area network

(CAN) protocol. This chapter describes FlexCAN module operation and provides a
programming model.

— Chapter 22, “Integrated Security Engine (SEC),” provides an overview of the MCF548x

security encryption controller.

— Chapter 23, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of

the MCF548x JTAG test implementation. It describes the use of JTAG instructions and
provides information on how to disable JTAG functionality.

• Part IV, “Communications Subsystem,” contains chapters that discuss the operation and
configuration of the communications I/O subsystem including the MCF548x multichannel DMA,
communications timer, PSC, FEC, DSPI, and USB2, and I2C.

— Chapter 24, “Multichannel DMA,” provides an overview of the multichannel DMA controller

module including the operation of the external DMA request signals.

— Chapter 25, “Comm Timer Module (CTM),” contains a detailed description of the

communications timer module, which functions as a baud clock generator or as a DMA task
initiator.

— Chapter 26, “Programmable Serial Controller (PSC),” provides an overview of asynchronous,

synchronous, and IrDA 1.1 compliant receiver/transmitter serial communications of the
MCF548x.

— Chapter 27, “DMA Serial Peripheral Interface (DSPI),” describes the use of the DMA serial

peripheral interface (DSPI) implemented on the MCF548x processor, including details of the
DSPI data transfers. The chapter concludes with timing diagrams and the DSPI features that
support Tx and Rx FIFO queue management.

— Chapter 28, “I2C Interface,” describes the MCF548x I2C module, including I2C protocol,

clock synchronization, and the registers in the I2C programing model. It also provides
programming examples.

— Chapter 29, “USB 2.0 Device Controller,” provides an overview of the USB 2.0 device

controller module used in the MCF548x.

— Chapter 30, “Fast Ethernet Controller (FEC),” provides a feature-set overview, a functional

block diagram, and transceiver connection information for both MII (Media Independent
Interface) and 7-wire serial interfaces. It also provides describes operation and the
programming model.

• Part V, “Mechanical,” provides a pinout and both electrical and functional descriptions of the
MCF548x signals. It also describes how these signals interact to support the variety of bus
operations shown in timing diagrams.

— Chapter 31, “Mechanical Data,” provides a functional pin listing and package diagram for the

MCF548x.

Suggested Reading

This section lists additional reading that provides background for the information in this manual as well as
general information about the ColdFire architecture.

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor xliii

General Information

The following documentation provides useful information about the ColdFire architecture and computer
architecture in general:

• ColdFire Programmers Reference Manual (CFPRM)

• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross
Bannatyne, Joseph D. Greenfield

• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David
A. Patterson.

• Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A.
Patterson and John L. Hennessy.

ColdFire Documentation

The ColdFire documentation is available from the sources listed on the back cover of this manual.
Document order numbers are included in parentheses for ease in ordering.

• ColdFire Programmers Reference Manual, R1.0 (CFPRM)

• Reference manuals—These books provide details about individual ColdFire implementations and
are intended to be used in conjunction with The ColdFire Programmers Reference Manual. These
include the following:

— ColdFire CF4e Core User's Manual (V4ECFUM)
— MCF5475 Reference Manual (MCF5475RM)
— MCF5485 Reference Manual (MCF5485RM)

Additional literature on ColdFire implementations is being released as new processors become available.
For a current list of ColdFire documentation, refer to the World Wide Web at

http://www.freescale.com/coldfire.

Conventions

This document uses the following notational conventions:
MNEMONICS In text, instruction mnemonics are shown in uppercase.
mnemonics In code and tables, instruction mnemonics are shown in lowercase.
italics Italics indicate variable command parameters.

Book titles in text are set in italics.
0x0 Prefix to denote hexadecimal number
0b0 Prefix to denote binary number
REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges

appear in brackets. For example, RAMBAR[BA] identifies the base address field

in the RAM base address register.
nibble A 4-bit data unit
byte An 8-bit data unit
word A 16-bit data unit

MCF548x Reference Manual, Rev. 3

xliv Freescale Semiconductor

Acronyms and Abbreviations

longword A 32-bit data unit
x In some contexts, such as signal encodings, x indicates a don’t care.
n Used to express an undefined numerical value
¬ NOT logical operator
& AND logical operator
| OR logical operator

Register Conventions

This reference manual uses the register diagram format shown below.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R0000000000000000

W

Reset0000000000000000

1514131211109876543210

R00000000000 DFL

W

Reset0000000000000000

Reg

Addr

0x00C

Table i. Example Register Diagram

Acronyms and Abbreviations

Table ii lists acronyms and abbreviations used in this document.

Table ii. . Acronyms and Abbreviated Terms

Ter m Me a ning

ADC Analog-to-digital conversion

ALU Arithmetic logic unit

AVEC Autovector

BDM Background debug mode

BIST Built-in self test

BSDL Boundary-scan description language

CODEC Code/decode

comm bus Internal communications bus

DAC Digital-to-analog conversion

DMA Direct memory access

DSP Digital signal processing

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor xlv

Table ii. . Acronyms and Abbreviated Terms (continued)

Ter m Me a ning

EA Effective address

EDO Extended data output (DRAM)

FIFO First-in, first-out

GPIO General-purpose I/O

2

C Inter-integrated circuit

I

IEEE Institute for Electrical and Electronics Engineers

IFP Instruction fetch pipeline

IPL Interrupt priority level

JEDEC Joint Electron Device Engineering Council

JTAG Joint Test Action Group

LIFO Last-in, first-out

LRU Least recently used

LSB Least-significant byte

lsb Least-significant bit

MAC Multiple accumulate unit

MBAR Memory base address register

MSB Most-significant byte

msb Most-significant bit

Mux Multiplex

NOP No operation

OEP Operand execution pipeline

PC Program counter

PCLK Processor clock

PLL Phase-locked loop

PLRU Pseudo least recently used

POR Power-on reset

PQFP Plastic quad flat pack

RISC Reduced instruction set computing

Rx Receive

SIM System integration module

SOF Start of frame

TAP Test access port

TTL Transistor-to-transistor logic

Tx Transmit

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xlvi Freescale Semiconductor

Table ii. . Acronyms and Abbreviated Terms (continued)

Ter m Me a ning

UART Universal asynchronous/synchronous receiver transmitter

XLB bus Internal 64-bit bus

Terminology and Notational Conventions

Table iii shows notational conventions used throughout this document.

Table iii. Notational Conventions

Instruction Operand Syntax

Opcode Wildcard

cc Logical condition (example: NE for not equal)

Register Specifications

An Any address register n (example: A3 is address register 3)

Ay,Ax Source and destination address registers, respectively

Dn Any data register n (example: D5 is data register 5)

Dy,Dx Source and destination data registers, respectively

Terminology and Notational Conventions

Rc Any control register (example VBR is the vector base register)

Rm MAC registers (ACC, MAC, MASK)

Rn Any address or data register

Rw Destination register w (used for MAC instructions only)

Ry,Rx Any source and destination registers, respectively

Xi index register i (can be an address or data register: Ai, Di)

Register Names

ACC MAC accumulator register

CCR Condition code register (lower byte of SR)

MACSR MAC status register

MASK MAC mask register

PC Program counter

SR Status register

Port Name

PSTDDATA Processor status/debug data port

Miscellaneous Operands

#<data> Immediate data following the 16-bit operation word of the instruction

<ea> Effective address

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Freescale Semiconductor xlvii

Table iii. Notational Conventions (continued)

Instruction Operand Syntax

<ea>y,<ea>x Source and destination effective addresses, respectively

<label> Assembly language program label

<list> List of registers for MOVEM instruction (example: D3–D0)

<shift> Shift operation: shift left (<<), shift right (>>)

<size> Operand data size: byte (B), word (W), longword (L)

bc Both instruction and data caches

dc Data cache

ic Instruction cache

# <vector> Identifies the 4-bit vector number for trap instructions

<> identifies an indirect data address referencing memory

<xxx> identifies an absolute address referencing memory

dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)

SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)

Operations

+ Arithmetic addition or postincrement indicator

– Arithmetic subtraction or predecrement indicator

x Arithmetic multiplication

/ Arithmetic division

~ Invert; operand is logically complemented

& Logical AND

| Logical OR

^ Logical exclusive OR

<< Shift left (example: D0 << 3 is shift D0 left 3 bits)

>> Shift right (example: D0 >> 3 is shift D0 right 3 bits)

→ Source operand is moved to destination operand

←→ Two operands are exchanged

sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion

If <condition>

then

<operations>

else

Test the condition. If true, the operations after ‘then’ are performed. If the condition is false and the
optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false
and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description
as an example.

<operations>

Subfields and Qualifiers

{} Optional operation

() Identifies an indirect address

d

n

Displacement value, n-bits wide (example: d16 is a 16-bit displacement)

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xlviii Freescale Semiconductor

Table iii. Notational Conventions (continued)

Instruction Operand Syntax

Address Calculated effective address (pointer)

Bit Bit selection (example: Bit 3 of D0)

lsb Least significant bit (example: lsb of D0)

LSB Least significant byte

LSW Least significant word

msb Most significant bit

MSB Most significant byte

MSW Most significant word

Condition Code Register Bit Names

CCarry

N Negative

VOverflow

X Extend

ZZero

Terminology and Notational Conventions

Table iv. MCF548x Revision History

Section/Page Substantive Changes

Revision 1.0 (03/2004)

Initial release.

Revision 1.1 (03/2004

Figure 15-1/Page 15-2 Changed instances of FEC2 to FEC1 and FEC1 to FEC0.

30.3.1/30-6–

30.3.3.1/30-10

Chapter 17 Took out FlexCan chapter. Fixed timing diagrams in FlexBus chapter.

Throughout Added all documentation errata from Revision 3 of the MCF5485RMAD document as described below.

Changed instances of FEC2 to FEC1 and FEC1 to FEC0.

Revision 1.2 (03/2004)

Revision 2.0 (10/2004)

Many content changes, the biggest being greatly enhancing the MC-DMA chapter and adding Clocks and
Internal Buses chapter. Many editorial changes.

Revision 2.1 (10/2004)

Revision 3.0 (01/2006)

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor xlix

Table iv. MCF548x Revision History (continued)

Section/Page Substantive Changes

Table 2-1/2-3 Add column to indicate whether the signal has a pull-up resistor.

These signals have a pull-up resistor at all times:
DSCLK/TRST, BKPT/TMS, DSI/TDI

These signals have a pull-up resistor whenever configured for general-purpose input (default state after
reset):
PCIBR[4:3], PCIGNT[4:3], E1MDIO, E1MDC, E1TXCLK, E1TXEN, E1TXD[3:0], E1COL, E1RXCLK,
E1RXDV, E1RXD[3:0], E1CRS, E1TXER, E1RXER

Table 2-1/2-3 Remove overbars from the following signals: FBADDR1, FBADDR0, SDDATA, SDADDR, SDBA, TIN3,

TOUT3

Table 2-1/2-3 In entry AD6, remove overbar from ALE

enable”

Table 2-1/2-3 Add overbars to IRQ[6:5].

Table 2-2/2-10 • Replace PPSCLn entries under the GPIO column with PPSC1PSC0n. There is no PPSCL port.

• Replace PPSCHn entries under the GPIO column with PPSC3PSC2n. There is no PPSCH port.

Table 2-2/2-10 The GPIO bit number for each of the UART control signals are incorrect for Table 2-2. However, they are

correct for Table 2-1:

•Y23/PSC1RTS

•AB23/PSC3RTS

pin: Change GPIO entry from PPSCL7 to PPSC1PSC06.

pin: Change GPIO entry from PPSCH7 to PPSC3PSC26.

•AB26/PSC0RTS pin: Change GPIO entry from PPSCL3 to PPSC1PSC02.

• AC19/PSC2CTS pin: Change GPIO entry from PPSCH2 to PPSC3PSC23.

• AD26/PSC2RTS

pin: Change GPIO entry from PPSCH3 to PPSC3PSC22.

•AE23/PSC0CTS pin: Change GPIO entry from PPSCL2 to PPSC1PSC03.

• AF23/PSC3CTS pin: Change GPIO entry from PPSCH6 to PPSC3PSC27.

• AF25/PSC1CTS

pin: Change GPIO entry from PPSCL6 to PPSC1PSC07.

Table 2-2/2-10 Remove overbars from the following signals: IVDD, TCK, PLLVDD, PSTDDATA1, PSTDDATA7, SDDATA21,

PSTDDATA2, E1RXCLK, E1RXD2, SDVDD, SDDATA31, SDADDR4, DSCLK, VSS, EVDD, PCIAD29,
PCIAD30, SCL, SDDATA16, AD17, AD20, E1CRS, E0TXD2, TOUT2, TOUT1, PSC2TXD, ALE, E0TXD3,
SDBA1, SDBA0, USBVDD, PSC3RXD, AD25, USBRBIAS, TIN1, TIN2, TIN0

Table 2-2/2-10 Add overbars to the following signals: IRQ3, IRQ2

and change description from “Transfer start” to “Address latch

Table 2-4/2-22 Replace table with the following:

Table 1. MCF548x Divide Ratio Encodings

Clock

AD[12:8]

1
2

1

00011 1:2 41.6–50.0 83.33–100 166.66–200

00101 1:2 25.0–41.5 50.0–83.0

01111 1:4 25.0 100 200

All other values of AD[12:8] are reserved.
Note that DDR memories typically have a minimum speed of 83 MHz. Some vendors specifiy
down to 75 MHz. Check with the memory component specifications to verify.

CLKIN–PCI and FlexBus

Ratio

Frequency Range (MHz)

Internal XLB, SDRAM

bus, and PSTCLK

Frequency Range (MHz)

2

Core Frequency

Range (MHz)

100.0–166.66

MCF548x Reference Manual, Rev. 3

l Freescale Semiconductor

Terminology and Notational Conventions

Table iv. MCF548x Revision History (continued)

Section/Page Substantive Changes

2.2.6.1/2-22 Add the following after Table 2-4:

Figure 1 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.

CLKIN

Internal Clock

Core Clock

2x

2x

100.0

200.0

200.0

2x

25.0 50.0

4x

25.0

25 40 50 60 70 70 80 90 100 110 120 130 140 150 160 170 180 190 20060

CLKIN (MHz) Core Clock (MHz)

50.0

40 50 60 70 80 90 10030

Internal Clock (MHz)

Figure 1. CLKIN, Internal Bus, and Core Clock Ratios

100.0

100.0

3.8.1/3-38 Change the second sentence of the first paragraph from “The second holds the 32-bit program counter

address of the faulted instruction.“ to “The second holds the 32-bit program counter address of the faulted
or interrupted instruction.”

Table 3-23/3-40 The “Interrupt exception” entry’s description is outdated. Change from “Interrupt exception processing, with

interrupt recognition and vector fetching, includes uninitialized and spurious interrupts as well as those
where the requesting device supplies the 8-bit interrupt vector. Autovectoring can optionally be configured
through the system interface module (SIM).” to “Please refer to Chapter 13 ‘Interrupt Controller.’”

Table 10-2/10-5 Add missing table using Ta bl e 1 from this document.

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Freescale Semiconductor li

Table iv. MCF548x Revision History (continued)

Section/Page Substantive Changes

10.2/10-5 Insert the following section before section 10.2 “XL Bus Arbiter”.

10.2 PLL

10.2.1 PLL Memory Map/Register Descriptions

MBAR Offset Name Byte0 Byte1 Byte2 Byte3 Access

0x300 System PLL Control Register SPCR R/W

10.2.2 System PLL Control Register (SPCR)

The system PLL control register (SPCR) defines the clock enables used to control clocks to a set of peripherals. Unused peripherals
can have their clock stopped, reducing power consumption. In addition, the SPCR contains a read-only bit for the system PLL lock
status. At reset, the clock enables are set, enabling all system PLL gated output clocks.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RPLLK000000000000000

W

Reset1000000000000000

1514131211109876543210

R

W

Reset0111111111111111

Addr MBAR + 0x300

0

CORENCRY

ENB

CRY
ENA

Table 2. System PLL Memory Map

CAN1

EN

PSC

0

0

EN

USBENFEC1ENFEC0ENDMAENCAN0ENFBENPCIENMEM

EN

Figure 2. System PLL Control Register (SPCR)

Table 3. SPCR Field Descriptions

Bits Name Description

31 PLLK System PLL Lock Status - Read-only lock status of the system PLL.

30-15 — Reserved, should be cleared.

14 COREN Core & Communications Sub-System Clock Enable - Controls clocks for the CF4 Core, System SRAM, CommBus

13 CRYENB Crypto Clock Enable B - Controls the fast clock to the SEC

12 CRYENA Crypto Clock Enable A - Controls the slow clock to the SEC

11 CAN1EN CAN1 Clock Enable

10 — Reserved, should be cleared.

9 PSCEN PSC Clock Enable - Controls clock for all PSC modules.

8 — Reserved, should be cleared.

7 USBEN USB Clock Enable

6 FEC1EN FEC1 Clock Enable

5 FEC0EN FEC0 Clock Enable

4 DMAEN Multi-channel DMA Clock Enable

3 CAN0EN CAN0 Clock Enable

2 FBEN FlexBus Clock Enable

1 PCIEN PCI Bus Clock Enable

0 MEMEN Memory Clock Enable - Controls clocks of the SDRAM controller module

1 PLL has obtained frequency lock
0 PLL has not locked

Arbiter, I2C, Comm Timers, and External DMA modules

MCF548x Reference Manual, Rev. 3

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Terminology and Notational Conventions

Table iv. MCF548x Revision History (continued)

Section/Page Substantive Changes

Table 10-3/10-5 Bits BA, DT, and AT: The 0 and 1 are switched. Setting each bit enables operation, while clearing disables

operation. The 0 and 1 (or the corresponding descriptions) need to be swapped for all three bits.

11.4.2/11-8 Remove all text from bullet item #2 starting with “This scenario works for all pulses except....” This errata

does not apply to this processor.

13.1.1/13-1 Correct the cross-reference link at top of page that reads “Section 3.8.1, ‘Exception Stack Frame

Definition.’”

Table 15-27/15-24 In the bit 7-6, PAR1_E1MDC entry, change ‘11’ bit setting description from: “E1MDC pin configured for

FEC1 MDC function” to “E1MDC pin configured for FEC1 E1MDC function” to be consistent with rest of
section.

Table 15-34/15-30 Remove extraneous “/” from “DSPICS0//SS

Table 16-1/16-2 Extend SSCR entry to include bytes 2 & 3 as well as bytes 0 and 1, since it is a 32 bit register.

17.6.5.4.2/17-23 Change “transfer start” to “address latch enable” in second sentence.

21.4.9/21-28 Figure 21-14 and Table 21-18 are missing. Add them as shown below and correct the cross-references to

them.

NRZ Signal

” in second sentence of the PAR_CS0 bit description.

SYNC_SEG

1 4 ... 16 2 ... 8

Time Segment 1 Time Segment 2

(PROP_SEG + PSEG1 + 2) (PSEG2 + 1)

8 ... 25 Time Quanta

= 1 Bit Time

Transmit Point

Sample Point
(single or triple sampling)

Figure 21-14. Segments within the Bit Time

Table 21-18. Time Segment Syntax

Syntax Description

SYNC_SEG System expects transitions to occur on the bus during this period.

Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point.

Sample Point A node samples the bus at this point. If the three samples per bit option is selected,

then this point marks the position of the third sample.

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor liii

Table iv. MCF548x Revision History (continued)

Section/Page Substantive Changes

21.4.9/21-28 Add the following table below the note at the end of the section and correct the cross-reference pointing to

it:

Table 21-19. CAN Standard Compliant Bit Time Segment Settings

Time Segment 1 Time Segment 2

5 .. 10 2 1 .. 2

4 .. 11 3 1 .. 3

5 .. 12 4 1 .. 4

6 .. 13 5 1 .. 4

7 .. 14 6 1 .. 4

8 .. 15 7 1 .. 4

9 .. 16 8 1 .. 4

Re-synchronization

Table 23-5/23-7 The JTAG IR codes are incorrect. Replace table with the following:

F

Instruction IR[5:0] Instruction Summary

EXTEST 000000 Selects boundary scan register while applying fixed values to output

pins and asserting functional reset

SAMPLE 000001 Selects boundary scan register for shifting, sampling, and preloading

without disturbing functional operation

IDCODE 011101 Selects IDCODE register for shift

CLAMP 011111 Selects bypass while applying fixed values to output pins and

asserting functional reset

HIGHZ 111101

Selects bypass register while tri-stating all output pins and asserting
functional reset

Jump Width

ENABLE 000010 Selects TEST_CTRL register

BYPASS 111111 Selects bypass register for data operations

23.4.3/23-7 Remove the TEST_LEAKAGE section, as the instruction is not supported.

23.4.3/23-7 Remove the LOCKOUT_RECOVERY section, as the instruction is not supported.

Table 24-18/24-20 Correct Base Address Mask Register 1 mnemonic from EREQMASK0 to EREQMASK1.

24.3.4.2/24-20 Correct overbar in first sentence. From “After DREQ is asserted,

this register contains...” to “After DREQ

is asserted, this register contains...”

MCF548x Reference Manual, Rev. 3

liv Freescale Semiconductor

Table iv. MCF548x Revision History (continued)

Section/Page Substantive Changes

25.1.2/25-2 Add the following section after section 24.1.2:

24.1.3 Comm Timer External Clock[7:0]

The comm timer external clock is the alternate clock signal and is provided by the user. The user must write
a 1 to CTCR[S] in the variable channel and write a 1001 to CTCR[S] within the fixed channel to select this
signal. If this signal is selected, all timing will be with respect to this clock signal. This signal is restricted to
being half the frequency or less of the system bus clock.

Table 0-4. Comm Timers External Clock

Timer Channel External Signal

0TIN0

1TIN1

2TIN2

3TIN3

4PSC3BCLK

5PSC2BCLK

6PSC1BCLK

7PSC0BCLK

Terminology and Notational Conventions

Table 25-3/25-5 In the S bit description change the 1001 setting from “Reserved” to “External clock”

Table 25-4/25-6 The S bit field is incorrect. Bits 31-29 should be reserved, and only bit 28 should be the S bit. And the S bit

description should be:
Clock enable source select. Selects the clock rate for the fixed timer channels. The clock rate for the timer
is the internal system clock divided by an 8-bit prescaler.
1 External Clock
0 Sysclk
Note: The external bus clock cannot be an faster than half the frequency of the system clock.

26.1/26-1 Fix broken cross-reference to Figure 26-1.

Table 26-13/26-19 In description of TXRDY change PSCTFALARM to PSCTFAR

Table 26-30/26-29 In description of ALARM change instance of “less than alarm bytes” to “more than alarm bytes” and change

instance of “more than alarm bytes” to “less than alarm bytes”.

26.3.3.24/26-30 Change bit 30 to reserved, as the WFR field is only one-bit wide.

Figure 26-22/Page

Remove shading from W field as the PSCRFARn and PSCTFARn

registers are R/W accessible.

26-32

26.4/26-35 Add section 15.3.7 “PSC FIFO System” from the MPC5200 User’s Manual to before section 26.4.9

“Looping Modes.” Change the following text to apply to the MCF548x:

MPC5200 → MCF5478x
BestComm → Multichannel DMA
MR1 → PSCMR1n
SR→ PSCSRn
ORERR → ERR

Figure 28-1/Page 28-1 Change IFDR to I2FDR and IADR to I2ADR in figure.

28.3.2.1/28-3 Change instances of I2AR to I2ADR.

28.3.2.3/28-5 Change I2ICR to I2CR throughout section.

Chapter 28, “I2C

After section 27.3.2.4, change instances of R/W to R/W

throughout chapter.

Interface”

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor lv

Table iv. MCF548x Revision History (continued)

Section/Page Substantive Changes

27.6.1/27-5 Remove instances of MDIS bit as it is not present on this version of the DSPI.

Table 29-3/29-11 USBCR[APPLOCK] bit description, the bit setting numbers are incorrrect. When cleared (0), APPLOCK is

deasserted. When set (1), APPLOCK is asserted.

Table 29-29/29-30 Endpoint status register’s PSTALL entry: the last sentence should be “Setting this bit also sets

USBAISR[EPSTALL].” instead of “Setting this bit also sets USBAISR[EPHALT].”

Table 29-37/29-36 EPnISR[EOT] bit description, add a note to the last sentence of the first paragraph stating “The EOT

interrupt will not assert for an isochronous OUT packet that experiences a PID sequencing error.”

29.4.3.1/29-51 Add a section below USB Packets entitled “Handshakes” with the following paragraphs:

“The USB device will return a NYET handshake packet to an OUT transaction if there is already data
present in the FIFO and there are less than 2*MAXPACKETSIZE bytes free in the FIFO.

In cases where the FIFO depth is larger than 2*MAXPACKETSIZE (i.e. 3x or 4x), the following behavior
will occur. If after a transfer that returned a NYET handshake there is at least 1*MAXPACKETSIZE of free
space in the FIFO, the device will ACK the first PING request from the host and accept another
MAXPACKETSIZE transfer from the host. The device will again send a NYET handshake.

The only time the device will NAK a PING is when there is less than 1*MAXPACKETSIZE of free space in
the FIFO.”

Table 30-41/30-42 Change bit description of the FECFRST[SW_RST] bit to “Software Reset - This bit controls the soft reset

of the FEC FIFOs. A soft reset will reset the FIFO pointers and byte counters but not the status and control
registers. To cause a soft reset this bit should be set and then cleared by application software.”

Change bit description of the FECFRST[RST_CTL] bit to “Reset control - Setting this bit allows the FEC
controller to perform a soft reset of the FIFOs when the FEC is disabled (ECR[ETHER_EN] cleared).”

Table 31-1/31-1 Add column to indicate whether the signal has a pull-up resistor.

These signals have a pull-up resistor at all times:
DSCLK/TRST, BKPT/TMS, DSI/TDI

These signals have a pull-up resistor whenever configured for general-purpose input (default state after
reset):
PCIBR[4:3], PCIGNT[4:3], E1MDIO, E1MDC, E1TXCLK, E1TXEN, E1TXD[3:0], E1COL, E1RXCLK,
E1RXDV, E1RXD[3:0], E1CRS, E1TXER, E1RXER

Table 31-1/31-1 Ball P3 should be SD_VDD instead of EVDD.

Table 31-1/31-1 The GPIO bit number for each of the UART control signals are incorrect for Table 31-1. However, they are

correct for Table 2-1:

•Y23/PSC1RTS

•AB23/PSC3RTS

•AB26/PSC0RTS pin: Change GPIO entry from PPSCL3 to PPSC1PSC02.

• AC19/PSC2CTS

• AD26/PSC2RTS

•AE23/PSC0CTS pin: Change GPIO entry from PPSCL2 to PPSC1PSC03.

• AF23/PSC3CTS

• AF25/PSC1CTS

Table 31-1/31-1 Remove overbar from ALE

Table 31-1/31-1 • Replace PPSCLn entries under the GPIO column with PPSC1PSC0n. There is no PPSCL port.

• Replace PPSCHn entries under the GPIO column with PPSC3PSC2n. There is no PPSCH port.

pin: Change GPIO entry from PPSCL7 to PPSC1PSC06.

pin: Change GPIO entry from PPSCH7 to PPSC3PSC26.

pin: Change GPIO entry from PPSCH2 to PPSC3PSC23.
pin: Change GPIO entry from PPSCH3 to PPSC3PSC22.

pin: Change GPIO entry from PPSCH6 to PPSC3PSC27.
pin: Change GPIO entry from PPSCL6 to PPSC1PSC07.

at location AD6.

MCF548x Reference Manual, Rev. 3

lvi Freescale Semiconductor

Table iv. MCF548x Revision History (continued)

Section/Page Substantive Changes

Terminology and Notational Conventions

Figure 31-3/Page 31-10 Remove overbar from ALE

Figure 31-7/Page 31-14 Remove overbar from ALE

Figure 31-11/Page

Remove overbar from ALE

31-18

at location AD6.

at location AD6.

at location AD6.

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor lvii

MCF548x Reference Manual, Rev. 3

lviii Freescale Semiconductor

Chapter 1 Overview

This chapter provides an overview of the MCF548x microprocessor features, including the major
functional components.

1.1 MCF548x Family Overview

The MCF548x family is based on the ColdFire V4e core, a complex which comprises the ColdFire V4
central processor unit (CPU), an enhanced multiply-accumulate unit (EMAC), a memory management unit
(MMU), a double-precision floating point unit (FPU) conforming to standard IEEE-754, and controllers
for caches and local data memories. The MCF548x family is capable of performing at an operating
frequency of up to 200 MHz or 308 MIPS (Dhrystone 2.1).

To maximize throughput, the MCF548x family incorporates three independent external bus interfaces:

1. The general-purpose local bus (FlexBus) is used for system boot memories and simple peripherals
and has up to six chip selects.

2. Program code and data can be stored in SDRAM connected to a dedicated 32-bit double data rate
(DDR) bus that can run at up to one-half of the CPU core frequency. The glueless DDR SDRAM
controller handles all address multiplexing, input and output strobe timing, and memory bus clock
generation.

3. A 32-bit PCI bus compliant with the version 2.2 specification and running at a typical frequency
of 33 MHz or 66 MHz supports peripherals that require high bandwidth, the ability to arbitrate for
bus mastership, and access to internal MCF548x memory resources.

The MCF548x family provides substantial communications functionality by integrating the following
connectivity peripherals:

• Up to two 10/100 Mbps fast Ethernet controllers (FECs)

• One optional USB 2.0 device (slave) module with seven endpoints and an integrated transceiver

• Up to four UART/USART/IRDA/modem programmable serial controllers (PSCs)

• One DMA serial peripheral interface (DSPI)

• One inter-integrated circuit (I

• Two controller area network 2.0B (FlexCAN) interfaces with 16 message buffers each

Additionally, the MCF548x provides hardware support for a range of Internet security standards with an
optional bus-mastering cryptography accelerator. This module incorporates units to speed DES/3DES and
AES block ciphers, the RC4 stream cipher, bulk data hashing (MD5/SHA-1/SHA-256/HMAC), and
random number generation. Hardware acceleration of these functions is critical to avoiding the throughput
bottlenecks associated with software-only implementations of SSH, SSL/TLS, IPsec, SRTP, WEP, and
other security standards. The incorporation of cryptography acceleration makes the MCF548x family a
compelling solution for a wide range of office automation, industrial control, and SOHO networking
devices that must have the ability to securely transmit critical equipment control information across
typically insecure Ethernet data networks.

Additional features of MCF548x products include a watchdog timer, two 32-bit slice timers for RTOS
scheduling and alarm functionality, up to four 32-bit general-purpose timers with capture, compare, and
pulse width modulation capability, a multisource vectored interrupt controller, a phase-locked loop (PLL)
to generate the system clock, 32 Kbytes of SRAM for high-speed local data storage, and multiple
general-purpose I/O ports.

2C™

) bus controller

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 1-1

With on-chip support for multiple common communications interfaces, MCF548x products require only
the addition of memories and certain physical layer transceivers to be cost-effective system solutions for
many applications. Such applications include industrial routers, high-end POS terminals, building
automation systems, and process control equipment.

MCF548x products require four supply voltages: 1.5V for the high-performance, low power, internal core
logic, 2.5V for the DDR SDRAM bus interface, 1.25V for the DDR SDRAM V

, and 3.3V for all other

REF

I/O functionality, including the PCI and FlexBus interfaces.

1.2 MCF548x Block Diagram

Figure 1-1 shows a top-level block diagram of the MCF548x products.

ColdFire V4e Core

FPU, MMU

EMAC

32K D-cache

32K I-cache

Interrupt

Controller

System

Watchdog

Integration Unit

Time r

Slice

Time rs x 2

GP

Time rs x 4

FlexCAN

x 2

Bus

Slave

PLL

DDR SDRAM

XL Bus

Arbiter

XL Bus

Master/Slave

Interface

Cryptography

Accelerator

32K System

SRAM

DMA

Read

3

R/W

Crypto

XL Bus

Read/Write

DMA

Write

Multichannel DMA

Master Bus Interface and FIFOs

Interface

Memory

Controller

FlexBus
Interface

FlexBus

Controller

PCI 2.2

Controller

PCI I/O Interface and Ports

PCI Interface

& FIFOs

CommBus

Perpheral I/O Interface & Ports

I/O Subsystem

DSPI

PSC x 4I2C FEC1

Perpheral Communications I/O Interface & Ports

1

Available in MCF5485, MCF5484, MCF5483, and MCF5482 devices.

2

Available in MCF5485, MCF5484, MCF5481, and MCF5480 devices.

3

Available in MCF5485, MCF5483, and MCF5481 devices.

FEC2

2

USB 2.0

DEVICE

USB 2.0

PHY

Communications

1

1

Figure 1-1. MCF548x Block Diagram

MCF548x Reference Manual, Rev. 3

1-2 Freescale Semiconductor

MCF548x Family Products

1.3 MCF548x Family Products

Table 1-1 summarizes the products available within the MCF548x product family. All products are

available in pin-compatible, 388-pin PBGA packaging allowing for ease of migration between products
within the family. A printed circuit board designed using the MCF5485/4 footprint is compatible with any
of the MCF548x family devices.

Table 1-1. MCF548x Family Products

Product Performance Features Temperature Range

MCF5485 308 MIPS

200 MHz

MCF5484 308 MIPS

200 MHz

MCF5483 255 MIPS

166 MHz

MCF5482 255 MIPS

166 MHz

MCF5481 255 MIPS

166 MHz

Two 10/100 Ethernet Controllers

Two CAN Controllers

USB 2.0 Device with Integrated PHY

v2.2 PCI Controller

DDR Memory Controller

Encryption Accelerator

Two 10/100 Ethernet Controllers

Two CAN Controllers

USB 2.0 Device with Integrated PHY

v2.2 PCI Controller

DDR Memory Controller

One 10/100 Ethernet Controller

Two CAN Controllers

USB 2.0 Device with Integrated PHY

v2.2 PCI Controller

DDR Memory Controller

Encryption Accelerator

One 10/100 Ethernet Controller

Two CAN Controllers

USB 2.0 Device with Integrated PHY

v2.2 PCI Controller

DDR Memory Controller

Two 10/100 Ethernet Controllers

Two CAN Controllers

v2.2 PCI Controller

DDR Memory Controller

Encryption Accelerator

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

° C

° C

° C

° C

° C

MCF5480 255 MIPS

166 MHz

Two 10/100 Ethernet Controllers

Two CAN Controllers

v2.2 PCI Controller

DDR Memory Controller

-40 to 85

° C

1.4 MCF548x Family Features

• ColdFire V4e core
— Limited superscalar V4 ColdFire processor core

— Up to 200 MHz peak internal core frequency (308 Dhrystone 2.1 MIPS)
— Harvard architecture

– 32-Kbyte instruction cache
– 32-Kbyte data cache

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 1-3

— Memory management unit (MMU)

– Separate, 32-entry, fully-associative instruction and data translation lookahead buffers

— Floating point unit (FPU)

– Double-precision support that conforms to IEEE-754 standard
– Eight floating point registers

• Internal master bus (XLB) arbiter
— High performance split address and data transactions
— Support for various parking modes

• 32-bit double data rate (DDR) synchronous DRAM (SDRAM) controller
— 66–133 MHz operation

— Supports both DDR and SDR DRAM
— Built-in initialization and refresh
— Up to four chip selects enabling up to 1 GB of external memory

• Version 2.2 peripheral component interconnect (PCI) bus
— 32-bit target and initiator operation

— Support for up to five external PCI masters
— 33–66 MHz operation with PCI bus to XLB divider ratios of 1:1, 1:2, and 1:4

• Flexible multi-function external bus (FlexBus)
— Supports operation with the following:

– Non-multiplexed 32-bit address and 32-bit data (32-bit address muxed over

PCI bus–PCI not usable)
– Multiplexed 32-bit address and 32-bit data (PCI usable)
– Multiplexed 32-bit address and 16-bit data
– Multiplexed 32-bit address and 8-bit data

— Provides a glueless interface to boot Flash/ROM, SRAM, and peripheral devices
— Up to six chip selects
— 33–66 MHz operation

• Communications I/O subsystem
— Intelligent 16-channel DMA controller
— Dedicated DMA channels for receive and transmit on all subsystem peripheral interfaces
— Up to two 10/100 Mbps fast Ethernet controllers (FECs), each with separate 2-Kbyte receive

and transmit FIFOs

— Universal serial bus (USB) version 2.0 device controller

– Support for one control and six programmable endpoints — interrupt, bulk, or isochronous
– 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM
– Integrated physical layer interface

— Up to four programmable serial controllers (PSCs) each with separate 512-byte receive and

transmit FIFOs for UART, USART, modem, codec, and IrDA 1.1 interfaces
—I2C peripheral interface
— Two FlexCAN controller area network 2.0B controllers each with 16 message buffers
— DMA serial peripheral interface (DSPI)

• Optional security encryption controller (SEC) module

MCF548x Reference Manual, Rev. 3

1-4 Freescale Semiconductor

MCF548x Family Features

— Execution units for the following:

– DES/3DES block cipher

– AES block cipher

– RC4 stream cipher

– MD5/SHA-1/SHA-256/HMAC hashing

– Random number generator compliant with FIPS 140-1 standards for randomness and

non-determinism

— Dual-channel architecture permits single-pass encryption and authentication

• 32-Kbyte system SRAM
— Arbitration mechanism shares bandwidth between internal bus masters (CPU, cryptography

accelerator, PCI, and DMA)

• System integration unit (SIU)
— Interrupt controller

— Watchdog timer
— Two 32-bit slice timers for periodic alarm and interrupt generation
— Up to four 32-bit general-purpose timers with capture, compare, and PWM capability
— General-purpose I/O ports multiplexed with peripheral pins

• Debug and test features
— Core debug support via ColdFire background debug mode (BDM) port

— Chip debug support via JTAG/ IEEE 1149.1 test access port

• PLL and clock generator
— 30–66.67 MHz input frequency range

• Operating Voltages
— 1.5V internal logic

— 2.5V DDR SDRAM bus I/O (1.25V V

REF

)

— 3.3V PCI, FlexBus, and all other I/O

• Estimated power consumption
— <1.5W

1.4.1 ColdFire V4e Core Overview

The ColdFire V4e core is a variable-length RISC, clock-multiplied core that includes a Harvard memory
architecture, branch cache acceleration logic, and limited superscalar dual-instruction issue capabilities.
The limited superscalar design approaches dual-issue performance with the cost of a scalar execution
pipeline.

The ColdFire V4e processor core is comprised of two separate pipelines that are decoupled by an
instruction buffer. The four-stage instruction fetch pipeline (IFP) prefetches the instruction stream,
examines it to predict changes of flow, partially decodes instructions, and packages fetched data into
instructions for the operand execution pipeline (OEP). The IFP can prefetch instructions before the OEP
needs them, minimizing the wait for instructions. The instruction buffer is a 10 instruction, first-in-first-out
(FIFO) buffer that decouples the IFP and OEP by holding prefetched instructions awaiting execution in
the OEP. The OEP includes five pipeline stages: the first stage decodes instructions and selects operands
(DS), and the second stage generates operand addresses (OAG). The third and fourth stages fetch operands
(OC1 and OC2), and the fifth stage executes instructions (EX).

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 1-5

The ColdFire V4e processor contains a double-precision floating point unit (FPU). The FPU conforms to
the American National Standards Institute (ANSI)/Institute of Electrical and Electronics Engineers (IEEE)
Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754). The FPU operates on 64-bit,
double-precision floating point data and supports single-precision and signed integer input operands. The
FPU programming model is like that in the MC68060 microprocessor. The FPU is intended to accelerate
the performance of certain classes of embedded applications, especially those requiring high-speed
floating point arithmetic computations.

The ColdFire V4e processor also incorporates the ColdFire memory management unit (MMU), which
provides virtual-to-physical address translation and memory access control. The MMU consists of
memory-mapped control, status, and fault registers that provide access to translation lookaside buffers
(TLBs). Software can control address translation and access attributes of a virtual address by configuring
MMU control registers and loading TLBs. With software support, the MMU provides demand-paged,
virtual addressing.

The ColdFire V4e core implements the ColdFire instruction set architecture revision B with support for
floating Point instructions. Additionally, the ColdFire V4e core includes the enhanced
multiply-accumulate unit (EMAC) for improved signal processing capabilities. The EMAC implements a
4-stage execution pipeline, optimized for 32 x 32-bit operations, with support for four 48-bit accumulators.
Supported operands include 16- and 32-bit signed and unsigned integers, as well as signed fractional
operands and a complete set of instructions to process these data types. The EMAC provides superb
support for execution of DSP operations within the context of a single processor at a minimal hardware
cost.

Refer to Chapter 3, “ColdFire Core,” for detailed information on the ColdFire V4e core architecture.

1.4.2 Debug Module (BDM)

The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
real-time trace and debug information. This allows the processor and system to be debugged at full speed
without the need for costly in-circuit emulators.

The MCF548x debug module provides support in three different areas:

• Real-time trace support: The ability to determine the dynamic execution path through an
application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel
output bus that reports processor execution status and data to an external BDM emulator system.

• Background debug mode (BDM): Provides low-level debugging in the ColdFire processor
complex. In BDM, the processor complex is halted and a variety of commands can be sent to the
processor to access memory and registers. The external BDM emulator uses a three-pin, serial,
full-duplex channel.

• Real-time debug support: BDM requires the processor to be halted, which many real-time
embedded applications cannot permit. Debug interrupts let real-time systems execute a unique
service routine that can quickly save key register and variable contents and return the system to
normal operation without halting. External development systems can access saved data, because
the hardware supports concurrent operation of the processor and BDM-initiated commands. In
addition, the option is provided to allow interrupts to occur.

1.4.3 JTAG

The MCF548x family supports circuit board test strategies based on the Test Technology Committee of
IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting
of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit

MCF548x Reference Manual, Rev. 3

1-6 Freescale Semiconductor

MCF548x Family Features

boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into
one shift register. Test logic, implemented using static logic design, is independent of the device system
logic. The MCF548x implementation can do the following:

• Perform boundary scan operations to test circuit board electrical continuity

• Sample MCF548x system pins during operation and transparently shift out the result in the
boundary scan register

• Bypass the MCF548x for a given circuit board test by effectively reducing the boundary-scan
register to a single bit

• Disable the output drive to pins during circuit-board testing

• Drive output pins to stable levels

1.4.4 On-Chip Memories

1.4.4.1 Caches

There are two independent caches associated with the ColdFire V4e core complex: a 32-Kbyte instruction
cache and a 32-Kbyte data cache. Caches improve system performance by providing single-cycle access
to the instruction and data pipelines. This decouples processor performance from system memory
performance, increasing bus availability for on-chip DMA or external devices.

1.4.4.2 System SRAM

The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access
in a single cycle. The location of the memory block can be set to any 32-Kbyte address boundary within
the 4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the
system stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the
processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing
commands from the debug module.

The SRAM module is also accessible by multiple non-core bus masters, such as the DMA controller, the
encryption accelerator, and the PCI Controller.

1.4.5 PLL and Chip Clocking Options

MCF548x products contain an on-chip PLL capable of accepting input frequencies from 30–66.66 MHz.

Table 1-2 contains the frequencies of the system buses for the members of the MCF548x family under

various core/SDRAM/PCI/Flexbus clocking options.

Table 1-2. MCF548x Family Clocking Options

Core

(MHz)

120.0–200 60.0–100 30.0–50.0 1:2

Internal XLB, SDRAM

Bus, and PSTCLK

Frequency (MHz)

CLKIN—PCI and FlexBus

Frequency (MHz)

Clock Ratio

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 1-7

1.4.6 Communications I/O Subsystem

1.4.6.1 DMA Controller

The communications subsystem contains an intelligent DMA unit that provides front line interrupt control
and data movement interface via a separate peripheral bus to the on-chip peripheral functions, leaving the
processor core free to handle higher level activities. This concurrent operation enables a significant boost
in overall system performance.

The communications subsystem can support up to 16 simultaneously enabled DMA tasks, with support for
up to two external DMA requests. It uses internal buffers to prefetch reads and post writes such that
bursting is used whenever possible. This optimizes both internal and external bus activity. The following
communications and computer control peripheral functions are integrated and controlled by the
communications subsystem:

• Up to two 10/100 Mbps fast Ethernet controllers (FECs)

• Optional universal serial bus (USB) version 2.0 device controller

• Up to four programmable serial controllers (PSCs)

•I2C peripheral interface

• DMA serial peripheral interface (DSPI)

• Two FlexCAN controller area network 2.0B controllers

1.4.6.2 10/100 Fast Ethernet Controller (FEC)

The FEC supports two standard MAC/PHY interfaces: 10/100 Mbps IEEE 802.3 MII and 10Mbps 7-wire
interface. The controller is full duplex, supports a programmable maximum frame length and
retransmission from the transmit FIFO following a collision.

Support for different Ethernet physical interfaces:

— 100 Mbps IEEE 802.3 MII
— 10 Mbps IEEE 802.3 MII
— 10 Mbps 7-wire interface

• IEEE 802.3 full-duplex flow control.

• Support for full-duplex operation (200 Mbps throughput) with a minimum system clock frequency
of 50 MHz.

• Support for half duplex operation (100 Mbps throughput) with a minimum system clock frequency
of 25 MHz.

• Retransmit from transmit FIFO following collision.

• Internal loopback for diagnostic purposes.

1.4.6.3 USB 2.0 Device (Universal Serial Bus)

The USB module implementation on the MCF548x product family provides all the logic necessary to
process the USB protocol as defined by version 2.0 specification for peripheral devices. It features the
following:

• High-speed operation up to 480 Mbps, full-speed operation at 12 Mbps, and low-speed operation
at 1.5 Mbps

• Physical interface on chip

• Bulk, interrupt, and isochronous transport modes.

• Six programmable in/out endpoints and one control endpoint

MCF548x Reference Manual, Rev. 3

1-8 Freescale Semiconductor

MCF548x Family Features

• 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM

1.4.6.4 Programmable Serial Controllers (PSCs)

The MCF548x product family supports four PSCs that can be independently configured to operate in the
following modes:

• Universal asynchronous receiver transmitter (UART) mode
— 5,6,7,8 bits of data plus parity
— Odd, even, none, or force parity
— Stop bit width programmable in 1/16 bit increments
— Parity, framing, and overrun error detection
— Automatic PSCCTS

• IrDA 1.0 SIR mode (SIR)
— Baud rate range of 2400–115200 bps

— Selectable pulse width: either 3/16 of the bit duration or 1.6 µs

• IrDA 1.1 MIR mode (MIR)
— Baud rate of 0.576 or 1.152 Mbps

• IrDA 1.1 FIR mode (FIR)
— Baud rate of 4.0 Mbps

• 8-bit soft modem mode (modem8)

• 16-bit soft modem mode (modem16)

• AC97 soft modem mode (AC97)

and PSCRTS modem control signals

Each PSC supports synchronous (USART) and asynchronous (UART) protocols. The PSCs can be used to
interface to external full-function modems or external codecs for soft modem support, as well as IrDA 1.1
or 1.0 interfaces. Both 8- and 16-bit data widths are supported. PSCs can be configured to support a
1200-baud plain old telephone system (POTS) modem, V.34 or V.90 protocols. The standard UART
interface supports connection to an external terminal/computer for debug support.

1.4.6.5 I2C (Inter-Integrated Circuit)

The MCF548x product family provides an I2C two-wire, bidirectional serial bus for on-board
communication. It features the following:

• Multimaster operation with arbitration and collision detection

• Calling address recognition and interrupt generation

• Automatic switching from master to slave on arbitration loss

• Software-selectable acknowledge bit

• Start and stop signal generation and detection

• Bus busy status detection

1.4.6.6 DMA Serial Peripheral Interface (DSPI)

The DSPI block operates as a basic SPI block with FIFOs providing support for external queue operation.
Data to be transmitted and data received reside in separate FIFOs. The FIFOs can be popped and pushed
by host software or by the system DMA controller. The DSPI supports these SPI features:

• Full-duplex, three-wire synchronous transfers

• Master and slave mode—two peripheral chip selects in master mode

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 1-9

• DMA support

1.4.6.7 Controller Area Network (CAN)

The FlexCAN modules are communication controllers implementing the CAN protocol. The CAN
protocol can be used as an industrial control serial data bus, meeting the specific requirements of real-time
processing and reliable operation in a harsh EMI environment, while maintaining cost-effectiveness. Each
of the two CAN controllers on the MCF548x family products contains sixteen message buffers. The CAN
controllers can be configured to either function as an interface with two separate CAN networks, or as a
single 32 message buffer CAN network.

1.4.7 DDR SDRAM Memory Controller

The DDR SDRAM memory controller is a glueless interface to DDR memories. The module uses a 32-bit
memory port and can address a maximum of 1 Gbyte of data with 16 64M x 8 (512-Mbit) devices, four
per chip select. The controller supplies two clock lines and respective inverted clock lines to help minimize
system complexity when using DDR. The module supports either DDR or SDR, but not both. This is due
to voltage differences between the memory technologies.

The supported memory clock rate is up to 133 MHz. At this memory clock rate, DDR memory can receive
data at an effective rate of up to 266 MHz.

• Support for up to 13 lines of row address, 11 lines of column address, two lines of bank address,
and up to four chip selects

• Memory bus width fixed at 32 bits

• Four chip selects support up to 1 GByte of SDRAM memory

• Support for page mode to maximize the data rate. Page mode remembers active pages for all four
chip selects

• Support for sleep mode and self refresh

• Cache line reads that can use critical word first. These reads can start in the center of a burst and
will wrap to the beginning. This allows the processor quicker access to a needed instruction.

All on-chip bus masters have access to DRAM. This includes PCI, the ColdFire V4e core, the
cryptography accelerator, and the DMA controller.

1.4.8 Peripheral Component Interconnect (PCI)

The PCI controller is a PCI V2.2-compliant bus controller and arbiter. The PCI bus is capable of 66-MHz
operation with a 32-bit address/data bus and support for five external masters.

The PCI module includes an inbound FIFO to increase performance when using an external bus master.
The bus can address all 4 Gbytes of PCI-addressable space.

The PCI bus is also multiplexed with the flexible local bus (FlexBus) address lines. If 32-bit non-muxed
local address and data is required, it can be obtained at the expense of utilizing the PCI bus.

When implemented, the PCI controller acts as the central resource, bus arbiter, and configuring master on
the PCI bus.

1.4.9 Flexible Local Bus (FlexBus)

The FlexBus module is intended to provide the user with basic functionality required to interface to
peripheral devices. The FlexBus interface is a multiplexed or non-multiplexed bus, with an operating

MCF548x Reference Manual, Rev. 3

1-10 Freescale Semiconductor

MCF548x Family Features

frequency from 33–66 MHz. The Flexbus is targeted to support external Flash memories, boot ROMs,
gate-array logic, or other simple target interfaces. Up to six chip selects are supported by the FlexBus.

Possible combinations of address and data bits are the following:

• Non-multiplexed 32-bit address and 32-bit data (32-bit address muxed over
PCI bus–PCI not usable)

• Multiplexed 32-bit address and 32-bit data (PCI usable)

• Multiplexed 32-bit address and 16-bit data

• Multiplexed 32-bit address and 8-bit data

The non-multiplexed 32-bit address and 32-bit data mode is determined at chip reset. For all other modes,
the full 32-bit address is driven during the address phase. The number of bytes used for data are determined
on a chip select by chip select basis.

1.4.10 Security Encryption Controller (SEC)

As consumers and businesses continue to embrace the Internet, the need for secure point-to-point
communications across what is an entirely insecure network has been met by the development of a range
of standard protocols. Computer cryptography fundamentally involves calculations with very large
numbers. Personal computers have sufficient processing power to implement these algorithms entirely in
software. When placed upon the embedded devices typically used for routing and remote access functions,
this same computational burden can potentially decrease the throughput of a 100 Mbps Ethernet interface
down to 10 Mbps.

Hardware acceleration of common cryptography algorithms is the solution to the computational bandwidth
requirements of Internet security standards. Discrete solutions currently address this problem, but the next
logical step is to integrate a cryptography accelerator on an embedded processor, such as the MCF548x
family.

Freescale has developed the SEC on the MCF548x family for this purpose. This block accelerates the core
cryptography algorithms that underlie standard Internet security protocols like SSL/TLS, IPSec, IKE, and
WTLS/WAP.

• The SEC includes execution units for the following:
— DES/3DES block cipher

— AES block cipher
— RC4 stream cipher
— MD5/SHA-1/SHA-256/HMAC hashing
— Random number generator compliant with FIPS 140-1 standards for randomness and

non-determinism

• Dual-channel architecture permits single-pass encryption and authentication

1.4.11 System Integration Unit (SIU)

1.4.11.1 Timers

The MCF548x family integrates several timer functions required by most embedded systems. Two internal
32-bit slice timers create short cycle periodic interrupts, typically utilized for RTOS scheduling and alarm
functionality. A watchdog timer resets the processor if not regularly serviced, catching software hang-ups.
Four 32-bit general purpose timers can perform input capture, output compare, and PWM functionality.

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 1-11

1.4.11.2 Interrupt Controller

The interrupt controller on the MCF548x family can support up to 63 interrupt sources. The interrupt
controller is organized as seven levels with nine interrupt sources per level. Each interrupt source has a
unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7]
and priority within the level.

• Support for up to 63 interrupt sources organized as follows:
— 56 fully-programmable interrupt sources
— 7 fixed-level interrupt sources

• Seven external interrupt signals

• Unique vector number for each interrupt source

• Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

• Support for hardware and software interrupt acknowledge (IACK) cycles

• Combinatorial path to provide wake-up from stop mode

1.4.11.3 General Purpose I/O

All peripheral I/O pins on the MCF548x family are multiplexed with GPIO, adding flexibility and usability
to all signals on the chip.

MCF548x Reference Manual, Rev. 3

1-12 Freescale Semiconductor

Chapter 2 Signal Descriptions

2.1 Introduction

This chapter describes the MCF548x signals.

The terms ‘assertion’ and ‘negation’ are used to avoid confusion when
dealing with a mixture of active-low and active-high signals. The term
‘asserted’ indicates that a signal is active, independent of the voltage level.
The term ‘negated’ indicates that a signal is inactive.

Active-low signals, such as RAS and TA, are indicated with an overbar.

2.1.1 Block Diagram

Figure 2-1 displays the signals of the MCF548x.

NOTE

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 2-1

FlexBus

SDRAM

Controller

PCI

Controller

PSCs

DSPI

[5:1] / PFBCS[5:1]

FBCS

ALE / PFBCTL0 / TBST

R/W / PFBCTL2 / TBST

BE/BWE3 / PFBCTL7 / TSIZ1

/BWE2 / PFBCTL6 / TSIZ0

BE

/BWE1 / PFBCTL5 / FBADDR1

BE

/BWE0 / PFBCTL4 / FBADDR0

BE

PCIAD[31:24] / FBADDR[31:24]
PCIAD[23:16] / FBADDR[23:16]

PCIAD[15:8] / FBADDR[15:8]

PCIAD[7:0] / FBADDR[7:0]

PCIBG[3:0] / PPCIBG[3:0] / TOUT[3:0]

PSC2CTS

PSC2RTS / PPSCH3 / PSC2FSYNC / CANTX0

DSPISCK / PDSPI2 / PSC3CTS / PSC3BCLK

DSPICS3 / PDSPI5 / TOUT3 / CANTX1
DSPICS2 / PDSPI4 / TOUT2 / CANTX1

DSPICS0/SS

/ PDSPI3 / PSC3RTS / PSC3FSYNC

PCIBG4

PCIBR4

PCIBR[3:0] / PPCIBR[3:0] / TIN[3:0]

/ PPSCL2 / PSC0BCLK

PSC0CTS

/ PPSCL3 / PSC0FSYNC

PSC0RTS

/ PPSCL6 / PSC1BCLK

PSC1CTS

/ PPSCL7 / PSC1FSYNC

PSC1RTS

/ PPSCH2 / PSC2BCLK / CANRX0

PSC3CTS / PPSCH6 / PSC3BCLK

/ PPSCH7 / PSC3FSYNC

PSC3RTS

DSPISOUT / PDSPI0 / PSC3TXD

DSPISIN / PDSPI1 / PSC3RXD

DSPICS5/PCSS

OE

TA

SDDATA[31:24]
SDDATA[23:16]

SDDATA[15:8]

SDADDR[12:0]

PCICXBE

/ PPCIBG4 / TBST

/ PPCIBR4 / IRQ4

PCS0TXD / PPSCL0

PSC0RXD / PPSCL1

PSC1TXD / PPSCL4

PSC1RXD / PPSCL5

PSC2TXD / PPSCH0

PSC2RXD / PPSCH1

PSC3TXD / PPSCH4

PSC3RXD / PPSCH5

AD[31:24]
AD[23:16]

AD15:8]

AD[7:0]

FBCS0

/ PFBCTL3

/ PFBCTL1

SDDATA[7:0]

SDBA[1:0]

RAS
CAS

SDCS[3:0]

SDDM[3:0]

SDDQS[3:0]

SDCLK[1:0]

[1:0]

SDCLK

SDWE

SDCKE

SDRDQS

VREF

[3:0]

PCIDEVSEL

PCIFRM

PCIIDSEL

PCIIRDY

PCIPAR

PCIPERR

PCIRESET

PCISERR
PCISTOP

PCITRDY

/ PDSPI6

MCF548x

E0MDIO / PFECI2C3
E0MDC / PFECI2C2
E0TXCLK / PFEC0H7
E0TXEN / PFEC0H6
E0TXD0 / PFEC0H5
E0COL / PFEC0H4
E0RXCLK / PFEC0H3
E0RXDV / PFEC0H2
E0RXD0 / PFEC0H1
E0CRS / PFEC0H0
E0TXD[3:1] / PFEC0L[7:5]
E0TXER / PFEC0L4
E0RXD[3:1] / PFEC0L[3:1]
E0RXER / PFEC0L0

E1MDIO / SDA / CANRX0
E1MDC / SCL / CANTX0
E1TXCLK / PFEC1H7
E1TXEN / PFEC1H6
E1TXD0 / PFEC1H5
E1COL / PFEC1H4
E1RXCLK / PFEC1H3
E1RXDV / PFEC1H2
E1RXD0 / PFEC1H1
E1CRS / PFEC1H0
E1TXD[3:1] / PFEC1L[7:5]
E1TXER / PFEC1L4
E1RXD[3:1] / PFEC1L[3:1]
E1RXER / PFEC1L0

USBD+
USBD–
USBVBUS

USBRBIAS
USBCLKIN
USBCLKOUT

SDA / PFECI2C1
SCL / PFECI2C0

IRQ7 / PIRQ7
IRQ[6:5] / PIRQ[6:5] / CANRX1

DREQ1 / PDMA1 / TIN1 / IRQ1
DREQ0 / PDMA0 / TIN0
DACK[1:0] / PDMA[3:2] / TOUT[1:0]

TIN3 / PTIM7 / IRQ3 / CANRX1
TOUT3 / PTIM6 / CANTX1
TIN2 / PTIM5 / IRQ2 / CANRX1
TOUT2 / PTIM4 / CANTX1
TIN1
TOUT1
TIN0
TOUT0

PSTCLK
PSTDDATA[7:0]
DSCLK / TRST
BKPT / TMS
DSI / TDI
DSO / TDO
TCK

MTMOD[3:0]
RSTI
RSTO
CLKIN

EVDD
IVDD
VSS
SDVDD
PLLVDD
PLLVSS
USB_OSCVDD
USB_PHYVDD
USB_OSCAVDD
USB_PLLVDD
USBVDD

Ethernet
MAC 0

Ethernet
MAC 1

USB

I2C

External
Interrupts
Port

DMA
Controller

Timer
Module

Debug &
JTAG
Tes t Po r t
Control

Tes t /
Reset &
Clock

Power
Supplies

Figure 2-1. MCF548x Signals

MCF548x Reference Manual, Rev. 3

2-2 Freescale Semiconductor

Table 2-1 lists the signals for the MCF548x in functional group order.

Table 2-1. MCF548x Signal Description

Pin Functions

PBGA Pin

Primary GPIO Secondary Ter t iary

FlexBus

Description I/O

Introduction

Drive

Pull-up

Reset

State

AE2, AF3, AF1,

AE3, AE4, AD5,

AF2, AD4

AD3, AC3, AD2,
AC2, AA4, AE1,

AC1, AD1

AB2, AA3, W4,

AB1, AA2, AA1,

Y1, Y2

W3, W1, W2, V3,

V1, V2, T4, U3

R1, T2, T3, T1, U2 FBCS

U1 FBCS0 — — — Chip select 0 O 24 High

AD6 ALE PFBCTL0 TBST — Address Latch Enable O:I/O 16 High

AE5 R/W PFBCTL2 TBST — Read/write O:I/O 16 Hi-Z

AF4 BE/BWE3 PFBCTL7 TSIZ1 — Byte enables O:I/O 16 High

AF5 BE/BWE2 PFBCTL6 TSIZ0 — Byte enables O:I/O 16 High

AC4 BE/BWE1 PFBCTL5 FBADDR1 — Byte enables O:I/O 16 High

AE7 BE/BWE0 PFBCTL4 FBADDR0 — Byte enables O:I/O 16 High

AD[31:24] — — — Multiplexed

address/data bus

AD[23:16] — — — Multiplexed

address/data bus

AD[15:8] — — — Multiplexed

address/data bus

AD[7:0] — — — Multiplexed

address/data bus

[5:1] PFBCS[5:1] — — Chip selects 5–1 O:I/O 24 High

I/O 16 Hi-Z

I/O 16 Hi-Z

I/O 16 Hi-Z

I/O 16 Hi-Z

AE6 OE PFBCTL3 — — Output enable O:I/O 16 High

AF6 TA PFBCTL1 — — Transfer acknowledge I:I/O 16 —

SDRAM Controller

C10, B9, A8, D5,

A6, C8, B7, A5

A4, C7, B6, B4,

C5, B3, C4, D4

E2, D1, G4, E1,

K4, F1, G2, H3

N4, G1, H2, J3,

J1, M4, K3, K2

A13, A12, D10,
B12, C12, A11,

D8, B11, C11,

A10, D7, B10, A9

Freescale Semiconductor 2-3

SDDATA[31:24] — — — SDRAM data bus I/O 24 Hi-Z

SDDATA[23:16] — — — SDRAM data bus I/O 24 Hi-Z

SDDATA[15:8] — — — SDRAM data bus I/O 24 Hi-Z

SDDATA[7:0] — — — SDRAM data bus I/O 24 Hi-Z

SDADDR[12:0] — — — SDRAM address bus O 24 Low

MCF548x Reference Manual, Rev. 3

PBGA Pin

Table 2-1. M C F 548x Signal Description (Continued)

Pin Functions

Primary GPIO Secondary Ter t iary

Description I/O

Drive

Reset

Pull-up

State

M2, M3 SDBA[1:0] — — — SDRAM bank

addresses

E3 RAS — — — SDRAM row address

strobe

C2 CAS — — — SDRAM column

address strobe

R2, P2, P1, N3 SDCS[3:0] — — — SDRAM chip selects O 24 High

B8, A3, G3, J2 SDDM[3:0] — — — SDRAM write data

byte mask

A7, B5, F2, H1 SDDQS[3:0] — — — SDRAM data strobe I/O 24 High

L1, N1 SDCLK[1:0] — — — SDRAM clock O 24 Low

M1, N2 SDCLK

K1 SDWE — — — SDRAM write enable O 24 Low

E4 SDCKE — — — SDRAM clock enable O 24 Low

L2 SDRDQS — — — SDR SDRAM data

D2 VREF — — — SDRAM reference

[1:0] — — — Inverted SDRAM

clock

strobe

voltage

O24Low

O24High

O24High

O24High

O24Low

O24Low

I——

PCI Controller

V25, V26, U25,

U26, T24, T25,

T26, R24

R25, R26, P26,

P24, P23, P25,

N25, N23

N26, N24, M26,

M25, L26, L25,

K26, K25

J26, K24, J25,

H26, J24, G26,

H25, K23

F26, G25, E26,

G24

J23 PCIDEVSEL ———PCI device select I/O 16 Hi-Z

F25 PCIFRM ———PCI frame I/O 16 Hi-Z

C23 PCIIDSEL — — — PCI initialization

PCIAD[31:24] — FBADDR[31:24] — PCI address/data bus I/O 16 Hi-Z

PCIAD[23:16] — FBADDR[23:16] — PCI address/data bus I/O 16 Hi-Z

PCIAD[15:8] — FBADDR[15:8] — PCI address/data bus I/O 16 Hi-Z

PCIAD[7:0] — FBADDR[7:0] — PCI address/data bus I/O 16 Hi-Z

PCICXBE[3:0] — — — PCI command/byte

enables

device select

I/O 16 Hi-Z

I — —

MCF548x Reference Manual, Rev. 3

2-4 Freescale Semiconductor

Introduction

Table 2-1. M C F 548x Signal Description (Continued)

Pin Functions

PBGA Pin

Primary GPIO Secondary Ter t iary

D24 PCIIRDY ———PCI initiator ready I/O 16 Hi-Z

F23 PCIPAR — — — PCI parity I/O 16 Hi-Z

D26 PCIPERR ———PCI parity error I/O 16 Hi-Z

G23 PCIRESET ———PCI reset O 16 Low

F24 PCISERR ———PCI system error I/O 16 Hi-Z

E25 PCISTOP ———PCI stop I/O 16 Hi-Z

C26 PCITRDY — — — PCI target ready I/O 16 Hi-Z

W24 PCIBG4 PPCIBG4 TBST — PCI external grant 4 O:I/O 16 GPI

Description I/O

Drive

Pull-up

Reset

State

Y26, W25, V24,

PCIBG[3:0] PPCIBG[3:0] TOUT[3:0] — PCI external grant 3–0 O:I/O 16 GPI

W26

D21 PCIBR4 PPCIBR4 IRQ4 — PCI external

I:I/O Y18 GPI

request 4

B24 PCIBR3 PPCIBR3 TIN3 — PCI external

I:I/O Y18 GPI

request 3

A25, B23, A24 PCIBR[2:0] PPCIBR[2:0] TIN[2:0] — PCI external

I:I/O 8 GPI

request 2–0

External Interrupts Port

D14 IRQ7 PIRQ7 — — External interrupt

I:I/O — —

request 7

B14, A14 IRQ[6:5] PIRQ[6:5] CANRX1 — External interrupt

I:I/O — —

request 6–5

Ethernet MAC 0

AF10 E0MDIO PFECI2C3 — — Management channel

I/O 8 GPI

serial data

AD11 E0MDC PFECI2C2 — — Management channel

O:I/O 8 GPI

clock

AF9 E0TXCLK PFEC0H7 — — MAC transmit clock I:I/O 8 GPI

AE10 E0TXEN PFEC0H6 — — MAC transmit enable O:I/O 8 GPI

AD9 E0TXD0 PFEC0H5 — — MAC transmit data O:I/O 8 GPI

AC9 E0COL PFEC0H4 — — MAC collision I:I/O 8 GPI

AD14 E0RXCLK PFEC0H3 — — MAC receive clock I:I/O 8 GPI

AE14 E0RXDV PFEC0H2 — — MAC receive enable I:I/O 8 GPI

AD13 E0RXD0 PFEC0H1 — — MAC receive data I:I/O 8 GPI

AE19 E0CRS PFEC0H0 — — MAC carrier sense I:I/O 8 GPI

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 2-5

Table 2-1. M C F 548x Signal Description (Continued)

Pin Functions

PBGA Pin

Primary GPIO Secondary Ter t iary

AD8, AC6, AF7 E0TXD[3:1] PFEC0L[7:5] — — MAC transmit data O:I/O 8 GPI

AE9 E0TXER PFEC0L4 — — MAC transmit error O:I/O 8 GPI

Description I/O

Drive

Pull-up

Reset

State

AF11, AF12,

E0RXD[3:1] PFEC0L[3:1] — — MAC receive data I:I/O 8 GPI

AF13

AC14 E0RXER PFEC0L0 — — MAC receive error I:I/O 8 GPI

Ethernet MAC 1

2

AE25

E1MDIO — SDA CANRX0 Management channel

I/O Y18 —

serial data

2

AD24

E1MDC — SCL CANTX0 Management channel

O:I/O Y18 —

clock

2

AE13

2

AD25

2

AE12

2

AF8

2

B22

2

B25

2

AF24

2

AC5

AC82, AC112,

AE11

AE24

2

2

D252, B262, A26

2

AE8

E1TXCLK PFEC1H7 — — MAC Transmit clock I:I/O Y18 GPI

E1TXEN PFEC1H6 — — MAC Transmit enable O:I/O Y18 GPI

E1TXD0 PFEC1H5 — — MAC Transmit data O:I/O Y18 GPI

E1COL PFEC1H4 — — MAC Collision I:I/O Y18 GPI

E1RXCLK PFEC1H3 — — MAC Receive clock I:I/O Y18 GPI

E1RXDV PFEC1H2 — — MAC Receive enable I:I/O Y18 GPI

E1RXD0 PFEC1H1 — — MAC Receive data I:I/O Y18 GPI

E1CRS PFEC1H0 — — MAC Carrier sense I:I/O Y18 GPI

E1TXD[3:1] PFEC1L[7:5] — — MAC Transmit data O:I/O Y18 GPI

E1TXER PFEC1L4 — — MAC Transmit error O:I/O Y18 GPI

2

E1RXD[3:1] PFEC1L[3:1] — — MAC Receive data I:I/O Y18 GPI

E1RXER PFEC1L0 — — MAC Receive error I:I/O Y18 GPI

USB

3

AF16

AF17

AC17

3

3

USBD+ — — — USB differential data I/O 24 —

USBD- — — — USB differential data I/O 24 —

USBVBUS — — — USB Vbus monitor

I — —

input

AF18 USBRBIAS — — — USB bias resistor I — —

3

AF15

AF14

3

USBCLKIN — — — USB crystal input I — —

USBCLKOUT — — — USB crystal output O 24 —

DSPI

Y24 DSPISOUT PDSPI0 PSC3TXD — QSPI data out O:I/O 24 GPI

MCF548x Reference Manual, Rev. 3

2-6 Freescale Semiconductor

Introduction

Table 2-1. M C F 548x Signal Description (Continued)

Pin Functions

PBGA Pin

Primary GPIO Secondary Ter t iary

AC24 DSPISIN PDSPI1 PSC3RXD — QSPI data in I:I/O 24 GPI

AD22 DSPISCK PDSPI2 PSC3CTS PSC3BCLK QSPI clock I/O 24 GPI

W23 DSPICS5/PCSS PDSPI6 — — QSPI chip select O:I/O 24 GPI

V23 DSPICS3 PDSPI5 TOUT3 CANTX1 QSPI chip select O:I/O 24 GPI

AA26 DSPICS2 PDSPI4 TOUT2 CANTX1 QSPI chip select O:I/O 24 GPI

Y25 DSPICS0/SS PDSPI3 PSC3RTS PSC3FSYNC QSPI chip select O:I/O 24 GPI

I2C

C24 SDA PFECI2C1 — — I
C25 SCL PFECI2C0 — — I

PSCs

AA25 PSC0TXD PPSC1PSC00 — — PSC0 transmit data O:I/O 8 GPI

Description I/O

Drive

Pull-up

2

C Serial data I/O 8 GPI

2

C Serial clock I/O 8 GPI

Reset

State

AC21 PSC0RXD PPSC1PSC01 — — PSC0 receive data I:I/O 8 GPI

AE23 PSC0CTS PPSC1PSC03 PSC0BCLK — PSC0 clear to send I:I/O 8 GPI

AB26 PSC0RTS PPSC1PSC02 PSC0FSYNC — PSC0 request to send I/O 8 GPI

AB25 PSC1TXD PPSC1PSC04 — — PSC1 transmit data O:I/O 8 GPI

AE22 PSC1RXD PPSC1PSC05 — — PSC1 receive data I:I/O 8 GPI

AF25 PSC1CTS PPSC1PSC07 PSC1BCLK — PSC1 clear to send I:I/O 8 GPI

Y23 PSC1RTS PPSC1PSC06 PSC1FSYNC — PSC1 request to send I/O 8 GPI

AC26 PSC2TXD PPSC3PSC20 — — PSC2 transmit data O:I/O 8 GPI

AD21 PSC2RXD PPSC3PSC21 — — PSC2 receive data I:I/O 8 GPI

AC19 PSC2CTS PPSC3PSC23 PSC2BCLK CANRX0 PSC2 clear to send I:I/O 8 GPI

AD26 PSC2RTS PPSC3PSC22 PSC2FSYNC CANTX0 PSC2 request to send I/O 8 GPI

AE26 PSC3TXD PPSC3PSC24 — — PSC3 transmit data O:I/O 8 GPI

AE21 PSC3RXD PPSC3PSC25 — — PSC3 receive data I:I/O 8 GPI

AF23 PSC3CTS PPSC3PSC27 PSC3BCLK — PSC3 clear to send I:I/O 8 GPI

AB23 PSC3RTS PPSC3PSC26 PSC3FSYNC — PSC3 request to send I/O 8 GPI

DMA Controller

AF19 DREQ1 PDMA1 TIN1 IRQ1 DMA request I:I/O 8 GPI

AF20 DREQ0 PDMA0 TIN0 — DMA request I:I/O 8 GPI

AC25, AB24 DACK[1:0] PDMA[3:2] TOUT[1:0] — DMA acknowledge O:I/O 8 GPI

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 2-7

Table 2-1. M C F 548x Signal Description (Continued)

Pin Functions

PBGA Pin

Primary GPIO Secondary Ter t iary

Timer Module

AD19 TIN3 PTIM7 IRQ3 CANRX1 Timer input I:I/O 8 GPI

AD23 TOUT3 PTIM6 CANTX1 — Timer output O:I/O 8 GPI

AF21 TIN2 PTIM5 IRQ2 CANRX1 Timer input I:I/O 8 GPI

AC22 TOUT2 PTIM4 CANTX1 — Timer output O:I/O 8 GPI

AE20 TIN1 — — — Timer input I 8 GPI

AC23 TOUT1 — — — Timer output O 8 GPI

AF22 TIN0 — — — Timer input I 8 GPI

AF26 TOUT0 — — — Timer output O 8 GPI

Debug and JTAG Test Port Control

Description I/O

Drive

Pull-up

Reset

State

D20 PSTCLK — — — Processor clock

output

A23, B21, D18,
C20, A22, B20,

A21, B19

C15 DSCLK — TRST — Debug clock / TAP

B15 BKPT — TMS — Breakpoint/TAP test

A15 DSI — TDI — Debug data in / TAP

D17 DSO — TDO — Debug data out / TAP

A16 TCK — — — TAP clock I — —

B17, C14, A18,

B16

B13 RSTI — — — Reset input I — —

A20 RSTO — — — Reset output O 8 Low

A17 CLKIN — — — Clock input I — —

PSTDDATA[7:0] — — — Processor status

debug data

reset

mode select

data in

data out

Test, Reset, and Clock

MTMOD[3:0] — — — Test mode pins I — —

O 8 High

O 8 High

I Y — —

I Y — —

I Y — —

O 8 High

D15 NC — — — No Connect I — —

AC15 NC — — — No Connect I — —

MCF548x Reference Manual, Rev. 3

2-8 Freescale Semiconductor

PBGA Pin

Table 2-1. M C F 548x Signal Description (Continued)

Pin Functions

Primary GPIO Secondary Ter t iary

Power Supplies

Description I/O

Introduction

Drive

Pull-up

Reset

State

C16, C22, E24,

H24, M24, R3,

U24, Y3, AA24,

AB3, AD7, AD10,

AD18

C18, D11, D12,

D19, D22, H4,

H23, L23, P4,

R23, V4, AA23,

AC12, AC20

A2, B2, C3, C17,

C19, C21, D6, D9,

D13, D16, D23,

E23, F4, J4, L4,

L11, L12, L13,
L14, L15, L16,

L24, M11, M12,
M13, M14, M15,
M16, M23, N11,

N12, N13, N14,

N15, N16, P11,

P12, P13, P14,

P15, P16, R4,
R11, R12, R13,
R14, R15, R16,

T11, T12, T13,
T14, T15, T16,

T23, U4, U23, Y4,

AB4, AC7, AC10,

AC18, AD12,

AD17, AD20,

AE15, AE16,

AE17

EVDD — — — Positive I/O supply I — —

IVDD — — — Positive core supply I — —

VSS — — Ground

A1, B1, C1, C6,

C9, C13, D3, F3,

SDVDD — — — Positive SDRAM

supply

L3, P3

A19 PLLVDD — — — Positive PLL analog

supply

B18 PLLVSS — — — PLL ground

4

AC13

AC16

AD15

4

4

USB_OSCVDD — — — USB oscillator supply

USB_PHYVDD — — — USB PHY supply

USB_OSCAVDD — — — USB oscillator analog

supply

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 2-9

Table 2-1. M C F 548x Signal Description (Continued)

Pin Functions

PBGA Pin

Primary GPIO Secondary Ter t iary

4

AD16

4

AE18

1

Pull-up resistor when configured for general purpose input (default state after reset).

2

This pin is a “no connect” on the MCF5483 and MCF5482 devices.

3

This pin is a “no connect” on the MCF5481 and MCF5480 devices.

4

This pin is a “no connect” on the MCF5481 and MCF5480 devices. On MCF5485, MCF5484, MCF5483, and MCF5482 device the pin

USB_PLLVDD — — — USB PLL supply

USBVDD — — — USB supply

Description I/O

Drive

Pull-up

should be connected to the appriopriate power rail even is USB is not being used.

Table 2-2 lists the MCF548x signals in pin number order for the 388 PBGA package.

Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number

Reset

State

Pin Functions

Pin Functions

Primary GPIO Secondary Tertiary Primary GPIO Secondary Tertiary

PBGA Pin

A1 SDVDD — — — P1 SDCS1

PBGA Pin

———

A2 VSS — — — P2 SDCS2 ———

A3 SDDM2 — — — P3 SDVDD — — —

A4 SDDATA23 — ——P4IVDD — — —

A5 SDDATA24 — — — P11 VSS — — —

A6 SDDATA27 — — — P12 VSS — — —

A7 SDDQS3 — — — P13 VSS — — —

A8 SDDATA29 — — — P14 VSS — — —

A9 SDADDR0 — — — P15 VSS — — —

A10 SDADDR3 — — — P16 VSS — — —

A11 SDADDR7 — — — P23 PCIAD19 — FBADDR19 —

A12 SDADDR11 — — — P24 PCIAD20 — FBADDR20 —

A13 SDADDR12

— — — P25 PCIAD18 — FBADDR18 —

A14 IRQ5 PIRQ5 CANRX1 — P26 PCIAD21 — FBADDR21 —

A15 DSI — TDI — R1 FBCS5 PFBCS5 — —

A16 TCK — — — R2 SDCS3 ———

A17 CLKIN — — — R3 EVDD — — —

A18 MTMOD1 — — — R4 VSS — — —

A19 PLLVDD — — — R11 VSS — — —

A20 RSTO

— — — R12 VSS — — —

MCF548x Reference Manual, Rev. 3

2-10 Freescale Semiconductor

Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)

Introduction

Pin Functions

Pin Functions

Primary GPIO Secondary Tertiary Primary GPIO Secondary Tertiary

PBGA Pin

A21 PSTDDATA1

A22 PSTDDATA3

— — — R13 VSS — — —

— — — R14 VSS — — —

PBGA Pin

A23 PSTDDATA7 — — — R15 VSS — — —

A24 PCIBR0 PPCIBR0 TIN0 — R16 VSS — — —

A25 PCIBR2 PPCIBR2 TIN2 — R23 IVDD — — —

A261E1RXD1 PFEC1L5 — — R24 PCIAD24 — FBADDR24 —

B1 SDVDD — — — R25 PCIAD23 — FBADDR23 —

B2 VSS — — — R26 PCIAD22 — FBADDR22 —

B3 SDDATA18 — ——T1FBCS2PFBCS2 — —

B4 SDDATA20 — ——T2FBCS4PFBCS4 — —

B5 SDDQS2 — ——T3FBCS3PFBCS3 — —

B6 SDDATA21 — ——T4AD1 — — —

B7 SDDATA25 — — — T11 VSS — — —

B8 SDDM3 — — — T12 VSS — — —

B9 SDDATA30 — — — T13 VSS — — —

B10 SDADDR1 — — — T14 VSS — — —

B11 SDADDR5 — — — T15 VSS — — —

B12 SDADDR9 — — — T16 VSS — — —

B13 RSTI — — — T23 VSS — — —

B14 IRQ6 PIRQ6 CANRX1 — T24 PCIAD27 — FBADDR27 —

B15 BKPT

— TMS — T25 PCIAD26 — FBADDR26 —

B16 MTMOD0 — — — T26 PCIAD25 — FBADDR25 —

B17 MTMOD3 — — — U1 FBCS0 ———

B18 PLLVSS — — — U2 FBCS1 PFBCS1 — —

B19 PSTDDATA0 — ——U3AD0 — — —

B20 PSTDDATA2 — — — U4 VSS — — —

B21 PSTDDATA6 — — — U23 VSS — — —

B221E1RXCLK PFEC1H3 — — U24 EVDD — — —

B23 PCIBR1 PPCIBR1 TIN1 — U25 PCIAD29 — FBADDR29 —

B24 PCIBR3

PPCIBR3 TIN3 — U26 PCIAD28 — FBADDR28 —

B251E1RXDV PFEC1H2 — —V1 AD3 — — —

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 2-11

Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)

Pin Functions

Primary GPIO Secondary Tertiary Primary GPIO Secondary Tertiary

PBGA Pin

B261E1RXD2 PFEC1L2 — —V2 AD2 — — —

C1 SDVDD

C2 CAS — ——V4IVDD — — —

C3 VSS — — — V23 DSPICS3 PDSPI5 TOUT3 CANTX1

C4 SDDATA17 — — — V24 PCIBG1 PPCIBG1 TOUT1 —

C5 SDDATA19 — — — V25 PCIAD31 — FBADDR31 —

C6 SDVDD — — — V26 PCIAD30 — FBADDR30 —

C7 SDDATA22 — ——W1AD6 — — —

C8 SDDATA26 — ——W2AD5 — — —

C9 SDVDD — ——W3AD7 — — —

C10 SDDATA31 — ——W4AD13 — — —

C11 SDADDR4 — — — W23 DSPICS5/PCSS PDSPI6 — —

C12 SDADDR8 — ——W24PCIBG4PPCIBG4 TBST —

C13 SDVDD — ——W25PCIBG2PPCIBG2 TOUT2 —

— ——V3AD4 — — —

PBGA Pin

Pin Functions

C14 MTMOD2 — ——W26PCIBG0PPCIBG0 TOUT0 —

C15 DSCLK —TRST —Y1 AD9 — — —

C16 EVDD — ——Y2AD8 — — —

C17 VSS — — — Y3 EVDD — — —

C18 IVDD — — — Y4 VSS — — —

C19 VSS — — — Y23 PSC1RTS PPSC1PSC06 PSC1FSYNC —

C20 PSTDDATA4

C21 VSS — — — Y25 DSPICS0/SS PDSPI3 — —

C22 EVDD — — — Y26 PCIBG3 PPCIBG3 TOUT3 —

C23 PCIIDSEL — — — AA1 AD10 — — —

C24 SDA PFECI2C1 — — AA2 AD11 — — —

C25 SCL PFECI2C0 — — AA3 AD14 — — —

C26 PCITRDY — — — AA4 AD19 — — —

D1 SDDATA14 — — — AA23 IVDD ———

D2 VREF — — — AA24 EVDD — — —

D3 SDVDD

D4 SDDATA16 — — — AA26 DSPICS2 PDSPI4 TOUT2 CANTX1

— — — Y24 DSPISOUT PDSPI0 PSC3TXD —

— — — AA25 PCS0TXD PPSC1PSC00 — —

MCF548x Reference Manual, Rev. 3

2-12 Freescale Semiconductor

Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)

Introduction

Pin Functions

Pin Functions

Primary GPIO Secondary Tertiary Primary GPIO Secondary Tertiary

PBGA Pin

D5 SDDATA28

D6 VSS

— — — AB1 AD12 — — —

— — — AB2 AD15 — — —

PBGA Pin

D7 SDADDR2 — — — AB3 EVDD — — —

D8 SDADDR6 — — — AB4 VSS — — —

D9 VSS — — — AB23 PSC3RTS PPSC3PSC26 PSC3FSYNC —

D10 SDADDR10 — — — AB24 DACK0 PDMA2 TOUT0 —

D11 IVDD — — — AB25 PSC1TXD PPSC1PSC04 — —

D12 IVDD — — — AB26 PSC0RTS PPSC1PSC02 PSC0FSYNC —

D13 VSS — ——AC1AD17 — — —

D14 IRQ7 PIRQ7 ——AC2AD20 — — —

D15 NC — ——AC3AD22 — — —

D16 VSS — ——AC4BE/BWE1 PFBCTL5 FBADDR1 —

D17 DSO —TDO —AC5

1

E1CRS PFEC1H0 — —

D18 PSTDDATA5 — ——AC6E0TXD2PFEC0L6— —

D19 IVDD — — — AC7 VSS — — —

D20 PSTCLK — ——AC8

1

E1TXD3 PFEC1L7 — —

D21 PCIBR4 PPCIBR4 IRQ4 — AC9 E0COL PFEC0H4 — —

D22 IVDD — — — AC10 VSS — — —

D23 VSS — ——AC11

1

E1TXD2 PFEC1L6 — —

D24 PCIIRDY — ——AC12IVDD — — —

D251E1RXD3 PFEC1L3 — — AC132USB_OSCVDD — — —

D26 PCIPERR — — — AC14 E0RXER PFEC0L0 — —

E1 SDDATA12 — ——AC15NC — — —

E2 SDDATA15 — ——AC162USB_PHYVDD — — —

E3 RAS — ——AC17

2

USBVBUS — — —

E4 SDCKE — — — AC18 VSS — — —

E23 VSS — — — AC19 PSC2CTS PPSC3PSC23 PSC2BCLK CANRX0

E24 EVDD — ——AC20IVDD — — —

E25 PCISTOP — — — AC21 PSC0RXD PPSC1PSC01 — —

E26 PCICXBE1

— — — AC22 TOUT2 PTIM4 CANTX1 —

F1 SDDATA10 — ——AC23TOUT1 — — —

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 2-13

Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)

Pin Functions

Pin Functions

Primary GPIO Secondary Tertiary Primary GPIO Secondary Tertiary

PBGA Pin

F2 SDDQS1

F3 SDVDD

— — — AC24 DSPISIN PDSPI1 PSC3RXD —

— ——AC25DACK1PDMA3 TOUT1 —

PBGA Pin

F4 VSS — — — AC26 PSC2TXD PPSC3PSC20 — —

F23 PCIPAR — ——AD1AD16 — — —

F24 PCISERR — ——AD2AD21 — — —

F25 PCIFRM — ——AD3AD23 — — —

F26 PCICXBE3 — ——AD4AD24 — — —

G1 SDDATA6 — ——AD5AD26 — — —

G2 SDDATA9 — — — AD6 ALE PFBCTL0 TBST —

G3 SDDM1 — — — AD7 EVDD — — —

G4 SDDATA13 — — — AD8 E0TXD3 PFEC0L7 — —

G23 PCIRESET — — — AD9 E0TXD0 PFEC0H5 — —

G24 PCICXBE0 — — — AD10 EVDD — — —

G25 PCICXBE2 — — — AD11 E0MDC PFECI2C2 — —

G26 PCIAD2 — FBADDR2 — AD12 VSS — — —

H1 SDDQS0 — — — AD13 E0RXD0 PFEC0H1 — —

H2 SDDATA5 — — — AD14 E0RXLK PFEC0H3 — —

H3 SDDATA8 — ——AD152USB_OSCAVDD — — —

H4 IVDD — ——AD162USB_PLLVDD — — —

H23 IVDD — — — AD17 VSS — — —

H24 EVDD

— — — AD18 EVDD — — —

H25 PCIAD1 — FBADDR1 — AD19 TIN3 PTIM7 IRQ3 CANRX1

H26 PCIAD4 — FBADDR4 — AD20 VSS — — —

J1 SDDATA3 — — — AD21 PSC2RXD PPSC3PSC21 — —

J2 SDDM0 — — — AD22 DSPISCK PDSPI2 PSC3CTS PSC3BCLK

J3 SDDATA4 — — — AD23 TOUT3 PTIM6 CANTX1 —

J4 VSS — ——AD24

J23 PCIDEVSEL — ——AD25

1

E1MDC — SCL CANTX0

1

E1TXEN PFEC1H6 — —

J24 PCIAD3 — FBADDR3 — AD26 PSC2RTS PPSC3PSC22 PSC2FSYNC CANTX0

J25 PCIAD5

— FBADDR5 — AE1 AD18 — — —

J26 PCIAD7 — FBADDR7 — AE2 AD31 — — —

MCF548x Reference Manual, Rev. 3

2-14 Freescale Semiconductor

Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)

Introduction

Pin Functions

Pin Functions

Primary GPIO Secondary Tertiary Primary GPIO Secondary Tertiary

PBGA Pin

K1 SDWE

K2 SDDATA0

— — — AE3 AD28 — — —

— — — AE4 AD27 — — —

PBGA Pin

K3 SDDATA1 — — — AE5 R/W PFBCTL2 TBST —

K4 SDDATA11 — — — AE6 OE PFBCTL3 — —

K23 PCIAD0 — FBADDR0 — AE7 BE/BWE0 PFBCTL4 FBADDR0 —

K24 PCIAD6 — FBADDR6 — AE8

1

E1RXER PFEC1L0 — —

K25 PCIAD8 — FBADDR8 — AE9 E0TXER PFEC0L4 — —

K26 PCIAD9 — FBADDR9 — AE10 E0TXEN PFEC0H6 — —

L1 SDCLK1 — ——AE11

L2 SDRDQS — ——AE12

L3 SDVDD — ——AE13

1

E1TXD1 PFEC1L5 — —

1

E1TXD0 PFEC1h5 — —

1

E1TXCLK PFEC1H7 — —

L4 VSS — — — AE14 E0RXDV PFEC1H2 — —

L11 VSS — — — AE15 VSS — — —

L12 VSS — — — AE16 VSS — — —

L13 VSS — — — AE17 VSS — — —

L14 VSS — ——AE18

2

USBVDD — — —

L15 VSS — — — AE19 E0CRS PFEC0H0 — —

L16 VSS — — — AE20 TIN1 — — —

L23 IVDD — — — AE21 PSC3RXD PPSC3PSC25 — —

L24 VSS — — — AE22 PSC1RXD PPSC1PSC05 — —

L25 PCIAD10

L26 PCIAD11 — FBADDR11 — AE24

M1 SDCLK1 — ——AE25

— FBADDR10 — AE23 PSC0CTS PPSC1PSC03 PSC0BCLK —

1

E1TXER PFEC1L4 — —

1

E1MDIO — SCL CANTX0

M2 SDBA1 — — — AE26 PSC3TXD PPSC3PSC24 — —

M3 SDBA0 — ——AF1AD29 — — —

M4 SDDATA2 — ——AF2AD25 — — —

M11 VSS — ——AF3AD30 — — —

M12 VSS — — — AF4 BE/BWE3 PFBCTL7 TSIZ1 —

M13 VSS — — — AF5 BE/BWE2 PFBCTL6 TSIZ0 —

M14 VSS

— ——AF6TAPFBCTL1 — —

M15 VSS — — — AF7 E0TXD1 PFEC0L5 — —

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 2-15

Table 2-2. MCF5485/MCF5484 Signal Description by Pin Number (Continued)

Pin Functions

Primary GPIO Secondary Tertiary Primary GPIO Secondary Tertiary

PBGA Pin

M16 VSS — ——AF8

M23 VSS

M24 EVDD — — — AF10 E0MDIO PFECI2C3 — —

M25 PCIAD12 — FBADDR12 — AF11 E0RXD3 PFEC0L3 — —

M26 PCIAD13 — FBADDR13 — AF12 E0RXD2 PFEC0L2 — —

N1 SDCLK0 — — — AF13 E0RXD1 PFEC0L1 — —

N2 SDCLK0 — ——AF143USBCLKOUT — — —

N3 SDCS0 — ——AF15

N4 SDDATA7 — ——AF16

N11 VSS — ——AF17

N12 VSS — — — AF18 USBRBIAS — — —

N13 VSS — — — AF19 DREQ1 PDMA1 TIN1 IRQ1

N14 VSS — — — AF20 DREQ0 PDMA0 TIN0 —

N15 VSS — ——AF21TIN2PTIM5IRQ2CANRX1

— — — AF9 E0TXCLK PFEC0H7 — —

PBGA Pin

1

3

3

3

E1COL PFEC1H4 — —

USBCLKIN — — —

USBD+ — — —

USBD- — — —

Pin Functions

N16 VSS — ——AF22TIN0 — — —

N23 PCIAD16 — FBADDR16 — AF23 PSC3CTS PPSC3PSC27 PSC3BCLK —

N24 PCIAD14 — FBADDR14 — AF24

N25 PCIAD17 — FBADDR17 — AF25 PSC1CTS PPSC1PSC07 PSC1BCLK —

N26 PCIAD15 — FBADDR15 — AF26 TOUT0 — — —

1

This pin is a “no connect” on the MCF5483 and MCF5482 devices.

2

This pin is a “no connect” on the MCF5481 and MCF5480 devices. On MCF5485, MCF5484, MCF5483, and MCF5482 device the pin
should be connected to the appriopriate power rail even is USB is not being used.

3

This pin is a “no connect” on the MCF5481 and MCF5480 devices.

1

E1RXD0 PFEC1H1 — —

2.2 MCF548x External Signals

2.2.1 FlexBus Signals

2.2.1.1 Address/Data Bus (AD[31:0])

The AD[31:0] bus carries address and data. The full 32-bit address is always driven on the first clock of a
bus cycle (address phase). The number of bytes used for data during the data phase is determined by the
port size associated with the matching chip select.

MCF548x Reference Manual, Rev. 3

2-16 Freescale Semiconductor

MCF548x External Signals

2.2.1.2 Chip Select (FBCS[5:0])

FBCS[5:0] are asserted to indicate which device is being selected. A particular chip select asserts when
the transfer address is within the device’s address space as defined in the base and mask address registers.
Each chip select can be programmed for a base address location, masking addresses, port size,
burst-capability indication, wait-state generation, and internal/external termination.

Reset clears all chip select programming; FBCS0 is the only chip select initialized out of reset. FBCS0 is
also unique because it can function at reset as a global chip select that allows boot ROM to be selected at
any defined address space. Port size and termination (internal vs. external) for boot FBCS0 are configured
by the levels on AD[2:0] on the rising edge of RSTI, as described in Section 2.2.6, “Reset Configuration

Pins.”

2.2.1.3 Address Latch Enable (ALE)

The assertion of ALE indicates that the MCF548x has begun a bus transaction and that the address and
attributes are valid. ALE is asserted for one bus clock cycle. In multiplexed bus mode, ALE is used
externally as an address latch enable to capture the address phase of the bus transfer.

2.2.1.4 Read/Write (R/W)

The MCF548x drives the R/W signal to indicate the direction of the current bus operation. It is driven high
during read bus cycles and driven low during write bus cycles.

2.2.1.5 Transfer Burst (TBST)

Transfer burst indicates that a burst transfer is in progress. A burst transfer can be 2 to 16 beats depending
on the size of the transfer and the port size.

2.2.1.6 Transfer Size (TSIZ[1:0])

For memory accesses, these signals along with TBST, indicate the data transfer size of the current bus
operation. The FlexBus interface supports byte, word, and longword operand transfers and allows accesses
to 8-, 16-, and 32-bit data ports.

For misaligned transfers, TSIZ[1:0] indicates the size of each transfer. For example, if a longword access
through a 32-bit port device occurs at a misaligned offset of 0x1, a byte is transferred first (TSIZ[1:0] =

01), a word is next transferred at offset 0x2 (TSIZ[1:0] = 10), then the final byte is transferred at offset 0x4
(TSIZ[1:0] = 01).

For aligned transfers larger than the port size, TSIZ[1:0] behaves as follows:

• If bursting is used, TSIZ[1:0] is driven to the size of transfer.

• If bursting is inhibited, TSIZ[1:0] first shows the size of the entire transfer and then shows the port
size.

Table 2-3. Data Transfer Size

TSIZ[1:0] Transfer Size

00 4 bytes (longword)

01 1 byte

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor 2-17

Table 2-3. Data Transfer Size (Continued)

TSIZ[1:0] Transfer Size

10 2 bytes (word)

11 16 bytes (line)

For burst-inhibited transfers, TSIZ[1:0] changes with each ALE assertion to reflect the next transfer size.
For transfers to port sizes smaller than the transfer size, TSIZ[1:0] indicates the size of the entire transfer
on the first access and the size of the current port transfer on subsequent transfers. For example, for a
longword write to an 8-bit port, TSIZ[1:0] = 2’b00 for the first transaction and 2’b01 for the next three
transactions. If bursting is used and in the case of longword write to an 8-bit port, TSIZ[1:0] is driven to
2’b00 for the entire transfer.

2.2.1.7 Byte Selects (BE/BWE[3:0])

The four byte-enables are multiplexed with the byte-write-enable signals. Each pin can be individually
programmed through the chip select control registers (CSCRs). For each chip select, assertion of
byte-enables for reads and byte-write enables for write cycles can be programmed. Alternatively, users can
program byte-write enables to assert on writes and byte-enable to not assert on reads.

The byte strobe (BE/BWE[3:0]) outputs indicate that data is to be latched or driven onto a byte of the data.
BE/BWE[3:0] signals are asserted only to the memory bytes used during a read or write access.

2.2.1.8 Output Enable (OE)

The output enable signal is sent to the interfacing memory and/or peripheral to enable a read transfer. OE
is asserted only when a chip select matches the current address decode.

2.2.1.9 Transfer Acknowledge (TA)

The external system drives this input to terminate the bus transfer. For write cycles, the processor continues
to drive data at least one clock after FBCSx is negated. During read cycles, the peripheral must continue
to drive data until TA is recognized. The number of wait states is determined either by an internally
programmed auto acknowledgement or the external TA input. If the external TA is used, the peripheral has
total control over the number of wait states.

2.2.2 SDRAM Controller Signals

These signals are used for SDRAM accesses.

2.2.2.1 SDRAM Data Bus (SDDATA[31:0])

SDDATA[31:0] is the bidirectional, non-multiplexed data bus used for SDRAM accesses. Data is sampled
by the MCF548x on the rising edge of SDCLK when in SDR mode, and on both the rising and falling edge
of SDCLK when in DDR mode.

2.2.2.2 SDRAM Address Bus (SDADDR[12:0])

The SDADDR[12:0] signals are the 13-bit address bus used for multiplexed row and column addresses
during SDRAM bus cycles. The address multiplexing supports up to 256 Mbits of SDRAM per chip select.

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MCF548x External Signals

2.2.2.3 SDRAM Bank Addresses (SDBA[1:0])

Each SDRAM module has four internal row banks. The SDBA[1:0] signals are used to select the row bank.
It is also used to select the SDRAM internal mode register during power-up initialization.

2.2.2.4 SDRAM Row Address Strobe (RAS)

This output is the SDRAM synchronous row address strobe.

2.2.2.5 SDRAM Column Address Strobe (CAS)

This output is the SDRAM synchronous column address strobe.

2.2.2.6 SDRAM Chip Selects (SDCS[3:0])

These signals interface to the chip select lines of the SDRAMs within a memory block. Thus, there is one
SDCS line for each memory block (the MCF548x supports up to four SDRAM memory blocks).

2.2.2.7 SDRAM Write Data Byte Mask (SDDM[3:0])

These output signals are sampled by the SDRAM on both edges of SDDQS to determine which byte lanes
of the SDRAM data bus should be latched during a write cycle. In DDR mode, these bits are ignored during
read operations.

2.2.2.8 SDRAM Data Strobe (SDDQS[3:0])

These bidirectional signals indicate when valid data is on the SDRAM data bus when in DDR mode.

2.2.2.9 SDRAM Clock (SDCLK[1:0])

These signals are the output clock for SDRAM cycles.

2.2.2.10 Inverted SDRAM Clock (SDCLK[1:0])

These signals are the inverted version of the SDRAM clock. They are used with SDCLK to provide the
differential clocks for DDR SDRAM.

2.2.2.11 SDRAM Write Enable (SDWE)

The SDRAM write enable (SDWE) is asserted to signify that an SDRAM write cycle is underway. A read
cycle is indicated by the negation of SDWE.

2.2.2.12 SDRAM Clock Enable (SDCKE)

This output is the SDRAM clock enable. SDCKE is negated to put the SDRAM into low-power,
self-refresh mode.

2.2.2.13 SDR SDRAM Data Strobe (SDRDQS)

This signal is connected to SDDQS inputs. It is used in SDR mode only.

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Freescale Semiconductor 2-19

2.2.2.14 SDRAM Reference Voltage (VREF)

This is the input reference voltage for differential SSTL_2 inputs. It is used in both DDR and SDR modes.

2.2.3 PCI Controller Signals

2.2.3.1 PCI Address/Data Bus (PCIAD[31:0])

The PCIAD[31:0] lines are a time-multiplexed address data bus. The address is presented on the bus during
the address phase while the data is presented on the bus during one or more data phases.

If the FlexBus is used in 32-bit address or 32-bit data non-multiplexed mode, PCIAD[31:0] are used as a
32-bit address for FlexBus transfers.

2.2.3.2 Command/Byte Enables (PCICXBE[3:0])

The PCICXBE[3:0] lines are time-multiplexed. The PCI command is presented during the address phase,
and the byte enables are presented during the data phase.

2.2.3.3 Device Select (PCIDEVSEL)

The PCIDEVSEL signal is asserted active low when the MCF548x decodes that it is the target of a PCI
transaction from the address presented on the PCI bus during the address phase.

2.2.3.4 Frame (PCIFRM)

The PCIFRM signal is asserted by a PCI initiator to indicate the beginning of a transaction. It is negated
when the initiator is ready to complete the final data phase.

2.2.3.5 Initialization Device Select (PCIIDSEL)

The PCIIDSEL signal is asserted during a PCI type-0 configuration cycle to address the PCI configuration
header.

2.2.3.6 Initiator Ready (PCIIRDY)

The PCIIRDY signal is asserted to indicate that the PCI initiator is ready to transfer data. During a write
operation, assertion indicates that the master is driving valid data on the bus. During a read operation,
assertion indicates that the master is ready to accept data.

2.2.3.7 Parity (PCIPAR)

The PCIPAR signal indicates the parity of data on the PCIAD[31:0] and PCICXBE[3:0] lines.

2.2.3.8 Parity Error (PCIPERR)

The PCIPERR signal is asserted when a data phase parity error is detected if enabled.

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MCF548x External Signals

2.2.3.9 Reset (PCIRESET)

The PCIRESET signal is asserted active low by MCF548x to reset the PCI bus. This signal is asserted after
the MCF548x is reset and must be negated to enable usage of the PCI bus.

2.2.3.10 System Error (PCISERR)

The PCISERR signal, if enabled, is asserted when an address phase parity error is detected.

2.2.3.11 Stop (PCISTOP)

The PCISTOP signal is asserted by the currently addressed target to indicate that it wishes to stop the
current transaction.

2.2.3.12 Target Ready (PCITRDY)

The PCITRDY signal is asserted by the currently addressed target to indicate that it is ready to complete
the current data phase.

2.2.3.13 External Bus Grant (PCIBG[4:1])

The PCIBG signal is asserted to an external master to give it control of the PCI bus. If the internal PCI
arbiter is enabled, it asserts one of the PCIBG[4:1] lines to grant ownership of the PCI bus to an external
master. When the PCI arbiter module is disabled, PCIBG[4:1] is driven high and should be ignored.

2.2.3.14 External Bus Grant/Request Output (PCIBG0/PCIREQOUT)

The PCIBG0 signal is asserted to external master device 0 to give it control of the PCI bus. When the PCI
arbiter module is disabled, the signal operates as the PCIREQOUT output. It is asserted when the
MCF548x needs to initiate a PCI transaction.

2.2.3.15 External Bus Request (PCIBR[4:0])

The PCIBR signal is asserted by an external PCI master when it requires access to the PCI bus.

2.2.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN)

The PCIBR0 signal is asserted by external PCI master device 0 when it requires access to the PCI bus.
When the internal PCI arbiter module is disabled, this signal is used as a grant input for the PCI bus,
PCIGNTIN

. It is driven by an external PCI arbiter.

2.2.4 Interrupt Control Signals

The interrupt control signals supply the external interrupt level to the MCF548x device.

2.2.4.1 Interrupt Request (IRQ[7:1])

The IRQ[7:1] signals are the external interrupt inputs.

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2.2.5 Clock and Reset Signals

The clock and reset signals configure the MCF548x and provide interface signals to the external system.

2.2.5.1 Reset In (RSTI)

Asserting RSTI causes the MCF548x to enter reset exception processing. RSTO is asserted automatically
when RSTI is asserted.

2.2.5.2 Reset Out (RSTO)

After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is asserted. When the
PLL regains its lock, RSTO negates again. This signal can be used to reset external devices.

2.2.5.3 Clock In (CLKIN)

CLKIN is the MCF548x input clock frequency to the on-board, phase-locked loop (PLL) clock generator.
CLKIN is used to internally clock or sequence the MCF548x internal bus interface at a selected multiple
of the input frequency used for internal module logic.

CLKIN is used as the clock reference for PCI and FlexBus transfers.

2.2.6 Reset Configuration Pins

This section describes address/data pins, AD[12:0], that are read at reset to configure the MCF548x.

2.2.6.1 AD[12:8]—CLKIN to SDCLK Ratio (CLKCONFIG[4:0])

The clock configuration inputs, CLKCONFIG[4:0], indicate the CLKIN to SDCLK ratio. CLKIN is used
as the external reference for both PCI and FlexBus cycles. The CLKIN to SDCLK ratio is selectable, where
SDCLK is the clock frequency used for SDRAM accesses and the internal XLB bus. The core is always
clocked at twice the SDCLK frequency.

These signals are sampled on the rising edge of RSTI. Table 2 -4 shows how the logic levels of AD[12:8]
correspond to the selected clock ratio.

Table 2- 4 . MCF 5 48x Divide Ratio Encodings

FB_AD[12:8]

00011 1:2 41.6–50.0 83.33–100 166.66–200

00101 1:2 30.0–44.4 60.0–88.8 120.0–177.66

1

All other values of FB_AD[12:8] are reserved.

1

Clock Ratio

CLKIN—PCI and FlexBus

Frequency Range

(MHz)

Figure 2-2 correlates CLKIN, internal bus, and core clock frequenciesi for the 1x–4x multipliers.

Internal XLB, SDRAM

Bus, and PSTCLK
Frequency Range

(MHz)

Core Frequency Range

(MHz)

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MCF548x External Signals

CLKIN

2x

25.0 50.0

4x

25.0

25 40 50 60 70 70 80 90 100 110 120 130 140 150 160 170 180 190 20060

CLKIN (MHz) Core Clock (MHz)

Internal Clock

50.0

40 50 60 70 80 90 10030

Internal Clock (MHz)

100.0

100.0

2x

2x

100.0

Core Clock

200.0

200.0

Figure 2-2. CLKIN, Internal Bus, and Core Clock Ratios

2.2.6.2 AD5—FlexBus Size Configuration (FBSIZE)

At reset, the enabling and disabling of BE/BWE[3:0] versus TSIZ[1:0] and ADDR[1:0] is determined by
the logic level driven on AD5 at the rising edge of RSTI. FBSIZE is multiplexed with AD5 and sampled
only at reset. Table 2-5 shows how the AD5 logic level corresponds to the BE/BWE[3:0] function.

Table 2-5. AD5/FBSIZE Selection of BE/BWE[3:0] Signals

AD5 FlexBus Byte Enable Mode

0BE/BWE[3:0] used as byte/byte write

enables.

1BE/BWE[3:2] configured as TSIZ[1:0].

/BWE[1:0] configured as FBADDR[1:0].

BE

2.2.6.3 AD4—32-bit FlexBus Configuration (FBMODE)

During reset, the FlexBus can be configured to operate in a non-multiplexed 32-bit address with 32-bit data
mode. In this mode, the 32-bit FlexBus AD[31:0] is used for the data bus, and the PCI bus PCIAD[31:0]
is used as the address bus. The FlexBus operating mode is determined by the logic level driven on AD4 at
the rising edge of RSTI. Table 2-6 shows how the logic level of AD4 corresponds to the FlexBus mode.

Table 2-6. AD4/FBMODE Selection of Non-Multiplexed

32-bit Address/32-bit Data Mode

AD4 FlexBus Operating Mode

0 AD[31:0] used for data.

PCIAD[31:0] used for address

1 PCIAD[31:0] used for PCI bus.

AD[31:0] used for both address and data.

1

If the non-multiplexed 32-bit address/32-bit data mode is selected, the PCI bus
cannot be used.

1

2.2.6.4 AD3—Byte Enable Configuration (BECONFIG)

The default byte enable mode of the boot FBCS0 is determined by the logic level driven on AD3 at the
rising edge of RSTI. This logic level is reflected as the reset value of CSCR0[BEM]. Table 2-7 shows how
the logic level of AD3 corresponds to the byte enable mode for FBCS0 at reset.

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Table 2-7. AD3/BECONFIG, BE/BWE[3:0] Boot Configuration

AD3 Boot FBCS0 Byte Strobe Configuration

0BE

1BWE[3:0] are not asserted for reads;

[3:0] can assert for both read and write cycles.

BWE[3:0] only assert for write cycles

2.2.6.5 AD2—Auto Acknowledge Configuration (AACONFIG)

At reset, the enabling and disabling of auto acknowledge for boot FBCS0 is determined by the logic level
driven on AD2 at the rising edge of RSTI. AACONFIG is multiplexed with AD2 and sampled only at reset.
The AD2 logic level is reflected as the reset value of CSCR0[AA]. Tab le 2-8 shows how the AD2 logic
level corresponds to the auto acknowledge timing for FBCS0 at reset. Auto acknowledge can be disabled
by driving a logic 0 on AD2 at reset.

Table 2-8. AD2/AA_CONFIG Selection of FBCS0 Automatic Acknowledge

AD2 Boot FBCS0 AA Configuration at Reset

0Disabled

1 Enabled with 63 wait states

2.2.6.6 AD[1:0]—Port Size Configuration (PSCONFIG)

The default port size value of the boot FBCS0 is determined by the logic levels driven on AD[1:0] at the
rising edge of RSTI, which are reflected as the reset value of CSCR0[PS]. Table 2-9 shows how the logic
levels of AD[1:0] correspond to the FBCS0 port size at reset.

Table 2-9. AD[1:0]/PSCONFIG[1:0] Selection of FBCS0 Port Size

AD[1:0] Boot FBCS0 Port Size

00 32-bit port

01 8-bit port

1X 16-bit port

2.2.7 Ethernet Module Signals

The following signals are used by the Ethernet module for data and clock signals.

2.2.7.1 Management Data (E0MDIO, E1MDIO)

The bidirectional EMDIO signals transfer control information between the external PHY and the
media-access controller. Data is synchronous to EMDC and applies to MII mode operation. This signal is
an input after reset. When the FEC operates in 10 Mbps 7-wire interface mode, this signal should be
connected to VSS.

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MCF548x External Signals

2.2.7.2 Management Data Clock (E0MDC, E1MDC)

EMDC is an output clock that provides a timing reference to the PHY for data transfers on the EMDIO
signal; it applies to MII mode operation.

2.2.7.3 Transmit Clock (E0TXCLK, E1TXCLK)

This is an input clock that provides a timing reference for ETXEN, ETXD[3:0], and ETXER.

2.2.7.4 Transmit Enable (E0TXEN, E1TXEN)

The transmit enable (ETXEN) output indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the first ETXCLK following the final
nibble of the frame.

2.2.7.5 Transmit Data 0 (E0TXD0, E1TXD0)

ETXD0 is the serial output Ethernet data and is only valid during the assertion of ETXEN. This signal is
used for 10 Mbps Ethernet data. This signal is also used for MII mode data in conjunction with ETXD[3:1].

2.2.7.6 Collision (E0COL, E1COL)

The ECOL input is asserted upon detection of a collision and remains asserted while the collision persists.
This signal is not defined for full-duplex mode.

2.2.7.7 Receive Clock (E0RXCLK, E1RXCLK)

The receive clock (ERXCLK) input provides a timing reference for ERXDV, ERXD[3:0], and ERXER.

2.2.7.8 Receive Data Valid (E0RXDV, E1RXDV)

Asserting the receive data valid (ERXDV) input indicates that the PHY has valid nibbles present on the
MII. ERXDV should remain asserted from the first recovered nibble of the frame through to the last nibble.
Assertion of ERXDV must start no later than the SFD and exclude any EOF.

2.2.7.9 Receive Data 0 (E0RXD0, E1RXD0)

ERXD0 is the Ethernet input data transferred from the PHY to the media-access controller when ERXDV
is asserted. This signal is used for 10 Mbps Ethernet data. This signal is also used for MII mode Ethernet
data in conjunction with ERXD[3:1].

2.2.7.10 Carrier Receive Sense (E0CRS, E1CRS)

ECRS is an input signal that, when asserted, signals that transmit or receive medium is not idle, and applies
to MII mode operation.

2.2.7.11 Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1])

These pins contain the serial output Ethernet data and are valid only during assertion of ETXEN in MII
mode.

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Freescale Semiconductor 2-25

2.2.7.12 Transmit Error (E0TXER, E1TXER)

When the ETXER output is asserted for one or more clock cycles while ETXEN is also asserted, the PHY
sends one or more illegal symbols. ETXER has no effect at 10 Mbps or when ETXEN is negated, and
applies to MII mode operation.

2.2.7.13 Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1])

These pins contain the Ethernet input data transferred from the PHY to the media-access controller when
ERXDV is asserted in MII mode operation.

2.2.7.14 Receive Error (E0RXER, E1RXER)

ERXER is an input signal that, when asserted along with ERXDV, signals that the PHY has detected an
error in the current frame. When ERXDV is not asserted, ERXER has no effect and applies to MII mode
operation.

2.2.8 Universal Serial Bus (USB)

2.2.8.1 USB Differential Data (USBD+, USBD–)

USBD+ and USBD– are the outputs of the on-chip USB 2.0 transceiver. They provide differential data for
the USB 2.0 bus.

2.2.8.2 USBVBUS

This is the USB cable Vbus monitor input.

2.2.8.3 USBRBIAS

This is the connection for external current setting resistor. It should be connected to a 9.1kΩ +/– 1%
pull-down resistor.

For the MCF5481 and MCF5480 devices this pin should be connected to a 9.1kΩ +/– 20% pull-down
resistor.

2.2.8.4 USBCLKIN

This is the input pin for 12-MHz USB crystal circuit.

2.2.8.5 USBCLKOUT

This is the output pin for 12-MHz USB crystal circuit.

2.2.9 DMA Serial Peripheral Interface (DSPI) Signals

2.2.9.1 DSPI Synchronous Serial Data Output (DSPISOUT)

The DSPISOUT output provides the serial data from the DSPI and can be programmed to be driven on the
rising or falling edge of DSPISCK.

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MCF548x External Signals

2.2.9.2 DSPI Synchronous Serial Data Input (DSPISIN)

The DSPISIN input provides the serial data to the DSPI and can be programmed to be sampled on the
rising or falling edge of DSPISCK.

2.2.9.3 DSPI Serial Clock (DSPISCK)

DSPISCK is a serial communication clock signal. In master mode, the DSPI generates the DSPISCK. In
slave mode, DSPISCK is an input from an external bus master.

2.2.9.4 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS)

In master mode, the DSPICS0 signal is a peripheral chip select output that selects which slave device the
current transmission is intended for.

In slave mode, the SS signal is a slave select input signal that allows an SPI master to select the DSPI as
the target for transmission.

2.2.9.5 DSPI Chip Selects (DSPICS[2:3])

The synchronous peripheral chip selects (DSPICS[2:3]) outputs provide DSPI peripheral chip selects that
can be programmed to be active high or low.

2.2.9.6 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS)

DSPICS5 is a peripheral chip select output signal. When the DSPI is in master mode and the
DMCR[PCSSE] bit is cleared, this signal is used to select which slave device the current transfer is
intended for.

PCSS provides a strobe signal that can be used with an external demultiplexer for deglitching of the
DSPICSn signals. When the DSPI is in master mode and DMCR[PCSSE] is set, the PCSS provides the
appropriate timing for the decoding of the DSPICS[0,2,3] signals which prevents glitches from occurring.

This signal is not used in slave mode.

2.2.10 FlexCAN Signals

2.2.10.1 FlexCAN Transmit (CANTX0, CANTX1)

Controller area network transmit data output.

2.2.10.2 FlexCAN Receive (CANRX0, CANRX1)

Controller area network receive data input.

2.2.11 I2C I/O Signals

The I2C serial interface module uses the signals in this section.

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2.2.11.1 Serial Clock (SCL)

This bidirectional open-drain signal is the clock signal for the I2C interface. It is either driven by the I2C
module when the bus is in master mode, or it becomes the clock input when the I2C is in slave mode.

2.2.11.2 Serial Data (SDA)

This bidirectional open-drain signal is the data input/output for the I2C interface.

2.2.12 PSC Module Signals

The PSC modules use the signals in this section. The baud rate clock inputs are not supported.

2.2.12.1 Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD)

PSCnTXD are the transmitter serial data outputs for the PSC modules. The output is held high (mark
condition) when the transmitter is disabled, idle, or in the local loopback mode. The PSCxTXD pins can
be programmed to be driven low (break status) by a command.

2.2.12.2 Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD)

PSCnRXD are the receiver serial data inputs for the PSC modules. When the PSC clock is stopped for
power-down mode, any transition on the pins restarts them.

2.2.12.3 Clear-to-Send (PSCnCTS/PSCBCLK)

These signals either operate as the clear-to-send input signals in UART mode or the bit clock input signals
in modem modes and IrDA modes. In MIR and FIR mode, the frequency is a multiple of the input bit clock
frequency, and the bit clock frequency should be within +/-0.1% and +/-0.01% of the ideal one,
respectively.

2.2.12.4 Request-to-Send (PSCnRTS/PSCFSYNC)

The PSCnRTS signals act as transmitter request-to-send (RTS) outputs in UART mode, the frame sync
input in modem8 and modem16 modes, or the RTS
mode.

output (which acts as frame sync) in AC97 modem

2.2.13 DMA Controller Module Signals

The DMA controller module uses the signals in the following subsections to provide external requests for
either a source or destination.

2.2.13.1 DMA Request (DREQ[1:0])

These inputs are asserted by a peripheral device to request an operand transfer between that peripheral and
memory by either channel 0 or 1 of the on-chip DMA module.

2.2.13.2 DMA Acknowledge (DACK[1:0])

These outputs are asserted to acknowledge that a DMA request has been recognized.

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MCF548x External Signals

2.2.14 Timer Module Signals

The signals in the following sections are external interfaces to the four general-purpose MCF548x timers.
These 32-bit timers can capture timer values, trigger external events or internal interrupts, or count
external events.

2.2.14.1 Timer Inputs (TIN[3:0])

TINn can be programmed as clocks that cause events in the counter and prescalers. They can also cause
captures on the rising edge, falling edge, or both edges.

2.2.14.2 Timer Outputs (TOUT[3:0])

The programmable timer outputs, TOUTn, pulse or toggle on various timer events.

2.2.15 Debug Support Signals

The MCF548x complies with the IEEE 1149.1a JTAG testing standard. JTAG test pins are multiplexed
with background debug pins. Except for TCK, these signals are selected by the value of MTMOD0. If
MTMOD0 is high, JTAG signals are chosen; if it is low, debug module signals are chosen. MTMOD0
should be changed only while RSTI is asserted.

2.2.15.1 Processor Clock Output (PSTCLK)

The internal PLL generates this output signal, and is the processor clock output that is used as the timing
reference for the debug bus timing (PSTDDATA[7:0]). PSTCLK is at the same frequency as the internal
XLB and SDRAM bus frequency. The frequency is one-half the core frequency.

2.2.15.2 Processor Status Debug Data (PSTDDATA[7:0])

Processor status data outputs indicate both processor status and captured address/data values. They operate
at half the processor’s frequency, using PSTCLK. Given that real-time trace information appears as a
sequence of 4-bit data values, there are no alignment restrictions; that is, PST values and operands may
appear on either PSTDDATA[7:0] nibble. The upper nibble, PSTDDATA[7:4], is most significant.

2.2.15.3 Development Serial Clock/Test Reset (DSCLK/TRST)

If MTMOD0 is low, DSCLK is selected. DSCLK is the development serial clock for the serial interface to
the debug module. The maximum DSCLK frequency is 1/5 CLKIN.

If MTMOD0 is high, TRST is selected. TRST asynchronously resets the internal JTAG controller to the
test logic reset state, causing the JTAG instruction register to choose the bypass instruction. When this
occurs, JTAG logic is benign and does not interfere with normal MCF548x functionality.

Although TRST is asynchronous, Freescale recommends that it makes an asserted-to-negated transition
only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to
a logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to EVDD. Tying TRST
to ground places the JTAG controller in test logic reset state immediately. Tying it to EVDD causes the
JTAG controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks.

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2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS)

If MTMOD0 is low, BKPT is selected. BKPT signals a hardware breakpoint to the processor in debug
mode.

If MTMOD0 is high, TMS is selected. The TMS input provides information to determine the JTAG test
operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising
edge of TCK determine whether the JTAG controller holds its current state or advances to the next state.
This directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up
resistor so that if it is not driven low, it defaults to a logic level of 1. But if TMS is not used, it should be
tied to VDD.

2.2.15.5 Development Serial Input/Test Data Input (DSI/TDI)

If MTMOD0 is low, DSI is selected. DSI provides the single-bit communication for debug module
commands.

If MTMOD0 is high, TDI is selected. TDI provides the serial data port for loading the various JTAG
boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG
controller state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge.
TDI has an internal pull-up resistor, so when not driven low it defaults to high. But if TDI is not used, it
should be tied to EVDD.

2.2.15.6 Development Serial Output/Test Data Output (DSO/TDO)

If MTMOD0 is low, DSO is selected. DSO provides single-bit communication for debug module
responses.

If MTMOD0 is high, TDO is selected. The TDO output provides the serial data port for outputting data
from JTAG logic. Shifting out data depends on the JTAG controller state machine and the instruction in
the instruction register. Data shifting occurs on the falling edge of TCK. When TDO is not outputting test
data, it is three-stated. TDO can be three-stated to allow bused or parallel connections to other devices
having a JTAG port.

2.2.15.7 Test Clock (TCK)

TCK is the dedicated JTAG test logic clock independent of the MCF548x processor clock. Various JTAG
operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period
does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground.

2.2.16 Test Signals

2.2.16.1 Test Mode (MTMOD[3:0])

The test mode signals choose between multiplexed debug module and JTAG signals. If MTMOD0 is low,
the part is in normal and background debug mode (BDM); if it is high, it is in normal and JTAG mode. All
other MTMOD values are reserved; MTMOD[3:1] should be tied to ground and MTMOD[3:0] should not
be changed while RSTI is negated

MCF548x Reference Manual, Rev. 3

2-30 Freescale Semiconductor