How it Works
Freescale Semiconductor
Loading...
MCF5441X
User Manual
31 pgs1.34 Mb0

Freescale Semiconductor MCF5441X User Manual

MCF5441X Tower Module
User Manual
Rev. 1.1
Freescale Semiconductor Inc.
Microcontroller Solutions Group
Contents
1 PURPOSE ......................................................................................................................................................................... 3
2 REFERENCE DOCUMENTS ........................................................................................................................................ 3
3 OVERVIEW ..................................................................................................................................................................... 3
3.1 MCF5441X OVERVIEW ...................................................................................................................................................... 3
3.2 TWR-MCF5441X OVERVIEW ................................................................ ................................................................ ........... 5
4 HARDWARE SPECIFICATION ................................................................................................................................... 6
4.1 MICROCONTROLLER ........................................................................................................................................................... 6
4.2 CLOCKING .......................................................................................................................................................................... 7
4.3 SYSTEM POWER ................................................................................................................................................................. 8
4.4 DEBUG INTERFACE ............................................................................................................................................................. 8
4.4.1 Stardard BDM ........................................................................................................................................................... 8
4.4.2 OSBDM Bootloader Mode ...................................................................................................................................... 10
4.4.3 OSBDM Debug Interface ........................................................................................................................................ 10
4.5 RS232 HEADERS .............................................................................................................................................................. 10
4.6 SDRAM INTERFACE ........................................................................................................................................................ 11
4.7 NAND FLASH MEMORY INTERFACES .............................................................................................................................. 11
4.8 ACCELEROMETER ............................................................................................................................................................ 11
4.9 POTENTIOMETER .............................................................................................................................................................. 12
4.10 TEMPERATURE SENSOR ................................................................................................................................................. 13
4.11 AUDIO HEADERS (DAC) ................................................................................................................................................ 13
4.12 USER INTERFACES .......................................................................................................................................................... 13
4.13 RESET CONFIGURATION ................................................................................................................................................. 14
4.13.1 Default Configuration (J5: 3-4 and 1-2 = ON:ON) .............................................................................................. 15
4.13.2 Parallel Configuration (J5: 3-4 and 1-2 = ON:OFF)........................................................................................... 16
4.13.3 Serial Configuration (J5 OFF:OFF) .................................................................................................................... 17
4.14 JUMPERS, SWITCHES ...................................................................................................................................................... 20
4.15 CUT/TRACE PADS .......................................................................................................................................................... 21
1 Purpose
This document provides design and usage information for the Freescale TWR_M54418 evaluation, development and reference platform.
The TWR-MCF5441X platform provides and evaluation system for the Freescale MCF5441x ColdFire V4m embedded microprocessor family. The MCF54418 is the superset device in the family and is the processor featured on this platform. This allows evaluation and development for the entire MCF5441x family on an existing Tower system.
2 Reference Documents
MCF54418 Reference Manual TWR-M54418 Quick Start Guide TWR-M54418 Schematics MCF54418 Data Sheet MMA7361L Data Sheet – Three Axis Accelerometer DDR2 SDRAM Specification (JESD79-2C) Tower Overview Presentation Tower Mechanical Specification DS18B20 Data Sheet – Temperature Sensor DS18B20 Application Note 120: Using an API to Control the DS1WM 1-Wire Bus Master TS2007 Data Sheet – Class D audio power amplifier with 6-12dB gains. MC9S08JM60 Reference Manual Cut/Trace Pads
3 Overview
3.1 MCF5441x Overview
The following is a brief summary of the functional blocks in the MCF5441x superset device.
Version 4 ColdFire Core with MMU and EMAC
o CPU @250 MHz
16 KBytes instruction cache and 16 KBytes data cache
64 Kbytes internal SRAM Support for booting from SPI-compatible flash Support for booting from NAND flash Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple
bus masters
64 channel DMA controller DDR1/DDR2 Controller USB 2.0 On-the-Go controller with ULPI support Two smart card ports Two 10/100 Ethernet Controllers IEEE 1588-2002 SDHC host controller Two CAN modules Cryptographic acceleration unit (CAU) Random number generator Synchronous serial interface (SSI) Four 32-bit timers with DMA support Four DMA-supported serial peripheral interface (DSPI) Ten UARTs Six I2C bus interface 12-bit ADC A multi-channel PWM Two DACs
3.2 TWR-MCF5441X Overview
The TWR-MCF5441X provides hardware to evaluate as many of the configurations of the MCF5441x family as possible. The TWR-MCF5441X features:
Tower compatible processor board MCF54418 in a 256 MAPBGA package DDR2 SDRAM (128 MByte) A NAND Flash memory device (256MByte) Two RS232 headers (2x5 pins) Standard 26-pin BDM Header
MC9S08JM60 based Open Source BDM (OSBDM) circuit Standard 6-pin BKGD/MS Header MMA7361L three-axis accelerometer Wire Digital Temperature Sensor Four LEDs DIP Switches and push buttons for user input Potentiometer Audio Speaker (Header Only) uses LM4889 audio power amplifier.
4 Hardware Specification
This section provides specification details for the TWR-MCF5441X board.
4.1 Microcontroller
The microcontroller on the TWR-MCF5441X will be a member of the highly-integrated 32-bit microprocessor family based on the Coldfire V4m with MMU, EMAC, and CAU units.
MCF54418 ColdFire® V4m Microprocessor
256 MAPBGA
1.2V 1.8V 3.3V
DDR2
(128 MB)
Open-Source
BDM Interface
26-Pin Header
PCIe Expansion Connectors
Timers, IRQs, FlexBus, UARTs, I2C,
SPI, USB, Ethernet, SSI, SDHC,
CAN, ADC, DAC, mcPWM, etc.
USB
Mini-AB
SDRAM Interface
Freescale Silicon External Connectors Memory Devices Interface ICs Power Rails
Reset, GPIO
Power Switch and
Regulation
NAND Flash
(2Gbit)
ADC
UART
5.0V 3.3V
5.0V
UART
BDM
32.768 kHz (RTC)
25 MHz
(RefClk)
UART
DAC
Speaker
Header
ADC
MMA7361L 3-axis
Accelerometer
Temp Sensor
(DS18B20)
1-Wire
LED
LED
LED
LED
Dual
RS-232
2x5 Pin
2x5 Pin
NFC
High Speed
Analog
Switches
FEC RMII USB ULPI
UARTs, Flexbus, I2C, CAN, etc...
Clock Selection
Pin
External clock source
1-2
Onboard 25Mhz clock
2-3
4.2 Clocking
The MCF54418 requires 2 clocks sources in order to enable proper internal timing. A 25 MHz crystal is
connected to EXTAL to generate several clocks including the CPU clock and peripherals’ clock. The
EXTAL can also use a 50MHz clock from the Tower Elevator (selected via jumper J2). A 32.768 kHz crystal is connected to RTC_XTAL and RTC_EXTAL for Real-Time Clock usage.
The MCF54418’s core clock speed is default to 250 MHz on the TWR-MCF54418 platform. The DDR2 SDRAM bus speed is set at 250 MHz to generate a 500 MHz data rate. The system bus clock is set at 125MHz. All clock speeds such as CPU, SYSTEM, SDHC, USB and NAND can be programmable to desire frequency with software modification and jumpers.
Table 1 - J2 Headers
Clock Source
PLL Multiplier
SW1 Dip [7:8]
settings
50MHz
10x
0:0 (On:On)
25MHz
20x
1:1 (Off:Off)
To fully support the DDR2 interface a VCO of 500 MHz is required. In order to supply a VCO of 500MHz, the clock multiplier should be adjusted based on the input reference clock.
Note: VCO must be in the range from 240-500 MHz. USB frequency must be 60MHz, SDHC frequency must not be greater than 250MHz, and NAND frequency must not be greater than 80MHz.
4.3 System Power
The TWR-MCF5411X board is powered by +5V either from the OSBDM circuit (via the miniAB USB connector) or the Tower Elevator power connections. Power regulation circuitry is capable of providing 1.2V, 1.8V, and if needed 3.3V from either of the power source.
4.4 Debug Interface
TWR-MCF5441X provides two debug interfaces – a standard BDM and an Open Source BDM (OSBDM).
4.4.1 Stardard BDM
The primary debug port on the TWR-MCF5441X is referred to as the background debug module or BDM. The standard 26-pin BDM header (J11) is provided on the TWR-M5441X for attachment of an external BDM control interface.
J11
Function
J11
Function
1
RSTOUT_b
2
TMS/BKPT_b
3
GND
4
DSCLK
5
GND
6
TCK
7
RSTIN_b
8
TDI/DSI
9
3V3
10
TDO/DSO
11
GND
12
PST3
13
PST2
14
PST1
15
PST0
16
DDATA3
17
DDATA2
18
DDATA1
19
DDATA0
20
GND
21
NC
22
NC
23
GND
24
PSTCLK/OSBDM
25
3V3
26
NC
Debug Mode
Pin
JTAG
No shunt
BDM
Shunt on 1-2
TCLK_PSTCLK Routing
Pin
TCK/PSTCLK on J11[pin 24]
1-2
TCK/PSTCLK on J11[pin 6]
2-3
Table 2 - BDM Headers
The MCF5441x also features IEEE 1149.1 Test Access Port (JTAG) test logic that can be used for boundary-scan testability. The access pins for JTAG are multiplexed over the BDM control signals and are available on J11.
The JTAG_EN input signal to the MCF5441x determines the debug mode: BDM or JTAG. This signal is controllable by J6 as shown below:
Table 3 - J6 Headers
The TCLK and PSTCLK signals are the only two multiplexed signals that switch input/output state, depending on which debug mode is selected. In BDM mode, the PSTCLK is an output from the MCF5441x to the external BDM control interface. In JTAG mode, TCLK is the test clock input. The standard 26-pin BDM header defines pin 24 as PSTCLK. A common practice is to place TCLK on pin 6 of this header. J8 is available to control the routing of the multiplexed TCLK_PSTCLK signal to the 26-pin debug header (J11) as shown below.
Table 4 - J8 Headers
Pin Function
Pin Function
1
BKDG/MS
2
5V 3 NC 4 RESET_b
5
NC 6 5V
4.4.2 OSBDM Bootloader Mode
The MC9S08JM60 device used in the OSBMD circuit is preprogrammed with OSBDM debugger firmware and a USB Bootloader. Jumper J10 determines which application will run following a power­on reset. If Bootloader Mode is chosen (Jumper ON J10), the bootloader will executed, allowing in­circuit reprogramming of the JM60 flash memory via USB. This enables the OSBDM firmware to be upgraded by the user when upgrades become available. For details on the USB Bootloader, refer to Application Note AN3561 on the Freescale website (http://www.freescale.com).
The USB Bootloader communicates with a GUI application running on a host PC. The GUI application can be found on the Freescale website; search keyword “JM60 GUI”. Refer to section 2.5 and 3.3 of AN3561 for details on installing and running the application.
Note:
The JM60 GUI Installer should be run before connecting the OSBDM in Bootloader Mode to a host USB port. Otherwise, the JM60 USB device will not be recognized and the proper drivers will not be loaded.
4.4.3 OSBDM Debug Interface
The OSBDM circuit is designed so that it can program the on-board MCF54418 device. The steps necessary to operate the OSBDM in this mode are listed here:
1. Ensure that J10 is not shunted (J10 holds JM60 in reset)
2. Connect J7 (2x3 header) from TWR-MCF54418 to target debug connector
Table 5 - J7 JM60 BKGD Headers
4.5 RS232 Headers
The MCF54418 includes ten UART modules. The TWR-M5441X provides two RS232 transceivers on UART0 and UART4. Two 2x5 pin headers are provided allowing access to the RS232 interfaces - J1 (UART0) and J3 (UART4). A 2x5 adaptor to Female DB9 serial cable must be used in order to establish serial communication.
Loading...
+ 21 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use