Page 1
MCF5329 Reference Manual
Devices Supported:
MCF5327
MCF5328
MCF53281
MCF5329
Document Number: MCF5329RM
Rev. 3
12/2008
Page 2
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MCF5329RM
Rev. 3
12/2008
Page 3
Overview
123
456
7891011
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13
1415161718192021222324
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26
272829
3031323334
35
36
37
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
Crossbar Switch (XBS)
General Purpose I/O Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Enhanced Direct Memory Access (eDMA)
FlexBus
SDRAM Controller (SDRAMC)
Fast Ethernet Controller (FEC)
Universal Serial Bus Interface – Host Module
Universal Serial Bus Interface – On-The-Go Module
Liquid Crystal Display Controller (LCDC)
FlexCAN
Synchronous Serial Interface (SSI)
Real-Time Clock
Pulse-Width Modulation (PWM) Module
Watchdog Timer Module
Programmable Interrupt Timers (PIT0–PIT3)
DMA Timers (DTIM0–DTIM3)
Queued Serial Peripheral Interface (QSPI)
UART Modules
I2C Interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Symmetric Key Hardware Accelerator (SKHA)
Debug Module
IEEE 1149.1 Test Access Port (JTAG)
Register Memory Map Quick Reference
Revision History
A
B
Page 4
Overview
123
456
7891011
12
13
1415161718192021222324
25
26
272829
3031323334
35
36
37
B
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
Crossbar Switch (XBS)
General Purpose I/O Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Enhanced Direct Memory Access (eDMA)
FlexBus
SDRAM Controller (SDRAMC)
Fast Ethernet Controller (FEC)
Universal Serial Bus Interface – Host Module
Universal Serial Bus Interface – On-The-Go Module
Liquid Crystal Display Controller (LCDC)
FlexCAN
Synchronous Serial Interface (SSI)
Real-Time Clock
Pulse-Width Modulation (PWM) Module
Watchdog Timer Module
Programmable Interrupt Timers (PIT0–PIT3)
DMA Timers (DTIM0–DTIM3)
Queued Serial Peripheral Interface (QSPI)
UART Modules
I2C Interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
A
Symmetric Key Hardware Accelerator (SKHA)
Debug Module
IEEE 1149.1 Test Access Port (JTAG)
Register Memory Map Quick Reference
Revision History
Page 5
Contents
MCF5329 Reference Manual, Rev 3
Paragraph
Number
Title
Page
Number
About This Book
Audience ....................................................................................................................... xxix
Organization .................................................................................................................. xxix
Suggested Reading ....................................................................................................... xxxii
Hardware Specification ....................................................................................... xxxii
General Information ............................................................................................ xxxiii
ColdFire Documentation .................................................................................... xxxiii
Conventions ................................................................................................................ xxxiii
Register Figure Conventions .............................................................................. xxxiv
Acronyms and Abbreviations .......................................................................................xxxv
Terminology Conventions ........................................................................................... xxxvi
Chapter 1
Overview
1.1 MCF532x Device Configurations.................................................................................................. 1-1
1.2 Block Diagram ............................................................................................................................... 1-2
1.3 Features .......................................................................................................................................... 1-3
1.3.1 V3 Core Overview...........................................................................................................1-8
1.3.2 Debug Module ................................................................................................................. 1-9
1.3.3 JTAG................................................................................................................................ 1-9
1.3.4 On-chip Memories...........................................................................................................1-9
1.3.5 LCD Controller.............................................................................................................. 1-10
1.3.6 Voice-over-IP (VoIP) System Solution......................................................................... 1-10
1.3.7 SDR/DDR SDRAM Controller ..................................................................................... 1-11
1.3.8 USB Host and OTG Controllers.................................................................................... 1-11
1.3.9 Synchronous Serial Interface (SSI)................................................................................ 1-12
1.3.10 Fast Ethernet Controller (FEC)...................................................................................... 1-12
1.3.11 Cryptography Accelerators............................................................................................ 1-12
1.3.12 FlexCAN........................................................................................................................ 1-13
1.3.13 UARTs........................................................................................................................... 1-13
1.3.14 I
1.3.15 QSPI............................................................................................................................... 1-13
1.3.16 Pulse Width Modulation (PWM) Timer........................................................................ 1-13
1.3.17 Real Time Clock............................................................................................................ 1-13
1.3.18 DMA Timers (DTIM0-DTIM3).................................................................................... 1-13
1.3.19 Software Watchdog Timer............................................................................................. 1-14
2
C Bus...........................................................................................................................1-13
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Title
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Number
1.3.20 Periodic Interrupt Timers (PIT0–PIT3)......................................................................... 1-14
1.3.21 Clock Module and Phase Locked Loop (PLL).............................................................. 1-14
1.3.22 Interrupt Controllers ...................................................................................................... 1-14
1.3.23 DMA Controller............................................................................................................. 1-14
1.3.24 FlexBus External Interface............................................................................................ 1-15
1.3.25 Reset Controller Module................................................................................................ 1-15
1.3.26 GPIO.............................................................................................................................. 1-15
1.4 Documentation............................................................................................................................. 1-16
Chapter 2
Signal Descriptions
2.1 Introduction.................................................................................................................................... 2-1
2.2 Signal Properties Summary............................................................................................................ 2-1
2.2.1 Internal Pull-up/Pull-downs Resistors ............................................................................. 2-8
2.3 Signal Primary Functions...............................................................................................................2-9
2.3.1 Reset Signals.................................................................................................................... 2-9
2.3.2 PLL and Clock Signals .................................................................................................... 2-9
2.3.3 Mode Selection .............................................................................................................. 2-10
2.3.4 FlexBus Signals ............................................................................................................. 2-11
2.3.5 SDRAM Controller Signals........................................................................................... 2-12
2.3.6 External Interrupt Signals.............................................................................................. 2-12
2.3.7 DMA Signals ................................................................................................................. 2-12
2.3.8 LCD Controller Signals ................................................................................................. 2-13
2.3.9 Ethernet Module (FEC) Signals..................................................................................... 2-13
2.3.10 I2C I/O Signals.............................................................................................................. 2-14
2.3.11 FlexCAN Signals...........................................................................................................2-15
2.3.12 Queued Serial Peripheral Interface (QSPI).................................................................... 2-15
2.3.13 Synchronous Serial Interface (SSI) Signals................................................................... 2-15
2.3.14 Universal Serial Bus (USB) Signals.............................................................................. 2-16
2.3.15 Pulse Width Modulation (PWM) Module Signals......................................................... 2-16
2.3.16 UART Module Signals.................................................................................................. 2-17
2.3.17 DMA Timer Signals.......................................................................................................2-17
2.3.18 Debug Support Signals.................................................................................................. 2-17
2.3.19 Test Signals.................................................................................................................... 2-19
2.3.20 Power and Ground Pins................................................................................................. 2-19
2.4 External Boot Mode..................................................................................................................... 2-20
vi Freescale Semiconductor
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MCF5329 Reference Manual, Rev 3
Paragraph
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Title
Page
Number
Chapter 3
ColdFire Core
3.1 Introduction.................................................................................................................................... 3-1
3.1.1 Overview.......................................................................................................................... 3-1
3.2 Memory Map/Register Description................................................................................................ 3-4
3.2.1 Data Registers (D0–D7)................................................................................................... 3-6
3.2.2 Address Registers (A0–A6)............................................................................................. 3-6
3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)................................................... 3-6
3.2.4 Condition Code Register (CCR)...................................................................................... 3-7
3.2.5 Program Counter (PC) ..................................................................................................... 3-8
3.2.6 Cache Control Register (CACR) ..................................................................................... 3-8
3.2.7 Access Control Registers (ACRn)................................................................................... 3-9
3.2.8 Vector Base Register (VBR)............................................................................................ 3-9
3.2.9 Status Register (SR)......................................................................................................... 3-9
3.2.10 Memory Base Address Register (RAMBAR) ............................................................... 3-10
3.3 Functional Description................................................................................................................. 3-10
3.3.1 Version 3 ColdFire Microarchitecture........................................................................... 3-10
3.3.2 Instruction Set Architecture (ISA_A+).......................................................................... 3-11
3.3.3 Exception Processing Overview.................................................................................... 3-12
3.3.4 Processor Exceptions..................................................................................................... 3-15
3.3.5 Instruction Execution Timing........................................................................................ 3-23
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
4.1 Introduction.................................................................................................................................... 4-1
4.1.1 Overview.......................................................................................................................... 4-1
4.2 Memory Map/Register Definition.................................................................................................. 4-3
4.2.1 MAC Status Register (MACSR)...................................................................................... 4-3
4.2.2 Mask Register (MASK)................................................................................................... 4-5
4.2.3 Accumulator Registers (ACC0–3)................................................................................... 4-6
4.2.4 Accumulator Extension Registers (ACCext01, ACCext23)............................................ 4-7
4.3 Functional Description................................................................................................................... 4-8
4.3.1 Fractional Operation Mode............................................................................................ 4-10
4.3.2 EMAC Instruction Set Summary................................................................................... 4-12
4.3.3 EMAC Instruction Execution Times ............................................................................. 4-13
4.3.4 Data Representation....................................................................................................... 4-14
4.3.5 MAC Opcodes ............................................................................................................... 4-14
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Title
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Number
Chapter 5
Cache
5.1 Introduction.................................................................................................................................... 5-1
5.1.1 Overview.......................................................................................................................... 5-1
5.2 Memory Map/Register Definition.................................................................................................. 5-2
5.2.1 Cache Control Register (CACR) ..................................................................................... 5-2
5.2.2 Access Control Registers (ACR0–ACR1)....................................................................... 5-4
5.3 Functional Description................................................................................................................... 5-5
5.3.1 Cache Organization.......................................................................................................... 5-5
5.3.2 Cache Operation .............................................................................................................. 5-7
5.3.3 Caching Modes ..............................................................................................................5-10
5.3.4 Cache-Inhibited Accesses.............................................................................................. 5-11
5.3.5 Cache Protocol............................................................................................................... 5-11
5.3.6 Cache Coherency........................................................................................................... 5-13
5.3.7 Memory Accesses for Cache Maintenance.................................................................... 5-13
5.3.8 Cache Locking............................................................................................................... 5-15
5.3.9 Cache Management........................................................................................................ 5-16
5.3.10 Cache Operation Summary............................................................................................ 5-17
Chapter 6
Static RAM (SRAM)
6.1 Introduction.................................................................................................................................... 6-1
6.1.1 Overview.......................................................................................................................... 6-1
6.1.2 Features............................................................................................................................ 6-1
6.2 Memory Map/Register Description................................................................................................ 6-2
6.2.1 SRAM Base Address Register (RAMBAR).................................................................... 6-2
6.3 Initialization/Application Information ........................................................................................... 6-4
6.3.1 SRAM Initialization Code ............................................................................................... 6-4
6.3.2 Power Management ......................................................................................................... 6-5
Chapter 7
Clock Module
7.1 Introduction.................................................................................................................................... 7-1
7.1.1 Block Diagram................................................................................................................. 7-3
7.1.2 Features............................................................................................................................ 7-3
7.1.3 Modes of Operation .........................................................................................................7-3
7.2 Memory Map/Register Definition.................................................................................................. 7-5
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Title
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7.2.1 PLL Output Divider Register (PODR) ............................................................................ 7-6
7.2.2 PLL Control Register (PCR)............................................................................................ 7-6
7.2.3 PLL Modulation Divider Register (PMDR).................................................................... 7-7
7.2.4 PLL Feedback Divider Register (PFDR)......................................................................... 7-8
7.3 Functional Description................................................................................................................... 7-8
7.3.1 PLL Dithered and Non-Dithered Operation .................................................................... 7-8
7.3.2 Dithering Waveform Definition....................................................................................... 7-9
7.3.3 PLL Frequency Multiplication Factor Select................................................................. 7-10
7.3.4 System Clock Modes ..................................................................................................... 7-11
7.3.5 Clock Operation During Reset....................................................................................... 7-11
Chapter 8
Power Management
8.1 Introduction.................................................................................................................................... 8-1
8.1.1 Features............................................................................................................................ 8-1
8.2 Memory Map/Register Definition.................................................................................................. 8-1
8.2.1 Wake-up Control Register ............................................................................................... 8-2
8.2.2 Peripheral Power Management Set Registers (PPMSR0 & PPMSR1) ........................... 8-3
8.2.3 Peripheral Power Management Clear Registers (PPMCR0 & PPMCR1)....................... 8-4
8.2.4 Peripheral Power Management Registers (PPMHR0, PPMHR1, & PPMLR0).............. 8-4
8.2.5 Low-Power Control Register (LPCR) ............................................................................. 8-7
8.3 Functional Description................................................................................................................... 8-8
8.3.1 Peripheral Shut Down...................................................................................................... 8-8
8.3.2 Limp mode....................................................................................................................... 8-8
8.3.3 Low-Power Modes........................................................................................................... 8-9
8.3.4 Peripheral Behavior in Low-Power Modes ................................................................... 8-10
8.3.5 Summary of Peripheral State During Low-power Modes ............................................. 8-15
9.1 Introduction.................................................................................................................................... 9-1
9.1.1 Block Diagram................................................................................................................. 9-1
9.1.2 Features............................................................................................................................ 9-1
9.1.3 Modes of Operation .........................................................................................................9-1
9.2 External Signal Descriptions.......................................................................................................... 9-2
9.2.1 RCON .............................................................................................................................. 9-2
9.2.2 D[9:86:1] (Reset Configuration Override) ...................................................................... 9-2
9.3 Memory Map/Register Definition.................................................................................................. 9-2
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Chapter 9
Chip Configuration Module (CCM)
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Title
Page
Number
9.3.1 Chip Configuration Register (CCR)................................................................................ 9-3
9.3.2 Reset Configuration Register (RCON)............................................................................ 9-4
9.3.3 Chip Identification Register (CIR) .................................................................................. 9-4
9.3.4 Miscellaneous Control Register (MISCCR).................................................................... 9-5
9.3.5 Clock Divider Register .................................................................................................... 9-6
9.3.6 USB Host Controller Status Register (UHCSR).............................................................. 9-7
9.3.7 USB On-the-Go Controller Status Register (UOCSR).................................................... 9-7
9.4 Functional Description................................................................................................................... 9-9
9.4.1 Reset Configuration......................................................................................................... 9-9
9.4.2 PLL Mode Selection...................................................................................................... 9-11
9.4.3 Oscillator Mode Selection ............................................................................................. 9-11
9.4.4 Boot Device Selection ................................................................................................... 9-11
9.4.5 Output Pad Strength Configuration ............................................................................... 9-11
9.4.6 Chip Select Configuration ............................................................................................. 9-12
Chapter 10
Reset Controller Module
10.1 Introduction.................................................................................................................................. 10-1
10.1.1 Block Diagram............................................................................................................... 10-1
10.1.2 Features.......................................................................................................................... 10-1
10.2 External Signal Description ......................................................................................................... 10-2
10.2.1 RESET........................................................................................................................... 10-2
10.2.2 RSTOUT........................................................................................................................ 10-2
10.3 Memory Map/Register Definition................................................................................................ 10-2
10.3.1 Reset Control Register (RCR)....................................................................................... 10-2
10.3.2 Reset Status Register (RSR).......................................................................................... 10-3
10.4 Functional Description................................................................................................................. 10-4
10.4.1 Reset Sources................................................................................................................. 10-4
10.4.2 Reset Control Flow........................................................................................................ 10-5
10.4.3 Concurrent Resets.......................................................................................................... 10-7
Chapter 11
System Control Module (SCM)
11.1 Introduction.................................................................................................................................. 11-1
11.1.1 Overview........................................................................................................................ 11-1
11.1.2 Features.......................................................................................................................... 11-1
11.2 Memory Map/Register Definition................................................................................................ 11-2
11.2.1 Master Privilege Register 0 (MPR0) ............................................................................. 11-3
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11.2.2 Master Privilege Register 1 (MPR1) ............................................................................. 11-4
11.2.3 Peripheral Access Control Registers (PACRx)..............................................................11-4
11.2.4 Bus Monitor Timeout Registers (BMT
11.2.5 Core Watchdog Control Register (CWCR)................................................................... 11-8
11.2.6 Core Watchdog Service Register (CWSR).................................................................... 11-9
11.2.7 SCM Interrupt Status Register (SCMISR)...................................................................11-10
11.2.8 Burst Configuration Register (BCR)........................................................................... 11-10
11.2.9 Core Fault Address Register (CFADR)....................................................................... 11-11
11.2.10 Core Fault Interrupt Enable Register (CFIER)............................................................ 11-12
11.2.11 Core Fault Location Register (CFLOC)...................................................................... 11-12
11.2.12 Core Fault Attributes Register (CFATR).....................................................................11-12
11.2.13 Core Fault Data Register (CFDTR)............................................................................. 11-13
11.3 Functional Description............................................................................................................... 11-14
11.3.1 Access Control............................................................................................................. 11-14
11.3.2 Core Watchdog Timer ................................................................................................. 11-14
11.3.3 Core Data Fault Recovery Registers............................................................................ 11-15
Title
n)...................................................................... 11-7
Page
Number
Chapter 12
Crossbar Switch (XBS)
12.1 Overview...................................................................................................................................... 12-1
12.2 Features ........................................................................................................................................ 12-3
12.3 Modes of Operation...................................................................................................................... 12-3
12.4 Memory Map / Register Definition.............................................................................................. 12-3
12.4.1 XBS Priority Registers (XBS_PRSn)............................................................................ 12-4
12.4.2 XBS Control Registers (XBS_CRS
12.5 Functional Description................................................................................................................. 12-6
12.5.1 Arbitration...................................................................................................................... 12-6
12.6 Initialization/Application Information ......................................................................................... 12-7
n) ........................................................................... 12-5
Chapter 13
General Purpose I/O Module
13.1 Introduction.................................................................................................................................. 13-1
13.1.1 Overview........................................................................................................................ 13-2
13.1.2 Features.......................................................................................................................... 13-3
13.2 External Signal Description ......................................................................................................... 13-3
13.3 Memory Map/Register Definition.............................................................................................. 13-11
13.3.1 Port Output Data Registers (PODR_
13.3.2 Port Data Direction Registers (PDDR_
x)........................................................................ 13-14
x).................................................................... 13-17
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13.3.3 Port Pin Data/Set Data Registers (PPDSDR_x)...........................................................13-19
13.3.4 Port Clear Output Data Registers (PCLRR_
13.3.5 Pin Assignment Registers (PAR_
13.3.6 FlexBus Mode Select Control Register (MSCR_FLEXBUS)..................................... 13-34
13.3.7 SDRAM Mode Select Control Register (MSCR_SDRAM)........................................13-34
13.3.8 Drive Strength Control Registers (DSCR_x)............................................................... 13-35
13.4 Functional Description............................................................................................................... 13-38
13.4.1 Overview...................................................................................................................... 13-38
13.4.2 Port Digital I/O Timing................................................................................................13-38
13.5 Initialization/Application Information ....................................................................................... 13-39
Title
x) ............................................................ 13-21
x)............................................................................. 13-23
Page
Number
Chapter 14
Interrupt Controller Modules
14.1 Introduction.................................................................................................................................. 14-1
14.1.1 68 K/ColdFire Interrupt Architecture Overview ........................................................... 14-1
14.2 Memory Map/Register Definition................................................................................................ 14-2
14.2.1 Interrupt Pending Registers (IPRHn, IPRLn)................................................................ 14-4
14.2.2 Interrupt Mask Register (IMRHn, IMRLn)................................................................... 14-5
14.2.3 Interrupt Force Registers (INTFRCHn, INTFRCLn).................................................... 14-6
14.2.4 Interrupt Configuration Register (ICONFIG)................................................................ 14-7
14.2.5 Set Interrupt Mask Register (SIMRn)............................................................................14-8
14.2.6 Clear Interrupt Mask Register (CIMRn)........................................................................14-9
14.2.7 Current Level Mask Register (CLMASK)..................................................................... 14-9
14.2.8 Saved Level Mask Register (SLMASK) ..................................................................... 14-10
14.2.9 Interrupt Control Register (ICR0n, ICR1n, (n = 00, 01, 02, ..., 63))...........................14-11
14.2.10 Software and Level 1 – 7 IACK Registers (SWIACKn, L1IACKn – L7IACKn)...... 14-15
14.3 Functional Description............................................................................................................... 14-16
14.3.1 Interrupt Controller Theory of Operation.................................................................... 14-16
14.3.2 Prioritization Between Interrupt Controllers............................................................... 14-18
14.3.3 Low-Power Wake-up Operation.................................................................................. 14-18
14.4 Initialization/Application Information ....................................................................................... 14-19
14.4.1 Interrupt Service Routines........................................................................................... 14-19
15.1 Introduction.................................................................................................................................. 15-1
15.2 Low-Power Mode Operation........................................................................................................ 15-2
15.3 Interrupt/GPIO Pin Descriptions.................................................................................................. 15-2
xii Freescale Semiconductor
Chapter 15
Edge Port Module (EPORT)
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15.4 Memory Map/Register Definition................................................................................................ 15-2
15.4.1 EPORT Pin Assignment Register (EPPAR).................................................................. 15-3
15.4.2 EPORT Data Direction Register (EPDDR)................................................................... 15-4
15.4.3 Edge Port Interrupt Enable Register (EPIER) ............................................................... 15-5
15.4.4 Edge Port Data Register (EPDR)................................................................................... 15-5
15.4.5 Edge Port Pin Data Register (EPPDR).......................................................................... 15-5
15.4.6 Edge Port Flag Register (EPFR).................................................................................... 15-6
Chapter 16
Enhanced Direct Memory Access (eDMA)
16.1 Overview...................................................................................................................................... 16-1
16.2 Block Diagram ............................................................................................................................. 16-1
16.3 Features ........................................................................................................................................ 16-2
16.4 Modes of Operation...................................................................................................................... 16-2
16.4.1 Normal Mode................................................................................................................. 16-2
16.4.2 Debug Mode .................................................................................................................. 16-3
16.5 External Signal Description ......................................................................................................... 16-3
16.5.1 External Signal Timing.................................................................................................. 16-3
16.6 Memory Map/Register Definition................................................................................................ 16-4
16.6.1 eDMA Control Register (EDMA_CR).......................................................................... 16-4
16.6.2 eDMA Error Status Register (EDMA_ES).................................................................... 16-5
16.6.3 eDMA Enable Request Register (EDMA_ERQ)...........................................................16-8
16.6.4 eDMA Enable Error Interrupt Registers (EDMA_EEI)................................................ 16-9
16.6.5 eDMA Set Enable Request Register (EDMA_SERQ).................................................. 16-9
16.6.6 eDMA Clear Enable Request Register (EDMA_CERQ)............................................ 16-10
16.6.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEI) ....................................... 16-11
16.6.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)....................................16-11
16.6.9 eDMA Clear Interrupt Request Register (EDMA_CINT)........................................... 16-12
16.6.10 eDMA Clear Error Register (EDMA_CERR)............................................................. 16-13
16.6.11 eDMA Set START Bit Register (EDMA_SSRT)....................................................... 16-13
16.6.12 eDMA Clear DONE Status Bit Register (EDMA_CDNE)......................................... 16-14
16.6.13 eDMA Interrupt Request Register (EDMA_INT)....................................................... 16-15
16.6.14 eDMA Error Register (EDMA_ERR)......................................................................... 16-15
16.6.15 eDMA Channel n Priority Registers (DCHPRIn)........................................................16-16
16.6.16 Transfer Control Descriptors (TCDn) ......................................................................... 16-17
16.7 Functional Description............................................................................................................... 16-24
16.7.1 eDMA Microarchitecture............................................................................................. 16-24
16.7.2 eDMA Basic Data Flow............................................................................................... 16-25
16.8 Initialization/Application Information ....................................................................................... 16-28
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16.8.1 eDMA Initialization..................................................................................................... 16-28
16.8.2 DMA Programming Errors.......................................................................................... 16-31
16.8.3 DMA Arbitration Mode Considerations...................................................................... 16-31
16.8.4 DMA Transfer..............................................................................................................16-32
16.8.5 eDMA TCDn Status Monitoring................................................................................. 16-35
16.8.6 Channel Linking .......................................................................................................... 16-36
16.8.7 Dynamic Programming................................................................................................ 16-37
Chapter 17
FlexBus
17.1 Introduction.................................................................................................................................. 17-1
17.1.1 Overview........................................................................................................................ 17-1
17.1.2 Features.......................................................................................................................... 17-2
17.2 External Signals............................................................................................................................ 17-2
17.2.1 Address and Data Buses (FB_A[23:0], FB_D[31:0])................................................... 17-2
17.2.2 Chip Selects (FB_CS[5:0])............................................................................................ 17-3
17.2.3 Byte Enables/Byte Write Enables (FB_BE/BWE[3:0])................................................ 17-3
17.2.4 Output Enable (FB_OE)................................................................................................ 17-3
17.2.5 Read/Write (FB_R/W)................................................................................................... 17-3
17.2.6 Transfer Start (FB_TS).................................................................................................. 17-3
17.2.7 Transfer Acknowledge (FB_TA)................................................................................... 17-3
17.3 Memory Map/Register Definition................................................................................................ 17-4
17.3.1 Chip-Select Address Registers (CSAR0 – CSAR5)...................................................... 17-4
17.3.2 Chip-Select Mask Registers (CSMR0 – CSMR5)......................................................... 17-5
17.3.3 Chip-Select Control Registers (CSCR0 – CSCR5)....................................................... 17-6
17.4 Functional Description................................................................................................................. 17-9
17.4.1 Chip-Select Operation....................................................................................................17-9
17.4.2 Data Transfer Operation.............................................................................................. 17-10
17.4.3 Data Byte Alignment and Physical Connections......................................................... 17-11
17.4.4 Bus Cycle Execution.................................................................................................... 17-12
17.4.5 FlexBus Timing Examples...........................................................................................17-13
17.4.6 Burst Cycles................................................................................................................. 17-24
17.4.7 Misaligned Operands...................................................................................................17-30
17.4.8 Bus Errors.................................................................................................................... 17-30
18.1 Introduction.................................................................................................................................. 18-1
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Chapter 18
SDRAM Controller (SDRAMC)
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18.1.1 Block Diagram............................................................................................................... 18-2
18.1.2 Features.......................................................................................................................... 18-2
18.1.3 Terminology...................................................................................................................18-3
18.2 External Signal Description ......................................................................................................... 18-3
18.3 Interface Recommendations......................................................................................................... 18-5
18.3.1 Supported Memory Configurations............................................................................... 18-5
18.3.2 SDRAM SDR Connections ......................................................................................... 18-10
18.3.3 SDRAM DDR Component Connections..................................................................... 18-12
18.3.4 DDR SDRAM Layout Considerations ........................................................................ 18-12
18.4 Memory Map/Register Definition.............................................................................................. 18-14
18.4.1 SDRAM Mode/Extended Mode Register (SDMR)..................................................... 18-14
18.4.2 SDRAM Control Register (SDCR).............................................................................. 18-15
18.4.3 SDRAM Configuration Register 1 (SDCFG1)............................................................ 18-17
18.4.4 SDRAM Configuration Register 2 (SDCFG2)............................................................ 18-19
18.4.5 SDRAM Chip Select Configuration Registers (SDCSn).............................................18-20
18.5 Functional Description............................................................................................................... 18-21
18.5.1 SDRAM Commands.................................................................................................... 18-21
18.5.2 Read Clock Recovery (RCR) Block............................................................................ 18-26
18.6 Initialization/Application Information ....................................................................................... 18-27
18.6.1 Page Management........................................................................................................ 18-28
18.6.2 Transfer Size................................................................................................................ 18-29
Chapter 19
Fast Ethernet Controller (FEC)
19.1 Introduction.................................................................................................................................. 19-1
19.1.1 Overview....................................................................................................................... 19-1
19.1.2 Block Diagram............................................................................................................... 19-1
19.1.3 Features.......................................................................................................................... 19-3
19.2 Modes of Operation...................................................................................................................... 19-4
19.2.1 Full and Half Duplex Operation.................................................................................... 19-4
19.2.2 Interface Options............................................................................................................19-4
19.2.3 Address Recognition Options........................................................................................ 19-5
19.2.4 Internal Loopback.......................................................................................................... 19-5
19.3 External Signal Description ......................................................................................................... 19-5
19.4 Memory Map/Register Definition................................................................................................ 19-6
19.4.1 MIB Block Counters Memory Map............................................................................... 19-7
19.4.2 Ethernet Interrupt Event Register (EIR)........................................................................19-9
19.4.3 Interrupt Mask Register (EIMR)..................................................................................19-11
19.4.4 Receive Descriptor Active Register (RDAR)..............................................................19-11
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19.4.5 Transmit Descriptor Active Register (TDAR).............................................................19-12
19.4.6 Ethernet Control Register (ECR)................................................................................. 19-13
19.4.7 MII Management Frame Register (MMFR)................................................................ 19-13
19.4.8 MII Speed Control Register (MSCR).......................................................................... 19-15
19.4.9 MIB Control Register (MIBC) .................................................................................... 19-16
19.4.10 Receive Control Register (RCR) ................................................................................. 19-16
19.4.11 Transmit Control Register (TCR)................................................................................ 19-17
19.4.12 Physical Address Lower Register (PALR)..................................................................19-18
19.4.13 Physical Address Upper Register (PAUR).................................................................. 19-19
19.4.14 Opcode/Pause Duration Register (OPD)..................................................................... 19-19
19.4.15 Descriptor Individual Upper Address Register (IAUR).............................................. 19-20
19.4.16 Descriptor Individual Lower Address Register (IALR).............................................. 19-20
19.4.17 Descriptor Group Upper Address Register (GAUR)................................................... 19-21
19.4.18 Descriptor Group Lower Address Register (GALR)...................................................19-21
19.4.19 Transmit FIFO Watermark Register (TFWR)............................................................. 19-21
19.4.20 FIFO Receive Bound Register (FRBR)....................................................................... 19-22
19.4.21 FIFO Receive Start Register (FRSR)...........................................................................19-22
19.4.22 Receive Descriptor Ring Start Register (ERDSR) ...................................................... 19-23
19.4.23 Transmit Buffer Descriptor Ring Start Registers (ETSDR)........................................ 19-23
19.4.24 Receive Buffer Size Register (EMRBR)..................................................................... 19-24
19.5 Functional Description............................................................................................................... 19-25
19.5.1 Buffer Descriptors........................................................................................................19-25
19.5.2 Initialization Se quence................................................................................................. 19-30
19.5.3 User Initialization (Prior to Setting ECR[ETHER_EN])............................................. 19-30
19.5.4 Microcontroller Initialization....................................................................................... 19-31
19.5.5 User Initialization (After Setting ECR[ETHER_EN])................................................ 19-32
19.5.6 Network Interface Options...........................................................................................19-32
19.5.7 FEC Frame Transmission............................................................................................ 19-33
19.5.8 FEC Frame Reception..................................................................................................19-34
19.5.9 Ethernet Address Recognition..................................................................................... 19-35
19.5.10 Hash Algorithm............................................................................................................19-37
19.5.11 Full Duplex Flow Control............................................................................................ 19-40
19.5.12 Inter-Packet Gap (IPG) Time....................................................................................... 19-41
19.5.13 Collision Managing......................................................................................................19-41
19.5.14 MII Internal and External Loopback ........................................................................... 19-41
19.5.15 Ethernet Error-Managing Procedure............................................................................ 19-41
20.1 Introduction.................................................................................................................................. 20-1
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Chapter 20
Universal Serial Bus Interface – Host Module
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20.1.1 Block Diagram............................................................................................................... 20-2
20.1.2 Overview........................................................................................................................ 20-2
20.1.3 Features.......................................................................................................................... 20-2
20.1.4 Modes of Operation....................................................................................................... 20-3
20.2 External Signal Description ......................................................................................................... 20-3
20.2.1 USB Host Control and Status Signals............................................................................20-4
20.3 Memory Map/Register Definitions .............................................................................................. 20-5
20.4 Functional Description................................................................................................................. 20-6
Chapter 21
Universal Serial Bus Interface – On-The-Go Module
21.1 Introduction.................................................................................................................................. 21-1
21.1.1 Overview........................................................................................................................ 21-1
21.1.2 Block Diagram............................................................................................................... 21-2
21.1.3 Features.......................................................................................................................... 21-3
21.1.4 Modes of Operation....................................................................................................... 21-4
21.2 External Signal Description ......................................................................................................... 21-5
21.2.1 USB OTG Control and Status Signals........................................................................... 21-6
21.3 Memory Map/Register Definition................................................................................................ 21-8
21.3.1 Module Identification Registers.....................................................................................21-9
21.3.2 Capability Registers..................................................................................................... 21-13
21.3.3 Operational Registers................................................................................................... 21-16
21.4 Functional Description............................................................................................................... 21-45
21.4.1 System Interface .......................................................................................................... 21-45
21.4.2 DMA Engine................................................................................................................ 21-45
21.4.3 FIFO RAM Controller................................................................................................. 21-45
21.4.4 Physical Layer (PHY) Interface................................................................................... 21-45
21.5 Initialization/Application Information ....................................................................................... 21-46
21.5.1 Host Operation............................................................................................................. 21-46
21.5.2 Device Data Structures................................................................................................ 21-47
21.5.3 Device Operation.........................................................................................................21-54
21.5.4 Servicing Interrupts......................................................................................................21-72
21.5.5 Deviations from the EHCI Specifications ................................................................... 21-73
22.1 Introduction.................................................................................................................................. 22-1
22.1.1 Block Diagram............................................................................................................... 22-1
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Chapter 22
Liquid Crystal Display Controller (LCDC)
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22.1.2 Features.......................................................................................................................... 22-1
22.2 External Signal Description ......................................................................................................... 22-3
22.3 Memory Map/Register Definition................................................................................................ 22-3
22.3.1 LCDC Screen Start Address Register (LCD_SSAR).................................................... 22-5
22.3.2 LCDC Size Register (LCD_SR).................................................................................... 22-5
22.3.3 LCDC Virtual Page Width Register (LCD_VPW)........................................................ 22-5
22.3.4 LCDC Cursor Position Register (LCD_CPR) ............................................................... 22-6
22.3.5 LCDC Cursor Width Height and Blink Register (LCD_CWHB) ................................. 22-7
22.3.6 LCDC Color Cursor Mapping Register (LCD_CCMR)................................................ 22-8
22.3.7 LCDC Panel Configuration Register (LCD_PCR)........................................................ 22-9
22.3.8 LCDC Horizontal Configuration Register (LCD _HCR)............................................. 22-12
22.3.9 LCDC Vertical Configuration Register (LCD_VCR) ................................................. 22-12
22.3.10 LCDC Panning Offset Register (LCD_POR).............................................................. 22-13
22.3.11 LCDC Sharp Configuration Register (LCD_SCR) ..................................................... 22-14
22.3.12 LCDC PWM Contrast Control Register (LCD_PCCR).............................................. 22-16
22.3.13 LCDC DMA Control Register (LCD_DCR)............................................................... 22-16
22.3.14 LCDC Refresh Mode Control Register (LCD_RMCR).............................................. 22-17
22.3.15 LCDC Interrupt Configuration Register (LCD_ICR).................................................. 22-18
22.3.16 LCDC Interrupt Enable Register (LCD_IER)............................................................. 22-19
22.3.17 LCDC Interrupt Status Register (LCD_ISR)............................................................... 22-20
22.3.18 LCDC Graphic Window Start Address Register (LCD_GWSAR)............................. 22-22
22.3.19 LCDC Graphic Window Size Register (LCD_GWSR)............................................... 22-22
22.3.20 LCDC Graphic Window Virtual Page Width Register (LCD_GWVPW) .................. 22-23
22.3.21 LCDC Graphic Window Panning Offset Register (LCD_GWPOR)...........................22-23
22.3.22 LCDC Graphic Window Position Register (LCD_GWPR) ........................................ 22-24
22.3.23 LCDC Graphic Window Control Register (LCD_GWCR)......................................... 22-24
22.3.24 LCDC Graphic Window DMA Control Register (LCD_GWDCR)............................ 22-26
22.3.25 Mapping RAM Registers (BGLUT and GWLUT)...................................................... 22-26
22.4 Functional Description............................................................................................................... 22-29
22.4.1 LCD Screen Format..................................................................................................... 22-29
22.4.2 Graphic Window on Screen......................................................................................... 22-30
22.4.3 Panning........................................................................................................................ 22-31
22.4.4 Display Data Mapping................................................................................................. 22-31
22.4.5 Black-and-White Operation......................................................................................... 22-33
22.4.6 Gray-Scale Operation .................................................................................................. 22-33
22.4.7 Color Generation..........................................................................................................22-34
22.4.8 Frame Rate Modulation Control (FRC)....................................................................... 22-36
22.4.9 Panel Interface Signals and Timing............................................................................. 22-37
22.4.10 8 bpp Mode Color STN Panel......................................................................................22-40
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Chapter 23
FlexCAN
23.1 Introduction.................................................................................................................................. 23-1
23.1.1 Block Diagram............................................................................................................... 23-1
23.1.2 Features.......................................................................................................................... 23-3
23.1.3 Modes of Operation....................................................................................................... 23-3
23.2 External Signal Description ......................................................................................................... 23-5
23.3 Memory Map/Register Definition................................................................................................ 23-5
23.3.1 FlexCAN Configuration Register (CANMCR)............................................................. 23-6
23.3.2 FlexCAN Control Register (CANCTRL)...................................................................... 23-8
23.3.3 FlexCAN Free Running Timer Register (TIMER)...................................................... 23-10
23.3.4 Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK)................................. 23-11
23.3.5 FlexCAN Error Counter Register (ERRCNT)............................................................. 23-12
23.3.6 FlexCAN Error and Status Register (ERRSTAT)....................................................... 23-13
23.3.7 Interrupt Mask Register (IMASK)............................................................................... 23-15
23.3.8 Interrupt Flag Register (IFLAG)..................................................................................23-16
23.3.9 Message Buffer Structure............................................................................................ 23-16
23.3.10 Functional Overview....................................................................................................23-20
23.3.11 Transmit Process.......................................................................................................... 23-20
23.3.12 Arbitration Process ...................................................................................................... 23-21
23.3.13 Receive Process........................................................................................................... 23-21
23.3.14 Matching Process......................................................................................................... 23-23
23.3.15 Message Buffer Managing........................................................................................... 23-23
23.3.16 CAN Protocol Related Frames .................................................................................... 23-25
23.3.17 Time Stamp.................................................................................................................. 23-26
23.3.18 Bit Timing.................................................................................................................... 23-26
23.4 Initialization/Application Information ....................................................................................... 23-28
23.4.1 Interrupts...................................................................................................................... 23-29
24.1 Introduction.................................................................................................................................. 24-1
24.1.1 Overview........................................................................................................................ 24-2
24.1.2 Features.......................................................................................................................... 24-3
24.1.3 Modes of Operation....................................................................................................... 24-3
24.2 External Signal Description ......................................................................................................... 24-5
24.2.1 SSI_CLKIN — SSI Clock Input.................................................................................... 24-5
24.2.2 SSI_BCLK — Serial Bit Clock..................................................................................... 24-5
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Synchronous Serial Interface (SSI)
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24.2.3 SSI_MCLK — Serial Master Clock.............................................................................. 24-5
24.2.4 SSI_FS — Serial Frame Sync........................................................................................ 24-5
24.2.5 SSI_RXD — Serial Receive Data ................................................................................. 24-5
24.2.6 SSI_TXD — Serial Transmit Data................................................................................ 24-6
24.3 Memory Map/Register Definition................................................................................................ 24-7
24.3.1 SSI Transmit Data Registers 0 and 1 (SSI_TX0/1)...................................................... 24-8
24.3.2 SSI Transmit FIFO 0 and 1 Registers........................................................................... 24-9
24.3.3 SSI Transmit Shift Register (TXSR)............................................................................. 24-9
24.3.4 SSI Receive Data Registers 0 and 1 (SSI_RX0/1) ..................................................... 24-10
24.3.5 SSI Receive FIFO 0 and 1 Registers .......................................................................... 24-11
24.3.6 SSI Receive Shift Register (RXSR).............................................................................24-11
24.3.7 SSI Control Register (SSI_CR)................................................................................... 24-13
24.3.8 SSI Interrupt Status Register (SSI_ISR)...................................................................... 24-15
24.3.9 SSI Interrupt Enable Register (SSI_IER).................................................................... 24-20
24.3.10 SSI Transmit Configuration Register (SSI_TCR)....................................................... 24-21
24.3.11 SSI Receive Configuration Register (SSI_RCR).........................................................24-23
24.3.12 SSI Clock Control Register (SSI_CCR)...................................................................... 24-24
24.3.13 SSI FIFO Control/Status Register (SSI_FCSR).......................................................... 24-25
24.3.14 SSI AC97 Control Register (SSI_ACR)...................................................................... 24-27
24.3.15 SSI AC97 Command Address Register (SSI_ACADD) ............................................. 24-28
24.3.16 SSI AC97 Command Data Register (SSI_ACDAT)................................................... 24-29
24.3.17 SSI AC97 Tag Register (SSI_ATAG)......................................................................... 24-29
24.3.18 SSI Transmit Time Slot Mask Register (SSI_TMASK).............................................. 24-30
24.3.19 SSI Receive Time Slot Mask Register (SSI_RMASK)............................................... 24-30
24.4 Functional Description............................................................................................................... 24-30
24.4.1 Detailed Operating Mode Descriptions....................................................................... 24-30
24.4.2 SSI Clocking................................................................................................................ 24-43
24.4.3 External Frame and Clock Operation .......................................................................... 24-46
24.4.4 Supported Data Alignment Formats............................................................................ 24-46
24.4.5 Receive Interrupt Enable Bit Description.................................................................... 24-48
24.4.6 Transmit Interrupt Enable Bit Description.................................................................. 24-48
24.5 Initialization/Application Information ....................................................................................... 24-49
25.1 Introduction.................................................................................................................................. 25-1
25.1.1 Overview........................................................................................................................ 25-1
25.1.2 Features.......................................................................................................................... 25-2
25.1.3 Modes of Operation....................................................................................................... 25-2
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Chapter 25
Real-Time Clock
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25.2 External Signal Description ......................................................................................................... 25-3
25.3 Memory Map/Register Definition................................................................................................ 25-3
25.3.1 RTC Hours and Minutes Counter Register (RTC_HOURMIN)................................... 25-3
25.3.2 RTC Seconds Counter Register (RTC_SECONDS) ..................................................... 25-4
25.3.3 RTC Hours and Minutes Alarm Register (RTC_ALRM_HM)..................................... 25-4
25.3.4 RTC Seconds Alarm Register (RTC_ALRM_SEC) ..................................................... 25-5
25.3.5 RTC Control Register (RTC_CR)................................................................................. 25-5
25.3.6 RTC Interrupt Status Register (RTC_ISR).................................................................... 25-6
25.3.7 RTC Interrupt Enable Register (RTC_IER).................................................................. 25-7
25.3.8 RTC Stopwatch Minutes Register (RTC_STPWCH).................................................... 25-8
25.3.9 RTC Days Counter Register (RTC_DAYS).................................................................. 25-9
25.3.10 RTC Day Alarm Register (RTC_ALRM_DAY)........................................................... 25-9
25.4 Functional Description............................................................................................................... 25-10
25.4.1 Prescaler and Counter.................................................................................................. 25-10
25.4.2 Alarm........................................................................................................................... 25-10
25.4.3 Sampling Timer........................................................................................................... 25-11
25.4.4 Minute Stopwatch........................................................................................................ 25-11
25.5 Initialization/Application Information ....................................................................................... 25-12
25.5.1 Flow Chart of RTC Operation..................................................................................... 25-12
25.5.2 Programming the Alarm or Time-of-Day Registers.................................................... 25-12
Chapter 26
Pulse-Width Modulation (PWM) Module
26.1 Introduction.................................................................................................................................. 26-1
26.1.1 Overview........................................................................................................................ 26-1
26.2 Memory Map/Register Definition................................................................................................ 26-2
26.2.1 PWM Enable Register (PWME).................................................................................... 26-3
26.2.2 PWM Polarity Register (PWMPOL)............................................................................. 26-4
26.2.3 PWM Clock Select Register (PWMCLK)..................................................................... 26-4
26.2.4 PWM Prescale Clock Select Register (PWMPRCLK).................................................. 26-5
26.2.5 PWM Center Align Enable Register (PWMCAE) ........................................................ 26-6
26.2.6 PWM Control Register (PWMCTL)..............................................................................26-6
26.2.7 PWM Scale A Register (PWMSCLA)...........................................................................26-7
26.2.8 PWM Scale B Register (PWMSCLB)........................................................................... 26-8
26.2.9 PWM Channel Counter Registers (PWMCNTn) .......................................................... 26-9
26.2.10 PWM Channel Period Registers (PWMPER
26.2.11 PWM Channel Duty Registers (PWMDTYn)............................................................. 26-10
26.2.12 PWM Shutdown Register (PWMSDN)....................................................................... 26-11
26.3 Functional Description............................................................................................................... 26-12
n)............................................................ 26-10
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26.3.1 PWM Clock Select.......................................................................................................26-12
26.3.2 PWM Channel Timers................................................................................................. 26-14
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Chapter 27
Watchdog Timer Module
27.1 Introduction.................................................................................................................................. 27-1
27.1.1 Low-Power Mode Operation......................................................................................... 27-1
27.1.2 Block Diagram............................................................................................................... 27-2
27.2 Memory Map/Register Definition................................................................................................ 27-2
27.2.1 Watchdog Control Register (WCR)............................................................................... 27-3
27.2.2 Watchdog Modulus Register (WMR)............................................................................ 27-4
27.2.3 Watchdog Count Register (WCNTR)............................................................................ 27-4
27.2.4 Watchdog Service Register (WSR)............................................................................... 27-5
Chapter 28
Programmable Interrupt Timers (PIT0–PIT3)
28.1 Introduction.................................................................................................................................. 28-1
28.1.1 Overview........................................................................................................................ 28-1
28.1.2 Block Diagram............................................................................................................... 28-1
28.1.3 Low-Power Mode Operation......................................................................................... 28-1
28.2 Memory Map/Register Definition................................................................................................ 28-2
28.2.1 PIT Control and Status Register (PCSRn)..................................................................... 28-3
28.2.2 PIT Modulus Register (PMRn)......................................................................................28-5
28.2.3 PIT Count Register (PCNTR
28.3 Functional Description................................................................................................................. 28-6
28.3.1 Set-and-Forget Timer Operation.................................................................................... 28-6
28.3.2 Free-Running Timer Operation ..................................................................................... 28-6
28.3.3 Timeout Specifications.................................................................................................. 28-7
28.3.4 Interrupt Operation ........................................................................................................ 28-7
n)...................................................................................... 28-5
Chapter 29
DMA Timers (DTIM0–DTIM3)
29.1 Introduction.................................................................................................................................. 29-1
29.1.1 Overview........................................................................................................................ 29-1
29.1.2 Features.......................................................................................................................... 29-2
29.2 Memory Map/Register Definition................................................................................................ 29-3
29.2.1 DMA Timer Mode Registers (DTMR
n)........................................................................ 29-3
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29.2.2 DMA Timer Extended Mode Registers (DTXMRn)..................................................... 29-4
29.2.3 DMA Timer Event Registers (DTERn)......................................................................... 29-5
29.2.4 DMA Timer Reference Registers (DTRR
29.2.5 DMA Timer Capture Registers (DTCR
n).................................................................. 29-6
n) ..................................................................... 29-7
29.2.6 DMA Timer Counters (DTCNn)................................................................................... 29-8
29.3 Functional Description................................................................................................................. 29-8
29.3.1 Prescaler......................................................................................................................... 29-8
29.3.2 Capture Mode ................................................................................................................ 29-8
29.3.3 Reference Compare........................................................................................................29-8
29.3.4 Output Mode.................................................................................................................. 29-9
29.3.5 IEEE 1588 Support........................................................................................................ 29-9
29.4 Initialization/Application Information ......................................................................................... 29-9
29.4.1 Code Example................................................................................................................ 29-9
29.4.2 Calculating Time-Out Values......................................................................................29-10
Chapter 30
Queued Serial Peripheral Interface (QSPI)
30.1 Introduction.................................................................................................................................. 30-1
30.1.1 Block Diagram............................................................................................................... 30-1
30.1.2 Overview........................................................................................................................ 30-2
30.1.3 Features.......................................................................................................................... 30-2
30.1.4 Modes of Operation....................................................................................................... 30-2
30.2 External Signal Description ......................................................................................................... 30-2
30.3 Memory Map/Register Definition................................................................................................ 30-3
30.3.1 QSPI Mode Register (QMR)......................................................................................... 30-3
30.3.2 QSPI Delay Register (QDLYR) .................................................................................... 30-5
30.3.3 QSPI Wrap Register (QWR)..........................................................................................30-6
30.3.4 QSPI Interrupt Register (QIR)....................................................................................... 30-6
30.3.5 QSPI Address Register (QAR)...................................................................................... 30-7
30.3.6 QSPI Data Register (QDR)............................................................................................ 30-8
30.3.7 Command RAM Registers (QCR0–QCR15)................................................................. 30-8
30.4 Functional Description................................................................................................................. 30-9
30.4.1 QSPI RAM................................................................................................................... 30-11
30.4.2 Baud Rate Selection..................................................................................................... 30-12
30.4.3 Transfer Delays............................................................................................................ 30-13
30.4.4 Transfer Length............................................................................................................30-14
30.4.5 Data Transfer............................................................................................................... 30-14
30.5 Initialization/Application Information ....................................................................................... 30-15
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Chapter 31
UART Modules
31.1 Introduction.................................................................................................................................. 31-1
31.1.1 Overview........................................................................................................................ 31-1
31.1.2 Features.......................................................................................................................... 31-2
31.2 External Signal Description ......................................................................................................... 31-3
31.3 Memory Map/Register Definition................................................................................................ 31-3
31.3.1 UART Mode Registers 1 (UMR1n) .............................................................................. 31-5
31.3.2 UART Mode Register 2 (UMR2n)................................................................................ 31-6
31.3.3 UART Status Registers (USRn).................................................................................... 31-8
31.3.4 UART Clock Select Registers (UCSRn)....................................................................... 31-9
31.3.5 UART Command Registers (UCRn)............................................................................. 31-9
31.3.6 UART Receive Buffers (URBn).................................................................................. 31-11
31.3.7 UART Transmit Buffers (UTBn)................................................................................ 31-12
31.3.8 UART Input Port Change Registers (UIPCRn)........................................................... 31-12
31.3.9 UART Auxiliary Control Register (UACRn).............................................................. 31-13
31.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................................... 31-13
31.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n).......................................... 31-15
31.3.12 UART Input Port Register (UIPn)............................................................................... 31-15
31.3.13 UART Output Port Command Registers (UOP1n/UOP0n)........................................ 31-16
31.4 Functional Description............................................................................................................... 31-16
31.4.1 Transmitter/Receiver Clock Source............................................................................. 31-16
31.4.2 Transmitter and Receiver Operating Modes................................................................31-18
31.4.3 Looping Modes............................................................................................................ 31-22
31.4.4 Multidrop Mode........................................................................................................... 31-24
31.4.5 Bus Operation.............................................................................................................. 31-26
31.5 Initialization/Application Information ....................................................................................... 31-26
31.5.1 Interrupt and DMA Request Initialization................................................................... 31-26
31.5.2 UART Module Initialization Sequence....................................................................... 31-28
32.1 Introduction.................................................................................................................................. 32-1
32.1.1 Block Diagram............................................................................................................... 32-1
32.1.2 Overview........................................................................................................................ 32-2
32.1.3 Features.......................................................................................................................... 32-2
32.2 Memory Map/Register Definition................................................................................................ 32-3
32.2.1 I
xxiv Freescale Semiconductor
Chapter 32
2
I
C Interface
2
C Address Register (I2ADR)...................................................................................... 32-3
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Contents
MCF5329 Reference Manual, Rev 3
Paragraph
Number
Title
Page
Number
32.2.2 I2C Frequency Divider Register (I2FDR)...................................................................... 32-3
32.2.3 I2C Control Register (I2CR).......................................................................................... 32-4
2
32.2.4 I
32.2.5 I
C Status Register (I2SR)............................................................................................. 32-5
2
C Data I/O Register (I2DR)........................................................................................ 32-6
32.3 Functional Description................................................................................................................. 32-7
32.3.1 START Signal................................................................................................................32-7
32.3.2 Slave Address Transmission.......................................................................................... 32-8
32.3.3 Data Transfer................................................................................................................. 32-8
32.3.4 Acknowledge................................................................................................................. 32-9
32.3.5 STOP Signal .................................................................................................................. 32-9
32.3.6 Repeated START........................................................................................................... 32-9
32.3.7 Clock Synchronization and Arbitration....................................................................... 32-11
32.3.8 Handshaking and Clock Stretching..............................................................................32-12
32.4 Initialization/Application Information ....................................................................................... 32-12
32.4.1 Initialization Se quence................................................................................................. 32-12
32.4.2 Generation of START.................................................................................................. 32-12
32.4.3 Post-Transfer Software Response................................................................................ 32-13
32.4.4 Generation of STOP.....................................................................................................32-13
32.4.5 Generation of Repeated START.................................................................................. 32-14
32.4.6 Slave Mode.................................................................................................................. 32-14
32.4.7 Arbitration Lost............................................................................................................32-14
Chapter 33
Message Digest Hardware Accelerator (MDHA)
33.1 Introduction.................................................................................................................................. 33-1
33.1.1 Overview........................................................................................................................ 33-1
33.1.2 Features.......................................................................................................................... 33-1
33.1.3 Modes of Operation....................................................................................................... 33-2
33.2 Memory Map/Register Definition................................................................................................ 33-3
33.2.1 MDHA Mode Register (MDMR).................................................................................. 33-3
33.2.2 MDHA Control Register (MDCR)................................................................................ 33-6
33.2.3 MDHA Command Register (MDCMR)........................................................................ 33-7
33.2.4 MDHA Status Register (MDSR)................................................................................... 33-8
33.2.5 MDHA Interrupt Status & Mask Registers (MDISR and MDIMR) ............................. 33-9
33.2.6 MDHA Data Size Register (MDDSR).........................................................................33-11
33.2.7 MDHA Input FIFO (MDIN)........................................................................................ 33-11
33.2.8 MDHA Message Digest Registers 0 (MDx0).............................................................. 33-11
33.2.9 MDHA Message Data Size Register (MDMDS)......................................................... 33-12
33.2.10 MDHA Message Digest Registers 1 (MDx1).............................................................. 33-12
Freescale Semiconductor xxv
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MCF5329 Reference Manual, Rev 3
Paragraph
Number
Title
Page
Number
33.3 Functional Description............................................................................................................... 33-13
33.3.1 MDHA Top Control.....................................................................................................33-13
33.3.2 FIFO............................................................................................................................. 33-13
33.3.3 MDHA Logic............................................................................................................... 33-13
33.4 Initialization/Application Information ....................................................................................... 33-14
33.4.1 Performing a Standard HASH Operation.................................................................... 33-14
33.4.2 Performing a Standard HASH Operation with DMA.................................................. 33-15
33.4.3 Performing a HMAC Operation Without the MACFULL Bit .................................... 33-15
33.4.4 Performing a SHA-1 EHMAC..................................................................................... 33-17
33.4.5 Performing a MAC Operation With the MACFULL Bit ............................................ 33-18
33.4.6 Performing an NMAC ................................................................................................. 33-18
Chapter 34
Random Number Generator (RNG)
34.1 Introduction.................................................................................................................................. 34-1
34.1.1 Overview........................................................................................................................ 34-1
34.2 Memory Map/Register Definition................................................................................................ 34-2
34.2.1 RNG Control Register (RNGCR).................................................................................. 34-2
34.2.2 RNG Status Register (RNGSR)..................................................................................... 34-3
34.2.3 RNG Entropy Register (RNGER).................................................................................. 34-4
34.2.4 RNG Output FIFO (RNGOUT)..................................................................................... 34-4
34.3 Functional Description................................................................................................................. 34-5
34.3.1 Output FIFO................................................................................................................... 34-5
34.3.2 RNG Core/Control Logic Block.................................................................................... 34-5
34.4 Initialization/Application Information ......................................................................................... 34-6
35.1 Introduction.................................................................................................................................. 35-1
35.1.1 Features.......................................................................................................................... 35-1
35.2 Memory Map/Register Definition................................................................................................ 35-5
35.2.1 SKHA Mode Register (SKMR)..................................................................................... 35-6
35.2.2 SKHA Control Register (SKCR)................................................................................... 35-7
35.2.3 SKHA Command Register (SKCMR)........................................................................... 35-8
35.2.4 SKHA Status Register (SKSR)...................................................................................... 35-9
35.2.5 SKHA Error Status and Mask Registers (SKESR, SKESMR).................................... 35-10
35.2.6 SKHA Key Size Register (SKKSR)............................................................................ 35-12
35.2.7 SKHA Data Size Register (SKDSR) ........................................................................... 35-12
xxvi Freescale Semiconductor
Chapter 35
Symmetric Key Hardware Accelerator (SKHA)
Page 27
Contents
MCF5329 Reference Manual, Rev 3
Paragraph
Number
Title
Page
Number
35.2.8 SKHA Input FIFO (SKIN) .......................................................................................... 35-13
35.2.9 SKHA Output FIFO (SKOUT).................................................................................... 35-13
35.2.10 SKHA Key Data Registers (SKKDR
35.2.11 SKHA Context Registers (SKC
n)....................................................................... 35-13
n) ............................................................................... 35-14
35.3 Functional Description............................................................................................................... 35-15
35.3.1 Transmit FIFO Interface Block....................................................................................35-16
35.3.2 Receive FIFO Interface Block.....................................................................................35-16
35.3.3 Top Control Block....................................................................................................... 35-16
35.3.4 SKHA Logic Block...................................................................................................... 35-17
35.3.5 Security Assurance Features........................................................................................ 35-18
35.4 Initialization/Application Information ....................................................................................... 35-19
35.4.1 General Oper ation........................................................................................................ 35-19
35.4.2 Operation with DMA................................................................................................... 35-19
35.4.3 Operation with Context Switch....................................................................................35-20
Chapter 36
Debug Module
36.1 Introduction.................................................................................................................................. 36-1
36.1.1 Block Diagram............................................................................................................... 36-1
36.1.2 Overview........................................................................................................................ 36-1
36.2 Signal Descriptions ...................................................................................................................... 36-2
36.3 Memory Map/Register Definition................................................................................................ 36-3
36.3.1 Shared Debug Resources............................................................................................... 36-4
36.3.2 Configuration/Status Register (CSR).............................................................................36-5
36.3.3 BDM Address Attribute Register (BAAR).................................................................... 36-8
36.3.4 Address Attribute Trigger Register (AATR)................................................................. 36-9
36.3.5 Trigger Definition Register (TDR).............................................................................. 36-10
36.3.6 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR)............................... 36-13
36.3.7 Address Breakpoint Registers (ABLR, ABHR) .......................................................... 36-15
36.3.8 Data Breakpoint and Mask Registers (DBR, DBMR)................................................. 36-16
36.4 Functional Description............................................................................................................... 36-17
36.4.1 Background Debug Mode (BDM)............................................................................... 36-17
36.4.2 Real-Time Debug Support........................................................................................... 36-38
36.4.3 Concurrent BDM and Processor Operation................................................................. 36-40
36.4.4 Real-Time Trace Support.............................................................................................36-40
36.4.5 Debug Translate Block................................................................................................ 36-43
36.4.6 Processor Status, Debug Data Definition .................................................................... 36-44
36.4.7 Freescale-Recommended BDM Pinout ....................................................................... 36-49
Freescale Semiconductor xxvii
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Contents
MCF5329 Reference Manual, Rev 3
Paragraph
Number
Title
Page
Number
Chapter 37
IEEE 1149.1 Test Access Port (JTAG)
37.1 Introduction.................................................................................................................................. 37-1
37.1.1 Block Diagram............................................................................................................... 37-1
37.1.2 Features.......................................................................................................................... 37-2
37.1.3 Modes of Operation....................................................................................................... 37-2
37.2 External Signal Description ......................................................................................................... 37-2
37.2.1 JTAG Enable (JTAG_EN)............................................................................................. 37-2
37.2.2 Test Clock Input (TCLK) .............................................................................................. 37-3
37.2.3 Test Mode Select/Breakpoint (TMS/BKPT)................................................................. 37-3
37.2.4 Test Data Input/Development Serial Input (TDI/DSI).................................................. 37-3
37.2.5 Test Reset/Development Serial Clock (TRST/DSCLK) ............................................... 37-4
37.2.6 Test Data Output/Development Serial Output (TDO/DSO).......................................... 37-4
37.3 Memory Map/Register Definition................................................................................................ 37-4
37.3.1 Instruction Shift Register (IR)....................................................................................... 37-4
37.3.2 IDCODE Register.......................................................................................................... 37-5
37.3.3 Bypass Register..............................................................................................................37-5
37.3.4 TEST_CTRL Register................................................................................................... 37-5
37.3.5 Boundary Scan Register.................................................................................................37-6
37.4 Functional Description................................................................................................................. 37-6
37.4.1 JTAG Module................................................................................................................ 37-6
37.4.2 TAP Controller .............................................................................................................. 37-6
37.4.3 JTAG Instructions.......................................................................................................... 37-7
37.5 Initialization/Application Information ....................................................................................... 37-10
37.5.1 Restrictions.................................................................................................................. 37-10
37.5.2 Nonscan Chain Operation............................................................................................ 37-10
A.1 Register Memory Map.................................................................................................... A-1
B.1 Changes Between Rev. 2 and Rev. 3 ...............................................................................B-1
B.2 Changes Between Rev. 1 and Rev. 2 ...............................................................................B-5
B.3 Changes Between Rev. 0.1 and Rev. 1 ..........................................................................B-12
B.4 Changes Between Rev. 0 and Rev. 0.1 ..........................................................................B-17
xxviii Freescale Semiconductor
Appendix A
Register Memory Map Quick Reference
Appendix B
Revision History
Page 29
About This Book
MCF5329 Reference Manual, Rev 3
The primary objective of this reference manual is to define the functionality of the MCF5329
processor for use by software and hardware developers. In addition, this manual supports the
MCF5327, MCF5328, and MCF53281. This book is written from the perspective of the
MCF5329, and unless otherwise noted, the information applies also to the MCF5327, MCF5328,
and MCF53281. The MCF5327, MCF5328, and MCF53281 have the same functionality as the
MCF5329 and any differences in data regarding bus timing, signal behavior, and AC, DC, and
thermal characteristics are in the hardware specifications. Please refer to Table 1-1 to see a
summary of the differences.
The information in this book is subject to change without notice, as described in the disclaimers
on the title page. As with any technical documentation, it is the reader’s responsibility to be sure
he is using the most recent version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com/coldfire.
Portions of Chapter 20, “Universal Serial Bus Interface – Host Module,” and Chapter 21,
“Universal Serial Bus Interface – On-The-Go Module,” relating to the EHCI specification are
Copyright © Intel Corporation 1999-2001. The EHCI specification is provided as is with no
warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for
any particular purpose, or any warranty otherwise arising out of any proposal, specification or
sample. Intel disclaims all liability, including liability for infringement of any proprietary rights,
relating to use of information in the EHCI specification. Intel may make changes to the EHCI
specifications at any time, without notice.
Audience
This manual is intended for system software and hardware developers and applications
programmers who want to develop products with the MCF5329. It is assumed that the reader
understands operating systems, microprocessor system design, basic principles of software and
hardware, and basic details of the ColdFire
Organization
Following is a summary and brief description of the major sections of this manual:
• Chapter 1, “Overview,” includes general descriptions of the modules and features
incorporated in the device, focusing in particular on new features.
Freescale Semiconductor xxix
®
architecture.
Page 30
• Chapter 2, “Signal Descriptions,” describes the device signals. It includes a listing of
MCF5329 Reference Manual, Rev 3
signals that characterizes each signal as an input or output, defines its state at reset, and
identifies whether a pull-up resistor should be used.
• Chapter 3, “ColdFire Core,” provides an overview of the microprocessor core. The chapter
describes the organization of the Version 2 (V2) ColdFire processor core and an overview
of the programming model as they are implemented on the device.
• Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC),” describes the
multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and
miscellaneous register instructions. The EMAC is integrated into the operand execution
pipeline (OEP).
• Chapter 5, “Cache,” describes the cache implementation, including organization,
configuration, and coherency. It describes cache operations and how the cache interacts
with other memory structures.
• Chapter 6, “Static RAM (SRAM),” describes the on-chip static RAM (SRAM)
implementation. It covers general operations, configuration, and initialization. It also
provides information and examples of how to minimize power consumption when using the
SRAM.
• Chapter 7, “Clock Module,” describes the device’s different clocking methods. It also
describes clock module operation in low power modes.
• Chapter 8, “Power Management,” describes the low power operation of the device and
peripheral behavior in low power modes.
• Chapter 9, “Chip Configuration Module (CCM),” details the various operating
configurations of the device. This chapter provides a description of signals used by the
CCM and a programming model.
• Chapter 10, “Reset Controller Module,” describes the operation of the reset controller
module, detailing the different types of reset that can occur.
• Chapter 11, “System Control Module (SCM),” describes the functionality of the SCM,
which provides the programming model for peripheral access control, the software core
watchdog timer (CWT), and the generic access error information.
• Chapter 12, “Crossbar Switch (XBS),” details the interaction between bus masters and bus
slaves within the device, including arbitration schemes.
• Chapter 13, “General Purpose I/O Module,” describes the operation and programming
model of the general purpose I/O (GPIO) ports on the device.
• Chapter 14, “Interrupt Controller Modules,” describes operation of the interrupt controller
portion of the SCM. Includes descriptions of the registers in the interrupt controller
memory map and the interrupt priority scheme.
• Chapter 15, “Edge Port Module (EPORT),” describes EPORT module functionality,
including operation in low power mode.
xxx Freescale Semiconductor
Page 31
• Chapter 16, “Enhanced Direct Memory Access (eDMA),” describes the direct memory
MCF5329 Reference Manual, Rev 3
access (DMA) controller module. It provides an overview of the module and describes in
detail its signals and registers. The latter sections of this chapter describe operations,
features, and supported data transfer modes in detail.
• Chapter 17, “FlexBus,” describes data-transfer operations, chip-select operation, error
conditions, bus arbitration, and reset operations.
• Chapter 18, “SDRAM Controller (SDRAMC),” describes the configuration and operation
of the SDRAM controller . It begins with a general description and includes a description of
signals involved in DRAM operations. The remainder of the chapter describes the
programming model and signal timing, as well as the command set required for
synchronous operations.
• Chapter 19, “Fast Ethernet Controller (FEC),” provides a feature-set overview , a functional
block diagram, and transceiver connection information for MII (media independent
interface) and 7-wire serial interfaces. It also provides describes operation and the
programming model.
• Chapter 20, “Universal Serial Bus Interface – Host Module,” provides an overview of the
universal serial bus (USB) host module. The USB Specification, Revision 2.0 is a
recommended supplement to this chapter.
• Chapter 21, “Universal Serial Bus Interface – On-The-Go Module,” provides an overview
of the universal serial bus (USB) On-the-Go module. The USB Specification, Revision 2.0
is a recommended supplement to this chapter.
• Chapter 23, “FlexCAN,” describes the implementation of the controller area network
(CAN) protocol. This chapter describes FlexCAN module operation and provides a
programming model.
• Chapter 24, “Synchronous Serial Interface (SSI),” describes SSI module operation and
provides a programming model.
• Chapter 25, “Real-Time Clock,” describes the real-time clock module operation and
provides a programming model.
• Chapter 26, “Pulse-Width Modulation (PWM) Module,” describes the configuration and
operation of the pulse width modulation (PWM) module. It includes a block diagram,
programming model, and functional description.
• Chapter 27, “Watchdog Timer Module,” describes software watchdog timer functionality,
including operation in low power mode.
• Chapter 28, “Programmable Interrupt Timers (PIT0–PIT3),” describes the functionality of
the PIT timers, including operation in low power mode.
• Chapter 29, “DMA Timers (DTIM0–DTIM3),” describes the configuration and operation
of the DMA timer modules. These 32-bit timers provide input capture and reference
compare capabilities with optional signaling of events using interrupts or triggers. This
chapter also provides programming examples.
Freescale Semiconductor xxxi
Page 32
• Chapter 30, “Queued Serial Peripheral Interface (QSPI),” provides a feature-set overview
MCF5329 Reference Manual, Rev 3
and a description of operation, including details of the QSPI’ s internal storage organization.
The chapter concludes with the programming model and a timing diagram.
• Chapter 31, “UART Modules,” desc ribes the use of the universal asynchronous
receiver/transmitters (UARTs) implemented on the device and includes programming
examples.
• Chapter 32, “I2C Interface,” describes the I
synchronization, and I
2
C programming model registers.
2
C module, including I2C protocol, clock
• Chapter 33, “Message Digest Hardware Accelerator (MDHA),” describes implementation
of two of the world’s most popular cryptographic hash functions: SHA-1 and MD5.
Accelerators for either algorithm separately have been designed, however the MDHA
combines similar functions of the two algorithms into one small, optimized area of silicon
on the device.
• Chapter 34, “Random Number Generator (RNG),” describes the 32-bit Random Number
Generator (RNG), including a programming model, functional description, and application
information.
• Chapter 35, “Symmetric Key Hardware Accelerator (SKHA),” describes the cryptographic
hardware coprocessor designed to implement two widely used symmetric key block cipher
algorithms, AES and DES.
• Chapter 36, “Debug Module,” describes the hardware debug support in the device.
• Chapter 37, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and
operation of the Joint Test Action Group (JTAG) implementation. It describes those items
required by the IEEE 1149.1 standard and provides additional information specific to the
device. For internal details and sample applications, see the IEEE 1149.1 document.
This manual includes the following appendices:
• Appendix A, “Register Memory Map Quick Reference,” provides the entire address map
for memory-mapped registers.
• Appendix B, “Revision History,” provides a revision history for all previously released
versions of this document.
Suggested Reading
This section lists additional reading that provides background for the information in this manual
as well as general information about the ColdFire architecture.
Hardware Specification
The MCF5329EC document contains the mechanical and electrical specifications of the
MCF52329. It can be found at http://www.freescale.com/coldfire.
xxxii Freescale Semiconductor
Page 33
General Information
MCF5329 Reference Manual, Rev 3
The following documentation provides useful information about the ColdFire architecture and
computer architecture in general:
• ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD)
• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray,
Ross Bannatyne, Joseph D. Greenfield
• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy
and David A. Patterson.
• Computer Organization and Design: The Hardware/Software Interface, Second Edition,
David A. Patterson and John L. Hennessy.
ColdFire Documentation
ColdFire documentation is available from the sources listed on the back cover of this manual.
• Reference manuals (formerly called user’s manuals)—These books provide details about
individual ColdFire implementations and are intended to be used in conjunction with The
ColdFire Programmers Reference Manual.
• Addenda/errata to reference manuals—Because some processors have follow-on parts, an
addendum is provided that describes the additional features and functionality changes.
Also, if mistakes are found within a reference manual, an errata document will be issued
before the next published release of the reference manual. These addenda/errata are
intended for use with the corresponding reference manuals.
• Hardware specifications—Hardware specifications provide specific data regarding bus
timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design
considerations.
• Product briefs—Each device has a product brief that provides an overview of its features.
This document is roughly equivalent to the overview (Chapter 1) of an implementation’s
reference manual.
• Application notes—These short documents address specific design issues useful to
programmers and engineers working with Freescale Semiconductor processors.
Additional literature is published as new processors become available. For a current list of
ColdFire documentation, refer to http://www.freescale.com/coldfire.
Conventions
This document uses the following notational conventions:
cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value
of one, it is said to be set.
Freescale Semiconductor xxxiii
Page 34
MNEMONICS In text, instruction mnemonics are shown in uppercase.
MCF5329 Reference Manual, Rev 3
mnemonics In code and tables, instruction mnemonics are shown in lowercase.
italics Italics indicate variable command parameters.
Book titles in text are set in italics.
0x0 Prefix to denote hexadecimal number
0b0 Prefix to denote binary number
REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or
ranges appear in brackets. For example, RAMBAR[BA] identifies the base
address field in the RAM base address register.
nibble A 4-bit data unit
byte An 8-bit data unit
word A 16-bit data unit
1
longword A 32-bit data unit
x In some contexts, such as signal encodings, x indicates a don’t care.
n Used to express an undefined numerical value
~ NOT logical operator
& AND logical operator
| OR logical operator
OVERBAR
An overbar indicates that a signal is active-low.
Register Figure Conventions
This document uses the following conventions for the register reset values:
— Undefined at reset.
u Unaffected by reset.
[signal_name] Reset value is determined by the polarity of the indicated signal.
The following register fields are used:
R0
W
R1
W
Indicates a reserved bit field in a memory-mapped register . These bits are
always read as zeros.
Indicates a reserved bit field in a memory-mapped register . These bits are
always read as ones.
1. The only exceptions to this appear in the discussion of serial communication modules th at support variable-length data
transmission units. To simplify the discussion these units are referred to as words regardless of length.
xxxiv Freescale Semiconductor
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R FIELDNAME
MCF5329 Reference Manual, Rev 3
W
Indicates a read/write bit.
R FIELDNAME
W
R
W FIELDNAME
R FIELDNAME
Ww1c
R0
W FIELDNAME
Indicates a read-only bit field in a memory-mapped register.
Indicates a write-only bit field in a memory-mapped register.
Write 1 to clear: indicates that writing a 1 to this bit field clears it.
Indicates a self-clearing bit.
Acronyms and Abbreviations
Table 1 lists acronyms and abbreviations used in this document.
Table 1. Acronyms and Abbreviated Terms
Term Meaning
ADC Analog-to-digital con version
ALU Arithmetic logic unit
BDM Background debug mode
BIST Built-in self test
BSDL Boundary-scan description langu age
CODEC Code/decode
DAC Digital-to-analog conversion
DMA Direct memory access
DSP Digital signal processing
EA Effective address
FIFO First-in, first-out
GPIO General-purpose I/O
2
C Inter-integrated circuit
I
IEEE Institute for Electrical and Electronics Engineers
IFP Instruction fetch pipeline
IPL Interrupt priority level
JEDEC Joint Electron Device Engineering Council
JTAG Joint Test Action Group
Freescale Semiconductor xxxv
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Table 1. Acronyms and Abbreviated Terms (continued)
MCF5329 Reference Manual, Rev 3
Term Meaning
LIFO Last-in, first-out
LRU Least recently used
LSB Least-significant byte
lsb Least-significant bit
MAC Multiply accumulate unit, also Media access controller
MBAR Memory base address register
MSB Most-significant byte
msb Most-significant bit
Mux Multiplex
NOP No operation
OEP Operand execution pipeline
PC Program counter
PCLK Processor clock
PLIC Physical layer interface controller
PLL Phase-locked loop
POR Power-on reset
PQFP Plastic quad flat pack
PWM Pulse width modulation
QSPI Queued serial peripheral interface
RISC Reduced instruction set computing
Rx Receive
SIM System integration module
SOF Start of frame
TAP Test access port
TTL Transistor transistor logic
Tx Transmit
UART Universal asynchronous/synchronous receiver transmitter
USB Universal serial bus
Terminology Conventions
Table 2 shows terminology conventions used throughout this document.
xxxvi Freescale Semiconductor
Page 37
Table 2. Notational Conventions
MCF5329 Reference Manual, Rev 3
Instruction Operand Syntax
Opcode Wildcard
cc Lo gical condition (example: NE for not equal)
Register Specifications
An Any address register n (example: A3 is address register 3)
Ay,Ax Source and destination address registers, respectively
Dn Any data register n (example: D5 is data register 5)
Dy,Dx Source and destination data registers, respectively
Rc Any control register (example VBR is the vector base register)
Rm MAC registers (ACC, MAC, MASK)
Rn Any address or data register
Rw Destination register w (used for MAC instructions only)
Ry,Rx Any source and destination registers, respectively
Xi Index register i (can be an address or data register: Ai, Di)
Miscellaneous Operands
#<data> Immediate data following the 16-bit operation word of the instruction
<ea> Effective address
<ea>y,<ea>x Source and destination effective addresses, respectively
<label> Assembly language program label
<list> List of registers for MOVEM instruction (example: D3–D0)
<shift> Shift operation: shift left (<<), shift right (>>)
<size> Operand data size: byte (B), word (W), longword (L)
bc Instruction and data caches
dc Data cache
ic Instruction cache
# <vector> Identifies the 4-bit vector number for trap instructions
<> identifies an indirect data address referencing memory
<xxx> identifies an absolute address referencing memory
dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Freescale Semiconductor xxxvii
Page 38
Table 2. Notational Conventions (continued)
MCF5329 Reference Manual, Rev 3
Instruction Operand Syntax
Operations
+ Arithmetic addition or postincrement indicator
– Arithmetic subtraction or predecrement indicator
x Arithmetic multiplication
/ Arithmetic division
~ Invert; operand is logically complemented
&Logical AND
| Logical OR
^ Logical exclusive OR
<< Shift left (example: D0 << 3 is shift D0 left 3 bits)
>> Shift right (example: D0 >> 3 is shift D0 right 3 bits)
→ Source operand is moved to destination operand
←→ Two operands are exchanged
sign-extended All bits of the upper portion are made equal to the high-o rder bit of the lower portion
If <condition>
then
<operations>
else
<operations>
{} Optional operation
() Identifies an indirect address
d
n
Address Calculated effective address (pointer)
Bit Bit selection (example: Bit 3 of D0)
lsb Least significant bit (e xample: lsb of D0)
LSB Least sign ificant byte
LSW Least significant word
msb Most significant bit
MSB Most significant byte
MSW Most significant word
Test the condition. If true, the operations after then are performed. If the cond ition is false and the
optional else clause is present, the operations after else are performed. If the condition is false and
else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an
example.
Subfields and Qualifiers
Displacement value, n-bits wide (example: d16 is a 16-bit displacement)
xxxviii Freescale Semiconductor
Page 39
Chapter 1
MCF5329 Reference Manual, Rev 3
Overview
The MCF532x devices are highly-integrated 32-bit microprocessors based on the Version 3 ColdFire
microarchitecture. All MCF532x devices contain a 32-Kbyte internal SRAM, an LCD controller, USB
host and On-the-Go controllers, a two-bank SDR/DDR SDRAM controller, a 16-channel DMA controller ,
up to three UAR Ts, a queued SPI, as well as other peripherals that enable the MCF532x family for use in
general purpose industrial control applications. Optional peripherals include a fast Ethernet controller, a
CAN module, and cryptography hardware accelerators.
This chapter provides an overview of the MCF5327, MCF5328, MCF53281, and MCF5329
microprocessors. It was written from the perspective of the MCF5329 device. See the following section
for a summary of differences between the devices.
1.1 MCF532x Device Configurations
The following table compares the various devices derivatives available:
Ta ble 1-1. MCF5 3 2x Family Configurations
Module MCF5327 MCF5328 MCF53281 MCF5329
ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
Core (System) Clock up to 240 MHz
Peripheral and External Bus Clock
(Core clock ÷ 3)
Perfo rmance (Dhrystone/2.1 MIPS) up to 211
Unified Cache 16 Kbytes
Static RAM (SRAM) 32 Kbytes
LCD Controller • • • •
SDR/DDR SDRAM Controller • • • •
USB 2.0 Host • • • •
USB 2.0 On-the-Go • • • •
UTMI+ Low Pin Interface (ULPI) — • • •
Synchronous Serial Interface (SSI) • • • •
Fast Ethernet Controller (FEC) — • • •
Cryptography Hardware Accelerators — — — •
Embedded Voice-over-IP System Solution — — • —
FlexCAN 2.0B communication module — — • •
••••
up to 80 MHz
Freescale Semiconductor 1-1
Page 40
Overview
MCF5329 Reference Manual, Rev 3
Table 1-1. MCF532x Family Configurations (continued)
Module MCF5327 MCF5328 MCF53281 MCF5329
UARTs 3333
2
C ••••
I
QSPI • • • •
PWM Module • • • •
Real Time Clock • • • •
32-bit DMA Timers 4444
Watchdog Timer (WDT) • • • •
Periodic Interrupt Timers (PIT) 4444
Edge Port Module (EPORT) • • • •
Interrupt Controllers (INTC) 2222
16-channel Direct Memory Access (DMA) • • • •
FlexBus External Interface • • • •
General Purpose I/O Module (GPIO) • • • •
®
JTAG - IEEE
Package 196
1149.1 Test Access Port • • • •
MAPBGA
256
MAPBGA
256
MAPBGA
MAPBGA
256
1.2 Block Diagram
The superset device in the MCF532x family is available in a 256 mold array process ball grid array
(MAPBGA) package. Figure 1-1 shows a top-level block diagram of the MCF5329.
1-2 Freescale Semiconductor
Page 41
Overview
FlexBus
XBS
M2
M1 M0
M5
PWMs, EPORT,
JTAG
TAP
TRST
TCLK
TMS
TDI
TDO
Cache
(1024x32)x4
DMA
UARTs
FlexCAN
I2C
QSPI
DMA Timers
Watchdog, PITs
PADI — Pin Muxing
EXTAL
XTAL
CLKOUT
16 KByte
Chip
External
Selects
(To/From PADI)
FEC
JTAG_EN
RTC
USB Host
M4
LCDC
S4
S7
S1
Reset
PORTS
SDRAMC
SSI
LCDC
USB OTG
RESET
SRAM
(4096x32)x2
32 KByte
PLL
S6
SDRAMC
M6
USB Host
USB OTG
XCVR
ULPI Interface
INTC0
INTC1
RCON
XCVR
V3 ColdFire CPU
DIV EMAC
BDM
(To/From PADI)
RNGA
SKHA
MDHA
Cryptography
Modules
Interface
RSTOUT
EXTAL32K
XTAL32K
(To/From SRAM backdoor)
(To/From XBS)
(To/From PADI)
D[31:0]
A[23:0]
R/W
CS[5:0]
TA
TS
CANTX
CANRX
FEC
DMA Timer
SDRAMC
UART
I
2
C
SDRAMC
QSPI
LCDC
SSI
DREQ
n
DACKn
USB Host
USB OTG
BE/BWE[3:0]
PWM
(To/From PADI)
MCF5329 Reference Manual, Rev 3
1.3 Features
The following is a brief summary of the functional blocks in the MCF5329 superset device.
• Version 3 ColdFire variable-length RISC processor core
Freescale Semiconductor 1-3
— Static operation
— 32-bit address and data path on-chip
— Processor core runs at three times the bus frequency
— Sixteen general-purpose 32-bit data and address registers
— Implements the ColdFire instruction set architecture, ISA_A+, with extensions to support the
user stack pointer register, and 4 new instructions for improved bit processing
— Enhanced multiply-accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit
signal processing algorithms
Figure 1-1. MCF5329 Block Diagram
Page 42
Overview
MCF5329 Reference Manual, Rev 3
— Hardware divide execution unit supporting various 32-bit operations
— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Background debug mode (BDM) revision B+ for in-circuit debugging
— Real time debug support, with nine user-visible hardware breakpoint registers (PC and address
with optional data) that can be configured into a 1- or 2-level trigger
• JTAG support for system level board testing
• On-Chip memories
— 16-Kbyte unified write-back cache
— 32-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters
(DMA, FEC, LCD controller, and USB host and OTG)
• Power management
— Fully static operation with processor wait, doze, and stop modes
— Very rapid response to interrupts from sleep mode
— Global clock disable register to disable clocks to most modules
— Ability to bypass PLL circuitry for low-power and low-speed mode
• Liquid crystal display controller (LCDC)
— Support for single (non-split) screen monochrome/color LCD panels and self-refresh type LCD
panels
— 16 simultaneous gray-scale levels from a palette of 16 for monochrome display
— Maximum supported panel size of 800x600 pixels
— 4(mapped to RGB444)/8(RGB444)/12 bits per pixel (bpp) for passive color panel
— 4(mapped to RGB666)/8(mapped to RGB666)/12(RGB444)/16(RGB565)/18 bpp for TFT
• Embedded voice-over-IP (VoIP) system solution
— Fully integrated and tested software VoIP package
• SDR/DDR SDRAM controller
— Supports a glueless interface to SDR and DDR SDRAM devices
— 16-bit (DDR) or 32-bit (SDR) fixed memory port width
— 16 bytes critical word first burst transfer
— Up to 14 lines of row address, up to 12 (in 32-bit mode) or 13 (in 16-bit bus mode) column
address lines, 2 bits of bank address, and a maximum of two pinned-out chip selects. The
maximum row bits plus column bits equals 24 in 32-bit bus mode or 25 in 16-bit mode.
— Supports up to 256 MBytes of memory per chip select, 512 MBytes total
— Supports page mode to maximize the data rate
— Supports sleep and self-refresh modes
• Universal serial bus (USB) host controller
— Fully compliant with the Universal Serial Bus Specification, Revision 2.0
— Support for full speed (FS = 12 Mbps) and low speed (LS = 1.5 Mbps) with on-chip
1-4 Freescale Semiconductor
Page 43
transceiver in host mode.
MCF5329 Reference Manual, Rev 3
— Support for full speed with on-chip transceiver in device mode.
— Compatible with the Enhanced Host Controller Interface (EHCI) Specification for Universal
Serial Bus, Revision 1.0
— Connects to external 5V power control chip for 100mA to 500mA downstream power
— Uses 60 MHz reference clock based off of the system clock or from an external pin
• Universal serial bus (USB) On-the-Go (OTG) controller
— Fully compliant with the On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a
— Support for full speed and low speed with on-chip FS/LS transceiver.
— Optional UTMI+ Low Pin Interface (ULPI) available on some packages to support high speed
(HS = 480 Mbps) transfers
— Connects to external OTG charge pump and resistor chip via I2C bus
— Embedded host controller compatible with the Enhanced Host Controller Interface (EHCI)
Specification for Universal Serial Bus, Revision 1.0
— Uses 60 MHz reference clock based on the system clock or from an external pin
• Synchronous serial interface (SSI)
— Supports shared (synchronous) transmit and receive sections
— Normal mode operation using frame sync
Overview
— Network mode operation allowing multiple devices to share the port with as many as 32 time
slots
— Gated clock mode operation requiring no frame sync
— Programmable data interface modes such as I2S, LSB, MSB aligned
— Programmable word length up to 24 bits
— AC97 support
• Fast Ethernet controller (FEC)
— 10/100 BaseT/TX capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
— Media independent interface (MII) to external transceiver (PHY)
• Cryptography hardware accelerators
— FIPS-140 compliant random number generator
— MD5 and SHA-160 one-way hash algorithms
— DES, Triple-DES, and AES ciphers
• FlexCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard Data and Remote Frames (up to 109 bits long)
– Extended Data and Remote Frames (up to 127 bits long)
Freescale Semiconductor 1-5
Page 44
Overview
MCF5329 Reference Manual, Rev 3
– 0–8 bytes data length
– Programmable bit rate up to 1 Mbit/sec
— 16 flexible Message Buffers (MBs) of 0–8 bytes data length each, configurable as Rx or Tx, all
supporting standard and extended messages
— Listen-only mode capability
— Content-related addressing
— Three programmable mask registers: global (for MBs 0-13), special for MB14 and special for
MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— Time stamp based on 16-bit free-running timer
— Global network time, synchronized by a specific message
• Three universal asynchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic
— DMA support with separate transmit and receive requests
— Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Flow control support includes request-to-send (UnRTS) and clear-to-send (UnCTS) lines
•I2C module
— Interchip bus interface for EEPROMs, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master or slave modes support multiple masters
— Automatic interrupt generation with programmable level
• Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to three chip selects available
— Master mode operation only with programmable master bit rates
— Up to 16 pre-programmed transfers
• Pulse width modulation (PWM) module
— Four independent PWM channels with programmable period and duty cycle
— Dedicated counter for each PWM channel
— Programmable PWM enable/disable for each channel
— Software selection of PWM duty pulse polarity for each channel
• Real time clock
— Full clock - days, hours, minutes, seconds
— Minute countdown timer with interrupt
— Programmable daily alarm with interrupt
1-6 Freescale Semiconductor
Page 45
— Sampling timer with interrupt
MCF5329 Reference Manual, Rev 3
— Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts
— Operation at 32.768 kHz, 32 kHz, or 38.4 kHz (determined by reference clock crystal)
• Four 32-bit DMA timers
— 12.5-ns resolution at 80 MHz
— Programmable prescaler and sources for clock input, including an external clock option
— Input-capture capability with programmable trigger edge on input pin
— Output-compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts and DMA trigger capability on input capture or output compare
• Software watchdog timer
— 16-bit counter
— Low-power mode support
• Four periodic interrupt timers (PITs)
— 16-bit counter
— Selectable as free running or count down
Overview
• Phase locked loop (PLL)
— 16 MHz reference frequency
— Programmable dithering
• Interrupt controllers (x2)
— Support for up to 126 interrupt sources
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
• DMA controller
— 16 fully programmable channels with 32-byte transfer control
— Data movement via dual-address transfers for 8-, 16-, 32-, and 128-bit data values
— Programmable source and destination addresses, transfer size, and support for enhanced
address modes
— Support for major and minor nested counters with one request and one interrupt per channel
— Support for channel-to-channel linking and scatter/gather for continuous transfers with fixed
priority and round-robin channel arbitration
— External request pins for up to four channels
• FlexBus (external interface)
— Glueless connections to 8-, 16-, or 32-bit external memory devices (SRAM, Flash, ROM, etc.)
— Support for independent primary and secondary wait states per chip select
Freescale Semiconductor 1-7
Page 46
Overview
MCF5329 Reference Manual, Rev 3
— Programmable address setup and hold time with respect to chip select negation, per transfer
direction
— Glueless interface to SRAM devices with or without byte strobe inputs
— Programmable wait state generator
— 32-bit bidirectional data bus and 24-bit address bus
— Up to six chip selects available
— Byte/write enables (byte strobes)
— Ability to boot from external memories that are 8, 16, or 32 bits wide
• Chip configuration module (CCM)
— System configuration during reset
— Unique part identification number and part revision number
• Reset controller
– Separate reset in and reset out signals
– Five reset sources: power-on reset (POR), external, software, watchdog, PLL loss of lock
– Status flag indication of source of last reset
• General purpose I/O interface
— Up to 94 bits of GPIO for the MCF5328, MCF53281, and MCF5329
— Up to 64 bits of GPIO for the MCF5327
— Bit manipulation supported via set/clear functions
— Unused peripheral pins may be used as extra GPIO
— Programmable drive strength or slew rate control for related group of pins
1.3.1 V3 Core Overview
The Version 3 ColdFire processor core consists of two independent pipeline structures decoupled by an
instruction buffer. The four-stage instruction fetch pipeline (IFP) is responsible for instruction-address
generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds
prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes
two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V3 core implements the ColdFire Instruction Set Architecture Revision A+ with added support for a
separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the
core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities.
The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations, with support
for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers and
signed fractional operands, as well as a complete set of instructions to process these data types. The EMAC
provides superb support for execution of DSP operations within the context of a single processor at a
minimal hardware cost.
The core also includes a hardware divide unit which performs a number of integer-divide operations. The
supported divide functions include: 32-bit dividend and 16-bit divisor producing a 16-bit quotient and a
1-8 Freescale Semiconductor
Page 47
Overview
MCF5329 Reference Manual, Rev 3
16-bit remainder, 32-bit dividend and 32-bit divisor producing a 32-bit quotient, and 32-bit dividend and
32-bit divisor producing a 32-bit remainder.
1.3.2 Debug Module
The ColdFire processor core debug interface is provided to support system debugging with low-cost debug
and emulator development tools. Through a standard debug interface, you can access debug information.
This allows the processor and system to be debugged without the need for costly in-circuit emulators.
The on-chip breakpoint resources include a total of nine programmable registers—a pair of upper and
lower address registers, a pair of data registers (a 32-bit data register and a 32-bit data mask register), and
four 32-bit PC registers plus a 32-bit PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor’s supervisor mode programming
model. The breakpoint registers can be configured to generate triggers by combining the address, data, and
PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to
generate a processor halt or initiate a debug interrupt exception.
T o support program trace, the V3 Coldfire core’s debug module provides processor status (PST[3:0]) and
debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured
operand data, and branch target addresses defining processor activity at one-half the CPU’s clock rate.
1.3.3 JTAG
The device supports circuit board test strategies based on the T est Technology Committee of IEEE and the
Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state
controller, an instruction register, and three test registers (a bypass register, a boundary-scan register, and
an ID register). The boundary scan register links the device’s pins into one shift register. Test logic,
implemented using static logic design, is independent of the device system logic.
The implementation can do the following:
• Perform boundary-scan operations to test circuit board electrical continuity
• Sample device system pins during operation and transparently shift out the result in the boundary
scan register
• Bypass the device for a given circuit board test by effectively reducing the boundary-scan register
to a single bit
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
1.3.4 On-chip Memories
1.3.4.1 Cache
The MCF5329 architecture includes a 16-Kbyte unified cache. This four-way, set-associative cache
provides pipelined, single-cycle access on cached instructions and operands.
Freescale Semiconductor 1-9
Page 48
Overview
MCF5329 Reference Manual, Rev 3
As with all ColdFire caches, the cache controller implements a non-lockup, streaming design. The use of
processor-local memories decouples performance from external memory speeds and increases available
bandwidth for external devices or the on-chip DMA module.
The cache implements line-fill buffers to optimize 16-byte line burst accesses. Additionally, the cache
supports copyback, write-through, or cache-inhibited modes. A 4-entry , 32-bit buffer is used for cache line
push operations and can be configured for deferred write buffering in write-through or cache-inhibited
modes.
1.3.4.2 SRAM
The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access
in a single cycle. The memory is ideal for storing critical code or data structures or for use as the system
stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can
quickly service core-initiated accesses or memory-referencing commands from the debug module.
The dual-port SRAM module is also accessible by the DMA, USB host and OTG, LCD, and FEC non-core
bus masters through the crossbar switch. The dual-ported nature of the SRAM makes it ideal for
implementing applications with double-buffer schemes, where the processor and a bus-mastering device
operate in alternate regions of the SRAM to maximize system performance. As an example, system
performance can be increased significantly if Ethernet packets are moved from the FEC into the SRAM
(rather than external memory) prior to any processing.
1.3.5 LCD Controller
The Liquid Crystal Display Controller (LCDC) provides display data for external gray-scale or color LCD
panels. The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color (passive
color or CSTN), and active-matrix color (active color or TFT) LCD panels. The module also provides a
direct interface to Sharp 240x320 HR-TFT panels.
1.3.6 Voice-over-IP (VoIP) System Solution
A fully integrated and tested VoIP software development kit is provided with the MCF53281 device. The
development kit also includes a royalty-free uClinux™ embedded software BSP complete with source
code, GNU tools, kernel, and a broad collection of applications and drivers. This open source BSP is
augmented by a complete take-to-market middleware system that includes certified SIP telephony stack,
audio subsystem with APIs, and advanced device management system.
The product is suitable for applications that require real-time two-way voice communications and control
interfaces, including:
• Building intercom systems
• Building fire and alarm panels
• Emergency panels and poles
• Drive-thru kiosks
• Self-serve kiosks
• Elevator control panels
1-10 Freescale Semiconductor
Page 49
• Gas bar attendant
API API FECSSI
Protocol
Stacks &
Low-Level
Drivers
(TCP/IP)
Speaker
Microphone
Audio
External
Internet
External
Ethernet
PHY (Wired
or Wireless)
Call Control
& Signaling
(SIP)
NRE-free openSIP-based middleware
solution from Arcturus Networks
Hardware Hardware
Binaries supplied by Encore Software
Vocoders
(Audio
Compression)
Supported algorithms: G.168 LEC, AEC,
DTMF, CPT, AGC, G.711, G.729AB,
G.726, CID gen. iLBC, and G.722
Supported applications: caller-ID, call waiting,
hold/retreive, call transfers, conference, hotline,
push-to-call, speed dial, CID privacy,
outgoing call blocking, and call back on busy
RTOS (µClinux)Device Management
Open source Linux available
separately as open source BSP
Management middleware
from Arcturus Networks
MCF53281
Codec
MCF5329 Reference Manual, Rev 3
• Point-of-sale equipment
• Terminal adapter equipment
• Handsets, spearkerphones
• WiFi phones
Figure 1-2 illustrates the placement of the VoIP development kit in an embedded system solution.
Overview
Figure 1-2. MCF53281 Embedded VoIP System Solution
1.3.7 SDR/DDR SDRAM Controller
The SDRAM controller provides a glueless interface to SDR and DDR SDRAM memory devices. The
module uses a 32-bit (for SDR) or a 16-bit (for DDR) memory port and can address up to 512 MB of data
(256 MB per chip select). The controller supports DDR and SDR SDRAM, but both cannot be used at the
same time.
1.3.8 USB Host and OTG Controllers
MCF5329 supports two separate USB 2.0 compliant controllers on chip; a host-only core and an
On-The-Go (or dual-role) core. Both controllers support full-speed (12 Mbps) and/or low-speed
(1.5 Mbps) USB data rates via on-chip transceivers (The USB OTG module in device mode does not
support low-speed). The The USB host module and the USB On-The-Go module’s embedded host
controllers are compliant with the EHCI driver model and support directly connected full-speed and
low-speed devices without the need for UHCI/OHCI companion controllers and associated driver stacks.
Both USB controllers contain chaining direct memory access (DMA) engines that reduce interrupt load on
the CPU, thereby reducing total system bus bandwidth utilization.
The USB controllers are compliant with the following industry standards:
• Universal Serial Bus Specification, Revision 2.0
Freescale Semiconductor 1-11
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Overview
MCF5329 Reference Manual, Rev 3
• On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a
• Enhanced Host Controller Interface (EHCI) Specification for Universal Serial Bus, Revision 1.0
• USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.05
1.3.8.1 USB Host Controller
The USB host controller is configured for a single port, which can connect to downstream hubs to support
connection of up to 127 devices. The host controller also supports connection to external USB power
control devices for downstream power delivery.
1.3.8.2 USB On-the-Go Controller
The second USB controller is programmable to support host, device or On-the-Go operations. The
dual-role feature allows device-to-device connectivity , without the need for a host PC (e.g. digital camera
to photo printer). The OTG module supports high-speed (480 Mbps) operation via an external ULPI
transceiver.
For more details, the following specifications can be found from the ULPI web page at http://www.ulpi.org
• UTMI+ Specification, Revision 1.0
• UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.0
1.3.9 Synchronous Serial Interface (SSI)
The SSI is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices,
including audio codecs, digital signal processors (DSPs), and microprocessors that implement the inter-IC
sound bus standard (I2S) or Intel AC97 standard. SSI typically transfers samples in a periodic manner.
1.3.10 Fast Ethernet Controller (FEC)
The device’s integrated fast Ethernet controller (FEC) performs the full set of IEEE® 802.3/Ethernet
CSMA/CD media access control and channel interface functions. The FEC supports connection and
functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external
transceiver (PHY) to complete the interface to the media.
1.3.11 Cryptography Accelerators
The superset device, MCF532973L, incorporates small, fast, dedicated hardware accelerators for random
number generation, message digest and hashing, and the DES, 3DES, and AES block cipher functions.
This allows for the implementation of common Internet security protocol cryptography operations with
performance well in excess of software-only algorithms. Each of the three accelerator modules contains a
DMA option for transferring data.
1-12 Freescale Semiconductor
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Overview
MCF5329 Reference Manual, Rev 3
1.3.12 FlexCAN
The FlexCAN module implements the 2.0B CAN protocol that is a commonly used industrial control serial
bus that meets the specific requirements of real-time processing, reliable operation in a harsh EMI
environment, cost-effectiveness, and required bandwidth. FlexCAN has 16 message buffers.
1.3.13 UARTs
The device contains three independent, full-duplex UARTs. The three UARTs can be clocked by the
system bus clock, eliminating the need for an externally supplied clock. They can use DMA requests on
transmit-ready and receive-ready as well as interrupt requests for servicing.
1.3.14 I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides an efficient method of data exchange,
minimizing the interconnection between devices. This bus is suitable for applications requiring occasional
communications over a short distance between many devices.
1.3.15 QSPI
The queued serial peripheral interface module provides a high-speed synchronous serial peripheral
interface with queued transfer capability . It allows up to 16 transfers to be queued at once, eliminating CPU
intervention between transfers.
1.3.16 Pulse Width Modulation (PWM) Timer
The pulse width modulation (PWM) timer generates a synchronous series of pulses having programmable
duty cycle. With a suitable low-pass filter, the PWM can be used as a digital-to-analog converter.
The PWM module has four channels, each having a programmable period and duty cycle as well as a
dedicated counter. A flexible clock select scheme allows a total of four dif ferent clock sources to be used
with the counters. Each of the modulators can create independent continuous waveforms with
software-selectable duty rates from 0% to 100%. The PWM outputs can be programmed as left-aligned
outputs or center-aligned outputs
1.3.17 Real Time Clock
The real time clock module has a dedicated 32/32.768/38.4 kHz crystal oscillator and provides the system
with a full clock, capable of interrupting the core once per day, hour, minute, or second. It also contains a
sampling timer which can periodically interrupt the core.
1.3.18 DMA Timers (DTIM0-DTIM3)
There are four independent, DMA-transfer-generating 32-bit timers (DTIM[3:0]). Each timer module
incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be
configured to operate from the system clock or from an external clock source using one of the DTnIN
Freescale Semiconductor 1-13
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Overview
MCF5329 Reference Manual, Rev 3
signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by
a user-programmable 8-bit prescaler that clocks the actual timer counter register (TCRn). Each of these
timers can be configured for input-capture or output-compare mode. By configuring the internal registers,
each timer may be configured to assert an external pin, generate an interrupt on a particular event, or cause
a DMA transfer.
1.3.19 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter
is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown.
1.3.20 Periodic Interrupt Timers (PIT0–PIT3)
The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at regular
intervals with minimal processor intervention. Each timer can count down from the value written in its PIT
modulus register, or it can be a free-running down-counter.
1.3.21 Clock Module and Phase Locked Loop (PLL)
The device contains a 16 MHz crystal oscillator, a phase-locked loop, as well as status and control
registers. The PLL’s output dividers and dithering waveform are register programmable. The system
operates via two main clocks generated by the PLL, typically 240 MHz (core) and 80 MHz (peripherals).
However, two additional clocks are also generated by the PLL for use by the USB and SDRAM controller
modules. To improve noise immunity, the PLL has its own power supply inputs, PLL_VDD and
PLL_VSS. All other circuits are powered by the normal internal supply pins, IVDD (core), EVDD (I/O),
SD_VDD (SDRAM), and VSS.
The PLL circuitry may be bypassed to reduce system speed and decrease power consumption. The external
clock (EXTAL) is used directly, with an optional programmable divider, to produce the internal core and
bus clocks.
1.3.22 Interrupt Controllers
There are two interrupt controllers on the MCF5329, which can support up to 126 interrupt sources. Each
interrupt source has a unique interrupt vector, and all sources of a given controller provide a programmable
level (1-7).
1.3.23 DMA Controller
The implementation of the DMA is targeted towards cost-sensitive applications while providing a high
level of functionality . The DMA executes in parallel with the core, enabling transfers of data between the
memory and peripherals with little intervention from the core, thus increasing system performance, as well
as simplifying software development. The DMA is capable of performing complex data transfers via 16
programmable DMA channels. The hardware microarchitecture includes the DMA engine (which
1-14 Freescale Semiconductor
Page 53
Overview
MCF5329 Reference Manual, Rev 3
performs source/destination address calculations and data movement operations), and a dedicated memory
array containing transfer control descriptors.
1.3.24 Fle xBus External Interface
The FlexBus provides an external interface to 8-, 16-, or 32-bit memory devices (SRAM, flash, ROM,
etc.). The FlexBus’ s internal data lines are s hared with the SDRAM controller. When the SDRAMC is in
DDR mode (DRAMSEL = 0) the data bus signals, D[31:16], are dedicated to the SDRAM controller and
the D[15:0] data bus signals are dedicated to the FlexBus. In SDR mode (DRAMSEL = 1), all 32 data lines
are shared between the FlexBus and SDRAM controller.
Features are available to support external flash modules and secondary wait states on reads and writes and
a signal to support active-low address valid (TS). Six programmable chip-select outputs provide signals to
enable external memory and peripheral circuits, providing all handshaking and timing signals for
automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting
address must be on a boundary that is a multiple of the block size. Each chip select can be configured to
provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data
bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available
for protection from user mode access or read-only access.
1.3.25 Reset Controller Module
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the
system, and keep track of what caused the last reset. There are five sources of reset:
• External
• Power-on reset (POR)
• Watchdog timer
• Phase locked-loop (PLL) loss of lock
• Software
External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also
software-readable status flags indicating the cause of the last reset.
1.3.26 GPIO
Unused bus interface and peripheral pins can be used as discrete general-purpose inputs and outputs. These
are managed by a dedicated GPIO module that logically groups all pins into ports located within a
contiguous block of memory-mapped control registers. Each port has registers that configure, monitor , and
control the port pins. Slew rate control or output pad drive strength control is available on all pins.
Most of the pins associated with the FlexBus interface may be used for several different functions. Their
primary function is to provide an external interface to access off-chip resources. When not used for this,
the pins may be used as general-purpose digital I/O pins.
Freescale Semiconductor 1-15
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Overview
MCF5329 Reference Manual, Rev 3
1.4 Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale
Literature Distribution Center, or through the Freescale World Wide Web address at
http://www.freescale.com/coldfire.
1-16 Freescale Semiconductor
Page 55
Chapter 2
MCF5329 Reference Manual, Rev 3
Signal Descriptions
2.1 Introduction
This chapter describes the external signals on the device. It includes an alphabetical listing of signals that
characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up
resistor should be used.
NOTE
The terms assertion and negation are used to avoid confusion when dealing
with a mixture of active-low and active-high signals. The term asserted
indicates that a signal is active, independent of the voltage level. The term
negated indicates that a signal is inactive.
Active-low signals, such as SD_SRAS and TA, are indicated with an
overbar.
2.2 Signal Properties Summary
The below table lists the signals grouped by functionality.
NOTE
In this table and throughout this document, a single signal within a group is
designated without square brackets (i.e., A23), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality .
Pins that are muxed with GPIO default to their GPIO functionality.
Table 2-1. MCF5327/8/9 Signal Information and Muxing
Signal Name GPIO Alternate 1 Alternate 2
Reset
RESET
RSTOUT — — — O
2
— — — I
MCF53281
MCF5329
256
MAPBGA
Voltage
Domain
MCF5327
196
MAPBGA
J11 N15 N15
P14 P14 P14
1
Dir.
EVDD
EVDD
MCF5328
256
MAPBGA
Freescale Semiconductor 2-1
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Signal Descriptions
MCF5329 Reference Manual, Rev 3
Table 2-1. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
Clock
EXTAL — — — I
2
XTAL
— — — O
EXTAL32K — — — I
XTAL32K — — — O
FB_CLK — — — O
Mode Selection
2
RCON
— — — I
DRAMSEL — — — I
FlexBus
A[23:22] — FB_CS
[5:4] — O
A[21:16] — — — O
A[15:14] — SD_BA[1:0]
A[13:11] — SD_A[13:11]
3
3
—O
—O
1
Dir.
Voltage
EVDD
EVDD
EVDD
EVDD
SDVDD
EVDD
EVDD
SDVDD
SDVDD
SDVDD
SDVDD
Domain
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
L14 P16 P16
K14 N16 N16
M11 P13 P13
N11 R13 R13
L1 T2 T2
M7 M8 M8
G11 H12 H12
B11,C11 C13, D13 C13, D13
B12, A12,
D11, C12,
B13, A13
E13, A14,
B14, C14,
A15, B15
A14, B14 D14, B16 D14, B16
C13, C14,
D12
C15, C16,
D15
MCF53281
MCF5329
256
MAPBGA
E13, A14,
B14, C14,
A15, B15
C15, C16,
D15
A10 — — — O
A[9:0] — SD_A[9:0]
D[31:16] — SD_D[31:16]
D[15:1] — FB_D[31:17]
2
D0
BE/BWE
[3:0] PBE[3:0] SD_DQM[3:0]
— FB_D[16]
3
4
4
4
3
—O
— I/O
— I/O
— I/O
— O
OE PBUSCTL3 — — O
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
D13 D16 D16
D14,
E11–14,
F11–F14,
E14–E16,
F13–F16,
G16– G14
E14–E16,
F13–F16,
G16– G14
G14
H3–H1,
J4–J1, K1,
L4, M2, M3,
N1, N2, P1,
P2, N3
F4–F1,
G5–G2, L5,
N4, P4, M5,
N5, P5, L6
M1–M4,
N1–N4, T3,
P4, R4, T4,
N5, P5, R5,
T5
J3–J1,
K4–K1, L2,
R6, N7, P7,
R7, T7, P8,
R8
M1–M4,
N1–N4, T3,
P4, R4, T4,
N5, P5, R5,
T5
J3–J1,
K4–K1, L2,
R6, N7, P7,
R7, T7, P8,
R8
M6 T8 T8
H4, P3, G1, M4L4, P6, L3, N6L4, P6, L3,
N6
P6 R9 R9
2-2 Freescale Semiconductor
Page 57
Table 2-1. MCF5327/8/9 Signal Information and Muxing (continued)
MCF5329 Reference Manual, Rev 3
Signal Descriptions
Signal Name GPIO Alternate 1 Alternate 2
2
TA
R/W
PBUSCTL2 — — I
PBUSCTL1 — — O
TS PBUSCTL0 DACK0 —O
1
Dir.
Voltage
SDVDD
SDVDD
SDVDD
Chip Selects
FB_CS[5:4] PCS[5:4] — — O
FB_CS[3:1] PCS[3:1] O
FB_CS0
———O
SDVDD
SDVDD
SDVDD
SDRAM Controller
SD_A10 — — — O
SD_CKE — — — O
SD_CLK — — — O
SD_CLK ———O
SD_CS1 ———O
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
Domain
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
G13 G13 G13
N6 N8 N8
D2 H4 H4
— B13, A13 B13, A13
A11, D10,
C10
A12, B12,
C12
B10 D12 D12
L2 P2 P2
E1 H2 H2
K3 R1 R1
K2 R2 R2
— J4 J4
MCF53281
MCF5329
256
MAPBGA
A12, B12,
C12
SD_CS0 ———O
SD_DQS3 — — — O
SD_DQS2 — — — O
SD_SCAS ———O
SD_SRAS ———O
SD_SDR_DQS — — — O
SD_WE ———O
External Interrupts Port
IRQ7
IRQ6
2
2
PIRQ7
PIRQ6
2
2
— — I
USBHOST_
— I
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
5
EVDD
EVDD
VBUS_EN
IRQ5
2
PIRQ5
2
USBHOST_
— I
EVDD
VBUS_OC
IRQ4
IRQ3
IRQ2
IRQ1
2
2
2
2
PIRQ4
PIRQ3
PIRQ2
PIRQ1
2
2
2
2
SSI_MCLK — I
— — I
USB_CLKIN — I
DREQ1
2
SSI_CLKIN I
EVDD
EVDD
EVDD
EVDD
E2 H1 H1
H5 L1 L1
K6 T6 T6
L3 P3 P3
M1 R3 R3
K4 P1 P1
D1 H3 H3
J13 J13 J13
— J14 J14
— J15 J15
L13 J16 J16
M14 K14 K14
M13 K15 K15
N13 K16 K16
Freescale Semiconductor 2-3
Page 58
Signal Descriptions
MCF5329 Reference Manual, Rev 3
Table 2-1. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
FEC
FEC_MDC PFECI2C3 I2C_SCL
FEC_MDIO PFECI2C2 I2C_SDA
2
2
— O
— I/O
FEC_TXCLK PFECH7 — — I
FEC_TXEN PFECH6 — — O
FEC_TXD0 PFECH5 ULPI_DATA0 — O
FEC_COL PFECH4 ULPI_CLK — I
FEC_RXCLK PFECH3 ULPI_NXT — I
FEC_RXDV PFECH2 ULPI_STP — I
FEC_RXD0 PFECH1 ULPI_DATA4 — I
FEC_CRS PFECH0 ULPI_DIR — I
FEC_TXD[3:1] PFECL[7:5] ULPI_DATA[3:1] — O
FEC_TXER PFECL4 — — O
MCF53281
MCF5329
256
MAPBGA
Voltage
Domain
MCF5327
196
MAPBGA
— C1 C1
— C2 C2
— A2 A2
— B2 B2
— E4 E4
— A8 A8
— C8 C8
— D8 D8
— C6 C6
— B8 B8
— D3–D1 D3–D1
— B1 B1
1
Dir.
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
MCF5328
256
MAPBGA
FEC_RXD[3:1] PFECL[3:1] ULPI_DATA[7:5] — I
FEC_RXER PFECL0 — — I
LCD Controller
LCD_D17 PLCDDH1 CANTX — O
LCD_D16 PLCDDH0 CANRX — O
LCD_D17 PLCDDH1 — — O
LCD_D16 PLCDDH0 — — O
LCD_D15 PLCDDM7 — — O
LCD_D14 PLCDDM6 — — O
LCD_D13 PLCDDM5 — — O
LCD_D12 PLCDDM4 — — O
LCD_D[11:8] PLCDDM[3:0] — — O
LCD_D7 PLCDDL7 — — O
LCD_D6 PLCDDL6 — — O
LCD_D5 PLCDDL5 — — O
LCD_D4 PLCDDL4 — — O
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
— E7, A6, B6 E7, A6, B6
— D4 D4
— — C9
— — D9
A6 C9 —
B6 D9 —
C6 A7 A7
D6 B7 B7
A5 C7 C7
B5 D7 D7
C5, D5, A4, B4D6, E6, A5, B5D6, E6, A5,
B5
C4 C5 C5
B3 D5 D5
A3 A4 A4
A2 A3 A3
2-4 Freescale Semiconductor
Page 59
Table 2-1. MCF5327/8/9 Signal Information and Muxing (continued)
MCF5329 Reference Manual, Rev 3
Signal Descriptions
Signal Name GPIO Alternate 1 Alternate 2
LCD_D[3:0] PLCDDL[3:0] — — O
LCD_ACD/
PLCDCTLH0 — — O
LCD_OE
LCD_CLS PLCDCTLL7 — — O
LCD_CONTRAST PLCDCTLL6 — — O
LCD_FLM/
PLCDCTLL5 — — O
LCD_VSYNC
LCD_LP/
PLCDCTLL4 — — O
LCD_HSYNC
LCD_LSCLK PLCDCTLL3 — — O
LCD_PS PLCDCTLL2 — — O
LCD_REV PLCDCTLL1 — — O
LCD_SPL_SPR PLCDCTLL0 — — O
USB Host & USB On-the-Go
1
Dir.
EVDD
MCF5327
196
MAPBGA
Voltage
Domain
D4, C3, D3, B2B4, C4, B3, C3B4, C4, B3,
MCF5328
256
MAPBGA
MCF53281
MCF5329
256
MAPBGA
C3
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
D7 B9 B9
C7 A9 A9
B7 D10 D10
A7 C10 C10
A8 B10 B10
B8 A10 A10
C8 A11 A11
D8 B11 B11
B9 C11 C11
USBOTG_M — — — I/O
USBOTG_P — — — I/O
USBHOST_M — — — I/O
USBHOST_P — — — I/O
FlexCAN (MCF53281 & MCF5329 only)
CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing:
I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX.
PWM
PWM7 PPWM7 — — I/O
PWM5 PPWM5 — — I/O
PWM3 PPWM3 DT3OUT DT3IN I/O
PWM1 PPWM1 DT2OUT DT2IN I/O
SSI
SSI_MCLK PSSI4 — — I/O
USB
VDD
USB
VDD
USB
VDD
USB
VDD
EVDD
EVDD
EVDD
EVDD
EVDD
G12 L15 L15
H13 L16 L16
K13 M15 M15
J12 M16 M16
— H13 H13
— H14 H14
H14 H15 H15
J14 H16 H16
— G4 G4
SSI_BCLK PSSI3 U2CTS PWM7 I/O
Freescale Semiconductor 2-5
EVDD
— F4 F4
Page 60
Signal Descriptions
MCF5329 Reference Manual, Rev 3
Table 2-1. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2
SSI_FS PSSI2 U2RTS PWM5 I/O
SSI_RXD
SSI_TXD
SSI_RXD
SSI_TXD
2
2
2
2
PSSI1 U2RXD CANRX I
PSSI0 U2TXD CANTX O
PSSI1 U2RXD — I
PSSI0 U2TXD — O
Voltage
Domain
MCF5327
196
MAPBGA
— G3 G3
— — G2
— — G1
— G2 —
— G1 —
1
Dir.
EVDD
EVDD
EVDD
EVDD
EVDD
MCF5328
MAPBGA
I2C
I2C_SCL
I2C_SDA
I2C_SCL
I2C_SDA
2
2
2
2
PFECI2C1 CANTX U2TXD I/O
PFECI2C0 CANRX U2RXD I/O
PFECI2C1 — U2TXD I/O
PFECI2C0 — U2RXD I/O
EVDD
EVDD
EVDD
EVDD
— — F3
— — F2
E3 F3 —
E4 F2 —
DMA
DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:
TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.
256
MCF53281
MCF5329
256
MAPBGA
QSPI
QSPI_CS2 PQSPI5 U2RTS — O
QSPI_CS1 PQSPI4 PWM7 USBOTG_
PU_EN
QSPI_CS0 PQSPI3 PWM5 — O
QSPI_CLK PQSPI2 I2C_SCL
2
— O
QSPI_DIN PQSPI1 U2CTS — I
QSPI_DOUT PQSPI0 I2C_SDA — O
UARTs
U1CTS PUARTL7 SSI_BCLK — I
U1RTS PUARTL6 SSI_FS — O
U1TXD PUARTL5 SSI_TXD
U1RXD PUARTL4 SSI_RXD
2
2
— O
— I
U0CTS PUARTL3 — — I
U0RTS PUARTL2 — — O
U0TXD PUARTL1 — — O
U0RXD PUARTL0 — — I
EVDD
EVDD
O
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
P10 T12 T12
L11 T13 T13
— P11 P11
N10 R12 R12
L10 N12 N12
M10 P12 P12
C9 D11 D11
D9 E10 E10
A9 E11 E11
A10 E12 E12
P13 R15 R15
N12 T15 T15
P12 T14 T14
P11 R14 R14
Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins.
2-6 Freescale Semiconductor
Page 61
Table 2-1. MCF5327/8/9 Signal Information and Muxing (continued)
MCF5329 Reference Manual, Rev 3
Signal Descriptions
Signal Name GPIO Alternate 1 Alternate 2
DMA Timers
DT3IN PTIMER3 DT3OUT U2RXD I
DT2IN PTIMER2 DT2OUT U2TXD I
DT1IN PTIMER1 DT1OUT DACK1 I
DT0IN PTIMER0 DT0OUT DREQ0
JTAG_EN
DSCLK — TRST
PSTCLK — TCLK
7
— — — I
BKPT — TMS
DSI — TDI
2
2
2
2
2
BDM/JTAG
— I
— O
— I
— I
6
DSO — TDO — O
DDATA[3:0] — — — O
1
Dir.
EVDD
EVDD
EVDD
EVDD
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
MCF5327
196
MAPBGA
Voltage
Domain
C1 F1 F1
B1 E1 E1
A1 E2 E2
C2 E3 E3
L12 M13 M13
N14 P15 P15
L7 T9 T9
M12 R16 R16
K12 N14 N14
N9 N11 N11
N7, P7, L8, M8N9, P9,
MCF5328
256
MAPBGA
N10, P10
MCF53281
MCF5329
256
MAPBGA
N9, P9,
N10, P10
PST[3:0] — — — O
EVDD
N8, P8, L9, M9R10, T10,
R11, T11
R10, T10,
R11, T11
Test
7
TEST
PLL_TEST
— — — I
8
— — — I
EVDD
EVDD
E10 A16 A16
— N13 N13
Power Supplies
EVDD — — — — — E6, E7,
F5–F7, H9,
J8, J9, K8,
K9, K11
E8, F5–F8,
G5, G6, H5,
H6, J11,
K11, K12,
L9–L11, M9,
E8, F5–F8,
G5, G6, H5,
H6, J11,
K11, K12,
L9–L11, M9,
M10
IVDD — — — — — E5, K5, K10,
J10
E5, G12,
M5, M11,
E5, G12,
M5, M11,
M12
PLL_VDD — — — — — H10 J12 J12
SD_VDD — — — — — E8, E9,
F8–F10,
J5–J7, K7
E9, F9–F11,
G11, H11,
J5, J6, K5,
K6, L5–L8,
M6, M7
E9, F9–F11,
G11, H11,
J5, J6, K5,
K6, L5–L8,
M6, M7
M10
M12
Freescale Semiconductor 2-7
Page 62
Signal Descriptions
MCF5329 Reference Manual, Rev 3
Table 2-1. MCF5327/8/9 Signal Information and Muxing (continued)
MCF53281
MCF5329
256
MAPBGA
Signal Name GPIO Alternate 1 Alternate 2
Voltage
Domain
MCF5327
196
MAPBGA
1
Dir.
MCF5328
256
MAPBGA
USB_VDD — — — — — G10 L14 L14
VSS — — — — — G6–G9,
H6–H8, P9
G7–G10,
H7–H10,
J7–10,
K7–K10,
L12, L13
G7–G10,
H7–H10,
J7–10,
K7–K10,
L12, L13
PLL_VSS — — — — — H11 K13 K13
USB_VSS — — — — — H12 M14 M14
1
Refers to pin’s primary function.
2
Pull-up enabled internally on this signal for this mode.
3
The SDRAM functions of these signals are not programmable by the user. They are dynamically switched b y the processor
when accessing SDRAM memory space and are included he re for completeness.
4
Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating
the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.
5
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate
functions.
6
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for
assigning these pins.
7
Pull-down enabled internally on this signal for this mode.
8
Must be left floating for proper operation of the PLL.
2.2.1 Internal Pull-up/Pull-downs Resistors
The following table summarizes which external signals contain internal pull-up or pull-down resistors.
Table 2-2. Internal Pull-up/down Resistors
Pin Name Pull-Up Pull-Down Comment
RESET
TEST x Always, except JTAG mode
RCON x Always, except JTAG mode
XTAL x When not in crystal oscillator mode (intended for
IRQ
[7:2] x IRQ mode only
IRQ1 xIRQ and DREQ modes
TA
QSPI_DOUT x I2C mode only (I2C_SDA)
2-8 Freescale Semiconductor
x Always, except JTAG mode
factory test)
x Only when used as TA
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Signal Descriptions
MCF5329 Reference Manual, Rev 3
Table 2-2. Internal Pull-up/down Resistors (continued)
Pin Name Pull-Up Pull-Down Comment
QSPI_CLK x I2C mode only (I2C_SCL)
2
FEC_MDIO x I
FEC_MDC x I
I2C_SDA x I2C mode only (I2C_SDA)
I2C_SCL x I2C mode only (I2C_SCL)
DT0IN x When used as DREQ0
U1RXD x x When used as SSI_RXD, configured by the MISCCR
U1TXD x x When used as SSI_TXD, configured by the MISCCR
SSI_RXD x x SSI mode only . Configured b y the MISCCR register in
SSI_TXD x x SSI mode only. Configured by the MISCCR register in
C mode only (I2C_SDA)
2
C mode only (I2C_SCL)
register in the CCM
register in the CCM
the CCM
the CCM
JTAG_EN x
TDI x JTAG mode only
TMS x JTAG mode only
TRST
TCLK x JTAG mode only
D0 x During reset only
x JTAG mode only
2.3 Signal Primary Functions
2.3.1 Reset Signals
Table 2-3 describes signals that are used to reset the chip or as a reset indication.
Table 2-3. Reset Sign als
Signal Name Abbreviation Function I/O
Reset In RESET Primary reset input to the device. Asserting RESET immediately resets
the core and peripherals, which stay in reset until RESET
Reset Out RSTOUT Reset output (RSTOUT) is an indicator that the chip is in reset.
RSTOUT
internal or external reset.
is driven low for 512 FB_CLK clock cycles in response to any
is negated.
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2.3.2 PLL and Clock Signals
Table 2-4 describes signals that are used to support the on-chip clock generation circuitry.
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MCF5329 Reference Manual, Rev 3
Signal Name Abbreviation Function I/O
Table 2-4. PLL and Clock Signals
External Clock In EXTAL Always driven by an external clock input except when used as a
connection to the external crystal when the internal oscillator circuit is
used. The clock source may be configured during reset by asserting
. See Chapter 9, “Chip Configuration Module (CCM)” for more
RCON
details.
Crystal XTAL Used as a connection to the external crystal when the internal
oscillator circuit is used to drive the crystal.
32 kHz External Clock InEXTAL32K 32 kHz crystal input clock for the real time clock. I
32 kHz Crystal XTAL32K Oscillator output to EXTAL 32kHz crystal. O
USB Clock In USBCLKIN Allows the user to drive the reference clock to the USB modules,
instead of the clock being generated internally by the PLL. This pin
should only be driven with a 60 MHz clock. When using the ULPI USB
interface , this pin becomes the ULPI input clock.
SSI Clock In SSICLKIN Allows the user to drive a specific clock frequency to the SSI module,
instead of using the internally generated clock.
FlexBus Clock Out FB_CLK Reflects the internal bus clock (or one-third the core/system clock).
)
(f
sys/3
2.3.3 Mode Selection
Table 2-5 describes signals used in mode selection.
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Table 2-5. Mode Selection Signals
Signal Name Abbreviation Function I/O
Reset Configuration RCON Indicates whether the external D[15:0] pi n states affect chip
configuration at reset.
SDR/DDR SDRAM
Select
DRAMSEL Controls whether certain pins act as FlexBus or SDRAMC signals.
When asserted, D[31:0] dynamically switches between SDR data and
FlexBus data. When negated, D[31:16] are dedicated for DDR data
while D[15:0] are dedicated for FlexBus data.
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Page 65
2.3.4 FlexBus Signals
MCF5329 Reference Manual, Rev 3
Table 2-6 describes signals that are used for doing transactions on the external bus.
Table 2-6. FlexBus Si gnals
Signal Name Abbreviation Function I/O
Signal Descriptions
Address Bus A[23:0] The 24 dedicated address signals define the address of external byte,
word, and longword accesses. These three-state outputs are the 24
lsbs of the internal 32-bit address bus and multiplexed with the
SDRAM controller row and column addresses.
Data Bus D[31:0] These three-state bidirectional signals provide the general purpose
data path between the processor and all other devices.
Byte Enables BW/BWE
Output Enable OE
[3:0] Define the flow of data on the data bus. During peripheral accesses,
these output signals indicate that data is to be latched or driven onto
a byte of the data when driven low. The BE/BWE[3:0] signals are
asserted only to the memory bytes used during a read or write access.
BE/BWE
and BE/BWE3 controls access to the least significant byte lane of
data.
For SRAM or Flash devices , the BE/BWE
connected to individual byte strobe signals.
The BE/BWE
peripherals, but not to on-chip SRAM or cache. During SDRAM
accesses, these signals act as the SD_DQM[3:0] signals, which
indicate a byte transfer between SDRAM and the chip when driven
high. See Table 2-7 for more details.
Indicates when an external device can drive data during external read
cycles.
0 controls access to the most significant byte lane of data,
n outputs should be
n signals are asserted during accesses to on-chip
O
I/O
O
O
Transfer Acknowledge TA Indicates that the external data transfer is complete. During a read
cycle, when the processor recognizes TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes TA
Read/Write R/W
Transfer Start TS
Chip Selects FB_CS[5:0] These output signals select external devices for external bus
Indicates the direction of the data transfer on the bus for SRAM (R/W )
accesses. A logic 1 indicates a read from a slave de vice and a logic 0
indicates a write to a slave device.
Bus control output signal indicating the start of a transfer. O
transactions.
, the bus cycle is terminated.
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Signal Descriptions
MCF5329 Reference Manual, Rev 3
2.3.5 SDRAM Controller Signals
Table 2-7 describes signals that are used for SDRAM accesses.
Table 2-7. SDRAM Controller Signals
Signal Name Abbreviation Function I/O
SDRAM A10 SD_A10 Bit 10 of the SDRAM Address bus O
SDRAM Clock Enable SD_CKE SDRAM clock enable. O
DDR SDRAM Clock SD_CLK Output clock for DDR SDRAM. O
DDR SDRAM Clock SD_CLK Inverted output clock for DDR SDRAM. O
SDRAM Chip Selects SD_CS[1:0] SDRAM chip select signals. O
DDR SDRAM Data Strobes SD_DQS[3:2] Indicates when valid data is on the data bus. SD_DQS1 is tied to
SD_DQS3 and SD_DQS0 is tied to SD_DQS2 internally.
SDR SDRAM Write Data
Byte Mask
SDRAM Synchronous
Column Address Strobe
SDRAM Synchronous Row
Address Strobe
SDR SDRAM Data Strobe SD_SDRDQS Generated by the memory controller in SDR mode, to mimic the DQS
SDRAM Write Enable SD_WE
SD_DQM[3:0] Used to determine which byte lanes of the data bus should be latched
during a write cycle. These pins are multiplexed with the BE/BWE
pins.
The SD_DQMn should be connected to individual SDRAM DQM
signals. Most SDRAMs associate DQM3 with the MSB, in which case
SD_DQM3 should be connected to the SDRAM's DQM3 input.
SD_SCAS
SD_SRAS SDRAM synchronous row address strobe. O
SDRAM synchronous column address strobe. O
generated by DDR memories during reads. It is routed out and
connected back to SD_DQS inputs.
Indicates the direction of the data transfer on the bus for SDRAM
accesses. A logic 1 indicates a read from a slave device and a logic 0
indicates a write to a slave device.
2.3.6 External Interrupt Signals
Table 2-8 describes the external interrupt signals.
I/O
O
n
O
O
Signal Name Abbreviation Function I/O
External Interrupts IRQ[7:1] External interrupt sources. I
2.3.7 DMA Signals
Table 2-9 describes the external DMA signals.
2-12 Freescale Semiconductor
Table 2-8. External Interrupt Signals
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Signal Descriptions
MCF5329 Reference Manual, Rev 3
Table 2-9. DMA Signals
Signal Name Abbreviation Function I/O
DMA Request DREQ
DMA Acknowledge DACK[1:0] Active low external DMA acknowledge lines. O
[1:0] Active low external DMA request lines. I
2.3.8 LCD Controller Signals
Table 2-9 describes the LCD controller signals.
Table 2-10. LC D Sign a ls
Signal Name Abbreviation Function I/O
Line Data LCD_D[17:0] LCD data bus. O
First Line Marker/
Vertical Sync
Line Pulse/
Horizontal Sync
Shift Clock LCD_LSCLK Clock for latching data into the display driver’s interna l shift register. O
Alt. Crystal Direction/
Output Enable
Contrast LCD_CONTRAST Controls the LCD bias voltage for contrast control. O
Power Save LCD_PS Controls signal output for source driver (Sharp HR-TFT 240x320 panels
LCD_FLM/
LCD_VSYNC
LCD_LP/
LCD_HSYNC
LCD_ACD/
LCD_OE
Passive matrix: First line marker
Active matrix: Vertical sync pulse. Indicates start of next frame.
Passive matrix: Line pulse
Active matrix: Horizontal sync pulse. Indicates start of next line.
Passive matrix: Alternate crystal direction
Active matrix: Output enable to enable data to be shifted onto the display.
only)
O
O
O
O
Gate Driver Clock
Signal
Reverse Control LCD_REV Signal for common electrode driving signal preparation (Sharp HR-TFT
Sampling Start Signal LCD_SPL_SPR Sets the horizontal scan direction (Sharp HR-TFT 240x3 20 panels only). O
LCD_CLS Start signal output for gate driver, inverted version of LCD_PS (Sharp
HR-TFT 240x320 panels only).
240x320 panels only).
2.3.9 Ethernet Module (FEC ) Signals
The following signals are used by the Ethernet module for data and clock signals.
Table 2-11. Ethernet Module (FEC) Signals
Signal Name Ab breviation Function I/O
Management Data FEC_MDIO Transfers control information between the external PHY and the
media-access controller. Data is synchronous to FEC_MDC. Applies
to MII mode operation. This signal is an input after reset. When the
FEC is operated in 10Mbps 7-wire interface mode, this signal should
be connected to VSS.
Management Data
Clock
FEC_MDC In Ethernet mode, FEC_MDC is an output clock which provides a
timing reference to the PHY for data transfers on the FEC_MDIO
signal. Applies to MII mode operation.
O
O
I/O
O
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MCF5329 Reference Manual, Rev 3
Signal Name Ab breviation Function I/O
Table 2-11. Ethernet Module (FEC) Signals (continued)
Collision FEC_COL Asserted upon detection of a collision and remains asserted while the
collision persists. This signal is not defined for full-duplex mode.
Carrier Receive Sense FEC_CRS When asserted, indicates that transmit or receive medium is not idle.
Applies to MII mode operation.
Transmit Clock FEC_TXCLK Input clock which provides a timing reference for FEC_TXEN,
FEC_TXD[3:0] and FEC_TXER
Transmit Enable FEC_TXEN Indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the
first FEC_TXCLK following the final nibble of the frame.
Transmit Data 0 FEC_TXD0 FEC_TXD0 is the serial output Ethernet data and is only valid during
the assertion of FEC_TXEN. This signal is used for 10-Mbps Ethernet
data. It is also used for MII mode data in conjunction with
FEC_TXD[3:1].
Transmit Data 1–3 FEC_TXD[3:1] In Ethernet mode, these pins contain the serial output Ethernet data
and are valid only during assertion of FEC_TXEN in MII mode.
T ransmit Error FEC_TXER In Ethernet mode, when FEC_TXER is asserted for one or more clock
cycles while FEC_TXEN is also asserted, the PHY sends one or more
illegal symbols. FEC_TXER has no effect at 10 Mbps or when
FEC_TXEN is negated. Applies to MII mode operation.
Receive Clock FEC_RXCLK Provides a timing reference for FEC_RXDV, FEC_RXD[3:0], and
FEC_RXER.
Receive Data Valid FEC_RXDV Asserting the FEC_RXDV input indicates that the PHY has valid
nibbles present on the MII. FEC_RXD V should remain asserted from
the first recovered nibble of the frame through to the last nibble.
Assertion of FEC_RXDV must start no later than the SFD and exclude
any EOF.
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Receive Data 0 FEC_RXD0 FEC_RXD0 is the Ethernet input data transferred f rom the PHY to the
media-access controller when FEC_RXDV is asserted. This signal is
used for 10-Mbps Ethernet data. This signal is also used for MII mode
Ethernet data in conjunction with FEC_RXD[3:1].
Receive Data 1–3 FEC_RXD[3:1] In Ethernet mode, these pins contain the Ethernet input data
transferred from the PHY to the media access controller when
FEC_RXDV is asserted in MII mode operation.
Receive Error FEC_RXER In Ethernet mode, FEC_RXER—when asserted with
FEC_RXDV—indicates that the PHY has detected an error in the
current frame. When FEC_RXDV is not asserted FEC_RXER has no
effect. Applies to MII mode operation.
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2.3.10 I2C I/O Signals
Table 2-12 describes the I2C serial interface module signals.
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Table 2-12. I2C I/O Signals
MCF5329 Reference Manual, Rev 3
Signal Name Abbreviation Function I/O
2
Serial Clock I2C_SCL Open-drain clock signal for the I
module when the bus is in the master mode or it becomes the clock
input when the I
Serial Data I2C_SDA Open-drain signal that serves as the data input/output for the I
interface.
2
C is in the slave mode.
C interface. It is driven by the I2C
2
2.3.11 FlexCAN Signals
Table 2-13 describes the FlexCAN module signals.
Table 2-13. FlexCAN Signals
Signal Name Abbreviation Function I/O
FlexCAN Transmit CANTX Controller area network transmit data output. O
FlexCAN Receive CANRX Controller area network receive data input. I
2.3.12 Queued Serial Peripheral Interface (QSPI)
Signal Descriptions
I/O
C
I/O
Table 2-14 describes QSPI signals.
Table 2-14. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name Abbreviation Function I/O
QSPI Syncrhonous
Serial Output
QSPI Synchronous
Serial Data Input
QSPI Serial Clock QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of
Synchronous Peripheral
Chip Selects
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK. Each byte is sent
msb first.
QSPI_DIN Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK. Each byte is
written to RAM lsb first.
QSPI_CLK are programmable. The output frequency is programmed
according to the following formula, in which n can be any value
between 1 and 255:
SPI_CLK = f
QSPI_CS[2:0] Provide QSPI peripheral chip selects that can be programmed to be
active high or low.
sys/3
÷ (2 × n)
2.3.13 Synchronous Serial Interface (SSI) Signals
The SSI module uses the signals in this section.
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Signal Descriptions
MCF5329 Reference Manual, Rev 3
Signal Name Abbreviation Function I/O
Table 2-15. SSI Module Signals
Serial Clock SSI_CLK Used by the receive and transmit blocks. In gated clock mode,
SSI_CLK is only valid during the transmission of data, otherwise it is
pulled to an inactive state.
Serial Frame Sync SSI_FS Used by transmitter/receiver to synchronize the transfer of data. In
gated clock mode, this signal is not used. When configured as an
input, the external device should drive SSI_FS during the riding edge
of SSI_CLK.
Serial Receive Data SSI_RXD Receives data into the receive data shift register I
Serial Transmit Data SSI_TXD Transmits data from the serial transmit shift register. O
I/O
I/O
2.3.14 Universal Serial Bus (USB) Signals
The following table describes the signals for the USB module.
Table 2-16. USB Module Signals
Signal Name Abbreviation Function I/O
On-the-Go D- USBOTG_DM D- output of the dual-speed transceiver for the On-the-Go module. O
On-the-Go D+ USBOTG_DP D+ output of the dual-speed transceiver for the On-the-Go module. O
On-the-Go Enable USBOTG_PU_EN Enables an external pull-up on the USBOTG_DP line. This signal is
controlled by the UOCSR[BVLD] bit.
Host D- USBHOST_DM D- output of the dual-speed transceiver for the USB Host module. O
O
Host D+ USBHOST_DP D+ output of the dual-speed transceiver for the USB Host module. O
Host VBUS Enable USBHOST_VBUS_EN Enables off-chip VBUS charge pump O
Host VBUS over-current USBHOST_VBUS_OC Indicates to the processor that a short has occurred on the USB
data bus.
ULPI Data Bus ULPI_DATA[7:0] Data bus for the ULPI interface, which is synchronous to
USBCLKIN/ULPI_CLK.
ULPI Data Bus
Direction
ULPI Stop Data ULPI_STP Synchronous to USBCLKIN
ULPI Next Data ULPI_NXT Synchronous to USBCLKIN
ULPI On-Chip Clock ULPI_CLK 60MHz clock which is generated on-chip O
USB Off-Chip Clock USBCLKIN See Section 2.3.2, “PLL and Clock Signals” I
ULPI_DIR Indicates direction of the ULPI data bus., which is synchronous to
USBCLKIN/ULPI_CLK
2.3.15 Pulse Width Modulation (PWM) Module Signals
The following table describes the signals for the PWM module.
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Signal Descriptions
MCF5329 Reference Manual, Rev 3
Table 2-17. PWM Module Signals
Signal Name Abbreviation Function I/O
PWM7 Output PWM7 Wavef orm output for channel 7 of the PWM module. Also functions as
an input for the emergency shutdown feature of the PWM.
PWM[5,3,1,0] Outputs PWM[5,3,1,0] Waveform output for channels 5, 3, 1, and 0 respectively. O
I/O
2.3.16 UART Module Signals
Table 2-18 describes the signals of the three UAR T modules, where n=0–2. Baud rate clock inputs are not
supported.
Table 2-18. UART Module Signals
Signal Name Abbreviation Function I/O
Transmit Serial Data
Output
Receive Serial Data
Input
Clear-to-Send U
Request-to-Send UnRTS Automatic request-to-send outputs from the UART modules. They ma y
UnTXD T ransmitter serial data outputs. Data is shifted out lsb first on this pin at
the falling edge of the serial clock source. The output is held high when
the transmitter is disabled, idle, or in local loopback mode.
UnRXD Receiver serial data inputs. Data is sampled on the rising edge of the
serial clock source lsb first. When the UART clock is stopped for
power-down mode, any transition on this pin restarts it.
nCTS Indicates that the UART modules can begin data transmission I
also be asserted and negated as a functio n of the receive FIFO level.
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2.3.17 DMA Timer Signals
Table 2-19 describes the signals of the four DMA timer modules, where n=0–3.
Table 2-19. DMA Timer Signals
Signal Name Abbreviation Function I/O
DMA Timer n Input DTnIN Can be programmed to cause events to occur in the respective timer .
It can clock the event counter or provide a trigger to the timer value
capture logic.
DMA Timer n Output DTnOUT The output from the respective timer. O
I
2.3.18 Debug Support Signals
These signals are used as the interface to the on-chip JT AG controller and the BDM logic. Pin functionality
between JTAG and BDM is dependent upon the JTAG_EN pin.
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Signal Descriptions
MCF5329 Reference Manual, Rev 3
Signal Name Abbreviation Function I/O
Table 2-20. Debug Support Signals
Test Reset TRST
This active-low signal is used to initialize the JTAG logic
asynchronously.
Test Clock TCLK Used to synchronize the JTAG logic. I
Test Mode Select TMS Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
T est Data Input TDI Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
T est Data Output TDO Serial output for test instructions and data. TDO is three-stateable and
is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
Development Serial
Clock
Breakpoint BKPT
Development Serial
Input
Development Serial
Output
DSCLK Clocks the serial communication port to the BDM module during
packet transfers.
Used to request a manual breakpoint. I
DSI This internally-synchronized signal provides data input for the serial
communication port to the BDM module.
DSO This internally-registered signal provides serial output communication
for BDM module responses.
Processor Status Clock PSTCLK Used by the development system to known when to sample the
DDATA and PST signals.
Debug Data DDAT A[3:0] Display captured processor data and breakpoint status. The PSTCLK
signal can be used by the development system to know when to
sample DDATA[3:0].
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Processor Status
Outputs
PST[3:0] Indicate core status, as shown in Table 2-21. Debug mode timing is
synchronous with the processor clock; status is unrelated to the
current bus transfer. The PSTCLK signal can be used by the
development system to know when to sample PST[3:0].
Table 2-21. Processor Status
PST[3:0] Processor Status
0000 Continue execution
0001 Begin execution of one instruction
0010 Reserved
0011 Entry into user mode
0100 Begin execution of PULSE and WDDATA instructions
0101 Begin execution of taken branch
0110 Reserved
0111 Begin execution of RTE instruction
1000 Begin one-byte transfer on DDATA
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Table 2-21. Processor Status (continued)
MCF5329 Reference Manual, Rev 3
PST[3:0] Processor Status
1001 Begin two-byte transfer on DDATA
1010 Begin three-byte transfer on DDATA
1011 Begin four-byte transfer on DDATA
1100 Exception processing
1101 Reserved
1110 Processor is stopped
1111 Processor is halted
2.3.19 Test Signals
Table 2-22 describes test signals which are reserved for factory testing.
Table 2-22. Test Signals
Signal Name Abbreviation Function I/O
Signal Descriptions
Test TEST Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of test
functions.
PLL Test PLL_TEST Reserved for factory testing only and should be treated as a
no-connect (NC).
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2.3.20 Power and Ground Pins
The pins described in Table 2-23 provide system power and ground to the chip. Multiple pins are provided
for adequate current capability. All power supply pins must have adequate bypass capacitance for
high-frequency noise suppression.
Table 2-23. Power and Ground Pins
Signal Name Abbreviation Function I/O
PLL Analog Supply PLL_VDD
PLL_VSS
Positiv e I/O Supply EVDD These pins supply positive power to the I/O pads
Positive Core Supply IVDD These pins supply positive power to the core logic. —
SDRAMC Supply SD_VDD These pins supply positive power to the SDRAM controller. —
USB Supply USB_VDD These pins supply positive power to the USB controllers. —
Dedicated power supply signals to isolate the sensitive PLL analog
(VCO) circuitry from the nor mal levels of noise present on the digital
power supply.
. —
—
USB Ground USB_VSS These pins are the negative supply (ground) for the USB controllers. —
Ground VSS These pins are the negative supply (ground) for the device. —
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MCF5329 Reference Manual, Rev 3
2.4 External Boot Mode
After reset, the address bus, data bus, FlexBus control signals, and SDRAM control signals default to their
bus functionalities. All other signals default to GPIO inputs (if applicable).
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Chapter 3
MCF5329 Reference Manual, Rev 3
ColdFire Core
3.1 Introduction
This section describes the organization of the Version 3 (V3) ColdFire® processor core and an overview
of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the
ColdFire Family Programmer’s Reference Manual. The V3 ColdFire core emphasizes operating
frequency and system performance and provides backward object file compatibility to the Version 2 (V2)
ColdFire core. It is a step on the ColdFire core roadmap of providing higher performance embedded
microprocessors. Specific enhancements include a 4-stage instruction fetch pipeline (IFP) with an 8-entry
instruction buffer and change-of-flow acceleration, a 2-stage pipeline local bus structure, and a 4-way
set-associative unified cache design supporting copyback and write-through modes of operation.
3.1.1 Overview
As with all ColdFire cores, the V3 ColdFire core is comprised of two separate pipelines decoupled by an
instruction buffer.
Freescale Semiconductor 3-1
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ColdFire Core
Instruction
Instruction
FIFO
Decode & Select,
Address
Instruction
Operand
Data[31:0]
Instruction
Fetch Cycle 2
Instruction
Pipeline
Execution
Fetch
Pipeline
IAG
IC1
IC2
IED
IB
DSOC
AGEX
Address [31:0]
Instruction Buffer
Address
Generation
Fetch Cycle 1
Early Decode
Generation,
Execute
Operand Fetch
MCF5329 Reference Manual, Rev 3
The instruction fetch pipeline (IFP) is a four-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the
Figure 3-1. V3 ColdFire Core Pipelines
instruction, fetches the required operands and then executes the required function. Because the IFP and
OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch
instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.
The V3 ColdFire core pipeline stages include the following:
• Four-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage)
— Instruction address generation (IAG) — Calculates the next prefetch address
— Instruction fetch cycle 1 (IC1) — Prefetch on the processor’s local bus
— Instruction fetch cycle 2 (IC2) — Completes prefetch on the processor’s local bus
— Instruction early decode (IED) — Generates time-critical decode signals needed for the OEP
— Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO
queue
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ColdFire Core
MCF5329 Reference Manual, Rev 3
• Two-stage operand execution pipeline (OEP)
— Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the
required components for effective address calculation, or the operand fetch cycle
— Address generation/execute cycle (AGEX)—Calculates operand address or executes the
instruction
When the instruction buffer is empty, opcodes are loaded directly from the IED cycle into the operand
execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction and its
early decode informration in the IB until it is required by the OEP.
For register-to-register and register-to-memory store operations, the instruction passes through both OEP
stages once. For memory-to-register and read-modify-write memory operations, an instruction is
effectively staged through the OEP twice: the first time to calculate the effective address and initiate the
operand fetch on the processor’s local bus, and the second time to complete the operand reference and
perform the required function defined by the instruction.
The V3 ColdFire core’s instruction buffer is or ganized differently than the V2 ColdFire core’ s. One of the
time-critical decode fields provided by the early-decode stage of the IFP is the instruction length. By
knowing the length of the prefetched instructions, the IED field can package the fetched data into machine
instructions and load them into the FIFO instruction buffer in that form. This approach greatly simplifies
and accelerates the OEP read logic. As one instruction is completed in the OEP, the next
instruction—regardless of instruction length—is read from the next sequential buffer location and loaded
into the instruction registers.
The resulting pipeline and local bus structure allow the V3 ColdFire core to deliver sustained high
performance across a variety of demanding embedded applications.
3.1.1.1 Change-of-Flow Acceleration
Because the IFP and OEP are decoupled by the instruction buffer, the increased depth of the IFP is
generally hidden from the OEP’s inst ruction execution. However , for change-of-flow instructions, such as
unconditional branches or jumps, subroutine calls, taken conditional branches, the increased IFP depth is
fully exposed. T o minimize the effects of this increased depth, a logic module dedicated to change-of-flow
acceleration was developed for the IED stage of the IFP.
The basic premise of the V3 ColdFire core’s branch acceleration is to detect certain types of
change-of-flow instructions, calculate their target instruction address, and immediately begin fetching
down the target stream. By allowing the IFP to manage switching of the prefetch stream without OEP
intervention, typical execution time is greatly improved.
For example, consider a PC-relative unconditional branch using the BRA instruction. The branch
acceleration logic searches the prefetch stream for this type of opcode. After encountered, the acceleration
logic calculates the target address by summing the current instruction prefetch address with a displacement
contained in the instruction. This detection and calculation of the target address occurs in the IED stage of
the BRA prefetch. The target address is then immediately fed back into the IAG stage, causing the current
prefetch stream to be discarded and establishing a new stream at the target address. Given that the two
pipelines are decoupled, in many cases, the target instruction is available to the OEP immediately after the
BRA instruction, making its execution time appear as a single cycle.
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(described fully in Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC
• One 32-bit memory base address register (RAMBAR)
MCF5329 Reference Manual, Rev 3
The acceleration logic uses a static prediction algorithm when processing conditional branch (Bcc)
instructions. The default prediction scheme is as follows: forward Bcc instructions are predicted as not
taken, while backward Bcc opcodes are predicted as taken. A user-mode bit in the condition control
register, CCR[P], supports altering the prediction dynamically for forward Bcc instructions. See
Section 3.2.4, “Condition Code Register (CCR).”
Depending on the run-time characteristics of an application, processor performance may be increased
significantly by setting or clearing this configuration bit. Section 3.3.5.7, “Branch Instruction Execution
Times,” gives details on individual instruction performance.
3.2 Memory Map/Register Description
The following sections describe the processor registers in the user and supervisor programming models.
The programming model is selected based on the processor privilege level (user mode or supervisor mode)
as defined by the S bit of the status register (SR). Table 3-1 lists the processor registers.
The user-programming model consists of the following registers:
• 16 general-purpose 32-bit registers (D0–D7, A0–A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
• EMAC registers :
— Four 48-bit accumulator registers partitioned as follows:
– Four 32-bit accumulators (ACC0–ACC3)
– Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two
32-bit values for load and store operations (ACCEXT01 and ACCEXT23).
Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC
arithmetic operations generally affect the entire 48-bit destination.
— One 16-bit mask register (MASK)
— One 32-bit Status register (MACSR) including four indicator bits signaling product or
accumulation overflow (one for each accumulator: PAV0–PAV3)
The supervisor programming model is to be used only by system control software to implement restricted
operating system functions, I/O control, and memory management. All accesses that affect the control
features of ColdFire processors are in the supervisor programming model, which consists of registers
available in user mode as well as the following control registers:
• 16-bit status register (SR)
• 32-bit supervisor stack pointer (SSP)
• 32-bit vector base register (VBR)
• 32-bit cache control register (CACR)
• 32-bit access control registers (ACR0, ACR1)
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Table 3-1. ColdFire Core Programming Model
MCF5329 Reference Manual, Rev 3
ColdFire Core
BDM
1
Register
Width
(bits)
Access Reset Value
Written with
MOVEC
Supervisor/User Access Registers
Load: 0x080
Data Register 0 (D0) 32 R/W 0xCF30_60 No 3.2.1/3-6
Store: 0x180
Load: 0x081
Data Register 1 (D1) 32 R/W 0x0000_0670 No 3.2.1/3-6
Store: 0x181
Load: 0x082–7
Data Register 2–7 (D2–D7) 32 R/W Undefined No 3.2.1/3-6
Store: 0x182–7
Load: 0x088–8E
Address Register 0–6 (A0–A6) 32 R/W Undefined No 3.2.2/3-6
Store: 0x188–8E
Load: 0x08F
Supervisor/User A7 Stack Pointer (A7) 32 R/W Undefined No 3.2.3/3-6
Store: 0x18F
0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 No 4.2.1/4-3
0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF No 4.2.2/4-5
0x806, 0x809,
MAC Accumulators 0–3 (ACC0–3) 32 R/W Undefined No 4.2.3/4-6
0x80A, 0x80B
0x807 MAC Accumulator 0,1 Exten si on By te s
32 R/W Undefined No 4.2.4/4-7
(ACCext01)
Section/Page
0x808 MAC Accumulator 2,3 Exten si on By te s
32 R/W Undefined No 4.2.4/4-7
(ACCext23)
0x80E Condition Code Register (CCR) 8 R/W Undefined No 3.2.4/3-7
0x80F Program Counter (PC) 32 R/W Contents of
No 3.2.5/3-8
location
0x0000_0004
Supervisor Access Only Registers
0x002 Cache Control Register (CACR) 32 R/W 0x0000_0000 Yes 3.2.6/3-8
0x004–5 Access Control Register 0–1 (ACR0–1) 32 R/W See Section Yes 3.2.7/3-9
0x800 User/Supervisor A7 Stack Pointer
(OTHER_A7)
32 R/W Contents of
location
No 3.2.3/3-6
0x0000_0000
0x801 Vector Base Register (VBR) 32 R/W 0x0000_0000 Y es 3.2.8/3-9
0x80E Status Register (SR) 16 R/W 0x27-- No 3.2.9/3-9
0xC05 RAM Base Address Register (RAMBAR) 32 R/W See Section Yes 3.2.10/3-10
1
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see Chapter 36, “Debug Module”.
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3.2.1 Data Registers (D0–D7)
D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they
can also be used as index registers.
NOTE
Registers D0 and D1 contain hardware configuration details after reset. See
Section 3.3.4.15, “Reset Exception” for more details.
BDM: Load: 0x080 + n; n = 0-7 (Dn)
Store: 0x180 + n; n = 0-7 (Dn)
313029282726252423222120191817161514131211109876543210
R
W
Reset
(D2-D7)
(D0, D1)
––––––––––––––––––––––––––––––––
Reset
Data
See Section 3.3.4.15, “Reset Exception”
Figure 3-2. Data Registers (D0–D7)
Access: User read/write
BDM read/write
3.2.2 Address Registers (A0–A6)
These registers can be used as software stack pointers, index registers, or base address registers. They can
also be used for word and longword operations.
BDM: Load: 0x088 + n; n =0–6 (An)
Store: 0x188 + n; n =0–6 (An)
313029282726252423222120191817161514131211109876543210
R
Address
W
Access: User read/write
BDM read/write
Reset––––––––––––––––––––––––––––––––
Figure 3-3. Address Registers (A0–A6)
3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)
This ColdFire architecture supports two independent stack pointer (A7) registers—the supervisor stack
pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two
program-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead, the
hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents
are a function of the processor operation mode, as shown in the following:
if SR[S] = 1
then A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer
else A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
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The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the
responsibility of the external development system to determine, based on the setting of SR[S], the mapping
of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP). This functionality is
enabled by setting the enable user stack pointer bit, CACR[EUSP]. If this bit is cleared, only a single stack
pointer (A7), defined for ColdFire ISA_A, is available. EUSP is cleared at reset.
To support dual stack pointers, the following two supervisor instructions are included in the ColdFire
instruction set architecture to load/store the USP:
move.l Ay,USP;move to USP
move.l USP,Ax;move from USP
These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other
instruction references to the stack pointer, explicit or implicit, access the active A7 register.
NOTE
The SSP is loaded during reset exception processing with the contents of
location 0x0000_0000.
BDM: Load: 0x08F (A7)
Store: 0x18F (A7)
0x800 (OTHER_A7)
313029282726252423222120191817161514131211109876543210
R
Address
W
Reset––––––––––––––––––––––––––––––––
Figure 3-4. Stack Pointer Registers (A7 and OTHER_A7)
Access: A7: User or BDM read/write
OTHER_A7: Supervisor or BDM read/write
3.2.4 Condition Code Register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. The extend bit (X) is also an input operand during multiprecision
arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare
(CMP), Bcc, or Scc instructions are executed.
BDM: LSB of Status Register (SR) Access: User read/write
BDM read/write
76543210
R
P
W
0 0
X N Z V C
Reset:0 0 0—————
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Figure 3-5. Condition Code Register (CCR)
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MCF5329 Reference Manual, Rev 3
Table 3-2. CCR Field Descriptions
Field Description
7
Branch prediction bit. Alters the static prediction algorithm used by the branch acceleration logic in the IFP on forward
P
conditional branches.
0 Predicit ed as no t ta ken.
1 Predicted as taken.
6–5 Reserved, must be cleared.
4
Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified
X
result.
3
Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.
N
2
Zero condition code bit. Set if result equals zero; otherwise cleared.
Z
1
Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand
V
size; otherwise cleared.
0
Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a
C
subtraction; otherwise cleared.
3.2.5 Program Counter (PC)
The PC contains the currently executing instruction address. During instruction execution and exception
processing, the processor automatically increments contents of the PC or places a new value in the PC, as
appropriate. The PC is a base address for PC-relative operand addressing.
The PC is initially loaded during reset exception processing with the contents of location 0x0000_0004.
BDM: 0x80F (PC) Access: User read/write
BDM read/write
313029282726252423222120191817161514131211109876543210
R
W
Reset––––––––––––––––––––––––––––––––
Figure 3-6. Program Counter Register (PC)
Address
3.2.6 Cache Control Register (CACR)
The CACR controls operation of the instruction/data cache memories. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and
write-protect fields. The CACR is described in Section 5.2.1, “Cache Control Register (CACR).”
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3.2.7 Access Control Registers (ACRn)
The access control registers define attributes for user-defined memory regions. These attributes include the
definition of cache mode, write protect, and buffer write enables. The ACRs are described in Section 5.2.2,
“Access Control Registers (ACR0–ACR1).”
3.2.8 Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in memory. To access the vector table,
the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are
not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on
a 1 MByte boundary.
BDM: 0x801 (VBR) Access: Supervisor read/write
BDM read/write
313029282726252423222120191817161514131211109876543210
R
Base Address
W
Reset00000000000000000000000000000000
0 0 0 0 0 000000000 000 0 00
Figure 3-7. Vector Base Register (VBR)
3.2.9 Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are
accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor
or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access
when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and
before any compare (CMP), Bcc, or Scc instructions execute.
BDM: 0x80E (SR) Access: Supervisor read/write
BDM read/write
System Byte Condition Code Register (CCR)
1514131211109876543210
R
W
Reset00100111000—————
Field Description
0
T
S M
0
Figure 3-8. Status Register (SR)
Table 3-3. SR Field Descriptions
IP
00
X N ZVC
15
Trace enable. When set, the processor performs a trace exception after every instruction.
T
14 Reserved, must be cleared.
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3.2.10 Memory Base Address Register (RAMBAR)
The memory base address register is used to specify the base address of the internal SRAM module and
indicates the types of references mapped to it. The base address register includes a base address,
write-protect bit, address space mask bits, and an enable bit. RAMBAR determines the base address of
the on-chip RAM. For more information, refer to Section 6.2.1, “SRAM Base Address Register
(RAMBAR)”.
MCF5329 Reference Manual, Rev 3
Table 3-3. SR Field Descriptions (continued)
Field Description
13
S
12
M
Supervisor/user state.
0User mode
1 Supervisor mode
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
11 Reserved, must be cleared.
10–8IInterrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
7–0
CCR
equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
Refer to Section 3.2.4, “Condition Code Register (CCR)”.
3.3 Functional Description
3.3.1 Version 3 ColdFire Microarchitecture
The following diagrams present a more detailed view of the internal pipeline structures for the Version 3
design. In particular, note the increased length of the IFP with the early decode (ED) table lookup and the
branch acceleration target address adders in the IED stage with the feedback to the prefetch address logic
in the IAG stage. The OEP is essentially unchanged from the Version 2 design with the exception of the
extended opword provided from the IFP as part of the instruction interface:
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Figure 3-9. Version 3 ColdFire Processor Instruction Fetch Pipeline Diagram
IAG
IC 1 IB
Core bus
Opword
Extension 1
Extension 2
FIFO
IB
IC 2 IED
Extended
opword
ED
+4
read data
DSOC AGEX
Opword
Extension 1
Extension 2
Core bus
Core bus
Core bus
RGF
Extended
opword
write data
read data
address
MCF5329 Reference Manual, Rev 3
ColdFire Core
Figure 3-10. Version 3 ColdFire Processor Operand Execution Pipeline Diagram
3.3.2 Instruction Set Architecture (ISA_A+)
The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes
based on extensive analysis of embedded application code. The ISA was optimized for code compiled
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from high-level languages where the dominant operand size was the 32-bit integer declaration. This
approach minimized processor complexity and cost, while providing excellent performance for compiled
applications.
After the initial ColdFire compilers were created, developers noted there were certain ISA additions that
would enhance code density and overall performance. Additionally , as users implemented ColdFire-based
designs into a wide range of embedded systems, they found certain frequently-used instruction sequences
that could be improved by the creation of additional instructions.
The original ISA definition minimized support for instructions referencing byte- and word-sized operands.
Full support for the move byte and move word instructions was provided, but the only other opcodes
supporting these data types are CLR (clear) and TST (test). A set of instruction enhancements has been
implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three
areas:
1. Enhanced support for byte and word-sized operands
2. Enhanced support for position-independent code
3. Miscellaneous instruction additions to address new functionality
Table 3-4 summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details
see the ColdFire Family Programmer’s Reference Manual.
Table 3-4. Instruction Enhancements over Revision ISA_A
Instruction D escription
BITREV The contents of the destination data register are bit-reversed; new Dn[31] equals old Dn[0], new
Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31].
BYTEREV The contents of the destination data register are byte-reversed; new Dn[31:24] equals old
Dn[7:0],..., new Dn[7:0] equals old Dn[31:24].
FF1 The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending
with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.
Move from USP USP → Destination register
Move to USP Source register → USP
3.3.3 Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
differ from the M68000 family because they include:
• A simplified exception vector table
• Reduced relocation capabilities using the vector-base register
• A single exception stack frame format
• Use of separate system stack pointers for user and supervisor modes.
All ColdFire processors use an instruction restart exception model. However, Version 3 ColdFire
processors require more software support to recover from certain access errors. See Section 3.3.4.1,
“Access Error Exception” for details.
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2. The processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller. The IACK cycle is mapped to special locations within the interrupt
controller’s address space with the interrupt level encoded in the address.
All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see
Table 3-5).
MCF5329 Reference Manual, Rev 3
Exception processing includes all actions from fault condition detection to the initiation of fetch for first
handler instruction. Exception processing is comprised of four major steps:
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to
be cleared and the interrupt priority mask to set to current interrupt request level.
3. The processor saves the current context by creating an exception stack frame on the system stack.
The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to
by the supervisor stack pointer (SSP). As shown in Figure 3-11, the processor uses a simplified
fixed-length stack frame for all exceptions. The exception type determines whether the program
counter placed in the exception stack frame defines the location of the faulting instruction (fault)
or the address of the next instruction to be executed (next).
4. The processor calculates the address of the first instruction of the exception handler. By definition,
the exception vector table is aligned on a 1 Mbyte boundary . This instruction address is generated
by fetching an exception vector from the table located at the address defined in the vector base
register . The index into the exception table is calculated as (4 × vector number). After the exception
vector has been fetched, the vector contents determine the address of the first instruction of the
desired handler. After the instruction fetch for the first opcode of the handler has initiated,
exception processing terminates and normal instruction processing continues in the handler.
The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are
device-specific peripheral interrupt vectors. See Chapter 14, “Interrupt Controller Modules” for details on
the device-specific interrupt sources.
Table 3-5. Exception Vector Assignments
Vector
Number(s)
0 0x000 — Initial supervisor stack pointer
1 0x004 — Initial program counter
2 0x008 Fault Access error
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
3 0x00C Fault Address error
4 0x010 Fault Illegal instruction
5 0x014 Fault Divide by zero
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Table 3-5. Exception Vector Assignments (continued)
Vector
Number(s)
6–7 0x018–0x01C — Reserved
8 0x020 Fault Privilege violation
9 0x024 Next Trace
10 0x028 Fault Unimplemente d line-A opcode
11 0x02C Fault Unimplemented line-F opcode
12 0x030 Next Debug interrupt
13 0x034 — Reserved
14 0x038 Fault Format error
15–23 0x03C–0x05C — Reserved
24 0x060 Next Spurious interrupt
25–31 0x064–0x07C — Reserved
32–47 0x080–0x0BC Next Trap # 0-15 instructions
48–63 0x0C0–0x0FC — Reserved
64–255 0x100–0x3FC Next Device-specific interrupts
1
Fault ref ers to the PC of the instruction that caused the exception. Next ref ers to the PC
of the instruction that follows the instruction that caused the fault.
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level
contained in the status register. For more details, see ColdFire Family Programmer’s Reference Manual.
3.3.3.1 Exception Stack Frame Definition
Figure 3-11 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)
and the 16-bit status register, and the second longword contains the 32-bit program counter address.
313029282726252423222120191817161514131211109876543210
SSP → Format FS[3:2] Vector FS[1:0] Status Register
+ 0x4
Figure 3-11. Exception Stack Frame Form
The 16-bit format/vector word contains three unique fields:
• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by
the processor, indicating a two-longword frame format. See Table 3-6.
Program Counter
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Table 3-6. Format Field Encodings
MCF5329 Reference Manual, Rev 3
ColdFire Core
Original SSP @ Time
of Exception, Bits 1:0
00 Original SSP - 8 0100
01 Original SSP - 9 0101
10 Original SSP - 10 0110
11 Original SSP - 11 0111
SSP @ 1st
Instruction of
Handler
Format Field
• There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for
access and address errors only and written as zeros for all other exceptions. See Table 3-7.
Table 3-7. Fault Status Encodings
FS[3:0] Definition
00xx Reserved
0100 Error on instruction fetch
0101 Reserved
011x Reserved
1000 Error on operand write
1001 Attempted write to write-protected space
101x Reserved
1100 Error on operand read
1101 Reserved
111x Reserved
• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor
for all internal faults and represents the value supplied by the interrupt controller in case of an
interrupt. See Table 3-5.
3.3.4 Processor Exceptions
3.3.4.1 Access Error Exception
The exact processor response to an access error depends on the memory reference being performed. For
an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an
instruction for execution. Therefore, faults during instruction prefetches followed by a change of
instruction flow do not generate an exception. When the processor attempts to execute an instruction with
a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For this
type of exception, the programming model has not been altered by the instruction generating the access
error.
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If the access error occurs on an operand read, the processor immediately aborts the current instruction’s
execution and initiates exception processing. In this situation, any address register updates attributable to
the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming
model contains the updated An value. In addition, if an access error occurs during a MOVEM instruction
loading from memory, any registers already updated before the fault occurs contain the operands from
memory.
The V3 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes.
Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the
signaling of an access error appears to be decoupled from the instruction that generated the write.
Accordingly , the PC contained in the exception stack fra me merely represents the location in the program
when the access error was signaled. All programming model updates associated with the write instruction
are completed. The NOP instruction can collect access errors for writes. This instruction delays its
execution until all previous operations, including all pending write operations, are complete. If any
previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.
3.3.4.2 Address Error Exception
Any attempted execution transferring control to an odd instruction address (if bit 0 of the target address is
set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of eight on an indexed effective
addressing mode generates an address error, as does an attempted execution of a full-format indexed
addressing mode, which is defined by bit 8 of extension word 1 being set.
If an address error occurs on a JSR instruction, the Version 3 ColdFire processor calculates the target
address then the return address is pushed onto the stack. If an address error occurs on an R TS instruction,
the Version 3 ColdFire processor overwrites the faulting return PC with the address error stack frame.
3.3.4.3 Illegal Instruction Exception
The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits.
The first instruction word is known as the operation word (or opword), while the optional words are known
as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper
four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode
(opmode), and the low-order 6 bits define the effective address. See Figure 3-12. The opword line
definition is shown in Table 3-8.
1514131211109876543210
Line OpMode Effective Address
Mode Register
Figure 3-12. ColdFire Instruction Operation Word (Opword) Format
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Table 3-8. ColdFire Opword Line Definition
MCF5329 Reference Manual, Rev 3
Opword[Line] Instruction Class
0x0 Bit manipulation, Arithmetic and Logical Immediate
0x1 Move Byte
0x2 Move Long
0x3 Move Word
0x4 Miscellaneous
0x5 Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc)
0x6 PC-relative change-of-flow instructions
Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR)
0x7 Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ)
0x8 Logical OR (OR)
0x9 Subtract (SUB), Subtract Extended (SUBX)
0xA EMAC, Move 3-bit Quick (MOV3Q)
0xB Compare (CMP), Exclusive-OR (EOR)
0xC Logical AND (AND), Multiply Word (MUL)
ColdFire Core
0xD Add (ADD), Add Extended (ADDX)
0xE Arithmetic and logical shifts (ASL, ASR, LSL, LSR)
0xF Cache Push (CPUSHL), Write DDATA (WDDATA), Wr ite Debug (WDEBUG)
In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations
(line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors
associated with illegal opwords in these two lines.
Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an
illegal instruction exception (vector 4). Additionally , any attempted execution of any non-MAC line-A and
most line-F opcodes generate their unique exception types, vector numbers 10 and 11, respectively.
ColdFire cores do not provide illegal instruction detection on the extension words on any instruction,
including MOVEC.
3.3.4.4 Divide-By-Zero
Attempting to divide by zero causes an exception (vector 5, offset equal 0x014).
3.3.4.5 Privilege Violation
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. See ColdFire Programmer’s Reference Manual for a list of supervisor-mode
instructions.
There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode
instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in
user mode for debugging purposes.
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3.3.4.6 Trace Exception
To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing
capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction
execution (for all but the stop instruction) signals a trace exception. This functionality allows a debugger
to monitor program execution.
The stop instruction has the following effects:
1. The instruction before the stop executes and then generates a trace exception. In the exception stack
frame, the PC points to the stop opcode.
2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate
operand from the instruction.
3. The processor then generates a trace exception. The PC in the exception stack frame points to the
instruction after the stop, and the SR reflects the value loaded in the previous step.
If the processor is not in trace mode and executes a stop instruction where the immediate operand sets
SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points
to the instruction after the stop, and the SR reflects the value loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types. As
an example, consider a TRAP instruction execution while in trace mode. The processor initiates the trap
exception and then passes control to the corresponding handler . If the system requires that a trace exception
be processed, it is the responsibility of the trap exception handler to check for this condition (SR[T] in the
exception stack frame set) and pass control to the trace handler before returning from the original
exception.
3.3.4.7 Unimplemented Line-A Opcode
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the
attempted execution of an undefined line-A opcode.
3.3.4.8 Unimplemented Line-F Opcode
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when
attempting to execute an undefined line-F opcode.
3.3.4.9 Debug Interrupt
See Chapter 36, “Debug Module,” for a detailed explanation of this exception, which is generated in
response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle, but
rather calculates the vector number internally (vector number 12). Additionally , SR[M,I] are unaffected by
the interrupt.
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3.3.4.10 RTE and Format Error Exception
When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the
frame type. For a ColdFire core, any attempted R TE execution (where the format is not equal to {4,5,6,7})
generates a format error. The exception stack frame for the format error is created without disturbing the
original RTE frame and the stacked PC pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code from M68000
applications. On M68000 family processors, the SR was located at the top of the stack. On those
processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE
is attempted using this old format, it generates a format error on a ColdFire processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second
longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address
after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the
second longword operand within the stack frame.
3.3.4.11 TRAP Instruction Exception
The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing
system calls. The TRAP instruction may be used to change from user to supervisor mode.
3.3.4.12 Unsupported Instruction Exception
If execution of a valid instruction is attempted but the required hardware is not present in the processor , an
unsupported instruction exception is generated. The instruction functionality can then be emulated in the
exception handler, if desired.
All ColdFire cores record the processor hardware configuration in the D0 register immediately after the
negation of RESET. See Section 3.3.4.15, “Reset Exception,” for details.
3.3.4.13 Interrupt Exception
Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from
the interrupt controller using an IACK cycle. See Chapter 14, “Interrupt Controller Modules,” for details
on the interrupt controller.
3.3.4.14 Fault-on-Fault Halt
If a ColdFire processor encounters any type of fault during the exception processing of another fault, the
processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to
to exit this state.
3.3.4.15 Reset Exception
Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from catastrophic
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failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot
be recovered.
The reset exception places the processor in the supervisor mode by setting the SR[S] bit and disables
tracing by clearing the SR[T] bit. This exception also clears the SR[M] bit and sets the processor’s SR[I]
field to the highest level (level 7, 0b11 1). Next, the VBR is initialized to zero (0x0000_0000). The control
registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly
to the processor are disabled.
NOTE
Other implementation-specific registers are also affected. Refer to each
module in this reference manual for details on these registers.
After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at
address 0x0000_0000 is loaded into the supervisor stack pointer and the second longword at address
0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory,
program execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault state.
ColdFire processors load hardware configuration information into the D0 and D1 general-purpose
registers after system reset. The hardware configuration information is loaded immediately after the
reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM
to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in Figure 3-13.
BDM: Load: 0x080 (D0)
Store: 0x180 (D0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PF VER REV
W
Reset1100111100110000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAC DIVEMACFPU0000 ISA DEBUG
W
Reset0110000010001001
Figure 3-13. D0 Hardware Configuration Info
Access: User read-only
BDM read-only
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Table 3-9. D0 Hardware Configuration Info Field Description
(This is the value used for this device.)
MCF5329 Reference Manual, Rev 3
Field Description
31–24PFProcessor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.
ColdFire Core
23–20
VER
ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core.
0001 V1 ColdFire core
0010 V2 ColdFire core
0011 V3 ColdFire core (This is the value used for this device.)
0100 V4 ColdFire core
0101 V5 ColdFire core
Else Reserved for future use
19–16
Processor revision number. The default is 0b000 0.
REV
15
MAC present. This bit signals if the optional multiply-accumulate (MAC) ex ecution engine is present in processor core.
MAC
0 MA C execute engine not present in core. (This is the value used for this device.)
1 MAC execute engine is present in core.
14
Divide present. This bit signals if the hardware divider (DIV) is present in the processor core.
DIV
0 Divide execute engine not prese nt in core.
1 Divide execute engine is present in core.
13
EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution engine is present in
EMAC
processor core.
0 EMAC execute engine not present in core.
1 EMAC execute engine is present in core. (This is the value used for this device.)
12
FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core.
FPU
0 FPU execute engine not present in core. (This is the value used for this device.)
1 FPU execute engine is present in core.
10–8 Reserved.
7–4
ISA
3–0
DEBUG
ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core.
0000 ISA_A
0001 ISA_B
0010 ISA_C
1000 ISA_A+ (This is the value used for this device.)
Else Reserved
Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core.
0000 DEBUG_A
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
1001 DEBUG_B+ (This is the value used for this device.)
1011 DEBUG_D+
1111 DEBUG_D+PST Buffer
Else Reserved
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Information loaded into D1 defines the local memory hardware configuration as shown in the figure below .
BDM: Load: 0x081 (D1)
Store: 0x181 (D1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access: User read-only
BDM read-only
RCLSZ 00000000000000
W
Reset0000000000000000
1514131211109876543210
R MBSZ UCAS UCSZ SRAMSZ 0 0 0
W
Reset0000011001110000
Figure 3-14. D1 Hardware Configuration Info
Table 3-10. D1 Hardware Configuration Information Field Description
Field Description
31–30
CLSZ
29–24 Reserved.
Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.
23–16 Reserved.
15–14
MBSZ
Bus size. Defines the width of the ColdFire master bus datapath.
00 32-bit system bus datapath (This is the value used for this device)
01 64-bit system bus datapath
Else Reserved
13–12
UCAS
Unified cache associativity. Defines the un ified cache set-associativity.
00 Four-way (This is the value used for this device)
01 Direct mapped
Else Reserved for future use
11–8
UCSZ
Unified cache size. Indicates the size of the unified cache.
0000 No unified cache
0001 512 bytes
0010 1 Kbytes
0011 2 Kbytes
0100 4 Kbytes
0101 8 Kbytes
0110 16 Kbytes (This is the value used for this device)
0111 32 Kbytes
Else Reserved for future use
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Table 3-10. D1 Hardware Configuration Information Field Description (continued)
MCF5329 Reference Manual, Rev 3
Field Description
ColdFire Core
7–3
SRAMSZ
2–0 Reserved.
SRAM bank size.
00000 N o SRAM
00010 512 bytes
00100 1 Kbytes
00110 2 Kbytes
01000 4 Kbytes
01010 8 Kbytes
01100 16 Kbytes
01110 32 Kbytes (This is the value used for this device)
10000 64 Kbytes
10010 128 Kbytes
Else Reserved for future use
3.3.5 Instruction Execution Timing
This section presents processor instruction execution times in terms of processor-core clock cycles. The
number of operand references for each instruction is enclosed in parentheses following the number of
processor clock cycles. Each timing entry is presented as C(R/W) where:
•C is the number of processor clock cycles, including all applicable operand fetches and writes, and
all internal core cycles required to complete the instruction execution.
• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation
performing a read-modify-write function is denoted as (1/1).
This section includes the assumptions concerning the timing values and the execution time details.
3.3.5.1 Timing Assumptions
For the timing data presented in this section, these assumptions apply:
1. The OEP is loaded with the opword and all required extension words at the beginning of each
instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or
extension words.
2. The OEP does not experience any sequence-related pipeline stalls. The most common example of
stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE
operations (except MOVEM), certain hardware resources within the processor are marked as busy
for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store
instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is
stalled until the resource again becomes available. Thus, the maximum pipeline stall involving
consecutive STORE operations is two cycles. The MOVEM instruction uses a different set of
resources and this stall does not apply.
3. The OEP completes all memory accesses without any stall conditions caused by the memory itself.
Thus, the timing details provided in this section assume that an infinite zero-wait state memory is
attached to the processor core.
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4. All operand data accesses are aligned on the same byte boundary as the operand size; for example,
16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4
addresses.
The processor core decomposes misaligned operand references into a series of aligned accesses as
shown in Table 3-11.
Table 3-11. Misaligned Operand References
address[1:0] Size
01 or 11 Word Byte, Byte 2(1/0) if read
01 or 11 Long Byte, Word,
10 Long Word, Word 2(1/0) if read
Bus
Operations
Byte
Additional
C(R/W)
1(0/1) if write
3(2/0) if read
2(0/2) if write
1(0/1) if write
3.3.5.2 MOVE Instruction Execution Times
Table 3-12 lists execution times for MOVE.{B,W} instructions; Table 3-13 lists timings for MOVE.L.
NOTE
For all tables in this section, the execution time of any instruction using the
PC-relative effective addressing modes is the same for the comparable
An-relative mode.
ET with {<ea> = (d16,PC)} equals ET with {<ea> = (d16,An)}
ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<e a> = (d8,An,Xi*SF)}
The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w
and xxx.l.
Table 3-12. MOVE Byte and Word Execution Times
Destination
Source
Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl
Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
(Ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1)) 4(1/1)
(Ay)+ 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1)) 4(1/1)
-(Ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1)) 4(1/1)
(d16,Ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — —
(d8,Ay,Xi*SF) 5(1/0) 5(1/1) 5(1/1) 5(1/1) — — —
xxx.w 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —
xxx.l 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —
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Table 3-12. MOVE Byte and Word Execution Times (continued)
Destination
Source
Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl
(d16,PC) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — —
(d8,PC,Xi*SF) 5(1/0) 5(1/1) 5(1/1) 5(1/1)) — — —
#xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — —
Table 3-13. MOVE Long Execution Times
Destination
Source
Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl
Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)
(Ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)
-(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)
(d16,Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —
(d8,Ay,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —
xxx.w 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
xxx.l 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
(d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —
(d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —
#xxx 1(0/0) (0/1) (0/1) (0/1) — — —
3.3.5.3 Standard One Operand Instruction Execution Times
Table 3-14. One Operand Instruction Execution Times
Effective Address
Opcode <EA>
Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx
BITREVDx1(0/0)———— — ——
BYTEREVDx1(0/0)———— — ——
CLR.B <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —
CLR.W <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —
CLR.L <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —
EXT.WDx1(0/0)———— — ——
EXT.LDx1(0/0)———— — ——
EXTB.LDx1(0/0)———— — ——
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Table 3-14. One Operand Instruction Execution Times (continued)
Effective Address
Opcode <EA>
Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx
FF1Dx1(0/0)———— — ——
NEG.LDx1(0/0)———— — ——
NEGX.LDx1(0/0)———— — ——
NOT.LDx1(0/0)———— — ——
SCCDx1(0/0)———— — ——
SWAPDx1(0/0)———— — ——
TST.B <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
TST.W <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
TST.L <ea> 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)
3.3.5.4 Standard Two Operand Instruction Execution Times
Table 3-15. Two Op erand Instruction Execution Times
Effective Address
Opcode <EA>
Rn (An) (An)+ -(An)
ADD.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
ADD.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
ADDI.L #imm,Dx 1(0/0) — — — — — — —
ADDQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
ADDX.L Dy,Dx 1(0/0) — — — — — — —
AND.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)
AND.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —
ANDI.L #imm,Dx 1(0/0) — — — — — — —
ASL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)
ASR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)
BCHG Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —
BCHG #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —
BCLR Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —
BCLR #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —
BSET Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —
BSET #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —
BTST Dy,<ea> 2(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —
BTST #imm,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —
(d16,An)
(d16,PC)
(d8,An,Xn*SF)
(d8,PC,Xn*SF)
xxx.wl #xxx
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