Freescale Semiconductor MCF5282 User Manual Addendum

Freescale Semiconductor

User’s Manual Addendum

MCF5282UMAD

Rev. 15, 05/2007

MCF5282 User’s Manual Errata

by: Microcontroller Division

This errata document describes corrections to the
MCF5282 ColdFire Microcontroller User’s Manual,
order number MCF5282UM. For convenience, the
addenda items are grouped by revision. Please check our
website at http://www.freescale.com for the latest
updates.

Table of Contents

1 Errata for Revision 2.3.........................................2

2 Errata for Revision 2.1 & 2.2 ...............................5

3 Errata for Revision 2.0.........................................6

4 Errata for Revision 1.0.........................................7

5 Revision History ............... ... ... ...........................16

© Freescale Semiconductor, Inc., 2007. All rights reserved.

Errata for Revision 2.3

f

sys

f

ref

2MFD 2+()×

2

RFD

--------------------------------------------- -

f

ref

2MFD 2+()× f

sys max() fsysfsys max()

≤;≤;=

1 Errata for Revision 2.3

Table 1. MCF5282UM Rev 2.3 Errata

Location Description

Table 2-1/Page 2-4 Remove last sentence in C bit field description.
Table 2-3/Page 2-7 Change PC’s Written with MOVEC entry to “No”.

Section 2.5/Page 2-8 Change last bullet to “Use of separate system stack pointers for user and supervisor

modes”

Section 2.5/Page 2-9 Change last sentence in fourth paragraph (step 2) to “The IACK cycle is mapped to special

locations within the interrupt controller's address space with the interrupt level encoded in
the address."

Figure 3-6/Page 3-8 Add minus sign to the exponent so that it is “–(i + 1 – N)”.

Table 4-3/Page 4-5 Change reset value of A CR0, A CR1 to “See Section” since some of the bits are undefined

after reset.

Figure 4-2/Page 4-6 Change CACR fields to R/W, since they may be read via the debug module.

Table 4-5/Page 4-8 For split instruction/data cache entry, swap text in parantheses in the description field.

Instruction cache uses the upper half of the arrays, while data cache uses the lower half.

Figure 4-3/Page 4-9 Change reset value of ACR: Bits 31-16, 14-13, 6-5, and 2 are undefined, and other bits are

cleared.
Change ACR fields to R/W, since they may be read via the debug module.

Section 4.4.2.2/Page 4-9 Change note to:

NOTE

Peripheral (IPSBAR) space should not be cached. The
combination of the CACR defaults and the two ACRn
registers must define the non-cacheable attribute for
this address space.

Figure 5-1/Page 5-2 Change RAMBAR fields to R/W, since they may be read via the debug module.

Table 5-1/Page 5-2 The PRI1/PRI2 text description does not match the table below it. It should be: “If a bit is

set, CPU has priority. If a bit is cleared, DMA has priority.”

Chapter 8 Remove any references to the core watchdog timer being able to reset the de vice. It is only

able to interrupt the processor. Use the peripheral watchdog timer described in
Chapter 18 if needing a watchdog timer to reset the device.

Table 9-4/Page 9-7 In the table for MFD bit definition, footnote (1) equation should read:

Where f

is the maximum system frequency for the particular MCF5282 device

sys(max)

(66MHz or 80MHz)

Section 10.3.6/Page 10-11 Include the following text in the section description and as a note in Figure 10-9.

“It is the responsibility of the software to program the ICRnx registers with u niq ue an d

non-overlapping level and priority definitions. Failure to program the ICRnx registers in
this manner can result in undefined behavior. If a specific interrupt request is completely
unused, the ICRnx value can remain in its reset (and disabled) state.”

Figure 10-6/Page 10-9 Interrupt Force Register Low (INTFRCLn) is illustrated as read-only in the figure. Howev er ,

this register should be read/write.

MCF5282 User’s Manual Errata, Rev. 15

Freescale Semiconductor2

Errata for Revision 2.3

Table 1. MCF5282UM Rev 2.3 Errata (continued)

Location Description

Table 10-14/Page 10-15 Change flag clearing mechanism for sources 24-26. They should read as follows:

Write ERR_INT = 1 after reading ERR_INT = 1
Write BOFF_INT = 1 after reading BOFF_INT = 1
Write WAKE_INT = 1 after reading WAKE_INT = 1

Table 12-7/Page 12-7 BAM bit field description, the first example should read “So, if CSAR0 = 0x0000 and

CSMR0[BAM] = 0x0001” instead of “So, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008”.

Table 10-2/Page 10-4 In footnote, remove mention of the SWIACK register, as it is not supported in the global

IACK space.

Section 10.3.7/Page 10-16 Change last paragraph to: “In addition to the IACK registers within each interrupt controller,

there are global LnIACK registers. A read from one of the global LnIACK registers returns
the vector for the highest priority unmasked interrupt within a level for all interrupt
controllers. There is no global SWIACK register. However, reading the SWIACK register
from each interrupt controller return s the vector number of the highest priority unmasked

request within that controller.”
Table 15-1/Page 15-3 NOP command entry. Replace “SRAS
Table 15-5/Page 15-7 Add the following note to the DACRn[CBM] field description:

Note: It is important to set CBM according to the location of the command bit.

Section 16.5/Page 16-11 Remove last sentence in this section starting with “BCRn decrements...” since SAA bit is

not supported.

asserted” with “SDRAM_CS[1:0] asserted”

Chapter 17 The maximum buffer size of the FEC is 2032 bytes. Replace any mention of the max size

being 2047 bytes with 2032 bytes.

Section 17.4.6/Page 17-7 Add the following subsection entitled “Duplicate Frame Transmission”:

The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data

continuously until the transmit FIFO is full. It does not determine whether the TxBD to be

fetched is already being processed internally (as a result of a wrap). As the FEC nears the

end of the transmission of one frame, it begins to DMA the data for the next frame. In order

to remain one BD ahead of the DMA, it also fetches the TxBD for the next frame. It is

possible that the FEC will fetch from memory a BD that has already been processed but not

yet written back (that is, it is read a second time with the R bit still set). In this case, the data

is fetched and transmitted again.

Using at least three TxBDs fixes this problem for large frames , but not for small frames. To

ensure correct operation for either large or small frames, one of the following must be true:

• The FEC software driver ensures that there is always at least one TxBD with the ready
bit cleared.

• Every frame uses more than one TxBD and every TxBD but the last is written back
immediately after the data is fetched.

• The FEC software driver ensures a minimum frame size, n. The minimum number of
TxBDs is then (Tx FIFO Size ÷ (n + 4)) rounded up to the nearest integer (though the
result cannot be less than three). The default Tx FIFO size is 192 bytes; this size is
programmable.

Table 17-9/Page 17-17 Correct MIB block counters end addresses to IPSBAR + 0x12FF.

Table 17-11/Page 17-19 Add RMON_R_DROP with an IPSBAR Offset of 0x1280 and a description of ‘Count of

frames not counted correctly’.

Figure 17-26/Page 17-41 Change EMRBR register address from “IPSBAR + 0x11B8” to “IPSBAR + 0x1188”.

Section 20.5.13/Page 20-12 Deleted reference to none xistent CF bits in the figure and bit descriptions for the GPTFLG2

register.

MCF5282 User’s Manual Errata, Rev. 15

Freescale Semiconductor 3

Errata for Revision 2.3

Characteristic Symbol Min

Max

Unit

66MHz 80MHz

PLL Reference Frequency Range

Crystal reference
External reference
1:1 Mode

f

ref_crystal

f

ref_ext

f

ref_1:1

2
2

33.33

8.33

8.33

66.66

10.0

10.0

80

MHz

System Frequency

1

External Clock Mode
On-Chip PLL Frequency

f

sys

0

f

ref

/ 32

f

sys(max)

66.66

66.66

f

sys(max)

80
80

MHz

Table 1. MCF5282UM Rev 2.3 Errata (continued)

Location Description

Figure 23-18/Page 23-18 Remove the two 16-bit divider blocks from timer input, as the divider is not available using

external clock sources.

Section 23.5.1.2.2/Page

23-19

Remove 16-bit divider from equation, as the divider is not available using external clock

sources.

Section 25.5.8/Page 25-25 Change end of last sentence from “...and can be written by the host to ‘0’. ” to “...and can be

written by the host to ‘1’.”

Table 25-17/Page 25-29 Remove the following information from the BITERR and ACKERR descriptions as these

fields are read only: “To clear this bit, first read it as a one, the n write it as a one . Writing
zero has no effect.” (This is a rescindment of a previous documentation errata.)

Change last sentence in ERRINT description from: “To clear this bit, first read it as a one,

then write as a zero. Writing a one has no effect.” to “To clear this bit, first read it as a
one, then write a one. Writing a zero has no effect.”

Add the following information to the BOFFINT and W AKEINT descriptions: “T o clear this bit,

first read it as a one, then write it as a one. Writing zero has no effect.”

Table 25-17/Page 25-27 Definition of bits ERRINT and BOFFINT are incorrect for register ESTAT: ERRINT should

be bit 1, BOFFINT should be bit 2. They should be cleared by writing a one instead of a
zero.

Table 26-1/Page 26-5 Change description field for DTOUT1 from “DMA timer 1 output / Port TD[3]...” to “DMA

timer 1 output / Port TD[2]...”

Change description field for DTIN0 from “DMA timer 0 input / Port TD[3]...” to “DMA timer 1

output / Port TD[1]...”

Change description field for DTOUT0 from “DMA timer 0 output / Port TD[3]...” to “DMA

timer 1 output / Port TD[0]...”

Table 30-12/Page 30-14 Add the following note to the PBR[Address] field description:

Note: PBR[0] should always be loaded with a 0.

Table 30-20/Page 30-35 Change CSR’s initial state to 0x0000_0000.

Chapter 33 Add the following note:

“It is crucial during power-up that VDD never exceeds VDDH b y more that ~0.3V. There
are diode devices between the two voltage domains, and violating this rule can lead to a
latch-up condition.”

Table 33-3/Page 33-3 In the V

to “I

and VOL entries, change the respective IOH and IOL specs from “IOH= -2.0mA”

OH

= -5.0mA” and “IOL= +2.0mA” to “IOL= +5.0mA”

OH

Table 33-8/Page 33-7 In the PLL Electrical Specifications table, only specs for the 80MHz MCF5282 device were

listed. Insert specs for the 66MHz device in the first 2 rows and also declare symbol
f

, as shown below:

sys(max)

MCF5282 User’s Manual Errata, Rev. 15

Freescale Semiconductor4

Table 1. MCF5282UM Rev 2.3 Errata (continued)

f

sys

f

ref

2MFD 2+()×

2

RFD

--------------------------------------------- -

f

ref

2MFD 2+()× f

sys max() fsysfsys max()

≤;≤;=

Location Description

Errata for Revision 2.1 & 2.2

Table 33-8/Page 33-7 Change EXTAL Input High Voltage (V

XTAL

+0.4”.

to “V

Change EXTAL Input Low Voltage (V

“V

-0.4”.

XTAL

) Crystal Mode minimum spec from “VDD-1.0”

IHEXT

) Crystal Mode maximum spec from “1.0” to

ILEXT

Section 33.13.1/Page 33-21 Remove second sentence:

“There is no minimum frequency requirement.”

Section 33.13.2/Page 33-22 Remove second sentence:

“There is no minimum frequency requirement.”

Remove second paragraph as this feature is not supported on this device:

“The transmit outputs (ETXD[3:0], ETXEN, ETXER) ca n be pro grammed to
transition from either the rising or falling edge of ETXCLK, and the timing is the
same in either case. This options allows the use of non-compliant MII PHYs. Refer
to the Ethernet chapter for details of this option and how to enable it.”

Table A-3/Page A-4 The CSMR1 and CSCR1 register addresses are incorrect. They should be

IPSBAR + 0x090 and IPSBAR + 0x096 respectively

2 Errata for Revision 2.1 & 2.2

Table 2. MCF5282UM Rev 2.1 & 2.2 Errata

Location Description

Figure 4-2/4-6 Changed bit 23 from DIDI to DISI

Table 4-6/4-9 Under ‘Configuration’ for ‘Instruction Cache’ the ‘Operation’ entry changed to “Invalidate

2 KByte data cache”

Table 4-6/4-9 Under ‘Configuration’ for ‘Data Cache’ the ‘Operation’ entry changed to “Invalidate 2 KByte

instruction cache”

Figure 6-3/6-6 Changed bit 8 to write-only instead of read/write

Table 6-10/6-15 Removed “selected by BKSL[1:0]” as these are internal signal names not necessary for

end-user.

Table 9-4/9-7 In the table for MFD bit definition, footnote (1) equation should read:

Where f

is the maximum system frequency for the particular MCF5282 device

sys(max)

(66MHz or 80MHz)

10.3.2/10-8 Add the following note: ‘If an interrupt source is being masked in the interrupt controller
mask register (IMR) or a module’s interrupt mask register while the interrupt mask in the
status register (SR[I]) is set to a value lower than the interrupt’s le vel, a spurious interrupt
may occur. This is because by the time the status register acknowledges this interrupt,
the interrupt has been masked. A spurious interrupt is generated because the CPU
cannot determine the interrupt source. To avoid this situation for interrupts sources with
levels 1-6, first write a higher level interrupt mask to the status register, before setting the
mask in the IMR or the module’s interrupt mask register. After the mask is set, return the
interrupt mask in the status register to its previous value. Since level seven interrupts
cannot be disabled in the status register prior to masking, use of the IMR or module
interrupt mask registers to disable level seven interrupts is not recommended.’

MCF5282 User’s Manual Errata, Rev. 15

Freescale Semiconductor 5

Errata for Revision 2.0

Characteristic Symbol Min

Max

Unit

66MHz 80MHz

PLL Reference Frequency Range

Crystal reference
External reference
1:1 Mode

f

ref_crystal

f

ref_ext

f

ref_1:1

2
2

33.33

8.33

8.33

66.66

10.0

10.0

80

MHz

System Frequency

1

External Clock Mode
On-Chip PLL Frequency

f

sys

0

f

ref

/ 32

f

sys(max)

66.66

66.66

f

sys(max)

80
80

MHz

Location Description

Chapter 17 The maximum buffer size of the FEC is 2032 bytes. Replace any mention of the max size

Table 17-2/17-5 In PALR/PAUR entry, delete “(only needed for full duplex flow control)”

Figure 17-23/17-39 Change FRSR to read/write instead of read-only.

25.4.10/25-16 Change CANICR to ICRn.

Table 25-17/25-29 Add the following information to BITERR and ACKERR descriptions: “To clear this bit, first

Table 25-17/25-30 Change bit ordering: ERRINT should be bit 2 and BOFFINT should be bit 1.
Table 25-19/25-32 Change BUFnI field description from “To clear an interrupt flag, first read the flag as a one,

Chapter 33 It is crucial during power-up that VDD never e xceeds VDDH by more that ~0.3V. There are

Table 33-8/33-7 In the PLL Electrical Specifications table, only specs for the 80MHz MCF5282 device w ere

Table 2. MCF5282UM Rev 2.1 & 2.2 Errata (continued)

being 2047 bytes with 2032 bytes.

read it as a one, then write it as a one. Writing zero has no effect.”

then write it as a zero” to “T o clear an interrupt flag, first read the flag as a one, then write
it as a one.”

diode devices between the two voltage domains, and violating this rule can lead to a
latch-up condition.

listed. Insert specs for the 66MHz device in the first 2 rows and also declare symbol
f

, as shown below:

sys(max)

3 Errata for Revision 2.0

Location Description

Table 33-8/33-9 Reference to ‘TA = TL to TH’ was not deleted. Delete.

Table 3. MCF5282UM Rev 2.0 Errata

MCF5282 User’s Manual Errata, Rev. 15

Freescale Semiconductor6