Freescale Semiconductor MCF52277 Reference Manual

MCF52277 Reference Manual

Devices Supported:

MCF52274
MCF52277

Document Number: MCF52277RM

Rev. 1

04/2008

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software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.

Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
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arising out of the application or use of any product or circuit, and specifically
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Semiconductor data sheets and/or specifications can and do vary in different
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parameters, including “Typicals”, must be validated for each customer
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Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
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Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property
of their respective owners.© Freescale Semiconductor, Inc. 2006. All rights
reserved.

MCF52277RM
Rev. 1
04/2008

About This Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxiii

Audience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxiii

Suggested Reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv

General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxvi

ColdFire Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxvi

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxvi

Register Figure Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii

Acronyms and Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxviii

Terminology Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxix

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxxi

Chapter 1

Overview

1.1 MCF5227x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3.1 Version 2 ColdFire Variable-Length RISC Processor . . . . . . . . . . . . . . . . . . . . 1-4

1.3.2 On-chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3.3 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.4 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.5 Chip Configuration Module (CCM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.6 Reset Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.7 System Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.8 Crossbar Switch Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.9 Liquid Crystal Display Controller (LCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.10 ADC and Touch Screen Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.11 Universal Serial Bus (USB) 2.0 On-The-Go (OTG) Controller. . . . . . . . . . . . . . 1-6

1.3.12 SDR/DDR SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.13 FlexBus (External Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.14 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.15 FlexCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.16 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.3.17 Programmable Interrupt Timers (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.3.18 DMA Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.3.19 DMA Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.3.20 Pulse Width Modulation (PWM) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.3.21 Universal Asynchronous Receiver Transmitters (UARTs). . . . . . . . . . . . . . . . . 1-9

1.3.22 I2C Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.3.23 Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.3.24 Edge Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.3.25 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.26 General Purpose I/O interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.27 System Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

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1.3.28 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.4 Memory Map Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.4.1 Internal Peripheral Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.5 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Chapter 2

Signal Descriptions

2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.3 Signal Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3.1 Reset Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3.2 PLL and Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.3.3 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.3.4 FlexBus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.3.5 SDRAM Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.3.6 Serial Boot Facility Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.3.7 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.3.8 DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.3.9 LCD Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.3.10 FlexCAN Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.3.11 Pulse Width Modulation (PWM) Module Signals . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.3.12 Universal Serial Bus (USB) On-the-Go Signals. . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.3.13 Touschreen Controller/ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.3.14 I2C I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.3.15 DMA Serial Peripheral Interface (DSPI) Signals . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.3.16 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.3.17 Synchronous Serial Interface (SSI) Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.3.18 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.3.19 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.3.20 Test Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.3.21 Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Chapter 3

ColdFire Core

3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . . 3-5

3.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.2.5 Program Counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.2.6 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.2.7 Access Control Registers (ACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

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3.2.8 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.2.9 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.2.10 Memory Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.3.1 Version 2 ColdFire Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.3.2 Instruction Set Architecture (ISA_A+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.3.3 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.3.4 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.3.5 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

Chapter 4

Enhanced Multiply-Accumulate Unit (EMAC)

4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.1 MAC Status Register (MACSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.2 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.2.3 Accumulator Registers (ACC0–3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.2.4 Accumulator Extension Registers (ACCext01, ACCext23) . . . . . . . . . . . . . . . . 4-7

4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.3.2 EMAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.3.3 EMAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

4.3.4 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

4.3.5 MAC Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Chapter 5

Cache

5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2.1 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2.2 Access Control Registers (ACR0, ACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.3.1 Interaction with Other Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.3.2 Memory Reference Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.3.3 Cache Coherency and Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.3.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.3.5 Cache Miss Fetch Algorithm/Line Fills. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Chapter 6

Static RAM (SRAM)

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6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.2.1 SRAM Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.3 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.3.1 SRAM Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.3.2 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Chapter 7

Clock Module

7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.2.1 PLL Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.2.2 PLL Status Register (PSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.3.1 PLL Frequency Multiplication Factor Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.3.2 Lock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

7.3.3 Loss-of-Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

7.3.4 System Clock Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

7.3.5 Clock Operation During Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11

Chapter 8

Power Management

8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2.1 Wake-up Control Register (WCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.2.2 Peripheral Power Management Set Register (PPMSR) . . . . . . . . . . . . . . . . . . 8-3

8.2.3 Peripheral Power Management Clear Register (PPMCR). . . . . . . . . . . . . . . . . 8-4

8.2.4 Peripheral Power Management Registers (PPMHR & PPMLR) . . . . . . . . . . . . 8-4

8.2.5 Low-Power Control Register (LPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.3.1 Peripheral Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.3.2 Limp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.3.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.3.4 Peripheral Behavior in Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

Chapter 9

Chip Configuration Module (CCM)

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9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 External Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2.1 BOOTMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2.2 FB_A[21:16] (Reset Configuration Override). . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.3.1 Chip Configuration Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.3.2 Reset Configuration Register (RCON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.3.3 Chip Identification Register (CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.3.4 Miscellaneous Control Register (MISCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.3.5 Clock-Divider Register (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.3.6 USB On-the-Go Controller Status Register (UOCSR). . . . . . . . . . . . . . . . . . . . 9-8

9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.4.1 Reset Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.4.2 Boot Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.4.3 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.4.4 Chip Select Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.4.5 Low Power Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15

Chapter 10

Serial Boot Facility (SBF)

10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.3.1 Serial Boot Facility Status Register (SBFSR) . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.3.2 Serial Boot Facility Control Register (SBFCR) . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.4.1 Serial Initialization and Shift Clock Frequency Adjustment . . . . . . . . . . . . . . . 10-4

10.4.2 Reset Configuration and Optional Boot Load . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.3 Execution Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.5.1 SPI Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.5.2 FAST_READ Feature Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Chapter 11

Reset Controller Module

11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

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11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2.1 RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2.2 RSTOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.3.1 Reset Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.3.2 Reset Status Register (RSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.4.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.4.2 Reset Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.4.3 Concurrent Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

Chapter 12

System Control Module (SCM)

12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.2.1 Master Privilege Register (MPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.2.2 Peripheral Access Control Registers (PACRx) . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.2.3 Core Watchdog Control Register (CWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7

12.2.4 Core Watchdog Service Register (CWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.2.5 SCM Interrupt Status Register (SCMISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.2.6 Burst Configuration Register (BCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

12.2.7 Core Fault Address Register (CFADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.2.8 Core Fault Interrupt Enable Register (CFIER). . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.2.9 Core Fault Location Register (CFLOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

12.2.10 Core Fault Attributes Register (CFATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

12.2.11 Core Fault Data Register (CFDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

12.3.1 Access Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

12.3.2 Core Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

12.3.3 Core Data Fault Recovery Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14

Chapter 13

Crossbar Switch (XBS)

13.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

13.4 Memory Map / Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

13.4.1 XBS Priority Registers (XBS_PRSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

13.4.2 XBS Control Registers (XBS_CRSn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

13.5.1 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

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13.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7

Chapter 14

General Purpose I/O Module

14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.1.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9

14.3.1 Port Output Data Registers (PODR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11

14.3.2 Port Data Direction Registers (PDDR_x). . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12

14.3.3 Port Pin Data/Set Data Registers (PPDSDR_x) . . . . . . . . . . . . . . . . . . . . . . 14-13

14.3.4 Port Clear Output Data Registers (PCLRR_x). . . . . . . . . . . . . . . . . . . . . . . . 14-15

14.3.5 Pin Assignment Registers (PAR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16

14.3.6 FlexBus Mode Select Control Register (MSCR_FLEXBUS) . . . . . . . . . . . . . 14-23

14.3.7 SDRAM Mode Select Control Register (MSCR_SDRAM). . . . . . . . . . . . . . . 14-24

14.3.8 Drive Strength Control Registers (DSCR_x) . . . . . . . . . . . . . . . . . . . . . . . . . 14-25

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26

14.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26

14.4.2 Port Digital I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27

14.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28

Chapter 15

Interrupt Controller Modules

15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.1.1 68K/ColdFire Interrupt Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

15.2.1 Interrupt Pending Registers (IPRHn, IPRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.2.2 Interrupt Mask Register (IMRHn, IMRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

15.2.3 Interrupt Force Registers (INTFRCHn, INTFRCLn). . . . . . . . . . . . . . . . . . . . . 15-6

15.2.4 Interrupt Configuration Register (ICONFIGn) . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

15.2.5 Set Interrupt Mask Register (SIMRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

15.2.6 Clear Interrupt Mask Register (CIMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

15.2.7 Current Level Mask Register (CLMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9

15.2.8 Saved Level Mask Register (SLMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10

15.2.9 Interrupt Control Register (ICR0n, ICR1n, (n = 00, 01, 02, ..., 63)) . . . . . . . . 15-11

15.2.10 Software and Level 1–7 IACK Registers (SWIACKn, L1IACKn–L7IACKn) . . 15-14

15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

15.3.1 Interrupt Controller Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

15.3.2 Prioritization Between Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17

15.3.3 Low-Power Wake-up Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18

15.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18

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15.4.1 Interrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18

Chapter 16

Edge Port Module (EPORT)

16.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1

16.2 Low-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.3 Interrupt/GPIO Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.4.1 EPORT Pin Assignment Register (EPPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.4.2 EPORT Data Direction Register (EPDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.4.3 Edge Port Interrupt Enable Register (EPIER) . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

16.4.4 Edge Port Data Register (EPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

16.4.5 Edge Port Pin Data Register (EPPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

16.4.6 Edge Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

Chapter 17

Enhanced Direct Memory Access (eDMA)

17.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.4.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.4.2 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

17.5 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

17.5.1 External Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

17.6 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.6.1 eDMA Control Register (EDMA_CR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.6.2 eDMA Error Status Register (EDMA_ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5

17.6.3 eDMA Enable Request Register (EDMA_ERQ) . . . . . . . . . . . . . . . . . . . . . . . 17-8

17.6.4 eDMA Enable Error Interrupt Registers (EDMA_EEI) . . . . . . . . . . . . . . . . . . . 17-9

17.6.5 eDMA Set Enable Request Register (EDMA_SERQ) . . . . . . . . . . . . . . . . . . 17-10

17.6.6 eDMA Clear Enable Request Register (EDMA_CERQ) . . . . . . . . . . . . . . . . 17-10

17.6.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEI) . . . . . . . . . . . . . . 17-11

17.6.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEI) . . . . . . . . . . . . . 17-11

17.6.9 eDMA Clear Interrupt Request Register (EDMA_CINT) . . . . . . . . . . . . . . . . 17-12

17.6.10 eDMA Clear Error Register (EDMA_CERR) . . . . . . . . . . . . . . . . . . . . . . . . . 17-13

17.6.11 eDMA Set START Bit Register (EDMA_SSRT). . . . . . . . . . . . . . . . . . . . . . . 17-13

17.6.12 eDMA Clear DONE Status Bit Register (EDMA_CDNE). . . . . . . . . . . . . . . . 17-14

17.6.13 eDMA Interrupt Request Register (EDMA_INT) . . . . . . . . . . . . . . . . . . . . . . 17-15

17.6.14 eDMA Error Register (EDMA_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15

17.6.15 eDMA Channel n Priority Registers (DCHPRIn) . . . . . . . . . . . . . . . . . . . . . . 17-16

17.6.16 Transfer Control Descriptors (TCDn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

17.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24

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17.7.1 eDMA Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24

17.7.2 eDMA Basic Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25

17.8 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28

17.8.1 eDMA Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28

17.8.2 DMA Programming Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31

17.8.3 DMA Arbitration Mode Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31

17.8.4 DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32

17.8.5 eDMA TCDn Status Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35

17.8.6 Channel Linking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36

17.8.7 Dynamic Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37

Chapter 18

FlexBus

18.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

18.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

18.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.2.1 Address & Data Buses (FB_A[23:0], FB_D[31:0]). . . . . . . . . . . . . . . . . . . . . . 18-2

18.2.2 Chip-Selects (FB_CS[5:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.2.3 Byte Enables/Byte Write Enables (FB_BE/BWE[3:0]) . . . . . . . . . . . . . . . . . . . 18-3

18.2.4 Output Enable (FB_OE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.2.5 Read/Write (FB_R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.2.6 Transfer Start (FB_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.2.7 Transfer Acknowledge (FB_TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

18.3.1 Chip-Select Address Registers (CSAR0–CSAR5) . . . . . . . . . . . . . . . . . . . . . 18-4

18.3.2 Chip-Select Mask Registers (CSMR0–CSMR5) . . . . . . . . . . . . . . . . . . . . . . . 18-5

18.3.3 Chip-Select Control Registers (CSCR0–CSCR5) . . . . . . . . . . . . . . . . . . . . . . 18-6

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9

18.4.1 Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9

18.4.2 Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10

18.4.3 Data Byte Alignment and Physical Connections . . . . . . . . . . . . . . . . . . . . . . 18-11

18.4.4 Bus Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11

18.4.5 FlexBus Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12

18.4.6 Burst Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23

18.4.7 Misaligned Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27

18.4.8 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28

Chapter 19

SDRAM Controller (SDRAMC)

19.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

19.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.1.3 Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

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19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

19.3 Interface Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

19.3.1 Supported Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

19.3.2 SDRAM SDR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10

19.3.3 SDRAM DDR Component Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12

19.3.4 DDR SDRAM Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12

19.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14

19.4.1 SDRAM Mode/Extended Mode Register (SDMR) . . . . . . . . . . . . . . . . . . . . . 19-14

19.4.2 SDRAM Control Register (SDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15

19.4.3 SDRAM Configuration Register 1 (SDCFG1) . . . . . . . . . . . . . . . . . . . . . . . . 19-17

19.4.4 SDRAM Configuration Register 2 (SDCFG2) . . . . . . . . . . . . . . . . . . . . . . . . 19-19

19.4.5 SDRAM Chip Select Configuration Registers (SDCSn) . . . . . . . . . . . . . . . . 19-20

19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21

19.5.1 SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21

19.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26

19.6.1 Page Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27

19.6.2 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28

Chapter 20

Universal Serial Bus Interface – On-The-Go Module

20.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

20.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

20.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2

20.1.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2

20.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4

20.2.1 USB OTG Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4

20.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

20.3.1 Module Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8

20.3.2 Device/Host Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11

20.3.3 Capability Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12

20.3.4 Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16

20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45

20.4.1 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45

20.4.2 DMA Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45

20.4.3 FIFO RAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45

20.4.4 Physical Layer (PHY) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45

20.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-46

20.5.1 Host Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-46

20.5.2 Device Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-47

20.5.3 Device Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-54

20.5.4 Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-72

20.5.5 Deviations from the EHCI Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-73

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Chapter 21

Liquid Crystal Display Controller (LCDC)

21.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1

21.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1

21.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1

21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

21.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

21.3.1 LCDC Screen Start Address Register (LCD_SSAR). . . . . . . . . . . . . . . . . . . . 21-4

21.3.2 LCDC Size Register (LCD_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5

21.3.3 LCDC Virtual Page Width Register (LCD_VPW) . . . . . . . . . . . . . . . . . . . . . . . 21-5

21.3.4 LCDC Cursor Position Register (LCD_CPR). . . . . . . . . . . . . . . . . . . . . . . . . . 21-6

21.3.5 LCDC Cursor Width Height and Blink Register (LCD_CWHB) . . . . . . . . . . . . 21-7

21.3.6 LCDC Color Cursor Mapping Register (LCD_CCMR) . . . . . . . . . . . . . . . . . . . 21-8

21.3.7 LCDC Panel Configuration Register (LCD_PCR) . . . . . . . . . . . . . . . . . . . . . . 21-9

21.3.8 LCDC Horizontal Configuration Register (LCD_HCR). . . . . . . . . . . . . . . . . . 21-12

21.3.9 LCDC Vertical Configuration Register (LCD_VCR) . . . . . . . . . . . . . . . . . . . . 21-12

21.3.10 LCDC Panning Offset Register (LCD_POR) . . . . . . . . . . . . . . . . . . . . . . . . . 21-13

21.3.11 LCDC Sharp Configuration Register (LCD_SCR) . . . . . . . . . . . . . . . . . . . . . 21-14

21.3.12 LCDC PWM Contrast Control Register (LCD_PCCR). . . . . . . . . . . . . . . . . . 21-16

21.3.13 LCDC DMA Control Register (LCD_DCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16

21.3.14 LCDC Refresh Mode Control Register (LCD_RMCR). . . . . . . . . . . . . . . . . . 21-17

21.3.15 LCDC Interrupt Configuration Register (LCD_ICR). . . . . . . . . . . . . . . . . . . . 21-18

21.3.16 LCDC Interrupt Enable Register (LCD_IER) . . . . . . . . . . . . . . . . . . . . . . . . . 21-19

21.3.17 LCDC Interrupt Status Register (LCD_ISR) . . . . . . . . . . . . . . . . . . . . . . . . . 21-20

21.3.18 LCDC Graphic Window Start Address Register (LCD_GWSAR) . . . . . . . . . 21-22

21.3.19 LCDC Graphic Window Size Register (LCD_GWSR) . . . . . . . . . . . . . . . . . . 21-22

21.3.20 LCDC Graphic Window Virtual Page Width Register (LCD_GWVPW) . . . . . 21-23

21.3.21 LCDC Graphic Window Panning Offset Register (LCD_GWPOR) . . . . . . . . 21-23

21.3.22 LCDC Graphic Window Position Register (LCD_GWPR) . . . . . . . . . . . . . . . 21-24

21.3.23 LCDC Graphic Window Control Register (LCD_GWCR). . . . . . . . . . . . . . . . 21-24

21.3.24 LCDC Graphic Window DMA Control Register (LCD_GWDCR). . . . . . . . . . 21-26

21.3.25 Mapping RAM Registers (BGLUT and GWLUT) . . . . . . . . . . . . . . . . . . . . . . 21-26

21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29

21.4.1 LCD Screen Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29

21.4.2 Graphic Window on Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30

21.4.3 Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31

21.4.4 Display Data Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31

21.4.5 Black-and-White Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33

21.4.6 Gray-Scale Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33

21.4.7 Color Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-34

21.4.8 Frame Rate Modulation Control (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-36

21.4.9 Panel Interface Signals and Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-37

21.4.10 8 bpp Mode Color STN Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-40

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Chapter 22

Touchscreen Controller/Analog-to-Digital Converter

22.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1

22.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

22.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

22.3.1 ASP Control Register (ASP_CR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4

22.3.2 ASP Sample Setting Register (ASP_SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7

22.3.3 ASP Sample Timing Register (ASP_TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

22.3.4 ASP Interrupt/DMA Control Register (ASP_ICR) . . . . . . . . . . . . . . . . . . . . . . 22-9

22.3.5 ASP Status Register (ASP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10

22.3.6 ASP Sample FIFO (ASP_SFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11

22.3.7 ASP FIFO Pointer Register (ASP_FIFOP) . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12

22.3.8 ASP Clock Divider Register (ASP_CLKD). . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13

22.4 Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13

22.4.1 Touchscreen Controller Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14

22.4.2 General ADC Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16

22.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17

22.5.1 Touchscreen Mode 00. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17

22.5.2 Touchscreen Mode 01—Single Round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19

22.5.3 Touchscreen Mode 01—Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20

22.5.4 Touchscreen Mode 10—Single Round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21

22.5.5 Touchscreen Mode 10—Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22

22.5.6 Touchscreen Mode 11—Single Round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23

22.5.7 Touchscreen Mode 11—Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24

22.5.8 General Purpose ADC—Single Round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26

22.5.9 General Purpose ADC—Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26

22.5.10 Touchscreen Calibration—Single Round. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27

22.5.11 Touchscreen Calibration – Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28

Chapter 23

FlexCAN

23.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1

23.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1

23.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

23.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5

23.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5

23.3.1 FlexCAN Configuration Register (CANMCR) . . . . . . . . . . . . . . . . . . . . . . . . . 23-6

23.3.2 FlexCAN Control Register (CANCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9

23.3.3 FlexCAN Free Running Timer Register (TIMER) . . . . . . . . . . . . . . . . . . . . . 23-11

23.3.4 Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK). . . . . . . . . . . . . 23-12

23.3.5 FlexCAN Error Counter Register (ERRCNT). . . . . . . . . . . . . . . . . . . . . . . . . 23-13

23.3.6 FlexCAN Error and Status Register (ERRSTAT). . . . . . . . . . . . . . . . . . . . . . 23-14

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23.3.7 Interrupt Mask Register (IMASK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16

23.3.8 Interrupt Flag Register (IFLAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17

23.3.9 Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17

23.3.10 Rx Individual Masking Registers (RXIMR0–15). . . . . . . . . . . . . . . . . . . . . . . 23-21

23.3.11 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22

23.3.12 Transmit Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22

23.3.13 Arbitration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23

23.3.14 Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23

23.3.15 Matching Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24

23.3.16 Message Buffer Managing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25

23.3.17 CAN Protocol Related Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-27

23.3.18 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-28

23.3.19 Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-28

23.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-30

23.4.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-31

Chapter 24

Pulse-Width Modulation (PWM) Module

24.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1

24.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1

24.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2

24.2.1 PWM Enable Register (PWME). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

24.2.2 PWM Polarity Register (PWMPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4

24.2.3 PWM Clock Select Register (PWMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4

24.2.4 PWM Prescale Clock Select Register (PWMPRCLK) . . . . . . . . . . . . . . . . . . . 24-5

24.2.5 PWM Center Align Enable Register (PWMCAE) . . . . . . . . . . . . . . . . . . . . . . . 24-6

24.2.6 PWM Control Register (PWMCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6

24.2.7 PWM Scale A Register (PWMSCLA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7

24.2.8 PWM Scale B Register (PWMSCLB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8

24.2.9 PWM Channel Counter Registers (PWMCNTn) . . . . . . . . . . . . . . . . . . . . . . . 24-9

24.2.10 PWM Channel Period Registers (PWMPERn) . . . . . . . . . . . . . . . . . . . . . . . 24-10

24.2.11 PWM Channel Duty Registers (PWMDTYn) . . . . . . . . . . . . . . . . . . . . . . . . . 24-10

24.2.12 PWM Shutdown Register (PWMSDN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11

24.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12

24.3.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12

24.3.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14

Chapter 25

Synchronous Serial Interface (SSI)

25.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1

25.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

25.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

25.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

25.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

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25.2.1 SSI_CLKIN — SSI Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.2.2 SSI_BCLK — Serial Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.2.3 SSI_MCLK — Serial Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.2.4 SSI_FS — Serial Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.2.5 SSI_RXD — Serial Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.2.6 SSI_TXD — Serial Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7

25.3.1 SSI Transmit Data Registers 0 & 1 (SSI_TX0/1). . . . . . . . . . . . . . . . . . . . . . . 25-8

25.3.2 SSI Transmit FIFO 0 & 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

25.3.3 SSI Transmit Shift Register (TXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

25.3.4 SSI Receive Data Registers 0 & 1 (SSI_RX0/1) . . . . . . . . . . . . . . . . . . . . . . 25-10

25.3.5 SSI Receive FIFO 0 & 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11

25.3.6 SSI Receive Shift Register (RXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11

25.3.7 SSI Control Register (SSI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12

25.3.8 SSI Interrupt Status Register (SSI_ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.3.9 SSI Interrupt Enable Register (SSI_IER). . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20

25.3.10 SSI Transmit Configuration Register (SSI_TCR). . . . . . . . . . . . . . . . . . . . . . 25-21

25.3.11 SSI Receive Configuration Register (SSI_RCR) . . . . . . . . . . . . . . . . . . . . . . 25-23

25.3.12 SSI Clock Control Register (SSI_CCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24

25.3.13 SSI FIFO Control/Status Register (SSI_FCSR). . . . . . . . . . . . . . . . . . . . . . . 25-25

25.3.14 SSI AC97 Control Register (SSI_ACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27

25.3.15 SSI AC97 Command Address Register (SSI_ACADD). . . . . . . . . . . . . . . . . 25-28

25.3.16 SSI AC97 Command Data Register (SSI_ACDAT). . . . . . . . . . . . . . . . . . . . 25-29

25.3.17 SSI AC97 Tag Register (SSI_ATAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-29

25.3.18 SSI Transmit Time Slot Mask Register (SSI_TMASK) . . . . . . . . . . . . . . . . . 25-29

25.3.19 SSI Receive Time Slot Mask Register (SSI_RMASK). . . . . . . . . . . . . . . . . . 25-30

25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30

25.4.1 Detailed Operating Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30

25.4.2 SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43

25.4.3 External Frame and Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46

25.4.4 Supported Data Alignment Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46

25.4.5 Receive Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-48

25.4.6 Transmit Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-48

25.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49

Chapter 26

Real-Time Clock

26.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1

26.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1

26.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

26.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

26.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

26.3.1 RTC Hours and Minutes Counter Register (RTC_HOURMIN) . . . . . . . . . . . . 26-3

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26.3.2 RTC Seconds Counter Register (RTC_SECONDS) . . . . . . . . . . . . . . . . . . . . 26-4

26.3.3 RTC Hours and Minutes Alarm Register (RTC_ALRM_HM) . . . . . . . . . . . . . . 26-4

26.3.4 RTC Seconds Alarm Register (RTC_ALRM_SEC) . . . . . . . . . . . . . . . . . . . . . 26-5

26.3.5 RTC Control Register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5

26.3.6 RTC Interrupt Status Register (RTC_ISR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6

26.3.7 RTC Interrupt Enable Register (RTC_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7

26.3.8 RTC Stopwatch Minutes Register (RTC_STPWCH) . . . . . . . . . . . . . . . . . . . . 26-9

26.3.9 RTC Days Counter Register (RTC_DAYS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9

26.3.10 RTC Day Alarm Register (RTC_ALRM_DAY) . . . . . . . . . . . . . . . . . . . . . . . . . 26-9

26.3.11 RTC General Oscillator Clock Upper Register (RTC_GOCU). . . . . . . . . . . . 26-10

26.3.12 RTC General Oscillator Clock Lower Register (RTC_GOCL) . . . . . . . . . . . . 26-10

26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11

26.4.1 Clock Generation and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11

26.4.2 Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12

26.4.3 Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12

26.4.4 Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13

26.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13

26.5.1 Flow Chart of RTC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13

26.5.2 Programming the Alarm or Time-of-Day Registers . . . . . . . . . . . . . . . . . . . . 26-13

Chapter 27

Programmable Interrupt Timers (PIT0–PIT1)

27.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1

27.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1

27.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1

27.1.3 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1

27.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2

27.2.1 PIT Control and Status Register (PCSRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3

27.2.2 PIT Modulus Register (PMRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4

27.2.3 PIT Count Register (PCNTRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5

27.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5

27.3.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5

27.3.2 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6

27.3.3 Timeout Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6

27.3.4 Interrupt Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6

Chapter 28

DMA Timers (DTIM0–DTIM3)

28.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1

28.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1

28.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2

28.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2

28.2.1 DMA Timer Mode Registers (DTMRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3

28.2.2 DMA Timer Extended Mode Registers (DTXMRn) . . . . . . . . . . . . . . . . . . . . . 28-4

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28.2.3 DMA Timer Event Registers (DTERn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5

28.2.4 DMA Timer Reference Registers (DTRRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6

28.2.5 DMA Timer Capture Registers (DTCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7

28.2.6 DMA Timer Counters (DTCNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7

28.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8

28.3.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8

28.3.2 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8

28.3.3 Reference Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8

28.3.4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8

28.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9

28.4.1 Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9

28.4.2 Calculating Time-Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10

Chapter 29

DMA Serial Peripheral Interface (DSPI)

29.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1

29.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1

29.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1

29.1.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2

29.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3

29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

29.2.1 Signal Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

29.2.2 Peripheral Chip Select/Slave Select (DSPI_PCS0/SS). . . . . . . . . . . . . . . . . . 29-4

29.2.3 Peripheral Chip Selects 2,4 (DSPI_PCS[2,4]). . . . . . . . . . . . . . . . . . . . . . . . . 29-4

29.2.4 Serial Input (DSPI_SIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

29.2.5 Serial Output (DSPI_SOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

29.2.6 Serial Clock (DSPI_SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.3.1 DSPI Module Configuration Register (DSPI_MCR). . . . . . . . . . . . . . . . . . . . . 29-5

29.3.2 DSPI Transfer Count Register (DSPI_TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8

29.3.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTARn) . . . . . . . . 29-8

29.3.4 DSPI Status Register (DSPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13

29.3.5 DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER) . . 29-15

29.3.6 DSPI PUSH TX FIFO Register (DSPI_PUSHR) . . . . . . . . . . . . . . . . . . . . . . 29-16

29.3.7 DSPI POP RX FIFO Register (DSPI_POPR) . . . . . . . . . . . . . . . . . . . . . . . . 29-18

29.3.8 DSPI Transmit FIFO Registers 0–15 (DSPI_TXFRn) . . . . . . . . . . . . . . . . . . 29-18

29.3.9 DSPI Receive FIFO Registers 0–15 (DSPI_RXFRn) . . . . . . . . . . . . . . . . . . 29-19

29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-20

29.4.1 Start and Stop of DSPI Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-20

29.4.2 Serial Peripheral Interface (SPI) Configuration . . . . . . . . . . . . . . . . . . . . . . . 29-21

29.4.3 DSPI Baud Rate and Clock Delay Generation . . . . . . . . . . . . . . . . . . . . . . . 29-24

29.4.4 Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-26

29.4.5 Continuous Serial Communications Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 29-32

29.4.6 Interrupts/DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-33

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29.4.7 Power Saving Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-35

29.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36

29.5.1 How to Change Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36

29.5.2 Switching Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36

29.5.3 Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36

29.5.4 Delay Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-37

29.5.5 Calculation of FIFO Pointer Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38

Chapter 30

UART Modules

30.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1

30.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1

30.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2

30.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3

30.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3

30.3.1 UART Mode Registers 1 (UMR1n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5

30.3.2 UART Mode Register 2 (UMR2n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6

30.3.3 UART Status Registers (USRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7

30.3.4 UART Clock Select Registers (UCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9

30.3.5 UART Command Registers (UCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9

30.3.6 UART Receive Buffers (URBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11

30.3.7 UART Transmit Buffers (UTBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12

30.3.8 UART Input Port Change Registers (UIPCRn) . . . . . . . . . . . . . . . . . . . . . . . 30-12

30.3.9 UART Auxiliary Control Register (UACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13

30.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn) . . . . . . . . . . . . . . . . 30-13

30.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) . . . . . . . . . . . . . . . 30-15

30.3.12 UART Input Port Register (UIPn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15

30.3.13 UART Output Port Command Registers (UOP1n/UOP0n) . . . . . . . . . . . . . . 30-16

30.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16

30.4.1 Transmitter/Receiver Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16

30.4.2 Transmitter and Receiver Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . 30-18

30.4.3 Looping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22

30.4.4 Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-24

30.4.5 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26

30.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26

30.5.1 Interrupt and DMA Request Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26

30.5.2 UART Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-28

Chapter 31

2

C Interface

I

31.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1

31.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1

31.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2

31.1.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2

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31.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3

31.2.1 I2C Address Register (I2ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3

31.2.2 I2C Frequency Divider Register (I2FDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3

31.2.3 I2C Control Register (I2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4

31.2.4 I2C Status Register (I2SR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6

2

31.2.5 I

C Data I/O Register (I2DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7

31.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7

31.3.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7

31.3.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8

31.3.3 Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8

31.3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9

31.3.5 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9

31.3.6 Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9

31.3.7 Clock Synchronization and Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11

31.3.8 Handshaking and Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12

31.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12

31.4.1 Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12

31.4.2 Generation of START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12

31.4.3 Post-Transfer Software Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13

31.4.4 Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13

31.4.5 Generation of Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14

31.4.6 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14

31.4.7 Arbitration Lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14

Chapter 32

Debug Module

32.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1

32.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1

32.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1

32.2 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2

32.3 Real-Time Trace Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3

32.3.1 Begin Execution of Taken Branch (PST = 0x5) . . . . . . . . . . . . . . . . . . . . . . . . 32-4

32.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5

32.4.1 Shared Debug Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7

32.4.2 Configuration/Status Register (CSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7

32.4.3 BDM Address Attribute Register (BAAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-10

32.4.4 Address Attribute Trigger Register (AATR) . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11

32.4.5 Trigger Definition Register (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12

32.4.6 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) . . . . . . . . . 32-15

32.4.7 Address Breakpoint Registers (ABLR, ABHR) . . . . . . . . . . . . . . . . . . . . . . . 32-17

32.4.8 Data Breakpoint and Mask Registers (DBR, DBMR). . . . . . . . . . . . . . . . . . . 32-18

32.5 Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19

32.5.1 CPU Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19

32.5.2 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-20

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32.5.3 BDM Command Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-22

32.6 Real-Time Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-40

32.6.1 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-40

32.6.2 Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 32-42

32.7 Processor Status, Debug Data Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-43

32.7.1 User Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-43

32.7.2 Supervisor Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-48

32.8 Freescale-Recommended BDM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-49

Chapter 33

IEEE 1149.1 Test Access Port (JTAG)

33.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1

33.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1

33.1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2

33.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2

33.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2

33.2.1 JTAG Enable (JTAG_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2

33.2.2 Test Clock Input (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3

33.2.3 Test Mode Select/Breakpoint (TMS/BKPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3

33.2.4 Test Data Input/Development Serial Input (TDI/DSI). . . . . . . . . . . . . . . . . . . . 33-3

33.2.5 Test Reset/Development Serial Clock (TRST/DSCLK) . . . . . . . . . . . . . . . . . . 33-4

33.2.6 Test Data Output/Development Serial Output (TDO/DSO) . . . . . . . . . . . . . . . 33-4

33.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4

33.3.1 Instruction Shift Register (IR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4

33.3.2 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5

33.3.3 Bypass Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5

33.3.4 TEST_CTRL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5

33.3.5 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6

33.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6

33.4.1 JTAG Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6

33.4.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6

33.4.3 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7

33.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10

33.5.1 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10

33.5.2 Nonscan Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor xxi

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductorxxii

About This Book

The primary objective of this reference manual is to define the MCF52277 processor for software and
hardware developers. In addition, this manual supports the MCF52274. This book is written from the
perspective of the MCF52277, and unless otherwise noted, the information applies also to the MCF52274.
This device has the same functionality as the MCF52277; any differences in data regarding bus timing,
signal behavior, and AC, DC, and thermal characteristics are detailed in the device data sheet
(MCF52277DS). Refer to Table 1-1 for a summary of the differences.

The information in this book is subject to change without notice, as described in the disclaimers on the title
page. As with any technical documentation, the reader needs to make sure to use the most recent version
of the documentation.

To locate any published errata or updates for this document, refer to the world-wide web at

http://www.freescale.com/coldfire.

Portions of Chapter 20, “Universal Serial Bus Interface – On-The-Go Module,” relating to the EHCI
specification are Copyright © Intel Corporation 1999-2001. The EHCI specification is provided as is with
no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any
particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Intel
disclaims all liability, including liability for infringement of any proprietary rights, relating to use of
information in the EHCI specification. Intel may make changes to the EHCI specifications at any time,
without notice.

Audience

This manual is intended for system software and hardware developers and applications programmers who
want to develop products with the MCF52277 processor. It is assumed that the reader understands
operating systems, microprocessor system design, basic principles of software and hardware, and basic

®

details of the ColdFire

architecture.

Organization

Following is a summary and brief description of the major sections of this manual:

• Chapter 1, “Overview,” includes general descriptions of the modules and features incorporated in
the device while focusing on new features.

• Chapter 2, “Signal Descriptions,” describes device signals. It includes a listing of signals
characterizing each signal as an input or output, defines its state at reset, and identifies whether a
pull-up resistor should be used.

• Chapter 3, “ColdFire Core,” provides microprocessor core overview. The chapter describes the
organization of the Version 2 (V2) ColdFire processor core and an overview of the programming
models as they are implemented on the device.

MCF52277 Reference Manual, Rev. 0

Freescale Semiconductor xxiii

• Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC),” describes the multiply/accumulate
unit, which executes integer multiply, multiply-accumulate, and miscellaneous register
instructions. The EMAC is integrated into the operand execution pipeline (OEP).

• Chapter 5, “Cache,” describes cache implementation, including organization, configuration, and
coherency. It describes cache operations and how the cache interacts with other memory structures.

• Chapter 6, “Static RAM (SRAM),” describes the on-chip static RAM (SRAM) implementation,
covers general operations, configuration, and initialization. It also provides information and
examples of how to minimize power consumption when using the SRAM.

• Chapter 7, “Clock Module,” describes the device’s different clocking methods. It also describes
clock-module operation in low power modes.

• Chapter 8, “Power Management,” describes the low power operation of the device and peripheral
behavior in low-power modes.

• Chapter 9, “Chip Configuration Module (CCM),” details the various devices operating
configurations and provides a description of signals used by the CCM and a programming model.

• Chapter 10, “Serial Boot Facility (SBF),” describes the interface to an external SPI memory that
reads configuration data and boot code during the processor-reset sequence.

• Chapter 11, “Reset Controller Module,” describes the operation of the reset controller module,
detailing the different types of reset that can occur.

• Chapter 12, “System Control Module (SCM),” describes the functionality of the SCM, which
provides the programming model for peripheral-access control, the software core watchdog timer
(CWT), and the generic access error information.

• Chapter 13, “Crossbar Switch (XBS),” details the interaction between bus masters and bus slaves
within the device, including arbitration schemes.

• Chapter 14, “General Purpose I/O Module,” describes the operation and programming model of
the general purpose I/O (GPIO) ports on the device.

• Chapter 15, “Interrupt Controller Modules,” describes interrupt controller operation. Includes
descriptions of the registers in the interrupt controller memory map and the interrupt priority
scheme.

• Chapter 16, “Edge Port Module (EPORT),” describes EPORT module functionality, including
operation in low-power mode.

• Chapter 17, “Enhanced Direct Memory Access (eDMA),” describes the direct memory access
(DMA) controller module and provides an overview of the module and describes in detail its
signals and registers. The latter sections of this chapter describe operations, features, and supported
data transfer modes in detail.

• Chapter 18, “FlexBus,” describes data-transfer operations, chip-select operation, error conditions,
bus arbitration, and reset operations.

• Chapter 19, “SDRAM Controller (SDRAMC),” describes the configuration and operation of the
SDRAM controller. It begins with a general description and includes a description of signals
involved in DRAM operations. The remainder of the chapter describes the programming model
and signal timing, as well as the command set required for synchronous operations.

MCF52277 Reference Manual, Rev. 0

xxiv Freescale Semiconductor

• Chapter 20, “Universal Serial Bus Interface – On-The-Go Module,” provides an overview of the
universal serial bus (USB) On-the-Go module. The USB Specification, Revision 2.0 is a
recommended supplement to this chapter.

• Chapter 21, “Liquid Crystal Display Controller (LCDC),” describes the operation and
programming model of the LCD controller.

• Chapter 22, “Touchscreen Controller/Analog-to-Digital Converter,” describes operation of the
analog signal processor that may be configured as a touchscreen controller or general-purpose
ADC.

• Chapter 23, “FlexCAN,” describes the implementation of the controller area network (CAN)
protocol. This chapter describes FlexCAN module operation and provides a programming model.

• Chapter 24, “Pulse-Width Modulation (PWM) Module,” describes the configuration and operation
of the pulse width modulation (PWM) module. It includes a block diagram, programming model,
and functional description.

• Chapter 25, “Synchronous Serial Interface (SSI),” describes SSI module operation and provides a
programming model.

• Chapter 26, “Real-Time Clock,” describes the real-time clock module operation and provides a
programming model.

• Chapter 27, “Programmable Interrupt Timers (PIT0–PIT1),” describes the functionality of the PIT
timers, including operation in low-power mode.

• Chapter 28, “DMA Timers (DTIM0–DTIM3),” describes the configuration and operation of the
DMA timer modules. These 32-bit timers provide input-capture and reference-compare
capabilities with optional signaling of events using interrupts or triggers. This chapter also provides
programming examples.

• Chapter 29, “DMA Serial Peripheral Interface (DSPI),” provides a feature-set overview and an
operation description, including details of the DSPI’s internal storage organization. The chapter
concludes with the programming model and a timing diagram.

• Chapter 30, “UART Modules,” describes the use of the universal asynchronous
receiver/transmitters (UARTs) implemented on the device and includes programming examples.

2

• Chapter 31, “I2C Interface,” describes the I

C module, including I2C protocol, clock

synchronization, and I2C programming model registers.

• Chapter 32, “Debug Module,” describes the hardware debug support in the device.

• Chapter 33, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the
Joint Test Action Group (JTAG) implementation. It describes those items required by the IEEE

1149.1 standard and provides additional information specific to the device. For internal details and
sample applications, see the IEEE 1149.1 document.

Suggested Reading

This section lists additional reading that provides background for the information in this manual as well as
general information about ColdFire architecture.

MCF52277 Reference Manual, Rev. 0

Freescale Semiconductor xxv

General Information

Useful information about the ColdFire architecture and computer architecture in general:

• ColdFire Programmers Reference Manual (MCF5200PRM)

• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross
Bannatyne, Joseph D. Greenfield

• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David
A. Patterson.

• Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A.
Patterson and John L. Hennessy.

ColdFire Documentation

ColdFire documentation is available from the sources listed on the back cover of this manual, as well as
our web site, http://www.freescale.com/coldfire.

• Reference manuals (formerly called user’s manuals)—These books provide details about
individual ColdFire implementations and are intended to be used in conjunction with the ColdFire

Programmers Reference Manual.

• Addenda/errata to reference manuals—Because some processors have follow-on parts, an
addendum is provided that describes the additional features and functionality changes. Also, if
mistakes are found within a reference manual, an errata document will be issued before the next
published release of the reference manual. These addenda/errata are intended for use with the
corresponding reference manuals.

• Data sheets—Data sheets provide specific information regarding pin-out diagrams, bus timing,
signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations.

• Product briefs—Each device has a product brief that provides an overview of its features. This
document is roughly equivalent to the overview (Chapter 1) of a device’s reference manual.

• Application notes—These short documents address specific design issues useful to programmers
and engineers working with Freescale Semiconductor processors.

Additional literature is published as new processors become available. For a current list of ColdFire
documentation, refer to http://www.freescale.com/coldfire.

Conventions

This document uses the following notational conventions:

cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value of

one, it is said to be set.

MNEMONICS In text, instruction mnemonics are shown in uppercase.

mnemonics In code and tables, instruction mnemonics are shown in lowercase.

italics Italics indicate variable command parameters.

Book titles in text are set in italics.

0x0 Prefix to denote hexadecimal number

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xxvi Freescale Semiconductor

0b0 Prefix to denote binary number

REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges

appear in brackets. For example, RAMBAR[BA] identifies the base address field
in the RAM base address register.

nibble A 4-bit data unit

byte An 8-bit data unit

word A 16-bit data unit

1

longword A 32-bit data unit

x In some contexts, such as signal encodings, x indicates a don’t care.

n Used to express an undefined numerical value

~ NOT logical operator

& AND logical operator

| OR logical operator

|| Field concatenation operator

OVERBAR An overbar indicates that a signal is active-low.

Register Figure Conventions

This document uses the following conventions for the register reset values:

— Undefined at reset.

u Unaffected by reset.

[signal_name] Reset value is determined by the polarity of the indicated signal.

The following register fields are used:

R 0 Indicates a reserved bit field in a memory-mapped register. These bits are always read as zeros.

W

R 1 Indicates a reserved bit field in a memory-mapped register. These bits are always read as ones.

W

R FIELDNAME Indicates a read/write bit.

W

R FIELDNAME Indicates a read-only bit field in a memory-mapped register.

W

R Indicates a write-only bit field in a memory-mapped register.

W FIELDNAME

1

The only exceptions to this appear in the discussion of serial communication modules that support variable-length data

transmission units. To simplify the discussion these units are referred to as words regardless of length.

MCF52277 Reference Manual, Rev. 0

Freescale Semiconductor xxvii

R FIELDNAME Write 1 to clear: indicates that writing a 1 to this bit field clears it.

Ww1c

R 0 Indicates a self-clearing bit.

W FIELDNAME

Acronyms and Abbreviations

Table i lists acronyms and abbreviations used in this document.

Table i. Acronyms and Abbreviated Terms

Ter m Me a ning

ADC Analog-to-digital conversion

ALU Arithmetic logic unit

BDM Background debug mode

BIST Built-in self test

BSDL Boundary-scan description language

CODEC Code/decode

DAC Digital-to-analog conversion

DMA Direct memory access

DSP Digital signal processing

EA Effective address

FIFO First-in, first-out

GPIO General-purpose I/O

2

C Inter-integrated circuit

I

IEEE Institute for Electrical and Electronics Engineers

IFP Instruction fetch pipeline

IPL Interrupt priority level

JEDEC Joint Electron Device Engineering Council

JTAG Joint Test Action Group

LIFO Last-in, first-out

LRU Least recently used

LSB Least-significant byte

lsb Least-significant bit

MAC Multiply accumulate unit, also Media access controller

MSB Most-significant byte

msb Most-significant bit

MCF52277 Reference Manual, Rev. 0

xxviii Freescale Semiconductor

Table i. Acronyms and Abbreviated Terms (continued)

Ter m Me a ning

Mux Multiplex

NOP No operation

OEP Operand execution pipeline

PC Program counter

PLIC Physical layer interface controller

PLL Phase-locked loop

POR Power-on reset

RISC Reduced instruction set computing

Rx Receive

SOF Start of frame

TAP Test access port

TTL Transistor transistor logic

Tx Transmit

UART Universal asynchronous/synchronous receiver transmitter

USB Universal serial bus

Terminology Conventions

Table ii shows terminology conventions used throughout this document.

Table ii. Notational Conventions

Instruction Operand Syntax

Opcode Wildcard

cc Logical condition (example: NE for not equal)

Register Specifications

An Any address register n (example: A3 is address register 3)

Ay,Ax Source and destination address registers, respectively

Dn Any data register n (example: D5 is data register 5)

Dy,Dx Source and destination data registers, respectively

Rc Any control register (example VBR is the vector base register)

Rm MAC registers (ACC, MAC, MASK)

Rn Any address or data register

Rw Destination register w (used for MAC instructions only)

Ry,Rx Any source and destination registers, respectively

MCF52277 Reference Manual, Rev. 0

Freescale Semiconductor xxix

Table ii. Notational Conventions (continued)

Instruction Operand Syntax

Xi Index register i (can be an address or data register: Ai, Di)

Miscellaneous Operands

#<data> Immediate data following the 16-bit operation word of the instruction

<ea> Effective address

<ea>y,<ea>x Source and destination effective addresses, respectively

<label> Assembly language program label

<list> List of registers for MOVEM instruction (example: D3–D0)

<shift> Shift operation: shift left (<<), shift right (>>)

<size> Operand data size: byte (B), word (W), longword (L)

bc Instruction and data caches

dc Data cache

ic Instruction cache

# <vector> Identifies the 4-bit vector number for trap instructions

<> identifies an indirect data address referencing memory

<xxx> identifies an absolute address referencing memory

dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)

SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)

Operations

+ Arithmetic addition or postincrement indicator

– Arithmetic subtraction or predecrement indicator

x Arithmetic multiplication

MCF52277 Reference Manual, Rev. 0

xxx Freescale Semiconductor

Table ii. Notational Conventions (continued)

Instruction Operand Syntax

/ Arithmetic division

~ Invert; operand is logically complemented

&Logical AND

| Logical OR

^ Logical exclusive OR

<< Shift left (example: D0 << 3 is shift D0 left 3 bits)

>> Shift right (example: D0 >> 3 is shift D0 right 3 bits)

→ Source operand is moved to destination operand

←→ Two operands are exchanged

sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion

If <condition>

then

<operations>

else

<operations>

{} Optional operation

() Identifies an indirect address

d

n

Address Calculated effective address (pointer)

Bit Bit selection (example: Bit 3 of D0)

lsb Least significant bit (example: lsb of D0)

LSB Least significant byte

LSW Least significant word

msb Most significant bit

MSB Most significant byte

MSW Most significant word

Test the condition. If true, the operations after then are performed. If the condition is false and the
optional else clause is present, the operations after else are performed. If the condition is false and
else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an
example.

Subfields and Qualifiers

Displacement value, n-bits wide (example: d16 is a 16-bit displacement)

Revision History

Table iii provides a revision history for this document.

Table iii. MCF52277RM Revision History

Revision

Number

1 04/2008 First public revision of this document.

Freescale Semiconductor xxxi

Revision

Date

Description of Changes

MCF52277 Reference Manual, Rev. 0

MCF52277 Reference Manual, Rev. 0

xxxii Freescale Semiconductor

Chapter 1 Overview

The MCF5227x devices are a family of highly-integrated 32-bit microprocessors based on the Version 2
ColdFire microarchitecture. All MCF5227x devices contain a 128-Kbyte internal SRAM, an LCD
controller, a touchscreen controller, a USB On-the-Go controller, a two-bank SDR/DDR SDRAM
controller, a 16-channel DMA controller, a serial boot facility, CAN module, a SSI interface, up to three
UARTs, a DMA SPI, as well as other peripherals that enable the MCF5227x family for use in .

This document provides details of the MCF5227x microprocessor family, focusing on its highly diverse
feature set. It was written from the perspective of the MCF52277 device. However, it also pertains to the
MCF52274. See the following section for a summary of differences between the various devices of the
MCF5227x family.

1.1 MCF5227x Family Comparison

The following table compares the various device derivatives available within the MCF5227x family.

Table 1-1 . MCF5 227x Family Configurations

Module MCF52274 MCF52277

ColdFire Version 2 Core with EMAC (Enhanced
Multiply-Accumulate Unit)

Core (System) Clock up to 120 MHz up to 160 MHz

Peripheral and External Bus Clock
(Core clock ÷ 2)

Performance (Dhrystone/2.1 MIPS) up to 114 up to 152

Static RAM (SRAM) 128 Kbytes

Configurable Cache 8 Kbytes

Touchscreen Controller /
Analog-to-Digital Converter

LCD Controller 12-bit color 18-bit color

USB 2.0 On-the-Go • •

FlexBus External Interface • •

SDR/DDR SDRAM Controller • •

FlexCAN 2.0B communication module • •

Real Time Clock • •

Watchdog Timer • •

16-channel Direct Memory Access (DMA) • •

••

up to 60 MHz up to 80 MHz

••

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 1-1

Overview

Table 1-1. MCF5227x Family Configurations (continued)

Module MCF52274 MCF52277

Interrupt Controllers (INTC) 1 1

Synchronous Serial Interface (SSI) • •

2

C••

I

DSPI • •

UARTs 3 3

32-bit DMA Timers 4 4

Periodic Interrupt Timers (PIT) 2 2

PWM Module • •

Edge Port Module (EPORT) • •

General Purpose I/O Module (GPIO) • •

®

JTAG - IEEE

Package 176 LQFP 196 MAPBGA

1149.1 Test Access Port • •

MCF52277 Reference Manual, Rev. 1

1-2 Freescale Semiconductor

1.2 Block Diagram

Version 2 ColdFire Core

LEGEND

INTC

Data BusInstruction Bus

Oscillator

PLL

DSPI

EPORT

3 UARTs

I

2

C

To u ch

4 DMA

RTC

BDM – Background debug module
DSPI – DMA serial peripheral interface
eDMA – Enhanced direct memory access
EMAC – Enchance multiply-accumulate unit
EPORT – Edge port module
GPIO – General Purpose Input/Output Module
I

2

C – Inter-Intergrated Circuit
INTC – Interrupt controller
JTAG – Joint Test Action Group interface

LCD – Liquid-crystal display
PIT – Programmable interrupt timer
PLL – Phase locked loop module
PWM – Pulse-width modulator
RTC – Real time clock
SSI – Synchronous Serial Interface
UART – Universal asynchronous receiver/transmitter
USB OTG – Universal Serial Bus On-the-Go controller

MCF52277

EMAC

JTAG

Crossbar Switch (XBS)

Peripheral Bridge

8K

Configurable

Cache

Timers

BDM

LCD

SDRAM

Controller

eDMA

FlexBus

2 PITs

SSI FlexCAN GPIO

Hardware

Divide

Screen

Controller

PWM

Serial Boot

Facility

128 K

SRAM

USB OTG

Figure 1-1 shows a top-level block diagram of the MCF52277 superset device.

Overview

Figure 1-1. MCF52277 Block Diagram

Freescale Semiconductor 1-3

MCF52277 Reference Manual, Rev. 1

Overview

1.3 Features

The following is a brief summary of the functional blocks in the MCF52277 superset device followed by
a module-by-module feature list.

®

• Version 2 ColdFire

• Up to 159 Dhrystone 2.1 MIPS @ 166.67 MHz

• 8 Kbytes configurable cache (instruction only, data only, or split instruction/data)

• 128 Kbytes internal SRAM

• Support for booting from SPI-compatible flash, EEPROM, and FRAM devices

• Cross-bar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus
masters

• 16 channel DMA controller

• 16- or 32-bit SDR/DDR controller

• USB 2.0 On-the-Go controller

• Liquid crystal display controller with support up to 4096 × 4096 pixels

• ADC and touchscreen controller

• FlexCAN module

• 4 32-bit timers with DMA support

• DMA supported serial peripheral interface (DSPI)

Core with EMAC

• 3 UARTs

2

•I

C bus interface

• Synchronous serial interface

• Plus-width modulator

• Real-time clock

• Two programmable interrupt controllers

1.3.1 Version 2 ColdFire Variable-Length RISC Processor

• Static operation

• 32-bit address and data path on-chip

• Maximum 166.67 MHz processor core and 83.33 MHz bus frequency

• Sixteen general-purpose 32-bit data and address registers

• Enhanced multiply-accumulate unit (EMAC) for DSP and fast multiply operations

• Hardware divide execution unit supporting various 32-bit operations

• Implements the ColdFire Instruction Set Architecture, ISA_A+

1.3.2 On-chip Memories

• 128 Kbyte dual-ported SRAM on CPU internal bus

MCF52277 Reference Manual, Rev. 1

1-4 Freescale Semiconductor

— Accessible to non-core bus masters (e.g. DMA, USB OTG, and LCD controller) via the

crossbar switch

• 8 Kbyte unified cache configurable as instruction-only, data-only, or split I-/D-cache

1.3.3 Phase Locked Loop (PLL)

• 16–66.66 MHz reference crystal

• Loss-of-lock detection

1.3.4 Power Management

• Fully static operation with processor sleep and whole chip stop modes

• Very rapid response to interrupts from the low-power sleep mode (wake-up feature)

• Peripheral power management register to enable/disable clocks to most modules

• Software controlled disable of external clock input for low power consumption

1.3.5 Chip Configuration Module (CCM)

• System configuration during reset

Overview

• Bus monitor

• Configurable output pad drive strength control

• Unique part identification and part revision numbers

• Serial boot capability

— Supports SPI-compatible EEPROM, flash, and FRAM

— Configurable boot clock frequency

1.3.6 Reset Controller

• Separate reset in and reset out signals

• Six sources of reset: power-on reset (POR), external, software, watchdog timer, loss of lock, JTAG
instruction

• Status flag indication of source of last reset

1.3.7 System Control Module

• Access control registers

n

• Core watchdog timer with a 2

• Core fault reporting

(where n = 8–31) clock cycle selectable timeout period

1.3.8 Crossbar Switch Module

• Concurrent access from different masters to different slaves

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 1-5

Overview

• Slave arbitration attributes configured on a slave by slave basis

• Fixed or round-robin arbitration

1.3.9 Liquid Crystal Display Controller (LCDC)

• Support for single (non-split) screen monochrome/color LCD panels and self-refresh type LCD
panels

• 16 simultaneous gray-scale levels from a palette of 16 for monochrome display

• Maximum supported panel size of 4096 × 4096 pixels

• 4(mapped to RGB444)/8(RGB444)/12 bits per pixel (bpp) for passive color panel

• 4(mapped to RGB666)/8(mapped to RGB666)/12(RGB444)/16(RGB565)/18 bpp for TFT

1.3.10 ADC and Touch Screen Controller

• 12-bit 125 kS/s ADC for touch screen and general purpose measurements

• Unsigned 12-bit binary output with ±2 LSB INL, ±1 LSB DNL, ±2 LSB offset error, and ±4 LSB
gain error

• Ratiometric measurements drivers

• Touch/pressure measurements

• Supports 4/5/7 and 8-wire touch screen configurations

• Up to 8 auxiliary input channels are available for general purpose ADC measurements (the number
of the auxiliary input channels are defined by the touch-screen topology)

• Can work as an 8-channel general purpose ADC, when no touch-screen is connected

• Embedded touch screen circuitry

• Supports automatic sampling, single-round sampling, and manual sampling modes

• Provides data-ready and FIFO-full interrupts

• Pen-down detection circuitry to generate pen interrupt request

• True differential input

• Built-in selectable reference generator

• Support for temperature compensation by software

• Power-down capability

• 1.5/3.3 V dual power supply

• Internal or external reference

• Conversion executed synchronously to bus clock

• Triggerable through software and/or external hardware

1.3.11 Universal Serial Bus (USB) 2.0 On-The-Go (OTG) Controller

• Support for full speed (FS) and low speed (LS) via an on-chip FS/LS transceiver

• Uses 60 MHz reference clock based off of the system clock or from an external pin

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1-6 Freescale Semiconductor

1.3.12 SDR/DDR SDRAM Controller

• Supports a glueless interface to SDR and DDR SDRAM devices

• Support for 16- or 32-bit fixed memory port width for SDR SDRAM devices; 16-bit fixed memory
port width for DDR SDRAM devices.

• 16-byte critical word first burst transfer

• Up to 13 lines of row address, up to 12 (32-bit bus) or 13 (16-bit bus) column address lines, 2 bits
of bank address, and two pinned-out chip selects. The maximum row bits plus column bits equals
24 in 32-bit bus mode or 25 in 16-bit bus mode.

• Supports up to 512 MByte of memory; minimum memory configuration of 8 MByte

• Supports page mode to maximize the data rate

• Supports sleep mode and self-refresh mode

1.3.13 FlexBus (External Interface)

• Glueless connections to 8-, 16-, and 32-bit external memory devices (SRAM, flash, ROM, etc.)

• Support for independent primary and secondary wait states per chip select

• Programmable address setup and hold time with respect to chip-select assertion, per transfer
direction

• Glueless interface to SRAM devices with or without byte strobe inputs

Overview

• Programmable wait state generator

• 32-bit external bidirectional data bus and 24-bit address bus

• Up to six chip selects available

• Byte/write enables (byte strobes)

• Ability to boot from external memories that are 8, 16, or 32 bits wide

1.3.14 Synchronous Serial Interface (SSI)

• Supports shared (synchronous) transmit and receive sections

• Normal mode operation using frame sync

• Network mode operation allowing multiple devices to share the port with as many as 32 time slots

• Gated clock mode operation requiring no frame sync

• Programmable data interface modes such as I2S, LSB aligned, and MSB aligned

• Programmable word length up to 24 bits

• AC97 support

1.3.15 FlexCAN Module

• Full implementation of the CAN protocol specification version 2.0B

— Standard data and remote frames (up to 109 bits long)

— Extended data and remote frames (up to 127 bits long)

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 1-7

Overview

— 0–8 bytes data length

— Programmable bit rate up to 1 Mbit/sec

• Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 bytes data length each,
configurable as Rx or Tx, all supporting standard and extended messages

• Unused MB space can be used as general purpose RAM space

• Listen-only mode capability

• Content-related addressing

• Three programmable mask registers: global (for MBs 0-13), special for MB14 and special for
MB15

• Programmable transmit-first scheme: lowest ID or lowest buffer number

• Time stamp based on 16-bit free-running timer

• Global network time, synchronized by a specific message

1.3.16 Real Time Clock

• Full clock: days, hours, minutes, seconds

• Minute countdown timer with interrupt

• Programmable daily alarm with interrupt

• Sampling timer with interrupt

• Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts

• Operation determined by reference input oscillator clock frequency and value programmed into
user-accessible registers

— Minimum supported oscillator frequency of 2 Hz

• Ability to wake the processor from low-power modes (wait, doze, and stop) via the RTC interrupts

— The RTC is enabled during stop mode

1.3.17 Programmable Interrupt Timers (PIT)

• Two programmable interrupt timers each with a 16-bit counter

• Configurable as a down counter or free-running counter

1.3.18 DMA Timers

• Four 32-bit timers with DMA and interrupt request trigger capability

• Input capture and reference compare modes

1.3.19 DMA Serial Peripheral Interface (DSPI)

• Full-duplex, three-wire synchronous transfer

• Up to three chip selects available

• Master and slave modes with programmable master bit-rates

MCF52277 Reference Manual, Rev. 1

1-8 Freescale Semiconductor

• Up to 16 pre-programmed transfers

1.3.20 Pulse Width Modulation (PWM) Module

• Four independent PWM channels with programmable period and duty cycle

• Dedicated counter for each PWM channel

• Programmable PWM enable/disable for each channel

• Software selection of PWM duty pulse polarity for each channel

1.3.21 Universal Asynchronous Receiver Transmitters (UARTs)

• 16-bit divider for clock generation

• Interrupt control logic

• DMA support with separate transmit and receive requests

• Programmable clock-rate generator

• Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity

• Up to 2 stop bits in 1/16 increments

• Error-detection capabilities

Overview

1.3.22 I2C Module

• Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads

• Fully compatible with industry-standard I2C bus

• Master or slave modes support multiple masters

• Automatic interrupt generation with programmable level

1.3.23 Interrupt Controllers

• Two interrupt controllers, supporting up to 64 interrupt sources each, organized as seven
programmable levels

• Unique vector number for each interrupt source

• Ability to mask any individual interrupt source plus a global mask-all capability

• Support for service routine software interrupt acknowledge (IACK) cycles

• Combinational path to provide wake-up from low power modes

1.3.24 Edge Port Module

• Each pin can be individually configured as low level sensistive interrupt pin or edge-detecting
interrupt pin (rising, falling, or both)

• Exit stop mode via level-detect function

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 1-9

Overview

1.3.25 DMA Controller

• 16 fully programmable channels with 32-byte transfer control

• Data movement via dual-address transfers for 8-, 16-, 32- and 128-bit data values

• Programmable source, destination addresses, transfer size, support for enhanced address modes

• Support for major and minor nested counters with one request and one interrupt per channel

• Support for channel-to-channel linking and scatter/gather for continuous transfers with fixed
priority and round-robin channel arbitration

• External request pins for one channel

1.3.26 General Purpose I/O interface

• Up to 47 bits of GPIO for the MCF52274 (176 LQFP)

• Up to 55 bits of GPIO for the MCF52277 (196 MAPBGA)

• Bit manipulation supported via set/clear functions

• Various unused peripheral pins may be used as GPIO

1.3.27 System Debug Support

• Background debug mode (BDM) Revision B+

• Real time debug support, with four PC breakpoint registers and a pair of address breakpoint
registers with optional data

1.3.28 JTAG Support

• JTAG part identification and part revision numbers

1.4 Memory Map Overview

Table 1-2 illustrates the overall memory map of the device.

Table 1-2. System Memory Map

Internal

Address[31:28]

00xx 0x0000_0000–0x3FFF_FFFF FlexBus 1024 MB

01xx 0x4000_0000–0x7FFF_FFFF SDRAM Controller 1024 MB

1000 0x8000_0000–0x8FFF_FFFF Internal SRAM 256 MB

1001, 101x 0x9000_0000–0xBFFF_FFFF Reserved 256 MB

110x 0xC000_0000–0xDFFF_FFFF FlexBus 512 MB

1110 0xE000_0000–0xEFFF_FFFF Reserved 256 MB

Address Range Destination Slave Slave Memory Size

1

1111 0xF000_0000–0xFFFF_FFFF Internal Peripheral Space 256 MB

1

The actual size of the SRAM is 128 KByte. However, it may be placed anywhere within the 256 MB space
using the RAMBAR register.

MCF52277 Reference Manual, Rev. 1

1-10 Freescale Semiconductor

Overview

NOTE

This memory map provides two disjointed regions mapped to the FlexBus
controller. The first region gives support for glueless connections to
external memories (flash and SRAM). The second space (starting at
0xC000_0000) gives support for one (or more) unique chip-selects that can
be used for non-cacheable, non-memory devices. Additionally, this
mapping is selected because it easily maps into the ColdFire access control
registers, which provide a coarse association between memory addresses
and their attributes (cacheable, non-cacheable). For this device, one possible
configuration defines the default memory attribute as non-chacheable, and
one ACR is then used to identify cacheable addresses, e.g., ADDR[31] set
to zero identifies the cacheable space.

1.4.1 Internal Peripheral Space

The internal peripheral space contains locations for all internal registers used to program and control the
device’s functional blocks and external interfaces. Table 1-3 summarizes the various register spaces and
their base addresses. Each slot is 16 kB in size, which is not necessarily taken up entirely by the functional
blocks. Any slot not illustrated is reserved. See corresponding chapter for details on their individual
memory maps.

Table 1-3. Internal Peripheral Space Memory Map

Base Address Slot Number Peripheral

0xFC00_0000 0 SCM (MPR & PACRs)

0xFC00_4000 1 Crossbar switch

0xFC00_8000 2 FlexBus

0xFC02_0000 8 FlexCAN

0xFC03_C000 15 Real-Time Clock

0xFC04_0000 16 SCM (CWT & Core Fault Registers)

0xFC04_4000 17 eDMA Controller

0xFC04_8000 18 Interrupt Controller 0

0xFC04_C000 19 Interrupt Controller 1

0xFC05_4000 21 Interrupt Controller IACK

2

0xFC05_8000 22 I

0xFC05_C000 23 DSPI

0xFC06_0000 24 UART0

0xFC06_4000 25 UART1

C

0xFC06_8000 26 UART2

0xFC07_0000 28 DMA Timer 0

0xFC07_4000 29 DMA Timer 1

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 1-11

Overview

Table 1-3. Internal Peripheral Space Memory Map (continued)

Base Address Slot Number Peripheral

0xFC07_8000 30 DMA Timer 2

0xFC07_C000 31 DMA Timer 3

0xFC08_0000 32 PIT 0

0xFC08_4000 33 PIT 1

0xFC09_0000 36 PWM

0xFC09_4000 37 Edge Port

0xFC0A_0000 40 CCM, Reset Controller, Power Management

0xFC0A_4000 41 GPIO Module

0xFC0A_8000 42 ADC and Touchscreen Controller

0xFC0A_C000 43 LCD Controller

0xFC0B_0000 44 USB On-the-Go

0xFC0B_8000 46 SDRAM Controller

0xFC0B_C000 47 SSI

0xFC0C_0000 48 PLL

1.5 Documentation

Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale
Literature Distribution Center, or through the Freescale world-wide web address at

http://www.freescale.com/coldfire.

MCF52277 Reference Manual, Rev. 1

1-12 Freescale Semiconductor

Chapter 2 Signal Descriptions

2.1 Introduction

This chapter describes the external signals on the device. It includes an alphabetical signal listing of signals
that characterizes each signal as an input or output, defines its state at reset, and identifies whether a
pull-up resistor should be used.

NOTE

The terms assertion and negation are used to avoid confusion when dealing
with a mixture of active-low and active-high signals. The term asserted
indicates that a signal is active, independent of the voltage level. The term
negated indicates that a signal is inactive.

Active-low signals, such as SD_SRAS and TA, are indicated with an
overbar.

2.2 Signal Properties Summary

The below table lists the signals grouped by functionality.

NOTE

In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., FB_A23), while designations for
multiple signals within a group use brackets (i.e., FB_A[23:21]) and is
meant to include all signals within the two bracketed numbers when these
numbers are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.
Most pins that are muxed with GPIO will default to their GPIO
functionality. See Ta ble 2- 1 for a list of the exceptions.

Table 2-1. Special-Case Default Signal Functionality

Pin Default Signal

FB_BE/BWE

FB_CS

FB_OE FB_OE

FB_TA FB_TA

[3:0] FB_BE/BWE[3:0]

[3:0] FB_CS[3:0]

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 2-1

Signal Descriptions

Table 2-1. Special-Case Default Signal Functionality (continued)

Pin Default Signal

FB_R/W

FB_R/W

FB_TS FB_TS

Table 2-2 . MCF5 227x Signal Information and Muxing

1

Signal Name GPIO Alternate 1 Alternate 2

Reset

RESET

—— —U

RSTOUT —— ——

Clock

EXTAL — — — —

XTAL — — — U

Mode Selection

BOOTMOD[1:0] — — — —

2

Pull-up (U)

Direction

Pull-down (D)

I EVDD 103 J11

O EVDD 102 K11

I EVDD 106 F14

3

O EVDD 105 G14

I EVDD 110, 109 G10, H10

Vol tag e

Domain

MCF52274

176 LQFP

MCF52277

196 MAPBGA

FlexBus

FB_A[23:22] — FB_CS[5:4] — —

FB_A[21:16] — — — —

FB_A[15:14] — SD_BA[1:0] — —

FB_A[13:11] — SD_A[13:11] — —

FB_A10 — — —

FB_A[9:0] — SD_A[9:0] —

FB_D[31:16] — SD_D[31:16] —

FB_D[15:0] — FB_D[31:16] —

FB_CLK — — —

FB_BE/BWE[3:0] PBE[3:0] SD_DQM[3:0] — —

FB_CS[3:2] PCS[3:2] — — —

FB_CS1 PCS1 SD_CS1 ——

O SDVDD 143, 142 C11, D11

O SDVDD 141–139,

O SDVDD 131, 130 B14, C13

O SDVDD 129–127 C14, D12, D13

O SDVDD 126 D14

O SDVDD 125–116 E11–E14,

I/O SDVDD 30–37, 49–56 J4, K1–K4, L1–L3,

I/O SDVDD 19–26, 60–67 G1–G4, H1–H4,

OSDVDD 42 P1

O SDVDD 29, 57, 27, 59 J3, N5, J1, L6

OSDVDD

O SDVDD 144 D10

137–135

—

A12, B12, C12,

B13, A13, A14

F11–F13, G11,

G12, H11

M3, N3, P3,M4,
N4, P4, L5, M5

M6, N6, P6, L7,
M7, N7, P7, L8

B11, A11

MCF52277 Reference Manual, Rev. 1

2-2 Freescale Semiconductor

Table 2-2. MCF5227x Signal Information and Muxing (continued)

Signal Descriptions

1

2

Signal Name GPIO Alternate 1 Alternate 2

Pull-up (U)

FB_CS0

PCS0 — — —

FB_OE PFBCTL3 — — —

FB_TA PFBCTL2 — — U

FB_R/W PFBCTL1 — — —

FB_TS PFBCTL0 DACK0 ——

Direction

Pull-down (D)

O SDVDD 145 C10

OSDVDD 69 N8

I SDVDD 115 H12

OSDVDD 68 M8

OSDVDD 15 F4

SDRAM Controller

SD_A10 — — — —

SD_CAS —— ——

SD_CKE — — — —

SD_CLK — — — —

SD_CLK —— ——

SD_CS0 —— ——

SD_DQS[3:2] — — — —

SD_RAS —— ——

SD_SDR_DQS — — — —

SD_WE —— ——

External Interrupts Port

4

OSDVDD 46 L4

OSDVDD 47 N2

OSDVDD 17 F2

OSDVDD 40 M1

OSDVDD 41 N1

OSDVDD 18 F1

I/O SDVDD 28, 58 J2, P5

OSDVDD 48 P2

OSDVDD 38 M2

OSDVDD 16 F3

Volt ag e

Domain

MCF52274

176 LQFP

MCF52277

196 MAPBGA

IRQ7 PIRQ7 — — —

IRQ4 PIRQ4 DREQ0 DSPI_PCS4

IRQ1 PIRQ1 USB_CLKIN SSI_CLKIN —

6

LCD_D[17:16]

LCD_D[15:14]

LCD Controller

6

PLCDDH[1:0] LCD_D[11:10] — — O

6

PLCDDM[7:6] LCD_D[9:8] — — O

LCD_D13 PLCDDM5 CANTX — — O

LCD_D12 PLCDDM4 CANRX — — O

LCD_D[11:8]

6

PLCDDM[3:0] LCD_D[7:4] — — O

LCD_D7 PLCDDL7 PWM7 — — O

LCD_D6 PLCDDL6 PWM5 — — O

LCD_D[5:2]

6

PLCDDL[5:2] LCD_D[3:0] — — O

I EVDD 162 D7

5

I EVDD 161 C7

I EVDD 160 B7

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

9, 8 E3, E4

7, 6 D1, D2

—C1

—C2

5–2 D3, C3, D4, B1

—B2

—A1

175–172 A2, A3, B3, A4

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 2-3

Signal Descriptions

Table 2-2. MCF5227x Signal Information and Muxing (continued)

1

Signal Name GPIO Alternate 1 Alternate 2

Pull-up (U)

Pull-down (D)

LCD_D1 PLCDDL1 PWM3 — — O

LCD_D0 PLCDDL0 PWM1 — — O

LCD_ACD/

PLCDCTL3 LCD_SPL_SPR — — O

LCD_OE

LCD_FLM/

PLCDCTL2 — — — O

LCD_VSYNC

LCD_LP/

PLCDCTL1 — — — O

LCD_HSYNC

LCD_LSCLK PLCDCTL0 — — — O

USB On-the-Go

USB_DM — — — —

USB_DP — — — —

Real Time Clock

2

Volt ag e

Direction

OUSB

OUSB

Domain

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

VDD

VDD

MCF52274

176 LQFP

—B4

—C4

169 B5

10 E2

11 E1

170 A5

149 A9

150 A10

MCF52277

196 MAPBGA

RTC_EXTAL — — — —

RTC_XTAL — — — —

I EVDD 100 J14

O EVDD 99 K14

ADC

ADC_IN[7:0] — — — —

ADC_REF — — — —

I VDD_

I VDD_

I2C

I2C_SCL PI2C1 CANTX U2TXD U

I2C_SDA PI2C0 CANRX U2RXD U

7

DSPI

DSPI_PCS0/SS PDSPI3 U2RTS —U

DSPI_SIN PDSPI2 U2RXD SBF_DI

DSPI_SOUT PDSPI1 U2TXD SBF_D0 —

DSPI_SCK PDSPI0 U2CTS SBF_CK —

I/O EVDD 168 C5

I/O EVDD 167 D5

I/O EVDD 152 B9

8

I EVDD 155 D8

O EVDD 154 D9

I/O EVDD 153 C9

UARTs

U1CTS

PUART7 SSI_BCLK LCD_CLS —

I EVDD 156 C8

ADC

ADC

82–85, 87–90 P12, N12, P13,

86 M12

N13, P14, N14,

M13, M14

MCF52277 Reference Manual, Rev. 1

2-4 Freescale Semiconductor

Table 2-2. MCF5227x Signal Information and Muxing (continued)

Signal Descriptions

Signal Name GPIO Alternate 1 Alternate 2

U1RTS

PUART6 SSI_FS LCD_PS —

U1RXD PUART5 SSI_RXD — —

U1TXD PUART4 SSI_TXD — —

U0CTS PUART3 DT1OUT USB_VBUS_EN —

U0RTS PUART2 DT1IN USB_VBUS_OC —

U0RXD PUART1 CANRX — —

U0TXD PUART0 CANTX — —

DMA Timers

DT3IN PTIMER3 DT3OUT SSI_MCLK —

DT2IN/SBF_CS

7

PTIMER2 DT2OUT DSPI_PCS2 —

DT1IN PTIMER1 DT1OUT LCD_CONTRAST —

DT0IN PTIMER0 DT0OUT LCD_REV —

BDM/JTAG

9

1

2

Pull-up (U)

Pull-down (D)

O EVDD 157 B8

I EVDD 158 A8

O EVDD 159 A7

I EVDD 97 K12

O EVDD 98 J12

I EVDD 96 K13

O EVDD 95 L12

I EVDD 163 D6

I EVDD 164 C6

I EVDD 165 B6

I EVDD 166 A6

Direction

Volt ag e

Domain

MCF52274

176 LQFP

MCF52277

196 MAPBGA

PST[3:0] — — — —

DDATA[3:0] — — — —

ALLPST — — — —

JTAG_EN — — — D

PSTCLK — TCLK — U

DSI — TDI — U

DSO — TDO — —

BKPT —TMS —U

DSCLK — TRST —U

O EVDD — L9, M9, N9, P9

O EVDD — L10, M10, N10,

O EVDD 76 —

I EVDD 79 K10

O EVDD 74 P8

I EVDD 78 M11

O EVDD 81 L11

I EVDD 80 N11

I EVDD 77 P11

Test

TEST — — — D

I EVDD 134 E10

Power Supplies

IVDD — — — — — —

EVDD — — — — — —

SD_VDD — — — — — —

39, 75, 114, 138,

171

12, 72, 73, 94,

111, 148, 176

14, 43, 44, 70,

113, 132, 146

P10

K5, F10, E5, J10

E6, E7, F5, F6,

G5, H9, J9, K8, K9

E8, E9, F9, G9,

H5, J5, J6, K6, K7

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 2-5

Signal Descriptions

Table 2-2. MCF5227x Signal Information and Muxing (continued)

1

Signal Name GPIO Alternate 1 Alternate 2

VDD_OSC — — — — — —

VDD_PLL — — — — — —

VDD_USB — — — — — —

VDD_RTC — — — — — —

VDD_ADC — — — — — —

VSS — — — — — —

VSS_OSC — — — — — —

VSS_ADC — — — — — —

1

Pull-ups are generally only enabled on pins with their primary function, except as noted.

2

Refers to pin’s primary function.

3

Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).

4

GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.

5

Pull-up when DREQ controls the pin.

6

The 176 LQFP device only supports a 12-bit LCD data bus.

7

DSPI or SBF signal functionality is controlled by RESET. When asserted, these pins are configured for serial boot; when negated, the

2

Pull-down (D)

Direction

Pull-up (U)

Volt ag e

Domain

1, 13, 45, 71, 93,

MCF52274

176 LQFP

108 G13

104 H14

151 B10

101 J13

91 L13

112, 133, 147

107 H13

92 L14

MCF52277

196 MAPBGA

F7, F8, G6–G8,

H6–H8, J7, J8

pins are configured for DSPI.

8

Pull-up when the serial boot facility (SBF) controls the pin.

9

If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these
pins.

2.3 Signal Primary Functions

2.3.1 Reset Signals

Table 2-3 describes signals used to reset the chip or to indicate a reset.

Table 2-3. Reset Signals

Signal Name Abbreviation Function I/O

Reset In RESET

Primary reset input to the device. Asserting RESET resets the core and
peripherals after four FB_CLK cycles. Asserting RESET
RSTOUT

to be asserted.

also causes

Reset Out RSTOUT Reset output is an indicator that the chip is in reset. RSTOUT is

asserted at least 512 internal system bus clock cycles in response to
any internal or external reset. (The exact time depends on how long it
takes for the PLL to lock and/or the serial boot sequence to complete.)

MCF52277 Reference Manual, Rev. 1

2-6 Freescale Semiconductor

I

O

2.3.2 PLL and Clock Signals

Table 2-4 describes signals that are used to support the on-chip clock generation circuitry.

Table 2-4. PLL and Clock Signals

Signal Name Abbreviation Function I/O

Signal Descriptions

External Clock In EXTAL Always driven by an external clock input except when used as a

connection to the external crystal if the internal oscillator circuit is
used. Clock source may be configured during reset. See Chapter 9,

“Chip Configuration Module (CCM),” for more details.

Crystal XTAL Used as a connection to the external crystal when the internal

oscillator circuit is used to drive the crystal.

RTC External Clock In RTC_EXTAL Crystal input clock for the real-time clock module. I

RTC Crystal RTC_XTAL Oscillator output to RTC crystal. O

FlexBus Clock Out FB_CLK Reflects the internal bus clock (or one-half the core/system clock).

)

(f

sys/2

USB Clock In USB_CLKIN This pin allows the user to drive the reference clock to the USB module

as an alternate method of generating the USB reference clock during
FS/LS operation. This pin should be driven only with a 60 MHz clock.

SSI Clock In SSI_CLKIN This pin allows the user to drive a specific clock frequency to the SSI

module.

2.3.3 Mode Selection

Table 2-5. Mode Selection Signals

Signal Name Abbreviation Function I/O

I

O

O

I

I

Boot Mode BOOTMOD[1:0] Indicates the device’s boot mode and chip configuration at reset. See

Chapter 9, “Chip Configuration Module (CCM),” for the signal

encodings.

2.3.4 FlexBus Signals

Table 2-6 describes signals that are used for performing transactions on the external bus.

Table 2-6 . FlexB u s Sig n als

Signal Name Abbreviation Function I/O

Address Bus FB_A[23:0] Defines address of external byte, word, and longword accesses.

These three-state outputs are the 24 lsbs of the internal 32-bit
address bus.

Data Bus FB_D[31:0] These three-state bidirectional signals provide the general purpose

data path between the processor and all other devices.

MCF52277 Reference Manual, Rev. 1

I

O

I/O

Freescale Semiconductor 2-7

Signal Descriptions

Signal Name Abbreviation Function I/O

Table 2-6. FlexBus Signals (continued)

Byte Enables FB_BE/BWE[3:0] Defines flow of data on data bus. During peripheral accesses, these

output signals indicate that data is to be latched or driven onto a byte
of the data bus when driven low. The BE/BWE
asserted only to the memory bytes used during a read or write access.
BE/BWE
and BE/BWE3 controls access to the least significant byte lane of
data.

For SRAM or Flash devices, the BE/BWE
connected to individual byte strobe signals.

Chip Selects FB_CS

Output Enable FB_OE Indicates when an external device can drive data during external read

Transfer Acknowledge FB_TA Indicates external data transfer is complete. During a read cycle, when

Read/Write FB_R/W Indicates direction of the data transfer on the bus for SRAM accesses.

Transfer Start FB_TS

[5:0] Select external devices for external bus transactions. O

cycles.

the processor recognizes FB_TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes FB_TA

A logic 1 indicates a read from a slave device and a logic 0 indicates
a write to a slave device.

Bus control output signal indicating the start of a transfer. O

0 controls access to the most significant byte lane of data,

, the bus cycle is terminated.

[3:0] signals are

n outputs should be

2.3.5 SDRAM Controller Signals

O

O

I

O

Table 2-7 describes signals used for SDRAM accesses.

Table 2-7. SDRAM Controller Signals

Signal Name Abbreviation Function I/O

Address Bus SD_A[13:0] Address bus used for multiplexed row and column addresses during

SDRAM bus cycles.

Data Bus SD_D[31:16] Bidirectional, non-multiplexed data bus for SDRAM accesses. I/O

Bank Address SD_BA[1:0] Selects one of the four SDRAM row banks. O

Clock Enable SD_CKE SDRAM clock enable. O

DDR Clock SD_CLK Output clock for DDR SDRAM. O

DDR Clock SD_CLK

Chip Selects SD_CS[1:0] SDRAM chip select signals. O

DDR Data Strobes SD_DQS[3:2] Indicates when valid data is on data bus. I/O

Write Data Byte Mask SD_DQM[3:0] Used to determine which byte lanes of data bus should be latched

Inverted output clock for DDR SDRAM. O

during a write cycle.
The SD_DQMn should be connected to individual SDRAM DQM
signals. Most SDRAMs associate DQM3 with the MSB, in which case
SD_DQM3 should be connected to the SDRAM's DQM3 input.

O

O

MCF52277 Reference Manual, Rev. 1

2-8 Freescale Semiconductor

Signal Descriptions

Table 2-7. SDRAM Controller Signals (continued)

Signal Name Abbreviation Function I/O

Column Address Strobe SD_CAS SDRAM column address strobe. O

Row Address Strobe SD_RAS

SDR Data Strobe SD_SDRDQS Generated by the memory controller in SDR mode, to mimic the DQS

Write Enable SD_WE

SDRAM row address strobe. O

signal generated by DDR memories during reads. It is routed out and
connected back to SD_DQS inputs.

Indicates direction of data transfer on bus for SDRAM accesses. A
logic 1 indicates a read from a slave device and a logic 0 indicates a
write to a slave device.

2.3.6 Serial Boot Facility Signals

Table 2-8. SBF Signals

Signal Name Abbreviation Function I/O

Chip Select SBF_CS Chip select used to access external SPI memory. O

Clock SBF_CK 25 MHz clock source for external SPI memory. O

Data In SBF_DI Data being driven by SPI memory. I

Data Out SBF_DO Data out to SPI memory. SBF uses this output solely for the purpose

of issuing the SPI memory
to SPI memory.

READ command. SBF does not write data

2.3.7 External Interrupt Signals

O

O

O

Table 2-9. External Interrupt Signals

Signal Name Abbreviation Function I/O

External Interrupts IRQ

[7,4,1] External interrupt sources. I

2.3.8 DMA Signals

Table 2-10. DMA Signals

Signal Name Abbreviation Function I/O

DMA Request DREQ0

DMA Acknowledge DACK0 Asserted by processor to indicate DMA request has been recognized. O

Asserted by an external device to request a DMA transfer. I

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Freescale Semiconductor 2-9

Signal Descriptions

2.3.9 LCD Controller Signals

Table 2-10 describes the LCD controller signals.

Table 2-11. LCD Signals

Signal Name Abbreviation Function I/O

Line Data LCD_D[17:0] LCD data bus. O

First Line Marker/
Vertical Sync

Line Pulse/
Horizontal Sync

Shift Clock LCD_LSCLK Clock for latching data into the display driver’s internal shift register. O

Alt. Crystal Direction/
Output Enable

Contrast LCD_CONTRAST Controls the LCD bias voltage for contrast control. O

Power Save LCD_PS Controls signal output for source driver (Sharp HR-TFT 240x320

Gate Driver Clock
Signal

Reverse Control LCD_REV Signal for common electrode driving signal preparation (Sharp

Sampling Start Signal LCD_SPL_SPR Sets the horizontal scan direction (Sharp HR-TFT 240x320 panels

LCD_FLM/
LCD_VSYNC

LCD_LP/
LCD_HSYNC

LCD_ACD/
LCD_OE

LCD_CLS Start signal output for gate driver, inverted version of LCD_PS (Sharp

Passive matrix: First line marker
Active matrix: Vertical sync pulse. Indicates start of next frame.

Passive matrix: Line pulse
Active matrix: Horizontal sync pulse. Indicates start of next line.

Passive matrix: Alternate crystal direction
Active matrix: Output enable to enable data to be shifted onto the
display.

panels only).

HR-TFT 240x320 panels only).

HR-TFT 240x320 panels only).

only).

2.3.10 FlexCAN Signals

Table 2-12 describes the FlexCAN module signals.

O

O

O

O

O

O

O

Table 2-12. FlexCAN Signals

Signal Name Abbreviation Function I/O

FlexCAN Transmit CANTX Controller area network transmit data output. O

FlexCAN Receive CANRX Controller area network receive data input. I

2.3.11 Pulse Width Modulation (PWM) Module Signals

The following table describes the signals for the PWM module.

Table 2-13. PWM Module Signals

Signal Name Abbreviation Function I/O

PWM7 Output PWM7 Waveform output for channel 7 of the PWM module. Also functions as

an input for the emergency shutdown feature of the PWM.

PWM[5,3,1,0] Outputs PWM[5,3,1,0] Waveform output for channels 5, 3, 1, and 0 respectively. O

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2-10 Freescale Semiconductor

I/O

Signal Descriptions

2.3.12 Universal Serial Bus (USB) On-the-Go Signals

Table 2-14. USB Module Signals

Signal Name Abbreviation Function I/O

USB D- USB_DM D- output of the dual-speed transceiver for the On-the-Go module. O

USB D+ USB_DP D+ output of the dual-speed transceiver for the On-the-Go module. O

USB VBUS Enable USB_VBUS_EN Enables the off-chip VBUS charge pump when USB OTG module is

configured as a host.

USB VBUS over-current USB_VBUS_OC Indicates to the processor that a short has occurred on USB data

bus.

2.3.13 Touschreen Controller/ADC Signals

Table 2-15. Touchscreen/ADC Signals

Signal Name Abbreviation Function I/O

ADC Reference ADC_REF External ADC reference voltage I

ADC Inputs ADC_IN[7:0] Touchscreen and/or ADC inputs. ADC_IN[7:0] serves as a

touchscreen interface or generic ADC interface.

2

2.3.14 I

Serial Clock I2C_SCL Open-drain clock signal. It is driven by the I2C module when the bus

Serial Data I2C_SDA Open-drain signal serving as the I

C I/O Signals

Table 2-16. I2C I/O Signals

Signal Name Abbreviation Function I/O

is in master mode, or it becomes the clock input when the I2C is in
slave mode.

2

C data input/output. I/O

O

I

I

I/O

2.3.15 DMA Serial Peripheral Interface (DSPI) Signals

Table 2-17. DMA Serial Peripheral Interface (DSPI) Signals

Signal Name Abbreviation Function I/O

Synchronous Serial
Output

Freescale Semiconductor 2-11

DSPI_SOUT Provides the serial data from the DSPI, which may be driven on the

rising or falling edge of DSPI_SCK. Each byte is sent msb first.

MCF52277 Reference Manual, Rev. 1

O

Signal Descriptions

Signal Name Abbreviation Function I/O

Table 2-17. DMA Serial Peripheral Interface (DSPI) Signals (continued)

Synchronous Serial Data
Input

Serial Clock DSPI_SCK Provides the serial clock from the DSPI. In master mode, the

Peripheral Chip Selects DSPI_PCS[4,2] Provide DSPI peripheral chip selects, which may be active high or low. O

Peripheral Chip Select 0/
Slave Select

DSPI_SIN Provides the serial data to the DSPI, which may be sampled on the

rising or falling edge of DSPI_SCK. Each byte is written to RAM lsb
first.

processor generates DSPI_SCK; in slave mode, DSPI_SCK is an
input from an external bus master.

DSPI_PCS0/
DSPI_SS

In master mode, DSPI_PCS0 is a peripheral chip select output that
selects which slave device the current transmission is intended.
In slave mode, the SS signal is a slave select input that an SPI master
uses to select the processor as the target for transmission.

I

I/O

I/O

2.3.16 UART Module Signals

Table 2-18 describes the signals of the three UART modules, where n equals 0–2. Baud-rate clock inputs

are not supported.

Table 2-18. UART Module Signals

Signal Name Abbreviation Function I/O

Transmit Serial Data
Output

UnTXD Data is shifted out lsb first at the falling edge of the serial clock source.

Output is held high when transmitter is disabled, idle, or in local
loopback mode.

O

Receive Serial Data
Input

Request-to-Send U

Clear-to-Send UnCTS Indicates UART modules can begin data transmission I

UnRXD Data is sampled Isb first at the serial clock source’s rising edge. When

the UART clock is stopped for power-down mode, any transition on this
pin restarts it.

nRTS Automatic request-to-send outputs from UART modules. They may

also be asserted and negated as a function of the received FIFO level.

2.3.17 Synchronous Serial Interface (SSI) Signals

Table 2-19. SSI Module Signals

Signal Name Abbreviation Function I/O

Serial Bit Clock SSI_BCLK Used by the receive and transmit blocks. In gated clock mode,

SSI_BCLK is only valid during transmission of data; otherwise it is
pulled to an inactive state.

Serial Master Clock SSI_MCLK This clock signal is output from the device when it is the master. When

2

S master mode, this signal is referred to as the oversampling

in I
clock. The frequency of SSI_MCLK is a multiple of the frame clock.

I

O

I/O

O

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2-12 Freescale Semiconductor

Signal Descriptions

Table 2-19. SSI Module Signals (continued)

Signal Name Abbreviation Function I/O

Serial Frame Sync SSI_FS Used by transmitter/receiver to synchronize the transfer of data. In

gated clock mode, this signal is not used. When configured as an
input, the external device should drive SSI_FS during the rising edge
of SSI_BCLK.

Serial Receive Data SSI_RXD Receives data into the receive data shift register I

Serial Transmit Data SSI_TXD Transmits data from the serial transmit shift register. O

I/O

2.3.18 DMA Timer Signals

Table 2-20 describes the signals of the four DMA timer modules, where n equals 0–3.

Table 2-20. DMA Timer Signals

Signal Name Abbreviation Function I/O

DMA Timer n Input DTnIN Can be programmed to cause events in the respective timer. It can

clock the event counter or provide a trigger to the timer value capture
logic.

DMA Timer n Output DTnOUT Output from respective timer. O

I

2.3.19 Debug Support Signals

These signals are used as the interface to the on-chip JTAG controller and the BDM logic. Pin functionality
between JTAG and BDM is dependent upon the JTAG_EN pin.

Table 2-21. Debug Support Signals

Signal Name Abbreviation Function I/O

JTAG Enable JTAG_EN Enables JTAG (asserted) or BDM (negated) operation. I

JTAG Signals

Test Reset TRST

Test Clock TCLK Used to synchronize the JTAG logic. I

Test Mode Select TMS Used to sequence the JTAG state machine. TMS is sampled on the

Test Data Input TDI Serial input for test instructions and data. TDI is sampled on the rising

Test Data Output TDO Serial output for test instructions and data. TDO is three-stateable and

Development Serial
Clock

DSCLK Clocks the serial communication port to the BDM module during

Active-low signal used to initialize the JTAG logic asynchronously. I

rising edge of TCLK.

edge of TCLK.

actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.

BDM Signals

packet transfers.

I

I

O

I

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Freescale Semiconductor 2-13

Signal Descriptions

Signal Name Abbreviation Function I/O

Table 2-21. Debug Support Signals (continued)

Breakpoint BKPT

Development Serial
Input

Development Serial
Output

Processor Status Clock PSTCLK Used by the development system to know when to sample DDATA and

Debug Data DDATA[3:0] Display captured processor data and breakpoint status. The PSTCLK

Processor Status
Outputs

All Processor Status
Outputs

DSI Internally-synchronized signal provides data input for the serial

DSO Internally-registered signal provides serial output communication for

PST[3:0] Indicate core status, as shown in Ta bl e 2- 2 2 . Debug mode timing is

ALLPST ALLPST is a logical AND of the four PST signals and is present in

Used to request a manual breakpoint. I

communication port to the BDM module.

BDM module responses.

PST signals.

signal can be used by the development system to know when to
sample DDATA[3:0].
Only present on the BGA device (MCF52277).

synchronous with the processor clock; status is unrelated to the
current bus transfer. The PSTCLK signal can be used by the
development system to know when to sample PST[3:0].
Only present on the BGA device (MCF52277).

place of PST[3:0] and DDATA[3:0] on the LQFP device (MCF52274).
When asserted, reflects that the core is halted.

Table 2-22. Processor Status

I

O

O

O

O

O

PST[3:0]

(MCF52274)

0000 0 Continue execution

0001 0 Begin execution of one instruction

0010 0 Reserved

0011 0 Entry into user mode

0100 0 Begin execution of PULSE and WDDATA instructions

0101 0 Begin execution of taken branch

0110 0 Reserved

0111 0 Begin execution of RTE instruction

1000 0 Begin one-byte transfer on DDATA

1001 0 Begin two-byte transfer on DDATA

1010 0 Begin three-byte transfer on DDATA

1011 0 Begin four-byte transfer on DDATA

1100 0 Exception processing

1101 0 Reserved

ALLPST

(MCF52277)

Processor Status

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2-14 Freescale Semiconductor

Table 2-22. Processor Status (continued)

Signal Descriptions

PST[3:0]

(MCF52274)

1110 0 Processor is stopped

1111 1 Processor is halted

ALLPST

(MCF52277)

Processor Status

2.3.20 Test Signals

Table 2-23 describes test signals reserved for factory testing.

Table 2-23. Test Signals

Signal Name Abbreviation Function I/O

Test TEST Reserved for factory testing only and in normal modes of operation

should be connected to VSS to prevent unintentional activation of test
functions.

I

2.3.21 Power and Ground Pins

The pins described in Table 2-24 provide system power and ground to the device. Multiple pins are
provided for adequate current capability. All power supply pins must have adequate bypass capacitance
for high-frequency noise suppression.

Table 2-24. Power and Ground Pins

Signal Name Abbreviation Function I/O

PLL Analog Supply VDD_A_PLL Dedicated power supply signal to isolate the sensitive PLL analog

(VCO) circuitry from the normal levels of noise present on the digital
power supply.

Oscillator VDD_OSC

VSS_OSC

Positive I/O Supply EVDD These pins supply positive power to the I/O pads

Positive Core Supply IVDD These pins supply positive power to the core logic. —

SDRAMC Supply SD_VDD These pins supply positive power to the SDRAM controller. —

USB Supply VDD_USB These pins supply positive power to the USB controller. —

Real-time clock Supply VDD_RTC These pins supply positive power to the RTC module. —

ADC supply VDD_ADC

VSS_ADC

Ground VSS These pins are the negative supply (ground) for the device. —

Dedicated power supply signals to isolate the sensitive oscillator
circuitry from the normal levels of noise present on the digital power
supply.

. —

Dedicated power supply for the touchscreen controller/ADC. —

—

—

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 2-15

Signal Descriptions

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2-16 Freescale Semiconductor

Chapter 3

Instruction

Instruction

FIFO

Decode & Select,

Address

IAG

IC

IB

DSOC

AGEX

Instruction Buffer

Address

Generation

Fetch Cycle

Generation,

Execute

Operand Fetch

Instruction

Operand

Pipeline

Execution

Fetch

Pipeline

Address [ :0]

31

Read Data[31:0]

Write Data[31:0]

ColdFire Core

3.1 Introduction

This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview
of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the
ColdFire Family Programmer’s Reference Manual.

3.1.1 Overview

As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an
instruction buffer.

The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the

Freescale Semiconductor 3-1

Figure 3-1. V2 ColdFire Core Pipelines

MCF52277 Reference Manual, Rev. 1

ColdFire Core

(described fully in Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC

instruction, fetches the required operands and then executes the required function. Because the IFP and
OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch
instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.

The V2 ColdFire core pipeline stages include the following:

• Two-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage)

— Instruction address generation (IAG) — Calculates the next prefetch address

— Instruction fetch cycle (IC)—Initiates prefetch on the processor’s local bus

— Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO

queue

• Two-stage operand execution pipeline (OEP)

— Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the

required components for effective address calculation, or the operand fetch cycle

— Address generation/execute cycle (AGEX)—Calculates operand address or executes the

instruction

When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the operand
execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction in the
IB until it is required by the OEP.

For register-to-register and register-to-memory store operations, the instruction passes through both OEP
stages once. For memory-to-register and read-modify-write memory operations, an instruction is
effectively staged through the OEP twice: the first time to calculate the effective address and initiate the
operand fetch on the processor’s local bus, and the second time to complete the operand reference and
perform the required function defined by the instruction.

The resulting pipeline and local bus structure allow the V2 ColdFire core to deliver sustained high
performance across a variety of demanding embedded applications.

3.2 Memory Map/Register Description

The following sections describe the processor registers in the user and supervisor programming models.
The programming model is selected based on the processor privilege level (user mode or supervisor mode)
as defined by the S bit of the status register (SR). Table 3-1 lists the processor registers.

The user-programming model consists of the following registers:

• 16 general-purpose 32-bit registers (D0–D7, A0–A7)

• 32-bit program counter (PC)

• 8-bit condition code register (CCR)

• EMAC registers :

— Four 48-bit accumulator registers partitioned as follows:

– Four 32-bit accumulators (ACC0–ACC3)

– Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two

32-bit values for load and store operations (ACCEXT01 and ACCEXT23).

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3-2 Freescale Semiconductor

ColdFire Core

• One 32-bit memory base address register (RAMBAR)

Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC
arithmetic operations generally affect the entire 48-bit destination.

— One 16-bit mask register (MASK)

— One 32-bit Status register (MACSR) including four indicator bits signaling product or

accumulation overflow (one for each accumulator: PAV0–PAV3)

The supervisor-programming model is intended to be used only by system control software to implement
restricted operating system functions, I/O control, and memory management. All accesses that affect the
control features of ColdFire processors are in the supervisor programming model, which consists of
registers available in user mode as well as the following control registers:

• 16-bit status register (SR)

• 32-bit supervisor stack pointer (SSP)

• 32-bit vector base register (VBR)

• 32-bit cache control register (CACR)

• 32-bit access control registers (ACR0, ACR1)

Table 3-1. ColdFire Core Programming Model

1

BDM

Load: 0x080

Store: 0x180

Load: 0x081

Store: 0x181

Load: 0x082–7

Store: 0x182–7

Load: 0x088–8E
Store: 0x188–8E

Load: 0x08F

Store: 0x18F

0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 No 4.2.1/4-3

0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF No 4.2.2/4-5

0x806, 0x809,
0x80A, 0x80B

0x807 MAC Accumulator 0,1 Extension Bytes

Data Register 0 (D0) 32 R/W 0xCF20_6089 No 3.2.1/3-4

Data Register 1 (D1) 32 R/W 0x1500_1090 No 3.2.1/3-4

Data Register 2–7 (D2–D7) 32 R/W Undefined No 3.2.1/3-4

Address Register 0–6 (A0–A6) 32 R/W Undefined No 3.2.2/3-4

Supervisor/User A7 Stack Pointer (A7) 32 R/W Undefined No 3.2.3/3-5

MAC Accumulators 0–3 (ACC0–3) 32 R/W Undefined No 4.2.3/4-6

(ACCext01)

Register

Supervisor/User Access Registers

Width

(bits)

Access Reset Value

32 R/W Undefined No 4.2.4/4-7

Written with

MOVEC

Section/Page

0x808 MAC Accumulator 2,3 Extension Bytes

(ACCext23)

0x80E Condition Code Register (CCR) 8 R/W Undefined No 3.2.4/3-6

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 3-3

32 R/W Undefined No 4.2.4/4-7

ColdFire Core

Table 3-1. ColdFire Core Programming Model (continued)

1

BDM

0x80F Program Counter (PC) 32 R/W Contents of

0x002 Cache Control Register (CACR) 32 R/W 0x0000_0000 Yes 3.2.6/3-7

0x004–5 Access Control Register 0–1 (ACR0–1) 32 R/W See Section Yes 3.2.7/3-7

0x800 User/Supervisor A7 Stack Pointer

(OTHER_A7)

0x801 Vector Base Register (VBR) 32 R/W 0x0000_0000 Yes 3.2.8/3-7

0x80E Status Register (SR) 16 R/W 0x27-- No 3.2.9/3-8

0xC05 RAM Base Address Register (RAMBAR) 32 R/W See Section Yes 3.2.10/3-8

1

The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see Chapter 32, “Debug Module”.

Register

Supervisor Access Only Registers

Width

(bits)

Access Reset Value

location

0x0000_0004

32 R/W Contents of

location

0x0000_0000

Written with

MOVEC

No 3.2.5/3-7

No 3.2.3/3-5

Section/Page

3.2.1 Data Registers (D0–D7)

D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they
can also be used as index registers.

NOTE

Registers D0 and D1 contain hardware configuration details after reset. See

Section 3.3.4.15, “Reset Exception” for more details.

BDM: Load: 0x080 + n; n = 0-7 (Dn)

Store: 0x180 + n; n = 0-7 (Dn)

313029282726252423222120191817161514131211109876543210

R

W

Reset

(D2-D7)

(D0, D1)

––––––––––––––––––––––––––––––––

Reset

Data

See Section 3.3.4.15, “Reset Exception”

Figure 3-2. Data Registers (D0–D7)

Access: User read/write

BDM read/write

3.2.2 Address Registers (A0–A6)

These registers can be used as software stack pointers, index registers, or base address registers. They can
also be used for word and longword operations.

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3-4 Freescale Semiconductor

ColdFire Core

BDM: Load: 0x088 + n; n =0–6 (An)

Store: 0x188 + n; n =0–6 (An)

313029282726252423222120191817161514131211109876543210

R

Address

W

Reset––––––––––––––––––––––––––––––––

Figure 3-3. Address Registers (A0–A6)

Access: User read/write

BDM read/write

3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)

This ColdFire architecture supports two independent stack pointer (A7) registers—the supervisor stack
pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two
program-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead, the
hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents
are a function of the processor operation mode, as shown in the following:

if SR[S] = 1

then A7 = Supervisor Stack Pointer

OTHER_A7 = User Stack Pointer

else A7 = User Stack Pointer

OTHER_A7 = Supervisor Stack Pointer

The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the
responsibility of the external development system to determine, based on the setting of SR[S], the mapping
of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP). This functionality is
enabled by setting the enable user stack pointer bit, CACR[EUSP]. If this bit is cleared, only a single stack
pointer (A7), defined for ColdFire ISA_A, is available. EUSP is cleared at reset.

To support dual stack pointers, the following two supervisor instructions are included in the ColdFire
instruction set architecture to load/store the USP:

move.l Ay,USP;move to USP
move.l USP,Ax;move from USP

These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other
instruction references to the stack pointer, explicit or implicit, access the active A7 register.

NOTE

The SSP is loaded during reset exception processing with the contents of
location 0x0000_0000.

MCF52277 Reference Manual, Rev. 1

Freescale Semiconductor 3-5

ColdFire Core

BDM: Load: 0x08F (A7)

Store: 0x18F (A7)
0x800 (OTHER_A7)

313029282726252423222120191817161514131211109876543210

R

Address

W

Reset––––––––––––––––––––––––––––––––

Access: A7: User or BDM read/write

OTHER_A7: Supervisor or BDM read/write

Figure 3-4. Stack Pointer Registers (A7 and OTHER_A7)

3.2.4 Condition Code Register (CCR)

The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. The extend bit (X) is also an input operand during multiprecision
arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare
(CMP), Bcc, or Scc instructions are executed.

BDM: LSB of Status Register (SR) Access: User read/write

BDM read/write

76543210

R 0 0 0

W

X N Z V C

Reset:0 0 0 —————

Figure 3-5. Condition Code Register (CCR)

Table 3-2. CCR Field Descriptions

Field Description

7–5 Reserved, must be cleared.

4

Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified

X

result.

3

Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.

N

2

Zero condition code bit. Set if result equals zero; otherwise cleared.

Z

1

Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand

V

size; otherwise cleared.

0

Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a

C

subtraction; otherwise cleared.

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3-6 Freescale Semiconductor

ColdFire Core

3.2.5 Program Counter (PC)

The PC contains the currently executing instruction address. During instruction execution and exception
processing, the processor automatically increments contents of the PC or places a new value in the PC, as
appropriate. The PC is a base address for PC-relative operand addressing.

The PC is initially loaded during reset exception processing with the contents of location 0x0000_0004.

BDM: 0x80F (PC) Access: User read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

R

W

Reset––––––––––––––––––––––––––––––––

Figure 3-6. Program Counter Register (PC)

Address

3.2.6 Cache Control Register (CACR)

The CACR controls operation of the instruction/data cache memories. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and
write-protect fields. The CACR is described in Section 5.2.1, “Cache Control Register (CACR).”

3.2.7 Access Control Registers (ACRn)

The access control registers define attributes for user-defined memory regions. These attributes include the
definition of cache mode, write protect, and buffer write enables. The ACRs are described in Section 5.2.2,

“Access Control Registers (ACR0, ACR1).”

3.2.8 Vector Base Register (VBR)

The VBR contains the base address of the exception vector table in memory. To access the vector table,
the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are
not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on
a 1 MByte boundary.

BDM: 0x801 (VBR) Access: Supervisor read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

R

Base Address

W

Reset00000000000000000000000000000000

Figure 3-7. Vector Base Register (VBR)

0 0 0 0 0 000000000 000 0 00

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3.2.10 Memory Base Address Register (RAMBAR)

The memory base address register is used to specify the base address of the internal SRAM module and
indicates the types of references mapped to it. The base address register includes a base address,
write-protect bit, address space mask bits, and an enable bit. RAMBAR determines the base address of
the on-chip RAM. For more information, refer to Section 6.2.1, “SRAM Base Address Register

(RAMBAR)”.

3.2.9 Status Register (SR)

The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are
accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor
or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access
when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and
before any compare (CMP), Bcc, or Scc instructions execute.

BDM: 0x80E (SR) Access: Supervisor read/write

BDM read/write

System Byte Condition Code Register (CCR)

1514131211109876543210

R

W

Reset00100111000—————

0

T

S M

0

I

Figure 3-8. Status Register (SR)

Table 3-3. SR Field Descriptions

Field Description

000

X N ZVC

15

14 Reserved, must be cleared.

13

12

11 Reserved, must be cleared.

10–8IInterrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or

7–0

CCR

Trace enable. When set, the processor performs a trace exception after every instruction.

T

Supervisor/user state.

S

0User mode
1 Supervisor mode

Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or

M

move to SR instructions.

equal to current level, except edge-sensitive level 7 requests, which cannot be masked.

Refer to Section 3.2.4, “Condition Code Register (CCR)”.

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IAG IC IB

Core Bus
Address

Core Bus

Read Data

Opword

Extension 1

Extension 2

FIFO

IB

+4

3.3 Functional Description

3.3.1 Version 2 ColdFire Microarchitecture

From the block diagram in Figure 3-1, the non-Harvard architecture of the processor is readily apparent.
The processor interfaces to the local memory subsystem via a single 32-bit address and two unidirectional
32-bit data buses. This structure minimizes the core size without compromising performance to a large
degree.

A more detailed view of the hardware structure within the two pipelines is presented in Figure 3-9 and

Figure 3-10 below. In these diagrams, the internal structure of the instruction fetch and operand execution

pipelines is shown:

Figure 3-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram

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DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus
Address

Core Bus
Write Data

RGF

Figure 3-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram

The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For
sequential prefetches, the next instruction address is generated by adding four to the last prefetch address.
This function is performed during the IAG stage and the resulting prefetch address gated onto the core bus
(if there are no pending operand memory accesses assigned a higher priority). After the prefetch address
is driven onto the core bus, the instruction fetch cycle accesses the appropriate local memory and returns
the instruction read data back to the IFP during the cycle. If the accessed data is not present in a local
memory (e.g., an instruction cache miss, or an external access cycle is required), the IFP is stalled in the
IC stage until the referenced data is available. As the prefetch data arrives in the IFP, it can be loaded into
the FIFO instruction buffer or gated directly into the OEP.

The V2 design uses a simple static conditional branch prediction algorithm (forward-assumed as
not-taken, backward-assumed as taken), and all change-of-flow operations are calculated by the OEP and
the target instruction address fed back to the IFP.

The IFP and OEP are decoupled by the FIFO instruction buffer, allowing instruction prefetching to occur
with the available core bus bandwidth not used for operand memory accesses. For the V2 design, the
instruction buffer contains three 32-bit locations.

Consider the operation of the OEP for three basic classes of non-branch instructions:

• Register-to-register:

op Ry,Rx

• Embedded load:

op <mem>y,Rx

• Register-to-memory (store)

move Ry,<mem>x

For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and
fetching of the required register operands (OC) from the dual-ported register file, while the actual

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Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus
Address

Core Bus
Write

Data

new Rx

Rx

Ry

RGF

instruction execution is performed in the second stage (EX) in one of the execute engines (e.g., ALU,
barrel shifter, divider, EMAC). There are no operand memory accesses associated with this class of
instructions, and the execution time is typically a single machine cycle. See Figure 3-11.

Figure 3-11. V2 OEP Register-to-Register

For memory-to-register (embedded-load) instructions, the instruction is effectively staged through the
OEP twice with a basic execution time of three cycles. First, the instruction is decoded and the components
of the operand address (base register from the RGF and displacement) are selected (DS). Second, the
operand effective address is generated using the ALU execute engine (AG). Third, the memory read
operand is fetched from the core bus, while any required register operand is simultaneously fetched (OC)
from the RGF. Finally, in the fourth cycle, the instruction is executed (EX). The heavily-used 32-bit load
instruction (

move.l <mem>y,Rx) is optimized to support a two-cycle execution time. The following example

in Figure 3-12 shows an effective address of the form <ea>y = (d16,Ay), i.e., a 16-bit signed displacement
added to a base register Ay.

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Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus
Address

Core Bus
Write

RGF

Data

Ay

d16

<ea>y

Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus
Address

Core Bus
Write

RGF

Data

Rx

new Rx

<mem>y

Figure 3-12. V2 OEP Embedded-Load Part 1

Figure 3-13. V2 OEP Embedded-Load Part 2

For register-to-memory (store) operations, the stage functions (DS/OC, AG/EX) are effectively performed
simultaneously allowing single-cycle execution. See Figure 3-14 where the effective address is of the form
<ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax.

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Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus
Address

Core Bus
Write

RGF

Data

Ax

d16

Ry

<ea>x

For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store
operation for a three-cycle execution time.

Figure 3-14. V2 OEP Register-to-Memory

The pipeline timing diagrams of Figure 3-15 depict the execution templates for these three classes of
instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown
progressing down the operand execution pipeline.

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Core clock

Register-to-Register

Core Bus

Embedded-Load

Core Bus

Register-to-Memory

op read

Core Bus

op write

OEP.DSOC OC next

OEP.AGEX EX

OEP.DSOC DS OC next

OEP.AGEX EXAG

OEP.DSOC DSOC next

OEP.AGEX AGEX

(Store)

3.3.2 Instruction Set Architecture (ISA_A+)

The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes
based on extensive analysis of embedded application code. The ISA was optimized for code compiled
from high-level languages where the dominant operand size was the 32-bit integer declaration. This
approach minimized processor complexity and cost, while providing excellent performance for compiled
applications.

After the initial ColdFire compilers were created, developers noted there were certain ISA additions that
would enhance code density and overall performance. Additionally, as users implemented ColdFire-based
designs into a wide range of embedded systems, they found certain frequently-used instruction sequences
that could be improved by the creation of additional instructions.

The original ISA definition minimized support for instructions referencing byte- and word-sized operands.
Full support for the move byte and move word instructions was provided, but the only other opcodes
supporting these data types are CLR (clear) and TST (test). A set of instruction enhancements has been
implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three
areas:

Figure 3-15. V2 OEP Pipeline Execution Templates

1. Enhanced support for byte and word-sized operands

2. Enhanced support for position-independent code

3. Miscellaneous instruction additions to address new functionality

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2. The processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller. The IACK cycle is mapped to special locations within the interrupt
controller’s address space with the interrupt level encoded in the address.

Table 3-4 summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details

see the ColdFire Family Programmer’s Reference Manual.

Table 3-4. Instruction Enhancements over Revision ISA_A

Instruction Description

BITREV The contents of the destination data register are bit-reversed; new Dn[31] equals old Dn[0], new

Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31].

BYTEREV The contents of the destination data register are byte-reversed; new Dn[31:24] equals old

Dn[7:0],..., new Dn[7:0] equals old Dn[31:24].

FF1 The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending

with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.

Move from USP USP → Destination register

Move to USP Source register → USP

STLDSR Pushes the contents of the status register onto the stack and then reloads the status register

with the immediate data value.

3.3.3 Exception Processing Overview

Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
differ from the M68000 family because they include:

• A simplified exception vector table

• Reduced relocation capabilities using the vector-base register

• A single exception stack frame format

• Use of separate system stack pointers for user and supervisor modes.

All ColdFire processors use an instruction restart exception model. However, Version 2 ColdFire
processors require more software support to recover from certain access errors. See Section 3.3.4.1,

“Access Error Exception” for details.

Exception processing includes all actions from fault condition detection to the initiation of fetch for first
handler instruction. Exception processing is comprised of four major steps:

1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to
be cleared and the interrupt priority mask to set to current interrupt request level.

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All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see

Table 3-5).

3. The processor saves the current context by creating an exception stack frame on the system stack.
The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to
by the supervisor stack pointer (SSP). As shown in Figure 3-16, the processor uses a simplified
fixed-length stack frame for all exceptions. The exception type determines whether the program
counter placed in the exception stack frame defines the location of the faulting instruction (fault)
or the address of the next instruction to be executed (next).

4. The processor calculates the address of the first instruction of the exception handler. By definition,
the exception vector table is aligned on a 1 Mbyte boundary. This instruction address is generated
by fetching an exception vector from the table located at the address defined in the vector base
register. The index into the exception table is calculated as (4 × vector number). After the exception
vector has been fetched, the vector contents determine the address of the first instruction of the
desired handler. After the instruction fetch for the first opcode of the handler has initiated,
exception processing terminates and normal instruction processing continues in the handler.

The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are
device-specific peripheral interrupt vectors. See Chapter 15, “Interrupt Controller Modules” for details on
the device-specific interrupt sources.

Table 3-5. Exception Vector Assignments

Vector

Number(s)

0 0x000 — Initial supervisor stack pointer

1 0x004 — Initial program counter

2 0x008 Fault Access error

3 0x00C Fault Address error

4 0x010 Fault Illegal instruction

5 0x014 Fault Divide by zero

6–7 0x018–0x01C — Reserved

8 0x020 Fault Privilege violation

9 0x024 Next Trace

10 0x028 Fault Unimplemented line-A opcode

11 0x02C Fault Unimplemented line-F opcode

12 0x030 Next Debug interrupt

13 0x034 — Reserved

14 0x038 Fault Format error

15–23 0x03C–0x05C — Reserved

24 0x060 Next Spurious interrupt

Vector

Offset (Hex)

Stacked

Program

Counter

Assignment

25–31 0x064–0x07C — Reserved

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Table 3-5. Exception Vector Assignments (continued)

ColdFire Core

Vector

Number(s)

32–47 0x080–0x0BC Next Trap # 0-15 instructions

48–63 0x0C0–0x0FC — Reserved

64–255 0x100–0x3FC Next Device-specific interrupts

1

Fault refers to the PC of the instruction that caused the exception. Next refers to the PC
of the instruction that follows the instruction that caused the fault.

Vector

Offset (Hex)

Stacked

Program

Counter

Assignment

All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level
contained in the status register. In addition, the ISA_A+ architecture includes an instruction (STLDSR)
that stores the current interrupt mask level and loads a value into the SR. This instruction is specifically
intended for use as the first instruction of an interrupt service routine that services multiple interrupt
requests with different interrupt levels. For more details, see ColdFire Family Programmer’s Reference
Manual.

3.3.3.1 Exception Stack Frame Definition

Figure 3-16 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)

and the 16-bit status register, and the second longword contains the 32-bit program counter address.

313029282726252423222120191817161514131211109876543210

SSP → Format FS[3:2] Vector FS[1:0] Status Register

+ 0x4

Program Counter

Figure 3-16. Exception Stack Frame Form

The 16-bit format/vector word contains three unique fields:

• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by
the processor, indicating a two-longword frame format. See Table 3-6.

Table 3-6. Format Field Encodings

Original SSP @ Time

of Exception, Bits 1:0

00 Original SSP - 8 0100

01 Original SSP - 9 0101

10 Original SSP - 10 0110

11 Original SSP - 11 0111

SSP @ 1st

Instruction of

Handler

Format Field

• There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for
access and address errors only and written as zeros for all other exceptions. See Table 3- 7.

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Table 3-7. Fault Status Encodings

FS[3:0] Definition

00xx Reserved

0100 Error on instruction fetch

0101 Reserved

011x Reserved

1000 Error on operand write

1001 Attempted write to write-protected space

101x Reserved

1100 Error on operand read

1101 Reserved

111x Reserved

• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor
for all internal faults and represents the value supplied by the interrupt controller in case of an
interrupt. See Table 3-5.

3.3.4 Processor Exceptions

3.3.4.1 Access Error Exception

The exact processor response to an access error depends on the memory reference being performed. For
an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an
instruction for execution. Therefore, faults during instruction prefetches followed by a change of
instruction flow do not generate an exception. When the processor attempts to execute an instruction with
a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For this
type of exception, the programming model has not been altered by the instruction generating the access
error.

If the access error occurs on an operand read, the processor immediately aborts the current instruction’s
execution and initiates exception processing. In this situation, any address register updates attributable to
the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming
model contains the updated An value. In addition, if an access error occurs during a MOVEM instruction
loading from memory, any registers already updated before the fault occurs contain the operands from
memory.

The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes.
Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the
signaling of an access error appears to be decoupled from the instruction that generated the write.
Accordingly, the PC contained in the exception stack frame merely represents the location in the program
when the access error was signaled. All programming model updates associated with the write instruction
are completed. The NOP instruction can collect access errors for writes. This instruction delays its

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execution until all previous operations, including all pending write operations, are complete. If any
previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.

3.3.4.2 Address Error Exception

Any attempted execution transferring control to an odd instruction address (if bit 0 of the target address is
set) results in an address error exception.

Any attempted use of a word-sized index register (Xn.w) or a scale factor of eight on an indexed effective
addressing mode generates an address error, as does an attempted execution of a full-format indexed
addressing mode, which is defined by bit 8 of extension word 1 being set.

If an address error occurs on a JSR instruction, the Version 2 ColdFire processor calculates the target
address then the return address is pushed onto the stack.If an address error occurs on an RTS instruction,
the Version 2 ColdFire processor overwrites the faulting return PC with the address error stack frame.

3.3.4.3 Illegal Instruction Exception

The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits.
The first instruction word is known as the operation word (or opword), while the optional words are known
as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper
four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode
(opmode), and the low-order 6 bits define the effective address. See Figure 3-17. The opword line
definition is shown in Table 3-8.

1514131211109876543210

Line OpMode Effective Address

Mode Register

Figure 3-17. ColdFire Instruction Operation Word (Opword) Format

Table 3-8. ColdFire Opword Line Definition

Opword[Line] Instruction Class

0x0 Bit manipulation, Arithmetic and Logical Immediate

0x1 Move Byte

0x2 Move Long

0x3 Move Word

0x4 Miscellaneous

0x5 Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc)

0x6 PC-relative change-of-flow instructions

Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR)

0x7 Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ)

0x8 Logical OR (OR)

0x9 Subtract (SUB), Subtract Extended (SUBX)

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Table 3-8. ColdFire Opword Line Definition (continued)

Opword[Line] Instruction Class

0xA EMAC, Move 3-bit Quick (MOV3Q)

0xB Compare (CMP), Exclusive-OR (EOR)

0xC Logical AND (AND), Multiply Word (MUL)

0xD Add (ADD), Add Extended (ADDX)

0xE Arithmetic and logical shifts (ASL, ASR, LSL, LSR)

0xF Cache Push (CPUSHL), Write DDATA (WDDATA), Write Debug (WDEBUG)

In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations
(line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors
associated with illegal opwords in these two lines.

Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an
illegal instruction exception (vector 4). Additionally, any attempted execution of any non-MAC line-A and
most line-F opcodes generate their unique exception types, vector numbers 10 and 11, respectively.
ColdFire cores do not provide illegal instruction detection on the extension words on any instruction,
including MOVEC.

3.3.4.4 Divide-By-Zero

Attempting to divide by zero causes an exception (vector 5, offset equal 0x014).

3.3.4.5 Privilege Violation

The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. See ColdFire Programmer’s Reference Manual for a list of supervisor-mode
instructions.

There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode
instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in
user mode for debugging purposes.

3.3.4.6 Trace Exception

To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing
capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction
execution (for all but the stop instruction) signals a trace exception. This functionality allows a debugger
to monitor program execution.

The stop instruction has the following effects:

1. The instruction before the stop executes and then generates a trace exception. In the exception stack
frame, the PC points to the stop opcode.

2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate
operand from the instruction.

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3. The processor then generates a trace exception. The PC in the exception stack frame points to the
instruction after the stop, and the SR reflects the value loaded in the previous step.

If the processor is not in trace mode and executes a stop instruction where the immediate operand sets
SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points
to the instruction after the stop, and the SR reflects the value loaded in step 2.

Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types. As
an example, consider a TRAP instruction execution while in trace mode. The processor initiates the trap
exception and then passes control to the corresponding handler. If the system requires that a trace exception
be processed, it is the responsibility of the trap exception handler to check for this condition (SR[T] in the
exception stack frame set) and pass control to the trace handler before returning from the original
exception.

3.3.4.7 Unimplemented Line-A Opcode

A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the
attempted execution of an undefined line-A opcode.

3.3.4.8 Unimplemented Line-F Opcode

A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when
attempting to execute an undefined line-F opcode.

3.3.4.9 Debug Interrupt

See Chapter 32, “Debug Module,” for a detailed explanation of this exception, which is generated in
response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle, but
rather calculates the vector number internally (vector number 12). Additionally, SR[M,I] are unaffected by
the interrupt.

3.3.4.10 RTE and Format Error Exception

When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the
frame type. For a ColdFire core, any attempted RTE execution (where the format is not equal to {4,5,6,7})
generates a format error. The exception stack frame for the format error is created without disturbing the
original RTE frame and the stacked PC pointing to the RTE instruction.

The selection of the format value provides some limited debug support for porting code from M68000
applications. On M68000 family processors, the SR was located at the top of the stack. On those
processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE
is attempted using this old format, it generates a format error on a ColdFire processor.

If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second
longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address
after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the
second longword operand within the stack frame.

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3.3.4.11 TRAP Instruction Exception

The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing
system calls. The TRAP instruction may be used to change from user to supervisor mode.

3.3.4.12 Unsupported Instruction Exception

If execution of a valid instruction is attempted but the required hardware is not present in the processor, an
unsupported instruction exception is generated. The instruction functionality can then be emulated in the
exception handler, if desired.

All ColdFire cores record the processor hardware configuration in the D0 register immediately after the
negation of RESET. See Section 3.3.4.15, “Reset Exception,” for details.

3.3.4.13 Interrupt Exception

Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from
the interrupt controller using an IACK cycle. See Chapter 15, “Interrupt Controller Modules,” for details
on the interrupt controller.

3.3.4.14 Fault-on-Fault Halt

If a ColdFire processor encounters any type of fault during the exception processing of another fault, the
processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to
force the processor to exit this halted state.

3.3.4.15 Reset Exception

Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from catastrophic
failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot
be recovered.

The reset exception places the processor in the supervisor mode by setting the SR[S] bit and disables
tracing by clearing the SR[T] bit. This exception also clears the SR[M] bit and sets the processor’s SR[I]
bit to the highest level (level 7, 0b111). Next, the VBR is initialized to zero (0x0000_0000). The control
registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly
to the processor are disabled.

NOTE

Other implementation-specific registers are also affected. Refer to each
module in this reference manual for details on these registers.

After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at
address 0x0000_0000 is loaded into the supervisor stack pointer and the second longword at address
0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory,
program execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault state.

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(This is the value used for this device.)

ColdFire processors load hardware configuration information into the D0 and D1 general-purpose
registers after system reset. The hardware configuration information is loaded immediately after the
reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM
to determine the hardware configuration.

Information loaded into D0 defines the processor hardware configuration as shown in Figure 3-18.

BDM: Load: 0x080 (D0)

Store: 0x180 (D0)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R PF VER REV

W

Reset110011110010 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R MAC DIVEMACFPUMMU000 ISA DEBUG

W

Reset 0 1 1 0000010001001

Access: User read-only

BDM read-only

Figure 3-18. D0 Hardware Configuration Info

Table 3-9. D0 Hardware Configuration Info Field Description

Field Description

31–24PFProcessor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.

23–20

VER

ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core.
0001 V1 ColdFire core
0010 V2 ColdFire core (This is the value used for this device.)
0011 V3 ColdFire core
0100 V4 ColdFire core
0101 V5 ColdFire core
Else Reserved for future use

19–16

REV

MAC

EMAC

FPU

Freescale Semiconductor 3-23

Processor revision number. The default is 0b0000.

15

MAC present. This bit signals if the optional multiply-accumulate (MAC) execution engine is present in processor core.
0 MAC execute engine not present in core. (This is the value used for this device.)
1 MAC execute engine is present in core.

14

Divide present. This bit signals if the hardware divider (DIV) is present in the processor core.

DIV

0 Divide execute engine not present in core.
1 Divide execute engine is present in core.

13

EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution engine is present in
processor core.
0 EMAC execute engine not present in core.
1 EMAC execute engine is present in core. (This is the value used for this device.)

12

FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core.
0 FPU execute engine not present in core. (This is the value used for this device.)
1 FPU execute engine is present in core.

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ColdFire Core

Table 3-9. D0 Hardware Configuration Info Field Description (continued)

Field Description

11

MMU present. This bit signals if the optional virtual memory management unit (MMU) is present in processor core.

MMU

10–8 Reserved.

DEBUG

0 MMU execute engine not present in core. (This is the value used for this device.)
1 MMU execute engine is present in core.

7–4

ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core.

ISA

0000 ISA_A
0001 ISA_B
0010 ISA_C
1000 ISA_A+ (This is the value used for this device.)
Else Reserved

3–0

Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core.
0000 DEBUG_A
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
1001 DEBUG_B+ (This is the value used for this device.)
1011 DEBUG_D+
Else Reserved

Information loaded into D1 defines the local memory hardware configuration as shown in the figure below.

BDM: Load: 0x081 (D1)

Store: 0x181 (D1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RCLSZ CCAS CCSZ 00000000

W

Reset0001010100000000

1514131211109876543210

RMBSZ 000000 SRAMSZ 0000

W

Reset 000 000010010000

Figure 3-19. D1 Hardware Configuration Info

Access: User read-only

BDM read-only

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3-24 Freescale Semiconductor

Table 3-10. D1 Hardware Configuration Information Field Description

Field Description

ColdFire Core

31–30

CLSZ

29–28
CCAS

27–24
CCSZ

23–16 Reserved.

15–14
MBSZ

13–8 Reserved, resets to 0b010000

Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.

Configurable cache associativity.
00 Four-way
01 Direct mapped (This is the value used for this device)
Else Reserved for future use

Configurable cache size. Indicates the amount of instruction/data cache. The cache configuration options
available are 50% instruction/50% data, 100% instruction, or 100% data, and are specified in the CACR register.
0000 No configurable cache
0001 512B configurable cache
0010 1KB configurable cache
0011 2KB configurable cache
0100 4KB configurable cache
0101 8KB configurable cache (This is the value used for this device)
0110 16KB configurable cache
0111 32KB configurable cache
Else Reserved

Bus size. Defines the width of the ColdFire master bus datapath.
00 32-bit system bus datapath (This is the value used for this device)
01 64-bit system bus datapath
Else Reserved

7–4

SRAMSZ

3-0 Reserved.

SRAM bank size.
0000 No SRAM
0001 512 bytes
0010 1 Kbytes
0011 2 Kbytes
0100 4 Kbytes
0101 8 Kbytes
0110 16 Kbytes
0111 32 Kbytes
1000 64 Kbytes
1001 128 Kbytes (This is the value used for this device)
Else Reserved for future use

3.3.5 Instruction Execution Timing

This section presents processor instruction execution times in terms of processor-core clock cycles. The
number of operand references for each instruction is enclosed in parentheses following the number of
processor clock cycles. Each timing entry is presented as C(R/W) where:

•C is the number of processor clock cycles, including all applicable operand fetches and writes, and
all internal core cycles required to complete the instruction execution.

• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation
performing a read-modify-write function is denoted as (1/1).

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This section includes the assumptions concerning the timing values and the execution time details.

3.3.5.1 Timing Assumptions

For the timing data presented in this section, these assumptions apply:

1. The OEP is loaded with the opword and all required extension words at the beginning of each
instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or
extension words.

2. The OEP does not experience any sequence-related pipeline stalls. The most common example of
stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE
operations (except MOVEM), certain hardware resources within the processor are marked as busy
for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store
instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is
stalled until the resource again becomes available. Thus, the maximum pipeline stall involving
consecutive STORE operations is two cycles. The MOVEM instruction uses a different set of
resources and this stall does not apply.

3. The OEP completes all memory accesses without any stall conditions caused by the memory itself.
Thus, the timing details provided in this section assume that an infinite zero-wait state memory is
attached to the processor core.

4. All operand data accesses are aligned on the same byte boundary as the operand size; for example,
16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4
addresses.

The processor core decomposes misaligned operand references into a series of aligned accesses as
shown in Table 3-11.

Table 3-11. Misaligned Operand References

address[1:0] Size

01 or 11 Word Byte, Byte 2(1/0) if read

01 or 11 Long Byte, Word,

10 Long Word, Word 2(1/0) if read

Bus

Operations

Byte

Additional

C(R/W)

1(0/1) if write

3(2/0) if read

2(0/2) if write

1(0/1) if write

3.3.5.2 MOVE Instruction Execution Times

Table 3-12 lists execution times for MOVE.{B,W} instructions; Table 3-13 lists timings for MOVE.L.

NOTE

For all tables in this section, the execution time of any instruction using the
PC-relative effective addressing modes is the same for the comparable
An-relative mode.

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ColdFire Core

ET with {<ea> = (d16,PC)} equals ET with {<ea> = (d16,An)}

ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<ea> = (d8,An,Xi*SF)}

The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w
and xxx.l.

Table 3-12. MOVE Byte and Word Execution Times

Destination

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1)

(Ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1)

-(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1)

(d16,Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,Ay,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

xxx.w 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

xxx.l 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1)) — — —

#xxx 1(0/0) 3(0/1) 3(0/1) 3(0/1) — — —

Table 3-13. MOVE Long Execution Times

Destination

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

(Ay)+ 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

-(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

(d16,Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

(d8,Ay,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

(d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

(d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

#xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — —

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3.3.5.3 Standard One Operand Instruction Execution Times

Table 3-14. One Operand Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

BITREVDx1(0/0)———— — ——

BYTEREVDx1(0/0)———— — ——

CLR.B <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

CLR.W <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

CLR.L <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

EXT.WDx1(0/0)———— — ——

EXT.LDx1(0/0)———— — ——

EXTB.LDx1(0/0)———— — ——

FF1Dx1(0/0)———— — ——

NEG.LDx1(0/0)———— — ——

NEGX.LDx1(0/0)———— — ——

NOT.LDx1(0/0)———— — ——

SCCDx1(0/0)———— — ——

SWAPDx1(0/0)———— — ——

TST.B <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

TST.W <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

TST.L <ea> 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)

3.3.5.4 Standard Two Operand Instruction Execution Times

Table 3-15. Two Operand Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

ADD.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

ADD.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ADDI.L #imm,Dx 1(0/0) — — — — — — —

ADDQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ADDX.L Dy,Dx 1(0/0) — — — — — — —

AND.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

AND.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ANDI.L #imm,Dx 1(0/0) — — — — — — —

(d16,An)
(d16,PC)

(d8,An,Xn*SF)
(d8,PC,Xn*SF)

xxx.wl #xxx

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Table 3-15. Two Operand Instruction Execution Times (continued)

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

ASL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

ASR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

BCHG Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

BCHG #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

BCLR Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

BCLR #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

BSET Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

BSET #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

BTST Dy,<ea> 2(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —

BTST #imm,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —

CMP.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

CMPI.L #imm,Dx 1(0/0) — — — — — — —

DIVS.W <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)

DIVU.W <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)

DIVS.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —
DIVU.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —

EOR.L Dy,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

EORI.L #imm,Dx 1(0/0) — — — — — — —

LEA <ea>,Ax — 1(0/0) — — 1(0/0) 2(0/0) 1(0/0) —

LSL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

LSR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

MOVEQ.L #imm,Dx — — — — — — — 1(0/0)

OR.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

OR.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ORI.L #imm,Dx 1(0/0) — — — — — — —

REMS.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —
REMU.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —

SUB.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

SUB.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

SUBI.L #imm,Dx 1(0/0) — — — — — — —

SUBQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

SUBX.L Dy,Dx 1(0/0) — — — — — — —

(d16,An)
(d16,PC)

(d8,An,Xn*SF)
(d8,PC,Xn*SF)

xxx.wl #xxx

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3.3.5.5 Miscellaneous Instruction Execution Times

Table 3-16. Miscellaneous Instruction Execution Times

Effective Address

Opcode <EA>

CPUSHL (Ax) — 11(0/1) — — — — — —

LINK.W Ay,#imm 2(0/1) — — — — — — —

MOVE.L Ay,USP 3(0/0) — — — — — — —

MOVE.L USP,Ax 3(0/0) — — — — — — —

MOVE.W CCR,Dx 1(0/0) — — — — — — —

MOVE.W <ea>,CCR 1(0/0) — — — — — — 1(0/0)

MOVE.W SR,Dx 1(0/0) — — — — — — —

MOVE.W <ea>,SR 7(0/0) — — — — — — 7(0/0)

MOVEC Ry,Rc 9(0/1) — — — — — — —

MOVEM.L <ea>,&list — 1+n(n/0) — — 1+n(n/0) — — —

MOVEM.L &list,<ea> — 1+n(0/n) — — 1+n(0/n) — — —

NOP 3(0/0)———— — ——

PEA <ea> — 2(0/1) — — 2(0/1)

PULSE 1(0/0)———— — ——

STLDSR#imm————— — —5(0/1)

STOP#imm————— — —3(0/0)

TRAP#imm————— — —15(1/2)

TPF 1(0/0)———— — ——

TPF.W 1(0/0)———— — ——

TPF.L 1(0/0)———— — ——

UNLK Ax 2(1/0) — — — — — — —

WDDATA <ea> — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —

WDEBUG<ea> —5(2/0)— —5(2/0) — — —

1

The n is the number of registers moved by the MOVEM opcode.

2

If a MOVE.W #imm,SR instruction is executed and imm[13] equals 1, the execution time is 1(0/0).

3

The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.

4

PEA execution times are the same for (d16,PC).

5

PEA execution times are the same for (d8,PC,Xn*SF).

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

4

3(0/1)

5

2(0/1) —

2

3

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3.3.5.6 EMAC Instruction Execution Times

Table 3-17. EMAC Instruction Execution Times

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An)

MAC.L Ry, Rx, Raccx 1(0/0) — — — — — — —

MAC.L Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)

MAC.W Ry, Rx, Raccx 1(0/0) — — — — — — —

MAC.W Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)

MOVE.L <ea>y, Raccx 1(0/0) — — — — — — 1(0/0)

MOVE.L Raccy,Raccx 1(0/0) — — — — — — —

MOVE.L <ea>y, MACSR 5(0/0) — — — — — — 5(0/0)

MOVE.L <ea>y, Rmask 4(0/0) — — — — — — 4(0/0)

MOVE.L <ea>y,Raccext01 1(0/0) — — — — — — 1(0/0)

Effective Address

1

1

ColdFire Core

(d8,An,
Xn*SF)

xxx.wl #xxx

———

———

MOVE.L <ea>y,Raccext23 1(0/0) — — — — — — 1(0/0)

2

MOVE.L Raccx,<ea>x 1(0/0)

——— — — ——

MOVE.L MACSR,<ea>x 1(0/0) — — — — — — —

MOVE.L Rmask, <ea>x 1(0/0) — — — — — — —

MOVE.L Raccext01,<ea.x 1(0/0) — — — — — — —

MOVE.L Raccext23,<ea>x 1(0/0) — — — — — — —

MSAC.L Ry, Rx, Raccx 1(0/0) — — — — — — —

MSAC.W Ry, Rx, Raccx 1(0/0) — — — — — — —

MSAC.L Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)

MSAC.W Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)

1

———

1

———

MULS.L <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) — — —

MULS.W <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) (1/0) (1/0) 4(0/0)

MULU.L <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) — — —

MULU.W <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) (1/0) (1/0) 4(0/0)

1

Effective address of (d16,PC) not supported

2

Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional
rounding is performed (MACSR[7:4] equals 1---, -11-, --11)

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NOTE

The execution times for moving the contents of the Racc, Raccext[01,23],
MACSR, or Rmask into a destination location <ea>x shown in this table
represent the best-case scenario when the store instruction is executed and
there are no load or M{S}AC instructions in the EMAC execution pipeline.
In general, these store operations require only a single cycle for execution,
but if preceded immediately by a load, MAC, or MSAC instruction, the
depth of the EMAC pipeline is exposed and the execution time is four
cycles.

3.3.5.7 Branch Instruction Execution Times

Table 3-18. General Branch Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

BRA — — — — 2(0/1) — — —

BSR — — — — 3(0/1) — — —

(d16,An)
(d16,PC)

(d8,An,Xi*SF)

(d8,PC,Xi*SF)

xxx.wl #xxx

JMP <ea> — 3(0/0) — — 3(0/0) 4(0/0) 3(0/0) —

JSR <ea> — 3(0/1) — — 3(0/1) 4(0/1) 3(0/1) —

RTE — — 10(2/0) — — — — —

RTS ——5(1/0)—————

Table 3-19. Bcc Instruction Execution Times

Opcode

Bcc 3(0/0) 1(0/0) 2(0/0) 3(0/0)

Forward

Taken

Forward

Not Taken

Backward

Taken

Backward
Not Taken

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Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)

4.1 Introduction

This chapter describes the functionality, microarchitecture, and performance of the enhanced
multiply-accumulate (EMAC) unit in the ColdFire family of processors.

4.1.1 Overview

The EMAC design provides a set of DSP operations that can improve the performance of embedded code
while supporting the integer multiply instructions of baseline ColdFire architecture.

The MAC provides functionality in three related areas:

1. Signed and unsigned integer multiplication

2. Multiply-accumulate operations supporting signed and unsigned integer operands as well as
signed, fixed-point, fractional operands

3. Miscellaneous register operations

The ColdFire family supports two MAC implementations with different performance levels and
capabilities. The original MAC features a three-stage execution pipeline optimized for 16-bit operands,
with a 16x16 multiply array and a single 32-bit accumulator. The EMAC features a four-stage pipeline
optimized for 32-bit operands, with a fully pipelined 32 × 32 multiply array and four 48-bit accumulators.

The first ColdFire MAC supported signed and unsigned integer operands and was optimized for 16x16
operations, such as those found in applications including servo control and image compression. As
ColdFire-based systems proliferated, the desire for more precision on input operands increased. The result
was an improved ColdFire MAC with user-programmable control to optionally enable use of fractional
input operands.

EMAC improvements target three primary areas:

• Improved performance of 32 × 32 multiply operation.

• Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges
between the accumulator and the pipeline’s general-purpose registers

• A 48-bit accumulation data path to allow a 40-bit product, plus 8 extension bits increase the
dynamic number range when implementing signal processing algorithms

The three areas of functionality are addressed in detail in following sections. The logic required to support
this functionality is contained in a MAC module (Figure 4-1).

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Enhanced Multiply-Accumulate Unit (EMAC)

X

+

/

-

Operand Y Operand X

Shift 0,1,-1

Accumulator(s)

yi() ak()yi k–()

k1=

N1–

∑

bk()xi k–()

k0=

N1–

∑

+=

yi() bk()xi k–()

3

∑

b0()xi() b1()xi 1–()b2()xi 2–()b3()xi 3–()+++==

Figure 4-1. Multiply-Accumulate Functionality Diagram

4.1.1.1 Introduction to the MAC

The MAC is an extension of the basic multiplier in most microprocessors. It is typically implemented in
hardware within an architecture and supports rapid execution of signal processing algorithms in fewer
cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some
variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal
transforms may have more demanding speed requirements beyond scope of any processor architecture and
may require full DSP implementation.

To balance among speed, size, and functionality, the ColdFire MAC is optimized for a small set of
operations that involve multiplication and cumulative additions. Specifically, the multiplier array is
optimized for single-cycle pipelined operations with a possible accumulation after product generation.
This functionality is common in many signal processing applications. The ColdFire core architecture is
also modified to allow an operand to be fetched in parallel with a multiply, increasing overall performance
for certain DSP operations.

Consider a typical filtering operation where the filter is defined as in Equation 4-1.

Eqn. 4-1

Here, the output y(i) is determined by past output values and past input values. This is the general form of
an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting
coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies
and product summing. To show this point, reduce Equation 4-1 to a simple, four-tap FIR filter, shown in

Equation 4-2, in which the accumulated sum is a past data values and coefficients sum.

Eqn. 4-2

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4.2 Memory Map/Register Definition

The following table and sections explain the MAC registers:

Table 4-1. EMAC Memory Map

Enhanced Multiply-Accumulate Unit (EMAC)

1

BDM

0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 4.2.1/4-3

0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF 4.2.2/4-5

0x806 MAC Accumulator 0 (ACC0) 32 R/W Undefined 4.2.3/4-6

0x807 MAC Accumulator 0,1 Extension Bytes (ACCext01) 32 R/W Undefined 4.2.4/4-7

0x808 MAC Accumulator 2,3 Extension Bytes (ACCext23) 32 R/W Undefined 4.2.4/4-7

0x809 MAC Accumulator 1 (ACC1) 32 R/W Undefined 4.2.3/4-6

0x80A MAC Accumulator 2 (ACC2) 32 R/W Undefined 4.2.3/4-6

0x80B MAC Accumulator 3 (ACC3) 32 R/W Undefined 4.2.3/4-6

1

The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see Chapter 32, “Debug Module.”

Register

Width

(bits)

Access Reset Value Section/Page

4.2.1 MAC Status Register (MACSR)

The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and multiple overflow condition flags are also provided.

BDM: 0x804 (MACSR) Access: Supervisor read/write

BDM read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

W

Reset000000000000000000000000 0 0 0 0 0 0 0 0

PAV n OMC

S/U F/I R/T N Z VEV

Figure 4-2. MAC Status Register (MACSR)

Table 4-2. MACSR Field Descriptions

Field Description

31–12 Reserved, must be cleared.

11–8

PAV n

Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or
MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a
MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator is used
to form the general overflow flag, MACSR[V]. After set, each flag remains set until V is cleared by a
move.l, MACSR instruction or the accumulator is loaded directly.

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Table 4-2. MACSR Field Descriptions (continued)

Field Description

7

OMC

6

S/U

5

F/I

Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set
to the appropriate constant on any operation that overflows the accumulator. After saturation, the
accumulator remains unaffected by any other MAC or MSAC instructions until the overflow bit is cleared or
the accumulator is directly loaded.

Signed/unsigned operations.

In integer mode:

S/U determines whether operations performed are signed or unsigned. It also determines the accumulator
value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, an accumulator saturates to the most positive

(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on the instruction and the
product value that overflowed.

1 Unsigned numbers. On overflow, if OMC is enabled, an accumulator saturates to the smallest value

(0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.

In fractional mode:

S/U controls rounding while storing an accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose

register as a 32-bit value.

1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when moved to

a general-purpose register. See Section 4.3.1.1, “Rounding”. The resulting 16-bit value is stored in the
lower word of the destination register. The upper word is zero-filled. This rounding procedure does not
affect the accumulator value.

Fractional/integer mode. Determines whether input operands are treated as fractions or integers.
0 Integers can be represented in signed or unsigned notation, depending on the value of S/U.
1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to

-15

for 16-bit fractions and -1 to 1 - 2

1-2

-31

for 32-bit fractions. See Section 4.3.4, “Data

Representation."

4

R/T

3

N

2
Z

Round/truncate mode. Controls rounding procedure for move.l ACCx,Rx, or MSAC.L instructions when
in fractional mode.
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator. Additionally, when

a store accumulator instruction is executed (move.l ACCx,Rx), the 8 lsbs of the 48-bit accumulator
logic are truncated.

1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest

40-bit value. If the low-order 24 bits equal 0x80_0000, the upper 40 bits are rounded to the nearest even
(lsb = 0) value. See Section 4.3.1.1, “Rounding”. Additionally, when a store accumulator instruction is
executed (move.l ACCx,Rx), the lsbs of the 48-bit accumulator logic rounds the resulting 16- or 32-bit
value. If MACSR[S/U] is cleared and MACSR[R/T] is set, the low-order 8 bits are used to round the
resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit
fraction.

Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.

Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.

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Table 4-2. MACSR Field Descriptions (continued)

Field Description

Enhanced Multiply-Accumulate Unit (EMAC)

1

V

0

EV

Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction, indicating that the result
cannot be represented in the limited width of the EMAC. V is set only if a product overflow occurs or the
accumulation overflows the 48-bit structure. V is evaluated on each MAC or MSAC operation and uses the
appropriate PAVn flag in the next-state V evaluation.

Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in integer mode
or the 40 lsbs in fractional mode of the destination accumulator. However, the result remains accurately
represented in the combined 48-bit accumulator structure. Although an overflow has occurred, the correct
result, sign, and magnitude are contained in the 48-bit accumulator. Subsequent MAC or MSAC operations
may return the accumulator to a valid 32/40-bit result.

Table 4-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.

Table 4-3. Summary of S/U, F/I, and R/T Control Bits

S/U F/I R/T Operational Modes

0 0 x Signed, integer

0 1 0 Signed, fractional

Truncate on MAC.L and MSAC.L
No round on accumulator stores

0 1 1 Signed, fractional

Round on MAC.L and MSAC.L
Round-to-32-bits on accumulator stores

1 0 x Unsigned, integer

1 1 0 Signed, fractional

Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores

1 1 1 Signed, fractional

Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores

4.2.2 Mask Register (MASK)

The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved
with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source
operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones.

This register performs a simple AND with the operand address for MAC instructions. The processor
calculates the normal operand address and, if enabled, that address is then ANDed with {0xFFFF,
MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address
can be constrained to a certain memory region. This is used primarily to implement circular queues with
the (An)+ addressing mode.

This minimizes the addressing support required for filtering, convolution, or any routine that implements
a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be
included in all memory effective address calculations. The syntax is as follows:

mac.sz Ry,RxSF,<ea>y&,Rw

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Enhanced Multiply-Accumulate Unit (EMAC)

The & operator enables the MASK use and causes bit 5 of the extension word to be set. The exact
algorithm for the use of MASK is:

if extension word, bit [5] = 1, the MASK bit, then

if <ea> = (An)

oa = An & {0xFFFF, MASK}

if <ea> = (An)+

oa = An
An = (An + 4) & {0xFFFF, MASK}

if <ea> =-(An)

oa = (An - 4) & {0xFFFF, MASK}
An = (An - 4) & {0xFFFF, MASK}

if <ea> = (d16,An)

oa = (An + se_d16) & {0xFFFF0x, MASK}

Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For
auto-addressing modes of post-increment and pre-decrement, the updated An value calculation is also
shown.

Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue
implementations.

BDM: 0x805 (MASK) Access: User read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

R 1 1 1 1 1 111111111 1 1

W

Reset11111111111111111111111111111111

MASK

Figure 4-3. Mask Register (MASK)

Table 4-4. MASK Field Descriptions

Field Description

31–16 Reserved, must be set.

15–0

MASK

Performs a simple AND with the operand address for MAC instructions.

4.2.3 Accumulator Registers (ACC0–3)

The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers
form the entire 48-bit result.

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Enhanced Multiply-Accumulate Unit (EMAC)

BDM: 0x806 (ACC0)

0x809 (ACC1)
0x80A (ACC2)
0x80B (ACC3)

313029282726252423222120191817161514131211109876543210

R

W

Reset––––––––––––––––––––––––––––––––

Accumulator

Access: User read/write

BDM read/write

Figure 4-4. Accumulator Registers (ACC0–3)

Table 4-5. ACC0–3 Field Descriptions

Field Description

31–0

Accumulator

Store 32-bits of the result of the MAC operation.

4.2.4 Accumulator Extension Registers (ACCext01, ACCext23)

Each pair of 8-bit accumulator extension fields are concatenated with the corresponding 32-bit
accumulator register to form the 48-bit accumulator. For more information, see Section 4.3, “Functional

Description.”

BDM: 0x807 (ACCext01) Access: User read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

R

Accumulator 0 Upper

W

Reset––––––––––––––––––––––––––––––––

Extension Byte

Accumulator 0 Lower

Extension Byte

Accumulator 1 Upper

Extension Byte

Accumulator 1 Lower

Extension Byte

Figure 4-5. Accumulator Extension Register (ACCext01)

Table 4-6. ACCext01 Field Descriptions

Field Description

31–24

ACC0U

23–16

ACC0L

15–8

ACC1U

7–0

ACC1L

Accumulator 0 upper extension byte

Accumulator 0 lower extension byte

Accumulator 1 upper extension byte

Accumulator 1 lower extension byte

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BDM: 0x808 (ACCext23) Access: User read/write

313029282726252423222120191817161514131211109876543210

R

Accumulator 2 Upper

W

Reset––––––––––––––––––––––––––––––––

Field Description

Extension Byte

Figure 4-6. Accumulator Extension Register (ACCext23)

Accumulator 2 Lower

Extension Byte

Table 4-7. ACCext23 Field Descriptions

Accumulator 3 Upper

Extension Byte

BDM read/write

Accumulator 3 Lower

Extension Byte

31–24

ACC2U

23–16

ACC2L

15–8

ACC3U

7–0

ACC3L

Accumulator 2 upper extension byte

Accumulator 2 lower extension byte

Accumulator 3 upper extension byte

Accumulator 3 lower extension byte

4.3 Functional Description

The MAC speeds execution of ColdFire integer-multiply instructions (MULS and MULU) and provides
additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC,
execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early
termination that the OEP normally uses if no MAC hardware is present.

The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed
by the addition or subtraction of the product to or from the value in an accumulator. Optionally, the product
may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation
arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions.
Multiply-accumulate operations support 16- or 32-bit input operands these formats:

• Signed integers

• Unsigned integers

• Signed, fixed-point, fractional numbers

The EMAC is optimized for single-cycle, pipelined 32 × 32 multiplications. For word- and
longword-sized integer input operands, the low-order 40 bits of the product are formed and used with the
destination accumulator. For fractional operands, the entire 64-bit product is calculated and truncated or
rounded to the most-significant 40-bit result using the round-to-nearest (even) method before it is
combined with the destination accumulator.

For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for
signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined
with the 48-bit destination accumulator.

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