Freescale Semiconductor MCF52230 ColdFire, MCF52231 ColdFire, MCF52235 ColdFire, MCF52236 ColdFire, MCF52232 ColdFire Reference Manual

...

MCF52235 ColdFire® Integrated

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Microcontroller Reference Manual

Devices Supported:

MCF52230 MCF52231 MCF52232 MCF52233 MCF52234 MCF52235 MCF52236

Document Number:

MCF52235RM

Rev. 6

07/2010

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technology

Document Number: MCF52235RM Rev. 6 07/2010

Chapter 1

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Overview

1.1 MCF52235 Family Configurations ............................................................................................... 1-2

1.2 Block Diagram .............................................................................................................................. 1-3

1.3 Part Numbers and Packaging ........................................................................................................ 1-3

1.4 Features ......................................................................................................................................... 1-4

1.5 Memory Map Overview .............................................................................................................. 1-14

Chapter 2

Signal Descriptions

2.1 Introduction ................................................................................................................................... 2-1

2.2 Overview ....................................................................................................................................... 2-1

2.3 Reset Signals .................................................................................................................................2-9

2.4 PLL and Clock Signals .................................................................................................................. 2-9

2.5 Mode Selection .............................................................................................................................. 2-9

2.6 External Interrupt Signals .............................................................................................................. 2-9

2.7 Queued Serial Peripheral Interface (QSPI) .................................................................................2-10

2.8 Fast Ethernet Controller PHY Signals ........................................................................................2-11

2.9 I2C I/O Signals ............................................................................................................................ 2-11

2.10 UART Module Signals ................................................................................................................ 2-12

2.11 DMA Timer Signals .................................................................................................................... 2-12

2.12 ADC Signals ................................................................................................................................ 2-12

2.13 General Purpose Timer Signals ...................................................................................................2-13

2.14 Pulse Width Modulator Signals ................................................................................................... 2-13

2.15 Debug Support Signals ................................................................................................................ 2-13

2.16 EzPort Signal Descriptions .......................................................................................................... 2-14

2.17 Power and Ground Pins ............................................................................................................... 2-15

3.1 Introduction ................................................................................................................................... 3-1

3.2 Memory Map/Register Description ............................................................................................... 3-2

3.3 Functional Description .................................................................................................................. 3-8

4.1 Introduction ................................................................................................................................... 4-1

4.2 Memory Map/Register Definition ................................................................................................. 4-3

4.3 Functional Description .................................................................................................................. 4-8

Freescale Semiconductor iii

Chapter 3

ColdFire Core

Chapter 4

Enhanced Multiply-Accumulate Unit (EMAC)

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

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Chapter 5

Cryptographic Acceleration Unit (CAU)

5.1 Introduction ................................................................................................................................... 5-1

5.2 Memory Map/Register Definition ................................................................................................. 5-2

5.3 Functional Description .................................................................................................................. 5-4

5.4 Application/Initialization Information ........................................................................................ 5-10

Chapter 6

Random Number Generator (RNG)

6.1 Introduction ................................................................................................................................... 6-1

6.2 Memory Map/Register Definition ................................................................................................. 6-2

6.3 Functional Description .................................................................................................................. 6-5

6.4 Initialization/Application Information .......................................................................................... 6-6

Chapter 7

Clock Module

7.1 Introduction ................................................................................................................................... 7-1

7.2 Features ......................................................................................................................................... 7-1

7.3 Modes of Operation ....................................................................................................................... 7-1

7.4 Low-power Mode Operation ......................................................................................................... 7-2

7.5 Block Diagram .............................................................................................................................. 7-2

7.6 Signal Descriptions ....................................................................................................................... 7-4

7.7 Memory Map and Registers .......................................................................................................... 7-5

7.8 Functional Description ................................................................................................................ 7-11

Chapter 8

Real-Time Clock

8.1 Introduction ................................................................................................................................... 8-1

8.2 Memory Map/Register Definition ................................................................................................. 8-2

8.3 Functional Description ................................................................................................................ 8-11

8.4 Initialization/Application Information ........................................................................................ 8-12

Chapter 9

Power Management

9.1 Introduction ................................................................................................................................... 9-1

9.2 Memory Map/Register Definition ................................................................................................. 9-1

9.3 IPS Bus Timeout Monitor ............................................................................................................. 9-9

9.4 Functional Description ................................................................................................................ 9-11

Chapter 10

Reset Controller Module

10.1 Introduction ................................................................................................................................. 10-1

10.2 Features ....................................................................................................................................... 10-1

10.3 Block Diagram ............................................................................................................................ 10-1

10.4 Signals ......................................................................................................................................... 10-2

iv Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

10.5 Memory Map and Registers ........................................................................................................ 10-2

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10.6 Functional Description ................................................................................................................ 10-5

Chapter 11

Static RAM (SRAM)

11.1 Introduction ................................................................................................................................. 11-1

11.2 Memory Map/Register Description ............................................................................................. 11-1

11.3 Initialization/Application Information ........................................................................................ 11-3

Chapter 12

Chip Configuration Module (CCM)

12.1 Introduction ................................................................................................................................. 12-1

12.2 External Signal Descriptions ....................................................................................................... 12-2

12.3 Memory Map/Register Definition ............................................................................................... 12-2

12.4 Functional Description ................................................................................................................ 12-5

12.5 Reset ............................................................................................................................................ 12-6

Chapter 13

System Control Module (SCM)

13.1 Introduction ................................................................................................................................. 13-1

13.2 Overview ..................................................................................................................................... 13-1

13.3 Features ....................................................................................................................................... 13-1

13.4 Memory Map and Register Definition ........................................................................................ 13-2

13.5 Register Descriptions .................................................................................................................. 13-3

13.6 Internal Bus Arbitration .............................................................................................................. 13-9

13.7 System Access Control Unit (SACU) ....................................................................................... 13-12

Chapter 14

General Purpose I/O Module

14.1 Introduction ................................................................................................................................. 14-1

14.2 Overview ..................................................................................................................................... 14-2

14.3 Features ....................................................................................................................................... 14-3

14.4 Signal Descriptions ..................................................................................................................... 14-3

14.5 Memory Map/Register Definition ............................................................................................... 14-3

14.6 Register Descriptions .................................................................................................................. 14-5

14.7 Ports Interrupts .......................................................................................................................... 14-15

Chapter 15

Interrupt Controller Module

15.1 68K/ColdFire Interrupt Architecture Overview .......................................................................... 15-1

15.2 Memory Map ............................................................................................................................... 15-4

15.3 Register Descriptions .................................................................................................................. 15-5

15.4 Low-Power Wakeup Operation ................................................................................................. 15-17

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor v

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Chapter 16

Edge Port Modules (EPORTn)

16.1 Introduction ................................................................................................................................. 16-1

16.2 Low-Power Mode Operation ....................................................................................................... 16-2

16.3 Signal Descriptions ..................................................................................................................... 16-2

16.4 Memory Map/Register Definition ............................................................................................... 16-3

Chapter 17

ColdFire Flash Module (CFM)

17.1 Introduction ................................................................................................................................. 17-1

17.2 External Signal Description ........................................................................................................ 17-3

17.3 Memory Map and Register Definition ........................................................................................ 17-3

17.4 Functional Description .............................................................................................................. 17-16

Chapter 18

Fast Ethernet Controller (FEC)

18.1 Overview ..................................................................................................................................... 18-1

18.2 Modes of Operation ..................................................................................................................... 18-1

18.3 FEC Top-Level Functional Diagram ........................................................................................... 18-2

18.4 Functional Description ................................................................................................................ 18-4

18.5 Programming Model ................................................................................................................. 18-18

18.6 Buffer Descriptors ..................................................................................................................... 18-47

Chapter 19

Ethernet Physical Transceiver (EPHY)

19.1 Introduction ................................................................................................................................. 19-1

19.2 External Signal Descriptions ....................................................................................................... 19-3

19.3 Memory Map and Register Descriptions .................................................................................... 19-5

19.4 Functional Description .............................................................................................................. 19-22

Chapter 20

DMA Controller Module

20.1 Introduction ................................................................................................................................. 20-1

20.2 DMA Transfer Overview ............................................................................................................20-3

20.3 Memory Map/Register Definition ............................................................................................... 20-3

20.4 Functional Description .............................................................................................................. 20-11

Chapter 21

EzPort

21.1 Features ....................................................................................................................................... 21-1

21.2 Modes of Operation ..................................................................................................................... 21-1

21.3 External Signal Description ........................................................................................................ 21-2

21.4 Command Definition ................................................................................................................... 21-3

21.5 Functional Description ................................................................................................................ 21-7

21.6 Initialization/Application Information ........................................................................................21-8

vi Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Chapter 22

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Programmable Interrupt Timers (PIT0–PIT1)

22.1 Introduction ................................................................................................................................. 22-1

22.2 Memory Map/Register Definition ............................................................................................... 22-2

22.3 Functional Description ................................................................................................................ 22-5

Chapter 23

General Purpose Timer Module (GPT)

23.1 Introduction ................................................................................................................................. 23-1

23.2 Features ....................................................................................................................................... 23-1

23.3 Block Diagram ............................................................................................................................ 23-2

23.4 Low-Power Mode Operation ....................................................................................................... 23-3

23.5 Signal Description ....................................................................................................................... 23-3

23.6 Memory Map and Registers ........................................................................................................ 23-3

23.7 Functional Description .............................................................................................................. 23-17

23.8 Reset .......................................................................................................................................... 23-21

23.9 Interrupts ................................................................................................................................... 23-21

Chapter 24

DMA Timers (DTIM0–DTIM3)

24.1 Introduction ................................................................................................................................. 24-1

24.2 Memory Map/Register Definition ............................................................................................... 24-3

24.3 Functional Description ................................................................................................................ 24-8

24.4 Initialization/Application Information ........................................................................................24-9

Chapter 25

Queued Serial Peripheral Interface (QSPI)

25.1 Introduction ................................................................................................................................. 25-1

25.2 External Signal Description ........................................................................................................ 25-2

25.3 Memory Map/Register Definition ............................................................................................... 25-3

25.4 Functional Description ................................................................................................................ 25-9

25.5 Initialization/Application Information ......................................................................................25-15

Chapter 26

UART Modules

26.1 Introduction ................................................................................................................................. 26-1

26.2 External Signal Description ........................................................................................................ 26-3

26.3 Memory Map/Register Definition ............................................................................................... 26-3

26.4 Functional Description .............................................................................................................. 26-16

26.5 Initialization/Application Information ......................................................................................26-26

Chapter 27

C Interface

27.1 Introduction ................................................................................................................................. 27-1

27.2 Memory Map/Register Definition ............................................................................................... 27-3

Freescale Semiconductor vii

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

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27.3 Functional Description ................................................................................................................ 27-7

27.4 Initialization/Application Information ......................................................................................27-12

Chapter 28

Analog-to-Digital Converter (ADC)

28.1 Introduction ................................................................................................................................. 28-1

28.2 Features ....................................................................................................................................... 28-1

28.3 Block Diagram ............................................................................................................................ 28-2

28.4 Memory Map and Register Definition ........................................................................................ 28-2

28.5 Functional Description .............................................................................................................. 28-21

Chapter 29

Pulse-Width Modulation (PWM) Module

29.1 Introduction ................................................................................................................................. 29-1

29.2 Memory Map/Register Definition ............................................................................................... 29-2

29.3 Functional Description .............................................................................................................. 29-13

Chapter 30

FlexCAN

30.1 Introduction ................................................................................................................................. 30-1

30.2 External Signal Description ........................................................................................................ 30-5

30.3 Memory Map/Register Definition ............................................................................................... 30-5

30.4 Initialization/Application Information ......................................................................................30-28

Chapter 31

Debug Module

31.1 Introduction ................................................................................................................................. 31-1

31.2 Signal Descriptions ..................................................................................................................... 31-2

31.3 Memory Map/Register Definition ............................................................................................... 31-3

31.4 Functional Description .............................................................................................................. 31-17

Chapter 32

IEEE 1149.1 Test Access Port (JTAG)

32.1 Introduction ................................................................................................................................. 32-1

32.2 External Signal Description ........................................................................................................ 32-2

32.3 Memory Map/Register Definition ............................................................................................... 32-4

32.4 Functional Description ................................................................................................................ 32-6

32.5 Initialization/Application Information ......................................................................................32-10

Appendix A

Appendix B

Revision History

viii Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor ix

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MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Chapter 1

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

Overview

This chapter provides an overview of the major features and functional components of the MCF52235 family of microcontrollers. The MCF52235 family is a highly integrated implementation of the ColdFire® family of reduced instruction set computing (RISC) microcontrollers that also includes the MCF52230, MCF52231, MCF52232, MC52233, MC52234, and MCF52236. The differences between these parts are summarized in Table 1-1. This document is written from the perspective of the MCF52235.

The MCF52235 represents a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire microarchitecture. Featuring up to 32 Kbytes of internal SRAM and 256 Kbytes of flash memory, four 32-bit timers with DMA request capability, a 4-channel DMA controller, fast Ethernet controller, a CAN module, an I2C™ module, 3 UARTs and a queued SPI, the MC52235 family has been designed for general-purpose industrial control applications.

This 32-bit device is based on the Version 2 (V2) ColdFire reduced instruction set computing (RISC) core with an enhanced multiply-accumulate unit (EMAC) and divider providing 56 Dhrystone 2.1 MIPS at a frequency of up to 60 MHz from internal flash. On-chip modules include the following:

• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC)

• Cryptographic Acceleration Unit (CAU)

• Up to 32 Kbytes of internal SRAM

• Up to 256 Kbytes of on-chip flash memory

• Fast Ethernet Controller (FEC) with on-chip transceiver (ePHY)

• Three universal asynchronous receiver/transmitters (UARTs)

• Controller area network 2.0B (FlexCAN) module

• Inter-integrated circuit (I

C) bus controller

• 10- or 12-bit analog-to-digital converter (ADC)

• Queued serial peripheral interface (QSPI) module

• Four-channel, 32-bit direct memory access (DMA) controller

• Four-channel, 32-bit input capture/output compare timers with optional DMA support

• Two 16-bit periodic interrupt timers (PITs)

• Programmable software watchdog timer

• Two interrupt controllers, each capable of handling up to 63 interrupt sources (126 total)

These devices are ideal for cost-sensitive applications requiring significant control processing for connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets such as security , imaging, networking, gaming, and medical. This leading package of integration and high performance allows fast time to market through easy code reuse and extensive third party tool support.

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor 1-1

Overview

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

To locate any published errata or updates for this document, refer to the ColdFire products website at

http://www.freescale.com/coldfire.

1.1 MCF52235 Family Configurations

Table 1-1. MCF52235 Family Configurations

Module 52230 52231 52232 52233 52234 52235 52236

Version 2 ColdFire Core with EMAC (Enhanced Multiply-Accumulate Unit)

System Clock (MHz) 60 60 50 60 60 60 50 Performance (Dhrystone 2.1 MIPS) 56 56 46 56 56 56 46 Flash / Static RAM (SRAM) 128/32

Interrupt Controllers (INTC0/INTC1) ••••••• Fast Analog-to-Digital Converter (ADC) ••••••• Random Number Generator and Crypto

Acceleration Unit (CAU) FlexCAN 2.0B Module — • —— ••— Fast Ethernet Controller (FEC) with on-chip

interface (EPHY) Four-channel Direct-Memory Access (DMA) ••••••• Software Watchdog Timer (WDT) ••••••• Programmable Interrupt Timer 2222222 Four-Channel General Purpose Timer ••••••• 32-bit DMA Timers 4444444 QSPI •••••••

•••••••

128/32

Kbytes

————— • —

•••••••

Kbytes

128/32 Kbytes

256/32 Kbytes

UART(s) 3333333

C •••••••

I Eight/Four-channel 8/16-bit PWM Timer ••••••• General Purpose I/O Module (GPIO) ••••••• Chip Configuration and Reset Controller

Module Background Debug Mode (BDM) ••••••• JTAG - IEEE 1149.1 Test Access Port Package 80 LQFP

The full debug/trace interface is availab le only on the 112- and 121-pin packages. A reduced debug interface is bonded on the 80-pin package.

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

1-2 Freescale Semiconductor

•••••••

112 LQFP

80 LQFP

112 LQFP

80 LQFP 80 LQFP

112 LQFP

121

MAPBGA

112 LQFP

121

MAPBGA

80 LQFP

Overview

Arbiter

Interrupt

Controller 1

UART

QSPI

UART

I2C

DTIM0DTIM1DTIM2DTIM

V2 ColdFire CPU

IFP

OEP

EMAC

4 CH DMA

MUX

JTAG

TAP

To/From PADI

32 Kbytes

SRAM

(4K×16)×4

256 Kbytes

Flash

(32K×16)×4

PORTS

(GPIO)

CIM

RSTIN RSTOUT

SDA SCL UTXDn URXDn U

RTSn

DTINn/DTOUTn CANRX

JTAG_EN

ADCAN[7:0]

RHVRL

PLL

CLKGEN

Edge

Port 2

FlexCAN

EXTAL XTAL CLKOUT

RNGA

PIT1

GPT

PWM

To/From Interrupt Controller

CANTX

CTSn

PMM

PADI – Pin Muxing

EzPort

EzPCS

QSPI_CLK, QSPI_CSn

PWMn

QSPI_DIN, QSPI_DOUT

GPTn

Fast Ethernet

Controller

(FEC)

EPHY

EPHY_RX

EPHY_TX

PIT0

Edge

Port 1

Interrupt

Controller 2

EzPQ

EzPD EzPCK

RTC

CAU

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1.2 Block Diagram

The superset device in the MCF52235 family comes in a 112-leaded quad flat package (LQFP) and a 121 pin MAPBGA. Figure 1-1 shows a top-level block diagram of the MCF52235.

1.3 Part Numbers and Packaging

Table 1-2 summarizes the features of the MCF52235 product family. Several speed/package options are

available to match cost- or performance-sensitive applications.

Freescale Semiconductor 1-3

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Figure 1-1. MCF52235 Block Diagram

Overview

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Table 1-2. Orderable Part Number Summary

Freescale Part

Number

MCF52230CAF60 MCF52230 Microcontroller 60 128 / 32 80 LQFP -40 to +85 MCF52230CAL60 MCF52230 Microcontroller 60 128 / 32 112 LQFP -40 to +85 MCF52231CAF60 MCF52231 Microcontroller, FlexCAN 60 128 / 32 80 LQFP -40 to +85 MCF52231CAL60 MCF52231 Microcontroller, FlexCAN 60 128 / 32 112 LQFP -40 to +85 MCF52232CAF50 MCF52232 Microcontroller 50 128 / 32 80 LQFP -40 to +85

MCF52232AF50 MCF52232 Microcontroller 50 128 / 32 80 LQFP 0 to +70 MCF52233CAF60 MCF52233 Microcontroller 60 256 / 32 80 LQFP -40 to +85 MCF52233CAL60 MCF52233 Microcontroller 60 256 / 32 112 LQFP -40 to +85

MCF52233CAL60A MCF52233 Microcontroller 60 256 / 32 112 LQFP -40 to +85

MCF52233CVM60 MCF52233 Microcontroller 60 256 / 32 121 MAPBGA -40 to +85

MCF52234CAL60 MCF52234 Microcontroller, FlexCAN 60 256 / 32 112 LQFP -40 to +85

MCF52234CVM60 MCF52234 Microcontroller, FlexCAN 60 256 / 32 121 MAPBGA -40 to +85

MCF52235CAL60 MCF52235 Microcontroller, FlexCAN, CA U, RNGA 60 256 / 32 112 LQFP -40 to +85

MCF52235CAL60A MCF52235 Microcontroller, FlexCAN, CA U , RNGA 60 256 / 32 112 LQFP -40 to +85

MCF52235CVM60 MCF52235 Microcontroller, FlexCAN, CAU, RNGA 60 256 / 32 121 MAPBGA -40 to +85

MCF52236CAF50 MCF52236 Microcontroller 50 256 / 32 80 LQFP -40 to +85

Description

Speed

(MHz)

Flash/SRAM

(Kbytes)

Package

Temp range

(°C)

MCF52236AF50 MCF52236 Microcontroller 50 256 / 32 80 LQFP 0 to +70 MCF52236AF50A MCF52236 Microcontroller 50 256 / 32 80 LQFP 0 to +70

1.4 Features

The MCF52235 family includes the following features:

• Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data paths on-chip — Up to 60 MHz processor core frequency — Sixteen general-purpose, 32-bit data and address registers — Implements ColdFire ISA_A with extensions to support the user stack pointer register and four

new instructions for improved bit processing (ISA_A+)

— Enhanced Multiply-Accumulate (EMAC) unit with 32-bit accumulator to support

16 × 16 → 32 or 32 × 32 → 32 operations

— Cryptography Acceleration Unit (CAU)

– Tightly-coupled coprocessor to accelerate software-based encryption and message digest

functions

– FIPS-140 compliant random number generator

1-4 Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

— Support for DES, 3DES, AES, MD5, and SHA-1 algorithms

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— Illegal instruction decode that allows for 68K emulation support

• System debug support — Real time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging (DEBUG_B+) — Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can

be configured into a 1- or 2-level trigger

• On-chip memories — Up to 32 Kbytes of dual-ported SRAM on CPU internal bus, supporting core and DMA access

with standby power supply support

— Up to 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses

• Power management — Fully static operation with processor sleep and whole chip stop modes — Rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used

• Fast Ethernet Controller (FEC)

Overview

— 10/100 BaseT/TX capability, half duplex or full duplex — On-chip transmit and receive FIFOs — Built-in dedicated DMA controller — Memory-based flexible descriptor rings

• On-chip Ethernet Transceiver (EPHY) — Digital adaptive equalization — Supports auto-negotiation — Baseline wander correction — Full-/Half-duplex support in all modes — Loopback modes — Supports MDIO preamble suppression — Jumbo packet

• FlexCAN 2.0B module — Based on and includes all existing features of the Freescale TouCAN module — Full implementation of the CAN protocol specification version 2.0B

– Standard Data and Remote Frames (up to 109 bits long) – Extended Data and Remote Frames (up to 127 bits long) – 0–8 bytes data length

Freescale Semiconductor 1-5

– Programmable bit rate up to 1 Mbit/sec

— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length

each, configurable as Rx or Tx, all supporting standard and extended messages

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— Unused Message Buffer space can be used as general purpose RAM space — Listen only mode capability — Content-related addressing — No read/write semaphores required — Three programmable mask registers: global for MBs 0-13, special for MB14, and special for

MB15 — Programmable transmit-first scheme: lowest ID or lowest buffer number — Time stamp based on 16-bit free-running timer — Global network time, synchronized by a specific message — Maskable interrupts

• Three universal asynchronous/synchronous receiver transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic with maskable interrupts — DMA support — Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity — Up to 2 stop bits in 1/16 increments — Error-detection capabilities — Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs — Transmit and receive FIFO buffers

•I2C module — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I2C bus — Master and slave modes support multiple masters — Automatic interrupt generation with programmable level

• Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to four chip selects available — Master mode operation only — Programmable bit rates up to half the CPU clock frequency — Up to 16 pre-programmed transfers

• Fast analog-to-digital converter (ADC) — Eight analog input channels — 12-bit resolution — Minimum 1.125 μs conversion time

1-6 Freescale Semiconductor

— Simultaneous sampling of two channels for motor control applications — Single-scan or continuous operation — Optional interrupts on conversion complete, zero crossing (sign change), or under/over

low/high limit

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

— Unused analog channels can be used as digital I/O

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• Four 32-bit DMA timers — 17-ns resolution at 60 MHz — Programmable sources for clock input, including an external clock option — Programmable prescaler — Input capture capability with programmable trigger edge on input pin — Output compare with programmable mode for the output pin — Free run and restart modes — Maskable interrupts on input capture or output compare — DMA trigger capability on input capture or output compare

• Four-channel general purpose timers — 16-bit architecture — Programmable prescaler — Output pulse widths variable from microseconds to seconds — Single 16-bit input pulse accumulator — Toggle-on-overflow feature for pulse-width modulator (PWM) generation

Overview

— One dual-mode pulse accumulation channel

• Pulse-width modulation timer — Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution — Programmable period and duty cycle — Programmable enable/disable for each channel — Software selectable polarity for each channel — Period and duty cycle are double buffered. Change takes effect when the end of the current

period is reached (PWM counter reaches zero) or when the channel is disabled. — Programmable center or left aligned outputs on individual channels — Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies — Emergency shutdown

• Real-Time Clock (RTC) — Maintains system time-of-day clock — Provides stopwatch and alarm interrupt functions

• Two periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down

• Software watchdog timer

Freescale Semiconductor 1-7

— 32-bit counter — Low power mode support

• Clock Generation Features

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— Up to 48 MHz crystal input — On-chip PLL can generate core frequencies up to maximum 60 MHz operating frequency — Provides clock for integrated EPHY

• Dual Interrupt Controllers (INTC0/INTC1) — Support for multiple interrupt sources organized as follows:

– Fully-programmable interrupt sources for each peripheral – 7 fixed-level interrupt sources

– Seven external interrupt signals — Unique vector number for each interrupt source — Ability to mask any individual interrupt source or all interrupt sources (global mask-all) — Support for hardware and software interrupt acknowledge (IACK) cycles — Combinatorial path to provide wake-up from low power modes

• DMA controller — Four fully programmable channels — Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for

16-byte (4 x 32-bit) burst transfers — Source/destination address pointers that can increment or remain constant — 24-bit byte transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle steal support — Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)

•Reset — Separate reset in and reset out signals — Seven sources of reset:

– Power-on reset (POR) – External – Software – Watchdog – Loss of clock – Loss of lock – Low-voltage detection (LVD)

— Status flag indication of source of last reset

• Chip integration module (CIM) — System configuration during reset — Selects one of three clock modes — Configures output pad drive strength — Unique part identification number and part revision number

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• General purpose I/O interface — Up to 56 bits of general purpose I/O — Bit manipulation supported via set/clear functions — Programmable drive strengths — Unused peripheral pins may be used as extra GPIO

• JTAG support for system level board testing

1.4.1 V2 Core Overview

The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer . The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the MCF52235 core includes the enhanced multiply-accumulate (EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic pipeline, optimized for 16×16 bit operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.

1.4.2 Integrated Debug Module

The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, access debug information and real-time tracing capability is provided on 112-and 121-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators.

The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. The MCF52235 implements revision B+ of the ColdFire Debug Architecture.

The MCF52235’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging.

To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand

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Freescale Semiconductor 1-9

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data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52235 includes a new debug signal, ALLPST. This signal is the logical AND of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).

The full debug/trace interface is available only on the 112 and 121-pin packages. However, every product features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.

1.4.3 JTAG

The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic.

The MCF52235 implementation can do the following:

• Perform boundary-scan operations to test circuit board electrical continuity

• Sample MCF52235 system pins during operation and transparently shift out the result in the boundary scan register

• Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan register to a single bit

• Disable the output drive to pins during circuit-board testing

• Drive output pins to stable levels

1.4.4 On-Chip Memories

1.4.4.1 SRAM

The dual-ported SRAM module provides a general-purpose 16- or 32-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 16- or 32-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module.

The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance.

1.4.4.2 Flash

The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local bus. The CFM is constructed with four banks of 32 K×16-bit flash arrays to generate 256 Kbytes of 32-bit flash memory. These arrays serve as electrically erasable and programmable, non-volatile program and data memory. The flash memory is ideal for program and data

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storage for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller which supports interleaved accesses from the 2-cycle flash arrays. A backdoor mapping of the flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort, which is a serial flash programming interface that allows the flash to be read, erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips. This allows easy device programming via Automated Test Equipment or bulk programming tools.

1.4.5 Cryptography Acceleration Unit

The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the CAU is a coprocessor tightly-coupled to the V2 ColdFire core that implements a set of specialized operations to increase the throughput of software-based encryption and message digest functions, specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms. Second, a random number generator provides FIPS-140 compliant 32-bit values to security processing routines. Both modules supply critical acceleration to software-based cryptographic algorithms at a minimal hardware cost.

1.4.6 Power Management

The MCF52235 incorporates several low-power modes of operation which are entered under program control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the LVD trip point.

1.4.7 FlexCAN

The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers.

1.4.8 UARTs

The MCF52235 has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions.

1.4.9 I2C Bus

The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices on a circuit board.

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1.4.10 QSPI

The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability . It allows up to 16 transfers to be queued at once, mi nimizing the need for CPU intervention between transfers.

1.4.11 Fast ADC

The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding separate 10- or 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.

The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform a programmed scan sequence repeatedly until manually stopped.

The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.

During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.

Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.

1.4.12 DMA Timers (DTIM0–DTIM3)

There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the each device. Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers.

1.4.13 General Purpose Timer (GPT)

The general purpose timer (GP T) is a 4-channel timer module consisting of a 16-bit programmable counter driven by a 7-stage programmable prescaler . Each of the four channels can be configured for input capture or output compare. Additionally , one of the channels, channel 3, can be configured as a pulse accumulator.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.

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1.4.14 Periodic Interrupt Timers (PIT0 and PIT1)

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. Each timer can count down from the value written in its PIT modulus register or can be a free-running down-counter.

1.4.15 Pulse Width Modulation (PWM) Timers

The MCF52235 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated counter . Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0 to 100%. The PWM outputs have programmable polarity and can be programmed as left-aligned outputs or center-aligned outputs. For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.

1.4.16 Software Watchdog Timer

The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.

1.4.17 Phase Locked Loop (PLL)

The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS.

1.4.18 Interrupt Controller (INTC0/INTC1)

There are two interrupt controllers on the MCF52235. These interrupt controllers are organized as seven levels with up to nine interrupt sources per level. Each interrupt source has a unique interrupt vector, and provide each peripheral with all necessary interrupts. Each internal interrupt has a programmable level [1-7] and priority within the level. The seven external interrupts have fixed levels/priorities.

1.4.19 DMA Controller

The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.

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1.4.20 Reset

The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last reset. There are seven sources of reset:

• External reset input

• Power-on reset (POR)

• Watchdog timer

• Phase locked-loop (PLL) loss of lock

• PLL loss of clock

• Software

• Low-voltage detector (LVD)

Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO pin.

1.4.21 GPIO

Nearly all pins on the MCF52235 have general purpose I/O capability in addition to their primary functions and are grouped into 8-bit ports. Some ports do not utilize all 8 bits. Each port has registers that configure, monitor, and control the port pins.

1.4.22

1.5 Memory Map Overview

Table 1-3. System Memory Map

Base Address (Hex) Size Use

0x0000_0000 1G On-Chip Flash/RAM Array2 0x4000_0000 64 bytes System Control Module 0x4000_0040 64 bytes Reserved 0x4000_0080 128 bytes Reserved 0x4000_0100 16 bytes DMA (Channel 0) 0x4000_0110 16 bytes DMA (Channel 1) 0x4000_0120 16 bytes DMA (Channel 2) 0x4000_0130 16 bytes DMA (Channel 3) 0x4000_0140 196 bytes Reserved 0x4000_0200 64 bytes UART0 0x4000_0240 64 bytes UART1

1-14 Freescale Semiconductor

0x4000_0280 64 bytes UART2

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Table 1-3. System Memory Map (continued)

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Base Address (Hex) Size Use

0x4000_02c0 64 bytes Reserved 0x4000_0300 64 bytes I2C 0x4000_0340 64 bytes QSPI 0x4000_0380 64 bytes Reserved

0x4000_03C0 64 bytes RTC

0x4000_0400 64 bytes TMR0 0x4000_0440 64 bytes TMR1 0x4000_0480 64 bytes TMR2 0x4000_04c0 64 bytes TMR3 0x4000_0500 1792 bytes Reserved 0x4000_0c00 256 bytes Interrupt Cntl 0 0x4000_0d00 256 bytes Interrupt Cntl 1 0x4000_0e00 256 bytes Reserved

Overview

0x4000_0f00 256 bytes Global Interrupt Ack Cycles

0x4000_1000 1K Fast Ethernet Controller - Registers and

MIB RAM 0x4000_1400 1K Fast Ethernet Controller - FIFO Memory 0x4000_1800 1M – 6K Reserved 0x4010_0000 64K Ports 0x4011_0000 64K CIM_IBO 0x4012_0000 64K Clocks (PLLMRBI) 0x4013_0000 64K Edge Port 0 0x4014_0000 64K Edge Port 1 0x4015_0000 64K Programmable Interval Timer 0 0x4016_0000 64K Programmable Interval Timer 1 0x4017_0000 64K Reserved 0x4018_0000 64K Reserved 0x4019_0000 64K ADC 0x401a_0000 64K Timer 0x401b_0000 64K PWM

Freescale Semiconductor 1-15

0x401c_0000 64K FlexCAN2 0x401d_0000 64K CFM (Flash) control registers 0x401e_0000 64K Ethernet Physical Transceiver

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Table 1-3. System Memory Map (continued)

Base Address (Hex) Size Use

0x401f_0000 64K Random Number Generator H/W

Accelerator 0x4020_0000 62M Reserved 0x4400_0000 256K CFM (Flash) memory for IPS reads and

writes 0x4408_0000 1G – 64M – 256K Reserved 0x8000_0000 2G Reserved

1-16 Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Chapter 2

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Signal Descriptions

2.1 Introduction

This chapter describes signals implemented on this device and includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used.

NOTE

The terms ‘assertion’ and ‘negation’ are used to avoid confusion when dealing with a mixture of active-low and active-high signals. The term ‘asserted’ indicates that a signal is active, independent of the voltage level. The term ‘negated’ indicates that a signal is inactive.

Active-low signals, such as SRAS and TA, are indicated with an overbar.

2.2 Overview

Figure 2-1 shows the block diagram of the device with the signal interface.

Freescale Semiconductor 2-1

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Signal Descriptions

Arbiter

Interrupt

Controller 1

UART

QSPI

UART

I2C

DTIM0DTIM1DTIM2DTIM

V2 ColdFire CPU

IFP

OEP

EMAC

4 CH DMA

MUX

JTAG

TAP

To/From PADI

32 Kbytes

SRAM

(4K×16)×4

256 Kbytes

Flash

(32K×16)×4

PORTS

(GPIO)

CIM

RSTIN RSTOUT

SDA SCL UTXDn URXDn U

RTSn

DTINn/DTOUTn CANRX

JTAG_EN

ADCAN[7:0]

RHVRL

PLL

CLKGEN

Edge

Port 2

FlexCAN

EXTAL XTAL CLKOUT

RNGA

PIT1

GPT

PWM

To/From Interrupt Controller

CANTX

UCTSn

PMM

PADI – Pin Muxing

EzPort

EzPCS

QSPI_CLK, QSPI_CSn

PWMn

QSPI_DIN, QSPI_DOUT

GPTn

Fast Ethernet

Controller

(FEC)

EPHY

EPHY_RX

EPHY_TX

PIT0

Edge

Port 1

Interrupt

Controller 2

EzPQ

EzPD EzPCK

RTC

CAU

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Table 2-1 shows the pin functions by primary and alternate purpose, and illustrates which packages contain

each pin.

Figure 2-1. Block Diagram with Signal Interfaces

2-2 Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

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Table 2-1. Pin Functions by Primary and Alternate Purpose

Pin Group

ADC

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Primary

Function

AN7 — — PAN[7] Low — — A10 88 64 AN6 — — PAN[6] Low — — B10 87 63

Secondary

Function

Tertiary

Function

Quaternary

Function

Drive

Strength/

Control

Wired OR

Control

Pull-up/

Pull-down

Pin on 121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

AN5 — — PAN[5] Low — — A11 86 62 AN4 — — PAN[4] Low — — B11 85 61 AN3 — — PAN[3] Low — — C9 89 65 AN2 — — PAN[2] Low — — B9 90 66 AN1 — — PAN[1] Low — — A9 91 67

AN0 — — PAN[0] Low — — C8 92 68 SYNCA CANTX SYNCB CANRX

FEC_MDIO PAS[3] PDSR[39] — — K1 28 20

FEC_MDC PAS[2] PDSR[39] — — J1 27 19 VDDA — — — N/A N/A — A8 93 69 VSSA — — — N/A N/A — A7 96 72

VRH — — — N/A N/A — B8 94 70

VRL — — — N/A N/A — B7 95 71

Clock

Generation

EXTAL — — — N/A N/A — L7 48 36

XTAL — — — N/A N/A — J7 49 37

VDDPLL

— — — N/A N/A — K6 45 33

VSSPLL — — — N/A N/A — K7 47 35

Debug

Data

ALLPST — — — High — — D3 7 7

DDATA[3:0] — — PDD[7:4] High — — E1, F3,F2, F1 12,13,16,17 —

PST[3:0] — — PDD[3:0] High — — D10, D9,

80,79,78,77 —

E10, E9

Signal Descriptions

2-4 Freescale Semiconductor

Table 2-1. Pin Functions by Primary and Alternate Purpose (continued)

Signal Descriptions

Pin Group

Ethernet

LEDs

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Primary

Function

ACTLED — — PLD[0] PDSR[32] PWOR[8] — C11 84 60 COLLED — — PLD[4] PDSR[36] PWOR[12] — J9 58 42

Secondary

Function

Tertiary

Function

Quaternary

Function

Drive

Strength/

Control

Wired OR

Control

Pull-up/

Pull-down

Pin on 121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

DUPLED — — PLD[3] PDSR[35] PWOR[11] — J10 59 43

LNKLED — — PLD[1] PDSR[33] PWOR[9] — C10 83 59

SPDLED — — PLD[2] PDSR[34] PWOR[10] — D11 81 57

RXLED — — PLD[5] PDSR[37] PWOR[13] — H9 52 —

TXLED — — PLD[6] PDSR[38] PWOR[14] — H8 51 —

VDDR — — — — — — D8 82 58

Ethernet

PHY

PHY_RBIAS — — — — — J11 66 46

PHY_RXN — — — — — E11 74 54 PHY_RXP — — — — — F11 73 53 PHY_TXN — — — — — H11 71 51

PHY_TXP — — — — — G11 70 50

PHY_VDDA PHY_VDDRX PHY_VDDTX

——— N/A H106848 ——— N/A F107555 ——— N/A G106949

PHY_VSSA — — — N/A G8 67 47

PHY_VSSRX — — — N/A F9 76 56

PHY_VSSTX — — — N/A G9 72 52

I2C SCL CANTX

SDA CANRX

UTXD2 PAS[0] PDSR[0] — Pull-Up URXD2 PAS[1] PDSR[0] — Pull-Up

A3 111 79 A2 112 80

Freescale Semiconductor 2-5

Table 2-1. Pin Functions by Primary and Alternate Purpose (continued)

Pin Group

Interrupts

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Primary

Function

IRQ15 — — PGP[7] PSDR[47] — Pull-Up IRQ14 — — PGP[6] PSDR[46] — Pull-Up

Secondary

Function

Tertiary

Function

Quaternary

Function

Drive

Strength/

Control

IRQ13 — — PGP[5] PSDR[45] — Pull-Up IRQ12 — — PGP[4] PSDR[44] — Pull-Up

Continued

Interrupts

IRQ11 — — PGP[3] PSDR[43] — Pull-Up

IRQ10 — — PGP[2] PSDR[42] — Pull-Up

IRQ9 — — PGP[1] PSDR[41] — Pull-Up

Wired OR

Control

Pull-up/

Pull-down

Pin on 121

MAPBGA

Pin on 112

LQFP

A4 106 — A5 105 — A6 98 — C7 97 — K9 57 41 L1 29 — E2 11 —

Pin on 80

LQFP

IRQ8 — — PGP[0] PSDR[40] — Pull-Up E3 10 — IRQ7 — — PNQ[7] Low — Pull-Up IRQ6 — FEC_RXER PNQ[6] Low — Pull-Up IRQ5 — FEC_RXD[1] PNQ[5] Low — Pull-Up IRQ4 — — PNQ[4] Low — Pull-Up IRQ3 — FEC_RXD[2] PNQ[3] Low — Pull-Up IRQ2 — FEC_RXD[3] PNQ[2] Low — Pull-Up IRQ1 SYNCA PWM1 PNQ[1] High — Pull-Up

L9 56 40 G3 19 — G2 20 — L5 41 29 L8 53 — K8 54 —

J8 55 39

JTAG/BDM JTAG_EN — — — N/A N/A Pull-Down G4 18 12

TCLK/

CLKOUT — — High — Pull-Up

A1 1 1

PSTCLK

TDI/DSI — — — N/A N/A Pull-Up

C3 4 4

TDO/DSO — — — High N/A — C2 5 5

TMS/BKPT — — — N/A N/A Pull-Up

B1 2 2

TRST/DSCLK — — — N/A N/A Pull-Up C1 6 6

Mode

RCON/EZPCS — — — N/A N/A Pull-Up B2 3 3

Selection

Signal Descriptions

2-6 Freescale Semiconductor

Table 2-1. Pin Functions by Primary and Alternate Purpose (continued)

Signal Descriptions

Pin Group

Primary

Function

Secondary

Function

Tertiary

Function

Quaternary

Function

Drive

Strength/

Control

Wired OR

Control

Pull-up/

Pull-down

Pin on 121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

PWM PWM7 — — PTD[3] PDSR[31] — — C5 104 —

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

PWM5 — — PTD[2] PDSR[30] — — B5 103 — PWM3 — — PTD[1] PDSR[29] — — C6 100 — PWM1 — — PTD[0] PDSR[28] — — B6 99 —

QSPI

QSPI_DIN/

CANRX

URXD1 PQS[1] PDSR[2] PWOR[4] — H4 34 25

EZPD

QSPI_DOUT/

CANTX

UTXD1 PQS[0] PDSR[1] PWOR[5] — J4 35 26

EZPQ

QSPI_CLK/

SCL URTS1 PQS[2] PDSR[3] PWOR[6] Pull-Up

K4 36 27

EZPCK QSPI_CS3 SYNCA SYNCB PQS[6] PDSR[7] — — K5 40 — QSPI_CS2 — FEC_TXCLK PQS[5] PDSR[6] — — J5 39 — QSPI_CS1 — FEC_TXEN PQS[4] PDSR[5] — — H5 38 —

L4 37 28

J6 44 32

Reset

QSPI_CS0 SDA UCTS1 PQS[3] PDSR[4] PWOR[7] Pull-Up

RSTI — — — N/A N/A Pull-Up

RSTO — — — high — — L6 46 34

Test TEST — — — N/A N/A Pull-Down H7 50 38

Timers,

16-bit

Timers,

32-bit

GPT3 FEC_TXD[3] PWM7 PTA[3] PDSR[23] — Pull-Up GPT2 FEC_TXD[2] PWM5 PTA[2] PDSR[22] — Pull-Up GPT1 FEC_TXD[1] PWM3 PTA[1] PDSR[21] — Pull-Up GPT0 FEC_TXER PWM1 PTA[0] PDSR[20] — Pull-Up DTIN3 DTOUT3 PWM6 PTC[3] PDSR[19] — — H1 22 14 DTIN2 DTOUT2 PWM4 PTC[2] PDSR[18] — — G1 21 13

B4 107 75 C4 108 76 D4 109 77 B3 110 78

DTIN1 DTOUT1 PWM2 PTC[1] PDSR[17] — — D1 9 9 DTIN0 DTOUT0 PWM0 PTC[0] PDSR[16] — — D2 8 8

Freescale Semiconductor 2-7

Table 2-1. Pin Functions by Primary and Alternate Purpose (continued)

Pin Group

UART 0

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Primary

Function

UCTS0 CANRX4FEC_RXCLK PUA[3] PDSR[11] — — J2 26 18 URTS0 CANTX

Secondary

Function

Tertiary

Function

Quaternary

Function

FEC_RXDV PUA[2] PDSR[10] — — H2 25 17

Drive

Strength/

Control

Wired OR

Control

Pull-up/

Pull-down

Pin on 121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

URXD0 — FEC_RXD[0] PUA[1] PDSR[9] PWOR[0] — K2 30 21

UTXD0 — FEC_CRS PUA[0] PDSR[8] PWOR[1] — L2 31 22

UART 1

UCTS1 SYNCA URXD2 PUB[3] PDSR[15] — — J3 24 16 URTS1 SYNCB UTXD2 PUB[2] PDSR[14] — — H3 23 15

URXD1 — FEC_TXD[0] PUB[1] PDSR[13] PWOR[2] — K3 32 23

UTXD1 — FEC_COL PUB[0] PDSR[12] PWOR[3] — L3 33 24

UART 2 UCTS2 — — PUC[3] PDSR[27] — — L10 61 —

URTS2 — — PUC[2] PDSR[26] — — K10 60 —

URXD2 — — PUC[1] PDSR[25] — — K11 62 —

UTXD2 — — PUC[0] PDSR[24] — — L11 63 —

FlexCAN SYNCA CANTX

SYNCB CANRX

5,11

VDD

VDD — — — N/A N/A — D7 , E8 65,102 45,74

FEC_MDIO PAS[3] PDSR[39] — — — 28 20

FEC_MDC PAS[2] PDSR[39] — — — 27 19

VDDX VDDX — — — N/A N/A — D5, D6, E6, G5,

G6, G7, H6

VSS VSS — — — N/A N/A — E4, E5, E7,F4,

F5, F6, F7, F8

VSSX VSSX — — — N/A N/A — — 15, 42 11, 30

The PDSR and PSSR registers are described in Chapter 14, “General Purpose I/O Module. All programmable signals default to 2mA drive in normal

(single-chip) mode.

All signals have a pull-up in GPIO mode.

The use of an external PHY limits ADC, interrupt, and QSPI functionality. It also disables the UART0/1 and timer pins.

The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals.

The VDD1, VDD2, VDDPLL, and PHY_VDD pins are for decoupling only and should not have power directly applied to them.

For primary and GPIO functions only.

Only when JTAG mode is enabled.

14, 43 10, 31

64,101 44,73

Signal Descriptions

2-8 Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

For secondary and GPIO functions only.

RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended.

For GPIO function. Primary Function has pull-up control within the GPT module.

This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the Ethernet PHY.

Signal Descriptions

2.3 Reset Signals

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available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

Table 2-2 describes signals that are used to reset the chip or as a reset indication.

Table 2-2. Reset Signals

Signal Name Abbreviation Function I/O

Signal Descriptions

Reset In RSTI

Reset Out RSTO Driven low for 512 CPU clocks after the reset source has deasserted

Primary reset input to the device. Asserting RSTI immediately resets the CPU and peripherals.

and PLL locked.

2.4 PLL and Clock Signals

Table 2-3 describes signals that are used to support the on-chip clock generation circuitry.

Table 2-3. PLL and Clock Signals

Signal Name Abbreviation Function I/O

External Clock In EXTAL Crystal oscillator or external clock input. I

Crystal XTAL Crystal oscillator output. O

Clock Out CLKOUT This output signal reflects the internal system clock. O

2.5 Mode Selection

Table 2-4 describes signals used in mode selection.

Table 2-4. Mode Selection Signals

Signal Name Abbreviation Function I/O

Reset Configuration RCON

Test TEST Reserved for factory testing only and in normal modes of operation

The serial flash programming mode is entered by asserting the RCON pin (with the TEST pin negated) as the chip comes out of reset. During this mode, the EzPort has access to the flash memory which can be programmed from an external device.

I should be connected to VSS to prevent unintentional activation of test functions.

2.6 External Interrupt Signals

Table 2-5 describes the external interrupt signals.

Table 2-5. External Interrupt Signals

Signal Name Abbreviation Function I/O

External Interrupts IRQ

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor 2-9

[15:1] External interrupt sources. I

Signal Descriptions

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2.7 Queued Serial Peripheral Interface (QSPI)

Table 2-6 describes the QSPI signals.

Table 2-6. Queued Serial Peripheral Interface (QSPI) Signals

Signal Name Abbreviation Function I/O

QSPI Synchronous

Serial Output

QSPI Synchronous

Serial Data Input

QSPI Serial Clock QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of

Synchronous Peripheral

Chip Selects

QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be

driven on the rising or falling edge of QSPI_CLK.

QSPI_DIN Provides the serial data to the QSPI and can be programmed to be

sampled on the rising or falling edge of QSPI_CLK.

QSPI_CLK are programmable.

QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active

high or low.

2-10 Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

2.8 Fast Ethernet Controller PHY Signals

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available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

Table 7 describes the Fast Ethernet Controller (FEC) Signals.

Ta ble 7. Fast Ethernet Controller (FEC) Signals

Signal Name Abbreviation Function I/O

Signal Descriptions

Twisted Pair Input + RXP Differential Ethernet twisted-pair input pin. This pin is high-impedance

out of reset.

Twisted Pair Input - RXN Differential Ethernet twisted-pair input pin. This pin is high-impedance

out of reset.

Twisted Pair Output + TXN Differential Ethernet twisted-pair output pin. This pin is

high-impedance out of reset.

Twisted Pair Output - TXP Differential Ethernet twisted-pair output pin. This pin is

high-impedance out of reset.

Bias Control Resistor RBIAS Connect a 12.4 kΩ (1.0%) external resistor, RBIAS, between the

PHY_RBIAS pin and analog ground. Place this resistor as near to the chip pin as possible. Stray capacitance must be kept to less than 10 pF (>50 pF causes instability). No high-speed signals can be permitted in the region of RBIAS.

Activity LED ACT_LED Indicates when the EPHY is transmitting or receiving O

Link LED LINK_LED Ind icates when the EPHY has a valid link O

Speed LED SPD_LED Indicates the speed of the EPHY connection O

Duplex LED DUPLED Indicates the duplex (full or half) of the EPHY connection O Collision LED COLLED Indicates if the EPHY detects a collision O Transmit LED TXLED Indicates if the EPHY is transmitting O

Receive LED RXLED Indicates if the EPHY is receiving O

2.9 I2C I/O Signals

Table 2-8 describes the I2C serial interface module signals.

Table 2-8. I2C I/O Signals

Signal Name Abbreviation Function I/O

Serial Clock SCL Open-drain clock signal for the for the I2C interface. It is driven by the

Serial Data SDA Open-drain signal that serves as the data input/output for the I2C

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor 2-11

C module when the bus is in master mode or it becomes the clock

input when the I

interface.

C is in slave mode.

I/O

Signal Descriptions

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2.10 UART Module Signals

Table 2-9 describes the UART module signals.

Table 2-9. UART Module Signals

Signal Name Abbreviation Function I/O

Transmit Serial Data Output UTXDn Transmitter serial data outputs for the UART module s. The output is

held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, LSB first, on this pin at the falling edge of the serial clock source.

Receive Serial Data Input URXDn Receiver serial data inputs for the UART modules. Data is received on

this pin LSB first. When the UART clock is stopped for power-down mode, any transition on this pin restarts it.

Clear-to-Send UCTS

Request-to-Send URTSn Automatic request-to-send outputs from the UART modules. This

n Indicate to the UART modules that they can begin data transmission. I

signal can also be configured to be asserted and negated as a function of the RxFIFO level.

2.11 DMA Timer Signals

Table 2-10 describes the signals of the four DMA timer modules.

Table 2-10. DMA Timer Signals

Signal Name Abbreviation Function I/O

DMA Timer Input DTINn Event input to the DMA timer modules. I

DMA Timer Output DTOUTn Programmable output from the DMA timer modules. O

2.12 ADC Signals

Table 2-11 describes the signals of the analog-to-digital converter.

Table 2-11. ADC Signals

Signal Name Abbreviation Function I/O

Analog Inputs AN[7:0] Inputs to the A-to-D converter. I Analog Reference V

Analog Supply V

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

2-12 Freescale Semiconductor

DDA SSA

RH RL

Reference voltage high and low inputs. I

Isolate the ADC circuitry from power supply noise —

—

Signal Descriptions

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2.13 General Purpose Timer Signals

Table 2-12 describes the general purpose timer signals.

Table 2-12. GPT Signals

Signal Name Abbreviation Function I/O

General Purpose Timer Input/Output

GPT[3:0] Inputs to or outputs from the general purpose timer module I/O

2.14 Pulse Width Modulator Signals

Table 2-13 describes the PWM signals.

Table 2-13. PWM Signals

Signal Name Abbreviation Function I/O

PWM Output Channels PWM[7:0] Pulse width modulated output for PWM channels O

2.15 Debug Support Signals

The signals in Table 2-14 are used as the interface to the on-chip JTAG controller and also to interface to the BDM logic.

Table 2-14. Debug Support Signals

Signal Name Abbreviation Function I/O

JTAG Enable JTAG_EN Select between debug module and JTAG signals at reset I

Test Reset TRST This active-low signal is used to initialize the JTAG logic

asynchronously.

Test Clock TCLK Used to synchronize the JTAG logic. I

Test Mode Select TMS Used to sequence the JTAG state machine. TMS is sampled on the

rising edge of TCLK.

T est Data Input TDI Serial input for test instructions and data. TDI is sampled on the rising

edge of TCLK.

T est Data Output TDO Serial output for test instructions and data. TDO is three-stateable and

is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK.

Development Serial

Clock

Breakpoint BKPT

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor 2-13

DSCLK Development Serial Clock. Internally synchronized input. (The logic

level on DSCLK is validated if it has the same value on two consecutive rising bus clock edges.) Clocks the serial communication port to the debug module during packet transfers. Maxim um frequency is PSTCLK/5. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.

Breakpoint. Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status signals (PST[3:0]) as the value 0xF.

Signal Descriptions

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Signal Name Abbreviation Function I/O

Table 2-14. Debug Support Signals (continued)

Development Serial

Input

Development Serial

Output

Debug Data DDATA[3:0] Debug data. Displays captured processor data and breakpoint status.

Processor Status Clock PSTCLK Processor Status Clock. Delayed v ersion of the processor clock. Its

Processor Status

Outputs

DSI Development Serial Input. Internally synchronized input that provides

data input for the serial communication port to the debug module after the DSCLK has been seen as high (logic 1).

DSO Development Serial Output. Provides serial output communication for

debug module responses. DSO is registered internally. The output is delayed from the validation of DSCLK high.

The CLKOUT signal can be used b y the de velopment system to know when to sample DDATA[3:0].

rising edge appears in the center of valid PST and DDATA output. PSTCLK indicates when the development system should sample PST and DDATA values. If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and PST and DDATA outputs from toggling without disabling triggers. Non-quiescent operation can be reenabled by clearing CSR[PCD], although the external deve lopment systems must resynchroniz e with the PST and DDATA outputs. PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs during system reset exception processing.

PST[3:0] Indicate core status. Debug mode timing is synchronous with the

processor clock; status is unrelated to the current bus transfer. The CLKOUT signal can be used by the development system to know when to sample PST[3:0].

All Processor Status

Outputs

ALLPST Logical AND of PST[3.0] O

2.16 EzPort Signal Descriptions

Table 2-15 contains a list of EzPort external signals

Table 2-15. EzPort Signal Descriptions

Signal Name Abbreviation Function I/O

EzPort Clock EZPCK Shift clock for EzPort transfers I

EzPort Chip Select EZPCS Chip select for signaling the start and end of

serial transfers

EzPort Serial Data In EZPD EZPD is sampled on the rising edge of EZPCK I

EzPort Serial Data Out EZPQ EZPQ transitions on the falling edge of EZPCK O

2-14 Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Signal Descriptions

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2.17 Power and Ground Pins

The pins described in Table 2-16 provide system power and ground to the chip. Multiple pins are provided for adequate current capability. All power supply pins must have adequate decoupling (bypass capacitance) for high-frequency noise suppression.

Table 2-16. Power and Ground Pins

Signal Name Abbreviation Function I/O

PLL Analog Supply VDDPLL,

VSSPLL

Positive Supply VDD These pins supply positive power to the core logic. I

Ground VSS This pin is the negative supply (ground) to the chip.

Dedicated power supply signals to isolate the sensitive PLL analog circuitry from the nor mal levels of noise present on the digital power supply.

Some of the VDD and VSS pins on the device are only to be used for noise bypass. Figure 2 shows a typical connection diagram. Pay particular attention to those pins which show only capacitor connections.

CAUTION

Avoid connecting power-supply voltage directly to pins in Figure 2 which show only capacitor connections, as doing so could damage the device severely.

Freescale Semiconductor 2-15

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Signal Descriptions

MCF52235

35 69 70 71 72 58 11 10 31 30 45 44 74 73

0.22µF 1000pF

VDDPLL VSSPLL

DDA

SSA

DDR

SSX1

DDX1

DDX2

SSX2

DD2

SS2

DD1

SS1

0.1µF 10µH

10µF 10V Tantalum

0.1µF

0.22µF

3.3V

PHY_V

DDA

PHY_V

DDTX

0.22µF

PHY_V

DDRX

PHY_RBIAS

0.22µF0.22µF

12.4KΩ 1%

0.1µF

Pin numbering is shown

for the 80-lead LQFP

optional

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Figure 2. Suggested connection scheme for Power and Ground

2-16 Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Chapter 3

Instruction

FIFO

Decode & Select,

Address

IAG

DSOC

AGEX

Instruction Buffer

Address

Generation

Fetch Cycle

Generation,

Execute

Operand Fetch

Instruction

Operand

Pipeline

Execution

Fetch

Pipeline

Address [ :0]

Read Data[31:0]

Write Data[31:0]

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ColdFire Core

3.1 Introduction

This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the ColdFire Family Programmer’s Reference Manual.

3.1.1 Overview

As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer.

The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), that decodes the

Freescale Semiconductor 3-1

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Figure 3-1. V2 ColdFire Core Pipelines

ColdFire Core

(described fully in Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC

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instruction, fetches the required operands, and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.

The V2 ColdFire core pipeline stages include the following:

• Two-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage) — Instruction address generation (IAG) — Calculates the next prefetch address — Instruction fetch cycle (IC)—Initiates prefetch on the processor’s local bus — Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO

queue

• Two-stage operand execution pipeline (OEP) — Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the

required components for effective address calculation, or the operand fetch cycle

— Address generation/execute cycle (AGEX)—Calculates operand address or executes the

instruction

When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the operand execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction in the IB until it is required by the OEP.

For register-to-register and register-to-memory store operations, the instruction passes through both OEP stages once. For memory-to-register and read-modify-write memory operations, an instruction is effectively staged through the OEP twice; the first time to calculate the effective address and initiate the operand fetch on the processor’s local bus, and the second time to complete the operand reference and perform the required function defined by the instruction.

The resulting pipeline and local bus structure allow the V2 ColdFire core to deliver sustained high performance across a variety of demanding embedded applications.

3.2 Memory Map/Register Description

The following sections describe the processor registers in the user and supervisor programming models. The programming model is selected based on the processor privilege level (user mode or supervisor mode) as defined by the S bit of the status register (SR). Table 3-1 lists the processor registers.

The user-programming model consists of the following registers:

• 16 general-purpose 32-bit registers (D0–D7, A0–A7)

• 32-bit program counter (PC)

• 8-bit condition code register (CCR)

• EMAC registers — Four 48-bit accumulator registers partitioned as follows:

– Four 32-bit accumulators (ACC0–ACC3) – Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two

32-bit values for load and store operations (ACCEXT01 and ACCEXT23).

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

3-2 Freescale Semiconductor

ColdFire Core

• Two 32-bit memory base address registers (RAMBAR, FLASHBAR)

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Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC

arithmetic operations generally affect the entire 48-bit destination. — One 16-bit mask register (MASK) — One 32-bit Status register (MACSR) including four indicator bits signaling product or

accumulation overflow (one for each accumulator: PAV0–PAV3)

The supervisor programming model is to be used only by system control software to implement restricted operating system functions, I/O control, and memory management. All accesses that affect the control features of ColdFire processors are in the supervisor programming model, that consists of registers available in user mode as well as the following control registers:

• 16-bit status register (SR)

• 32-bit supervisor stack pointer (SSP)

• 32-bit vector base register (VBR)

Table 3-1. ColdFire Core Programming Model

BDM

Load: 0x080

Store: 0x180

Load: 0x081

Store: 0x181

Load: 0x082–7 Store: 0x182–7

Load: 0x088–8E

Store: 0x188–8E

Load: 0x08F Store: 0x18F

0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 No 4.2.1/4-3 0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF No 4.2.2/4-5

0x806, 0x809, 0x80A, 0x80B

0x807 MAC Accumulator 0,1 Extension Bytes

Data Register 0 (D0) 32 R/W 0xCF2_6 No 3.2.1/3-4

Data Register 1 (D1) 32 R/W 0x No 3.2.1/3-4

Data Register 2–7 (D2–D7) 32 R/W Undefined No 3.2.1/3-4

Address Register 0–6 (A0–A6) 32 R/W Undefined No 3.2.2/3-4

Supervisor/User A7 Stack Pointer (A7) 32 R/W Undefined No 3.2.3/3-5

MAC Accumulators 0–3 (ACC0–3) 32 R/W Undefined No 4.2.3/4-7

(ACCext01)

Supervisor/User Access Registers

Width

(bits)

Access Reset Value

32 R/W Undefined No 4.2.4/4-7

Written with

MOVEC

Section/Page

0x808 MAC Accumulator 2,3 Extension Bytes

(ACCext23) 0x80E Condition Code Register (CCR) 8 R/W Undefined No 3.2.4/3-6 0x80F Program Counter (PC) 32 R/W Contents of

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32 R/W Undefined No 4.2.4/4-7

No 3.2.5/3-7

location

0x0000_0004

ColdFire Core

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Table 3-1. ColdFire Core Programming Model (continued)

BDM

0x800 User/Supervisor A7 Stack Pointer

(OTHER_A7)

0x801 Vector Base Register (VBR) 32 R/W 0x0000_0000 Yes 3.2.6/3-7 0x80E Status Register (SR) 16 R/W 0x27-- No 3.2.7/3-7

0xC04 Flash Base Address Register

(FLASHBAR)

0xC05 RAM Base Address Register (RAMBAR) 32 R/W See Section Yes 3.2.8/3-8

The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 31, “Debug Module”.

Supervisor Access Only Registers

Width

(bits)

Access Reset Value

32 R/W Contents of

location

0x0000_0000

32 R/W 0x0000_0000 Yes 3.2.8/3-8

Written with

MOVEC

No 3.2.3/3-5

Section/Page

3.2.1 Data Registers (D0–D7)

D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they can also be used as index registers.

NOTE

Registers D0 and D1 contain hardware configuration details after reset. See

Section 3.3.4.15, “Reset Exception” for more details.

BDM: Load: 0x080 + n; n = 0-7 (Dn)

Store: 0x180 + n; n = 0-7 (Dn)

313029282726252423222120191817161514131211109876543210

Reset

(D2-D7)

Reset

(D0, D1)

––––––––––––––––––––––––––––––––

Data

See Section 3.3.4.15, “Reset Exception”

Access: User read/write

BDM read/write

Figure 3-2. Data Registers (D0–D7)

3.2.2 Address Registers (A0–A6)

These registers can be used as software stack pointers, index registers, or base address registers. They can also be used for word and longword operations.

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BDM: Load: 0x088 + n; n =0–6 (An)

Store: 0x188 + n; n =0–6 (An)

313029282726252423222120191817161514131211109876543210

Address

Reset––––––––––––––––––––––––––––––––

Figure 3 -3 . Addr ess Re gisters (A0–A6)

Access: User read/write

BDM read/write

3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)

This ColdFire architecture supports two independent stack pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two program-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead, the hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents are a function of the processor operation mode, as shown in the following:

if SR[S] = 1

then A7 = Supervisor Stack Pointer

OTHER_A7 = User Stack Pointer

else A7 = User Stack Pointer

OTHER_A7 = Supervisor Stack Pointer

The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the responsibility of the external development system to determine, based on the setting of SR[S], the mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP).

To support dual stack pointers, the following two supervisor instructions are included in the ColdFire instruction set architecture to load/store the USP:

move.l Ay,USP;move to USP move.l USP,Ax;move from USP

These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other instruction references to the stack pointer, explicit or implicit, access the active A7 register.

NOTE

The USP must be initialized using the move.l Ay,USP instruction before any entry into user mode.

The SSP is loaded during reset exception processing with the contents of location 0x0000_0000.

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BDM: Load: 0x08F (A7)

Store: 0x18F (A7) 0x800 (OTHER_A7)

313029282726252423222120191817161514131211109876543210

Address

Reset––––––––––––––––––––––––––––––––

Access: A7: User or BDM read/write

OTHER_A7: Supervisor or BDM read/write

Figure 3-4. Stack Pointer Registers (A7 and OTHER_A7)

3.2.4 Condition Code Register (CCR)

The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results generated by processor operations. The extend bit (X) is also an input operand during multiprecision arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare (CMP), Bcc, or Scc instructions are executed.

BDM: LSB of Status Register (SR) Access: User read/write

BDM read/write

76543210

R 0 0 0

X N Z V C

Reset:0 0 0 —————

Figure 3-5. Condition Code Register (CCR)

Table 3-2. CCR Field Descriptions

Field Description

7–5 Reserved, must be cleared.

Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified

result.

Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.

Zero condition code bit. Set if result equals zero; otherwise cleared.

Z 1

Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand

size; otherwise cleared.

Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a

subtraction; otherwise cleared.

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3.2.5 Program Counter (PC)

The PC contains the currently executing instruction address. During instruction execution and exception processing, the processor automatically increments PC contents or places a new value in the PC. The PC is a base address for PC-relative operand addressing.

The PC is initially loaded during reset exception processing with the contents at location 0x0000_0004.

BDM: 0x80F (PC) Access: User read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

Reset––––––––––––––––––––––––––––––––

Figure 3-6. Program Counter Register (PC)

Address

3.2.6 Vector Base Register (VBR)

The VBR contains the base address of the exception vector table in the memory . T o access th e vector table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on a 1 MB boundary.

BDM: 0x801 (VBR) Access: Supervisor read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

Base Address

Reset00000000000000000000000000000000

Figure 3-7. Vector Base Register (VBR)

0 0 0 0 0 000000000 000 0 00

3.2.7 Status Register (SR)

The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and before any compare (CMP), Bcc, or Scc instructions execute.

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3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR)

The memory base address registers are used to specify the base address of the internal SRAM and flash modules and indicate the types of references mapped to each. Each base address register includes a base address, write-protect bit, address space mask bits, and an enable bit. FLASHBAR determines the base address of the on-chip flash, and RAMBAR determines the base address of the on-chip RAM. For more information, refer to Section 11.2.1, “SRAM Base Address Register (RAMBAR)” and Section 15.3.2,

“Flash Base Address Register (FLASHBAR)”.

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BDM: 0x80E (SR) Access: Supervisor read/write

BDM read/write

System Byte Condition Code Register (CCR)

1514131211109876543210

Reset00100111000—————

S M

000

X N ZVC

Figure 3-8. Status Register (SR) Table 3-3. SR Field Descriptions

Field Description

15TTrace enable. When set, the processor performs a trace exception after every instruction.

14 Reserved, must be cleared. 13SSupervisor/user state.

0User mode 1 Supervisor mode

12MMaster/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or

move to SR instructions.

11 Reserved, must be cleared.

10–8IInterrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or

equal to current level, except edge-sensitive level 7 requests, which cannot be masked.

7–0

CCR

Refer to Section 3.2.4, “Condition Code Register (CCR)”.

3.3 Functional Description

3.3.1 Version 2 ColdFire Microarchitecture

From the block diagram in Figure 3-1, the non-Harvard architecture of the processor is readily apparent. The processor interfaces to the local memory subsystem via a single 32-bit address and two unidirectional 32-bit data buses. This structure minimizes the core size without compromising performance to a large degree.

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IAG IC IB

Core Bus Address

Core Bus

Read Data

Opword

Extension 1

Extension 2

FIFO

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write Data

RGF

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A more detailed view of the hardware structure within the two pipelines is presented in Figure 3-9 and

Figure 3-10 below . In these diagrams, the internal structure of the instruction fetch and operand execution

pipelines is shown:

Figure 3-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram

Figure 3-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram

The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For sequential prefetches, the next instruction address is generated by adding four to the last prefetch address. This function is performed during the IAG stage and the resulting prefetch address gated onto the core bus (if there are no pending operand memory accesses assigned a higher priority). After the prefetch address is driven onto the core bus, the instruction fetch cycle accesses the appropriate local memory and returns the instruction read data back to the IFP during the cycle. If the accessed data is not present in a local memory (e.g., an instruction cache miss, or an external access cycle is required), the IFP is stalled in the

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Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write

Data

new Rx

RGF

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IC stage until the referenced data is available. As the prefetch data arrives in the IFP, it can be loaded into the FIFO instruction buffer or gated directly into the OEP.

The V2 design uses a simple static conditional branch prediction algorithm (forward-assumed as not-taken, backward-assumed as taken), and all change-of-flow operations are calculated by the OEP and the target instruction address fed back to the IFP.

The IFP and OEP are decoupled by the FIFO instruction buffer , allowing instruction prefetching to occur with the available core bus bandwidth not used for operand memory accesses. For the V2 design, the instruction buffer contains three 32-bit locations.

Consider the operation of the OEP for three basic classes of non-branch instructions:

• Register-to-register:

op Ry,Rx

• Embedded load:

op <mem>y,Rx

• Register-to-memory (store)

move Ry,<mem>x

For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and fetching of the required register operands (OC) from the dual-ported register file, while the actual instruction execution is performed in the second stage (EX) in one of the execute engines (e.g., ALU, barrel shifter, divider, EMAC). There are no operand memory accesses associated with this class of instructions, and the execution time is typically a single machine cycle. See Figure 3-11.

For memory-to-register (embedded-load) instructions, the instruction is effectively staged through the OEP twice with a basic execution time of three cycles. First, the instruction is decoded and the components

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MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Figure 3-11. V2 OEP Register-to-Register

ColdFire Core

Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write

RGF

Data

d16

<ea>y

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of the operand address (base register from the RGF and displacement) are selected (DS). Second, the operand effective address is generated using the ALU execute engine (AG). Third, the memory read operand is fetched from the core bus, while any required register operand is simultaneously fetched (OC) from the RGF. Finally, in the fourth cycle, the instruction is executed (EX). The heavily-used 32-bit load instruction (

move.l <mem>y,Rx) is optimized to support a two-cycle execution time. The following example

in Figure 3-12 shows an effective address of the form <ea>y = (d16,A y), i.e., a 16-bi t signed displacement added to a base register Ay.

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Figure 3-12. V2 OEP Embedded-Load Part 1

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Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write

RGF

Data

new Rx

<mem>y

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Figure 3-13. V2 OEP Embedded-Load Part 2

For register-to-memory (store) operations, the stage functions (DS/OC, AG/EX) are effectively performed simultaneously allowing single-cycle execution. See Figure 3-14 where the effective address is of the form <ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax.

For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store operation for a three-cycle execution time.

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Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write

RGF

Data

d16

<ea>x

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Figure 3-14. V2 OEP Register-to-Memory

The pipeline timing diagrams of Figure 3-15 depict the execution templates for these three classes of instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown progressing down the operand execution pipeline.

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Core clock

Core Bus

Embedded-Load

Core Bus

op read

Core Bus

op write

OEP.DSOC OC next

OEP.AGEX EX

OEP.DSOC DS OC next

OEP.AGEX EXAG

OEP.DSOC DSOC next

OEP.AGEX AGEX

(Store)

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3.3.2 Instruction Set Architecture (ISA_A+)

The original ColdFire instruction set architecture (ISA_A) was derived from the M68000 family opcodes based on extensive analysis of embedded application code. The ISA was optimized for code compiled from high-level languages where the dominant operand size was the 32-bit integer declaration. This approach minimized processor complexity and cost, while providing excellent performance for compiled applications.

After the initial ColdFire compilers were created, developers noted there were certain ISA additions that would enhance code density and overall performance. Additionally , as users implemented ColdFire-based designs into a wide range of embedded systems, they found certain frequently-used instruction sequences that could be improved by the creation of additional instructions.

The original ISA definition minimized support for instructions referencing byte- and word-sized operands. Full support for the move byte and move word instructions was provided, but the only other opcodes supporting these data types are CLR (clear) and TST (test). A set of instruction enhancements has been implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three areas:

1. Enhanced support for byte and word-sized operands

2. Enhanced support for position-independent code

3. Miscellaneous instruction additions to address new functionality

Figure 3-15. V2 OEP Pipeline Execution Templates

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2. The processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to special locations within the interrupt controller’s address space with the interrupt level encoded in the address.

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Table 3-4 summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details

see the ColdFire Family Programmer’s Reference Manual.

Table 3-4. Instruction Enhancements over Revision ISA_A

Instruction Description

BITREV The contents of the destination data register are bit-reversed; new Dn[31] equals old Dn[0], new

Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31].

BYTEREV The contents of the destination data register are byte-reversed; new Dn[31:24] equals old

Dn[7:0],..., new Dn[7:0] equals old Dn[31:24].

FF1 The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending

with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then loaded with the offset count from bit 31 where the first set bit appears.

Move from USP USP → Destination register

Move to USP Source register → USP

STLDSR Pushes the contents of the status register onto the stack and then reloads the status register

with the immediate data value.

3.3.3 Exception Processing Overview

Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors differ from the M68000 family because they include:

• A simplified exception vector table

• Reduced relocation capabilities using the vector-base register

• A single exception stack frame format

• Use of separate system stack pointers for user and supervisor modes.

All ColdFire processors use an instruction restart exception model. However, Version 2 ColdFire processors require more software support to recover from certain access errors. See Section 3.3.4.1,

“Access Error Exception” for details.

Exception processing includes all actions from fault condition detection to the initiation of fetch for first handler instruction. Exception processing is comprised of four major steps:

1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to be cleared and the interrupt priority mask to set to current interrupt request level.

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All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see

Table 3-5).

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3. The processor saves the current context by creating an exception stack frame on the system stack. The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to by the supervisor stack pointer (SSP). As shown in Figure 3-16, the processor uses a simplified fixed-length stack frame for all exceptions. The exception type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next).

4. The processor calculates the address of the first instruction of the exception handler. By definition, the exception vector table is aligned on a 1 MB boundary . This instruction address is generated by fetching an exception vector from the table located at the address defined in the vector base register . The index into the exception table is calculated as (4 × vector number). After the exception vector has been fetched, the vector contents determine the address of the first instruction of the desired handler. After the instruction fetch for the first opcode of the handler has initiated, exception processing terminates and normal instruction processing continues in the handler.

The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are device-specific peripheral interrupt vectors. See Chapter 15, “Interrupt Controller Module” for details on the device-specific interrupt sources.

Table 3-5. Exception Vector Assignments

Vector

Number(s)

0 0x000 — Initial supervisor stack pointer 1 0x004 — Initial program counter 2 0x008 Fault Access error 3 0x00C Fault Address error 4 0x010 Fault Illegal instruction 5 0x014 Fault Divide by zero

6–7 0x018–0x01C — Reserved

8 0x020 Fault Privilege violation

9 0x024 Next Trace 10 0x028 Fault Unimplemented line-A opcode 11 0x02C Fault Unimplemented line-F opcode 12 0x030 Next Debug interrupt 13 0x034 — Reserved 14 0x038 Fault Format error

15–23 0x03C–0x05C — Reserved

24 0x060 Next Spurious interrupt

Vector

Offset (Hex)

Stacked

Program

Counter

Assignment

25–31 0x064–0x07C — Reserved

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Table 3-5. Exception Vector Assignments (continued)

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ColdFire Core

Vector

Number(s)

32–47 0x080–0x0BC Next Trap # 0-15 instructions 48–63 0x0C0–0x0FC — Reserved

64–255 0x100–0x3FC Next Device-specific interrupts

Fault ref ers to the PC of the instruction that caused the exception. Next ref ers to the PC of the instruction that follows the instruction that caused the fault.

Vector

Offset (Hex)

Stacked

Program

Counter

Assignment

All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level contained in the status register. In addition, the ISA_A+ architecture includes an instruction (STLDSR) that stores the current interrupt mask level and loads a value into the SR. This instruction is specifically intended for use as the first instruction of an interrupt service routine that services multiple interrupt requests with different interrupt levels. For more details, see ColdFire Family Programmer’s Reference Manual.

3.3.3.1 Exception Stack Frame Definition

Figure 3-16 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)

and the 16-bit status register, and the second longword contains the 32-bit program counter address.

313029282726252423222120191817161514131211109876543210

SSP → Format FS[3:2] Vector FS[1:0] Status Register

+ 0x4

Program Counter

Figure 3-16. Exception Stack Frame Form

The 16-bit format/vector word contains three unique fields:

• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by the processor, indicating a two-longword frame format. See Table 3-6.

Table 3-6. Format Field Encodings

Original SSP @ Time

of Exception, Bits 1:0

00 Original SSP - 8 0100 01 Original SSP - 9 0101 10 Original SSP - 10 0110 11 Original SSP - 11 0111

SSP @ 1st

Instruction of

Handler

Format Field

• There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other exceptions. See Table 3-7.

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Table 3-7. Fault Status Encodings

FS[3:0] Definition

00xx Reserved 0100 Error on instruction fetch 0101 Reserved 011x Reserved 1000 Error on operand write 1001 Attempted write to write-protected space 101x Reserved 1100 Error on operand read 1101 Reserved 111x Reserved

• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor for all internal faults and represents the value supplied by the interrupt controller in case of an interrupt. See Table 3-5.

3.3.4 Processor Exceptions

3.3.4.1 Access Error Exception

The exact processor response to an access error depends on the memory reference being performed. For an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an instruction for execution. Therefore, faults during instruction prefetches followed by a change of instruction flow do not generate an exception. When the processor attempts to execute an instruction with a faulted opword and/or extension words, the access error is signaled and the instruction is aborted. For this type of exception, the programming model has not been altered by the instruction generating the access error.

If the access error occurs on an operand read, the processor immediately aborts the current instruction’s execution and initiates exception processing. In this situation, any address register updates attributable to the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming model contains the updated An value. In addition, if an access error occurs during a MOVEM instruction loading from memory, any registers already updated before the fault occurs contain the operands from memory.

The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes. Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. Accordingly , the PC contained in the exception stack fra me merely represents the location in the program when the access error was signaled. All programming model updates associated with the write instruction are completed. The NOP instruction can collect access errors for writes. This instruction delays its

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execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.

3.3.4.2 Address Error Exception

Any attempted execution transferring control to an odd instruction address (if bit 0 of the target address is set) results in an address error exception.

Any attempted use of a word-sized index register (Xn.w) or a scale factor of eight on an indexed effective addressing mode generates an address error, as does an attempted execution of a full-format indexed addressing mode, which is defined by bit 8 of extension word 1 being set.

If an address error occurs on a JSR instruction, the Version 2 ColdFire processor calculates the target address then the return address is pushed onto the stack. If an address error occurs on an R TS instruction, the Version 2 ColdFire processor overwrites the faulting return PC with the address error stack frame.

3.3.4.3 Illegal Instruction Exception

The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits. The first instruction word is known as the operation word (or opword), while the optional words are known as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode (opmode), and the low-order 6 bits define the effective address. See Figure 3-17. The opword line definition is shown in Table 3-8.

1514131211109876543210

Line OpMode Effective Address

Mode Register

Figure 3-17. ColdFire Instruction Operation Word (Opword) Format

Table 3-8. ColdFire Opword Line Definition

Opword[Line] Instruction Class

0x0 Bit manipulation, Arithmetic and Logical Immediate 0x1 Move Byte 0x2 Move Long 0x3 Move Word 0x4 Miscellaneous 0x5 Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc) 0x6 PC-relative change-of-flow instructions

Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR) 0x7 Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ) 0x8 Logical OR (OR) 0x9 Subtract (SUB), Subtract Extended (SUBX)

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Table 3-8. ColdFire Opword Line Definition (continued)

Opword[Line] Instruction Class

0xA EMAC, Move 3-bit Quick (MOV3Q) 0xB Compare (CMP), Exclusive-OR (EOR) 0xC Logical AND (AND), Multiply Word (MUL) 0xD Add (ADD), Add Extended (ADDX) 0xE Arithmetic and logical shifts (ASL, ASR, LSL, LSR) 0xF Cache Push (CPUSHL), Write DDATA (WDDATA), Write Debug (WDEBUG)

In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations (line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors associated with illegal opwords in these two lines.

Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an illegal instruction exception (vector 4). Additionally , any attempted execution of any non-MAC line-A and most line-F opcodes generate their unique exception types, vector numbers 10 and 11, respectively. ColdFire cores do not provide illegal instruction detection on the extension words on any instruction, including MOVEC.

3.3.4.4 Divide-By-Zero

Attempting to divide by zero causes an exception (vector 5, offset equal 0x014).

3.3.4.5 Privilege Violation

The attempted execution of a supervisor mode instruction while in user mode generates a privilege violation exception. See ColdFire Programmer’s Reference Manual for a list of supervisor-mode instructions.

There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in user mode for debugging purposes.

3.3.4.6 Trace Exception

To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction execution (for all but the stop instruction) signals a trace exception. This functionality allows a debugger to monitor program execution.

The stop instruction has the following effects:

1. The instruction before the stop executes and then generates a trace exception. In the exception stack frame, the PC points to the stop opcode.

2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate operand from the instruction.

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3. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in the previous step.

If the processor is not in trace mode and executes a stop instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in step 2.

Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. As an example, consider a TRAP instruction execution while in trace mode. The processor initiates the trap exception and then passes control to the corresponding handler . If the system requires that a trace exception be processed, it is the responsibility of the trap exception handler to check for this condition (SR[T] in the exception stack frame set) and pass control to the trace handler before returning from the original exception.

3.3.4.7 Unimplemented Line-A Opcode

A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the attempted execution of an undefined line-A opcode.

3.3.4.8 Unimplemented Line-F Opcode

A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when attempting to execute an undefined line-F opcode.

3.3.4.9 Debug Interrupt

See Chapter 31, “Debug Module,” for a detailed explanation of this exception, which is generated in response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle, but rather calculates the vector number internally (vector number 12). Additionally , SR[M,I] are unaffected by the interrupt.

3.3.4.10 RTE and Format Error Exception

When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire core, any attempted R TE execution (where the format is not equal to {4,5,6,7}) generates a format error. The exception stack frame for the format error is created without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.

The selection of the format value provides some limited debug support for porting code from M68000 applications. On M68000 family processors, the SR was located at the top of the stack. On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE is attempted using this old format, it generates a format error on a ColdFire processor.

If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame.

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3.3.4.11 TRAP Instruction Exception

The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls. The TRAP instruction may be used to change from user to supervisor mode.

3.3.4.12 Unsupported Instruction Exception

If execution of a valid instruction is attempted but the required hardware is not present in the processor , an unsupported instruction exception is generated. The instruction functionality can then be emulated in the exception handler, if desired.

All ColdFire cores record the processor hardware configuration in the D0 register immediately after the negation of RESET. See Section 3.3.4.15, “Reset Exception,” for details.

3.3.4.13 Interrupt Exception

Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from the interrupt controller using an IACK cycle. See Chapter 15, “Interrupt Controller Module,” for details on the interrupt controller.

3.3.4.14 Fault-on-Fault Halt

If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to to exit this state.

3.3.4.15 Reset Exception

Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered.

The reset exception places the processor in the supervisor mode by setting the SR[S] bit and disables tracing by clearing the SR[T] bit. This exception also clears the SR[M] bit and sets the processor’s SR[I] field to the highest level (level 7, 0b11 1). Next, the VBR is initialized to zero (0x0000_0000). The control registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly to the processor are disabled.

NOTE

Other implementation-specific registers are also affected. Refer to each module in this reference manual for details on these registers.

After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at address 0x0000_0000 is loaded into the supervisor stack pointer and the second longword at address 0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault state.

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ColdFire processors load hardware configuration information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM to determine the hardware configuration.

Information loaded into D0 defines the processor hardware configuration as shown in Figure 3-18.

BDM: Load: 0x080 (D0)

Store: 0x180 (D0)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R PF VER REV

Reset1100111100100000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R MAC DIVEMACFPU0000 ISA DEBUG

Reset01100 001000 00

Access: User read-only

BDM read-only

Figure 3-18. D0 Hardware Configuration Info

Table 3-9. D0 Hardware Configuration Info Field Description

Field Description

31–24PFProcessor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.

23–20

VER

ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core. 0001 V1 ColdFire core 0010 V2 ColdFire core (This is the value used for this device.) 0011 V3 ColdFire core 0100 V4 ColdFire core 0101 V5 ColdFire core Else Reserved for future use

19–16

REV

MAC

EMAC

FPU

Freescale Semiconductor 3-23

Processor revision number. The default is 0b000 0.

MAC present. This bit signals if the optional multiply-accumulate (MAC) ex ecution engine is present in processor core. 0 MAC execute engine not present in core. (This is the value used for this device.) 1 MAC execute engine is present in core.

Divide present. This bit signals if the hardware divider (DIV) is present in the processor core.

DIV

0 Divide execute engine not present in core. 1 Divide execute engine is present in core.

EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution engine is present in processor core. 0 EMAC execute engine not present in core. 1 EMAC execute engine is present in core. (This is the value used for this device.)

FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core. 0 FPU execute engine not present in core. (This is the value used for this device.) 1 FPU execute engine is present in core.

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Table 3-9. D0 Hardware Configuration Info Field Description (continued)

Field Description

–8 Reserved.

7–4

ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core.

ISA

0000 ISA_A 0001 ISA_B 0010 ISA_C 1000 ISA_A+ (This is the value used for this device.) Else Reserved

3–0

Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core.

DEBUG

0000 DEBUG_A 0001 DEBUG_B 0010 DEBUG_C 0011 DEBUG_D 0100 DEBUG_E 1001 DEBUG_B+ 1011 DEBUG_D+ 1111 DEBUG_D+PST Buffer Else Reserved

Information loaded into D1 defines the local memory hardware configuration as shown in the figure below .

BDM: Load: 0x1 (D1)

Store: 0x1 (D1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R CLSZ CCAS CCSZ FLASHSZ 0 0 0

1514131211109876543210

RMBSZ UCAS 0000 SRAMSZ 000

Access: User read-only

BDM read-only

Figure 3-19. D1 Hardware Configuration Info

Table 3-10. D1 Hardware Configuration Information Field Description

Field Description

31–30

CLSZ

29–28 CCAS

Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.

Configurable cache associativity. 00 Four-way 01 Direct mapped (This is the value used for this device) Else Reserved for future use

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Table 3-10. D1 Hardware Configuration Information Field Description (continued)

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Field Description

ColdFire Core

27–24 CCSZ

23–19

FLASHSZ

18–16 Reserved 15–14

MBSZ

Configurable cache size. Indicates the amount of instruction/data cache.The cache configuration options available are 50% instruction/50% data, 100% instruction, or 100% data, and are specified in the CACR register. 0000 No configurable cache 0001 512 B configurable cache 0010 1 KB configurable cache 0011 2 KB configurable cache 0100 4 KB configurable cache 0101 8 KB configurable cache 0110 16 KB configurable cache 0111 32 KB configurable cache Else Reserved

Flash bank size. 00000-01110 No flash 10000 64 KB flash 10010 128 KB flash 10011 96 KB flash 10100 256 KB flash 10110 512 KB flash Else Reserved for future use

Bus size. Defines the width of the ColdFire master bus datapath. 00 32-bit system bus datapath (This is the value used for this device) 01 64-bit system bus datapath Else Reserved

13–8 Reserved, resets to 0b01_0000

7–3

SRAMSZ

2–0 Reserved.

SRAM bank size. 00000 No SRAM 00010 512 bytes 00100 1 KB 00110 2 KB 01000 4 KB 01010 8 KB 01100 16 KB 01111 24 KB 01110 32 KB 10000 64 KB 10010 128 KB Else Reserved for future use

3.3.5 Instruction Execution Timing

This section presents processor instruction execution times in terms of processor-core clock cycles. The number of operand references for each instruction is enclosed in parentheses following the number of processor clock cycles. Each timing entry is presented as C(R/W) where:

•C is the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution.

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• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing a read-modify-write function is denoted as (1/1).

This section includes the assumptions concerning the timing values and the execution time details.

3.3.5.1 Timing Assumptions

For the timing data presented in this section, these assumptions apply:

1. The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or extension words.

2. The OEP does not experience any sequence-related pipeline stalls. The most common example of stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE operations (except MOVEM), certain hardware resources within the processor are marked as busy for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive STORE operations is two cycles. The MOVEM instruction uses a different set of resources and this stall does not apply.

3. The OEP completes all memory accesses without any stall conditions caused by the memory itself. Thus, the timing details provided in this section assume that an infinite zero-wait state memory is attached to the processor core.

4. All operand data accesses are aligned on the same byte boundary as the operand size; for example, 16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4 addresses.

The processor core decomposes misaligned operand references into a series of aligned accesses as shown in Table 3-11.

Table 3-11. Misaligned Operand References

address[1:0] Size

01 or 11 Word Byte, Byte 2(1/0) if read

01 or 11 Long Byte, Word,

10 Long Word, Word 2(1/0) if read

Bus

Operations

Byte

Additional

C(R/W)

1(0/1) if write 3(2/0) if read

2(0/2) if write

1(0/1) if write

3.3.5.2 MOVE Instruction Execution Times

Table 3-12 lists execution times for MOVE.{B,W} instructions; Table 3-13 lists timings for MOVE.L.

NOTE

For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode.

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ET with {<ea> = (d16,PC)} equals ET with {<ea> = (d16,An)} ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<ea> = (d8,An,Xi*SF)}

The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w and xxx.l.

Table 3-12. MOVE Byte and Word Execution Times

Destination

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1)

(Ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1)

-(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1)

(d16,Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,Ay,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

xxx.w 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

xxx.l 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1)) — — —

#xxx 1(0/0) 3(0/1) 3(0/1) 3(0/1) — — —

Table 3-13. MOVE Long Execution Times

Destination

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

(Ay)+ 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

-(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

(d16,Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

(d8,Ay,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

(d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

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(d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

#xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — —

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3.3.5.3 Standard One Operand Instruction Execution Times

Table 3-14. One Operand Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

BITREVDx1(0/0)———— — ——

BYTEREVDx1(0/0)———— — ——

CLR.B <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

CLR.W <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

CLR.L <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

EXT.WDx1(0/0)———— — ——

EXT.LDx1(0/0)———— — ——

EXTB.LDx1(0/0)———— — ——

FF1Dx1(0/0)———— — ——

NEG.LDx1(0/0)———— — ——

NEGX.LDx1(0/0)———— — ——

NOT.LDx1(0/0)———— — ——

SCCDx1(0/0)———— — ——

SWAPDx1(0/0)———— — ——

TST.B <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

TST.W <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

TST.L <ea> 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)

3.3.5.4 Standard Two Operand Instruction Execution Times

Table 3-15. Two Operand Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

ADD.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) ADD.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ADDI.L #imm,Dx 1(0/0) — — — — — — —

ADDQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ADDX.L Dy,Dx 1(0/0) — — — — — — —

AND.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) AND.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ANDI.L #imm,Dx 1(0/0) — — — — — — —

(d16,An) (d16,PC)

(d8,An,Xn*SF)

(d8,PC,Xn*SF)

xxx.wl #xxx

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Table 3-15. Two Operand Instruction Execution Times (continued)

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

ASL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0) ASR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0) BCHG Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — BCHG #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

BCLR Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — BCLR #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — BSET Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — BSET #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — BTST Dy,<ea> 2(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) — BTST #imm,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —

CMP.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

CMPI.L #imm,Dx 1(0/0) — — — — — — — DIVS.W <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) DIVU.W <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)

DIVS.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —

DIVU.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —

EOR.L Dy,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

EORI.L #imm,Dx 1(0/0) — — — — — — —

LEA <ea>,Ax — 1(0/0) — — 1(0/0) 2(0/0) 1(0/0) —

LSL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

LSR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

MOVEQ.L #imm,Dx — — — — — — — 1(0/0)

OR.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) OR.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ORI.L #imm,Dx 1(0/0) — — — — — — — REMS.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — — REMU.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —

SUB.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) SUB.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

SUBI.L #imm,Dx 1(0/0) — — — — — — —

SUBQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

SUBX.L Dy,Dx 1(0/0) — — — — — — —

(d16,An) (d16,PC)

(d8,An,Xn*SF)

(d8,PC,Xn*SF)

xxx.wl #xxx

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3.3.5.5 Miscellaneous Instruction Execution Times

Table 3-16. Miscellaneous Instruction Execution Times

Effective Address

Opcode <EA>

CPUSHL (Ax) — 11(0/1) — — — — — —

LINK.W Ay,#imm 2(0/1) — — — — — — — MOVE.L Ay,USP 3(0/0) — — — — — — — MOVE.L USP,Ax 3(0/0) — — — — — — —

MOVE.W CCR,Dx 1(0/0) — — — — — — — MOVE.W <ea>,CCR 1(0/0) — — — — — — 1(0/0) MOVE.W SR,Dx 1(0/0) — — — — — — — MOVE.W <ea>,SR 7(0/0) — — — — — — 7(0/0)

MOVEC Ry,Rc 9(0/1) — — — — — — —

MOVEM.L <ea>,and

list

MOVEM.L and

list,<ea>

NOP 3(0/0)———— — ——

PEA <ea> — 2(0/1) — — 2(0/1)

PULSE 1(0/0)———— — ——

STLDSR#imm————— — —5(0/1)

STOP#imm————— — —3(0/0) TRAP#imm————— — —15(1/2)

TPF 1(0/0)———— — ——

TPF.W 1(0/0)———— — ——

TPF.L 1(0/0)———— — —— UNLK Ax 2(1/0) — — — — — — —

WDDATA <ea> — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —

WDEBUG<ea> —5(2/0)— —5(2/0) — — —

The n is the number of registers moved by the MOVEM opcode.

If a MOVE.W #imm,SR instruction is executed and imm[13] equ als 1, the execution time is 1(0/0).

The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.

PEA execution times are the same for (d16,PC).

PEA execution times are the same for (d8,PC,Xn*SF).

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

—1+n(n/0)— —1+n(n/0) — — —

—1+n(0/n)— —1+n(0/n) — — —

3(0/1)

2(0/1) —

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3.3.5.6 EMAC Instruction Execution Times

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Table 3-17. EMAC Instruction Execution Times

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An)

MAC.L Ry, Rx, Raccx 1(0/0) — — — — — — —

MAC.L Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0) MAC.W Ry, Rx, Raccx 1(0/0) — — — — — — — MAC.W Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)

MOVE.L <ea>y, Raccx 1(0/0) — — — — — — 1(0/0) MOVE.L Raccy,Raccx 1(0/0) — — — — — — — MOVE.L <ea>y, MACSR 5(0/0) — — — — — — 5(0/0) MOVE.L <ea>y, Rmask 4(0/0) — — — — — — 4(0/0) MOVE.L <ea>y,Raccext01 1(0/0) — — — — — — 1(0/0)

Effective Address

ColdFire Core

(d8,An, Xn*SF)

xxx.wl #xxx

———

MOVE.L <ea>y,Raccext23 1(0/0) — — — — — — 1(0/0)

MOVE.L Raccx,<ea>x 1(0/0)

——— — ——— MOVE.L MACSR,<ea>x 1(0/0) — — — — — — — MOVE.L Rmask, <ea>x 1(0/0) — — — — — — — MOVE.L Raccext01,<ea.x 1(0/0) — — — — — — — MOVE.L Raccext23,<ea>x 1(0/0) — — — — — — —

MSAC.L Ry, Rx, Raccx 1(0/0) — — — — — — —

MSAC.W Ry, Rx, Raccx 1(0/0) — — — — — — —

MSAC.L Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)

MSAC.W Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)

———

MULS.L <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) — — —

MULS.W <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) (1/0) (1/0) 4(0/0)

MULU.L <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1 /0) — — —

MULU.W <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) (1/0) (1/0) 4(0/0)

Effective address of (d16,PC) not supported

Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] equals 1---, -11-, --11)

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NOTE

The execution times for moving the contents of the Racc, Raccext[01,23], MACSR, or Rmask into a destination location <ea>x shown in this table represent the best-case scenario when the store instruction is executed and there are no load or M{S}AC instructions in the EMAC execution pipeline. In general, these store operations require only a single cycle for execution, but if preceded immediately by a load, MAC, or MSAC instruction, the depth of the EMAC pipeline is exposed and the execution time is four cycles.

3.3.5.7 Branch Instruction Execution Times

Table 3-18. General Branch Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

BRA — — — — 2(0/1) — — — BSR — — — — 3(0/1) — — —

(d16,An) (d16,PC)

(d8,An,Xi*SF)

(d8,PC,Xi*SF)

xxx.wl #xxx

JMP <ea> — 3(0/0) — — 3(0/0) 4(0/0) 3(0/0) —

JSR <ea> — 3(0/1) — — 3(0/1) 4(0/1) 3(0/1) — RTE — — 10(2/0) — — — — — RTS ——5(1/0)—————

Table 3-19. Bcc Instruction Execution Times

Opcode

Bcc 3(0/0) 1(0/0) 2(0/0) 3(0/0)

Forward

T aken

Forward

Not Taken

Backward

T aken

Backward Not T a ken

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Chapter 4

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Enhanced Multiply-Accumulate Unit (EMAC)

4.1 Introduction

This chapter describes the functionality, microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors.

4.1.1 Overview

The EMAC design provides a set of DSP operations that can improve the performance of embedded code while supporting the integer multiply instructions of the baseline ColdFire architecture.

The MAC provides functionality in three related areas:

1. Signed and unsigned integer multiplication

2. Multiply-accumulate operations supporting signed and unsigned integer operands as well as signed, fixed-point, and fractional operands

3. Miscellaneous register operations

The ColdFire family supports two MAC implementations with different performance levels and capabilities. The original MAC features a three-stage execution pipeline optimized for 16-bit operands, with a 16x16 multiply array and a single 32-bit accumulator. The EMAC features a four-stage pipeline optimized for 32-bit operands, with a fully pipelined 32 × 32 multiply array and four 48-bit accumulators.

The first ColdFire MAC supported signed and unsigned integer operands and was optimized for 16x16 operations, such as those found in applications including servo control and image compression. As ColdFire-based systems proliferated, the desire for more precision on input operands increased. The result was an improved ColdFire MAC with user-programmable control to optionally enable use of fractional input operands.

EMAC improvements target three primary areas:

• Improved performance of 32 × 32 multiply operation.

• Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges between the accumulator and the pipeline’s general-purpose registers

• A 48-bit accumulation data path to allow a 40-bit product, plus 8 extension bits increase the dynamic number range when implementing signal processing algorithms

The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module (Figure 4-1).

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Enhanced Multiply-Accumulate Unit (EMAC)

Operand Y Operand X

Shift 0,1,-1

Accumulator(s)

yi() ak()yi k–()

k1=

N1–

∑

bk()xi k–()

k0=

N1–

∑

yi() bk()xi k–()

k0=

∑

b0()xi() b1()xi 1–()b2()xi 2–()b3()xi 3–()+++==

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Figure 4-1. Multiply-Accumulate Functionality Diagram

4.1.1.1 Introduction to the MAC

The MAC is an extension of the basic multiplier in most microprocessors. It is typically implemented in hardware within an architecture and supports rapid execution of signal processing algorithms in fewer cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements beyond scope of any processor architecture and may require full DSP implementation.

T o balance speed, size, and functionality, the ColdFire MAC is optimized for a small set of operations that involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for single-cycle pipelined operations with a possible accumulation after product generation. This functionality is common in many signal processing applications. The ColdFire core architecture is also modified to allow an operand to be fetched in parallel with a multiply , increasing overall perfo rmance for certain DSP operations.

Consider a typical filtering operation where the filter is defined as in Equation 4-1.

Eqn. 4-1

Here, the output y(i) is determined by past output values and past input values. This is the general form of an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies and product summing. To show this point, reduce Equation 4-1 to a simple, four-tap FIR filter, shown in

Equation 4-2, in which the accumulated sum is a past data values and coefficients sum.

Eqn. 4-2

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4.2 Memory Map/Register Definition

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The following table and sections explain the MAC registers:

Table 4-1. EMAC Memory Map

Enhanced Multiply-Accumulate Unit (EMAC)

BDM

0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 4.2.1/4-3 0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF 4.2.2/4-5 0x806 MAC Accumulator 0 (ACC0) 32 R/W Undefined 4.2.3/4-7 0x807 MAC Accumulator 0,1 Extension Bytes (ACCext01) 32 R/W Undefined 4.2.4/4-7 0x808 MAC Accumulator 2,3 Extension Bytes (ACCext23) 32 R/W Undefined 4.2.4/4-7

0x809 MAC Accumulator 1 (ACC1) 32 R/W Undefined 4.2.3/4-7 0x80A MAC Accumulator 2 (ACC2) 32 R /W Undefined 4.2.3/4-7 0x80B MAC Accumulator 3 (ACC3) 32 R /W Undefined 4.2.3/4-7

The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 31, “Debug Module.”

Width

(bits)

Access Reset Value Section/Page

4.2.1 MAC Status Register (MACSR)

The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags. Operational mode bits control whether operands are signed or unsigned and whether they are treated as integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding is performed. Negative, zero, and multiple overflow condition flags are also provided.

BDM: 0x804 (MACSR) Access: Supervisor read/write

BDM read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset000000000000000000000000 0 0 0 0 0 0 0 0

PAVn OMC

S/U F/I R/T N Z VEV

Figure 4-2. MAC Status Register (MACSR)

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Table 4-2. MACSR Field Descriptions

Field Description

31–12 Reserved, must be cleared.

11–8

PAVn

OMC

S/U

Product/accumulation overflow flags. Contains f our flags, one per accumulator , that indicate if past MA C or MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a MAC or MSA C instruction is e x ecuted, the PAVn flag associated with the destination accumulator forms the general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a move.l, MACSR instruction or the accumulator is loaded directly.

Bit 11: Accumulator 3 ... Bit 8: Accumulator 0

Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set to the appropriate constant (see S/U field description) on any operation that overflows the accumulator. After saturation, the accumulator remains unaffected by any other MA C or MSAC instructions until the overflow bit is cleared or the accumulator is directly loaded.

Signed/unsigned operations.

In integer mode:

S/U determines whether operations performed are signed or unsigned. It also determines the accumulator value during saturation, if enabled. 0 Signed numbers. On overflow, if OMC is enabled, an accumulator saturates to the most positive

(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on the instruction and the product value that overflowed.

1 Unsigned numbers. On overflow, if OMC is enabled, an accumulator saturates to the smallest value

(0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.

In fractional mode:

S/U controls rounding while storing an accumulator to a general-purpose register. 0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose

1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when mo v ed to

a general-purpose register. See Section 4.3.1.1, “Rounding”. The resulting 16-bit value is stored in the lower word of the destination register. The upper word is zero-filled. This rounding procedure does not affect the accumulator value.

F/I

Fractional/integer mode. Determines whether input operands are treated as fractions or integers. 0 Integers can be represented in signed or unsigned notation, depending on the value of S/U. 1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to

-15

for 16-bit fractions and -1 to 1 - 2

1-2

-31

for 32-bit fractions. See Section4.3.4, “Data

Representation."

R/T

Round/truncate mode. Controls rounding procedure for move.l ACCx,Rx, or MSAC.L instructions when in fractional mode. 0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator. Additionally, when

a store accumulator instruction is executed (move.l ACCx,Rx), the 8 lsbs of the 48-bit accumulator logic are truncated.

1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest

40-bit value. If the low-order 24 bits equal 0x80_0000, the upper 40 bits are rounded to the nearest even (lsb = 0) value. See Section 4.3.1.1, “Rounding”. Additionally, when a store accumulator instruction is executed (move.l ACCx,Rx), the lsbs of the 48-bit accumulator logic round the resulting 16- or 32-bit value. If MACSR[S/U] is cleared and MACSR[R/T] is set, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit fraction.

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Table 4-2. MACSR Field Descriptions (continued)

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Field Description

Enhanced Multiply-Accumulate Unit (EMAC)

2 Z

Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSA C , and load operations; it is not affected by MULS and MULU instructions.

Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions.

Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction, indicating that the result cannot be represented in the limited width of the EMAC. V is set only if a product overflow occurs or the accumulation overflows the 48-bit structure. V is ev aluated on each MAC or MSA C operation and uses the appropriate PAVn flag in the next-state V evaluation.

Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in integer mode or the 40 lsbs in fractional mode of the destination accumulator. However, the result remains accurately represented in the combined 48-bit accumulator structure. Although an overflow has occurred, the correct result, sign, and magnitude are contained in the 48-bit accumulator. Subsequent MAC or MSA C operations may return the accumulator to a valid 32/40-bit result.

Table 4-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.

Table 4-3. Summary of S/U, F/I, and R/T Control Bits

S/U F/I R/T Operational Modes

0 0 x Signed, integer 0 1 0 Signed, fractional

Truncate on MAC.L and MSAC.L No round on accumulator stores

0 1 1 Signed, fractional

Round on MAC.L and MSAC.L

Round-to-32-bits on accumulator stores 1 0 x Unsigned, integer 1 1 0 Signed, fractional

Truncate on MAC.L and MSAC.L

Round-to-16-bits on accumulator stores 1 1 1 Signed, fractional

Round on MAC.L and MSAC.L

Round-to-16-bits on accumulator stores

4.2.2 Mask Register (MASK)

The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones.

This register performs a simple AND with the operand address for MAC instructions. The processor calculates the normal operand address and, if enabled, that address is then ANDed with {0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address

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can be constrained to a certain memory region. This is used primarily to implement circular queues with the (An)+ addressing mode.

This minimizes the addressing support required for filtering, convolution, or any routine that implements a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be included in all memory effective address calculations. The syntax is as follows:

mac.sz Ry,RxSF,<ea>y&,Rw

The & operator enables the MASK use and causes bit 5 of the extension word to be set. The exact algorithm for the use of MASK is:

if extension word, bit [5] = 1, the MASK bit, then

if <ea> = (An)

oa = An & {0xFFFF, MASK}

if <ea> = (An)+

oa = An An = (An + 4) & {0xFFFF, MASK}

if <ea> =-(An)

oa = (An - 4) & {0xFFFF, MASK} An = (An - 4) & {0xFFFF, MASK}

if <ea> = (d16,An)

oa = (An + se_d16) & {0xFFFF0x, MASK}

Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For auto-addressing modes of post-increment and pre-decrement, the updated An value calculation is also shown.

Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue implementations.

BDM: 0x805 (MASK) Access: User read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

R 1 1 1 1 1 111111111 1 1

Reset11111111111111111111111111111111

Figure 4-3. Mask Register (MASK)

Table 4-4. MASK Field Descriptions

Field Description

31–16 Reserved, must be set.

15–0

MASK

Perf orms a simple AND with the operand address for MAC instructions.

MASK

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4.2.3 Accumulator Registers (ACC0–3)

The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers form the entire 48-bit result.

BDM: 0x806 (ACC0)

0x809 (ACC1) 0x80A (ACC2) 0x80B (ACC3)

313029282726252423222120191817161514131211109876543210

Reset––––––––––––––––––––––––––––––––

Accumulator

Access: User read/write

BDM read/write

Figure 4-4. Accumulator Registers (ACC0–3)

Table 4-5. ACC0–3 Field Descriptions

Field Description

31–0

Accumulator

Store 32-bits of the result of the MAC operation.

4.2.4 Accumulator Extension Registers (ACCext01, ACCext23)

Each pair of 8-bit accumulator extension fields are concatenated with the corresponding 32-bit accumulator register to form the 48-bit accumulator. For more information, see Section 4.3, “Functional

Description.”

BDM: 0x807 (ACCext01) Access: User read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

Reset––––––––––––––––––––––––––––––––

ACC0U ACC0L ACC1U ACC1L

Figure 4-5. Accumulator Extension Register (ACCext01)

Table 4-6. ACCext01 Field Descriptions

Field Description

31–24

ACC0U

23–16

ACC0L

15–8

ACC1U

7–0

ACC1L

Accumulator 0 upper extension byte

Accumulator 0 lower extension byte

Accumulator 1 upper extension byte

Accumulator 1 lower extension byte

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BDM: 0x808 (ACCext23) Access: User read/write

313029282726252423222120191817161514131211109876543210

Reset––––––––––––––––––––––––––––––––

Field Description

ACC2U ACC2L ACC3U ACC3L

Figure 4-6. Accumulator Extension Register (ACCext23)

Table 4-7. ACCext23 Field Descriptions

BDM read/write

31–24

ACC2U

23–16

ACC2L

15–8

ACC3U

7–0

ACC3L

Accumulator 2 upper extension byte

Accumulator 2 lower extension byte

Accumulator 3 upper extension byte

Accumulator 3 lower extension byte

4.3 Functional Description

The MAC speeds execution of ColdFire integer-multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC, execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early termination that the OEP normally uses if no MAC hardware is present.

The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of the product to or from the value in an accumulator . Optionally , the product may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions. Multiply-accumulate operations support 16- or 32-bit input operands in these formats:

• Signed integers

• Unsigned integers

• Signed, fixed-point, fractional numbers

The EMAC is optimized for single-cycle, pipelined 32 × 32 multiplications. For word- and longword-sized integer input operands, the low-order 40 bits of the product are formed and used with the destination accumulator. For fractional operands, the entire 64-bit product is calculated and truncated or rounded to the most-significant 40-bit result using the round-to-nearest (even) method before it is combined with the destination accumulator.

For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator.

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OperandY OperandX

Product

Extended Product

Accumulator

Extension Byte Upper [7:0]

Extension Byte Lower [7:0]

Accumulator [31:0]

OperandY

OperandX

Product

Extended Product

Accumulator

Extension Byte Upper [7:0]

Extension Byte Lower [7:0]

Accumulator [31:0]

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Figure 4-7 and Figure 4-8 show relative alignment of input operands, the full 64-bit product, the resulting

40-bit product used for accumulation, and 48-bit accumulator formats.

Figure 4-7. Fractional Alignment

Therefore, the 48-bit accumulator definition is a function of the EMAC operating mode. Given that each 48-bit accumulator is the concatenation of 16-bit accumulator extension register (ACCextn) contents and 32-bit ACCn contents, the specific definitions are:

if MACSR[6:5] == 00 /* signed integer mode */

if MACSR[6:5] == 01 or 11 /* signed fractional mode */

if MACSR[6:5] == 10 /* unsigned integer mode */

The four accumulators are represented as an array, ACCn, where n selects the register.

Freescale Semiconductor 4-9

Figure 4-8. Signed and Unsigned Integer Alignment

Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}

Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]}

Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}

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Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC instructions have an effective issue rate of 1 cycle, regardless of input operand size or type.

All arithmetic operations use register-based input operands, and summed values are stored in an accumulator. Therefore, an additional MOVE instruction is needed to store data in a general-purpose register. One new feature in EMAC instructions is the ability to choose the upper or lower word of a register as a 16-bit input operand. This is useful in filtering operations if one data register is loaded with the input data and another is loaded with the coefficient. Two 16-bit multiply accumulates can be performed without fetching additional operands between instructions by alternating word choice during calculations.

The EMAC has four accumulator registers versus the MAC’ s single accumulator. The additional registers improve the performance of some algorithms by minimizing pipeline stalls needed to store an accumulator value back to general-purpose registers. Many algorithms require multiple calculations on a given data set. By applying different accumulators to these calculations, it is often possible to store one accumulator without any stalls while performing operations involving a different destination accumulator.

The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP engines. Existing ColdFire instructions can accommodate these requirements. A MOVEM instruction can efficiently move large data blocks by generating line-sized burst references. The ability to load an operand simultaneously from memory into a register and execute a MAC instruction makes some DSP operations such as filtering and convolution more manageable.

The programming model includes a mask register (MASK), which can optionally be used to generate an operand address during MAC + MOVE instructions. The register application with auto-increment addressing mode supports efficient implementation of circular data queues for memory operands.

4.3.1 Fractional Operation Mode

This section describes behavior when the fractional mode is used (MACSR[F/I] is set).

4.3.1.1 Rounding

When the processor is in fractional mode, there are two operations during which rounding can occur:

1. Execution of a store accumulator instruction (move.l ACCx,Rx). The lsbs of the 48-bit accumulator logic are used to round the resulting 16- or 32-bit value. If MACSR[S/U] is cleared, the low-order 8 bits round the resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit fraction.

2. Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero, multiplying two 32-bit numbers creates a 64-bit product truncated to the upper 40 bits; otherwise, it is rounded using round-to-nearest (even) method.

T o understand the round-to-nearest-even method, consider the following example involving the rounding of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest 16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L.

4-10 Freescale Semiconductor

• If R0.L is less than 0x8000, the result is truncated to the value of R0.U.

• If R0.L is greater than 0x8000, the upper word is incremented (rounded up).

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• If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is based on the lsb of R0.U, so the result is always even (lsb = 0).

— If the lsb of R0.U equals 1 and R0.L equals 0x8000, the number is rounded up. — If the lsb of R0.U equals 0 and R0.L equals 0x8000, the number is rounded down.

This method minimizes rounding bias and creates as statistically correct an answer as possible. The rounding algorithm is summarized in the following pseudocode:

if R0.L < 0x8000

then Result = R0.U

else if R0.L > 0x8000

then Result = R0.U + 1

else if lsb of R0.U = 0 /* R0.L = 0x8000 */

then Result = R0.U

else Result = R0.U + 1

The round-to-nearest-even technique is also known as convergent rounding.

4.3.1.2 Saving and Restoring the EMAC Programming Model

The presence of rounding logic in the EMAC output datapath requires special care during the EMAC’s save/restore process. In particular, any result rounding modes must be disabled during the save/restore process so the exact bit-wise contents of the EMAC registers are accessed. Consider the memory structure containing the EMAC programming model:

struct macState {

int acc0; int acc1; int acc2; int acc3; int accext01; int accext02; int mask; int macsr;

} macState;

The following assembly language routine shows the proper sequence for a correct EMAC state save. This code assumes all Dn and An registers are available for use, and the memory location of the state save is defined by A7.

EMAC_state_save:

move.l macsr,d7 ; save the macsr clr.l d0 ; zero the register to ... move.l d0,macsr ; disable rounding in the macsr move.l acc0,d0 ; save the accumulators move.l acc1,d1 move.l acc2,d2 move.l acc3,d3 move.l accext01,d4 ; save the accumulator extensions move.l accext23,d5 move.l mask,d6 ; save the address mask movem.l #0x00ff,(a7) ; move the state to memory

This code performs the EMAC state restore:

EMAC_state_restore:

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movem.l (a7),#0x00ff ; restore the state from memory move.l #0,macsr ; disable rounding in the macsr move.l d0,acc0 ; restore the accumulators move.l d1,acc1 move.l d2,acc2 move.l d3,acc3 move.l d4,accext01 ; restore the accumulator extensions move.l d5,accext23 move.l d6,mask ; restore the address mask move.l d7,macsr ; restore the macsr

Executing this sequence type can correctly save and restore the exact state of the EMAC programming model.

4.3.1.3 MULS/MULU

MULS and MULU are unaffected by fractional-mode operation; operands remain assumed to be integers.

4.3.1.4 Scale Factor in MAC or MSAC Instructions

The scale factor is ignored while the MAC is in fractional mode.

4.3.2 EMAC Instruction Set Summary

Table 4-8 summarizes EMAC unit instructions.

Table 4-8. EMAC Instruction Summary

Command Mnemonic Description

Multiply Signed muls <ea>y,Dx Multiplies two signed operands yielding a signed result Multiply Unsigned mulu <ea>y,Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate mac Ry,RxSF,ACCx

msac Ry,RxSF,ACCx

Multiply Accumulate with Load

Load Accumulator move.l {Ry,#imm},ACCx Loads an accumulator with a 32-bit operand Store Accumulator move.l ACCx,Rx Writes the contents of an accumulator to a CPU register Copy Accumulator move.l ACCy,ACCx Copies a 48-bit accumulator Load MACSR move.l {Ry,#imm},MACSR Writes a value to MACSR Store MACSR move.l MACSR,Rx Write the contents of MACSR to a CPU register Store MACSR to CCR move.l MACSR,CCR Write the contents of MACSR to the CCR Load MAC Mask Reg move.l {Ry,#imm},MASK Writes a value to the MASK register

mac Ry,Rx,<ea>y,Rw,ACCx msac Ry,Rx,<ea>y,Rw,ACCx

Multiplies two operands and adds/subtracts the product to/from an accumulator

Multiplies two operands and combines the product to an accumulator while loading a register with the memory operand

Store MAC Mask Reg move.l MASK,Rx Writes the contents of the MASK to a CPU register Load Accumulator

Extensions 01

4-12 Freescale Semiconductor

move.l {Ry,#imm},ACCext01 Loads the accumulator 0,1 extension bytes with a 32-bit

operand

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DSOC

AGEX

mac

EMAC EX1

EMAC EX2

EMAC EX3 EMAC EX4

mac

move

movemove

Three-cycle

regBusy stall

Accumulator 0

old

new

mac

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Table 4-8. EMAC Instruction Summary (continued)

Command Mnemonic Description

Load Accumulator Extensions 23

Store Accumulator Extensions 01

Store Accumulator Extensions 23

move.l {Ry,#imm},ACCext23 Loads the accumulator 2,3 extension bytes with a 32-bit

operand

move.l ACCext01,Rx Writes the contents of accumulator 0,1 extension bytes into a

CPU register

move.l ACCext23,Rx Writes the contents of accumulator 2,3 extension bytes into a

CPU register

4.3.3 EMAC Instruction Execution Times

The instruction execution times for the EMAC can be found in Section 3.3.5.6, “EMAC Instruction

Execution Times”.

The EMAC execution pipeline overlaps the AGEX stage of the OEP (the first stage of the EMAC pipeline is the last stage of the basic OEP). EMAC units are designed for sustained, fully-pipelined operation on accumulator load, copy, and multiply-accumulate instructions. However, instructions that store contents of the multiply-accumulate programming model can generate OEP stalls that expose the EMAC execution pipeline depth:

mac.w Ry, Rx, Acc0 move.l Acc0, Rz

The MOVE.L instruction that stores the accumulator to an integer register (Rz) stalls until the program-visible copy of the accumulator is available. Figure 4-9 shows EMAC timing.

In Figure 4-9, the OEP stalls the store-accumulator instruction for three cycles: the EMAC pipleline depth minus 1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is performed, the recently updated accumulator 0 value is available.

Freescale Semiconductor 4-13

Figure 4-9. EMAC-Specific OEP Sequence Stall

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value 1 a

N1–

⋅()–2

i1N–+()–

ai⋅

i0=

N2–

∑

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As with change or use stalls between accumulators and general-purpose registers, introducing intervening instructions that do not reference the busy register can reduce or eliminate sequence-related store-MAC instruction stalls. A major benefit of the EMAC is the addition of three accumulators to minimize stalls caused by exchanges between accumulator(s) and general-purpose registers.

4.3.4 Data Representation

MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand type:

1. Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2 < operand < 2

(N-1)

- 1. The binary point is right of the lsb.

2. Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2N - 1. The binary point is right of the lsb.

3. Two’ s complement, signed fractional: In an N-bit number , the first bit is the sign bit. The remaining bits signify the first N-1 bits after the binary point. Given an N-bit number , a

N-1aN-2aN-3

its value is given by the equation in Equation 4-3.

(N-1)

... a2a1a0,

Eqn. 4-3

This format can represent numbers in the range -1 < operand < 1-2

(N-1)

For words and longwords, the largest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively . The largest positive word is 0x7FFF or (1 - 2 the most positive longword is 0x7FFF_FFFF or (1 - 2

-31

4.3.5 MAC Opcodes

MAC opcodes are described in the ColdFire Programmer’s Reference Manual. Remember the following:

• Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that involves the product and the accumulator.

• The overflow (V) flag is managed differently . It is set if the complete product cannot be represented as a 40-bit value (this applies to 32 × 32 integer operations only) or if the combination of the product with an accumulator cannot be represented in the given number of bits. The EMAC design includes an additional product/accumulation overflow bit for each accumulator that are treated as sticky indicators and are used to calculate the V bit on each MAC or MSAC instruction. See

Section 4.2.1, “MAC Status Register (MACSR)”.

• For the MAC design, the assembler syntax of the MAC (multiply and add to accumulator) and MSAC (multiply and subtract from accumulator) instructions does not include a reference to the single accumulator. For the EMAC, assemblers support this syntax and no explic it reference to an accumulator is interpreted as a reference to ACC0. Assemblers also support syntaxes where the destination accumulator is explicitly defined.

-15

);

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• The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is added to or subtracted from the accumulator. W ithout this operator , the product is not shifted. If the EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because a product can overflow, the following guidelines are implemented:

— For unsigned word and longword operations, a zero is shifted into the product on right shifts. — For signed, word operations, the sign bit is shifted into the product on right shifts unless the

product is zero. For signed, longword operations, the sign bit is shifted into the product unless an overflow occurs or the product is zero, in which case a zero is shifted in.

— For all left shifts, a zero is inserted into the lsb position.

The following pseudocode explains basic MAC or MSAC instruction functionality. This example is presented as a case statement covering the three basic operating modes with signed integers, unsigned integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {}, indicates a concatenation operation.

switch (MACSR[6:5]) /* MACSR[S/U, F/I] */ {

case 0: /* signed integers */

if (MACSR.OMC == 0 || MACSR.PAVn == 0)

then {

MACSR.PAVn = 0 /* select the input operands */ if (sz == word)

then {if (U/Ly == 1)

then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]}

else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]} if (U/Lx == 1)

then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}

else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]} } else {operandY[31:0] = Ry[31:0]

operandX[31:0] = Rx[31:0] }

/* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0]

/* check for product overflow */

if ((product[63:39] != 0x0000_00_0) && (product[63:39] != 0xffff_ff_1))

then { /* product overflow */

MACSR.PAVn = 1

MACSR.V = 1

if (inst == MSAC && MACSR.OMC == 1)

then if (product[63] == 1)

then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000

else if (MACSR.OMC == 1)

then /* overflowed MAC,

saturationMode enabled */

if (product[63] == 1)

then result[47:0] = 0xffff_8000_0000 else result[47:0] = 0x0000_7fff_ffff

}

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/* sign-extend to 48 bits before performing any scaling */

product[47:40] = {8{product[39]}} /* sign-extend */

/* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ {

case 0: /* no scaling specified */

break;

case 1: /* SF = “<< 1” */

product[40:0] = {product[39:0], 0} break;

case 2: /* reserved encoding */

break;

case 3: /* SF = “>> 1” */

product[39:0] = {product[39], product[39:1]} break;

}

if (MACSR.PAVn == 0)

then {if (inst == MSAC)

then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0]

}

/* check for accumulation overflow */ if (accumulationOverflow == 1)

then {MACSR.PAVn = 1

MACSR.V = 1

if (MACSR.OMC == 1)

then /* accumulation overflow,

saturationMode enabled */

if (result[47] == 1)

then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000

}

/* transfer the result to the accumulator */

ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000)

then MACSR.Z = 1 else MACSR.Z = 0

if ((ACCx[47:31] == 0x0000_0) || (ACCx[47:31] == 0xffff_1))

then MACSR.EV = 0 else MACSR.EV = 1

break;

case 1,3: /* signed fractionals */ if (MACSR.OMC == 0 || MACSR.PAVn == 0)

then {

MACSR.PAVn = 0

if (sz == word)

then {if (U/Ly == 1)

then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], 0x0000}

if (U/Lx == 1)

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then operandX[31:0] = {Rx[31:16], 0x0000}

else operandX[31:0] = {Rx[15:0], 0x0000} } else {operandY[31:0] = Ry[31:0]

operandX[31:0] = Rx[31:0]

}

/* perform the multiply */ product[63:0] = (operandY[31:0] * operandX[31:0]) << 1 /* check for product rounding */ if (MACSR.R/T == 1)

then { /* perform convergent rounding */

if (product[23:0] > 0x80_0000)

then product[63:24] = product[63:24] + 1 else if ((product[23:0] == 0x80_0000) && (product[24] == 1))

then product[63:24] = product[63:24] + 1

}

/* sign-extend to 48 bits and combine with accumulator */ /* check for the -1 * -1 overflow case */

if ((operandY[31:0] == 0x8000_0000) && (operandX[31:0] == 0x8000_0000))

then product[71:64] = 0x00 /* zero-fill */ else product[71:64] = {8{product[63]}} /* sign-extend */

if (inst == MSAC)

then result[47:0] = ACCx[47:0] - product[71:24] else result[47:0] = ACCx[47:0] + product[71:24]

/* check for accumulation overflow */ if (accumulationOverflow == 1)

then {MACSR.PAVn = 1

MACSR.V = 1 if (MACSR.OMC == 1)

then /* accumulation overflow,

saturationMode enabled */

if (result[47] == 1)

then result[47:0] = 0x007f_ffff_ff00 else result[47:0] = 0xff80_0000_0000

}

/* transfer the result to the accumulator */ ACCx[47:0] = result[47:0]

} MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000)

then MACSR.Z = 1 else MACSR.Z = 0

if ((ACCx[47:39] == 0x00_0) || (ACCx[47:39] == 0xff_1))

then MACSR.EV = 0

else MACSR.EV = 1 break; case 2: /* unsigned integers */

if (MACSR.OMC == 0 || MACSR.PAVn == 0)

then {

MACSR.PAVn = 0 /* select the input operands */ if (sz == word)

then {if (U/Ly == 1)

then operandY[31:0] = {0x0000, Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]}

if (U/Lx == 1)

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then operandX[31:0] = {0x0000, Rx[31:16]}

else operandX[31:0] = {0x0000, Rx[15:0]} } else {operandY[31:0] = Ry[31:0]

operandX[31:0] = Rx[31:0]

}

/* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0]

/* check for product overflow */ if (product[63:40] != 0x0000_00)

then { /* product overflow */

MACSR.PAVn = 1 MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1)

then result[47:0] = 0x0000_0000_0000

else if (MACSR.OMC == 1)

}

/* zero-fill to 48 bits before performing any scaling */

product[47:40] = 0 /* zero-fill upper byte */

then /* overflowed MAC,

saturationMode enabled */

result[47:0] = 0xffff_ffff_ffff

/* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ {

case 0: /* no scaling specified */

break;

case 1: /* SF = “<< 1” */

product[40:0] = {product[39:0], 0} break;

case 2: /* reserved encoding */

break;

case 3: /* SF = “>> 1” */

product[39:0] = {0, product[39:1]} break;

}

/* combine with accumulator */ if (MACSR.PAVn == 0)

then {if (inst == MSAC)

then result[47:0] = ACCx[47:0] - product[47:0]

else result[47:0] = ACCx[47:0] + product[47:0] }

/* check for accumulation overflow */ if (accumulationOverflow == 1)

then {MACSR.PAVn = 1

MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1)

then result[47:0] = 0x0000_0000_0000

else if (MACSR.OMC == 1)

then /* overflowed MAC,

saturationMode enabled */

4-18 Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

}

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available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

Enhanced Multiply-Accumulate Unit (EMAC)

result[47:0] = 0xffff_ffff_ffff

}

/* transfer the result to the accumulator */

ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000)

then MACSR.Z = 1 else MACSR.Z = 0

if (ACCx[47:32] == 0x0000)

then MACSR.EV = 0 else MACSR.EV = 1

break;

Freescale Semiconductor 4-19

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Chapter 5

ALU

CAA

CAx

DES /

CA0-CA3

File

Operand1

Result

Decode

Command

Hash

Datapath Control

AES Row

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available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

Cryptographic Acceleration Unit (CAU)

5.1 Introduction

The cryptographic acceleration unit (CAU) is a ColdFire coprocessor implementing a set of specialized operations in hardware to increase the throughput of software-based encryption and hashing functions.

5.1.1 Block Diagram

Figure 5-1 shows a simplified block diagram of the CAU.

5.1.2 Overview

The CAU supports acceleration of the following algorithms:

Freescale Semiconductor 5-1

•DES

•3DES

•AES

•MD5

Figure 5-1. Top Level CAU Block Diagram

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Cryptographic Acceleration Unit (CAU)

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•SHA-1

This selection of algorithms provides excellent support for network security standards (SSL, IPsec). Additionally , using the CAU efficiently permits the implementation of any higher level functions or modes of operation (HMAC, CBC, etc.) based on the supported algorithm.

The CAU is an instruction-level ColdFire coprocessor. The cryptographic algorithms are implemented partially in software with only functions critical to increasing performance implemented in hardware. The ColdFire coprocessor allows for efficient, fine-grained partitioning of functions between hardware and software.

• Implement the innermost round functions by using the coprocessor instructions

• Implement higher-level functions in software by using the standard ColdFire instructions

This partitioning of functions is key to minimizing size of the CAU while maintaining a high level of throughput. Using software for some functions also simplifies the CAU design. The CAU implements a set of 22 coprocessor commands that operate on a register file of eight 32-bit registers. It is tightly coupled to the ColdFire core and there is no local memory or external interface.

5.1.3 Features

The CAU includes these distinctive features:

• Supports DES, 3DES, AES, MD5, SHA-1 algorithms

• Simple, flexible programming model

5.2 Memory Map/Register Definition

The CAU only supports longword operations and register accesses. All registers support read, write, and ALU operations. However, only bits 1–0 of the CASR are writeable. Bits 31–2 of the CASR must be written as 0 for compatibility with future versions of the CAU.

Table 5-1. CAU Memory Map

Code Register

0 CAU status register (CASR) — — — — R/W 0x1000_0000 5.2.1/5-3 1 CAU accumulator (CAA) — — T a R 0x0000_0000 5.2.2/5-3 2 General purpose register 0 (CA0) C W0 A — R 0x0000_0000 5.2.3/5-4 3 General purpose register 1 (CA1) D W1 B b R 0x0000_0000 5.2.3/5-4 4 General purpose register 2 (CA2) L W2 C c R 0x0000_0000 5.2.3/5-4 5 General purpose register 3 (CA3) R W3 D d R 0x0000_0000 5.2.3/5-4

DES

AES

SHA-1

Access Reset Value Section/Page

MD5

5-2 Freescale Semiconductor

6 General purpose register 4 (CA4) — — E — R 0x0000_0000 5.2.3/5-4 7 General purpose register 5 (CA5) — — W — R 0x0000_0000 5.2.3/5-4

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

5.2.1 CAU Status Register (CASR)

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CASR contains the status and configuration for the CAU.

Cryptographic Acceleration Unit (CAU)

0x0 (CASR) Access: Read/write

code:

3130292827262524232221201918171615141312111098765432 1 0

R VER 0 000000000 0 0 0 000000000 0000

Reset000100000000000000000000000000 0 0

via CAU commands

DPE IC

Figure 5-2. CAU Status Register (CASR)

Table 5-2. CASR Field Descriptions

Field Description

31–28

VER

27–2 Reserved, must be cleared.

DPE

CAU version. Indicates CAU version 0x1 Initial CAU version (This is the value on this device) 0x2 Second version, added support for SHA-256 algorithm

DES parity error. 0 No error detected 1 DES key parity error detected

Illegal command. Indicates an illegal instruction not found in Section 5.3.3, “CAU Commands,” has been executed.

0 No illegal commands issued 1 Illegal coprocessor command issued

5.2.2 CAU Accumulator (CAA)

CAU commands use the CAU accumulator for storage of results and as an operand for the cryptographic algorithms.

Field Description

31–0 ACC

0x1 (CAA) Access: Read/write

code:

313029282726252423222120191817161514131211109876543210

Reset00000000000000000000000000000000

ACC

via CAU commands

Figure 5-3. CAU Accumulator Register (CAA)

Table 5-3. CAA Field Descriptions

Accumulator. Stores results of various CAU commands.

Freescale Semiconductor 5-3

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Cryptographic Acceleration Unit (CAU)

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5.2.3 CAU General Purpose Registers (CAn)

The six CAU general purpose registers are used in the CAU commands for storage of results and as operands for the various cryptographic algorithms.

Field Description

31–0 CAn

0x2 (CA0)

code:

0x3 (CA1) 0x4 (CA2) 0x5 (CA3) 0x6 (CA4) 0x7 (CA5)

313029282726252423222120191817161514131211109876543210

Reset00000000000000000000000000000000

Figure 5-4. CAU General Purpose Registers (CAn)

Table 5-4. CAn Field Descriptions

General purpose registers. Used by the CAU commands. Some cryptographic operations work with specific registers.

CAn

Access: Read/write

via CAU commands

5.3 Functional Description

5.3.1 Programming Model

The CAU is an instruction-level coprocessor. It has a dedicated register file, a specialized ALU, and specialized units for performing cryptographic operations. The CAU design uses a simple, flexible accumulator-based architecture. Most commands, including load and store, can specify any register in the register file. Some cryptographic operations work with specific registers.

5.3.2 Coprocessor Instructions

Operation of the CAU is controlled via standard ColdFire coprocessor load (cp0ld) and store (cp0st) instructions. The CAU has a dedicated register file accessed using these instructions. The load instruction loads CAU registers and specifies CAU operations. The store instruction stores CAU registers. The example assembler syntax for the CAU is:

cp0ld.l <ea>,<CMD> ; coprocessor load cp0st.l <ea>,<CMD> ; coprocessor store

The <ea> field specifies the source operand (operand1) for load instructions and destination (result) for store instructions. The basic ColdFire addressing modes {Rn, (An), -(An), (An)+, (d16,An)} are supported for this field. The <CMD> field is a 9-bit value that specifies the CAU command for an instruction.

Table 5-5 shows how the CAU supports a single command (STR) for store instructions and 21 commands

for the load instructions. The CAU only supports longword operations. A CAU command can be issued every clock cycle.

5-4 Freescale Semiconductor

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Cryptographic Acceleration Unit (CAU)

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5.3.3 CAU Commands

The CAU supports the commands shown in Table 5-5. All other encodings are reserved. The CASR[IC] bit is set if an undefined command is issued. A specific illegal command (ILL) is defined to allow software self-checking. Reserved commands should not be issued to ensure compatibility with future implementations.

The CMD field specifies the CAU command for the instruction.

Table 5-5. CAU Commands

Inst Type

cp0ld CNOP No Operation 0x000 — cp0ld LDR Load Reg 0x01 CAx Op1 → CAx cp0st STR Store Reg 0x02 CAx CAx → Result cp0ld ADR Add 0x03 CAx CAx + Op1 → CAx cp0ld RADR Reverse and Add 0x04 CAx CAx + ByteRev(Op1) → CAx cp0ld ADRA Add Reg to Acc 0x05 CAx CAx + CAA → CAA cp0ld XOR Exclusive Or 0x06 CAx CAx ^ Op1 → CAx cp0ld ROTL Rotate Left 0x07 CAx CAx <<< Op1 → CAx cp0ld MVRA Move Reg to Acc 0x08 CAx CAx → CAA cp0ld MVAR Move Acc to Reg 0x09 CAx CAA → CAx cp0ld AESS AES Sub Bytes 0x0A CAx SubBytes(CAx) → CAx cp0ld AESIS AES Inv Sub Bytes 0x0B CAx InvSubBytes(CAx) → CAx cp0ld AESC AES Column Op 0x0C CAx MixColumns(CAx)^Op1→ CAx cp0ld AESIC AES Inv Column Op 0x0D CAx InvMixColumns(CAx^Op1) → CAx cp0ld AESR AES Shift Rows 0x0E0 ShiftRows(CA0-CA3) → CA0-CA3

Command

Name

Description

876543210

CMD

Operation

cp0ld AESIR AES Inv Shift Rows 0x0F0 InvShiftRows(CA0-CA3)→

cp0ld cp0ld DESK DES Key Setup 0x11 0 0 CP DC DES Key Op(CA0-CA1)→CA0-CA1

cp0ld HASH Hash Function 0x12 0 HF[2:0] Hash Func(CA1-CA3)+CAA→CAA cp0ld SHS Secure Hash Shift 0x130 CAA <<< 5→ CAA,

cp0ld MDS Message Digest Shift 0x140 CA3→CAA, CAA→CA1,

cp0ld ILL Illegal Command 0x1F0 0x1→CASR[0]

Freescale Semiconductor 5-5

CA0-CA3

DESR DES Round 0x10 IP FP KS[1:0] DES Rou nd(CA0-CA3)→CA0-CA3

Key Parity Error & CP → CASR[1]

CAA

→CA0, CA0→CA1,

CA1 <<< 30

CA2→CA3, CA3→CA4

CA1

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

→CA2, CA2→CA3,

→ CA2,

Cryptographic Acceleration Unit (CAU)

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Section 5.4.2, “Assembler Equate Values,” contains a set of assembly constants used in the command

descriptions here. If supported by the assembler, macros can also be created for each instruction. The value CAx should be interpreted as any CAU register (CASR, CAA, CAn) and the <ea> field as one of the supported ColdFire addressing modes {Rn, (An), -(An), (An)+, (d16,An)}. For example, the instruction to add the value from the core register D1 to the CAU register CA0 is:

cp0ld.l %d1,#ADR+CA0 ; CA0=CA0+d1

5.3.3.1 Coprocessor No Operation (CNOP)

cp0ld.l #CNOP

The CNOP command is the coprocessor no-op defined by the ColdFire coprocessor definition for synchronization. It is not actually issued to the coprocessor from the core.

5.3.3.2 Load Register (LDR)

cp0ld.l <ea>,#LDR+CAx

The LDR command loads CAx with the source data specified by <ea>.

5.3.3.3 Store Register (STR)

cp0st.l <ea>,#STR+CAx

The STR command stores the value from CAx to the destination specified by <ea>.

5.3.3.4 Add to Register (ADR)

cp0ld.l <ea>,#ADR+CAx

The ADR command adds the source operand specified by <ea> to CAx and stores the result in CAx.

5.3.3.5 Reverse and Add to Register (RADR)

cp0ld.l <ea>,#RADR+CAx

The RADR command performs a byte reverse on the source operand specified by <ea>, adds that value to CAx, and stores the result in CAx. Table 5-6 shows an example.

Table 5-6. RADR Command Example

Operand CAx Before CAx After

0x0102_0304 0xA0B0_C0D0 0xA4B3_C2D1

5.3.3.6 Add Register to Accumulator (ADRA)

cp0ld.l #ADRA+CAx

The ADRA command adds CAx to CAA and stores the result in CAA.

5.3.3.7 Exclusive Or (XOR)

5-6 Freescale Semiconductor

cp0ld.l <ea>,#XOR+CAx

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Cryptographic Acceleration Unit (CAU)

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The XOR command performs an exclusive-or of the source operand specified by <ea> with CAx and stores the result in CAx.

5.3.3.8 Rotate Left (ROTL)

cp0ld.l <ea>,#ROTL+CAx

ROTL rotates the CAx bits to the left with the result stored back to CAx. The number of bits to rotate is the

value specified by <ea> modulo 32.

5.3.3.9 Move Register to Accumulator (MVRA)

cp0ld.l #MVRA+CAx

The MVRA command moves the value from the source register CAx to the destination register CAA.

5.3.3.10 Move Accumulator to Register (MVAR)

cp0ld.l #MVAR+CAx

The MVAR command moves the value from source register CAA to the destination register CAx.

5.3.3.11 AES Substitution (AESS)

cp0ld.l #AESS+CAx

The AESS command performs the AES byte substitution operation on CAx and stores the result back to CAx.

5.3.3.12 AES Inverse Substitution (AESIS)

cp0ld.l #AESIS+CAx

The AESIS command performs the AES inverse byte substitution operation on CAx and stores the result back to CAx.

5.3.3.13 AES Column Operation (AESC)

cp0ld.l <ea>,#AESC+CAx

The AESC command performs the AES column operation on the contents of CAx then performs an exclusive-or of that result with the source operand specified by <ea> and stores the result in CAx.

5.3.3.14 AES Inverse Column Operation (AESIC)

cp0ld.l <ea>,#AESIC+CAx

The AESIC command performs an exclusive-or operation of the source operand specified by <ea> on the contents of CAx followed by the AES inverse mix column operation on that result and stores the result back in CAx.

Freescale Semiconductor 5-7

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Cryptographic Acceleration Unit (CAU)

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5.3.3.15 AES Shift Rows (AESR)

cp0ld.l #AESR

The AESR command performs the AES shift rows operation on registers CA0, CA1, CA2, and CA3.

Table 5-7 shows an example.

Table 5-7. AESR Command Example

CA0 0x0102_0304 0x0106_0B00 CA1 0x0506_0708 0x050A_0F04 CA2 0x090A_0B0C 0x090E_0308 CA3 0x0D0E_0F00 0x0D02_070C

5.3.3.16 AES Inverse Shift Rows (AESIR)

cp0ld.l #AESIR

The AESIR command performs the AES inverse shift rows operation on registers CA0, CA1, CA2 and CA3. Table 5-8 has an example.

Table 5-8. AESIR Command Example

CA0 01060B00 01020304 CA1 050A0F04 05060708 CA2 090E0308 090A0B0C CA3 0D02070C 0D0E0F00

5.3.3.17 DES Round (DESR)

cp0ld.l #DESR+{IP}+{FP}+{KSx}

The DESR command performs a round of the DES algorithm and a key schedule update with the following source and destination designations: CA0=C, CA1=D, CA2=L, CA3=R. If the IP bit is set, DES initial permutation performs on CA2 and CA3 before the round operation. If the FP bit is set, DES final permutation (inverse initial permutation) performs on CA2 and CA3 after the round operation. The round operation uses the source values from registers CA0 and CA1 for the key addition operation. The KSx field specifies the shift for the key schedule operation to update the values in CA0 and CA1. Table 5-9 defines the specific shift function performed based on the KSx field.

Table 5-9. Key Shift Function Codes

5-8 Freescale Semiconductor

KSx

Code

0 KSL1 Left 1 1 KSL2 Left 2

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

KSx

Define

Shift Function

Freescale Semiconductor MCF52230 ColdFire, MCF52231 ColdFire, MCF52235 ColdFire, MCF52236 ColdFire, MCF52232 ColdFire Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 MCF52235 Family Configurations

1.2 Block Diagram

1.3 Part Numbers and Packaging

1.4 Features

1.4.1 V2 Core Overview

1.4.2 Integrated Debug Module

1.4.3 JTAG

1.4.4 On-Chip Memories

1.4.4.1 SRAM

1.4.4.2 Flash

1.4.5 Cryptography Acceleration Unit

1.4.6 Power Management

1.4.7 FlexCAN

1.4.8 UARTs

1.4.9 I2C Bus

1.4.10 QSPI

1.4.11 Fast ADC

1.4.13 General Purpose Timer (GPT)

1.4.14 Periodic Interrupt Timers (PIT0 and PIT1)

1.4.15 Pulse Width Modulation (PWM) Timers

1.4.16 Software Watchdog Timer

1.4.17 Phase Locked Loop (PLL)

1.4.18 Interrupt Controller (INTC0/INTC1)

1.4.19 DMA Controller

1.4.20 Reset

1.4.21 GPIO

1.4.22

1.5 Memory Map Overview

2.1 Introduction

2.2 Overview

2.3 Reset Signals

2.4 PLL and Clock Signals

2.5 Mode Selection

2.6 External Interrupt Signals

2.7 Queued Serial Peripheral Interface (QSPI)

2.8 Fast Ethernet Controller PHY Signals

2.9 I2C I/O Signals

2.10 UART Module Signals

2.11 DMA Timer Signals

2.12 ADC Signals

2.13 General Purpose Timer Signals

2.14 Pulse Width Modulator Signals

2.15 Debug Support Signals

2.16 EzPort Signal Descriptions

2.17 Power and Ground Pins

3.1 Introduction

3.1.1 Overview

3.2 Memory Map/Register Description

3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)

3.2.4 Condition Code Register (CCR)

3.2.5 Program Counter (PC)

3.2.6 Vector Base Register (VBR)

3.2.7 Status Register (SR)

3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR)

3.3 Functional Description

3.3.1 Version 2 ColdFire Microarchitecture

3.3.2 Instruction Set Architecture (ISA_A+)

3.3.3 Exception Processing Overview

3.3.3.1 Exception Stack Frame Definition

3.3.4 Processor Exceptions

3.3.4.1 Access Error Exception

3.3.4.2 Address Error Exception

3.3.4.3 Illegal Instruction Exception

3.3.4.4 Divide-By-Zero

3.3.4.5 Privilege Violation

3.3.4.6 Trace Exception

3.3.4.7 Unimplemented Line-A Opcode

3.3.4.8 Unimplemented Line-F Opcode

3.3.4.9 Debug Interrupt

3.3.4.10 RTE and Format Error Exception

3.3.4.11 TRAP Instruction Exception

3.3.4.12 Unsupported Instruction Exception

3.3.4.13 Interrupt Exception

3.3.4.14 Fault-on-Fault Halt

3.3.4.15 Reset Exception

3.3.5 Instruction Execution Timing