Freescale Semiconductor MCF52230 ColdFire, MCF52231 ColdFire, MCF52235 ColdFire, MCF52236 ColdFire, MCF52232 ColdFire Reference Manual
...
MCF52235 ColdFire® Integrated
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Microcontroller Reference Manual
Devices Supported:
MCF52230
MCF52231
MCF52232
MCF52233
MCF52234
MCF52235
MCF52236
Document Number:
MCF52235RM
Rev. 6
07/2010
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®
technology
Document Number: MCF52235RM
Rev. 6
07/2010
Chapter 1
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Overview
1.1 MCF52235 Family Configurations ............................................................................................... 1-2
1.2 Block Diagram .............................................................................................................................. 1-3
1.3 Part Numbers and Packaging ........................................................................................................ 1-3
1.4 Features ......................................................................................................................................... 1-4
1.5 Memory Map Overview .............................................................................................................. 1-14
Chapter 2
Signal Descriptions
2.1 Introduction ................................................................................................................................... 2-1
2.2 Overview ....................................................................................................................................... 2-1
2.3 Reset Signals .................................................................................................................................2-9
2.4 PLL and Clock Signals .................................................................................................................. 2-9
2.5 Mode Selection .............................................................................................................................. 2-9
2.6 External Interrupt Signals .............................................................................................................. 2-9
2.7 Queued Serial Peripheral Interface (QSPI) .................................................................................2-10
2.8 Fast Ethernet Controller PHY Signals ........................................................................................2-11
2.9 I2C I/O Signals ............................................................................................................................ 2-11
2.10 UART Module Signals ................................................................................................................ 2-12
2.11 DMA Timer Signals .................................................................................................................... 2-12
2.12 ADC Signals ................................................................................................................................ 2-12
2.13 General Purpose Timer Signals ...................................................................................................2-13
2.14 Pulse Width Modulator Signals ................................................................................................... 2-13
2.15 Debug Support Signals ................................................................................................................ 2-13
2.16 EzPort Signal Descriptions .......................................................................................................... 2-14
2.17 Power and Ground Pins ............................................................................................................... 2-15
3.1 Introduction ................................................................................................................................... 3-1
3.2 Memory Map/Register Description ............................................................................................... 3-2
3.3 Functional Description .................................................................................................................. 3-8
4.1 Introduction ................................................................................................................................... 4-1
4.2 Memory Map/Register Definition ................................................................................................. 4-3
4.3 Functional Description .................................................................................................................. 4-8
Freescale Semiconductor iii
Chapter 3
ColdFire Core
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
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Chapter 5
Cryptographic Acceleration Unit (CAU)
5.1 Introduction ................................................................................................................................... 5-1
5.2 Memory Map/Register Definition ................................................................................................. 5-2
5.3 Functional Description .................................................................................................................. 5-4
5.4 Application/Initialization Information ........................................................................................ 5-10
Chapter 6
Random Number Generator (RNG)
6.1 Introduction ................................................................................................................................... 6-1
6.2 Memory Map/Register Definition ................................................................................................. 6-2
6.3 Functional Description .................................................................................................................. 6-5
6.4 Initialization/Application Information .......................................................................................... 6-6
Chapter 7
Clock Module
7.1 Introduction ................................................................................................................................... 7-1
7.2 Features ......................................................................................................................................... 7-1
7.3 Modes of Operation ....................................................................................................................... 7-1
7.4 Low-power Mode Operation ......................................................................................................... 7-2
7.5 Block Diagram .............................................................................................................................. 7-2
7.6 Signal Descriptions ....................................................................................................................... 7-4
7.7 Memory Map and Registers .......................................................................................................... 7-5
7.8 Functional Description ................................................................................................................ 7-11
Chapter 8
Real-Time Clock
8.1 Introduction ................................................................................................................................... 8-1
8.2 Memory Map/Register Definition ................................................................................................. 8-2
8.3 Functional Description ................................................................................................................ 8-11
8.4 Initialization/Application Information ........................................................................................ 8-12
Chapter 9
Power Management
9.1 Introduction ................................................................................................................................... 9-1
9.2 Memory Map/Register Definition ................................................................................................. 9-1
9.3 IPS Bus Timeout Monitor ............................................................................................................. 9-9
9.4 Functional Description ................................................................................................................ 9-11
Chapter 10
Reset Controller Module
10.1 Introduction ................................................................................................................................. 10-1
10.2 Features ....................................................................................................................................... 10-1
10.3 Block Diagram ............................................................................................................................ 10-1
10.4 Signals ......................................................................................................................................... 10-2
iv Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
10.5 Memory Map and Registers ........................................................................................................ 10-2
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available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60
10.6 Functional Description ................................................................................................................ 10-5
Chapter 11
Static RAM (SRAM)
11.1 Introduction ................................................................................................................................. 11-1
11.2 Memory Map/Register Description ............................................................................................. 11-1
11.3 Initialization/Application Information ........................................................................................ 11-3
Chapter 12
Chip Configuration Module (CCM)
12.1 Introduction ................................................................................................................................. 12-1
12.2 External Signal Descriptions ....................................................................................................... 12-2
12.3 Memory Map/Register Definition ............................................................................................... 12-2
12.4 Functional Description ................................................................................................................ 12-5
12.5 Reset ............................................................................................................................................ 12-6
Chapter 13
System Control Module (SCM)
13.1 Introduction ................................................................................................................................. 13-1
13.2 Overview ..................................................................................................................................... 13-1
13.3 Features ....................................................................................................................................... 13-1
13.4 Memory Map and Register Definition ........................................................................................ 13-2
13.5 Register Descriptions .................................................................................................................. 13-3
13.6 Internal Bus Arbitration .............................................................................................................. 13-9
13.7 System Access Control Unit (SACU) ....................................................................................... 13-12
Chapter 14
General Purpose I/O Module
14.1 Introduction ................................................................................................................................. 14-1
14.2 Overview ..................................................................................................................................... 14-2
14.3 Features ....................................................................................................................................... 14-3
14.4 Signal Descriptions ..................................................................................................................... 14-3
14.5 Memory Map/Register Definition ............................................................................................... 14-3
14.6 Register Descriptions .................................................................................................................. 14-5
14.7 Ports Interrupts .......................................................................................................................... 14-15
Chapter 15
Interrupt Controller Module
15.1 68K/ColdFire Interrupt Architecture Overview .......................................................................... 15-1
15.2 Memory Map ............................................................................................................................... 15-4
15.3 Register Descriptions .................................................................................................................. 15-5
15.4 Low-Power Wakeup Operation ................................................................................................. 15-17
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor v
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Chapter 16
Edge Port Modules (EPORTn)
16.1 Introduction ................................................................................................................................. 16-1
16.2 Low-Power Mode Operation ....................................................................................................... 16-2
16.3 Signal Descriptions ..................................................................................................................... 16-2
16.4 Memory Map/Register Definition ............................................................................................... 16-3
Chapter 17
ColdFire Flash Module (CFM)
17.1 Introduction ................................................................................................................................. 17-1
17.2 External Signal Description ........................................................................................................ 17-3
17.3 Memory Map and Register Definition ........................................................................................ 17-3
17.4 Functional Description .............................................................................................................. 17-16
Chapter 18
Fast Ethernet Controller (FEC)
18.1 Overview ..................................................................................................................................... 18-1
18.2 Modes of Operation ..................................................................................................................... 18-1
18.3 FEC Top-Level Functional Diagram ........................................................................................... 18-2
18.4 Functional Description ................................................................................................................ 18-4
18.5 Programming Model ................................................................................................................. 18-18
18.6 Buffer Descriptors ..................................................................................................................... 18-47
Chapter 19
Ethernet Physical Transceiver (EPHY)
19.1 Introduction ................................................................................................................................. 19-1
19.2 External Signal Descriptions ....................................................................................................... 19-3
19.3 Memory Map and Register Descriptions .................................................................................... 19-5
19.4 Functional Description .............................................................................................................. 19-22
Chapter 20
DMA Controller Module
20.1 Introduction ................................................................................................................................. 20-1
20.2 DMA Transfer Overview ............................................................................................................20-3
20.3 Memory Map/Register Definition ............................................................................................... 20-3
20.4 Functional Description .............................................................................................................. 20-11
Chapter 21
EzPort
21.1 Features ....................................................................................................................................... 21-1
21.2 Modes of Operation ..................................................................................................................... 21-1
21.3 External Signal Description ........................................................................................................ 21-2
21.4 Command Definition ................................................................................................................... 21-3
21.5 Functional Description ................................................................................................................ 21-7
21.6 Initialization/Application Information ........................................................................................21-8
vi Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Chapter 22
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Programmable Interrupt Timers (PIT0–PIT1)
22.1 Introduction ................................................................................................................................. 22-1
22.2 Memory Map/Register Definition ............................................................................................... 22-2
22.3 Functional Description ................................................................................................................ 22-5
Chapter 23
General Purpose Timer Module (GPT)
23.1 Introduction ................................................................................................................................. 23-1
23.2 Features ....................................................................................................................................... 23-1
23.3 Block Diagram ............................................................................................................................ 23-2
23.4 Low-Power Mode Operation ....................................................................................................... 23-3
23.5 Signal Description ....................................................................................................................... 23-3
23.6 Memory Map and Registers ........................................................................................................ 23-3
23.7 Functional Description .............................................................................................................. 23-17
23.8 Reset .......................................................................................................................................... 23-21
23.9 Interrupts ................................................................................................................................... 23-21
Chapter 24
DMA Timers (DTIM0–DTIM3)
24.1 Introduction ................................................................................................................................. 24-1
24.2 Memory Map/Register Definition ............................................................................................... 24-3
24.3 Functional Description ................................................................................................................ 24-8
24.4 Initialization/Application Information ........................................................................................24-9
Chapter 25
Queued Serial Peripheral Interface (QSPI)
25.1 Introduction ................................................................................................................................. 25-1
25.2 External Signal Description ........................................................................................................ 25-2
25.3 Memory Map/Register Definition ............................................................................................... 25-3
25.4 Functional Description ................................................................................................................ 25-9
25.5 Initialization/Application Information ......................................................................................25-15
Chapter 26
UART Modules
26.1 Introduction ................................................................................................................................. 26-1
26.2 External Signal Description ........................................................................................................ 26-3
26.3 Memory Map/Register Definition ............................................................................................... 26-3
26.4 Functional Description .............................................................................................................. 26-16
26.5 Initialization/Application Information ......................................................................................26-26
Chapter 27
2
C Interface
I
27.1 Introduction ................................................................................................................................. 27-1
27.2 Memory Map/Register Definition ............................................................................................... 27-3
Freescale Semiconductor vii
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
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27.3 Functional Description ................................................................................................................ 27-7
27.4 Initialization/Application Information ......................................................................................27-12
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction ................................................................................................................................. 28-1
28.2 Features ....................................................................................................................................... 28-1
28.3 Block Diagram ............................................................................................................................ 28-2
28.4 Memory Map and Register Definition ........................................................................................ 28-2
28.5 Functional Description .............................................................................................................. 28-21
Chapter 29
Pulse-Width Modulation (PWM) Module
29.1 Introduction ................................................................................................................................. 29-1
29.2 Memory Map/Register Definition ............................................................................................... 29-2
29.3 Functional Description .............................................................................................................. 29-13
Chapter 30
FlexCAN
30.1 Introduction ................................................................................................................................. 30-1
30.2 External Signal Description ........................................................................................................ 30-5
30.3 Memory Map/Register Definition ............................................................................................... 30-5
30.4 Initialization/Application Information ......................................................................................30-28
Chapter 31
Debug Module
31.1 Introduction ................................................................................................................................. 31-1
31.2 Signal Descriptions ..................................................................................................................... 31-2
31.3 Memory Map/Register Definition ............................................................................................... 31-3
31.4 Functional Description .............................................................................................................. 31-17
Chapter 32
IEEE 1149.1 Test Access Port (JTAG)
32.1 Introduction ................................................................................................................................. 32-1
32.2 External Signal Description ........................................................................................................ 32-2
32.3 Memory Map/Register Definition ............................................................................................... 32-4
32.4 Functional Description ................................................................................................................ 32-6
32.5 Initialization/Application Information ......................................................................................32-10
Appendix A
Register Memory Map Quick Reference
Appendix B
Revision History
viii Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor ix
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available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Chapter 1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60
Overview
This chapter provides an overview of the major features and functional components of the MCF52235
family of microcontrollers. The MCF52235 family is a highly integrated implementation of the ColdFire®
family of reduced instruction set computing (RISC) microcontrollers that also includes the MCF52230,
MCF52231, MCF52232, MC52233, MC52234, and MCF52236. The differences between these parts are
summarized in Table 1-1. This document is written from the perspective of the MCF52235.
The MCF52235 represents a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire
microarchitecture. Featuring up to 32 Kbytes of internal SRAM and 256 Kbytes of flash memory, four
32-bit timers with DMA request capability, a 4-channel DMA controller, fast Ethernet controller, a CAN
module, an I2C™ module, 3 UARTs and a queued SPI, the MC52235 family has been designed for
general-purpose industrial control applications.
This 32-bit device is based on the Version 2 (V2) ColdFire reduced instruction set computing (RISC) core
with an enhanced multiply-accumulate unit (EMAC) and divider providing 56 Dhrystone 2.1 MIPS at a
frequency of up to 60 MHz from internal flash. On-chip modules include the following:
• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC)
• Cryptographic Acceleration Unit (CAU)
• Up to 32 Kbytes of internal SRAM
• Up to 256 Kbytes of on-chip flash memory
• Fast Ethernet Controller (FEC) with on-chip transceiver (ePHY)
• Three universal asynchronous receiver/transmitters (UARTs)
• Controller area network 2.0B (FlexCAN) module
2
• Inter-integrated circuit (I
C) bus controller
• 10- or 12-bit analog-to-digital converter (ADC)
• Queued serial peripheral interface (QSPI) module
• Four-channel, 32-bit direct memory access (DMA) controller
• Four-channel, 32-bit input capture/output compare timers with optional DMA support
• Two 16-bit periodic interrupt timers (PITs)
• Programmable software watchdog timer
• Two interrupt controllers, each capable of handling up to 63 interrupt sources (126 total)
These devices are ideal for cost-sensitive applications requiring significant control processing for
connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets
such as security , imaging, networking, gaming, and medical. This leading package of integration and high
performance allows fast time to market through easy code reuse and extensive third party tool support.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1-1
Overview
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60
To locate any published errata or updates for this document, refer to the ColdFire products website at
http://www.freescale.com/coldfire.
1.1 MCF52235 Family Configurations
Table 1-1. MCF52235 Family Configurations
Module 52230 52231 52232 52233 52234 52235 52236
Version 2 ColdFire Core with EMAC
(Enhanced Multiply-Accumulate Unit)
System Clock (MHz) 60 60 50 60 60 60 50
Performance (Dhrystone 2.1 MIPS) 56 56 46 56 56 56 46
Flash / Static RAM (SRAM) 128/32
Interrupt Controllers (INTC0/INTC1) •••••••
Fast Analog-to-Digital Converter (ADC) •••••••
Random Number Generator and Crypto
Acceleration Unit (CAU)
FlexCAN 2.0B Module — • —— ••—
Fast Ethernet Controller (FEC) with on-chip
interface (EPHY)
Four-channel Direct-Memory Access (DMA) •••••••
Software Watchdog Timer (WDT) •••••••
Programmable Interrupt Timer 2222222
Four-Channel General Purpose Timer •••••••
32-bit DMA Timers 4444444
QSPI •••••••
•••••••
128/32
Kbytes
————— • —
•••••••
Kbytes
128/32
Kbytes
256/32
Kbytes
256/32
Kbytes
256/32
Kbytes
256/32
Kbytes
UART(s) 3333333
2
C •••••••
I
Eight/Four-channel 8/16-bit PWM Timer •••••••
General Purpose I/O Module (GPIO) •••••••
Chip Configuration and Reset Controller
Module
Background Debug Mode (BDM) •••••••
JTAG - IEEE 1149.1 Test Access Port
Package 80 LQFP
1
The full debug/trace interface is availab le only on the 112- and 121-pin packages. A reduced debug interface is bonded on the
80-pin package.
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
1-2 Freescale Semiconductor
1
•••••••
•••••••
112 LQFP
80 LQFP
112 LQFP
80 LQFP 80 LQFP
112 LQFP
112 LQFP
121
MAPBGA
112 LQFP
121
MAPBGA
80 LQFP
Overview
Arbiter
Interrupt
Controller 1
UART
0
QSPI
UART
1
UART
2
I2C
DTIM0DTIM1DTIM2DTIM
3
V2 ColdFire CPU
IFP
OEP
EMAC
4 CH DMA
MUX
JTAG
TAP
To/From PADI
32 Kbytes
SRAM
(4K×16)×4
256 Kbytes
Flash
(32K×16)×4
PORTS
(GPIO)
CIM
RSTIN
RSTOUT
SDA
SCL
UTXDn
URXDn
U
RTSn
DTINn/DTOUTn
CANRX
JTAG_EN
ADCAN[7:0]
V
RHVRL
PLL
CLKGEN
Edge
Port 2
FlexCAN
EXTAL XTAL CLKOUT
RNGA
PIT1
GPT
PWM
To/From Interrupt Controller
CANTX
U
CTSn
PMM
PADI – Pin Muxing
EzPort
EzPCS
QSPI_CLK,
QSPI_CSn
PWMn
QSPI_DIN,
QSPI_DOUT
GPTn
Fast
Ethernet
Controller
(FEC)
EPHY
EPHY_RX
EPHY_TX
PIT0
Edge
Port 1
Interrupt
Controller 2
EzPQ
EzPD EzPCK
RTC
CAU
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1.2 Block Diagram
The superset device in the MCF52235 family comes in a 112-leaded quad flat package (LQFP) and a 121
pin MAPBGA. Figure 1-1 shows a top-level block diagram of the MCF52235.
1.3 Part Numbers and Packaging
Table 1-2 summarizes the features of the MCF52235 product family. Several speed/package options are
available to match cost- or performance-sensitive applications.
Freescale Semiconductor 1-3
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Figure 1-1. MCF52235 Block Diagram
Overview
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Table 1-2. Orderable Part Number Summary
Freescale Part
Number
MCF52230CAF60 MCF52230 Microcontroller 60 128 / 32 80 LQFP -40 to +85
MCF52230CAL60 MCF52230 Microcontroller 60 128 / 32 112 LQFP -40 to +85
MCF52231CAF60 MCF52231 Microcontroller, FlexCAN 60 128 / 32 80 LQFP -40 to +85
MCF52231CAL60 MCF52231 Microcontroller, FlexCAN 60 128 / 32 112 LQFP -40 to +85
MCF52232CAF50 MCF52232 Microcontroller 50 128 / 32 80 LQFP -40 to +85
MCF52232AF50 MCF52232 Microcontroller 50 128 / 32 80 LQFP 0 to +70
MCF52233CAF60 MCF52233 Microcontroller 60 256 / 32 80 LQFP -40 to +85
MCF52233CAL60 MCF52233 Microcontroller 60 256 / 32 112 LQFP -40 to +85
MCF52233CAL60A MCF52233 Microcontroller 60 256 / 32 112 LQFP -40 to +85
MCF52233CVM60 MCF52233 Microcontroller 60 256 / 32 121 MAPBGA -40 to +85
MCF52234CAL60 MCF52234 Microcontroller, FlexCAN 60 256 / 32 112 LQFP -40 to +85
MCF52234CVM60 MCF52234 Microcontroller, FlexCAN 60 256 / 32 121 MAPBGA -40 to +85
MCF52235CAL60 MCF52235 Microcontroller, FlexCAN, CA U, RNGA 60 256 / 32 112 LQFP -40 to +85
MCF52235CAL60A MCF52235 Microcontroller, FlexCAN, CA U , RNGA 60 256 / 32 112 LQFP -40 to +85
MCF52235CVM60 MCF52235 Microcontroller, FlexCAN, CAU, RNGA 60 256 / 32 121 MAPBGA -40 to +85
MCF52236CAF50 MCF52236 Microcontroller 50 256 / 32 80 LQFP -40 to +85
Description
Speed
(MHz)
Flash/SRAM
(Kbytes)
Package
Temp range
(°C)
MCF52236AF50 MCF52236 Microcontroller 50 256 / 32 80 LQFP 0 to +70
MCF52236AF50A MCF52236 Microcontroller 50 256 / 32 80 LQFP 0 to +70
1.4 Features
The MCF52235 family includes the following features:
• Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 60 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four
new instructions for improved bit processing (ISA_A+)
— Enhanced Multiply-Accumulate (EMAC) unit with 32-bit accumulator to support
16 × 16 → 32 or 32 × 32 → 32 operations
— Cryptography Acceleration Unit (CAU)
– Tightly-coupled coprocessor to accelerate software-based encryption and message digest
functions
– FIPS-140 compliant random number generator
1-4 Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
— Support for DES, 3DES, AES, MD5, and SHA-1 algorithms
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— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can
be configured into a 1- or 2-level trigger
• On-chip memories
— Up to 32 Kbytes of dual-ported SRAM on CPU internal bus, supporting core and DMA access
with standby power supply support
— Up to 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
• Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
• Fast Ethernet Controller (FEC)
Overview
— 10/100 BaseT/TX capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
• On-chip Ethernet Transceiver (EPHY)
— Digital adaptive equalization
— Supports auto-negotiation
— Baseline wander correction
— Full-/Half-duplex support in all modes
— Loopback modes
— Supports MDIO preamble suppression
— Jumbo packet
• FlexCAN 2.0B module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard Data and Remote Frames (up to 109 bits long)
– Extended Data and Remote Frames (up to 127 bits long)
– 0–8 bytes data length
Freescale Semiconductor 1-5
– Programmable bit rate up to 1 Mbit/sec
— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length
each, configurable as Rx or Tx, all supporting standard and extended messages
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Overview
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— Unused Message Buffer space can be used as general purpose RAM space
— Listen only mode capability
— Content-related addressing
— No read/write semaphores required
— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for
MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— Time stamp based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
• Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
•I2C module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
• Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
• Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
— Minimum 1.125 μs conversion time
1-6 Freescale Semiconductor
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over
low/high limit
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
— Unused analog channels can be used as digital I/O
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• Four 32-bit DMA timers
— 17-ns resolution at 60 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input capture capability with programmable trigger edge on input pin
— Output compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or output compare
— DMA trigger capability on input capture or output compare
• Four-channel general purpose timers
— 16-bit architecture
— Programmable prescaler
— Output pulse widths variable from microseconds to seconds
— Single 16-bit input pulse accumulator
— Toggle-on-overflow feature for pulse-width modulator (PWM) generation
Overview
— One dual-mode pulse accumulation channel
• Pulse-width modulation timer
— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution
— Programmable period and duty cycle
— Programmable enable/disable for each channel
— Software selectable polarity for each channel
— Period and duty cycle are double buffered. Change takes effect when the end of the current
period is reached (PWM counter reaches zero) or when the channel is disabled.
— Programmable center or left aligned outputs on individual channels
— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
— Emergency shutdown
• Real-Time Clock (RTC)
— Maintains system time-of-day clock
— Provides stopwatch and alarm interrupt functions
• Two periodic interrupt timers (PITs)
— 16-bit counter
— Selectable as free running or count down
• Software watchdog timer
Freescale Semiconductor 1-7
— 32-bit counter
— Low power mode support
• Clock Generation Features
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Overview
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— Up to 48 MHz crystal input
— On-chip PLL can generate core frequencies up to maximum 60 MHz operating frequency
— Provides clock for integrated EPHY
• Dual Interrupt Controllers (INTC0/INTC1)
— Support for multiple interrupt sources organized as follows:
– Fully-programmable interrupt sources for each peripheral
– 7 fixed-level interrupt sources
– Seven external interrupt signals
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
• DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for
16-byte (4 x 32-bit) burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)
•Reset
— Separate reset in and reset out signals
— Seven sources of reset:
– Power-on reset (POR)
– External
– Software
– Watchdog
– Loss of clock
– Loss of lock
– Low-voltage detection (LVD)
— Status flag indication of source of last reset
• Chip integration module (CIM)
— System configuration during reset
— Selects one of three clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
1-8 Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Overview
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• General purpose I/O interface
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
1.4.1 V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction
buffer . The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and
instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched
instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline
stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX)
performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a
separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the
MCF52235 core includes the enhanced multiply-accumulate (EMAC) unit for improved signal processing
capabilities. The EMAC implements a three-stage arithmetic pipeline, optimized for 16×16 bit operations,
with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned
integers, signed fractional operands, and a complete set of instructions to process these data types. The
EMAC provides support for execution of DSP operations within the context of a single processor at a
minimal hardware cost.
1.4.2 Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, access debug
information and real-time tracing capability is provided on 112-and 121-lead packages. This allows the
processor and system to be debugged at full speed without the need for costly in-circuit emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an
address mask register, a data and a data mask register, four PC registers, and one PC mask register. These
registers can be accessed through the dedicated debug serial communication channel or from the
processor’s supervisor mode programming model. The breakpoint registers can be configured to generate
triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions.
The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
The MCF52235 implements revision B+ of the ColdFire Debug Architecture.
The MCF52235’s interrupt servicing options during emulator mode allow real-time critical interrupt
service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system
continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data
(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1-9
Overview
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data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52235
includes a new debug signal, ALLPST. This signal is the logical AND of the processor status (PST[3:0])
signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 112 and 121-pin packages. However, every product
features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.4.3 JTAG
The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE
and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a
16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit
boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into
one shift register. Test logic, implemented using static logic design, is independent of the device system
logic.
The MCF52235 implementation can do the following:
• Perform boundary-scan operations to test circuit board electrical continuity
• Sample MCF52235 system pins during operation and transparently shift out the result in the
boundary scan register
• Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
1.4.4 On-Chip Memories
1.4.4.1 SRAM
The dual-ported SRAM module provides a general-purpose 16- or 32-Kbyte memory block that the
ColdFire core can access in a single cycle. The location of the memory block can be set to any 16- or
32-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data
structures and for use as the system stack. Because the SRAM module is physically connected to the
processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing
commands from the debug module.
The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal
for implementing applications with double-buffer schemes, where the processor and a DMA device
operate in alternate regions of the SRAM to maximize system performance.
1.4.4.2 Flash
The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the
processor’s high-speed local bus. The CFM is constructed with four banks of 32 K×16-bit flash arrays to
generate 256 Kbytes of 32-bit flash memory. These arrays serve as electrically erasable and
programmable, non-volatile program and data memory. The flash memory is ideal for program and data
1-10 Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Overview
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storage for single-chip applications, allowing for field reprogramming without requiring an external high
voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory
controller which supports interleaved accesses from the 2-cycle flash arrays. A backdoor mapping of the
flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for
the DMA. Flash memory may also be programmed via the EzPort, which is a serial flash programming
interface that allows the flash to be read, erased and programmed by an external controller in a format
compatible with most SPI bus flash memory chips. This allows easy device programming via Automated
Test Equipment or bulk programming tools.
1.4.5 Cryptography Acceleration Unit
The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the
CAU is a coprocessor tightly-coupled to the V2 ColdFire core that implements a set of specialized
operations to increase the throughput of software-based encryption and message digest functions,
specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms. Second, a random number generator
provides FIPS-140 compliant 32-bit values to security processing routines. Both modules supply critical
acceleration to software-based cryptographic algorithms at a minimal hardware cost.
1.4.6 Power Management
The MCF52235 incorporates several low-power modes of operation which are entered under program
control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors
the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)
monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the
LVD trip point.
1.4.7 FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts
A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific
requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of
FlexCAN has 16 message buffers.
1.4.8 UARTs
The MCF52235 has three full-duplex UARTs that function independently. The three UARTs can be
clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages,
the third UART is multiplexed with other digital I/O functions.
1.4.9 I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange
and minimizes the interconnection between devices. This bus is suitable for applications requiring
occasional communications over a short distance between many devices on a circuit board.
Freescale Semiconductor 1-11
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Overview
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1.4.10 QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with
queued transfer capability . It allows up to 16 transfers to be queued at once, mi nimizing the need for CPU
intervention between transfers.
1.4.11 Fast ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold
(S/H) circuits feeding separate 10- or 12-bit ADCs. The two separate converters store their results in
accessible buffers for further processing.
The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or
perform a programmed scan sequence repeatedly until manually stopped.
The ADC can be configured for sequential or simultaneous conversion. When configured for sequential
conversions, up to eight channels can be sampled and stored in any order specified by the channel list
register. Both ADCs may be required during a scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same
time. This configuration requires that a single channel may not be sampled by both S/H circuits
simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures
below the low threshold limit or above the high threshold limit set in the limit registers) or at several
different zero crossing conditions.
1.4.12 DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3)
on the each device. Each module incorporates a 32-bit timer with a separate register set for configuration
and control. The timers can be configured to operate from the system clock or from an external clock
source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The
input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter
register (TCRn). Each of these timers can be configured for input capture or reference (output) compare
mode. Timer events may optionally cause interrupt requests or DMA transfers.
1.4.13 General Purpose Timer (GPT)
The general purpose timer (GP T) is a 4-channel timer module consisting of a 16-bit programmable counter
driven by a 7-stage programmable prescaler . Each of the four channels can be configured for input capture
or output compare. Additionally , one of the channels, channel 3, can be configured as a pulse accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit
range of the counter. The input capture and output compare functions allow simultaneous input waveform
measurements and output waveform generation. The input capture function can capture the time of a
selected transition edge. The output compare function can generate output waveforms and timer software
delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.
1-12 Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Overview
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1.4.14 Periodic Interrupt Timers (PIT0 and PIT1)
The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular
intervals with minimal processor intervention. Each timer can count down from the value written in its PIT
modulus register or can be a free-running down-counter.
1.4.15 Pulse Width Modulation (PWM) Timers
The MCF52235 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty
cycle as well as a dedicated counter . Each of the modulators can create independent continuous waveforms
with software-selectable duty rates from 0 to 100%. The PWM outputs have programmable polarity and
can be programmed as left-aligned outputs or center-aligned outputs. For higher period and duty cycle
resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a
single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4
8-/16-bit channels.
1.4.16 Software Watchdog Timer
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter
is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown.
1.4.17 Phase Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked
loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control
logic. To improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own
power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins,
VDD and VSS.
1.4.18 Interrupt Controller (INTC0/INTC1)
There are two interrupt controllers on the MCF52235. These interrupt controllers are organized as seven
levels with up to nine interrupt sources per level. Each interrupt source has a unique interrupt vector, and
provide each peripheral with all necessary interrupts. Each internal interrupt has a programmable level
[1-7] and priority within the level. The seven external interrupts have fixed levels/priorities.
1.4.19 DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with
minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line
transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the
occurrence of certain UART or DMA timer events.
Freescale Semiconductor 1-13
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Overview
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1.4.20 Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and
keeps track of what caused the last reset. There are seven sources of reset:
• External reset input
• Power-on reset (POR)
• Watchdog timer
• Phase locked-loop (PLL) loss of lock
• PLL loss of clock
• Software
• Low-voltage detector (LVD)
Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other
registers provide status flags indicating the last source of reset and a control bit for software assertion of
the RSTO pin.
1.4.21 GPIO
Nearly all pins on the MCF52235 have general purpose I/O capability in addition to their primary
functions and are grouped into 8-bit ports. Some ports do not utilize all 8 bits. Each port has registers that
configure, monitor, and control the port pins.
1.4.22
1.5 Memory Map Overview
Table 1-3. System Memory Map
Base Address (Hex) Size Use
0x0000_0000 1G On-Chip Flash/RAM Array2
0x4000_0000 64 bytes System Control Module
0x4000_0040 64 bytes Reserved
0x4000_0080 128 bytes Reserved
0x4000_0100 16 bytes DMA (Channel 0)
0x4000_0110 16 bytes DMA (Channel 1)
0x4000_0120 16 bytes DMA (Channel 2)
0x4000_0130 16 bytes DMA (Channel 3)
0x4000_0140 196 bytes Reserved
0x4000_0200 64 bytes UART0
0x4000_0240 64 bytes UART1
1-14 Freescale Semiconductor
0x4000_0280 64 bytes UART2
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Table 1-3. System Memory Map (continued)
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Base Address (Hex) Size Use
0x4000_02c0 64 bytes Reserved
0x4000_0300 64 bytes I2C
0x4000_0340 64 bytes QSPI
0x4000_0380 64 bytes Reserved
0x4000_03C0 64 bytes RTC
0x4000_0400 64 bytes TMR0
0x4000_0440 64 bytes TMR1
0x4000_0480 64 bytes TMR2
0x4000_04c0 64 bytes TMR3
0x4000_0500 1792 bytes Reserved
0x4000_0c00 256 bytes Interrupt Cntl 0
0x4000_0d00 256 bytes Interrupt Cntl 1
0x4000_0e00 256 bytes Reserved
Overview
0x4000_0f00 256 bytes Global Interrupt Ack Cycles
0x4000_1000 1K Fast Ethernet Controller - Registers and
MIB RAM
0x4000_1400 1K Fast Ethernet Controller - FIFO Memory
0x4000_1800 1M – 6K Reserved
0x4010_0000 64K Ports
0x4011_0000 64K CIM_IBO
0x4012_0000 64K Clocks (PLLMRBI)
0x4013_0000 64K Edge Port 0
0x4014_0000 64K Edge Port 1
0x4015_0000 64K Programmable Interval Timer 0
0x4016_0000 64K Programmable Interval Timer 1
0x4017_0000 64K Reserved
0x4018_0000 64K Reserved
0x4019_0000 64K ADC
0x401a_0000 64K Timer
0x401b_0000 64K PWM
Freescale Semiconductor 1-15
0x401c_0000 64K FlexCAN2
0x401d_0000 64K CFM (Flash) control registers
0x401e_0000 64K Ethernet Physical Transceiver
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Overview
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Table 1-3. System Memory Map (continued)
Base Address (Hex) Size Use
0x401f_0000 64K Random Number Generator H/W
Accelerator
0x4020_0000 62M Reserved
0x4400_0000 256K CFM (Flash) memory for IPS reads and
writes
0x4408_0000 1G – 64M – 256K Reserved
0x8000_0000 2G Reserved
1-16 Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Chapter 2
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Signal Descriptions
2.1 Introduction
This chapter describes signals implemented on this device and includes an alphabetical listing of signals
that characterizes each signal as an input or output, defines its state at reset, and identifies whether a
pull-up resistor should be used.
NOTE
The terms ‘assertion’ and ‘negation’ are used to avoid confusion when
dealing with a mixture of active-low and active-high signals. The term
‘asserted’ indicates that a signal is active, independent of the voltage level.
The term ‘negated’ indicates that a signal is inactive.
Active-low signals, such as SRAS and TA, are indicated with an overbar.
2.2 Overview
Figure 2-1 shows the block diagram of the device with the signal interface.
Freescale Semiconductor 2-1
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Signal Descriptions
Arbiter
Interrupt
Controller 1
UART
0
QSPI
UART
1
UART
2
I2C
DTIM0DTIM1DTIM2DTIM
3
V2 ColdFire CPU
IFP
OEP
EMAC
4 CH DMA
MUX
JTAG
TAP
To/From PADI
32 Kbytes
SRAM
(4K×16)×4
256 Kbytes
Flash
(32K×16)×4
PORTS
(GPIO)
CIM
RSTIN
RSTOUT
SDA
SCL
UTXDn
URXDn
U
RTSn
DTINn/DTOUTn
CANRX
JTAG_EN
ADCAN[7:0]
V
RHVRL
PLL
CLKGEN
Edge
Port 2
FlexCAN
EXTAL XTAL CLKOUT
RNGA
PIT1
GPT
PWM
To/From Interrupt Controller
CANTX
UCTSn
PMM
PADI – Pin Muxing
EzPort
EzPCS
QSPI_CLK,
QSPI_CSn
PWMn
QSPI_DIN,
QSPI_DOUT
GPTn
Fast
Ethernet
Controller
(FEC)
EPHY
EPHY_RX
EPHY_TX
PIT0
Edge
Port 1
Interrupt
Controller 2
EzPQ
EzPD EzPCK
RTC
CAU
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Table 2-1 shows the pin functions by primary and alternate purpose, and illustrates which packages contain
each pin.
Figure 2-1. Block Diagram with Signal Interfaces
2-2 Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 2-3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60
Table 2-1. Pin Functions by Primary and Alternate Purpose
Pin Group
3
ADC
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Primary
Function
AN7 — — PAN[7] Low — — A10 88 64
AN6 — — PAN[6] Low — — B10 87 63
Secondary
Function
Tertiary
Function
Quaternary
Function
Drive
Strength/
Control
Wired OR
1
Control
Pull-up/
Pull-down
2
Pin on 121
MAPBGA
Pin on 112
LQFP
Pin on 80
LQFP
AN5 — — PAN[5] Low — — A11 86 62
AN4 — — PAN[4] Low — — B11 85 61
AN3 — — PAN[3] Low — — C9 89 65
AN2 — — PAN[2] Low — — B9 90 66
AN1 — — PAN[1] Low — — A9 91 67
AN0 — — PAN[0] Low — — C8 92 68
SYNCA CANTX
SYNCB CANRX
4
FEC_MDIO PAS[3] PDSR[39] — — K1 28 20
4
FEC_MDC PAS[2] PDSR[39] — — J1 27 19
VDDA — — — N/A N/A — A8 93 69
VSSA — — — N/A N/A — A7 96 72
VRH — — — N/A N/A — B8 94 70
VRL — — — N/A N/A — B7 95 71
Clock
Generation
EXTAL — — — N/A N/A — L7 48 36
XTAL — — — N/A N/A — J7 49 37
VDDPLL
5
— — — N/A N/A — K6 45 33
VSSPLL — — — N/A N/A — K7 47 35
Debug
Data
ALLPST — — — High — — D3 7 7
DDATA[3:0] — — PDD[7:4] High — — E1, F3,F2, F1 12,13,16,17 —
PST[3:0] — — PDD[3:0] High — — D10, D9,
80,79,78,77 —
E10, E9
Signal Descriptions
2-4 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60
Table 2-1. Pin Functions by Primary and Alternate Purpose (continued)
Signal Descriptions
Pin Group
Ethernet
LEDs
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Primary
Function
ACTLED — — PLD[0] PDSR[32] PWOR[8] — C11 84 60
COLLED — — PLD[4] PDSR[36] PWOR[12] — J9 58 42
Secondary
Function
Tertiary
Function
Quaternary
Function
Drive
Strength/
Control
Wired OR
1
Control
Pull-up/
Pull-down
2
Pin on 121
MAPBGA
Pin on 112
LQFP
Pin on 80
LQFP
DUPLED — — PLD[3] PDSR[35] PWOR[11] — J10 59 43
LNKLED — — PLD[1] PDSR[33] PWOR[9] — C10 83 59
SPDLED — — PLD[2] PDSR[34] PWOR[10] — D11 81 57
RXLED — — PLD[5] PDSR[37] PWOR[13] — H9 52 —
TXLED — — PLD[6] PDSR[38] PWOR[14] — H8 51 —
VDDR — — — — — — D8 82 58
Ethernet
PHY
PHY_RBIAS — — — — — J11 66 46
PHY_RXN — — — — — E11 74 54
PHY_RXP — — — — — F11 73 53
PHY_TXN — — — — — H11 71 51
PHY_TXP — — — — — G11 70 50
PHY_VDDA
PHY_VDDRX
PHY_VDDTX
5
5
5
——— N/A H106848
——— N/A F107555
——— N/A G106949
PHY_VSSA — — — N/A G8 67 47
PHY_VSSRX — — — N/A F9 76 56
PHY_VSSTX — — — N/A G9 72 52
I2C SCL CANTX
SDA CANRX
4
4
UTXD2 PAS[0] PDSR[0] — Pull-Up
URXD2 PAS[1] PDSR[0] — Pull-Up
6
6
A3 111 79
A2 112 80
Freescale Semiconductor 2-5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60
Table 2-1. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group
Interrupts
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Primary
Function
3
IRQ15 — — PGP[7] PSDR[47] — Pull-Up
IRQ14 — — PGP[6] PSDR[46] — Pull-Up
Secondary
Function
Tertiary
Function
Quaternary
Function
Drive
Strength/
Control
IRQ13 — — PGP[5] PSDR[45] — Pull-Up
IRQ12 — — PGP[4] PSDR[44] — Pull-Up
Continued
Interrupts
IRQ11 — — PGP[3] PSDR[43] — Pull-Up
3
IRQ10 — — PGP[2] PSDR[42] — Pull-Up
IRQ9 — — PGP[1] PSDR[41] — Pull-Up
Wired OR
1
Control
Pull-up/
Pull-down
2
6
6
6
6
6
6
6
Pin on 121
MAPBGA
Pin on 112
LQFP
A4 106 —
A5 105 —
A6 98 —
C7 97 —
K9 57 41
L1 29 —
E2 11 —
Pin on 80
LQFP
IRQ8 — — PGP[0] PSDR[40] — Pull-Up E3 10 —
IRQ7 — — PNQ[7] Low — Pull-Up
IRQ6 — FEC_RXER PNQ[6] Low — Pull-Up
IRQ5 — FEC_RXD[1] PNQ[5] Low — Pull-Up
IRQ4 — — PNQ[4] Low — Pull-Up
IRQ3 — FEC_RXD[2] PNQ[3] Low — Pull-Up
IRQ2 — FEC_RXD[3] PNQ[2] Low — Pull-Up
IRQ1 SYNCA PWM1 PNQ[1] High — Pull-Up
6
6
6
6
6
6
6
L9 56 40
G3 19 —
G2 20 —
L5 41 29
L8 53 —
K8 54 —
J8 55 39
JTAG/BDM JTAG_EN — — — N/A N/A Pull-Down G4 18 12
TCLK/
CLKOUT — — High — Pull-Up
7
A1 1 1
PSTCLK
TDI/DSI — — — N/A N/A Pull-Up
7
C3 4 4
TDO/DSO — — — High N/A — C2 5 5
TMS/BKPT — — — N/A N/A Pull-Up
7
B1 2 2
TRST/DSCLK — — — N/A N/A Pull-Up C1 6 6
Mode
RCON/EZPCS — — — N/A N/A Pull-Up B2 3 3
Selection
Signal Descriptions
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