Freescale Semiconductor MCF52210, MCF52212, MCF52213, MCF52211 User Manual

MCF52211 ColdFire® Integrated
Microcontroller Reference Manual
Devices Supported:
MCF52210 MCF52211 MCF52212 MCF52213
Document Number: MCF52211RM
Rev. 2
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© Freescale Semiconductor, Inc. 2007. All rights reserved.
MCF52211RM Rev. 2 09/2007
Chapter 1
Overview
1.1 MCF52211 Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Part Numbers and Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.1 V2 Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.2 Integrated Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.3 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.2.4 On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.6 USB On-The-Go Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.7 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2.8 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2.9 QSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2.10 Fast ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2.11 DMA Timers (DTIM0–DTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.2.12 General Purpose Timer (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.13 Periodic Interrupt Timers (PIT0 and PIT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.14 Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.15 Pulse-Width Modulation (PWM) Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.16 Software Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.17 Backup Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.18 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.19 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.20 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.21 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.22 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Chapter 2
Signal Descriptions
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.5 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.6 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.7 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.8 Queued Serial Peripheral Interface (QSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.9 I
2.10 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.11 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
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C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
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2.14 Pulse-Width Modulator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.15 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Chapter 3
ColdFire Core
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.6 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.7 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR) . . . . . . . . . . . . . . . . . . . . 3-8
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.3.1 Version 2 ColdFire Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.3.2 Instruction Set Architecture (ISA_A+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.3.3 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.3.4 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.3.5 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Chapter 4
Multiply-Accumulate Unit (MAC)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.1 MAC Status Register (MACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.2 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.3 Accumulator Register (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.3.2 MAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.3.3 MAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.3.4 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.3.5 MAC Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Chapter 5
Static RAM (SRAM)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
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5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2.1 SRAM Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3.1 SRAM Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Chapter 6
Clock Module
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.3.1 Backup Watchdog Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.3.2 RTC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.3.3 Normal PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.3.4 1:1 PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.3.5 External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.4 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.6 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.1 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.2 XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.3 CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.4 CLKMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.5 RSTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.7.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.8.1 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.8.2 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.8.3 System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.8.4 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Chapter 7
Backup Watchdog Timer (BWT) Module
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
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Chapter 8
Power Management
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2.1 Peripheral Power Management Registers (PPMRH, PPMRL) . . . . . . . . . . . . . . . . . . . 8-2
8.2.2 Low-Power Interrupt Control Register (LPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.2.3 Peripheral Power Management Set Register (PPMRS) . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.2.4 Peripheral Power Management Clear Register (PPMRC) . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.2.5 Low-Power Control Register (LPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.3 IPS Bus Timeout Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.4.1 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.4.2 Peripheral Behavior in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.4.3 Summary of Peripheral State During Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . 8-15
Chapter 9
Chip Configuration Module (CCM)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.1 RCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.2 CLKMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.3 JTAG_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.4 TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3.1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Chapter 10
Reset Controller Module
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.4 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.4.1 RSTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.4.2 RSTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.5 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.5.1 Reset Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.5.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.6.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.6.2 Reset Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
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10.6.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Chapter 11
Real-Time Clock
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.3.1 Prescaler and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.3.2 Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.3.3 Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.4.1 Flow Chart of RTC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.4.2 Code Example for Initializing the Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Chapter 12
System Control Module (SCM)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.5.1 Internal Peripheral System Base Address Register (IPSBAR) . . . . . . . . . . . . . . . . . . 12-3
12.5.2 Memory Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.5.3 Core Reset Status Register (CRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.5.4 Core Watchdog Control Register (CWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.5.5 Core Watchdog Service Register (CWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6 Internal Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.6.2 Arbitration Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.6.3 Bus Master Park Register (MPARK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.7 System Access Control Unit (SACU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.7.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Chapter 13
General Purpose I/O Module
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
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13.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.5 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.5.1 Ports Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.6 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.6.1 Port Output Data Registers (PORTn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.6.2 Port Data Direction Registers (DDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.6.3 Port Pin Data/Set Data Registers (PORTnP/SETn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.6.4 Port Clear Output Data Registers (CLRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.6.5 Pin Assignment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.6.6 Pad Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.7 Ports Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
Chapter 14
Interrupt Controller Module
14.1 68K/ColdFire Interrupt Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1.1 Interrupt Controller Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.3.1 Interrupt Pending Registers (IPRHn, IPRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.3.2 Interrupt Mask Register (IMRHn, IMRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.3.4 Interrupt Request Level Register (IRLRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
14.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) . . . . . . . . . . . . . . 14-10
14.3.6 Interrupt Control Registers (ICRnx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
14.3.7 Software and Level m IACK Registers (SWIACKn, LmIACKn) . . . . . . . . . . . . . . . 14-15
14.3.8 Global Level m IACK Registers (GLmIACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.4 Low-Power Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
Chapter 15
Universal Serial Bus, OTG Capable Controller
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.1 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.2 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.1.3 USB-FS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.2.1 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.3 Programmers Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.3.1 Buffer Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.3.2 Rx vs. Tx as a USB Target Device or USB Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.3.3 Addressing Buffer Descriptor Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.3.4 Buffer Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.3.5 USB Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.4 Memory Map/Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.4.1 Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
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15.5 OTG and Host Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33
15.6 Host Mode Operation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34
15.7 On-The-Go Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-36
15.7.1 OTG Dual Role A Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-36
15.7.2 OTG Dual Role B Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
15.7.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39
15.7.4 USB Suspend State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40
Chapter 16
Edge Port Module (EPORT)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.3 Interrupt/GPIO Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.4.1 EPORT Pin Assignment Register (EPPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.4.2 EPORT Data Direction Register (EPDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.4.3 Edge Port Interrupt Enable Register (EPIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.4.4 Edge Port Data Register (EPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.4.5 Edge Port Pin Data Register (EPPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.4.6 Edge Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Chapter 17
DMA Controller Module
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2 DMA Transfer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3.1 DMA Request Control (DMAREQC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.3.2 Source Address Registers (SARn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.3.3 Destination Address Registers (DARn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.3.4 Byte Count Registers (BCRn) and DMA Status Registers (DSRn) . . . . . . . . . . . . . . 17-6
17.3.5 DMA Control Registers (DCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.4.1 Transfer Requests (Cycle-Steal and Continuous Modes) . . . . . . . . . . . . . . . . . . . . . 17-12
17.4.2 Dual-Address Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.4.3 Channel Initialization and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.4.4 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
17.4.5 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
Chapter 18
ColdFire Flash Module (CFM)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
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18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3.2 Flash Base Address Register (FLASHBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16
18.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16
18.4.2 Flash Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17
18.4.3 Flash Security Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30
Chapter 19
EzPort
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.3.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.4 Command Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.4.1 Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
Chapter 20
Programmable Interrupt Timers (PIT0–PIT1)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.3 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.2.1 PIT Control and Status Register (PCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.2.2 PIT Modulus Register (PMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.2.3 PIT Count Register (PCNTRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.3.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.3.2 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
20.3.3 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
20.3.4 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Chapter 21
General Purpose Timer Module (GPT)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
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21.4 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.5.1 GPT[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.5.2 GPT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.5.3 SYNCn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.6.1 GPT Input Capture/Output Compare Select Register (GPTIOS) . . . . . . . . . . . . . . . . . 21-5
21.6.2 GPT Compare Force Register (GPCFORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.6.3 GPT Output Compare 3 Mask Register (GPTOC3M) . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.6.4 GPT Output Compare 3 Data Register (GPTOC3D) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.6.5 GPT Counter Register (GPTCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.6.6 GPT System Control Register 1 (GPTSCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.6.7 GPT Toggle-On-Overflow Register (GPTTOV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.6.8 GPT Control Register 1 (GPTCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
21.6.9 GPT Control Register 2 (GPTCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
21.6.10GPT Interrupt Enable Register (GPTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
21.6.11GPT System Control Register 2 (GPTSCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.6.12GPT Flag Register 1 (GPTFLG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12
21.6.13GPT Flag Register 2 (GPTFLG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12
21.6.14GPT Channel Registers (GPTCn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
21.6.15Pulse Accumulator Control Register (GPTPACTL) . . . . . . . . . . . . . . . . . . . . . . . . . 21-13
21.6.16Pulse Accumulator Flag Register (GPTPAFLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14
21.6.17Pulse Accumulator Counter Register (GPTPACNT) . . . . . . . . . . . . . . . . . . . . . . . . . 21-15
21.6.18GPT Port Data Register (GPTPORT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16
21.6.19GPT Port Data Direction Register (GPTDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16
21.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16
21.7.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17
21.7.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17
21.7.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17
21.7.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
21.7.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
21.7.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
21.7.7 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19
21.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.9.1 GPT Channel Interrupts (CnF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.9.2 Pulse Accumulator Overflow (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.9.3 Pulse Accumulator Input (PAIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22
21.9.4 Timer Overflow (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22
Chapter 22
DMA Timers (DTIM0–DTIM3)
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
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22.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.2.1 DMA Timer Mode Registers (DTMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.2.2 DMA Timer Extended Mode Registers (DTXMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.3 DMA Timer Event Registers (DTERn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.2.4 DMA Timer Reference Registers (DTRRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.2.5 DMA Timer Capture Registers (DTCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.2.6 DMA Timer Counters (DTCNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.3.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.3.2 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.3.3 Reference Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.3.4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
22.4.1 Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
22.4.2 Calculating Time-Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10
Chapter 23
Queued Serial Peripheral Interface (QSPI)
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.3.1 QSPI Mode Register (QMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.3.2 QSPI Delay Register (QDLYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.3.3 QSPI Wrap Register (QWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.3.4 QSPI Interrupt Register (QIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.3.5 QSPI Address Register (QAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.3.6 QSPI Data Register (QDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.3.7 Command RAM Registers (QCR0–QCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.4.1 QSPI RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11
23.4.2 Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12
23.4.3 Transfer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.4.4 Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14
23.4.5 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14
23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15
Chapter 24
UART Modules
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
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24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.1 UART Mode Registers 1 (UMR1n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3.2 UART Mode Register 2 (UMR2n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.3.3 UART Status Registers (USRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
24.3.4 UART Clock Select Registers (UCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.5 UART Command Registers (UCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.6 UART Receive Buffers (URBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
24.3.7 UART Transmit Buffers (UTBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.3.8 UART Input Port Change Registers (UIPCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.3.9 UART Auxiliary Control Register (UACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13
24.3.10UART Interrupt Status/Mask Registers (UISRn/UIMRn) . . . . . . . . . . . . . . . . . . . . . 24-13
24.3.11UART Baud Rate Generator Registers (UBG1n/UBG2n) . . . . . . . . . . . . . . . . . . . . . 24-15
24.3.12UART Input Port Register (UIPn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15
24.3.13UART Output Port Command Registers (UOP1n/UOP0n) . . . . . . . . . . . . . . . . . . . . 24-16
24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16
24.4.1 Transmitter/Receiver Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16
24.4.2 Transmitter and Receiver Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18
24.4.3 Looping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22
24.4.4 Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24
24.4.5 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26
24.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26
24.5.1 Interrupt and DMA Request Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26
24.5.2 UART Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28
Chapter 25
2
C Interface
I
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
25.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
25.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.2.1 I
25.2.2 I2C Frequency Divider Registers (I2FDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.2.3 I2C Control Registers (I2CRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.2.4 I2C Status Registers (I2SRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
25.2.5 I
25.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.3.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.3.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.3.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
25.3.5 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
25.3.6 Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
2
C Address Registers (I2ADRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
2
C Data I/O Registers (I2DRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
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25.3.7 Clock Synchronization and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
25.3.8 Handshaking and Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
25.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
25.4.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
25.4.2 Generation of START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
25.4.3 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
25.4.4 Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
25.4.5 Generation of Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.4.6 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.4.7 Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
Chapter 26
Analog-to-Digital Converter (ADC)
26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
26.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.4.1 Control 1 Register (CTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
26.4.2 Control 2 Register (CTRL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
26.4.3 Zero Crossing Control Register (ADZCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8
26.4.4 Channel List 1 and 2 Registers (ADLST1 and ADLST2) . . . . . . . . . . . . . . . . . . . . . . 26-8
26.4.5 Sample Disable Register (ADSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10
26.4.6 Status Register (ADSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11
26.4.7 Limit Status Register (ADLSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13
26.4.8 Zero Crossing Status Register (ADZCSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14
26.4.9 Result Registers (ADRSLTn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14
26.4.10Low and High Limit Registers (ADLLMTn and ADHLMTn) . . . . . . . . . . . . . . . . . 26-15
26.4.11Offset Registers (ADOFSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17
26.4.12Power Control Register (POWER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17
26.4.13Voltage Reference Register (CAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-20
26.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21
26.5.1 Input MUX Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23
26.5.2 ADC Sample Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-25
26.5.3 ADC Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27
26.5.4 Sequential vs. Parallel Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28
26.5.5 Scan Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-29
26.5.6 Scan Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30
26.5.7 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-32
26.5.8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-32
26.5.9 ADC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-34
26.5.10Voltage Reference Pins VREFH and VREFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-37
26.5.11Supply Pins VDDA and VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-38
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Chapter 27
Pulse-Width Modulation (PWM) Module
27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
27.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
27.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.2.1 PWM Enable Register (PWME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.2.2 PWM Polarity Register (PWMPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4
27.2.3 PWM Clock Select Register (PWMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4
27.2.4 PWM Prescale Clock Select Register (PWMPRCLK) . . . . . . . . . . . . . . . . . . . . . . . . 27-5
27.2.5 PWM Center Align Enable Register (PWMCAE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.2.6 PWM Control Register (PWMCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
27.2.7 PWM Scale A Register (PWMSCLA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.2.8 PWM Scale B Register (PWMSCLB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9
27.2.9 PWM Channel Counter Registers (PWMCNTn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9
27.2.10PWM Channel Period Registers (PWMPERn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10
27.2.11PWM Channel Duty Registers (PWMDTYn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11
27.2.12PWM Shutdown Register (PWMSDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12
27.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13
27.3.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13
27.3.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-15
Chapter 28
Debug Module
28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2
28.3 Real-Time Trace Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
28.3.1 Begin Execution of Taken Branch (PST = 0x5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
28.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6
28.4.1 Shared Debug Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7
28.4.2 Configuration/Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7
28.4.3 BDM Address Attribute Register (BAAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10
28.4.4 Address Attribute Trigger Register (AATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10
28.4.5 Trigger Definition Register (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12
28.4.6 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) . . . . . . . . . . . . . . . 28-15
28.4.7 Address Breakpoint Registers (ABLR, ABHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17
28.4.8 Data Breakpoint and Mask Registers (DBR, DBMR) . . . . . . . . . . . . . . . . . . . . . . . . 28-18
28.5 Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19
28.5.1 CPU Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19
28.5.2 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20
28.5.3 BDM Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-22
28.6 Real-Time Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39
28.6.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39
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28.6.2 Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-41
28.7 Processor Status, Debug Data Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42
28.7.1 User Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42
28.7.2 Supervisor Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47
28.8 Freescale-Recommended BDM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47
Chapter 29
IEEE 1149.1 Test Access Port (JTAG)
29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
29.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
29.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.2.1 JTAG Enable (JTAG_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.2.2 Test Clock Input (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.2.3 Test Mode Select/Breakpoint (TMS/BKPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.2.4 Test Data Input/Development Serial Input (TDI/DSI) . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.2.5 Test Reset/Development Serial Clock (TRST/DSCLK) . . . . . . . . . . . . . . . . . . . . . . . 29-4
29.2.6 Test Data Output/Development Serial Output (TDO/DSO) . . . . . . . . . . . . . . . . . . . . 29-4
29.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
29.3.1 Instruction Shift Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
29.3.2 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
29.3.3 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
29.3.4 JTAG_CFM_CLKDIV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
29.3.5 TEST_CTRL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
29.3.6 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6
29.4.1 JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6
29.4.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6
29.4.3 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7
29.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10
29.5.1 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10
29.5.2 Nonscan Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10
B.1 Changes between Rev. 1 and Rev. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1
B.2 Changes between Rev. 0 and Rev. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
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Chapter 1 Overview

This chapter provides an overview of the major features and functional components of the MCF52211 family of microcontrollers. The MCF52211 family is a highly integrated implementation of the ColdFire® family of reduced instruction set computing (RISC) microcontrollers that also includes the MCF52210, MCF52212, and MCF52213. The differences between these parts are summarized in Table 1-1. This document is written from the perspective of the MCF52211.
The MCF52211 represents a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire microarchitecture. Featuring up to 16 Kbytes of internal SRAM and up to 128 Kbytes of flash memory, four 32-bit timers with DMA request capability , a 4-channel DMA controller , two I2C™ modules, up to 3 UAR T s and a queued SPI, the MCF5221 1 family has been designed for general-purpose industrial control applications.
This 32-bit device is based on the Version 2 (V2) ColdFire reduced instruction set computing (RISC) core with a multiply-accumulate unit (MAC) and divider providing 76 Dhrystone 2.1 MIPS at a frequency up to 80 MHz from internal flash. On-chip modules include the following:
V2 ColdFire core with multiply-accumulate unit (MAC)
Up to 16 Kbytes of internal SRAM
Up to 128 Kbytes of on-chip flash memory
Universal Serial Bus On-The-Go (USB OTG) full speed/low speed host and device controller
Up to three universal asynchronous receiver/transmitters (UARTs)
Two inter-integrated circuit (I2C) bus controllers
12-bit analog-to-digital converter (ADC)
Real-time clock
Queued serial peripheral interface (QSPI) module
Four-channel, 32-bit direct memory access (DMA) controller
Four-channel, 32-bit general purpose timers with optional DMA support
Two 16-bit periodic interrupt timers (PITs)
Programmable software watchdog timer
Backup watchdog timer
Interrupt controller capable of handling up to 63 interrupt sources
Clock module with 8 MHz on-chip relaxation oscillator and integrated phase-locked loop (PLL)
To locate any published errata or updates for this document, refer to the ColdFire products website at
http://www.freescale.com/coldfire.
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Overview

1.1 MCF52211 Family Configurations

Table 1-1. MCF52211 Family Configurations
Module 52210 52211 52212 52213
Version 2 ColdFire Core with MAC (Multiply-Accumulate Unit)
System Clock 66, 80 MHz 50 MHz
Performance (Dhrystone 2.1 MIPS) up to 76 up to 46
Flash / Static RAM (SRAM) 64/16 Kbytes 128/16 Kbytes 64/8 Kbytes 128/8 Kbytes
Interrupt Controller (INTC)
Fast Analog-to-Digital Converter (ADC)
USB On-The-Go (USB OTG)
Four-channel Direct-Memory Access (DMA)
Software Watchdog Timer (WDT)
Secondary Watchdog Timer
Two-channel Periodic Interrupt Timer (PIT) 2 2 2 2
Four-Channel General Purpose Timer (GPT)
32-bit DMA Timers 4 4 4 4
QSPI
UART(s) 2 3 2 2
••••
••••
••••
••••
••••
••••
••••
••••
••••
I2C2222
Eight/Four-channel 8/16-bit PWM Timer
General Purpose I/O Module (GPIO)
Chip Configuration and Reset Controller Module
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port
Package 64 LQFP/QFN
1
The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on smaller
packages.
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1
••••
••••
••••
••••
••••
81 MAPBGA
64 LQFP/QFN
81 MAPBGA
100 LQFP
64 LQFP 64 LQFP
Arbiter
Interrupt
Controller
UART
0
QSPI
UART
1
UART
2
I2C
V2 ColdFire CPU
4 CH
JTAG
TAP
16 Kbytes
SRAM
(2K×32)×2
128 Kbytes
Flash
(16K×16)×4
PORTS
CIM_IBO
RSTI RSTO
ADC
AN[7:0]
PLL OCO
CLKGEN
Edge
Port
TIM
EXTAL XTAL CLKOUT
PIT0 PIT1 PWM
IRQ[7:1]
PMM
V
STBY
PADI – Pin Muxing
AN
Slave Mode Access
(CIM_IBO/EzPort)
M3
TMS
TDI
TDO TRST TCLK
JTAG_EN
DMA
M2 M0
Watch
Dog
TMR
0
RTC
TMR
1
TMR
2
TMR
3
I
2
C
DDATA
QSPI SDAn SCLn UTXDn URXDn URTS
n
UCTSn PWMn DTINn/DTOUTn GPT RCON_B ALLPST PST
BDM
PORT
IPS Bus Gasket
Watchdog
CIM_IBO
CFM
V
PP
CLKMOD
GPT[3:0]
Backup
USB
On-The-Go
USB TCVR
USBD+
USBD-
M1
Overview

1.2 Block Diagram

The superset device in the MCF52211 family comes in a 100-lead leaded quad flat package (LQFP).
Figure 1-1 shows a top-level block diagram of the MCF52211.

1.3 Part Numbers and Packaging

Table 1-2 summarizes the features of the MCF52211 product family. Several speed/package options are
available to match cost- or performance-sensitive applications.
Figure 1-1. MCF52211 Block Diagram
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Overview
Table 1-2. Orderable Part Number Summary
Freescale Part
Number
MCF52210CAE66 MCF52210 Microcontroller, 2 UARTs 66 64 / 16 64 LQFP -40 to +85
MCF52210CEP66 MCF52210 Microcontroller, 2 UARTs 66 64 / 16 64 QFN -40 to +85
MCF52210CVM66 MCF52210 Microcontroller, 2 UARTs 66 64 / 16 81 MAPBGA -40 to +85
MCF52210CVM80 MCF52210 Microcontroller, 2 UARTs 80 64 / 16 81 MAPBGA -40 to +85
MCF52211CAE66 MCF52211 Microcontroller, 3 UARTs 66 128 / 16 64 LQFP -40 to +85
MCF52211CAF80 MCF52211 Microcontroller, 3 UARTs 80 128 / 16 100 LQFP -40 to +85
MCF52211CEP66 MCF52211 Microcontroller, 3 UARTs 66 128 / 16 64 QFN -40 to +85
MCF52211CVM66 MCF52211 Microcontroller, 3 UARTs 66 128 / 16 81 MAPBGA -40 to +85
MCF52211CVM80 MCF52211 Microcontroller, 3 UARTs 80 128 / 16 81 MAPBGA -40 to +85
MCF52212CAE50 MCF52212 Microcontroller, 2 UARTs 50 64 / 8 64 LQFP -40 to +85
MCF52212AE50 MCF52212 Microcontroller, 2 UARTs 50 64 / 8 64 LQFP 0 to +70
MCF52213CAE50 MCF52213 Microcontroller, 2 UARTs 50 128 / 8 64 LQFP -40 to +85
MCF52213AE50 MCF52213 Microcontroller, 2 UARTs 50 128 / 8 64 LQFP 0 to +70
Description
Speed
(MHz)
Flash/SRAM
(Kbytes)
Package
Tem p rang e
(°C)

1.2 Features

The MCF52211 family includes the following features:
Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data paths on-chip — Up to 80 MHz processor core frequency — 40 MHz and 33 MHz off-platform bus frequency — Sixteen general-purpose, 32-bit data and address registers — Implements ColdFire ISA_A with extensions to support the user stack pointer register and four
new instructions for improved bit processing (ISA_A+)
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16×16 32 or
32×32 32 operations
System debug support — Real-time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging (DEBUG_B+) — Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data)
configurable into a 1- or 2-level trigger
On-chip memories
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— Up to 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access
with standby power supply support
— Up to 128 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management — Fully static operation with processor sleep and whole chip stop modes — Rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used (except backup watchdog timer) — Software controlled disable of external clock output for low-power consumption
Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller — Full-speed / low-speed host controller — USB 1.1 and 2.0 compliant full-speed / low speed device controller — 16 bidirectional end points — DMA or FIFO data stream interfaces — Low power consumption — OTG protocol logic
Three universal asynchronous/synchronous receiver transmitters (UARTs)
Overview
— 16-bit divider for clock generation — Interrupt control logic with maskable interrupts — DMA support — Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity — Up to two stop bits in 1/16 increments — Error-detection capabilities — Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs — Transmit and receive FIFO buffers
•Two I2C modules — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
2
— Fully compatible with industry-standard I
C bus — Master and slave modes support multiple masters — Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to four chip selects available — Master mode operation only — Programmable bit rates up to half the CPU clock frequency — Up to 16 pre-programmed transfers
Fast analog-to-digital converter (ADC) — Eight analog input channels
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— 12-bit resolution — Minimum 1.125 μs conversion time — Simultaneous sampling of two channels for motor control applications — Single-scan or continuous operation — Optional interrupts on conversion complete, zero crossing (sign change), or under/over
low/high limit
— Unused analog channels can be used as digital I/O
Four 32-bit timers with DMA support — 12.5 ns resolution at 80 MHz — Programmable sources for clock input, including an external clock option — Programmable prescaler — Input capture capability with programmable trigger edge on input pin — Output compare with programmable mode for the output pin — Free run and restart modes — Maskable interrupts on input capture or output compare — DMA trigger capability on input capture or output compare
Four-channel general purpose timer — 16-bit architecture — Programmable prescaler — Output pulse-widths variable from microseconds to seconds — Single 16-bit input pulse accumulator — Toggle-on-overflow feature for pulse-width modulator (PWM) generation — One dual-mode pulse accumulation channel
Pulse-width modulation timer — Support for PCM mode (resulting in superior signal quality compared to conventional PWM) — Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution — Programmable period and duty cycle — Programmable enable/disable for each channel — Software selectable polarity for each channel — Period and duty cycle are double buffered. Change takes effect when the end of the current
period is reached (PWM counter reaches zero) or when the channel is disabled. — Programmable center or left aligned outputs on individual channels — Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies — Emergency shutdown
Two periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down
Real-Time Clock (RTC)
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— Maintains system time-of-day clock — Provides stopwatch and alarm interrupt functions
Software watchdog timer — 32-bit counter — Low-power mode support
Backup watchdog timer (BWT) — Independent timer that can be used to help software recover from runaway code — 16-bit counter — Low-power mode support
Clock generation features — One to 48 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference
options — Trimmed relaxation oscillator — Two to 10 MHz reference frequency for normal PLL mode with a pre-divider programmable
from 1 to 8 — System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator
Overview
— Low power modes supported —2n (n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation
Interrupt controller — Uniquely programmable vectors for all interrupt sources — Fully programmable level and priority for all peripheral interrupt sources — Seven external interrupt signals with fixed level and priority — Unique vector number for each interrupt source — Ability to mask any individual interrupt source or all interrupt sources (global mask-all) — Support for hardware and software interrupt acknowledge (IACK) cycles — Combinatorial path to provide wake-up from low-power modes
DMA controller — Four fully programmable channels — Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for
16-byte (4×32-bit) burst transfers — Source/destination address pointers that can increment or remain constant — 24-bit byte transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle steal support — Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)
•Reset — Separate reset in and reset out signals — Seven sources of reset:
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Overview
– Power-on reset (POR) – External – Software – Watchdog – Loss of clock / loss of lock – Low-voltage detection (LVD) –JTAG
— Status flag indication of source of last reset
Chip integration module (CIM) — System configuration during reset — Selects one of six clock modes — Configures output pad drive strength — Unique part identification number and part revision number
General purpose I/O interface — Up to 56 bits of general purpose I/O — Bit manipulation supported via set/clear functions — Programmable drive strengths — Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing

1.2.1 V2 Core Overview

The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer . The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the core includes the multiply-accumulate (MAC) unit for improved signal processing capabilities. The MAC implements a three-stage arithmetic pipeline, optimized for 16×16 bit operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The MAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.

1.2.2 Integrated Debug Module

The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator development tools. Through a standard debug interface, access to debug information and
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Overview
real-time tracing capability is provided on 100-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. The MCF52211 implements revision B+ of the ColdFire Debug Architecture.
The MCF52211’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event. This ensure s the system continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52211 includes a new debug signal, ALLPST. This signal is the logical AND of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 100-pin packages. However, every product features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.

1.2.3 JTAG

The MCF52211 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic.
The MCF52211 implementation can:
Perform boundary-scan operations to test circuit board electrical continuity
Sample boundary scan register
Bypass the MCF52211 for a given circuit board test by effectively reducing the boundary-scan register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
MCF52211 system pins during operation and transparently shift out the result in the
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Overview

1.2.4 On-Chip Memories

1.2.4.1 SRAM
The dual-ported SRAM module provides a general-purpose 8- or 16-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 8- or 16-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module.
The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance.
1.2.4.2 Flash Memory
The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local bus. The CFM is constructed with up to four banks of 16-Kbyte×16-bit flash memory arrays to generate up to 128 Kbytes of 32-bit flash memory. These electrically erasable and programmable arrays serve as non-volatile program and data memory. The flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort, which is a serial flash memory programming interface that allows the flash memory to be read, erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips.

1.2.5 Power Management

The MCF52211 incorporates several low-power modes of operation entered under program control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the L VD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip falls below the standby battery voltage.

1.2.6 USB On-The-Go Controller

The MCF52211 includes a Universal Serial Bus On-The-Go (USB OTG) dual-mode controller. USB is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and handheld computers to host PCs. The OTG supplement to the USB specification extends USB to peer-to-peer application, enabling devices to connect directly to each other without the need for a PC. The dual-mode controller on the MCF52211 can act as a USB OTG host and as a USB device. It also supports full-speed and low-speed modes.
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1.2.7 UARTs

The MCF52211 has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions.

1.2.8 I2C Bus

The MCF52211 includes two I2C modules. The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices.

1.2.9 QSPI

The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability . It allows up to 16 transfers to be queued at once, mi nimizing the need for CPU intervention between transfers.

1.2.10 Fast ADC

The fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.
The ADC can be configured to perform a single scan and halt, a scan when triggered, or a programmed scan sequence repeatedly until manually stopped.
The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.
1.2.11 DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the MCF52211. Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler that clocks the actual timer counter
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register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers.

1.2.12 General Purpose Timer (GPT)

The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a seven-stage programmable prescaler . Each of the four channels can be configured for input capture or output compare. Additionally, channel three, can be configured as a pulse accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.

1.2.13 Periodic Interrupt Timers (PIT0 and PIT1)

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. Each timer can count down from the value written in its PIT modulus register or it can be a free-running down-counter.

1.2.14 Real-Time Clock (RTC)

The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch, alarm, and interrupt functions. It includes full clock features: seconds, minutes, hours, days and supports a host of time-of-day interrupt functions along with an alarm interrupt.

1.2.15 Pulse-Width Modulation (PWM) Timers

The MCF52211 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated counter . Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The timer supports PCM mode, which results in superior signal quality when compared to that of a conventional PWM. The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.

1.2.16 Software Watchdog Timer

The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.
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1.2.17 Backup Watchdog Timer

The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer, facilitates recovery from runaway code. This timer is a free-running down-counter that generates a reset on underflow . T o prevent a reset, software must periodically restart the countdown. The backup watchdog timer can be clocked by either the relaxation oscillator or the system clock.

1.2.18 Phase-Locked Loop (PLL)

The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS.

1.2.19 Interrupt Controller (INTC)

The MCF52211 has a single interrupt controller that supports up to 63 interrupt sources. There are 56 programmable sources, 49 of which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for software interrupt requests.

1.2.20 DMA Controller

The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.

1.2.21 Reset

The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last reset. There are seven sources of reset:
External reset input
Power-on reset (POR)
Watchdog timer
Phase locked-loop (PLL) loss of lock / loss of clock
Software
Low-voltage detector (LVD)
•JTAG
Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO pin.
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1.2.22 GPIO

Nearly all pins on the MCF52211 have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins.
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