Freescale Semiconductor MCF52210, MCF52212, MCF52213, MCF52211 User Manual

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MCF52211 ColdFire® Integrated

Microcontroller Reference Manual

Devices Supported:

MCF52210 MCF52211 MCF52212 MCF52213

Document Number: MCF52211RM

Rev. 2

09/2007

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Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical exper ts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semico nductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semicondu ctor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.

MCF52211RM Rev. 2 09/2007

Chapter 1

Overview

1.1 MCF52211 Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 Part Numbers and Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2.1 V2 Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.2.2 Integrated Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.2.3 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.2.4 On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.2.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.2.6 USB On-The-Go Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.2.7 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.2.8 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.2.9 QSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.2.10 Fast ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.2.11 DMA Timers (DTIM0–DTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.2.12 General Purpose Timer (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.2.13 Periodic Interrupt Timers (PIT0 and PIT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.2.14 Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.2.15 Pulse-Width Modulation (PWM) Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.2.16 Software Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.2.17 Backup Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.2.18 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.2.19 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.2.20 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.2.21 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.2.22 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Chapter 2

Signal Descriptions

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.3 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.4 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.5 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.6 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.7 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.8 Queued Serial Peripheral Interface (QSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.9 I

2.10 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.11 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Freescale Semiconductor i

C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

2.14 Pulse-Width Modulator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.15 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Chapter 3

ColdFire Core

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.2.6 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.2.7 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR) . . . . . . . . . . . . . . . . . . . . 3-8

3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.3.1 Version 2 ColdFire Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.3.2 Instruction Set Architecture (ISA_A+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.3.3 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.3.4 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.3.5 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

Chapter 4

Multiply-Accumulate Unit (MAC)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2.1 MAC Status Register (MACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2.2 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.2.3 Accumulator Register (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.3.2 MAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.3.3 MAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.3.4 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.3.5 MAC Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Chapter 5

Static RAM (SRAM)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor ii

5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2.1 SRAM Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3.1 SRAM Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Chapter 6

Clock Module

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.3.1 Backup Watchdog Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.3.2 RTC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.3.3 Normal PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.3.4 1:1 PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.3.5 External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.4 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.6 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.6.1 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.6.2 XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.6.3 CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.6.4 CLKMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.6.5 RSTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.7.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

6.8.1 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

6.8.2 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

6.8.3 System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

6.8.4 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

Chapter 7

Backup Watchdog Timer (BWT) Module

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

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Chapter 8

Power Management

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2.1 Peripheral Power Management Registers (PPMRH, PPMRL) . . . . . . . . . . . . . . . . . . . 8-2

8.2.2 Low-Power Interrupt Control Register (LPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.2.3 Peripheral Power Management Set Register (PPMRS) . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.2.4 Peripheral Power Management Clear Register (PPMRC) . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.2.5 Low-Power Control Register (LPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.3 IPS Bus Timeout Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.4.1 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.4.2 Peripheral Behavior in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.4.3 Summary of Peripheral State During Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . 8-15

Chapter 9

Chip Configuration Module (CCM)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2.1 RCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2.2 CLKMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2.3 JTAG_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2.4 TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.3.1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.3.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

Chapter 10

Reset Controller Module

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.4 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.4.1 RSTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.4.2 RSTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.5 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.5.1 Reset Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.5.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.6.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.6.2 Reset Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

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10.6.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

Chapter 11

Real-Time Clock

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

11.3.1 Prescaler and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

11.3.2 Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14

11.3.3 Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14

11.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14

11.4.1 Flow Chart of RTC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14

11.4.2 Code Example for Initializing the Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . 11-15

Chapter 12

System Control Module (SCM)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.5.1 Internal Peripheral System Base Address Register (IPSBAR) . . . . . . . . . . . . . . . . . . 12-3

12.5.2 Memory Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.5.3 Core Reset Status Register (CRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6

12.5.4 Core Watchdog Control Register (CWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7

12.5.5 Core Watchdog Service Register (CWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.6 Internal Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

12.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

12.6.2 Arbitration Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.6.3 Bus Master Park Register (MPARK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.7 System Access Control Unit (SACU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.7.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

Chapter 13

General Purpose I/O Module

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

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13.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.5 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.5.1 Ports Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.6 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.6.1 Port Output Data Registers (PORTn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.6.2 Port Data Direction Registers (DDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.6.3 Port Pin Data/Set Data Registers (PORTnP/SETn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7

13.6.4 Port Clear Output Data Registers (CLRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9

13.6.5 Pin Assignment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

13.6.6 Pad Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13

13.7 Ports Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15

Chapter 14

Interrupt Controller Module

14.1 68K/ColdFire Interrupt Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.1.1 Interrupt Controller Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5

14.3.1 Interrupt Pending Registers (IPRHn, IPRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

14.3.2 Interrupt Mask Register (IMRHn, IMRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

14.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

14.3.4 Interrupt Request Level Register (IRLRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10

14.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) . . . . . . . . . . . . . . 14-10

14.3.6 Interrupt Control Registers (ICRnx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11

14.3.7 Software and Level m IACK Registers (SWIACKn, LmIACKn) . . . . . . . . . . . . . . . 14-15

14.3.8 Global Level m IACK Registers (GLmIACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16

14.4 Low-Power Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16

Chapter 15

Universal Serial Bus, OTG Capable Controller

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.1.1 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.1.2 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

15.1.3 USB-FS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.2.1 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.3 Programmers Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.3.1 Buffer Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.3.2 Rx vs. Tx as a USB Target Device or USB Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

15.3.3 Addressing Buffer Descriptor Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

15.3.4 Buffer Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

15.3.5 USB Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

15.4 Memory Map/Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9

15.4.1 Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10

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15.5 OTG and Host Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33

15.6 Host Mode Operation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34

15.7 On-The-Go Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-36

15.7.1 OTG Dual Role A Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-36

15.7.2 OTG Dual Role B Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38

15.7.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39

15.7.4 USB Suspend State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40

Chapter 16

Edge Port Module (EPORT)

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1

16.2 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.3 Interrupt/GPIO Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.4.1 EPORT Pin Assignment Register (EPPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.4.2 EPORT Data Direction Register (EPDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.4.3 Edge Port Interrupt Enable Register (EPIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.4.4 Edge Port Data Register (EPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

16.4.5 Edge Port Pin Data Register (EPPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

16.4.6 Edge Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

Chapter 17

DMA Controller Module

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.2 DMA Transfer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

17.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

17.3.1 DMA Request Control (DMAREQC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.3.2 Source Address Registers (SARn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5

17.3.3 Destination Address Registers (DARn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5

17.3.4 Byte Count Registers (BCRn) and DMA Status Registers (DSRn) . . . . . . . . . . . . . . 17-6

17.3.5 DMA Control Registers (DCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11

17.4.1 Transfer Requests (Cycle-Steal and Continuous Modes) . . . . . . . . . . . . . . . . . . . . . 17-12

17.4.2 Dual-Address Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12

17.4.3 Channel Initialization and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13

17.4.4 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14

17.4.5 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15

Chapter 18

ColdFire Flash Module (CFM)

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

18.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

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18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.3.2 Flash Base Address Register (FLASHBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

18.3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16

18.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16

18.4.2 Flash Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17

18.4.3 Flash Security Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30

Chapter 19

EzPort

19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

19.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

19.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.3.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.4 Command Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

19.4.1 Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7

19.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8

Chapter 20

Programmable Interrupt Timers (PIT0–PIT1)

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

20.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

20.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

20.1.3 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

20.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2

20.2.1 PIT Control and Status Register (PCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

20.2.2 PIT Modulus Register (PMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4

20.2.3 PIT Count Register (PCNTRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.3.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.3.2 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

20.3.3 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

20.3.4 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

Chapter 21

General Purpose Timer Module (GPT)

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1

21.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1

21.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2

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21.4 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

21.5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

21.5.1 GPT[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

21.5.2 GPT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

21.5.3 SYNCn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4

21.6 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4

21.6.1 GPT Input Capture/Output Compare Select Register (GPTIOS) . . . . . . . . . . . . . . . . . 21-5

21.6.2 GPT Compare Force Register (GPCFORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6

21.6.3 GPT Output Compare 3 Mask Register (GPTOC3M) . . . . . . . . . . . . . . . . . . . . . . . . . 21-6

21.6.4 GPT Output Compare 3 Data Register (GPTOC3D) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7

21.6.5 GPT Counter Register (GPTCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7

21.6.6 GPT System Control Register 1 (GPTSCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8

21.6.7 GPT Toggle-On-Overflow Register (GPTTOV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9

21.6.8 GPT Control Register 1 (GPTCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9

21.6.9 GPT Control Register 2 (GPTCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10

21.6.10GPT Interrupt Enable Register (GPTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10

21.6.11GPT System Control Register 2 (GPTSCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11

21.6.12GPT Flag Register 1 (GPTFLG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12

21.6.13GPT Flag Register 2 (GPTFLG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12

21.6.14GPT Channel Registers (GPTCn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13

21.6.15Pulse Accumulator Control Register (GPTPACTL) . . . . . . . . . . . . . . . . . . . . . . . . . 21-13

21.6.16Pulse Accumulator Flag Register (GPTPAFLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14

21.6.17Pulse Accumulator Counter Register (GPTPACNT) . . . . . . . . . . . . . . . . . . . . . . . . . 21-15

21.6.18GPT Port Data Register (GPTPORT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16

21.6.19GPT Port Data Direction Register (GPTDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16

21.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16

21.7.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17

21.7.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17

21.7.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17

21.7.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18

21.7.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18

21.7.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18

21.7.7 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19

21.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21

21.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21

21.9.1 GPT Channel Interrupts (CnF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21

21.9.2 Pulse Accumulator Overflow (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21

21.9.3 Pulse Accumulator Input (PAIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22

21.9.4 Timer Overflow (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22

Chapter 22

DMA Timers (DTIM0–DTIM3)

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1

22.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1

22.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

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22.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2

22.2.1 DMA Timer Mode Registers (DTMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3

22.2.2 DMA Timer Extended Mode Registers (DTXMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4

22.2.3 DMA Timer Event Registers (DTERn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5

22.2.4 DMA Timer Reference Registers (DTRRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6

22.2.5 DMA Timer Capture Registers (DTCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7

22.2.6 DMA Timer Counters (DTCNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7

22.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

22.3.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

22.3.2 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

22.3.3 Reference Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

22.3.4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

22.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9

22.4.1 Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9

22.4.2 Calculating Time-Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10

Chapter 23

Queued Serial Peripheral Interface (QSPI)

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1

23.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1

23.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

23.3.1 QSPI Mode Register (QMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

23.3.2 QSPI Delay Register (QDLYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5

23.3.3 QSPI Wrap Register (QWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6

23.3.4 QSPI Interrupt Register (QIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6

23.3.5 QSPI Address Register (QAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7

23.3.6 QSPI Data Register (QDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8

23.3.7 Command RAM Registers (QCR0–QCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8

23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9

23.4.1 QSPI RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11

23.4.2 Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12

23.4.3 Transfer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13

23.4.4 Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14

23.4.5 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14

23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15

Chapter 24

UART Modules

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1

24.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1

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24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2

24.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

24.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

24.3.1 UART Mode Registers 1 (UMR1n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5

24.3.2 UART Mode Register 2 (UMR2n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6

24.3.3 UART Status Registers (USRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7

24.3.4 UART Clock Select Registers (UCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9

24.3.5 UART Command Registers (UCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9

24.3.6 UART Receive Buffers (URBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11

24.3.7 UART Transmit Buffers (UTBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12

24.3.8 UART Input Port Change Registers (UIPCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12

24.3.9 UART Auxiliary Control Register (UACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13

24.3.10UART Interrupt Status/Mask Registers (UISRn/UIMRn) . . . . . . . . . . . . . . . . . . . . . 24-13

24.3.11UART Baud Rate Generator Registers (UBG1n/UBG2n) . . . . . . . . . . . . . . . . . . . . . 24-15

24.3.12UART Input Port Register (UIPn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15

24.3.13UART Output Port Command Registers (UOP1n/UOP0n) . . . . . . . . . . . . . . . . . . . . 24-16

24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16

24.4.1 Transmitter/Receiver Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16

24.4.2 Transmitter and Receiver Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18

24.4.3 Looping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22

24.4.4 Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24

24.4.5 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

24.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

24.5.1 Interrupt and DMA Request Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

24.5.2 UART Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28

Chapter 25

C Interface

25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1

25.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

25.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

25.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

25.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3

25.2.1 I

25.2.2 I2C Frequency Divider Registers (I2FDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4

25.2.3 I2C Control Registers (I2CRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.2.4 I2C Status Registers (I2SRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7

25.2.5 I

25.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

25.3.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

25.3.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9

25.3.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9

25.3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10

25.3.5 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10

25.3.6 Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10

C Address Registers (I2ADRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4

C Data I/O Registers (I2DRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

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25.3.7 Clock Synchronization and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12

25.3.8 Handshaking and Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

25.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

25.4.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

25.4.2 Generation of START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

25.4.3 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.4.4 Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.4.5 Generation of Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15

25.4.6 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15

25.4.7 Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15

Chapter 26

Analog-to-Digital Converter (ADC)

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1

26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1

26.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

26.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

26.4.1 Control 1 Register (CTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3

26.4.2 Control 2 Register (CTRL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5

26.4.3 Zero Crossing Control Register (ADZCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8

26.4.4 Channel List 1 and 2 Registers (ADLST1 and ADLST2) . . . . . . . . . . . . . . . . . . . . . . 26-8

26.4.5 Sample Disable Register (ADSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10

26.4.6 Status Register (ADSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11

26.4.7 Limit Status Register (ADLSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13

26.4.8 Zero Crossing Status Register (ADZCSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14

26.4.9 Result Registers (ADRSLTn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14

26.4.10Low and High Limit Registers (ADLLMTn and ADHLMTn) . . . . . . . . . . . . . . . . . 26-15

26.4.11Offset Registers (ADOFSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17

26.4.12Power Control Register (POWER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17

26.4.13Voltage Reference Register (CAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-20

26.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21

26.5.1 Input MUX Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23

26.5.2 ADC Sample Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-25

26.5.3 ADC Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27

26.5.4 Sequential vs. Parallel Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28

26.5.5 Scan Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-29

26.5.6 Scan Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30

26.5.7 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-32

26.5.8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-32

26.5.9 ADC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-34

26.5.10Voltage Reference Pins VREFH and VREFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-37

26.5.11Supply Pins VDDA and VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-38

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Chapter 27

Pulse-Width Modulation (PWM) Module

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1

27.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1

27.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2

27.2.1 PWM Enable Register (PWME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3

27.2.2 PWM Polarity Register (PWMPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4

27.2.3 PWM Clock Select Register (PWMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4

27.2.4 PWM Prescale Clock Select Register (PWMPRCLK) . . . . . . . . . . . . . . . . . . . . . . . . 27-5

27.2.5 PWM Center Align Enable Register (PWMCAE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6

27.2.6 PWM Control Register (PWMCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7

27.2.7 PWM Scale A Register (PWMSCLA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8

27.2.8 PWM Scale B Register (PWMSCLB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9

27.2.9 PWM Channel Counter Registers (PWMCNTn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9

27.2.10PWM Channel Period Registers (PWMPERn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10

27.2.11PWM Channel Duty Registers (PWMDTYn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11

27.2.12PWM Shutdown Register (PWMSDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12

27.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13

27.3.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13

27.3.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-15

Chapter 28

Debug Module

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1

28.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1

28.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1

28.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2

28.3 Real-Time Trace Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3

28.3.1 Begin Execution of Taken Branch (PST = 0x5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5

28.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6

28.4.1 Shared Debug Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7

28.4.2 Configuration/Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7

28.4.3 BDM Address Attribute Register (BAAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10

28.4.4 Address Attribute Trigger Register (AATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10

28.4.5 Trigger Definition Register (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12

28.4.6 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) . . . . . . . . . . . . . . . 28-15

28.4.7 Address Breakpoint Registers (ABLR, ABHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17

28.4.8 Data Breakpoint and Mask Registers (DBR, DBMR) . . . . . . . . . . . . . . . . . . . . . . . . 28-18

28.5 Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19

28.5.1 CPU Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-19

28.5.2 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-20

28.5.3 BDM Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-22

28.6 Real-Time Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39

28.6.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-39

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28.6.2 Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-41

28.7 Processor Status, Debug Data Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42

28.7.1 User Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42

28.7.2 Supervisor Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47

28.8 Freescale-Recommended BDM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47

Chapter 29

IEEE 1149.1 Test Access Port (JTAG)

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1

29.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1

29.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2

29.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2

29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2

29.2.1 JTAG Enable (JTAG_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2

29.2.2 Test Clock Input (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3

29.2.3 Test Mode Select/Breakpoint (TMS/BKPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3

29.2.4 Test Data Input/Development Serial Input (TDI/DSI) . . . . . . . . . . . . . . . . . . . . . . . . . 29-3

29.2.5 Test Reset/Development Serial Clock (TRST/DSCLK) . . . . . . . . . . . . . . . . . . . . . . . 29-4

29.2.6 Test Data Output/Development Serial Output (TDO/DSO) . . . . . . . . . . . . . . . . . . . . 29-4

29.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

29.3.1 Instruction Shift Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

29.3.2 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4

29.3.3 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.3.4 JTAG_CFM_CLKDIV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.3.5 TEST_CTRL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.3.6 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5

29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6

29.4.1 JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6

29.4.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6

29.4.3 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7

29.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10

29.5.1 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10

29.5.2 Nonscan Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10

B.1 Changes between Rev. 1 and Rev. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1

B.2 Changes between Rev. 0 and Rev. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2

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Chapter 1 Overview

This chapter provides an overview of the major features and functional components of the MCF52211 family of microcontrollers. The MCF52211 family is a highly integrated implementation of the ColdFire® family of reduced instruction set computing (RISC) microcontrollers that also includes the MCF52210, MCF52212, and MCF52213. The differences between these parts are summarized in Table 1-1. This document is written from the perspective of the MCF52211.

The MCF52211 represents a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire microarchitecture. Featuring up to 16 Kbytes of internal SRAM and up to 128 Kbytes of flash memory, four 32-bit timers with DMA request capability , a 4-channel DMA controller , two I2C™ modules, up to 3 UAR T s and a queued SPI, the MCF5221 1 family has been designed for general-purpose industrial control applications.

This 32-bit device is based on the Version 2 (V2) ColdFire reduced instruction set computing (RISC) core with a multiply-accumulate unit (MAC) and divider providing 76 Dhrystone 2.1 MIPS at a frequency up to 80 MHz from internal flash. On-chip modules include the following:

• V2 ColdFire core with multiply-accumulate unit (MAC)

• Up to 16 Kbytes of internal SRAM

• Up to 128 Kbytes of on-chip flash memory

• Universal Serial Bus On-The-Go (USB OTG) full speed/low speed host and device controller

• Up to three universal asynchronous receiver/transmitters (UARTs)

• Two inter-integrated circuit (I2C) bus controllers

• 12-bit analog-to-digital converter (ADC)

• Real-time clock

• Queued serial peripheral interface (QSPI) module

• Four-channel, 32-bit direct memory access (DMA) controller

• Four-channel, 32-bit general purpose timers with optional DMA support

• Two 16-bit periodic interrupt timers (PITs)

• Programmable software watchdog timer

• Backup watchdog timer

• Interrupt controller capable of handling up to 63 interrupt sources

• Clock module with 8 MHz on-chip relaxation oscillator and integrated phase-locked loop (PLL)

To locate any published errata or updates for this document, refer to the ColdFire products website at

http://www.freescale.com/coldfire.

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1.1 MCF52211 Family Configurations

Table 1-1. MCF52211 Family Configurations

Module 52210 52211 52212 52213

Version 2 ColdFire Core with MAC (Multiply-Accumulate Unit)

System Clock 66, 80 MHz 50 MHz

Performance (Dhrystone 2.1 MIPS) up to 76 up to 46

Flash / Static RAM (SRAM) 64/16 Kbytes 128/16 Kbytes 64/8 Kbytes 128/8 Kbytes

Interrupt Controller (INTC)

Fast Analog-to-Digital Converter (ADC)

USB On-The-Go (USB OTG)

Four-channel Direct-Memory Access (DMA)

Software Watchdog Timer (WDT)

Secondary Watchdog Timer

Two-channel Periodic Interrupt Timer (PIT) 2 2 2 2

Four-Channel General Purpose Timer (GPT)

32-bit DMA Timers 4 4 4 4

QSPI

UART(s) 2 3 2 2

••••

I2C2222

Eight/Four-channel 8/16-bit PWM Timer

General Purpose I/O Module (GPIO)

Chip Configuration and Reset Controller Module

Background Debug Mode (BDM)

JTAG - IEEE 1149.1 Test Access Port

Package 64 LQFP/QFN

The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on smaller

packages.

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••••

81 MAPBGA

64 LQFP/QFN

81 MAPBGA

100 LQFP

64 LQFP 64 LQFP

Arbiter

Interrupt

Controller

UART

QSPI

UART

I2C

V2 ColdFire CPU

4 CH

JTAG

TAP

16 Kbytes

SRAM

(2K×32)×2

128 Kbytes

Flash

(16K×16)×4

PORTS

CIM_IBO

RSTI RSTO

ADC

AN[7:0]

PLL OCO

CLKGEN

Edge

Port

TIM

EXTAL XTAL CLKOUT

PIT0 PIT1 PWM

IRQ[7:1]

PMM

STBY

PADI – Pin Muxing

Slave Mode Access

(CIM_IBO/EzPort)

TMS

TDI

TDO TRST TCLK

JTAG_EN

DMA

M2 M0

Watch

Dog

TMR

RTC

TMR

DDATA

QSPI SDAn SCLn UTXDn URXDn URTS

UCTSn PWMn DTINn/DTOUTn GPT RCON_B ALLPST PST

BDM

PORT

IPS Bus Gasket

Watchdog

CIM_IBO

CFM

CLKMOD

GPT[3:0]

Backup

USB

On-The-Go

USB TCVR

USBD+

USBD-

Overview

1.2 Block Diagram

The superset device in the MCF52211 family comes in a 100-lead leaded quad flat package (LQFP).

Figure 1-1 shows a top-level block diagram of the MCF52211.

1.3 Part Numbers and Packaging

Table 1-2 summarizes the features of the MCF52211 product family. Several speed/package options are

available to match cost- or performance-sensitive applications.

Figure 1-1. MCF52211 Block Diagram

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Table 1-2. Orderable Part Number Summary

Freescale Part

Number

MCF52210CAE66 MCF52210 Microcontroller, 2 UARTs 66 64 / 16 64 LQFP -40 to +85

MCF52210CEP66 MCF52210 Microcontroller, 2 UARTs 66 64 / 16 64 QFN -40 to +85

MCF52210CVM66 MCF52210 Microcontroller, 2 UARTs 66 64 / 16 81 MAPBGA -40 to +85

MCF52210CVM80 MCF52210 Microcontroller, 2 UARTs 80 64 / 16 81 MAPBGA -40 to +85

MCF52211CAE66 MCF52211 Microcontroller, 3 UARTs 66 128 / 16 64 LQFP -40 to +85

MCF52211CAF80 MCF52211 Microcontroller, 3 UARTs 80 128 / 16 100 LQFP -40 to +85

MCF52211CEP66 MCF52211 Microcontroller, 3 UARTs 66 128 / 16 64 QFN -40 to +85

MCF52211CVM66 MCF52211 Microcontroller, 3 UARTs 66 128 / 16 81 MAPBGA -40 to +85

MCF52211CVM80 MCF52211 Microcontroller, 3 UARTs 80 128 / 16 81 MAPBGA -40 to +85

MCF52212CAE50 MCF52212 Microcontroller, 2 UARTs 50 64 / 8 64 LQFP -40 to +85

MCF52212AE50 MCF52212 Microcontroller, 2 UARTs 50 64 / 8 64 LQFP 0 to +70

MCF52213CAE50 MCF52213 Microcontroller, 2 UARTs 50 128 / 8 64 LQFP -40 to +85

MCF52213AE50 MCF52213 Microcontroller, 2 UARTs 50 128 / 8 64 LQFP 0 to +70

Description

Speed

(MHz)

Flash/SRAM

(Kbytes)

Package

Tem p rang e

(°C)

1.2 Features

The MCF52211 family includes the following features:

• Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data paths on-chip — Up to 80 MHz processor core frequency — 40 MHz and 33 MHz off-platform bus frequency — Sixteen general-purpose, 32-bit data and address registers — Implements ColdFire ISA_A with extensions to support the user stack pointer register and four

new instructions for improved bit processing (ISA_A+)

— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16×16 → 32 or

32×32 → 32 operations

• System debug support — Real-time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging (DEBUG_B+) — Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data)

configurable into a 1- or 2-level trigger

• On-chip memories

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— Up to 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access

with standby power supply support

— Up to 128 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses

• Power management — Fully static operation with processor sleep and whole chip stop modes — Rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used (except backup watchdog timer) — Software controlled disable of external clock output for low-power consumption

• Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller — Full-speed / low-speed host controller — USB 1.1 and 2.0 compliant full-speed / low speed device controller — 16 bidirectional end points — DMA or FIFO data stream interfaces — Low power consumption — OTG protocol logic

• Three universal asynchronous/synchronous receiver transmitters (UARTs)

Overview

— 16-bit divider for clock generation — Interrupt control logic with maskable interrupts — DMA support — Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity — Up to two stop bits in 1/16 increments — Error-detection capabilities — Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs — Transmit and receive FIFO buffers

•Two I2C modules — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads

— Fully compatible with industry-standard I

C bus — Master and slave modes support multiple masters — Automatic interrupt generation with programmable level

• Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to four chip selects available — Master mode operation only — Programmable bit rates up to half the CPU clock frequency — Up to 16 pre-programmed transfers

• Fast analog-to-digital converter (ADC) — Eight analog input channels

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— 12-bit resolution — Minimum 1.125 μs conversion time — Simultaneous sampling of two channels for motor control applications — Single-scan or continuous operation — Optional interrupts on conversion complete, zero crossing (sign change), or under/over

low/high limit

— Unused analog channels can be used as digital I/O

• Four 32-bit timers with DMA support — 12.5 ns resolution at 80 MHz — Programmable sources for clock input, including an external clock option — Programmable prescaler — Input capture capability with programmable trigger edge on input pin — Output compare with programmable mode for the output pin — Free run and restart modes — Maskable interrupts on input capture or output compare — DMA trigger capability on input capture or output compare

• Four-channel general purpose timer — 16-bit architecture — Programmable prescaler — Output pulse-widths variable from microseconds to seconds — Single 16-bit input pulse accumulator — Toggle-on-overflow feature for pulse-width modulator (PWM) generation — One dual-mode pulse accumulation channel

• Pulse-width modulation timer — Support for PCM mode (resulting in superior signal quality compared to conventional PWM) — Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution — Programmable period and duty cycle — Programmable enable/disable for each channel — Software selectable polarity for each channel — Period and duty cycle are double buffered. Change takes effect when the end of the current

period is reached (PWM counter reaches zero) or when the channel is disabled. — Programmable center or left aligned outputs on individual channels — Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies — Emergency shutdown

• Two periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down

• Real-Time Clock (RTC)

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— Maintains system time-of-day clock — Provides stopwatch and alarm interrupt functions

• Software watchdog timer — 32-bit counter — Low-power mode support

• Backup watchdog timer (BWT) — Independent timer that can be used to help software recover from runaway code — 16-bit counter — Low-power mode support

• Clock generation features — One to 48 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference

options — Trimmed relaxation oscillator — Two to 10 MHz reference frequency for normal PLL mode with a pre-divider programmable

from 1 to 8 — System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator

Overview

— Low power modes supported —2n (n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation

• Interrupt controller — Uniquely programmable vectors for all interrupt sources — Fully programmable level and priority for all peripheral interrupt sources — Seven external interrupt signals with fixed level and priority — Unique vector number for each interrupt source — Ability to mask any individual interrupt source or all interrupt sources (global mask-all) — Support for hardware and software interrupt acknowledge (IACK) cycles — Combinatorial path to provide wake-up from low-power modes

• DMA controller — Four fully programmable channels — Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for

16-byte (4×32-bit) burst transfers — Source/destination address pointers that can increment or remain constant — 24-bit byte transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle steal support — Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)

•Reset — Separate reset in and reset out signals — Seven sources of reset:

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– Power-on reset (POR) – External – Software – Watchdog – Loss of clock / loss of lock – Low-voltage detection (LVD) –JTAG

— Status flag indication of source of last reset

• Chip integration module (CIM) — System configuration during reset — Selects one of six clock modes — Configures output pad drive strength — Unique part identification number and part revision number

• General purpose I/O interface — Up to 56 bits of general purpose I/O — Bit manipulation supported via set/clear functions — Programmable drive strengths — Unused peripheral pins may be used as extra GPIO

• JTAG support for system level board testing

1.2.1 V2 Core Overview

The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer . The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the core includes the multiply-accumulate (MAC) unit for improved signal processing capabilities. The MAC implements a three-stage arithmetic pipeline, optimized for 16×16 bit operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The MAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.

1.2.2 Integrated Debug Module

The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator development tools. Through a standard debug interface, access to debug information and

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Overview

real-time tracing capability is provided on 100-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators.

The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. The MCF52211 implements revision B+ of the ColdFire Debug Architecture.

The MCF52211’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event. This ensure s the system continues to operate even during debugging.

To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52211 includes a new debug signal, ALLPST. This signal is the logical AND of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).

The full debug/trace interface is available only on the 100-pin packages. However, every product features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.

1.2.3 JTAG

The MCF52211 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic.

The MCF52211 implementation can:

• Perform boundary-scan operations to test circuit board electrical continuity

• Sample boundary scan register

• Bypass the MCF52211 for a given circuit board test by effectively reducing the boundary-scan register to a single bit

• Disable the output drive to pins during circuit-board testing

• Drive output pins to stable levels

MCF52211 system pins during operation and transparently shift out the result in the

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1.2.4 On-Chip Memories

1.2.4.1 SRAM

The dual-ported SRAM module provides a general-purpose 8- or 16-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 8- or 16-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module.

The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance.

1.2.4.2 Flash Memory

The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local bus. The CFM is constructed with up to four banks of 16-Kbyte×16-bit flash memory arrays to generate up to 128 Kbytes of 32-bit flash memory. These electrically erasable and programmable arrays serve as non-volatile program and data memory. The flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort, which is a serial flash memory programming interface that allows the flash memory to be read, erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips.

1.2.5 Power Management

The MCF52211 incorporates several low-power modes of operation entered under program control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the L VD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip falls below the standby battery voltage.

1.2.6 USB On-The-Go Controller

The MCF52211 includes a Universal Serial Bus On-The-Go (USB OTG) dual-mode controller. USB is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and handheld computers to host PCs. The OTG supplement to the USB specification extends USB to peer-to-peer application, enabling devices to connect directly to each other without the need for a PC. The dual-mode controller on the MCF52211 can act as a USB OTG host and as a USB device. It also supports full-speed and low-speed modes.

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1.2.7 UARTs

The MCF52211 has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions.

1.2.8 I2C Bus

The MCF52211 includes two I2C modules. The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices.

1.2.9 QSPI

The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability . It allows up to 16 transfers to be queued at once, mi nimizing the need for CPU intervention between transfers.

1.2.10 Fast ADC

The fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.

The ADC can be configured to perform a single scan and halt, a scan when triggered, or a programmed scan sequence repeatedly until manually stopped.

The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.

During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.

Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.

1.2.11 DMA Timers (DTIM0–DTIM3)

There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the MCF52211. Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler that clocks the actual timer counter

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor 1-11

Overview

register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers.

1.2.12 General Purpose Timer (GPT)

The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a seven-stage programmable prescaler . Each of the four channels can be configured for input capture or output compare. Additionally, channel three, can be configured as a pulse accumulator.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.

1.2.13 Periodic Interrupt Timers (PIT0 and PIT1)

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. Each timer can count down from the value written in its PIT modulus register or it can be a free-running down-counter.

1.2.14 Real-Time Clock (RTC)

The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch, alarm, and interrupt functions. It includes full clock features: seconds, minutes, hours, days and supports a host of time-of-day interrupt functions along with an alarm interrupt.

1.2.15 Pulse-Width Modulation (PWM) Timers

The MCF52211 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated counter . Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The timer supports PCM mode, which results in superior signal quality when compared to that of a conventional PWM. The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.

1.2.16 Software Watchdog Timer

The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.

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1-12 Freescale Semiconductor

Overview

1.2.17 Backup Watchdog Timer

The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer, facilitates recovery from runaway code. This timer is a free-running down-counter that generates a reset on underflow . T o prevent a reset, software must periodically restart the countdown. The backup watchdog timer can be clocked by either the relaxation oscillator or the system clock.

1.2.18 Phase-Locked Loop (PLL)

The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS.

1.2.19 Interrupt Controller (INTC)

The MCF52211 has a single interrupt controller that supports up to 63 interrupt sources. There are 56 programmable sources, 49 of which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for software interrupt requests.

1.2.20 DMA Controller

The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.

1.2.21 Reset

The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last reset. There are seven sources of reset:

• External reset input

• Power-on reset (POR)

• Watchdog timer

• Phase locked-loop (PLL) loss of lock / loss of clock

• Software

• Low-voltage detector (LVD)

•JTAG

Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO pin.

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Freescale Semiconductor 1-13

Overview

1.2.22 GPIO

Nearly all pins on the MCF52211 have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins.

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1-14 Freescale Semiconductor

Signal Descriptions

Chapter 2 Signal Descriptions

2.1 Introduction

This chapter describes signals implemented on this device and includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used.

NOTE

The terms assertion and negation are used to avoid confusion when dealing with a mixture of active-low and active-high signals. The term asserted indicates that a signal is active, independent of the voltage level. The term negated indicates that a signal is inactive.

Active-low signals, such as SRAS and TA, are indicated with an overbar.

2.2 Overview

Figure 2-1 shows the block diagram of the device with the signal interface.

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor 2-1

Arbiter

Interrupt

Controller

UART

QSPI

UART

I2C

V2 ColdFire CPU

4 CH

JTAG

TAP

16 Kbytes

SRAM

(2K×32)×2

128 Kbytes

Flash

(16K×16)×4

PORTS

CIM_IBO

RSTI RSTO

ADC

AN[7:0]

PLL OCO

CLKGEN

Edge

Port

TIM

EXTAL XTAL CLKOUT

PIT0 PIT1 PWM

IRQ[7:1]

PMM

STBY

PADI – Pin Muxing

Slave Mode Access

(CIM_IBO/EzPort)

TMS

TDI

TDO TRST TCLK

JTAG_EN

DMA

M2 M0

Watch

Dog

TMR

RTC

TMR

DDATA

QSPI SDAn SCLn UTXDn URXDn URTS

UCTSn PWMn DTINn/DTOUTn GPT RCON_B ALLPST PST

BDM

PORT

IPS Bus Gasket

Watchdog

CIM_IBO

CFM

CLKMOD

GPT[3:0]

Backup

USB

On-The-Go

USB TCVR

USBD+

USBD-

Signal Descriptions

2.3 Pin Functions

Figure 2-1. Block Diagram with Signal Interfaces

2-2 Freescale Semiconductor

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor 2-3

Table 2-1. Pin Functions by Primary and Alternate Purpose

Group

Primary

Function

Secondary

Function

Ter tia r y

Function

Quaternary

Function

Drive

Strength /

Control

Slew Rate /

Control

Pull-down

Pull-up /

100 LQFP

Pin on

Pin on 81 MAPBGA

Pin on 64

LQFP/QFN

ADC AN7 — — GPIO Low FAST — 51 H9 33

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

AN6 — — GPIO Low FAST — 52 G9 34

AN5 — — GPIO Low FAST — 53 G8 35

AN4 — — GPIO Low FAST — 54 F9 36

AN3 — — GPIO Low FAST — 46 G7 28

AN2 — — GPIO Low FAST — 45 G6 27

AN1 — — GPIO Low FAST — 44 H6 26

AN0 — — GPIO Low FAST — 43 J6 25

SYNCA

SYNCB

— — —N/AN/A————

VDDA — — — N/A N/A — 50 H8 32

VSSA — — — N/A N/A — 47 H7, J9 29

VRH — — — N/A N/A — 49 J8 31

VRL — — — N/A N/A — 48 J7 30

Clock

Generation

EXTAL — — — N/A N/A — 73 B9 47

XTAL — — — N/A N/A — 72 C9 46

VDDPLL — — — N/A N/A — 74 B8 48

VSSPLL — — — N/A N/A — 71 C8 45

Debug Data ALLPST — — — High FAST — 86 A6 55

DDATA[3:0] — — GPIO High FAST — 84,83,78,77 — —

PST[3:0] — — GPIO High FAST — 70,69,66,65 — —

C SCL USB_DMI UTXD2 GPIO PDSR[0] PSRR[0] pull-up

SDA USB_DPI URXD2 GPIO PDSR[0] PSRR[0] pull-up

10 E1 8

11 E2 9

Signal Descriptions

2-4 Freescale Semiconductor

Table 2-1. Pin Functions by Primary and Alternate Purpose (continued)

Signal Descriptions

Group

Primary

Function

Secondary

Function

Ter tia r y

Function

Quaternary

Function

Drive

Strength /

Control

Slew Rate /

Control

Pull-down

Pull-up /

100 LQFP

Pin on

Pin on 81 MAPBGA

Pin on 64

LQFP/QFN

Interrupts IRQ7 — —GPIOLowFAST—95C458

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ6

— — GPIO Low FAST — 94 B4 —

— — GPIO Low FAST — 91 A4 —

— —GPIOLowFAST—90C557

— — GPIO Low FAST — 89 A5 —

— — GPIO Low FAST — 88 B5 —

SYNCA USB_ALT_C

GPIO High FAST pull-up

87 C6 56

JTAG/BDM JTAG_EN — — — N/A N/A pull-down 26 J2 17

TCLK/

CLKOUT — — High FAST pull-up

64 C7 44

PSTCLK

TDI/DSI — — — N/A N/A pull-up

79 B7 50

TDO/DSO— — —HighFAST—80A751

TMS

— — — N/A N/A pull-up

76 A8 49

/BKPT

TRST

— — — N/A N/A pull-up

85 B6 54

/DSCLK

Mode

Selection

CLKMOD0 — — — N/A N/A pull-down

CLKMOD1 — — — N/A N/A pull-down

RCON

— — — N/A N/A pull-up 21 G3 16

40 G5 24

39 H5 —

EZPCS

Freescale Semiconductor 2-5

Table 2-1. Pin Functions by Primary and Alternate Purpose (continued)

Group

Primary

Function

QSPI QSPI_DIN/

Secondary

Function

Ter tia r y

Function

Quaternary

Function

— URXD1 GPIO PDSR[2] PSRR[2] — 16 F3 12

Drive

Strength /

Control

Slew Rate /

Control

Pull-down

Pull-up /

100 LQFP

Pin on

Pin on 81 MAPBGA

Pin on 64

LQFP/QFN

EZPD

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

QSPI_DOUT

— UTXD1 GPIO PDSR[1] PSRR[1] — 17 G1 13

/EZPQ

QSPI_CLK/

SCL URTS1 GPIO PDSR[3] PSRR[3] pull-up

18 G2 14

EZPCK

QSPI_CS3 SYNCA — GPIO PDSR[7] PSRR[7] pull-up/pull-

QSPI_CS2 — — GPIO PDSR[6] PSRR[6] pull-up/pull-

down

12 F1 —

13 F2 —

QSPI_CS1 — — GPIO PDSR[5] PSRR[5] — 19 H2 —

QSPI_CS0 SDA UCTS1 GPIO PDSR[4] PSRR[4] pull-up

Reset

RSTI — — — N/A N/A pull-up

RSTO

— — —highFAST—97B360

20 H1 15

96 A3 59

Test TEST — — — N/A N/A pull-down 5 C2 3

Timers, 16-bit GPT3 — PWM7 GPIO PDSR[23] PSRR[23] pull-up

GPT2 — PWM5 GPIO PDSR[22] PSRR[22] pull-up

GPT1 — PWM3 GPIO PDSR[21] PSRR[21] pull-up

GPT0 — PWM1 GPIO PDSR[20] PSRR[20] pull-up

63 D7 —

58 E8 —

33 J4 —

38 J5 —

Timers, 32-bit DTIN3 DTOUT3 PWM6 GPIO PDSR[19] PSRR[19] — 32 H3 19

DTIN2 DTOUT2 PWM4 GPIO PDSR[18] PSRR[18] — 31 J3 18

DTIN1 DTOUT1 PWM2 GPIO PDSR[17] PSRR[17] — 37 G4 23

DTIN0 DTOUT0 PWM0 GPIO PDSR[16] PSRR[16] — 36 H4 22

UART 0 UCTS0

URTS0

URXD0 RTC_EXTAL — GPIO PDSR[9] PSRR[9] — 7 D1 5

UTXD0 RTC_XTAL — GPIO PDSR[8] PSRR[8] — 8 D2 6

— — GPIO PDSR[11] PSRR[11] — 6 C1 4

— — GPIO PDSR[10] PSRR[10] — 9 D3 7

Signal Descriptions

2-6 Freescale Semiconductor

Table 2-1. Pin Functions by Primary and Alternate Purpose (continued)

Signal Descriptions

Group

Primary

Function

Secondary

Function

Ter tia r y

Function

Quaternary

Function

Drive

Strength /

Control

Slew Rate /

Control

Pull-down

Pull-up /

100 LQFP

Pin on

Pin on 81 MAPBGA

Pin on 64

LQFP/QFN

UART 1 UCTS1 SYNCA URXD2 GPIO PDSR[15] PSRR[15] — 98 C3 61

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

URXD1 — — GPIO PDSR[13] PSRR[13] — 100 B2 63

URTS1

SYNCB UTXD2 GPIO PDSR[14] PSRR[14] — 4 B1 2

UTXD1 — — GPIO PDSR[12] PSRR[12] — 99 A2 62

UART 2 UCTS2

URTS2

— — GPIO PDSR[27] PSRR[27] — 27 — —

— — GPIO PDSR[26] PSRR[26] — 30 — —

URXD2 — — GPIO PDSR[25] PSRR[25] — 28 — —

UTXD2 — — GPIO PDSR[24] PSRR[24] — 29 — —

VSTBY VSTBY — — — N/A N/A — 55 F8 37

USB VDDUSB — — — N/A N/A — 62 D8 43

VSSUSB — — — N/A N/A — 59 F7 40

USB_DM — — — N/A N/A — 61 D9 42

USB_DP — — — N/A N/A — 60 E9 41

VDD VDD — — — N/A N/A — 1,2,14,22,

23,34,41,

D5,E3–E7, F51,10,20,39,

57,68,81,93

VSS VSS — — — N/A N/A — 3,15,24,25,

35,42,56,

A1,A9,D4,D

6,F4,F6,J1

11,21,38,

53,64

67,75,82,92

The PDSR and PSSR registers are described in the General Purpose I/O chapter. All programmable signals default to 2 mA drive and FAST slew rate in

normal (single-chip) mode.

All signals have a pull-up in GPIO mode.

These signals are multiplexed on other pins.

For primary and GPIO functions only.

Only when JTAG mode is enabled.

CLKMOD0 and CLKMOD1 have internal pull-down resistors; however, the use of external resistors is very strongly recommended.

When these pins are configured for USB signals, they should use the USB transceiver’s internal pull-up/pull-down resistors (see the description of the OTG_CTRL register). If these pins are not configured for USB signals, each pin should be pulled down externally using a 10 kΩ resistor.

For secondary and GPIO functions only.

RSTI has an internal pull-up resistor; however, the use of an external resistor is very strongly recommended.

For GPIO function. Primary Function has pull-up control within the GPT module.

Freescale Semiconductor 2-7

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Signal Descriptions

2.4 Reset Signals

Table 2-2 describes signals that are used to reset the chip or as a reset indication.

Table 2-2. Reset Signals

Signal Name Abbreviation Function I/O

Reset In RSTI

Reset Out RSTO Driven low for 512 CPU clocks after the reset source has deasserted

Primary reset input to the device. Asserting RSTI immediately resets the CPU and peripherals.

and PLL locked.

2.5 PLL and Clock Signals

Table 2-3 describes signals that are used to support the on-chip clock generation circuitry.

Table 2-3. PLL and Clock Signals

Signal Name Abbreviation Function I/O

External Clock In EXTAL Crystal oscillator or external clock input except when the on-chip

relaxation oscillator is used.

Crystal XTAL Crystal oscillator output except when CLKMOD1=1, then sampled as

part of the clockmode selection mechanism.

Clock Out CLKOUT This output signal reflects the internal system clock. O

2.6 Mode Selection

Table 2-4 describes signals used in mode selection, Table 2-5 describes particular clocking modes.

Table 2-4. Mode Selection Signals

Signal Name Abbreviation Function I/O

Clock Mode Selection CLKMOD[1:0] Selects the clock boot mode. I

Reset Configuration RCON

Test TEST Reserved for factory testing only and in normal modes of operation

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

The serial flash programming mode is entered by asserting the RCON

pin (with the TEST pin negated) as the chip comes out of reset. During this mode, the EzPort has access to the flash memory which can be programmed from an external device.

should be connected to VSS to prevent unintentional activation of test functions.

2-8 Freescale Semiconductor

Table 2-5. Clocking Modes

CLKMOD[1:0] XTAL Configure the Clock Mode

00 0 PLL disabled, clock driven by external oscillator

00 1 PLL disabled, clock driven by on-chip oscillator

01 N/A PLL disabled, clock driven by crystal

10 0 PLL in normal mode, clock driven by external oscillator

10 1 PLL in normal mode, clock driven by on-chip oscillator

11 N/A PLL in normal mode, clock driven by crystal

2.7 External Interrupt Signals

Table 2-6 describes the external interrupt signals.

Table 2-6. External Interrupt Signals

Signal Name Abbreviation Function I/O

External Interrupts IRQ[7:1] External interrupt sources. I

Signal Descriptions

2.8 Queued Serial Peripheral Interface (QSPI)

Table 2-7 describes the QSPI signals.

Table 2-7. Queued Serial Peripheral Interface (QSPI) Signals

Signal Name Abbreviation Function I/O

QSPI Synchronous

Serial Output

QSPI Synchronous

Serial Data Input

QSPI Serial Clock QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of

Synchronous Peripheral

Chip Selects

QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be

driven on the rising or falling edge of QSPI_CLK.

QSPI_DIN Provides the serial data to the QSPI and can be programmed to be

sampled on the rising or falling edge of QSPI_CLK.

QSPI_CLK are programmable.

QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active

high or low.

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Freescale Semiconductor 2-9

Signal Descriptions

2.9 I2C I/O Signals

Table 2-8 describes the I2C serial interface module signals.

Table 2 -8. I2C I/O Signals

Signal Name Abbreviation Function I/O

Serial Clock SCLn Open-drain clock signal for the for the I2C interface. It is driven by the

Serial Data SDAn Open-drain signal that serves as the data input/output for the I2C

C module when the bus is in master mode or it becomes the clock

I input when the I2C is in slave mode.

interface.

2.10 UART Module Signals

Table 2-9 describes the UART module signals.

Table 2-9. UART Module Signals

Signal Name Abbreviation Function I/O

Transmit Serial Data Output UTXDn Transmitter serial data outputs for the UART modules. The output is

held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, LSB first, on this pin at the falling edge of the serial clock source.

Receive Serial Data Input URXDn Receiver serial data inputs for the UART modules. Data is received on

this pin LSB first. When the UART clock is stopped for power-down mode, any transition on this pin restarts it.

Clear-to-Send UCTS

Request-to-Send URTSn Automatic request-to-send outputs from the UART modules. This

n Indicate to the UART modules that they can begin data transmission. I

signal can also be configured to be asserted and negated as a function of the RxFIFO level.

I/O

2.11 DMA Timer Signals

Table 2-10 describes the signals of the four DMA timer modules.

Table 2-10. DMA Timer Signals

Signal Name Abbreviation Function I/O

DMA Timer Input DTINn Event input to the DMA timer modules. I

DMA Timer Output DTOUTn Programmable output from the DMA timer modules. O

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2-10 Freescale Semiconductor

Signal Descriptions

2.12 ADC Signals

Table 2-11 describes the signals of the analog-to-digital converter.

Table 2-11. ADC Signals

Signal Name Abbreviation Function I/O

Analog Inputs AN[7:0] Inputs to the ADC. I

Analog Reference V

Analog Supply V

DDA

SSA

Reference voltage high and low inputs. I

Isolate the ADC circuitry from power supply noise —

2.13 General Purpose Timer Signals

Table 2-12 describes the general purpose timer signals.

Table 2-12. GPT Signals

Signal Name Abbreviation Function I/O

—

General Purpose Timer Input/Output

GPT[3:0] Inputs to or outputs from the general purpose timer module I/O

2.14 Pulse-Width Modulator Signals

Table 2-13 describes the PWM signals.

Table 2-13. PWM Signals

Signal Name Abbreviation Function I/O

PWM Output Channels PWM[7:0] Pulse-width modulated output for PWM channels O

2.15 Debug Support Signals

The signals in Table 2-14 are used as the interface to the on-chip J TAG controller and also to interface to the BDM logic.

Table 2-14. Debug Support Signals

Signal Name Abbreviation Function I/O

JTAG Enable JTAG_EN Select between debug module and JTAG signals at reset I

Test Reset TRST

This active-low signal is used to initialize the JTAG logic asynchronously.

Test Clock TCLK Used to synchronize the JTAG logic. I

Test Mode Select TMS Used to sequence the JTAG state machine. TMS is sampled on the

rising edge of TCLK.

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Freescale Semiconductor 2-11

Signal Descriptions

Signal Name Abbreviation Function I/O

Table 2-14. Debug Support Signals (continued)

Test Data Input TDI Serial input for test instructions and data. TDI is sampled on the rising

edge of TCLK.

Test Data Output TDO Serial output for test instructions and data. TDO is three-stateable and

is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK.

Development Serial

Clock

DSCLK Development Serial Clock. Internally synchronized input. (The logic

level on DSCLK is validated if it has the same value on two consecutive rising bus clock edges.) Clocks the serial communication port to the debug module during packet transfers. Maximum frequency is PSTCLK/5. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.

Breakpoint BKPT

Breakpoint. Input used to request a manual breakpoint. Assertion of

puts the processor into a halted state after the current

BKPT instruction completes. Halt status is reflected on processor status signals as the value 0xF.

Development Serial

Input

DSI Development Serial Input. Internally synchronized input that provides

data input for the serial communication port to the debug module after the DSCLK has been seen as high (logic 1).

Development Serial

Output

DSO Development Serial Output. Provides serial output communication for

debug module responses. DSO is registered internally. The output is delayed from the validation of DSCLK high.

Debug Data DDATA[3:0] Debug data. Displays captured processor data and breakpoint status.

The CLKOUT signal can be used by the development system to know when to sample DDATA[3:0].

Processor Status Clock PSTCLK Processor Status Clock. Delayed version of the processor clock. Its

rising edge appears in the center of valid PST and DDATA output. PSTCLK indicates when the development system should sample PST and DDATA values. If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and PST and DDATA outputs from toggling without disabling triggers. Non-quiescent operation can be reenabled by clearing CSR[PCD], although the external development systems must resynchronize with the PST and DDATA outputs. PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs during system reset exception processing.

Processor Status

Outputs

PST[3:0] Indicate core status. Debug mode timing is synchronous with the

processor clock; status is unrelated to the current bus transfer. The CLKOUT signal can be used by the development system to know when to sample PST[3:0].

All Processor Status

ALLPST Logical AND of PST[3.0] O

Outputs

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2-12 Freescale Semiconductor

2.16 EzPort Signal Descriptions

Table 2-15 contains a list of EzPort external signals

Table 2-15. EzPort Signal Descriptions

Signal Name Abbreviation Function I/O

EzPort Clock EZPCK Shift clock for EzPort transfers I

Signal Descriptions

EzPort Chip Select EZPCS Chip select for signaling the start and end of

serial transfers

EzPort Serial Data In EZPD EZPD is sampled on the rising edge of EZPCK I

EzPort Serial Data Out EZPQ EZPQ transitions on the falling edge of EZPCK O

2.17 Power and Ground Pins

The pins described in Table 2-16 provide system power and ground to the chip. Multiple pins are provided for adequate current capability. All power supply pins must have adequate decoupling (bypass capacitance) for high-frequency noise suppression.

Table 2-16. Power and Ground Pins

Signal Name Abbreviation Function I/O

PLL Analog Supply VDDPLL,

VSSPLL

Positive Supply VDD These pins supply positive power to the core logic. I

Ground VSS This pin is the negative supply (ground) to the chip.

Dedicated power supply signals to isolate the sensitive PLL analog circuitry from the normal levels of noise present on the digital power supply.

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Freescale Semiconductor 2-13

Signal Descriptions

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2-14 Freescale Semiconductor

Chapter 3

Instruction

FIFO

Decode & Select,

Address

IAG

DSOC

AGEX

Instruction Buffer

Address

Generation

Fetch Cycle

Generation,

Execute

Operand Fetch

Instruction

Operand

Pipeline

Execution

Fetch

Pipeline

Address [31:0]

Read Data[31:0]

Write Data[31:0]

ColdFire Core

3.1 Introduction

This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the ColdFire Family Programmer’s Reference Manual.

3.1.1 Overview

As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer.

The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the

Freescale Semiconductor 3-1

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

Figure 3-1. V2 ColdFire Core Pipelines

ColdFire Core

instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.

The V2 ColdFire core pipeline stages include the following:

• Two-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage) — Instruction address generation (IAG) — Calculates the next prefetch address — Instruction fetch cycle (IC)—Initiates prefetch on the processor’s local bus — Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO

queue

• Two-stage operand execution pipeline (OEP) — Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the

required components for effective address calculation, or the operand fetch cycle

— Address generation/execute cycle (AGEX)—Calculates operand address or executes the

instruction

When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the operand execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction in the IB until it is required by the OEP.

For register-to-register and register-to-memory store operations, the instruction passes through both OEP stages once. For memory-to-register and read-modify-write memory operations, an instruction is effectively staged through the OEP twice: the first time to calculate the effective address and initiate the operand fetch on the processor’s local bus, and the second time to complete the operand reference and perform the required function defined by the instruction.

The resulting pipeline and local bus structure allow the V2 ColdFire core to deliver sustained high performance across a variety of demanding embedded applications.

3.2 Memory Map/Register Description

The following sections describe the processor registers in the user and supervisor programming models. The programming model is selected based on the processor privilege level (user mode or supervisor mode) as defined by the S bit of the status register (SR). Table 3-1 lists the processor registers.

The user-programming model consists of the following registers:

• 16 general-purpose 32-bit registers (D0–D7, A0–A7)

• 32-bit program counter (PC)

• 8-bit condition code register (CCR)

• MAC registers (described fully in Chapter 4, “Multiply-Accumulate Unit (MAC)”): — One 32-bit accumulator(ACC) register — One 16-bit mask register (MASK) — 8-bit Status register (MACSR)

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• Two 32-bit memory base address registers (RAMBAR, FLASHBAR)

The supervisor-programming model is intended to be used only by system control software to implement restricted operating system functions, I/O control, and memory management. All accesses that affect the control features of ColdFire processors are in the supervisor programming model, which consists of registers available in user mode as well as the following control registers:

• 16-bit status register (SR)

• 32-bit supervisor stack pointer (SSP)

• 32-bit vector base register (VBR)

Table 3-1. ColdFire Core Programming Model

BDM

Load: 0x080

Store: 0x180

Load: 0x081

Store: 0x181

Load: 0x082–7

Store: 0x182–7

Load: 0x088–8E

Store: 0x188–8E

Load: 0x08F Store: 0x18F

0x804 MAC Status Register (MACSR) 8 R/W 0x00 No 4.2.1/4-2

0x805 MAC Address Mask Register (MASK) 16 R/W 0xFFFF No 4.2.2/4-4

0x806 MAC Accumulator (ACC) 32 R/W Undefined No 4.2.3/4-5

0x80E Condition Code Register (CCR) 8 R/W Undefined No 3.2.4/3-5

0x80F Program Counter (PC) 32 R/W Contents of

Data Register 0 (D0) 32 R/W 0xCF20_C089 No 3.2.1/3-4

Data Register 1 (D1) 32 R/W 0x10A0_1070 No 3.2.1/3-4

Data Register 2–7 (D2–D7) 32 R/W Undefined No 3.2.1/3-4

Address Register 0–6 (A0–A6) 32 R/W Undefined No 3.2.2/3-4

Supervisor/User A7 Stack Pointer (A7) 32 R/W Undefined No 3.2.3/3-4

Supervisor/User Access Registers

Width

(bits)

Access Reset Value

location

0x0000_0004

Written with

MOVEC

No 3.2.5/3-6

Section/Page

Supervisor Access Only Registers

0x800 User/Supervisor A7 Stack Pointer

(OTHER_A7)

0x801 Vector Base Register (VBR) 32 R/W 0x0000_0000 Yes 3.2.6/3-6

0x80E Status Register (SR) 16 R/W 0x27-- No 3.2.7/3-7

0xC04 Flash Base Address Register

(FLASHBAR)

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32 R/W Contents of

32 R/W 0x0000_0000 Yes 3.2.8/3-8

No 3.2.3/3-4

location

0x0000_0000

ColdFire Core

Table 3-1. ColdFire Core Programming Model (continued)

BDM

0xC05 RAM Base Address Register (RAMBAR) 32 R/W See Section Yes 3.2.8/3-8

The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 28, “Debug Module”.

Width

(bits)

Access Reset Value

Written with

MOVEC

Section/Page

3.2.1 Data Registers (D0–D7)

D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they can also be used as index registers.

NOTE

Registers D0 and D1 contain hardware configuration details after reset. See

Section 3.3.4.15, “Reset Exception” for more details.

BDM: Load: 0x080 + n; n = 0-7 (Dn)

Store: 0x180 + n; n = 0-7 (Dn)

313029282726252423222120191817161514131211109876543210

Reset

(D2-D7)

(D0, D1)

––––––––––––––––––––––––––––––––

Reset

Data

See Section 3.3.4.15, “Reset Exception”

Access: User read/write

BDM read/write

Figure 3-2. Data Registers (D0–D7)

3.2.2 Address Registers (A0–A6)

These registers can be used as software stack pointers, index registers, or base address registers. They can also be used for word and longword operations.

BDM: Load: 0x088 + n; n =0–6 (An)

Store: 0x188 + n; n =0–6 (An)

313029282726252423222120191817161514131211109876543210

Reset––––––––––––––––––––––––––––––––

Address

Figure 3-3. Address Registers (A0–A6)

Access: User read/write

BDM read/write

3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)

This ColdFire architecture supports two independent stack pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two program-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead, the

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hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents are a function of the processor operation mode, as shown in the following:

if SR[S] = 1

then A7 = Supervisor Stack Pointer

OTHER_A7 = User Stack Pointer

else A7 = User Stack Pointer

OTHER_A7 = Supervisor Stack Pointer

The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the responsibility of the external development system to determine, based on the setting of SR[S], the mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP).

To support dual stack pointers, the following two supervisor instructions are included in the ColdFire instruction set architecture to load/store the USP:

move.l Ay,USP;move to USP move.l USP,Ax;move from USP

These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other instruction references to the stack pointer, explicit or implicit, access the active A7 register.

NOTE

The USP must be initialized using the move.l Ay,USP instruction before any entry into user mode.

The SSP is loaded during reset exception processing with the contents of location 0x0000_0000.

BDM: Load: 0x08F (A7)

Store: 0x18F (A7) 0x800 (OTHER_A7)

313029282726252423222120191817161514131211109876543210

Reset––––––––––––––––––––––––––––––––

Figure 3-4. Stack Pointer Registers (A7 and OTHER_A7)

Address

Access: A7: User or BDM read/write

OTHER_A7: Supervisor or BDM read/write

3.2.4 Condition Code Register (CCR)

The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results generated by processor operations. The extend bit (X) is also an input operand during multiprecision arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare (CMP), Bcc, or Scc instructions are executed.

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BDM: LSB of Status Register (SR) Access: User read/write

BDM read/write

76543210

R 0 0 0

Reset:0 0 0 —————

X N Z V C

Figure 3-5. Condition Code Register (CCR)

Table 3-2. CCR Field Descriptions

Field Description

7–5 Reserved, must be cleared.

Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified

result.

Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.

Zero condition code bit. Set if result equals zero; otherwise cleared.

Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand

size; otherwise cleared.

Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a

subtraction; otherwise cleared.

3.2.5 Program Counter (PC)

The PC contains the currently executing instruction address. During instruction execution and exception processing, the processor automatically increments contents of the PC or places a new value in the PC, as appropriate. The PC is a base address for PC-relative operand addressing.

The PC is initially loaded during reset exception processing with the contents of location 0x0000_0004.

BDM: 0x80F (PC) Access: User read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

Reset––––––––––––––––––––––––––––––––

Figure 3-6. Program Counter Register (PC)

Address

3.2.6 Vector Base Register (VBR)

The VBR contains the base address of the exception vector table in memory. To access the vector table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are

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not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on a 1 MByte boundary.

BDM: 0x801 (VBR) Access: Supervisor read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

Reset00000000000000000000000000000000

Base Address

0 0 0 0 000000000 000 0 00

Figure 3-7. Vector Base Register (VBR)

3.2.7 Status Register (SR)

The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and before any compare (CMP), Bcc, or Scc instructions execute.

BDM: 0x80E (SR) Access: Supervisor read/write

BDM read/write

System Byte Condition Code Register (CCR)

1514131211109876543210

Reset00100111000—————

S M

000

X N ZVC

Figure 3-8. Status Register (SR)

Table 3-3. SR Field Descriptions

Field Description

15TTrace enable. When set, the processor performs a trace exception after every instruction.

14 Reserved, must be cleared.

13SSupervisor/user state.

0User mode 1 Supervisor mode

12MMaster/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or

move to SR instructions.

11 Reserved, must be cleared.

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3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR)

The memory base address register sare used to specify the base address of the internal SRAM and flash modules and indicate the types of references mapped to each. Each base address register includes a base address, write-protect bit, address space mask bits, and an enable bit. FLASHBAR determines the base address of the on-chip flash, and RAMBAR determines the base address of the on-chip RAM. For more information, refer to Section 5.2.1, “SRAM Base Address Register (RAMBAR)” and Section 18.3.2,

“Flash Base Address Register (FLASHBAR)”.

IAG IC IB

Core Bus Address

Core Bus

Read Data

Opword

Extension 1

Extension 2

FIFO

Table 3-3. SR Field Descriptions (continued)

Field Description

10–8IInterrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or

equal to current level, except edge-sensitive level 7 requests, which cannot be masked.

7–0

CCR

Refer to Section 3.2.4, “Condition Code Register (CCR)”.

3.3 Functional Description

3.3.1 Version 2 ColdFire Microarchitecture

From the block diagram in Figure 3-1, the non-Harvard architecture of the processor is readily apparent. The processor interfaces to the local memory subsystem via a single 32-bit address and two unidirectional 32-bit data buses. This structure minimizes the core size without compromising performance to a large degree.

A more detailed view of the hardware structure within the two pipelines is presented in Figure 3-9 and

Figure 3-10 below . In these diagrams, the internal structure of the instruction fetch and operand execution

pipelines is shown:

Figure 3-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram

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Figure 3-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write Data

RGF

ColdFire Core

The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For sequential prefetches, the next instruction address is generated by adding four to the last prefetch address. This function is performed during the IAG stage and the resulting prefetch address gated onto the core bus (if there are no pending operand memory accesses which are assigned a higher priority). After the prefetch address is driven onto the core bus, the instruction fetch cycle accesses the appropriate local memory and returns the instruction read data back to the IFP during the cycle. If the accessed data is not present in a local memory (e.g., an instruction cache miss, or an external access cycle is required), the IFP is stalled in the IC stage until the referenced data is available. As the prefetch data arrives in the IFP, it can be loaded into the FIFO instruction buffer or gated directly into the OEP.

The V2 design uses a simple static conditional branch prediction algorithm (forward-assumed as not-taken, backward-assumed as taken), and all change-of-flow operations are calculated by the OEP and the target instruction address fed back to the IFP.

The IFP and OEP are decoupled by the FIFO instruction buffer , allowing instruction prefetching to occur with the available core bus bandwidth not used for operand memory accesses. For the V2 design, the instruction buffer contains three 32-bit locations.

Consider the operation of the OEP for three basic classes of non-branch instructions:

• Register-to-register:

op Ry,Rx

• Embedded load:

op <mem>y,Rx

• Register-to-memory (store)

move Ry,<mem>x

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Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write

Data

new Rx

RGF

For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and fetching of the required register operands (OC) from the dual-ported register file, while the actual instruction execution is performed in the second stage (EX) in one of the execute engines (e.g., ALU, barrel shifter, divider, EMAC). There are no operand memory accesses associated with this class of instructions, and the execution time is typically a single machine cycle. See Figure 3-11.

Figure 3-11. V2 OEP Register-to-Register

For memory-to-register (embedded-load) instructions, the instruction is effectively staged through the OEP twice with a basic execution time of three cycles. First, the instruction is decoded and the components of the operand address (base register from the RGF and displacement) are selected (DS). Second, the operand effective address is generated using the ALU execute engine (AG). Third, the memory read operand is fetched from the core bus, while any required register operand is simultaneously fetched (OC) from the RGF. Finally, in the fourth cycle, the instruction is executed (EX). The heavily-used 32-bit load instruction (

move.l <mem>y,Rx) is optimized to support a two-cycle execution time. The following example

in Figure 3-12 shows an effective address of the form <ea> y = (d16,Ay), i.e., a 16-bit signed displacement added to a base register Ay.

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Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write

RGF

Data

d16

<ea>y

Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write

RGF

Data

new Rx

<mem>y

Figure 3-12. V2 OEP Embedded-Load Part 1

Figure 3-13. V2 OEP Embedded-Load Part 2

For register-to-memory (store) operations, the stage functions (DS/OC, AG/EX) are effectively performed simultaneously allowing single-cycle execution. See Figure 3-14 where the effective address is of the form <ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax.

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Operand Execution Pipeline

DSOC AGEX

Opword

Extension 1

Extension 2

Core Bus

Read Data

Core Bus Address

Core Bus Write

RGF

Data

d16

<ea>x

For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store operation for a three-cycle execution time.

Figure 3-14. V2 OEP Register-to-Memory

The pipeline timing diagrams of Figure 3-15 depict the execution templates for these three classes of instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown progressing down the operand execution pipeline.

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Core clock

Core Bus

Embedded-Load

Core Bus

op read

Core Bus

op write

OEP.DSOC OC next

OEP.AGEX EX

OEP.DSOC DS OC next

OEP.AGEX EXAG

OEP.DSOC DSOC next

OEP.AGEX AGEX

(Store)

3.3.2 Instruction Set Architecture (ISA_A+)

The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes based on extensive analysis of embedded application code. The ISA was optimized for code compiled from high-level languages where the dominant operand size was the 32-bit integer declaration. This approach minimized processor complexity and cost, while providing excellent performance for compiled applications.

After the initial ColdFire compilers were created, developers noted there were certain ISA additions that would enhance code density and overall performance. Additionally , as users implemented ColdFire-based designs into a wide range of embedded systems, they found certain frequently-used instruction sequences that could be improved by the creation of additional instructions.

The original ISA definition minimized support for instructions referencing byte- and word-sized operands. Full support for the move byte and move word instructions was provided, but the only other opcodes supporting these data types are clr (clear) and tst (test). A set of instruction enhancements has been implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three areas:

1. Enhanced support for byte and word-sized operands

2. Enhanced support for position-independent code

3. Miscellaneous instruction additions to address new functionality

Figure 3-15. V2 OEP Pipeline Execution Templates

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Table 3-4 summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details

see the ColdFire Family Programmer’s Reference Manual.

Table 3-4. Instruction Enhancements over Revision ISA_A

Instruction Description

BITREV The contents of the destination data register are bit-reversed; that is, new Dn[31] equals old

Dn[0], new Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31].

BYTEREV The contents of the destination data register are byte-reversed; that is, new Dn[31:24] equals

old Dn[7:0],..., new Dn[7:0] equals old Dn[31:24].

FF1 The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending

with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then loaded with the offset count from bit 31 where the first set bit appears.

Move from USP USP → Destination register

Move to USP Source register → USP

STLDSR Pushes the contents of the status register onto the stack and then reloads the status register

with the immediate data value.

3.3.3 Exception Processing Overview

Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors differ from the M68000 family because they include:

• A simplified exception vector table

• Reduced relocation capabilities using the vector-base register

• A single exception stack frame format

• Use of separate system stack pointers for user and supervisor modes.

All ColdFire processors use an instruction restart exception model. However, Version 2 ColdFire processors require more software support to recover from certain access errors. See Section 3.3.4.1,

“Access Error Exception” for details.

Exception processing includes all actions from fault condition detection to the initiation of fetch for first handler instruction. Exception processing is comprised of four major steps:

1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to be cleared and the interrupt priority mask to set to current interrupt request level.

2. The processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to special locations within the interrupt controller’s address space with the interrupt level encoded in the address.

3. The processor saves the current context by creating an exception stack frame on the system stack. The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to by the supervisor stack pointer (SSP). As shown in Figure 3-16, the processor uses a simplified

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fixed-length stack frame for all exceptions. The exception type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next).

4. The processor calculates the address of the first instruction of the exception handler. By definition, the exception vector table is aligned on a 1 Mbyte boundary . This inst ruction address is generated by fetching an exception vector from the table located at the address defined in the vector base register . The index into the exception table is calculated as (4 × vector number). After the exception vector has been fetched, the vector contents determine the address of the first instruction of the desired handler. After the instruction fetch for the first opcode of the handler has initiated, exception processing terminates and normal instruction processing continues in the handler.

All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see

Table 3-5). The table contains 256 exception vectors; the first 64 are defined for the core and the remaining

192 are device-specific peripheral interrupt vectors. See Chapter 14, “Interrupt Controller Module” for details on the device-specific interrupt sources.

Table 3-5. Exception Vector Assignments

Vector

Number(s)

0 0x000 — Initial supervisor stack pointer

1 0x004 — Initial program counter

2 0x008 Fault Access error

3 0x00C Fault Address error

4 0x010 Fault Illegal instruction

5 0x014 Fault Divide by zero

6–7 0x018–0x01C — Reserved

8 0x020 Fault Privilege violation

9 0x024 Next Trace

10 0x028 Fault Unimplemented line-A opcode

11 0x02C Fault Unimplemented line-F opcode

12 0x030 Next Debug interrupt

13 0x034 — Reserved

14 0x038 Fault Format error

15–23 0x03C–0x05C — Reserved

24 0x060 Next Spurious interrupt

25–31 0x064–0x07C — Reserved

Vector

Offset (Hex)

Stacked

Program

Counter

Assignment

32–47 0x080–0x0BC Next Trap # 0-15 instructions

48–63 0x0C0–0x0FC — Reserved

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Table 3-5. Exception Vector Assignments (continued)

Vector

Number(s)

64–255 0x100–0x3FC Next Device-specific interrupts

Fault refers to the PC of the instruction that caused the exception. Next refers to the PC of the instruction that follows the instruction that caused the fault.

Vector

Offset (Hex)

Stacked

Program

Counter

Assignment

All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level contained in the status register. In addition, the ISA_A+ architecture includes an instruction (STLDSR) that stores the current interrupt mask level and loads a value into the SR. This instruction is specifically intended for use as the first instruction of an interrupt service routine that services multiple interrupt requests with different interrupt levels. For more details, see ColdFire Family Programmer’s Reference Manual.

3.3.3.1 Exception Stack Frame Definition

Figure 3-16 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)

and the 16-bit status register, and the second longword contains the 32-bit program counter address.

313029282726252423222120191817161514131211109876543210

SSP → Format FS[3:2] Vector FS[1:0] Status Register

+ 0x4

Program Counter

Figure 3-16. Exception Stack Frame Form

The 16-bit format/vector word contains three unique fields:

• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by the processor, indicating a two-longword frame format. See Table 3-6.

Table 3-6. Format Field Encodings

Original SSP @ Time

of Exception, Bits 1:0

00 Original SSP - 8 0100

01 Original SSP - 9 0101

10 Original SSP - 10 0110

11 Original SSP - 11 0111

SSP @ 1st

Instruction of

Handler

Format Field

• There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other exceptions. See Table 3-7.

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Table 3-7. Fault Status Encodings

FS[3:0] Definition

00xx Reserved

0100 Error on instruction fetch

0101 Reserved

011x Reserved

1000 Error on operand write

1001 Attempted write to write-protected space

101x Reserved

1100 Error on operand read

1101 Reserved

111x Reserved

• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor for all internal faults and represents the value supplied by the interrupt controller in case of an interrupt. See Table 3-5.

3.3.4 Processor Exceptions

3.3.4.1 Access Error Exception

The exact processor response to an access error depends on the memory reference being performed. For an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an instruction for execution. Therefore, faults during instruction prefetches followed by a change of instruction flow do not generate an exception. When the processor attempts to execute an instruction with a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For this type of exception, the programming model has not been altered by the instruction generating the access error.

If the access error occurs on an operand read, the processor immediately aborts the current instruction’s execution and initiates exception processing. In this situation, any address register updates attributable to the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming model contains the updated An value. In addition, if an access error occurs during a MOVEM instruction loading from memory, any registers already updated before the fault occurs contain the operands from memory.

The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes. Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. Accordingly , the PC contained in the exception stack fra me merely represents the location in the program when the access error was signaled. All programming model updates associated with the write instruction are completed. The NOP instruction can collect access errors for writes. This instruction delays its

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execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.

3.3.4.2 Address Error Exception

Any attempted execution transferring control to an odd instruction address (that is, if bit 0 of the target address is set) results in an address error exception.

Any attempted use of a word-sized index register (Xn.w) or a scale factor of eight on an indexed effective addressing mode generates an address error, as does an attempted execution of a full-format indexed addressing mode, which is defined by bit 8 of extension word 1 being set.

If an address error occurs on a JSR instruction, the Version 2 ColdFire processor calculates the target address then the return address is pushed onto the stack.If an address error occurs on an RTS instruction, the Version 2 ColdFire processor overwrites the faulting return PC with the address error stack frame.

3.3.4.3 Illegal Instruction Exception

The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits. The first instruction word is known as the operation word (or opword), while the optional words are known as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode (opmode), and the low-order 6 bits define the effective address. See Figure 3-17. The opword line definition is shown in Table 3-8.

1514131211109876543210

Line OpMode Effective Address

Mode Register

Figure 3-17. ColdFire Instruction Operation Word (Opword) Format

Table 3-8. ColdFire Opword Line Definition

Opword[Line] Instruction Class

0x0 Bit manipulation, Arithmetic and Logical Immediate

0x1 Move Byte

0x2 Move Long

0x3 Move Word

0x4 Miscellaneous

0x5 Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc)

0x6 PC-relative change-of-flow instructions

Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR)

0x7 Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ)

0x8 Logical OR (OR)

0x9 Subtract (SUB), Subtract Extended (SUBX)

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Table 3-8. ColdFire Opword Line Definition (continued)

Opword[Line] Instruction Class

0xA MAC, Move 3-bit Quick (MOV3Q)

0xB Compare (CMP), Exclusive-OR (EOR)

0xC Logical AND (AND), Multiply Word (MUL)

0xD Add (ADD), Add Extended (ADDX)

0xE Arithmetic and logical shifts (ASL, ASR, LSL, LSR)

0xF Cache Push (CPUSHL), Write DDATA (WDDATA), Write Debug (WDEBUG)

In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations (line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors associated with illegal opwords in these two lines.

Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an illegal instruction exception (vector 4). Additionally , any attempted execution of any non-MAC line-A and most line-F opcodes generate their unique exception types, vector numbers 10 and 11, respectively. ColdFire cores do not provide illegal instruction detection on the extension words on any instruction, including MOVEC.

3.3.4.4 Divide-By-Zero

Attempting to divide by zero causes an exception (vector 5, offset equal 0x014).

3.3.4.5 Privilege Violation

The attempted execution of a supervisor mode instruction while in user mode generates a privilege violation exception. See ColdFire Programmer’s Reference Manual for a list of supervisor-mode instructions.

There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in user mode for debugging purposes.

3.3.4.6 Trace Exception

To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction execution (for all but the stop instruction) signals a trace exception. This functionality allows a debugger to monitor program execution.

The stop instruction has the following effects:

1. The instruction before the stop executes and then generates a trace exception. In the exception stack frame, the PC points to the stop opcode.

2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate operand from the instruction.

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3. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in the previous step.

If the processor is not in trace mode and executes a stop instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in step 2.

Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. As an example, consider a TRAP instruction execution while in trace mode. The processor initiates the trap exception and then passes control to the corresponding handler . If the system requires that a trace exception be processed, it is the responsibility of the trap exception handler to check for this condition (SR[T] in the exception stack frame set) and pass control to the trace handler before returning from the original exception.

3.3.4.7 Unimplemented Line-A Opcode

A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the attempted execution of an undefined line-A opcode.

3.3.4.8 Unimplemented Line-F Opcode

A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when attempting to execute an undefined line-F opcode.

3.3.4.9 Debug Interrupt

See Chapter 28, “Debug Module,” for a detailed explanation of this exception, which is generated in response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle, but rather calculates the vector number internally (vector number 12). Additionally , SR[M,I] are unaffected by the interrupt.

3.3.4.10 RTE and Format Error Exception

When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire core, any attempted R TE execution (where the format is not equal to {4,5,6,7}) generates a format error. The exception stack frame for the format error is created without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.

The selection of the format value provides some limited debug support for porting code from M68000 applications. On M68000 family processors, the SR was located at the top of the stack. On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE is attempted using this old format, it generates a format error on a ColdFire processor.

If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame.

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3.3.4.11 TRAP Instruction Exception

The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls. The TRAP instruction may be used to change from user to supervisor mode.

3.3.4.12 Unsupported Instruction Exception

If execution of a valid instruction is attempted but the required hardware is not present in the processor , an unsupported instruction exception is generated. The instruction functionality can then be emulated in the exception handler, if desired.

All ColdFire cores record the processor hardware configuration in the D0 register immediately after the negation of RESET. See Section 3.3.4.15, “Reset Exception,” for details.

3.3.4.13 Interrupt Exception

Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from the interrupt controller using an IACK cycle. See Chapter 14, “Interrupt Controller Module,” for details on the interrupt controller.

3.3.4.14 Fault-on-Fault Halt

If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to force the processor to exit this halted state.

3.3.4.15 Reset Exception

Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered.

The reset exception places the processor in the supervisor mode by setting the SR[S] bit and disables tracing by clearing the SR[T] bit. This exception also clears the SR[M] bit and sets the processor’s SR[I] bit to the highest level (level 7, 0b111). Next, the VBR is initialized to zero (0x0000_0000). The control registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly to the processor are disabled.

NOTE

Other implementation-specific registers are also affected. Refer to each module in this reference manual for details on these registers.

After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at address 0x0000_0000 is loaded into the supervisor stack pointer and the second longword at address 0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault state.

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ColdFire processors load hardware configuration information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM to determine the hardware configuration.

Information loaded into D0 defines the processor hardware configuration as shown in Figure 3-18.

BDM: Load: 0x080 (D0)

Store: 0x180 (D0)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R PF VER REV

Reset110011110010 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R MAC DIVEMACFPUMMU000 ISA DEBUG

Reset1100000010001001

Access: User read-only

BDM read-only

Figure 3-18. D0 Hardware Configuration Info

Table 3-9. D0 Hardware Configuration Info Field Description

Field Description

31–24PFProcessor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.

23–20

VER

ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core. 0001 V1 ColdFire core 0010 V2 ColdFire core (This is the value used for this device.) 0011 V3 ColdFire core 0100 V4 ColdFire core 0101 V5 ColdFire core Else Reserved for future use.

19–16

REV

MAC

EMAC

FPU

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Processor revision number. The default is 0b0000.

MAC present. This bit signals if the optional multiply-accumulate (MAC) execution engine is present in processor core. 0 MAC execute engine not present in core. 1 MAC execute engine is present in core. (This is the value used for this device.)

Divide present. This bit signals if the hardware divider (DIV) is present in the processor core.

DIV

0 Divide execute engine not present in core. 1 Divide execute engine is present in core. (This is the value used for this device.)

EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution engine is present in processor core. 0 EMAC execute engine not present in core. (This is the value used for this device.) 1 EMAC execute engine is present in core.

FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core. 0 FPU execute engine not present in core. (This is the value used for this device.) 1 FPU execute engine is present in core.

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Table 3-9. D0 Hardware Configuration Info Field Description (continued)

Field Description

MMU present. This bit signals if the optional virtual memory management unit (MMU) is present in processor core.

MMU

10–8 Reserved.

DEBUG

0 MMU execute engine not present in core. (This is the value used for this device.) 1 MMU execute engine is present in core.

7–4

ISA revision. This 4-bit field defines the instruction-set architecture (ISA) revision level implemented in ColdFire

ISA

processor core. 0000 ISA_A 0001 ISA_B 0010 ISA_C 1000 ISA_A+ (This is the value used for this device.) Else Reserved

3–0

Debug module revision number. This 4-bit field defines revision level of the debug module used in the ColdFire processor core. 0000 DEBUG_A 0001 DEBUG_B 0010 DEBUG_C 0011 DEBUG_D 0100 DEBUG_E 1001 DEBUG_B+ (This is the value used for this device.) 1011 DEBUG_D+ Else Reserved

ColdFire Core

Information loaded into D1 defines the local memory hardware configuration as shown in the figure below .

BDM: Load: 0x081 (D1)

Store: 0x181 (D1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RCLSZ CCAS CCSZ FLASHSZ 0000

Reset0001000010100000

1514131211109876543210

RMBSZ UCAS 0000 SRAMSZ 0000

Reset0001000001110000

Figure 3-19. D1 Hardware Configuration Info

Access: User read-only

BDM read-only

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Table 3-10. D1 Hardware Configuration Information Field Description

Field Description

31–30

CLSZ

29–28 CCAS

27–24 CCSZ

23–20

FLASHSZ

Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.

Configurable cache associativity. 00 Four-way 01 Direct mapped (This is the value used for this device) Else Reserved for future use

Configurable cache size. Indicates the amount of instruction/data cache.The cache configuration options available are 50% instruction/50% data, 100% instruction, or 100% data, and are specified in the CACR register. 0000 No configurable cache (This is the value used for this device) 0001 512B configurable cache 0010 1KB configurable cache 0011 2KB configurable cache 0100 4KB configurable cache 0101 8KB configurable cache 0110 16KB configurable cache 0111 32KB configurable cache Else Reserved

Flash bank size. 0000-0111 No flash 1000 64-Kbyte flash 1001 128-Kbyte flash 1010 256-Kbyte flash (This is the value used for this device) 1011 512-Kbyte flash Else Reserved for future use.

19–16 Reserved

15–14 MBSZ

Bus size. Defines the width of the ColdFire master bus datapath. 00 32-bit system bus datapath (This is the value used for this device) 01 64-bit system bus datapath Else Reserved

13–8 Reserved, resets to 0b010000

7–4

SRAMSZ

SRAM bank size. 0000 No SRAM 0001 512 bytes 0010 1 Kbytes 0011 2 Kbytes 0100 4 Kbytes 0101 8 Kbytes 0110 16 Kbytes 0111 32 Kbytes (This is the value used for this device) 1000 64 Kbytes 1001 128 Kbytes Else Reserved for future use

3-0 Reserved.

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3.3.5 Instruction Execution Timing

This section presents processor instruction execution times in terms of processor-core clock cycles. The number of operand references for each instruction is enclosed in parentheses following the number of processor clock cycles. Each timing entry is presented as C(R/W) where:

•C is the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution.

• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing a read-modify-write function is denoted as (1/1).

This section includes the assumptions concerning the timing values and the execution time details.

3.3.5.1 Timing Assumptions

For the timing data presented in this section, these assumptions apply:

1. The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or extension words.

2. The OEP does not experience any sequence-related pipeline stalls. The most common example of stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE operations (except MOVEM), certain hardware resources within the processor are marked as busy for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive STORE operations is two cycles. The MOVEM instruction uses a different set of resources and this stall does not apply.

3. The OEP completes all memory accesses without any stall conditions caused by the memory itself. Thus, the timing details provided in this section assume that an infinite zero-wait state memory is attached to the processor core.

4. All operand data accesses are aligned on the same byte boundary as the operand size; for example, 16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4 addresses.

The processor core decomposes misaligned operand references into a series of aligned accesses as shown in Table 3-11.

Table 3-11. Misaligned Operand References

address[1:0] Size

01 or 11 Word Byte, Byte 2(1/0) if read

01 or 11 Long Byte, Word,

10 Long Word, Word 2(1/0) if read

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Operations

Byte

Additional

C(R/W)

1(0/1) if write

3(2/0) if read

2(0/2) if write

1(0/1) if write

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3.3.5.2 MOVE Instruction Execution Times

Table 3-12 lists execution times for MOVE.{B,W} instructions; Table 3-13 lists timings for MOVE.L.

NOTE

For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode.

ET with {<ea> = (d16,PC)} equals ET with {<ea> = (d16,An)}

ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<ea> = (d8,An,Xi*SF)}

The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w and xxx.l.

Table 3-12. MOVE Byte and Word Execution Times

Destination

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1)

(Ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1)

-(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1)

(d16,Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,Ay,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

xxx.w 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

xxx.l 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1)) — — —

#xxx 1(0/0) 3(0/1) 3(0/1) 3(0/1) — — —

Table 3-13. MOVE Long Execution Times

Destination

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl

Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

(Ay)+ 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

-(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

(d16,Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

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Table 3-13. MOVE Long Execution Times (continued)

Destination

Source

Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl

(d8,Ay,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

(d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

(d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

#xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — —

3.3.5.3 Standard One Operand Instruction Execution Times

Table 3-14. One Operand Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

BITREVDx1(0/0)———— — ——

BYTEREVDx1(0/0)———— — ——

CLR.B <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

CLR.W <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

CLR.L <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

EXT.WDx1(0/0)———— — ——

EXT.LDx1(0/0)———— — ——

EXTB.LDx1(0/0)———— — ——

FF1Dx1(0/0)———— — ——

NEG.LDx1(0/0)———— — ——

NEGX.LDx1(0/0)———— — ——

NOT.LDx1(0/0)———— — ——

SCCDx1(0/0)———— — ——

SWAPDx1(0/0)———— — ——

TST.B <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

TST.W <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

TST.L <ea> 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)

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3.3.5.4 Standard Two Operand Instruction Execution Times

Table 3-15. Two Operand Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

ADD.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

ADD.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ADDI.L #imm,Dx 1(0/0) — — — — — — —

ADDQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ADDX.L Dy,Dx 1(0/0) — — — — — — —

AND.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

AND.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ANDI.L #imm,Dx 1(0/0) — — — — — — —

ASL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

ASR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

BCHG Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

BCHG #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

BCLR Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

BCLR #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

BSET Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

BSET #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

BTST Dy,<ea> 2(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —

BTST #imm,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — —

CMP.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

CMPI.L #imm,Dx 1(0/0) — — — — — — —

DIVS.W <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)

DIVU.W <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)

DIVS.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —

DIVU.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —

EOR.L Dy,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

EORI.L #imm,Dx 1(0/0) — — — — — — —

LEA <ea>,Ax — 1(0/0) — — 1(0/0) 2(0/0) 1(0/0) —

LSL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

LSR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0)

MOVEQ.L #imm,Dx — — — — — — — 1(0/0)

OR.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

OR.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

ORI.L #imm,Dx 1(0/0) — — — — — — —

(d16,An) (d16,PC)

(d8,An,Xn*SF) (d8,PC,Xn*SF)

xxx.wl #xxx

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Table 3-15. Two Operand Instruction Execution Times (continued)

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

(d16,An) (d16,PC)

(d8,An,Xn*SF) (d8,PC,Xn*SF)

REMS.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — — REMU.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —

SUB.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

SUB.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

SUBI.L #imm,Dx 1(0/0) — — — — — — —

SUBQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

SUBX.L Dy,Dx 1(0/0) — — — — — — —

3.3.5.5 Miscellaneous Instruction Execution Times

Table 3-16. Miscellaneous Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

ColdFire Core

xxx.wl #xxx

CPUSHL (Ax) — 11(0/1) — — — — — —

LINK.W Ay,#imm 2(0/1) — — — — — — —

MOVE.L Ay,USP 3(0/0) — — — — — — —

MOVE.L USP,Ax 3(0/0) — — — — — — —

MOVE.W CCR,Dx 1(0/0) — — — — — — —

MOVE.W <ea>,CCR 1(0/0) — — — — — — 1(0/0)

MOVE.W SR,Dx 1(0/0) — — — — — — —

MOVE.W <ea>,SR 7(0/0) — — — — — — 7(0/0)

MOVEC Ry,Rc 9(0/1) — — — — — — —

MOVEM.L <ea>,&list — 1+n(n/0) — — 1+n(n/0) — — —

MOVEM.L &list,<ea> — 1+n(0/n) — — 1+n(0/n) — — —

NOP 3(0/0)———— — ——

PEA <ea> — 2(0/1) — — 2(0/1)

3(0/1)

2(0/1) —

PULSE 1(0/0)———— — ——

STLDSR#imm————— — —5(0/1)

STOP#imm————— — —3(0/0)

TRAP#imm————— — —15(1/2)

TPF 1(0/0)———— — ——

TPF.W 1(0/0)———— — ——

TPF.L 1(0/0)———— — ——

UNLK Ax 2(1/0) — — — — — — —

WDDATA <ea> — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —

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Table 3-16. Miscellaneous Instruction Execution Times (continued)

Opcode <EA>

Effective Address

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

WDEBUG<ea> —5(2/0)— —5(2/0) — — —

The n is the number of registers moved by the MOVEM opcode.

If a MOVE.W #imm,SR instruction is executed and imm[13] equals 1, the execution time is 1(0/0).

The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.

PEA execution times are the same for (d16,PC).

PEA execution times are the same for (d8,PC,Xn*SF).

3.3.5.6 MAC Instruction Execution Times

Table 3-17. MAC Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An)

MAC.L Ry, Rx 3(0/0) — — — — — — —

MAC.L Ry, Rx, <ea>, Rw — 4(1/0) 4(1/0) 4(1/0) 4(1/0)

MAC.W Ry, Rx 1(0/0) — — — — — — —

MAC.W Ry, Rx, <ea>, Rw — 2(1/0) 2(1/0) 2(1/0) 2(1/0)

(d8,An, Xn*SF)

xxx.wl #xxx

———

MOVE.L <ea>y, Racc 1(0/0) — — — — — — 1(0/0)

MOVE.L <ea>y, MACSR 2(0/0) — — — — — — 2(0/0)

MOVE.L <ea>y, Rmask 1(0/0) — — — — — — 1(0/0)

MOVE.L Racc,<ea>x 1(0/0)

——— — — ——

MOVE.L MACSR,<ea>x 1(0/0) — — — — — — —

MOVE.L Rmask, <ea>x 1(0/0) — — — — — — —

MSAC.L Ry, Rx 3(0/0) — — — — — — —

MSAC.W Ry, Rx 1(0/0) — — — — — — —

MSAC.L Ry, Rx, <ea>, Rw — 4(1/0) 4(1/0) 4(1/0) 4(1/0)

MSAC.W Ry, Rx, <ea>, Rw — 2(1/0) 2(1/0) 2(1/0) 2(1/0)

———

MULS.L <ea>y, Dx 5(0/0) 7(1/0) 7(1/0) 7(1/0) 7(1/0) — — —

MULS.W <ea>y, Dx 3(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) 6(1/0) 5(1/0) 3(0/0)

MULU.L <ea>y, Dx 5(0/0) 7(1/0) 7(1/0) 7(1/0) 7(1/0) — — —

MULU.W <ea>y, Dx 3(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) 6(1/0) 5(1/0) 3(0/0)

Effective address of (d16,PC) not supported

Storing the accumulator requires one additional processor clock cycle when rounding is performed

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3.3.5.7 Branch Instruction Execution Times

Table 3-18. General Branch Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

BRA — — — — 2(0/1) — — —

BSR — — — — 3(0/1) — — —

JMP <ea> — 3(0/0) — — 3(0/0) 4(0/0) 3(0/0) —

JSR <ea> — 3(0/1) — — 3(0/1) 4(0/1) 3(0/1) —

RTE — — 10(2/0) — — — — —

RTS ——5(1/0)—————

Table 3-19. Bcc Instruction Execution Times

(d16,An)

(d16,PC)

(d8,An,Xi*SF) (d8,PC,Xi*SF)

xxx.wl #xxx

ColdFire Core

Opcode

Bcc 3(0/0) 1(0/0) 2(0/0) 3(0/0)

Forward

Taken

Forward

Not Taken

Backward

Taken

Backward Not Taken

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Chapter 4

Operand Y Operand X

Shift 0,1,-1

Accumulator(s)

Multiply-Accumulate Unit (MAC)

4.1 Introduction

This chapter describes the functionality, microarchitecture, and performance of the multiply-accumulate (MAC) unit in the ColdFire family of processors.

4.1.1 Overview

The MAC design provides a set of DSP operations that can improve the performance of embedded code while supporting the integer multiply instructions of baseline ColdFire architecture.

The MAC provides functionality in three related areas:

1. Signed and unsigned integer multiplication

2. Multiply-accumulate operations supporting signed and unsigned integer operands as well as signed, fixed-point, fractional operands

3. Miscellaneous register operations

The MAC features a three-stage execution pipeline optimized for 16-bit operands, with a 16x16 multiply array and a single 32-bit accumulator.

The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module (Figure 4-1).

4.1.1.1 Introduction to the MAC

The MAC is an extension of the basic multiplier in most microprocessors. It is typically implemented in hardware within an architecture and supports rapid execution of signal processing algorithms in fewer

Freescale Semiconductor 4-1

Figure 4-1. Multiply-Accumulate Functionality Diagram

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Multiply-Accumulate Unit (MAC)

yi() ak()yi k–()

k1=

N1–

∑

bk()xi k–()

k0=

N1–

∑

yi() bk()xi k–()

k0=

∑

b0()xi() b1()xi 1–()b2()xi 2–()b3()xi 3–()+++==

cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements beyond scope of any processor architecture and may require full DSP implementation.

To balance among speed, size, and functionality, the ColdFire MAC is optimized for a small set of operations that involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for single-cycle pipelined operations with a possible accumulation after product generation. This functionality is common in many signal processing applications. The ColdFire core architecture is also modified to allow an operand to be fetched in parallel with a multiply , increasing overall performance for certain DSP operations.

Consider a typical filtering operation where the filter is defined as in Equation 4-1.

Eqn. 4-1

Here, the output y(i) is determined by past output values and past input values. This is the general form of an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies and product summing. To show this point, reduce Equation 4-1 to a simple, four-tap FIR filter, shown in

Equation 4-2, in which the accumulated sum is a past data values and coefficients sum.

Eqn. 4-2

4.2 Memory Map/Register Definition

The following table and sections explain the MAC registers:

Table 4-1. MAC Memory Map

BDM

0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 4.2.1/4-2

0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF 4.2.2/4-4

0x806 Accumulator (ACC) 32 R/W Undefined 4.2.3/4-5

The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 28, “Debug Module.”

4.2.1 MAC Status Register (MACSR)

The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags. Operational mode bits control whether operands are signed or unsigned and whether they are treated as integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding is performed. Negative, zero, and overflow condition flags are also provided.

Width

(bits)

Access Reset Value Section/Page

4-2 Freescale Semiconductor

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BDM: 0x804 (MACSR) Access: Supervisor read/write

BDM read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 000000000 0 0 0 0000000

S/U F/I R/T N Z VC

OMC

Reset000000000000000000000000 0 0 0 0 0 0 0 0

Figure 4-2. MAC Status Register (MACSR)

Table 4-2. MACSR Field Descriptions

Field Description

31–8 Reserved, must be cleared.

OMC

S/U

F/I

Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set to the appropriate constant on any operation that overflows the accumulator. After saturation, the accumulator remains unaffected by any other MAC or MSAC instructions until the overflow bit is cleared or the accumulator is directly loaded.

Signed/unsigned operations.

In integer mode:

S/U determines whether operations performed are signed or unsigned. It also determines the accumulator value during saturation, if enabled. 0 Signed numbers. On overflow, if OMC is enabled, the accumulator saturates to the most positive

(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on the instruction and the product value that overflowed.

1 Unsigned numbers. On overflow, if OMC is enabled, the accumulator saturates to the smallest value

(0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.

In fractional mode:

S/U controls rounding while storing the accumulator to a general-purpose register. 0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose

1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when moved to

a general-purpose register. See Section 4.3.1.1, “Rounding”. The resulting 16-bit value is stored in the lower word of the destination register. The upper word is zero-filled. This rounding procedure does not affect the accumulator value.

Fractional/integer mode. Determines whether input operands are treated as fractions or integers. 0 Integers can be represented in signed or unsigned notation, depending on the value of S/U. 1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to

-15

for 16-bit fractions and -1 to 1 - 2

1-2

-31

for 32-bit fractions. See Section 4.3.4, “Data

Representation."

R/T

Round/truncate mode. Controls rounding procedure for MSAC.L instructions when in fractional mode. 0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator. 1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest

32-bit value. If the low-order 32 bits equal 0x8000_0000, the upper 32 bits are rounded to the nearest even (lsb = 0) value. See Section 4.3.1.1, “Rounding”.

2 Z

Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions.

Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions.

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Table 4-2. MACSR Field Descriptions (continued)

Field Description

0 Carry. This field is always zero.

Overflow. Set if an arithmetic overflow occurs, implying that the result cannot be represented in the operand size. After set, V remains set until the accumulator register is loaded with a new value or MACSR is directly loaded. MULS and MULU instructions do not change this value.

Table 4-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.

Table 4-3. Summary of S/U, F/I, and R/T Control Bits

S/U F/I R/T Operational Modes

0 0 x Signed, integer

0 1 0 Signed, fractional

Truncate on MAC.L and MSAC.L No round on accumulator stores

0 1 1 Signed, fractional

Round on MAC.L and MSAC.L No round on accumulator stores

1 0 x Unsigned, integer

1 1 0 Signed, fractional

Truncate on MAC.L and MSAC.L Round-to-16-bits on accumulator stores

1 1 1 Signed, fractional

Round on MAC.L and MSAC.L Round-to-16-bits on accumulator stores

4.2.2 Mask Register (MASK)

The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones.

This register performs a simple AND with the operand address for MAC instructions. That is, the processor calculates the normal operand address and, if enabled, that address is then ANDed with {0xFFFF , MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address can be constrained to a certain memory region. This is used primarily to implement circular queues with the (An)+ addressing mode.

This minimizes the addressing support required for filtering, convolution, or any routine that implements a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be included in all memory effective address calculations. The syntax is as follows:

mac.sz Ry,RxSF,<ea>y&,Rw

The & operator enables the MASK use and causes bit 5 of the extension word to be set. The exact algorithm for the use of MASK is:

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Multiply-Accumulate Unit (MAC)

if extension word, bit [5] = 1, the MASK bit, then

if <ea> = (An)

oa = An & {0xFFFF, MASK}

if <ea> = (An)+

oa = An An = (An + 4) & {0xFFFF, MASK}

if <ea> =-(An)

oa = (An - 4) & {0xFFFF, MASK} An = (An - 4) & {0xFFFF, MASK}

if <ea> = (d16,An)

oa = (An + se_d16) & {0xFFFF0x, MASK}

Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For auto-addressing modes of post-increment and pre-decrement, the updated An value calculation is also shown.

Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue implementations.

BDM: 0x805 (MASK) Access: User read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

R 1 1 1 1 1 111111111 1 1

Reset11111111111111111111111111111111

MASK

Figure 4-3. Mask Register (MASK)

Table 4-4. MASK Field Descriptions

Field Description

31–16 Reserved, must be set.

15–0

MASK

Performs a simple AND with the operand address for MAC instructions.

4.2.3 Accumulator Register (ACC)

The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers form the entire 48-bit result.

BDM: 0x806 (ACC) Access: User read/write

BDM read/write

313029282726252423222120191817161514131211109876543210

Reset––––––––––––––––––––––––––––––––

Figure 4-4. Accumulator Register (ACC)

Accumulator

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Multiply-Accumulate Unit (MAC)

Table 4-5. ACC Field Descriptions

Field Description

31–0

Accumulator

Store 32-bits of the result of the MAC operation.

4.3 Functional Description

The MAC speeds execution of ColdFire integer-multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC, execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early termination that the OEP normally uses if no MAC hardware is present.

The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of the product to or from the value in the accumulator. Optionally, the product may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions. Multiply-accumulate operations support 16- or 32-bit input operands these formats:

• Signed integers

• Unsigned integers

• Signed, fixed-point, fractional numbers

The MAC is optimized for 16-bit multiplications to keep the area consumption low. Two 16-bit operands produce a 32-bit product. Longword operations are performed by reusing the 16-bit multiplier array at the expense of a small amount of extra control logic. Again, the product of two 32-bit operands is a 32-bit result. For longword integer operations, only the least significant 32 bits of the product are calculated. For fractional operations, the entire 64-bit product is calculated and then truncated or rounded to a 32-bit result using the round-to-nearest (even) method.

Because the multiplier array is implemented in a three-stage pipeline, MAC instructions have an effective issue rate of 1 cycle for word operations, 3 cycles for longword integer operations, and 4 cycles for 32-bit fractional operations.

All arithmetic operations use register-based input operands, and summed values are stored in the accumulator. Therefore, an additional MOVE instruction is needed to store data in a general-purpose register.

The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP engines. New and existing ColdFire instructions can accommodate these requirements. A MOVEM instruction can efficiently move large data blocks by generating line-sized burst references. The ability to load an operand simultaneously from memory into a register and execute a MAC instruction makes some DSP operations such as filtering and convolution more manageable.

The programming model includes a mask register (MASK), which can optionally be used to generate an operand address during MAC + MOVE instructions. The register application with auto-increment addressing mode supports efficient implementation of circular data queues for memory operands.

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Multiply-Accumulate Unit (MAC)

4.3.1 Fractional Operation Mode

This section describes behavior when the fractional mode is used (MACSR[F/I] is set).

4.3.1.1 Rounding

When the processor is in fractional mode, there are two operations during which rounding can occur:

1. The 32-bit accumulator is moved into a general purpose register. If MACSR[S/U] is cleared, the accumulator is stored as is in the destination register; if it is set, the 32-bit value is rounded to a 16-bit value using the round-to-nearest (even) method. The resulting 16-bit number is stored in the lower word of the destination register. The upper word is zero-filled. The accumulator value is unaffected by this rounding procedure.

2. Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero, multiplying two 32-bit numbers creates a 64-bit product truncated to the upper 32 bits; otherwise, it is rounded using round-to-nearest (even) method.

T o understand the round-to-nearest-even method, consider the following example involving the rounding of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest 16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L.

• If R0.L is less than 0x8000, the result is truncated to the value of R0.U.

• If R0.L is greater than 0x8000, the upper word is incremented (rounded up).

• If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is based on the lsb of R0.U, so the result is always even (lsb = 0).

— If the lsb of R0.U equals 1 and R0.L equals 0x8000, the number is rounded up. — If the lsb of R0.U equals 0 and R0.L equals 0x8000, the number is rounded down.

This method minimizes rounding bias and creates as statistically correct an answer as possible. The rounding algorithm is summarized in the following pseudocode:

if R0.L < 0x8000

then Result = R0.U

else if R0.L > 0x8000

then Result = R0.U + 1

else if lsb of R0.U = 0 /* R0.L = 0x8000 */

then Result = R0.U

else Result = R0.U + 1

The round-to-nearest-even technique is also known as convergent rounding.

4.3.1.2 Saving and Restoring the MAC Programming Model

The presence of rounding logic in the MAC output datapath requires that special care during the MAC’s save/restore process. In particular, any result rounding modes must be disabled during the save/restore process so the exact bit-wise contents of the MAC registers are accessed. Consider the memory structure containing the MAC programming model:

struct macState {

int acc; int mask;

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Multiply-Accumulate Unit (MAC)

int macsr;

} macState;

The following assembly language routine shows the proper sequence for a correct MAC state save. This code assumes all Dn and An registers are available for use, and the memory location of the state save is defined by A7.

MAC_state_save:

move.l macsr,d7 ; save the macsr clr.l d0 ; zero the register to ... move.l d0,macsr ; disable rounding in the macsr move.l acc,d5; save the accumulator move.l mask,d6 ; save the address mask movem.l #0x00e0,(a7); move the state to memory

This code performs the MAC state restore:

MAC_state_restore:

movem.l (a7),#0x00e0; restore the state from memory move.l #0,macsr ; disable rounding in the macsr move.l d5,acc; restore the accumulator move.l d6,mask ; restore the address mask move.l d7,macsr ; restore the macsr

Executing this sequence type can correctly save and restore the exact state of the MAC programming model.

4.3.1.3 MULS/MULU

MULS and MULU are unaffected by fractional-mode operation; operands remain assumed to be integers.

4.3.1.4 Scale Factor in MAC or MSAC Instructions

The scale factor is ignored while the MAC is in fractional mode.

4.3.2 MAC Instruction Set Summary

Table 4-6 summarizes MAC unit instructions.

Table 4-6. MAC Instruction Summary

Command Mnemonic Description

Multiply Signed muls <ea>y,Dx Multiplies two signed operands yielding a signed result Multiply Unsigned mulu <ea>y,Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate mac Ry,RxSF

msac Ry,RxSF

Multiply Accumulate with Load

mac Ry,RxSF,Rw msac Ry,RxSF,Rw

Multiplies two operands, then adds/subtracts the product to/from the accumulator

Multiplies two operands, combines the product to the accumulator while loading a register with the memory operand

Load Accumulator move.l {Ry,#imm},ACC Loads the accumulator with a 32-bit operand Store Accumulator move.l ACC,Rx Writes the contents of the accumulator to a CPU register

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N1–

⋅()–2

i1N–+()–

ai⋅

i0=

N2–

∑

Table 4-6. MAC Instruction Summary (continued)

Command Mnemonic Description

Load MACSR move.l {Ry,#imm},MACSR Writes a value to MACSR Store MACSR move.l MACSR,Rx Write the contents of MACSR to a CPU register Store MACSR to CCR move.l MACSR,CCR Write the contents of MACSR to the CCR Load MAC Mask Reg move.l {Ry,#imm},MASK Writes a value to the MASK register Store MAC Mask Reg move.l MASK,Rx Writes the contents of the MASK to a CPU register

4.3.3 MAC Instruction Execution Times

The instruction execution times for the MAC can be found in Section 3.3.5.6, “MAC Instruction Execution

Times”.

4.3.4 Data Representation

MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand type:

1. Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2 < operand < 2

(N-1)

- 1. The binary point is right of the lsb.

2. Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2N - 1. The binary point is right of the lsb.

(N-1)

3. T wo’s complement, signed fractional: In an N-bit number , the first bit is the sign bit. The remaining bits signify the first N-1 bits after the binary point. Given an N-bit number , a

N-1aN-2aN-3

... a2a1a0,

its value is given by the equation in Equation 4-3.

Eqn. 4-3

This format can represent numbers in the range -1 < operand < 1-2

(N-1)

For words and longwords, the largest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively . The largest positive word is 0x7FFF or (1 - 2

-31

the most positive longword is 0x7FFF_FFFF or (1 - 2

4.3.5 MAC Opcodes

MAC opcodes are described in the ColdFire Programmer’s Reference Manual. Remember the following:

• Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that involves the product and the accumulator.

• The overflow (V) flag is managed differently . It is set if the complete product cannot be represented as a 32-bit value (this applies to 32 × 32 integer operations only) or if the combination of the product with the accumulator cannot be represented in the given number of bits. This indicator is

-15

);

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Multiply-Accumulate Unit (MAC)

treated as a sticky flag, meaning after set, it remains set until the accumulator or the MACSR is directly loaded. See Section 4.2.1, “MAC Status Register (MACSR)”.

• The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is added to or subtracted from the accumulator. W ithout this operator , the product is not shifted. If the MAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because a product can overflow, the following guidelines are implemented:

— For unsigned word and longword operations, a zero is shifted into the product on right shifts. — For signed, word operations, the sign bit is shifted into the product on right shifts unless the

product is zero. For signed, longword operations, the sign bit is shifted into the product unless an overflow occurs or the product is zero, in which case a zero is shifted in.

— For all left shifts, a zero is inserted into the lsb position.

The following pseudocode explains basic MAC or MSAC instruction functionality. This example is presented as a case statement covering the three basic operating modes with signed integers, unsigned integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {}, indicates a concatenation operation.

switch (MACSR[6:5]) /* MACSR[S/U, F/I] */ {

case 0: /* signed integers */

if (MACSR.OMC == 0 || MACSR.V == 0)

then {

MACSR.V = 0 /* select the input operands */ if (sz == word)

then {if (U/Ly == 1)

then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]} else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]}

if (U/Lx == 1)

then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}

else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]} } else {operandY[31:0] = Ry[31:0]

operandX[31:0] = Rx[31:0]

}

/* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0]

/* check for product overflow */ if ((product[63:31] != 0x0000_0000_0) && (product[63:31] != 0xffff_ffff_1))

then { /* product overflow */

MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1)

then if (product[63] == 1)

then result[31:0] = 0x7fff_ffff else result[31:0] = 0x8000_0000

else if (MACSR.OMC == 1)

then /* overflowed MAC,

saturationMode enabled */

if (product[63] == 1)

then result[31:0] = 0x8000_0000

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else result[31:0] = 0x7fff_ffff

}

/* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ {

case 0: /* no scaling specified */

break;

case 1: /* SF = “<< 1” */

if (product[31] ^ product[30])

then {MACSR.V = 1

if (inst == MSAC && MACSR.OMC == 1)

then if (product[63] == 1)

then result[31:0] = 0x7fff_ffff else result[31:0] = 0x8000_0000

else if (MACSR.OMC == 1)

then /* overflowed MAC,

saturationMode enabled */

if (product[63] == 1)

then result[31:0] = 0x8000_0000

else result[31:0] = 0x7fff_ffff } else product[31:0] = {product[30:0], 0}

break;

case 2: /* reserved encoding */

break;

case 3: /* SF = “>> 1” */

if (MACSR.OMC == 0 || MACSR.V = 0)

then product[31:0] = {product[31], product[31:1]}

break;

}

Multiply-Accumulate Unit (MAC)

/* combine with accumulator */ if (MACSR.V == 0)

then {if (inst == MSAC)

then result[31:0] = acc[31:0] - product[31:0] else result[31:0] = acc[31:0] + product[31:0]

}

/* check for accumulation overflow */ if (accumulationOverflow == 1)

then {MACSR.V = 1

if (MACSR.OMC == 1)

then /* accumulation overflow,

saturationMode enabled */

if (result[31] == 1)

then result[31:0] = 0x7fff_ffff else result[31:0] = 0x8000_0000

}

/* transfer the result to the accumulator */ acc[31:0] = result[31:0] MACSR.N = result[31] if (result[31:0] == 0x0000_0000)

then MACSR.Z = 1 else MACSR.Z = 0

}

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Multiply-Accumulate Unit (MAC)

break; case 1: case 3: /* signed fractionals */

if (MACSR.OMC == 0 || MACSR.V == 0)

then {

MACSR.V = 0 if (sz == word)

then {if (U/Ly == 1)

then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], 0x0000}

if (U/Lx == 1)

then operandX[31:0] = {Rx[31:16], 0x0000}

else operandX[31:0] = {Rx[15:0], 0x0000} } else {operandY[31:0] = Ry[31:0]

operandX[31:0] = Rx[31:0]

}

/* perform the multiply */ product[63:0] = (operandY[31:0] * operandX[31:0]) << 1

/* check for product rounding */ if (MACSR.R/T == 1)

then { /* perform convergent rounding */

if (product[31:0] > 0x8000_0000)

then product[63:32] = product[63:32] + 1

else if ((product[31:0] == 0x8000_0000) && (product[32] == 1))

then product[63:32] = product[63:32] + 1

}

/* combine with accumulator */ if (inst == MSAC)

then result[31:0] = acc[31:0] - product[63:32] else result[31:0] = acc[31:0] + product[63:32]

/* check for accumulation overflow */ if (accumulationOverflow == 1)

then {MACSR.V = 1

if (MACSR.OMC == 1)

then /* accumulation overflow,

saturationMode enabled */

if (result[31] == 1)

then result[31:0] = 0x7fff_ffff else result[31:0] = 0x8000_0000

}

/* transfer the result to the accumulator */ acc[31:0] = result[31:0] MACSR.N = result[31] if (result[31:0] == 0x0000_0000)

then MACSR.Z = 1 else MACSR.Z = 0

}

break;

case 2: /* unsigned integers */

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if (MACSR.OMC == 0 || MACSR.V == 0)

then {

MACSR.V = 0 /* select the input operands */ if (sz == word)

then {if (U/Ly == 1)

then operandY[31:0] = {0x0000, Ry[31:16]}

else operandY[31:0] = {0x0000, Ry[15:0]}

if (U/Lx == 1)

then operandX[31:0] = {0x0000, Rx[31:16]}

else operandX[31:0] = {0x0000, Rx[15:0]} } else {operandY[31:0] = Ry[31:0]

operandX[31:0] = Rx[31:0]

}

/* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0]

/* check for product overflow */ if (product[63:32] != 0x0000_0000)

then { /* product overflow */

MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1)

then result[31:0] = 0x0000_0000

else if (MACSR.OMC == 1)

then /* overflowed MAC,

}

Multiply-Accumulate Unit (MAC)

saturationMode enabled */

result[31:0] = 0xffff_ffff

/* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ {

case 0: /* no scaling specified */

break;

case 1: /* SF = “<< 1” */

if (product[31] == 1)

then {MACSR.V = 1

if (inst == MSAC && MACSR.OMC == 1)

then result[31:0] = 0x0000_0000 else if (MACSR.OMC == 1)

then /* overflowed MAC,

saturationMode enabled */

result[31:0] = 0xffff_ffff } else product[31:0] = {product[30:0], 0}

break;

case 2: /* reserved encoding */

break;

case 3: /* SF = “>> 1” */

product[31:0] = {0, product[31:1]} break;

}

/* combine with accumulator */ if (MACSR.V == 0)

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Multiply-Accumulate Unit (MAC)

then {if (inst == MSAC)

}

/* check for accumulation overflow */ if (accumulationOverflow == 1)

then {MACSR.V = 1

}

/* transfer the result to the accumulator */ acc[31:0] = result[31:0] MACSR.N = result[31] if (result[31:0] == 0x0000_0000)

then MACSR.Z = 1 else MACSR.Z = 0

}

break;}

then result[31:0] = acc[31:0] - product[31:0] else result[31:0] = acc[31:0] + product[31:0]

if (inst == MSAC && MACSR.OMC == 1)

then result[31:0] = 0x0000_0000 else if (MACSR.OMC == 1)

then /* overflowed MAC,

saturationMode enabled */

result[31:0] = 0xffff_ffff

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Chapter 5 Static RAM (SRAM)

5.1 Introduction

This chapter describes the on-chip static RAM (SRAM) implementation, including general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM.

5.1.1 Overview

The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. The location of the memory block can be specified to any 0-modulo-16K address. The memory is ideal for storing critical code or data structures or for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can service processor-initiated accesses or memory-referencing commands from the debug module.

The SRAM is dual-ported to provide access. The SRAM is partitioned into two physical memory arrays to allow simultaneous access to arrays by the processor core and another bus master . For more information see Chapter 12, “System Control Module (SCM).”

5.1.2 Features

The major features includes:

• One 16 Kbyte SRAM

• Single-cycle access

• Physically located on the processor's high-speed local bus

• Memory location programmable on any 0-modulo-16 Kbyte address

• Byte, word, and longword address capabilities

5.2 Memory Map/Register Description

The SRAM programming model shown in Table 5-1 includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management.

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Static RAM (SRAM)

Table 5-1. SRAM Programming Model

Rc[11:0]

The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 28, “Debug Module.”

0xC05 RAM Base Address Register (RAMBAR) 32 R/W See Section Yes 5.2.1/5-2

Supervisor Access Only Registers

Width

(bits)

Access Reset Value

Written

w/ MOVEC

Section/Page

5.2.1 SRAM Base Address Register (RAMBAR)

The configuration information in the SRAM base-address register (RAMBAR) controls the operation of the SRAM module.

• The RAMBAR holds the SRAM base address. The MOVEC instruction provides write-only access to this register.

• The RAMBAR can be read or written from the debug module.

• All undefined bits in the register are reserved. These bits are ignored during writes to the RAMBAR and return zeroes when read from the debug module.

• A reset clears the RAMBAR’s valid bit. This invalidates the processor port to the SRAM (The RAMBAR must be initialized before the core can access the SRAM.) All other bits are unaffected.

The RAMBAR contains several control fields. These fields are shown in Figure 5-1.

Rc[11:0]: 0x0C05 (RAMBAR) Access: User write-only

Debug read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ResetUUUUUUUUUUUUUUUUUUUU 0 0 0 U 0 0 U U U U U 0

0 0

PRIU PRIL SPV WP

0 0

C/I SC SD UC UD V

Figure 5-1. SRAM Base Address Register (RAMBAR)

Table 5-2. RAMBAR Field Descriptions

Field Description

31–14

13–12 Reserved, should be cleared.

Base Address. Defines the 0-modulo-32K base address of the SRAM module. By programming this field, the SRAM may be located on any 32-Kbyte boundary.

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Table 5-2. RAMBAR Field Descriptions (continued)

PRIU,PRIL Upper Bank Priority Lower Bank Priority

00 01 CPU 10 CPU 11 CPU CPU

Field Description

Static RAM (SRAM)

11–10

PRIU

PRIL

SPV

7–6 Reserved, must be cleared.

5–1

C/I, SC, SD, UC,

Priority Bit. PRIU determines if DMA or CPU has priority in the upper 16K bank of memory. PRIL determines if DMA or CPU has priority in the lower 16K bank of memory. If a bit is set, the CPU has priority. If a bit is cleared, DMA has priority. Priority is determined according to the following table:

Note: The recommended setting (maximum performance) for the priority bits is 00.

Secondary port valid. Allows access by DMA. 0 DMA access to memory is disabled. 1 DMA access to memory is enabled. Note: The SPV bit in the second RAMBAR register must also be set to allow dual port access to the SRAM.

For more information, see Section 12.5.2, “Memory Base Address Register (RAMBAR).”

Write Protect. Allows only read accesses to the SRAM. When this bit is set, any attempted write access from the core generates an access error exception to the ColdFire processor core. 0 Allows core read and write accesses to the SRAM module 1 Allows only core read accesses to the SRAM module Note: This bit does not affect non-core write accesses.

Address Space Masks (ASn). These five bit fields allow types of accesses to be masked or inhibited from accessing the SRAM module. The address space mask bits are: C/I = CPU space/interrupt acknowledge cycle mask SC = Supervisor code address space mask SD = Supervisor data address space mask UC = User code address space mask UD = User data address space mask

For each address space bit: 0 An access to the SRAM module can occur for this address space 1 Disable this address space from the SRAM module. If a reference using this address space is made, it

is inhibited from accessing the SRAM module and is processed like any other non-SRAM reference. These bits are useful for power management as detailed in Section 5.3.2, “Power Management.” In most applications, the C/I bit is set

Valid. When set, this bit enables the SRAM module; otherwise, the module is disabled. A hardware reset clears this bit. 0 Contents of RAMBAR are not valid 1 Contents of RAMBAR are valid

5.3 Initialization/Application Information

After a hardware reset, the SRAM module contents are undefined. The valid bit of the RAMBAR is cleared, disabling the processor port into the memory . If the SRAM requires initialization with instructions or data, perform the following steps:

1. Load the RAMBAR, mapping the SRAM module to the desired location within the address space.

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Static RAM (SRAM)

2. Read the source data and write it to the SRAM. Various instructions support this function, including memory-to-memory move instructions, or the MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this opcode generally provides maximum performance.

3. After the data loads into the SRAM, it may be appropriate to load a revised value into the RAMBAR with a new set of attributes. These attributes consist of the write-protect and address space mask fields.

The ColdFire processor or an external debugger using the debug module can perform these initialization functions.

5.3.1 SRAM Initialization Code

The following code segment describes how to initialize the SRAM. The code sets the base address of the SRAM at 0x2000_0000 and initializes the SRAM to zeros.

RAMBASE EQU 0x20000000 ;set this variable to 0x20000000 RAMVALID EQU 0x00000001

move.l #RAMBASE+RAMVALID,D0 ;load RAMBASE + valid bit into D0. movec.l D0, RAMBAR ;load RAMBAR and enable SRAM

The following loop initializes the entire SRAM to zero:

lea.l RAMBASE,A0 ;load pointer to SRAM move.l #8192,D0 ;load loop counter into D0 (SRAM size/4)

SRAM_INIT_LOOP:

clr.l (A0)+ ;clear 4 bytes of SRAM clr.l (A0)+ ;clear 4 bytes of SRAM clr.l (A0)+ ;clear 4 bytes of SRAM clr.l (A0)+ ;clear 4 bytes of SRAM subq.l #4,D0 ;decrement loop counter bne.b SRAM_INIT_LOOP ;if done, then exit; else continue looping

5.3.2 Power Management

If the SRAM is used only for data operands, setting the ASn bits associated with instruction fetches can decrease power dissipation. Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power dissipation. Table 5-3 shows examples of typical RAMBAR settings.

Table 5-3. Typical RAMBAR Setting Examples

Data Contained in SRAM RAMBAR[7:0]

Instruction Only 0x2B

Data Only 0x35

Instructions and Data 0x21

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Chapter 6 Clock Module

6.1 Introduction

The clock module allows the device to be configured for one of several clocking methods. Clocking modes include internal phase-locked loop (PLL) clocking with an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device directly. The clock module contains the following:

• Crystal amplifier and oscillator (OSC)

• Phase-locked loop (PLL)

• Reduced frequency divider (RFD)

• Status and control registers

• Control logic

• Real-time clock (RTC) oscillator

6.2 Features

Features of the clock module include the following:

• 1- to 48-MHz crystal, 8-MHz on-chip relaxation oscillator , or e xternal oscillator reference options

• 2- to 10-MHz reference crystal oscillator for normal PLL mode

• External RTC/backup oscillator (nominal frequency 32.768 kHz)

• System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator

• Support for low-power modes

• Separate clock out signal

(0 ≤ n ≤ 15) low-power divider for extremely low frequency operation

•2

6.3 Modes of Operation

The clock module can be operated in backup watchdog timer mode, RTC mode, normal PLL mode (default), 1:1 PLL mode, or external clock mode (PLL disabled).

6.3.1 Backup Watchdog Timer Mode

In this mode, the backup watchdog timer is disabled after POR (power on reset), and the clock input to this timer is the system clock. The selection of the clock source for the secondary watchdog timer module can occur only once per POR. Thus, if the relaxation oscillator is selected as the timer’s input source, subsequent attempts to select the relaxation oscillator as the system clock’s source are blocked until the

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Clock Module

next POR. If the relaxation oscillator was already selected as the system clock’ s source and is subsequently selected as the timer’s input source, the system and the timer can use the oscillator as the source.

6.3.2 RTC Mode

A dedicated R TC oscillator can be selected to run the RTC circuitry. In normal operation, this oscillator is powered by the VDDPLL and VSSPLL pins. When the part is shut down, this oscillator is powered by the VSTBY pin. The nominal expected frequency for the RTC oscillator is 32.768 kHz, but can range from 32 kHz to 38.4 kHz.

6.3.3 Normal PLL Mode

In normal PLL mode, the PLL is fully programmable. It can synthesize frequencies ranging from 1x to 18x the reference frequency and has a post divider capable of reducing this synthesized frequency without disturbing the PLL. The PLL reference can be a crystal oscillator or an external clock.

6.3.4 1:1 PLL Mode

In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external clock input reference frequency. The post divider is not active.

6.3.5 External Clock Mode

In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL. The resulting operating frequency is equal to the external clock frequency.

6.4 Low-Power Mode Operation

This subsection describes the operation of the clock module in low-power and halted modes of operation. Low-power modes are described in Chapter 8, “Power Management.” Table 6-1 shows the clock module operation in low-power modes.

Table 6-1. Clock Module Operation in Low-power Modes

Low-power Mode Clock Operation Mode Exit

Wait Clocks sent to peripheral modules only Exit not caused by clock module, but normal

clocking resumes upon mode exit

Doze Clocks sent to peripheral modules only Exit not caused by clock module, but normal

clocking resumes upon mode exit

Stop All system clocks disabled Exit not caused by clock module, but clock

sources are re-enabled and normal clocking resumes upon mode exit

Halted Normal Exit not caused by clock module

In wait and doze modes, the system clocks to the peripherals are enabled and the clocks to the CPU and SRAM are stopped. Each module can disable its clock locally at the module level.

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Clock Module

In stop mode, all system clocks are disabled. There are several options for enabling or disabling the PLL or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time. The PLL can be disabled in stop mode, but requires a wakeup period before it can relock. The oscillator can also be disabled during stop mode, but requires a wakeup period to restart.

When the PLL is enabled in stop mode (STPMD[1:0]), the external CLKOUT signal can support systems using CLKOUT as the clock source.

There is also a fast wakeup option for quickly enabling the system clocks during stop recovery. This eliminates the wakeup recovery time but at the risk of sending a potentially unstable clock to the system. To prevent a non-locked PLL frequency overshoot when using the fast wakeup option, change the RFD divisor to the current RFD value plus one before entering stop mode.

In external clock mode, there are no wakeup periods for oscillator startup or PLL lock.

6.5 Block Diagram

Figure 6-1 shows a block diagram of the entire clock module.

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Clock Module

EXTAL

CLKMOD1

CLKSRC

PLL

Low Power

Divider

LPD[3:0]

Reference Clock

ADC auto-standby clock

PPRMH[11]

CFM

PPRMH[9]

PWM

PPRMH[8]

GPT

PPRMH[7]

ADC

PPRMH[4:3]

PPRMH[1]

Edge Port

PPRMH[0]

GPIO / Ports

STOP MODE

CLKOUT

PPRML[17]

Interrupt Controller

PPRML[16:13]

DMA Timers

PPRML[10]

QSPI

PPRML[9]

I2C

PPRML[7:5

UARTs

PPRML[4]

DMA

ColdFire V2 Core

BDM

PITs

DISCLK

PPRML[1]

÷ 2

System Clock (f

sys

)

Pre-

Divider

USB_CTRL

USB

USB_ALT_CLK

CCHR

ON-CHIP 8 MHz

OSCILLATOR

EXTERNAL

OSCILLATOR

XTAL

CLKMOD0

See note

below

Note: Must be 48 MHz for USB

operation.

6-4 Freescale Semiconductor

Figure 6-1. Clock Module Block Diagram

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Clock Module

6.6 Signal Descriptions

The clock module signals are summarized in Table 6-2 and a brief description follows. For more detailed information, refer to Chapter 2, “Signal Descriptions.”

Table 6-2. Signal Properties

Name Function

EXTAL Oscillator or clock input

XTAL Oscillator output

CLKOUT System clock output

CLKMOD[1:0] Clock mode select inputs

RSTO

Reset signal from reset controller

6.6.1 EXTAL

This input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator.

6.6.2 XTAL

This output is an internal oscillator connection to the external crystal. If CLKMOD0 is driven low during reset, XTAL is sampled to determine clocking mode.

6.6.3 CLKOUT

This output reflects the internal system clock.

6.6.4 CLKMOD[1:0]

These inputs are used to select the clock mode during chip configuration as described in Table 6-3.

Table 6-3. Clocking Modes

CLKMOD[1:0] XTAL Clocking Mode

00 0 PLL disabled, clock driven by external oscillator

00 1 PLL disabled, clock driven by on-chip oscillator

01 N/A PLL disabled, clock driven by external crystal

10 0 PLL in normal mode, clock driven by external oscillator

10 1 PLL in normal mode, clock driven by on-chip oscillator

11 N/A PLL in normal mode, clock driven by external crystal

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Clock Module

6.6.5 RSTO

The RSTO pin is asserted by one of the following:

• Internal system reset signal

• FRCRSTOUT bit in the reset control status register (RCR); see Section 10.5.1, “Reset Control

6.7 Memory Map and Registers

The clock module programming model shown in Table 6-4 consists of registers that define clock operation and status as well as additional peripheral power management registers.

Table 6-4. Clock Module Memory Map

IPSBAR

Offset

0x12_0000 Synthesizer Control Register (SYNCR) 16 R/W 0x1002 6.7.1.1/6-7

0x12_0002 Synthesizer Status Register (SYNSR) 8 R 0x00 6.7.1.2/6-9

0x12_0004 Relaxation Oscillator Control Register (ROCR) 16 R/W See note

0x12_0007 Low Power Divider Register (LPDR) 8 R/W 0x00 6.7.1.4/6-11

0x12_0008 Clock Control High Register (CCHR) 8 R/W 0x05 6.7.1.5/6-12

0x12_0009 Clock Control Low Register (CCLR) 8 R/W See note

0x12_000A Oscillator Control High Register (OCHR) 8 R/W See note

0x12_000B Oscillator Control Low Register (OCLR) 8 R/W See note

0x12_0012 Real Time Clock Control Register (RTCCR) 8 R/W 0x00 6.7.1.9/6-15

0x12_0013 Backup Watchdog Timer Control Register (BWCR) 8 R/W 0x00

0x000C Peripheral Power Management Register High (PPMRH)

0x0018 Peripheral Power Management Register Low (PPMRL)

Addresses not assigned to a register and undefined register bits are reserved for expansion.

The reset value for ROCR is loaded during reset from the flash information row (bits [9:0]). The bits reset to 0b10_0000_0000 during Power-On Reset.

CCLR reset state determined during reset configuration.

OCHR reset state determined during reset configuration.

OCLR reset state determined during reset configuration.

The contents of BWCR are reset only during Power-On Reset; they are preserved during a warm reset.

See Section 8.2.1, “Peripheral Power Management Registers (PPMRH, PPMRL).”

Supervisor Mode Access Only

Width

(bits)

Access Reset Value Section/Page

32 R/W 0x00 8.2.1/8-2

32 R/W 0x01 8.2.1/8-2

6.7.1.3/6-11

6.7.1.6/6-12

6.7.1.7/6-13

6.7.1.8/6-14

6.7.1.10/6-16

6.7.1 Register Descriptions

This subsection provides a description of the clock module registers.

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

6-6 Freescale Semiconductor

Freescale Semiconductor MCF52210, MCF52212, MCF52213, MCF52211 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Chapter 1 Overview

1.1 MCF52211 Family Configurations

1.2 Block Diagram

1.3 Part Numbers and Packaging

1.2 Features

1.2.1 V2 Core Overview

1.2.2 Integrated Debug Module

1.2.3 JTAG

1.2.4 On-Chip Memories

1.2.5 Power Management

1.2.6 USB On-The-Go Controller

1.2.7 UARTs

1.2.8 I2C Bus

1.2.9 QSPI

1.2.10 Fast ADC

1.2.12 General Purpose Timer (GPT)

1.2.13 Periodic Interrupt Timers (PIT0 and PIT1)

1.2.14 Real-Time Clock (RTC)

1.2.15 Pulse-Width Modulation (PWM) Timers

1.2.16 Software Watchdog Timer

1.2.17 Backup Watchdog Timer

1.2.18 Phase-Locked Loop (PLL)

1.2.19 Interrupt Controller (INTC)

1.2.20 DMA Controller

1.2.21 Reset

1.2.22 GPIO

Chapter 2 Signal Descriptions

2.1 Introduction

2.2 Overview

2.3 Pin Functions

2.4 Reset Signals

2.5 PLL and Clock Signals

2.6 Mode Selection

2.7 External Interrupt Signals

2.8 Queued Serial Peripheral Interface (QSPI)

2.9 I2C I/O Signals

2.10 UART Module Signals

2.11 DMA Timer Signals

2.12 ADC Signals

2.13 General Purpose Timer Signals

2.14 Pulse-Width Modulator Signals

2.15 Debug Support Signals

2.16 EzPort Signal Descriptions

2.17 Power and Ground Pins

3.1 Introduction

3.1.1 Overview

3.2 Memory Map/Register Description

3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)

3.2.4 Condition Code Register (CCR)

3.2.5 Program Counter (PC)

3.2.6 Vector Base Register (VBR)

3.2.7 Status Register (SR)

3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR)

3.3 Functional Description

3.3.1 Version 2 ColdFire Microarchitecture

3.3.2 Instruction Set Architecture (ISA_A+)

3.3.3 Exception Processing Overview

3.3.4 Processor Exceptions

3.3.5 Instruction Execution Timing

4.1 Introduction

4.1.1 Overview

4.2 Memory Map/Register Definition

4.2.1 MAC Status Register (MACSR)

4.2.2 Mask Register (MASK)

4.2.3 Accumulator Register (ACC)

4.3 Functional Description

4.3.1 Fractional Operation Mode

4.3.2 MAC Instruction Set Summary

4.3.3 MAC Instruction Execution Times

4.3.4 Data Representation

4.3.5 MAC Opcodes

Chapter 5 Static RAM (SRAM)

5.1 Introduction

5.1.1 Overview

5.1.2 Features

5.2 Memory Map/Register Description