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MCF51QE128RM
User Manual
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Freescale Semiconductor MCF51QE128RM User Manual

Microcontrollers
freescale.com
ColdFire
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MCF51QE128 MCF51QE64 MCF51QE32
Reference Manual
MCF51QE128 Series Features
• 32-Bit Version 1 ColdFire® Central Processor Unit (CPU) – Up to 50.33-MHz ColdFire CPU from 3.6V to 2.1V , and
20-MHz CPU at 2.1V to 1.8V across temperature range of -40°C to 85°C
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
performance when running from internal RAM
(0.76 DMIPS/MHz from flash) – Implements Instruction Set Revision C (ISA_C) – Support for up to 30 peripheral interrupt requests and
seven software interrupts
•On-Chip Memory – Flash read/program/erase over full operating voltage
and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes – Two low power stop modes; reduced power wait mode – Peripheral clock enable register can disable clocks to
unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode
– Very low power external oscillator can be used in stop3
mode to provide accurate clock to active peripherals
– Very low power real time counter for use in run, wait,
and stop modes with internal and external clock sources
–6 μs typical wake up time from stop modes
• Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator;
Crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — FLL controlled by
internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports CPU freq. from 2 to 50.33 MHz
• System Protection – Watchdog computer operating properly (COP) reset
with option to run from dedicated 1-kHz internal clock source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode and illegal address detection with
programmable reset or exception response
– Flash block protection
• Development Support – Single-wire background debug interface – 4 PC plus 2 address (optional data) breakpoint registers
with programmable 1- or 2-level trigger response
– 64-entry processor status and debug data trace buffer
with programmable start/stop conditions
• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V
• ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3
• SCIx — Two SCIs with full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge
• SPIx— Two serial peripheral interfaces with Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; MSB-first or LSB-first shifting
• IICx — Two IICs with; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing
• TPMx — One 6-channel and two 3-channel; Selectable input capture, output compare, or buffered edge- or center-aligned PWMs on each channel
• RTC — 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components
• Input/Output – 70 GPIOs and 1 input-only and 1 output-only pin – 16 KBI interrupts with selectable polarity – Hysteresis and configurable pull-up device on all input
pins; Configurable slew rate and drive strength on all
output pins. – SET/CLR registers on 16 pins (PTC and PTE) – 16 bits of Rapid GPIO connected to the CPU’s
high-speed local bus with set, clear, and toggle
functionality
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MCF51QE128 Reference Manual
Covers MCF51QE128
MCF51QE64 MCF51QE32
Related Documentation:
• MCF51QE128 (Data Sheet)
Contains pin assignments and diagrams, all electrical specififications, and mechanical drawing outlines.
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http://www.freescale.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
MCF51QE128RM
Rev. 3
09/2007
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MCF51QE128 MCU Series Reference Manual, Rev. 3
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Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Devices in the MCF51QE128/64/32 Series ....................................................................................23
1.2 MCU Block Diagram ......................................................................................................................24
1.3 V1 ColdFire Core ............................................................................................................................26
1.4 System Clocks .................................................................................................................................26
1.4.1 Internal Clock Source (ICS) Module ................................................................................26
1.4.2 System Clock Distribution ................................................................................................27
1.4.3 ICS Modes of Operation ...................................................................................................29
1.4.3.1 FLL Engaged Internal (FEI) ...........................................................................29
1.4.3.2 FLL Engaged External (FEE) .........................................................................29
1.4.3.3 FLL Bypassed Internal (FBI) ..........................................................................29
1.4.3.4 FLL Bypassed Internal Low-Power (FBILP) .................................................29
1.4.3.5 FLL Bypassed External (FBE) .......................................................................29
1.4.3.6 FLL Bypassed External Low-Power (FBELP) ...............................................30
1.4.3.7 Stop (STOP) ....................................................................................................30
Chapter 2
Pins and Connections
2.1 Device Pin Assignment ...................................................................................................................33
2.2 Recommended System Connections ...............................................................................................35
2.2.1 Power ................................................................................................................................37
2.2.2 Oscillator ...........................................................................................................................37
2.2.3 RESET and RSTO ............................................................................................................37
2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................38
2.2.5 ADC Reference Pins (V
2.2.6 General-Purpose I/O and Peripheral Ports ........................................................................39
REFH
, V
) .............................................................................39
REFL
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................43
3.2 Features ...........................................................................................................................................43
3.3 Overview .........................................................................................................................................44
3.4 Debug Mode ....................................................................................................................................48
3.5 Secure Mode ....................................................................................................................................48
3.6 Run Modes ......................................................................................................................................49
3.6.1 Run Mode .........................................................................................................................49
3.6.2 Low-Power Run Mode (LPrun) ........................................................................................49
3.6.2.1 BDM in Low-Power Run Mode .....................................................................49
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Section Number Title Page
3.7 Wait Modes ......................................................................................................................................50
3.7.1 Wait Mode .........................................................................................................................50
3.7.2 Low-Power Wait Mode (LPwait) ......................................................................................50
3.7.2.1 BDM in Low-Power Wait Mode .....................................................................50
3.8 Stop Modes ......................................................................................................................................50
3.8.1 Stop2 Mode .......................................................................................................................51
3.8.1.1 Low-Range Oscillator Considerations for Stop2 ............................................52
3.8.2 Stop3 Mode .......................................................................................................................52
3.8.3 Stop4: Low Voltage Detect or BDM Enabled in Stop Mode ............................................52
3.9 On-Chip Peripheral Modules in Stop and Low-Power Modes ........................................................53
Chapter 4
Memory
4.1 MCF51QE128/64/32 Memory Map ................................................................................................57
4.2 Register Addresses and Bit Assignments ........................................................................................58
4.2.1 Flash Module Reserved Memory Locations .....................................................................67
4.2.2 ColdFire Rapid GPIO Memory Map ................................................................................69
4.2.3 ColdFire Interrupt Controller Memory Map .....................................................................69
4.3 RAM ................................................................................................................................................70
4.4 Flash ................................................................................................................................................70
4.4.1 Features .............................................................................................................................71
4.4.2 Register Descriptions ........................................................................................................72
4.4.2.1 Flash Clock Divider Register (FCDIV) ..........................................................72
4.4.2.2 Flash Options Register (FOPT and NVOPT) ..................................................72
4.4.2.3 Flash Configuration Register (FCNFG) .........................................................73
4.4.2.4 Flash Protection Register (FPROT and NVPROT) ........................................74
4.4.2.5 Flash Status Register (FSTAT) ........................................................................76
4.4.2.6 Flash Command Register (FCMD) .................................................................77
4.5 Function Description .......................................................................................................................77
4.5.1 Flash Command Operations ..............................................................................................77
4.5.1.1 Writing the FCDIV Register ...........................................................................78
4.5.1.2 Command Write Sequence ..............................................................................79
4.5.2 Flash Commands ...............................................................................................................80
4.5.2.1 Erase Verify Command ...................................................................................80
4.5.2.2 Program Command .........................................................................................81
4.5.2.3 Burst Program Command ...............................................................................83
4.5.2.4 Sector Erase Command ...................................................................................84
4.5.2.5 Mass Erase Command ....................................................................................86
4.5.3 Illegal Flash Operations ....................................................................................................87
4.5.3.1 Flash Access Violations ..................................................................................87
4.5.3.2 Flash Protection Violations .............................................................................88
4.5.4 Operating Modes ...............................................................................................................88
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Section Number Title Page
4.5.4.1 Wait Mode .......................................................................................................88
4.5.4.2 Stop Modes .....................................................................................................88
4.5.4.3 Background Debug Mode ...............................................................................88
4.5.5 Security .............................................................................................................................89
4.5.5.1 Unsecuring the MCU using Backdoor Key Access ........................................89
4.5.6 Resets ................................................................................................................................90
4.5.6.1 Flash Reset Sequence ......................................................................................90
4.5.6.2 Reset While Flash Command Active ..............................................................90
4.5.6.3 Program and Erase Times ...............................................................................90
4.6 Security ............................................................................................................................................91
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction .....................................................................................................................................93
5.2 Features ...........................................................................................................................................93
5.3 Microcontroller Reset ......................................................................................................................93
5.3.1 Computer Operating Properly (COP) Watchdog ..............................................................94
5.3.2 Illegal Operation Reset .....................................................................................................95
5.3.3 Illegal Address Reset ........................................................................................................95
5.4 Interrupts and Exceptions ................................................................................................................95
5.4.1 External Interrupt Request (IRQ) Pin ...............................................................................95
5.4.1.1 Pin Configuration Options ..............................................................................95
5.4.1.2 Edge and Level Sensitivity .............................................................................96
5.4.1.3 External Interrupt Initialization ......................................................................96
5.5 Low-Voltage Detect (LVD) System ................................................................................................96
5.5.1 Power-On Reset Operation ...............................................................................................96
5.5.2 LVD Reset Operation ........................................................................................................97
5.5.3 LVD Interrupt Operation ...................................................................................................97
5.5.4 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................97
5.6 Peripheral Clock Gating ..................................................................................................................97
5.7 Reset, Interrupt, and System Control Registers and Control Bits ...................................................97
5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................98
5.7.2 System Reset Status Register (SRS) .................................................................................99
5.7.3 System Options Register 1 (SOPT1) ..............................................................................100
5.7.4 System Options Register 2 (SOPT2) ..............................................................................101
5.7.5 System Device Identification Register (SDIDH, SDIDL) ..............................................102
5.7.6 System Power Management Status and Control 1 Register (SPMSC1) .........................103
5.7.7 System Power Management Status and Control 2 Register (SPMSC2) .........................104
5.7.8 System Power Management Status and Control 3 Register (SPMSC3) .........................105
5.7.9 System Clock Gating Control 1 Register (SCGC1) ........................................................107
5.7.10 System Clock Gating Control 2 Register (SCGC2) ........................................................107
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Section Number Title Page
Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction ........................................................................................................113
6.2 Pull-up, Slew Rate, and Drive Strength ........................................................................................114
6.2.1 Port Internal Pull-up Enable ...........................................................................................114
6.2.2 Port Slew Rate Enable ....................................................................................................114
6.2.3 Port Drive Strength Select ..............................................................................................115
6.3 Port Data Set, Clear and Toggle Data Registers ............................................................................115
6.3.1 Port Data Set Registers ...................................................................................................116
6.3.2 Port Data Clear Registers ................................................................................................116
6.3.3 Port Data Toggle Register ............................................................................................... 116
6.4 V1 ColdFire Rapid GPIO Functionality ........................................................................................116
6.5 Keyboard Interrupts .......................................................................................................................116
6.5.1 Edge Only Sensitivity .....................................................................................................117
6.5.2 Edge and Level Sensitivity .............................................................................................117
6.5.3 Pull-up/Pull-down Resistors ...........................................................................................117
6.5.4 Keyboard Interrupt Initialization ....................................................................................118
6.6 Pin Behavior in Stop Modes ..........................................................................................................118
6.7 Parallel I/O, Keyboard Interrupt, and Pin Control Registers ........................................................118
6.7.1 Port A Registers ..............................................................................................................118
6.7.1.1 Port A Data Register (PTAD) .......................................................................119
6.7.1.2 Port A Data Direction Register (PTADD) ....................................................119
6.7.1.3 Port A Pull Enable Register (PTAPE) ...........................................................119
6.7.1.4 Port A Slew Rate Enable Register (PTASE) .................................................120
6.7.1.5 Port A Drive Strength Selection Register (PTADS) .....................................120
6.7.2 Port B Registers ..............................................................................................................121
6.7.2.1 Port B Data Register (PTBD) ........................................................................121
6.7.2.2 Port B Data Direction Register (PTBDD) .....................................................121
6.7.2.3 Port B Pull Enable Register (PTBPE) ...........................................................122
6.7.2.4 Port B Slew Rate Enable Register (PTBSE) .................................................122
6.7.2.5 Port B Drive Strength Selection Register (PTBDS) .....................................123
6.7.3 Port C Registers ..............................................................................................................123
6.7.3.1 Port C Data Register (PTCD) ........................................................................123
6.7.3.2 Port C Data Direction Register (PTCDD) .....................................................124
6.7.3.3 Port C Data Set Register (PTCSET) .............................................................124
6.7.3.4 Port C Data Clear Register (PTCCLR) .........................................................124
6.7.3.5 Port C Toggle Register (PTCTOG) ...............................................................125
6.7.3.6 Port C Pull Enable Register (PTCPE) ...........................................................125
6.7.3.7 Port C Slew Rate Enable Register (PTCSE) .................................................126
6.7.3.8 Port C Drive Strength Selection Register (PTCDS) .....................................126
6.7.4 Port D Registers ..............................................................................................................126
6.7.4.1 Port D Data Register (PTDD) .......................................................................126
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6.7.4.2 Port D Data Direction Register (PTDDD) ....................................................127
6.7.4.3 Port D Pull Enable Register (PTDPE) ..........................................................127
6.7.4.4 Port D Slew Rate Enable Register (PTDSE) ................................................128
6.7.4.5 Port D Drive Strength Selection Register (PTDDS) .....................................128
6.7.5 Port E Registers ..............................................................................................................128
6.7.5.1 Port E Data Register (PTED) ........................................................................128
6.7.5.2 Port E Data Direction Register (PTEDD) .....................................................129
6.7.5.3 Port E Data Set Register (PTESET) ..............................................................129
6.7.5.4 Port E Data Clear Register (PTECLR) .........................................................130
6.7.5.5 Port E Toggle Register (PTETOG) ...............................................................130
6.7.5.6 Port E Pull Enable Register (PTEPE) ...........................................................130
6.7.5.7 Port E Slew Rate Enable Register (PTESE) .................................................131
6.7.5.8 Port E Drive Strength Selection Register (PTEDS) ......................................131
6.7.6 Port F Registers ...............................................................................................................132
6.7.6.1 Port F Data Register (PTFD) ........................................................................132
6.7.6.2 Port F Data Direction Register (PTFDD) .....................................................132
6.7.6.3 Port F Pull Enable Register (PTFPE) ............................................................132
6.7.6.4 Port F Slew Rate Enable Register (PTFSE) ..................................................133
6.7.6.5 Port F Drive Strength Selection Register (PTFDS) ......................................133
6.7.7 Port G Registers ..............................................................................................................134
6.7.7.1 Port G Data Register (PTGD) .......................................................................134
6.7.7.2 Port G Data Direction Register (PTGDD) ....................................................134
6.7.7.3 Port G Pull Enable Register (PTGPE) ..........................................................135
6.7.7.4 Port G Slew Rate Enable Register (PTGSE) ................................................135
6.7.7.5 Port G Drive Strength Selection Register (PTGDS) .....................................135
6.7.8 Port H Registers ..............................................................................................................136
6.7.8.1 Port H Data Register (PTHD) .......................................................................136
6.7.8.2 Port H Data Direction Register (PTHDD) ....................................................136
6.7.8.3 Port H Pull Enable Register (PTHPE) ..........................................................137
6.7.8.4 Port H Slew Rate Enable Register (PTHSE) ................................................137
6.7.8.5 Port H Drive Strength Selection Register (PTHDS) .....................................137
6.7.9 Port J Registers ...............................................................................................................138
6.7.9.1 Port J Data Register (PTJD) ..........................................................................138
6.7.9.2 Port J Data Direction Register (PTJDD) .......................................................138
6.7.9.3 Port J Pull Enable Register (PTJPE) .............................................................139
6.7.9.4 Port J Slew Rate Enable Register (PTJSE) ...................................................139
6.7.9.5 Port J Drive Strength Selection Register (PTJDS) ........................................139
6.7.10 Keyboard Interrupt 1 (KBI1) Registers ..........................................................................140
6.7.10.1 KBI1 Interrupt Status and Control Register (KBI1SC) ................................140
6.7.10.2 KBI1 Interrupt Pin Select Register (KBI1PE) ..............................................141
6.7.10.3 KBI1 Interrupt Edge Select Register (KBI1ES) ...........................................141
6.7.11 Keyboard Interrupt 1 (KBI2) Registers ..........................................................................141
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6.7.11.1 KBI2 Interrupt Status and Control Register (KBI2SC) ................................142
6.7.11.2 KBI2 Interrupt Pin Select Register (KBI2PE) ..............................................142
6.7.11.3 KBI2 Interrupt Edge Select Register (KBI2ES) ...........................................143
Chapter 7
ColdFire Core
7.1 Introduction ...................................................................................................................................145
7.1.1 Overview .........................................................................................................................145
7.2 Memory Map/Register Description ...............................................................................................146
7.2.1 Data Registers (D0–D7) ..................................................................................................147
7.2.2 Address Registers (A0–A6) ............................................................................................148
7.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) ..................................................148
7.2.4 Condition Code Register (CCR) .....................................................................................149
7.2.5 Program Counter (PC) ....................................................................................................150
7.2.6 Vector Base Register (VBR) ...........................................................................................150
7.2.7 CPU Configuration Register (CPUCR) ..........................................................................151
7.2.8 Status Register (SR) ........................................................................................................152
7.3 Functional Description ..................................................................................................................153
7.3.1 Instruction Set Architecture (ISA_C) .............................................................................153
7.3.2 Exception Processing Overview .....................................................................................154
7.3.2.1 Exception Stack Frame Definition ................................................................156
7.3.2.2 S08 and ColdFire Exception Processing Comparison ..................................157
7.3.3 Processor Exceptions ......................................................................................................159
7.3.3.1 Access Error Exception ................................................................................159
7.3.3.2 Address Error Exception ...............................................................................159
7.3.3.3 Illegal Instruction Exception .........................................................................160
7.3.3.4 Privilege Violation ........................................................................................161
7.3.3.5 Trace Exception ............................................................................................161
7.3.3.6 Unimplemented Line-A Opcode ...................................................................162
7.3.3.7 Unimplemented Line-F Opcode ...................................................................162
7.3.3.8 Debug Interrupt .............................................................................................162
7.3.3.9 RTE and Format Error Exception .................................................................162
7.3.3.10 TRAP Instruction Exception .........................................................................163
7.3.3.11 Unsupported Instruction Exception ..............................................................163
7.3.3.12 Interrupt Exception .......................................................................................163
7.3.3.13 Fault-on-Fault Halt .......................................................................................163
7.3.3.14 Reset Exception ............................................................................................164
7.3.4 Instruction Execution Timing .........................................................................................167
7.3.4.1 Timing Assumptions .....................................................................................167
7.3.4.2 MOVE Instruction Execution Times ............................................................168
7.3.4.3 Standard One Operand Instruction Execution Times ...................................169
7.3.4.4 Standard Two Operand Instruction Execution Times ...................................170
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7.3.4.5 Miscellaneous Instruction Execution Times .................................................171
7.3.4.6 Branch Instruction Execution Times .............................................................172
Chapter 8
Interrupt Controller (CF1_INTC)
8.1 Introduction ...................................................................................................................................173
8.1.1 Overview .........................................................................................................................174
8.1.2 Features ...........................................................................................................................177
8.1.3 Modes of Operation ........................................................................................................178
8.2 External Signal Description ..........................................................................................................178
8.3 Memory Map and Register Definition ..........................................................................................178
8.3.1 Memory Map ..................................................................................................................179
8.3.2 Register Descriptions ......................................................................................................179
8.3.2.1 INTC Force Interrupt Register (INTC_FRC) ...............................................179
8.3.2.2 INTC Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6}) .....
180
8.3.2.3 INTC Wake-up Control Register (INTC_WCR) ..........................................181
8.3.2.4 INTC Set Interrupt Force Register (INTC_SFRC) .......................................182
8.3.2.5 INTC Clear Interrupt Force Register (INTC_CFRC) ...................................183
8.3.2.6 INTC Software and Level-n IACK Registers (n = 1,2,3,...,7) ......................184
8.3.3 Interrupt Request Level and Priority Assignments .........................................................185
8.4 Functional Description ..................................................................................................................187
8.4.1 Handling of Non-Maskable Level 7 Interrupt Requests .................................................187
8.5 Initialization Information ..............................................................................................................188
8.6 Application Information ................................................................................................................188
8.6.1 Emulation of the HCS08’s 1-Level IRQ Handling .........................................................188
8.6.2 Using INTC_PL6P{7,6} Registers .................................................................................189
8.6.3 More on Software IACKs ...............................................................................................189
Chapter 9
Rapid GPIO (RGPIO)
9.1 Introduction ...................................................................................................................................193
9.1.1 Overview .........................................................................................................................195
9.1.2 Features ...........................................................................................................................197
9.1.3 Modes of Operation ........................................................................................................198
9.2 External Signal Description ..........................................................................................................198
9.2.1 Overview .........................................................................................................................198
9.2.2 Detailed Signal Descriptions ..........................................................................................198
9.3 Memory Map/Register Definition .................................................................................................199
9.3.1 Memory Map ..................................................................................................................199
9.3.2 Register Descriptions ......................................................................................................200
9.3.2.1 RGPIO Data Direction (RGPIO_DIR) .........................................................200
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9.3.2.2 RGPIO Data (RGPIO_DATA) ......................................................................200
9.3.2.3 RGPIO Pin Enable (RGPIO_ENB) ..............................................................201
9.3.2.4 RGPIO Clear Data (RGPIO_CLR) ...............................................................201
9.3.2.5 RGPIO Set Data (RGPIO_SET) ...................................................................202
9.3.2.6 RGPIO Toggle Data (RGPIO_TOG) ............................................................202
9.4 Functional Description ..................................................................................................................203
9.5 Initialization Information ..............................................................................................................203
9.6 Application Information ................................................................................................................203
9.6.1 Application 1: Simple Square-Wave Generation ............................................................203
9.6.2 Application 2: 16-bit Message Transmission using SPI Protocol ...................................204
Chapter 10
Analog Comparator 3V (ACMPVLPV1)
10.1 Introduction ...................................................................................................................................207
10.1.1 ACMP Configuration Information ..................................................................................207
10.1.2 ACMP/TPM Configuration Information ........................................................................207
10.1.3 ACMP Clock Gating .......................................................................................................207
10.1.4 Interrupt Vectors .............................................................................................................208
10.1.5 Features ...........................................................................................................................211
10.1.6 Modes of Operation ........................................................................................................211
10.1.6.1 Wait Mode Operation ....................................................................................211
10.1.6.2 Stop3 Mode Operation ..................................................................................211
10.1.6.3 Stop2 Mode Operation ..................................................................................211
10.1.6.4 Active Background Mode Operation ............................................................211
10.1.7 Block Diagram ................................................................................................................211
10.2 External Signal Description ..........................................................................................................212
10.3 Register Definition ........................................................................................................................212
10.3.1 Status and Control Register (ACMPxSC) .......................................................................212
10.4 Functional Description ..................................................................................................................213
10.5 Interrupts .......................................................................................................................................213
Chapter 11
Analog-to-Digital Converter (S08ADC12V1)
11.1 Introduction ...................................................................................................................................215
11.1.1 ADC Clock Gating ..........................................................................................................215
11.1.2 Module Configurations ...................................................................................................217
11.1.2.1 Channel Assignments ...................................................................................217
11.1.2.2 Alternate Clock .............................................................................................217
11.1.2.3 Hardware Trigger ..........................................................................................218
11.1.2.4 Temperature Sensor ......................................................................................218
11.1.3 Interrupt Vectors .............................................................................................................218
11.1.4 Features ...........................................................................................................................219
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11.1.5 Block Diagram ................................................................................................................219
11.2 External Signal Description ..........................................................................................................220
11.2.1 Analog Power (V
11.2.2 Analog Ground (V
11.2.3 Voltage Reference High (V
11.2.4 Voltage Reference Low (V
11.2.5 Analog Channel Inputs (ADx) ........................................................................................221
11.3 Register Definition ........................................................................................................................221
11.3.1 Status and Control Register 1 (ADCSC1) ......................................................................221
11.3.2 Status and Control Register 2 (ADCSC2) ......................................................................223
11.3.3 Data Result High Register (ADCRH) .............................................................................223
11.3.4 Data Result Low Register (ADCRL) ..............................................................................224
11.3.5 Compare Value High Register (ADCCVH) ....................................................................224
11.3.6 Compare Value Low Register (ADCCVL) .....................................................................225
11.3.7 Configuration Register (ADCCFG) ................................................................................225
11.3.8 Pin Control 1 Register (APCTL1) ..................................................................................226
11.3.9 Pin Control 2 Register (APCTL2) ..................................................................................227
11.3.10Pin Control 3 Register (APCTL3) ..................................................................................228
11.4 Functional Description ..................................................................................................................229
11.4.1 Clock Select and Divide Control ....................................................................................230
11.4.2 Input Select and Pin Control ...........................................................................................230
11.4.3 Hardware Trigger ............................................................................................................230
11.4.4 Conversion Control .........................................................................................................230
11.4.4.1 Initiating Conversions ................................................................................... 231
11.4.4.2 Completing Conversions ...............................................................................231
11.4.4.3 Aborting Conversions ...................................................................................231
11.4.4.4 Power Control ...............................................................................................232
11.4.4.5 Sample Time and Total Conversion Time ....................................................232
11.4.5 Automatic Compare Function .........................................................................................233
11.4.6 MCU Wait Mode Operation ............................................................................................233
11.4.7 MCU Stop3 Mode Operation ..........................................................................................234
11.4.7.1 Stop3 Mode With ADACK Disabled ............................................................234
11.4.7.2 Stop3 Mode With ADACK Enabled .............................................................234
11.4.8 MCU Stop2 Mode Operation ..........................................................................................234
11.5 Initialization Information ..............................................................................................................234
11.5.1 ADC Module Initialization Example .............................................................................235
11.5.1.1 Initialization Sequence .................................................................................. 235
11.5.1.2 Pseudo-Code Example ..................................................................................235
11.6 Application Information ................................................................................................................236
11.6.1 External Pins and Routing ..............................................................................................236
11.6.1.1 Analog Supply Pins ......................................................................................237
11.6.1.2 Analog Reference Pins ..................................................................................237
) ..................................................................................................221
DDAD
) .................................................................................................221
SSAD
) ...................................................................................221
REFH
) ....................................................................................221
REFL
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11.6.1.3 Analog Input Pins .........................................................................................237
11.6.2 Sources of Error ..............................................................................................................238
11.6.2.1 Sampling Error .............................................................................................. 238
11.6.2.2 Pin Leakage Error .........................................................................................238
11.6.2.3 Noise-Induced Errors ....................................................................................238
11.6.2.4 Code Width and Quantization Error .............................................................239
11.6.2.5 Linearity Errors ............................................................................................. 239
11.6.2.6 Code Jitter, Non-Monotonicity, and Missing Codes .....................................240
Chapter 12
Internal Clock Source (S08ICSV3)
12.1 Introduction ...................................................................................................................................243
12.1.1 External Oscillator ..........................................................................................................243
12.1.2 Stop2 Mode Considerations ............................................................................................243
12.1.3 Features ...........................................................................................................................247
12.1.4 Block Diagram ................................................................................................................248
12.1.5 Modes of Operation ........................................................................................................248
12.1.5.1 FLL Engaged Internal (FEI) .........................................................................248
12.1.5.2 FLL Engaged External (FEE) .......................................................................248
12.1.5.3 FLL Bypassed Internal (FBI) ........................................................................248
12.1.5.4 FLL Bypassed Internal Low Power (FBILP) ...............................................249
12.1.5.5 FLL Bypassed External (FBE) .....................................................................249
12.1.5.6 FLL Bypassed External Low Power (FBELP) .............................................249
12.1.5.7 Stop (STOP) ..................................................................................................249
12.2 External Signal Description ..........................................................................................................249
12.3 Register Definition ........................................................................................................................249
12.3.1 ICS Control Register 1 (ICSC1) .....................................................................................250
12.3.2 ICS Control Register 2 (ICSC2) .....................................................................................251
12.3.3 ICS Trim Register (ICSTRM) .........................................................................................251
12.3.4 ICS Status and Control (ICSSC) .....................................................................................252
12.4 Functional Description ..................................................................................................................254
12.4.1 Operational Modes ..........................................................................................................254
12.4.1.1 FLL Engaged Internal (FEI) .........................................................................254
12.4.1.2 FLL Engaged External (FEE) .......................................................................255
12.4.1.3 FLL Bypassed Internal (FBI) ........................................................................255
12.4.1.4 FLL Bypassed Internal Low Power (FBILP) ...............................................255
12.4.1.5 FLL Bypassed External (FBE) .....................................................................255
12.4.1.6 FLL Bypassed External Low Power (FBELP) .............................................256
12.4.1.7 Stop ...............................................................................................................256
12.4.2 Mode Switching ..............................................................................................................256
12.4.3 Bus Frequency Divider ...................................................................................................256
12.4.4 Low Power Bit Usage .....................................................................................................257
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12.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................257
12.4.6 Internal Reference Clock ................................................................................................257
12.4.7 External Reference Clock ...............................................................................................257
12.4.8 Fixed Frequency Clock ...................................................................................................258
12.4.9 The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source. ICSFFCLK frequency must be no more than 1/4 of the ICSOUT frequency to be valid. Local Clock 258
Chapter 13
Inter-Integrated Circuit (S08IICV2)
13.1 Introduction ...................................................................................................................................259
13.1.1 Module Configuration .....................................................................................................259
13.1.2 Interrupt Vectors .............................................................................................................259
13.1.3 Features ...........................................................................................................................262
13.1.4 Modes of Operation ........................................................................................................262
13.1.5 Block Diagram ................................................................................................................263
13.2 External Signal Description ..........................................................................................................263
13.2.1 SCL — Serial Clock Line ...............................................................................................263
13.2.2 SDA — Serial Data Line ................................................................................................263
13.3 Register Definition ........................................................................................................................263
13.3.1 IIC Address Register (IICA) ...........................................................................................264
13.3.2 IIC Frequency Divider Register (IICF) ..........................................................................264
13.3.3 IIC Control Register (IICC1) ..........................................................................................267
13.3.4 IIC Status Register (IICS) ...............................................................................................268
13.3.5 IIC Data I/O Register (IICD) ..........................................................................................269
13.3.6 IIC Control Register 2 (IICC2) .......................................................................................269
13.4 Functional Description ..................................................................................................................270
13.4.1 IIC Protocol .....................................................................................................................270
13.4.1.1 Start Signal ....................................................................................................271
13.4.1.2 Slave Address Transmission .........................................................................271
13.4.1.3 Data Transfer .................................................................................................272
13.4.1.4 Stop Signal ....................................................................................................272
13.4.1.5 Repeated Start Signal ....................................................................................272
13.4.1.6 Arbitration Procedure ...................................................................................272
13.4.1.7 Clock Synchronization .................................................................................. 273
13.4.1.8 Handshaking .................................................................................................273
13.4.1.9 Clock Stretching ............................................................................................273
13.4.2 10-bit Address .................................................................................................................274
13.4.2.1 Master-Transmitter Addresses a Slave-Receiver ..........................................274
13.4.2.2 Master-Receiver Addresses a Slave-Transmitter ..........................................274
13.4.3 General Call Address ......................................................................................................275
13.5 Resets ............................................................................................................................................275
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13.6 Interrupts .......................................................................................................................................275
13.6.1 Byte Transfer Interrupt ....................................................................................................275
13.6.2 Address Detect Interrupt .................................................................................................275
13.6.3 Arbitration Lost Interrupt ................................................................................................275
13.7 Initialization/Application Information ..........................................................................................277
Chapter 14
Real-Time Counter (S08RTCV1)
14.1 Introduction ...................................................................................................................................281
14.1.1 ADC Hardware Trigger ..................................................................................................281
14.1.2 RTC Clock Sources .........................................................................................................281
14.1.3 RTC Modes of Operation ................................................................................................281
14.1.3.1 RTC Status after Stop2 Wakeup ....................................................................281
14.1.3.2 Clocks in Stop Modes ...................................................................................281
14.1.4 RTC Clock Gating ..........................................................................................................281
14.1.5 Interrupt Vector ...............................................................................................................282
14.1.6 Features ...........................................................................................................................284
14.1.7 Modes of Operation ........................................................................................................284
14.1.7.1 Wait Mode .....................................................................................................284
14.1.7.2 Stop Modes ...................................................................................................284
14.1.7.3 Active Background Mode .............................................................................284
14.1.8 Block Diagram ................................................................................................................285
14.2 External Signal Description ..........................................................................................................285
14.3 Register Definition ........................................................................................................................285
14.3.1 RTC Status and Control Register (RTCSC) ....................................................................286
14.3.2 RTC Counter Register (RTCCNT) ..................................................................................287
14.3.3 RTC Modulo Register (RTCMOD) ................................................................................287
14.4 Functional Description ..................................................................................................................287
14.4.1 RTC Operation Example .................................................................................................288
14.5 Initialization/Application Information ..........................................................................................289
Chapter 15
Serial Communications Interface (S08SCIV4)
15.1 Introduction ...................................................................................................................................291
15.1.1 SCI Clock Gating ............................................................................................................291
15.1.2 Interrupt Vectors .............................................................................................................291
15.1.3 Features ...........................................................................................................................295
15.1.4 Modes of Operation ........................................................................................................295
15.1.5 Block Diagram ................................................................................................................296
15.2 Register Definition ........................................................................................................................298
15.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................298
15.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................299
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15.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................300
15.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................301
15.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................303
15.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................304
15.2.7 SCI Data Register (SCIxD) .............................................................................................305
15.3 Functional Description ..................................................................................................................305
15.3.1 Baud Rate Generation .....................................................................................................305
15.3.2 Transmitter Functional Description ................................................................................306
15.3.2.1 Send Break and Queued Idle ........................................................................306
15.3.3 Receiver Functional Description ....................................................................................307
15.3.3.1 Data Sampling Technique .............................................................................307
15.3.3.2 Receiver Wakeup Operation .........................................................................308
15.3.3.2.1Idle-Line Wakeup .....................................................................308
15.3.3.2.2Address-Mark Wakeup .............................................................309
15.3.4 Interrupts and Status Flags ..............................................................................................309
15.3.5 Additional SCI Functions ...............................................................................................310
15.3.5.1 8- and 9-Bit Data Modes ...............................................................................310
15.3.5.2 Stop Mode Operation ....................................................................................310
15.3.5.3 Loop Mode ....................................................................................................310
15.3.5.4 Single-Wire Operation ..................................................................................311
Chapter 16
Serial Peripheral Interface (S08SPIV3)
16.1 Introduction ...................................................................................................................................313
16.1.1 SPI Clock Gating ............................................................................................................313
16.1.2 Interrupt Vector ...............................................................................................................313
16.1.3 Features ...........................................................................................................................317
16.1.4 Block Diagrams ..............................................................................................................317
16.1.4.1 SPI System Block Diagram ..........................................................................317
16.1.4.2 SPI Module Block Diagram ..........................................................................318
16.1.5 SPI Baud Rate Generation ..............................................................................................319
16.2 External Signal Description ..........................................................................................................320
16.2.1 SPSCK — SPI Serial Clock ............................................................................................320
16.2.2 MOSI — Master Data Out, Slave Data In ......................................................................320
16.2.3 MISO — Master Data In, Slave Data Out ......................................................................320
16.2.4 SS
16.3 Modes of Operation .......................................................................................................................321
16.3.1 SPI in Stop Modes ..........................................................................................................321
16.4 Register Definition ........................................................................................................................321
16.4.1 SPI Control Register 1 (SPIxC1) ....................................................................................321
16.4.2 SPI Control Register 2 (SPIxC2) ....................................................................................322
16.4.3 SPI Baud Rate Register (SPIxBR) ..................................................................................323
— Slave Select ..........................................................................................................320
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16.4.4 SPI Status Register (SPIxS) ............................................................................................324
16.4.5 SPI Data Register (SPIxD) .............................................................................................325
16.5 Functional Description ..................................................................................................................325
16.5.1 SPI Clock Formats ..........................................................................................................326
16.5.2 SPI Interrupts ..................................................................................................................328
16.5.3 Mode Fault Detection .....................................................................................................329
Chapter 17
Timer/Pulse-Width Modulator (S08TPMV3)
17.1 Introduction ...................................................................................................................................331
17.1.1 ACMP/TPM Configuration Information ........................................................................331
17.1.2 TPM Clock Gating ..........................................................................................................331
17.1.3 Interrupt Vector ...............................................................................................................331
17.1.4 Features ...........................................................................................................................335
17.1.5 Modes of Operation ........................................................................................................335
17.1.6 Block Diagram ................................................................................................................336
17.2 Signal Description .........................................................................................................................338
17.2.1 Detailed Signal Descriptions ..........................................................................................338
17.2.1.1 EXTCLK — External Clock Source ............................................................339
17.2.1.2 TPMxCHn — TPM Channel n I/O Pin(s) ....................................................339
17.3 Register Definition ........................................................................................................................341
17.3.1 TPM Status and Control Register (TPMxSC) ................................................................341
17.3.2 TPM Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................342
17.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................343
17.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................344
17.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................346
17.4 Functional Description ..................................................................................................................347
17.4.1 Counter ............................................................................................................................347
17.4.1.1 Counter Clock Source ...................................................................................347
17.4.1.2 Counter Overflow and Modulo Reset ...........................................................348
17.4.1.3 Counting Modes ............................................................................................ 349
17.4.1.4 Manual Counter Reset ..................................................................................349
17.4.2 Channel Mode Selection .................................................................................................349
17.4.2.1 Input Capture Mode ......................................................................................349
17.4.2.2 Output Compare Mode .................................................................................349
17.4.2.3 Edge-Aligned PWM Mode ...........................................................................350
17.4.2.4 Center-Aligned PWM Mode .........................................................................351
17.5 Reset Overview .............................................................................................................................352
17.5.1 General ............................................................................................................................352
17.5.2 Description of Reset Operation .......................................................................................352
17.6 Interrupts .......................................................................................................................................352
17.6.1 General ............................................................................................................................352
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17.6.2 Description of Interrupt Operation .................................................................................353
17.6.2.1 Timer Overflow Interrupt (TOF) Description ...............................................353
17.6.2.1.1Normal Case .............................................................................353
17.6.2.1.2Center-Aligned PWM Case ......................................................354
17.6.2.2 Channel Event Interrupt Description ............................................................354
17.6.2.2.1Input Capture Events ................................................................354
17.6.2.2.2Output Compare Events ...........................................................354
17.6.2.2.3PWM End-of-Duty-Cycle Events ............................................354
Chapter 18
Version 1 ColdFire Debug (CF1_DEBUG)
18.1 Introduction ...................................................................................................................................355
18.1.1 Overview .........................................................................................................................356
18.1.2 Features ...........................................................................................................................357
18.1.3 Modes of Operations .......................................................................................................357
18.2 External Signal Descriptions .........................................................................................................359
18.3 Memory Map/Register Definition .................................................................................................360
18.3.1 Configuration/Status Register (CSR) ..............................................................................361
18.3.2 Extended Configuration/Status Register (XCSR) ...........................................................364
18.3.3 Configuration/Status Register 2 (CSR2) .........................................................................367
18.3.4 Configuration/Status Register 3 (CSR3) .........................................................................370
18.3.5 BDM Address Attribute Register (BAAR) .....................................................................371
18.3.6 Address Attribute Trigger Register (AATR) ...................................................................372
18.3.7 Trigger Definition Register (TDR) .................................................................................373
18.3.8 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) ..................................376
18.3.9 Address Breakpoint Registers (ABLR, ABHR) .............................................................378
18.3.10Data Breakpoint and Mask Registers (DBR, DBMR) ....................................................379
18.3.11Resulting Set of Possible Trigger Combinations ............................................................380
18.4 Functional Description ..................................................................................................................380
18.4.1 Background Debug Mode (BDM) ..................................................................................380
18.4.1.1 CPU Halt .......................................................................................................381
18.4.1.2 Background Debug Serial Interface Controller (BDC) ................................383
18.4.1.3 BDM Communication Details ......................................................................384
18.4.1.4 BDM Command Set Descriptions ................................................................387
18.4.1.5 BDM Command Set Summary .....................................................................390
18.4.1.5.1SYNC .......................................................................................392
18.4.1.5.2ACK_DISABLE ......................................................................393
18.4.1.5.3ACK_ENABLE .......................................................................393
18.4.1.5.4BACKGROUND .....................................................................394
18.4.1.5.5DUMP_MEM.sz, DUMP_MEM.sz_WS .................................394
18.4.1.5.6FILL_MEM.sz, FILL_MEM.sz_WS .......................................395
18.4.1.5.7GO ............................................................................................397
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18.4.1.5.8NOP ..........................................................................................397
18.4.1.5.9READ_CREG ..........................................................................397
18.4.1.5.10READ_DREG ........................................................................398
18.4.1.5.11READ_MEM.sz, READ_MEM.sz_WS ................................398
18.4.1.5.12READ_PSTB .........................................................................399
18.4.1.5.13READ_Rn ..............................................................................400
18.4.1.5.14READ_XCSR_BYTE ............................................................400
18.4.1.5.15READ_CSR2_BYTE .............................................................400
18.4.1.5.16READ_CSR3_BYTE .............................................................400
18.4.1.5.17SYNC_PC ..............................................................................401
18.4.1.5.18WRITE_CREG ......................................................................401
18.4.1.5.19WRITE_DREG ......................................................................402
18.4.1.5.20WRITE_MEM.sz, WRITE_MEM.sz_WS .............................402
18.4.1.5.21WRITE_Rn ............................................................................403
18.4.1.5.22WRITE_XCSR_BYTE ..........................................................404
18.4.1.5.23WRITE_CSR2_BYTE ...........................................................404
18.4.1.5.24WRITE_CSR3_BYTE ...........................................................404
18.4.1.6 Serial Interface Hardware Handshake Protocol ............................................404
18.4.1.7 Hardware Handshake Abort Procedure ........................................................406
18.4.2 Real-Time Debug Support ..............................................................................................409
18.4.3 Real-Time Trace Support ................................................................................................409
18.4.3.1 Begin Execution of Taken Branch (PST = 0x05) .........................................411
18.4.3.2 PST Trace Buffer (PSTB) .............................................................................413
18.4.3.3 PST/DDATA Example ..................................................................................413
18.4.3.4 Processor Status, Debug Data Definition ......................................................414
18.4.3.4.1User Instruction Set ..................................................................415
18.4.3.4.2Supervisor Instruction Set ........................................................418
18.4.4 Freescale-Recommended BDM Pinout ..........................................................................419
Appendix A
Revision History
A.1 Changes between Rev. 2 and Rev. 3 .............................................................................................421
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Chapter 1 Device Overview

The MCF51QE128, MCF51QE64, and MCF51QE32 are members of the low-cost, low-power, high-performance Version 1 (V1) ColdFire family of 32-bit microcontroller units (MCUs). All MCUs in the family use the enhanced V1 ColdFire core and are available with a variety of modules, memory sizes, and package types. CPU clock rates on these devices can reach 50.33 MHz. Peripherals operate up to
25.165 MHz.

1.1 Devices in the MCF51QE128/64/32 Series

Table 1-1 summarizes the feature set available in the MCF51QE128/64/32 series of MCUs.
t
Flash size (Kbytes) 128 64 32
RAM size (Kbytes) 8 8 8
Pin quantity 80 64 64 64
Version 1 ColdFire core with debug yes
ACMP1 yes
Table 1-1. MCF51QE128 Series Features by MCU and Package
Feature MCF51QE128 MCF51QE64 MCF51QE32
ACMP2 yes
ADC channels 24 20 20 20
ICS yes
IIC1 yes
IIC2 yes
KBI 16
Por t I/O
Rapid GPIO yes
COP yes
RTC yes
SCI1 yes
SCI2 yes
SPI1 yes
SPI2 yes
Interrupt Controller yes
1, 2
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Table 1-1. MCF51QE128 Series Features by MCU and Package (continued)
Feature MCF51QE128 MCF51QE64 MCF51QE32
External IRQ yes
Low-Voltage Detect (LVD) yes
TPM1 channels 3
TPM2 channels 3
TPM3 channels 6
XOSC yes
1
Port I/O count does not include the input-only PTA5/IRQ/TPM1CLK/RESET or the output-only PTA4/ACMP1O/BKGD/MS.
2
16 bits associated with Ports C and E are shadowed with ColdFire Rapid GPIO module.

1.2 MCU Block Diagram

The block diagram in Figure 1-1 shows the structure of the MCF51QE128/64/32 MCU.
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Chapter 1 Device Overview
TPM2CH2-0
TPM1CH2-0
ANALOG COMPARATOR
(ACMP1)
ACMP1O
ACMP1-
ACMP1+
V
SS
V
DD
IIC MODULE (IIC1)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
USER FLASH
USER RAM
128K / 64K
V1 ColdFire CORE
CPU
BDC / Debug
6-CHANNEL TIMER/PWM
MODULE (TPM3)
SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
VOLTAGE
REGULATOR
COP
-
LV D
OSCILLATOR (XOSC)
RESET
V
REFL
V
REFH
8K / 4K
BKGD/MS
INTERFACE (SCI1)
SERIAL COMMUNICATIONS
MISO1
SS1
SPSCK1
3-CHANNEL TIMER/PWM
MODULE (TPM2)
REAL TIME COUNTER (RTC)
Rapid GPIO
IRQ
PTA3/KBI1P3/SCL1/ADP3
PTA4/ACMP1O/BKGD/MS
PTA5/IRQ/TPM1CLK/RESET
PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1­PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PORT A
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
MOSI1
PTB3/KBI1P7/MOSI1/ADP7
PTB4/TPM2CH1/MISO1
PTB5/TPM1CH1/SS1
PTB2/KBI1P6/SPSCK1/ADP6 PTB1/KBI1P5/TxD1/ADP5 PTB0/KBI1P4/RxD1/ADP4
PORT B
PTB6/SDA1/XTAL
PTB7/SCL1/EXTAL
PTC3/RGPIO11/TPM3CH3
PTC4/RGPIO12/TPM3CH4/RSTO
PTC5/RGPIO13/TPM3CH5/ACMP2O
PTC2/RGPIO10/TPM3CH2 PTC1/RGPIO9/TPM3CH1 PTC0/RGPIO8/TPM3CH0
PORT C
PTC6/RGPIO14/RxD2/ACMP2+
PTC7/RGPIO15/TxD2/ACMP2-
PTD3/KBI2P3/SS2
PTD4/KBI2P4
PTD5/KBI2P5
PTD2/KBI2P2/MISO2 PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2
PORT D
PTD6/KBI2P6
PTD7/KBI2P7
PTE3/RGPIO3/SS1
PTE4/RGPIO4
PTE5/RGPIO5
PTE2/RGPIO2/MISO1 PTE1/RGPIO1/MOSI1
TPM2CLK
PORT E
PTE6/RGPIO6
PTE0/RGPIO0/TPM2CLK/SPSCK1
PTF3/ADP13
PTF4/ADP14
PTF5/ADP15
PTF2/ADP12 PTF1/ADP11 PTF0/ADP10
PORT F
PTF6/ADP16
PTF7/ADP17
PTG1
PTG2/ADP18
PTG3/ADP19
PORT G
PTG4/ADP20
PTG5/ADP21
PTG0
V
SS
V
DD
V
SSAD
V
DDAD
IP Bus Bridge
INTC
ANALOG COMPARATOR
(ACMP2)
INTERFACE (SCI2)
SERIAL COMMUNICATIONS
TPM3CH5-0
PTG6/ADP22
PTG7/ADP23
SOURCE (ICS)
INTERNAL CLOCK
PORT J
PORT H
PTJ1
PTJ2
PTJ3
PTJ4
PTJ5
PTJ0
PTJ6
PTJ7
PTH1
PTH2
PTH3
PTH4
PTH5
PTH0
PTH6/SCL2
PTH7/SDA2
IIC MODULE (IIC2)
ANALOG-TO-DIGITAL
CONVERTER (ADC)
24-CHANNEL,12-BIT
3-CHANNEL TIMER/PWM
MODULE (TPM1)
SDA2 SCL2
SERIAL PERIPHERAL
INTERFACE MODULE (SPI2)
MISO2
SS2
SPSCK2
MOSI2
EXTAL
XTAL
16
SDA1
SCL1
ACMP2-
ACMP2+
ACMP2O
RxD1
TxD1
RxD2
TxD2
TPM3CLK
3
TPM1CLK
PTE7/RGPIO7/TPM3CLK
Figure 1-1. MCF51QE128/64/32 Block Diagram
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Table 1-2 provides the functional version of the on-chip modules
Table 1-2. Module Versions
Module Version
Analog Comparator (ACMP) 4
Analog-to-Digital Converter (ADC) 1
V1 ColdFire Core (CF1_CORE) 1
V1 ColdFire Interrupt Controller (CF1_INTC) 1
V1 ColdFire Debug Module (CF1_DEBUG) 1
General Purpose I/O (GPIO) 2
Inter-Integrated Circuit (IIC) 2
Internal Clock Source (ICS) 3
Keyboard Interrupt (KBI) 2
Low-Power Oscillator (OSCVLP) 1
Port Set/Clear (PSC) 1
Rapid GPIO (RGPIO) 1
Real-Time Counter (RTC) 1
Serial Communications Interface (SCI) 4
Serial Peripheral Interface (SPI) 3
Timer Pulse Width Modulator (TPM) 3
Voltage Regulator (PMCx)1

1.3 V1 ColdFire Core

The MCF51QE128/64/32 devices contain the Version 1 (V1) ColdFire core optimized for area and low-power. This CPU implements ColdFire instruction set architecture revision C (ISA_C):
• No hardware support for MAC/EMAC and DIV instructions
1
• Provides upward compatibility to all other ColdFire cores (V2–V5)
For more details on the V1 ColdFire core, see Chapter 7, “ColdFire Core”.

1.4 System Clocks

This section discusses on-chip clock generation and distribution for the MCF51QE128/64/32 devices.

1.4.1 Internal Clock Source (ICS) Module

Figure 1-2 shows a simplified view of the internal clock source module. For clarity, only one of three
available FLL modules is shown.
1. These operations can be emulated via software functions.
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DCO
Filter
RDIV
TRIM
/ 2
9
External Reference
IREFS
Clock Source
Block
CLKS
n=0-7
/ 2
n
n=0-3
/ 2
n
Internal
Reference
Clock
BDIV
9
ICSLCLK
ICSOUT
ICSIRCLK
EREFS
RANGE
EREFSTEN
HGO
Optional
IREFSTEN
ICSERCLK
Internal Clock Source Block
LP
ICSFFCLK
ERCLKEN
IRCLKEN
DCOOUT
FLL
RDIV_CLK
RTC
Figure 1-2. Simplified ICS Block Diagram

1.4.2 System Clock Distribution

Figure 1-3 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) used to drive the module function. All memory mapped registers associated with the modules (except RGPIO) are clocked with the peripheral clock (BUSCLK). The RGPIO registers are clocked with the CPU clock (ICSOUT). With the exception of the oscillator clock supplied directly to the RTC, the ICS supplies all clock sources:
• ICSOUT — This clock source is used throughout the core including the CPU. For consistency, it is known simply as the CPU clock. It is divided by two to generate the peripheral bus clock. Control bits in the ICS control registers determine which of three clock sources is connected:
— Internal reference clock — External reference clock — Frequency-locked loop (FLL) output See Chapter 12, “Internal Clock Source (S08ICSV3),” for details on configuring the ICSOUT
clock.
• ICSLCLK — This clock source is derived from the 10/20 MHz DCO (digitally controlled oscillator) of the ICS when the ICS is configured to run off of the internal or external reference clock. Development tools can select this internal self-clocked source (~10 MHz) to speed up BDC communications in systems where the bus clock is slow.
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TPM1 TPM2 TPM3
SCI1 &
SPI1 &
RAM
CPU &
ADC FLASH GPIO
ICS
ICSOUT
÷2
BUSCLK
ICSLCLK
ICSERCLK
COP
* The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency.
Flash has frequency requirements for program and erase operation. See the MCF51QE128 Data Sheet for details.
ADC has min and max frequency requirements. See the ADC chapter and the MCF51QE128 Data Sheet for details.
XOSC
EXTAL
XTAL
ACMP1 &
FFCLK*
ICSFFCLK
RTC
TPM1CLK
ICSIRCLK
÷2
PMC
IIC1 &
TPM3CLK
TPM2CLK
SYNC*
LPOCLK
BDC
1KHz LPO
OSCOUT
Debug
SCI2
SPI2 ACMP2
IIC2
INTC
RGPIO
Figure 1-3. System Clock Distribution Diagram
• OSCOUT — This is the direct output of the external oscillator module and can be selected as the real-time counter clock source. See Chapter 14, “Real-Time Counter (S08RTCV1),” for more information.
• ICSERCLK — This is the external reference clock and can be selected as the real-time counter clock source or the alternate clock for the ADC module. Section 11.4.7, “External Reference
Clock,” explains the ICSERCLK in more detail. See Chapter 11, “Analog-to-Digital Converter (S08ADC12V1),” for more information regarding the use of ICSERCLK with this module.
• ICSIRCLK — This is the internal reference clock and can be selected as the real-time counter clock source. Section 11.4.6, “Internal Reference Clock,” explains the ICSIRCLK in more detail. See
Chapter 14, “Real-Time Counter (S08RTCV1),” for more information regarding the use of
ICSIRCLK.
• ICSFFCLK — This generates the fixed frequency clock (FFCLK) after being synchronized to the bus clock. It can be selected as clock source for the TPM modules. The frequency of the ICSFFCLK is determined by the settings of the ICS. See Section 11.4.8, “Fixed Frequency Clock,” for details.
• LPOCLK — This clock is generated from an internal low-power oscillator that is completely independent of the ICS module. The LPOCLK can be selected as the clock source to the RTC or COP modules. See Chapter 14, “Real-Time Counter (S08RTCV1),” and Section 5.3.1, “Computer
Operating Properly (COP) Watchdog,” for details on using the LPOCLK with these modules.
•TPMxCLK — TPMxCLKs are optional external clock sources for the TPM modules. The TPMxCLK must be limited to 1/4 the frequency of the bus clock for synchronization. See
Section 16.2.1, “External TPM Clock Sources,” for more details.
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The ADC module also has an internally generated asynchronous clock that allows it to run in stop mode (ADACK). This signal is not available externally and is not shown in this figure.

1.4.3 ICS Modes of Operation

There are seven modes of operation for the internal clock source (ICS) module: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. These are shown in Figure 1-4. The IREFS and CLKS fields are contained within the ICS module definition. The LP bit is part of the on-chip power management controller (PMC) block. It is the responsibility of the software to ensure that the system bus frequency is less than 125 kHz and the FLLs are disengaged prior to enabling switching the LP bit to enable FBELP and FBILP modes of operation.
The clock source for the BDC is controlled by the debug CLKSW bit, discussed later in this document. Choices for the BDC clock are ICSOUT and the output from the 10MHz bus / 20 MHz CPU clock FLL.
1.4.3.1 FLL Engaged Internal (FEI)
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from one of three on chip FLLs, which are controlled by the internal reference clock. Upon exiting reset, the default FLL generates the 10 MHz bus/20 MHz CPU clocks.
1.4.3.2 FLL Engaged External (FEE)
In FLL engaged external mode, the ICS supplies a clock derived from one of the three FLLs, which are controlled by an external reference clock.
1.4.3.3 FLL Bypassed Internal (FBI)
In FLL bypassed internal mode, the FLLs are enabled and controlled by the internal reference clock, but are bypassed. The ICS supplies a clock derived from the internal reference clock.
1.4.3.4 FLL Bypassed Internal Low-Power (FBILP)
In FLL bypassed internal low-power mode, the FLLs are disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock.
1.4.3.5 FLL Bypassed External (FBE)
In FLL bypassed external mode, the FLLs are enabled and controlled by an external reference clock, but are bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source.
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FLL Bypassed Internal Low­Power(FBILP)
IREFS=1 CLKS=00 LP=0
Entered from any state when MCU enters stop with ENBDM=0.
FLL Engaged Internal (FEI)
FLL Bypassed Internal (FBI)
FLL Bypassed External (FBE)
FLL Engaged External (FEE)
FLL Bypassed External Low­Power(FBELP)
IREFS=0 CLKS=00 LP=0
IREFS=0 CLKS=10 LP=0
Returns to state that was active before MCU entered stop, unless reset occurs while in stop.
IREFS=0 CLKS=10 LP=1
IREFS=1 CLKS=01 LP=0
IREFS=1 CLKS=01 LP=1
Stop
1.4.3.6 FLL Bypassed External Low-Power (FBELP)
In FLL bypassed external low-power mode, the FLLs are disabled and bypassed, and the ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source.
1.4.3.7 Stop (STOP)
In stop mode, the FLLs are disabled and the internal or external reference clocks can be selected to be enabled or disabled. The ICS does not provide an MCU clock source unless the debug ENBDM bit is set.
Figure 1-4. ICS Modes of Operation
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