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MCF51QE128RM
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Freescale Semiconductor MCF51QE128RM User Manual

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MCF51QE128 MCF51QE64 MCF51QE32
Reference Manual
MCF51QE128 Series Features
• 32-Bit Version 1 ColdFire® Central Processor Unit (CPU) – Up to 50.33-MHz ColdFire CPU from 3.6V to 2.1V , and
20-MHz CPU at 2.1V to 1.8V across temperature range of -40°C to 85°C
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
performance when running from internal RAM
(0.76 DMIPS/MHz from flash) – Implements Instruction Set Revision C (ISA_C) – Support for up to 30 peripheral interrupt requests and
seven software interrupts
•On-Chip Memory – Flash read/program/erase over full operating voltage
and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes – Two low power stop modes; reduced power wait mode – Peripheral clock enable register can disable clocks to
unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode
– Very low power external oscillator can be used in stop3
mode to provide accurate clock to active peripherals
– Very low power real time counter for use in run, wait,
and stop modes with internal and external clock sources
–6 μs typical wake up time from stop modes
• Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator;
Crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — FLL controlled by
internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports CPU freq. from 2 to 50.33 MHz
• System Protection – Watchdog computer operating properly (COP) reset
with option to run from dedicated 1-kHz internal clock source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode and illegal address detection with
programmable reset or exception response
– Flash block protection
• Development Support – Single-wire background debug interface – 4 PC plus 2 address (optional data) breakpoint registers
with programmable 1- or 2-level trigger response
– 64-entry processor status and debug data trace buffer
with programmable start/stop conditions
• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V
• ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3
• SCIx — Two SCIs with full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge
• SPIx— Two serial peripheral interfaces with Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; MSB-first or LSB-first shifting
• IICx — Two IICs with; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing
• TPMx — One 6-channel and two 3-channel; Selectable input capture, output compare, or buffered edge- or center-aligned PWMs on each channel
• RTC — 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components
• Input/Output – 70 GPIOs and 1 input-only and 1 output-only pin – 16 KBI interrupts with selectable polarity – Hysteresis and configurable pull-up device on all input
pins; Configurable slew rate and drive strength on all
output pins. – SET/CLR registers on 16 pins (PTC and PTE) – 16 bits of Rapid GPIO connected to the CPU’s
high-speed local bus with set, clear, and toggle
functionality
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MCF51QE128 Reference Manual
Covers MCF51QE128
MCF51QE64 MCF51QE32
Related Documentation:
• MCF51QE128 (Data Sheet)
Contains pin assignments and diagrams, all electrical specififications, and mechanical drawing outlines.
Find the most current versions of all documents at:
http://www.freescale.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
MCF51QE128RM
Rev. 3
09/2007
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MCF51QE128 MCU Series Reference Manual, Rev. 3
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Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Devices in the MCF51QE128/64/32 Series ....................................................................................23
1.2 MCU Block Diagram ......................................................................................................................24
1.3 V1 ColdFire Core ............................................................................................................................26
1.4 System Clocks .................................................................................................................................26
1.4.1 Internal Clock Source (ICS) Module ................................................................................26
1.4.2 System Clock Distribution ................................................................................................27
1.4.3 ICS Modes of Operation ...................................................................................................29
1.4.3.1 FLL Engaged Internal (FEI) ...........................................................................29
1.4.3.2 FLL Engaged External (FEE) .........................................................................29
1.4.3.3 FLL Bypassed Internal (FBI) ..........................................................................29
1.4.3.4 FLL Bypassed Internal Low-Power (FBILP) .................................................29
1.4.3.5 FLL Bypassed External (FBE) .......................................................................29
1.4.3.6 FLL Bypassed External Low-Power (FBELP) ...............................................30
1.4.3.7 Stop (STOP) ....................................................................................................30
Chapter 2
Pins and Connections
2.1 Device Pin Assignment ...................................................................................................................33
2.2 Recommended System Connections ...............................................................................................35
2.2.1 Power ................................................................................................................................37
2.2.2 Oscillator ...........................................................................................................................37
2.2.3 RESET and RSTO ............................................................................................................37
2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................38
2.2.5 ADC Reference Pins (V
2.2.6 General-Purpose I/O and Peripheral Ports ........................................................................39
REFH
, V
) .............................................................................39
REFL
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................43
3.2 Features ...........................................................................................................................................43
3.3 Overview .........................................................................................................................................44
3.4 Debug Mode ....................................................................................................................................48
3.5 Secure Mode ....................................................................................................................................48
3.6 Run Modes ......................................................................................................................................49
3.6.1 Run Mode .........................................................................................................................49
3.6.2 Low-Power Run Mode (LPrun) ........................................................................................49
3.6.2.1 BDM in Low-Power Run Mode .....................................................................49
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Section Number Title Page
3.7 Wait Modes ......................................................................................................................................50
3.7.1 Wait Mode .........................................................................................................................50
3.7.2 Low-Power Wait Mode (LPwait) ......................................................................................50
3.7.2.1 BDM in Low-Power Wait Mode .....................................................................50
3.8 Stop Modes ......................................................................................................................................50
3.8.1 Stop2 Mode .......................................................................................................................51
3.8.1.1 Low-Range Oscillator Considerations for Stop2 ............................................52
3.8.2 Stop3 Mode .......................................................................................................................52
3.8.3 Stop4: Low Voltage Detect or BDM Enabled in Stop Mode ............................................52
3.9 On-Chip Peripheral Modules in Stop and Low-Power Modes ........................................................53
Chapter 4
Memory
4.1 MCF51QE128/64/32 Memory Map ................................................................................................57
4.2 Register Addresses and Bit Assignments ........................................................................................58
4.2.1 Flash Module Reserved Memory Locations .....................................................................67
4.2.2 ColdFire Rapid GPIO Memory Map ................................................................................69
4.2.3 ColdFire Interrupt Controller Memory Map .....................................................................69
4.3 RAM ................................................................................................................................................70
4.4 Flash ................................................................................................................................................70
4.4.1 Features .............................................................................................................................71
4.4.2 Register Descriptions ........................................................................................................72
4.4.2.1 Flash Clock Divider Register (FCDIV) ..........................................................72
4.4.2.2 Flash Options Register (FOPT and NVOPT) ..................................................72
4.4.2.3 Flash Configuration Register (FCNFG) .........................................................73
4.4.2.4 Flash Protection Register (FPROT and NVPROT) ........................................74
4.4.2.5 Flash Status Register (FSTAT) ........................................................................76
4.4.2.6 Flash Command Register (FCMD) .................................................................77
4.5 Function Description .......................................................................................................................77
4.5.1 Flash Command Operations ..............................................................................................77
4.5.1.1 Writing the FCDIV Register ...........................................................................78
4.5.1.2 Command Write Sequence ..............................................................................79
4.5.2 Flash Commands ...............................................................................................................80
4.5.2.1 Erase Verify Command ...................................................................................80
4.5.2.2 Program Command .........................................................................................81
4.5.2.3 Burst Program Command ...............................................................................83
4.5.2.4 Sector Erase Command ...................................................................................84
4.5.2.5 Mass Erase Command ....................................................................................86
4.5.3 Illegal Flash Operations ....................................................................................................87
4.5.3.1 Flash Access Violations ..................................................................................87
4.5.3.2 Flash Protection Violations .............................................................................88
4.5.4 Operating Modes ...............................................................................................................88
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Section Number Title Page
4.5.4.1 Wait Mode .......................................................................................................88
4.5.4.2 Stop Modes .....................................................................................................88
4.5.4.3 Background Debug Mode ...............................................................................88
4.5.5 Security .............................................................................................................................89
4.5.5.1 Unsecuring the MCU using Backdoor Key Access ........................................89
4.5.6 Resets ................................................................................................................................90
4.5.6.1 Flash Reset Sequence ......................................................................................90
4.5.6.2 Reset While Flash Command Active ..............................................................90
4.5.6.3 Program and Erase Times ...............................................................................90
4.6 Security ............................................................................................................................................91
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction .....................................................................................................................................93
5.2 Features ...........................................................................................................................................93
5.3 Microcontroller Reset ......................................................................................................................93
5.3.1 Computer Operating Properly (COP) Watchdog ..............................................................94
5.3.2 Illegal Operation Reset .....................................................................................................95
5.3.3 Illegal Address Reset ........................................................................................................95
5.4 Interrupts and Exceptions ................................................................................................................95
5.4.1 External Interrupt Request (IRQ) Pin ...............................................................................95
5.4.1.1 Pin Configuration Options ..............................................................................95
5.4.1.2 Edge and Level Sensitivity .............................................................................96
5.4.1.3 External Interrupt Initialization ......................................................................96
5.5 Low-Voltage Detect (LVD) System ................................................................................................96
5.5.1 Power-On Reset Operation ...............................................................................................96
5.5.2 LVD Reset Operation ........................................................................................................97
5.5.3 LVD Interrupt Operation ...................................................................................................97
5.5.4 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................97
5.6 Peripheral Clock Gating ..................................................................................................................97
5.7 Reset, Interrupt, and System Control Registers and Control Bits ...................................................97
5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................98
5.7.2 System Reset Status Register (SRS) .................................................................................99
5.7.3 System Options Register 1 (SOPT1) ..............................................................................100
5.7.4 System Options Register 2 (SOPT2) ..............................................................................101
5.7.5 System Device Identification Register (SDIDH, SDIDL) ..............................................102
5.7.6 System Power Management Status and Control 1 Register (SPMSC1) .........................103
5.7.7 System Power Management Status and Control 2 Register (SPMSC2) .........................104
5.7.8 System Power Management Status and Control 3 Register (SPMSC3) .........................105
5.7.9 System Clock Gating Control 1 Register (SCGC1) ........................................................107
5.7.10 System Clock Gating Control 2 Register (SCGC2) ........................................................107
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Section Number Title Page
Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction ........................................................................................................113
6.2 Pull-up, Slew Rate, and Drive Strength ........................................................................................114
6.2.1 Port Internal Pull-up Enable ...........................................................................................114
6.2.2 Port Slew Rate Enable ....................................................................................................114
6.2.3 Port Drive Strength Select ..............................................................................................115
6.3 Port Data Set, Clear and Toggle Data Registers ............................................................................115
6.3.1 Port Data Set Registers ...................................................................................................116
6.3.2 Port Data Clear Registers ................................................................................................116
6.3.3 Port Data Toggle Register ............................................................................................... 116
6.4 V1 ColdFire Rapid GPIO Functionality ........................................................................................116
6.5 Keyboard Interrupts .......................................................................................................................116
6.5.1 Edge Only Sensitivity .....................................................................................................117
6.5.2 Edge and Level Sensitivity .............................................................................................117
6.5.3 Pull-up/Pull-down Resistors ...........................................................................................117
6.5.4 Keyboard Interrupt Initialization ....................................................................................118
6.6 Pin Behavior in Stop Modes ..........................................................................................................118
6.7 Parallel I/O, Keyboard Interrupt, and Pin Control Registers ........................................................118
6.7.1 Port A Registers ..............................................................................................................118
6.7.1.1 Port A Data Register (PTAD) .......................................................................119
6.7.1.2 Port A Data Direction Register (PTADD) ....................................................119
6.7.1.3 Port A Pull Enable Register (PTAPE) ...........................................................119
6.7.1.4 Port A Slew Rate Enable Register (PTASE) .................................................120
6.7.1.5 Port A Drive Strength Selection Register (PTADS) .....................................120
6.7.2 Port B Registers ..............................................................................................................121
6.7.2.1 Port B Data Register (PTBD) ........................................................................121
6.7.2.2 Port B Data Direction Register (PTBDD) .....................................................121
6.7.2.3 Port B Pull Enable Register (PTBPE) ...........................................................122
6.7.2.4 Port B Slew Rate Enable Register (PTBSE) .................................................122
6.7.2.5 Port B Drive Strength Selection Register (PTBDS) .....................................123
6.7.3 Port C Registers ..............................................................................................................123
6.7.3.1 Port C Data Register (PTCD) ........................................................................123
6.7.3.2 Port C Data Direction Register (PTCDD) .....................................................124
6.7.3.3 Port C Data Set Register (PTCSET) .............................................................124
6.7.3.4 Port C Data Clear Register (PTCCLR) .........................................................124
6.7.3.5 Port C Toggle Register (PTCTOG) ...............................................................125
6.7.3.6 Port C Pull Enable Register (PTCPE) ...........................................................125
6.7.3.7 Port C Slew Rate Enable Register (PTCSE) .................................................126
6.7.3.8 Port C Drive Strength Selection Register (PTCDS) .....................................126
6.7.4 Port D Registers ..............................................................................................................126
6.7.4.1 Port D Data Register (PTDD) .......................................................................126
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6.7.4.2 Port D Data Direction Register (PTDDD) ....................................................127
6.7.4.3 Port D Pull Enable Register (PTDPE) ..........................................................127
6.7.4.4 Port D Slew Rate Enable Register (PTDSE) ................................................128
6.7.4.5 Port D Drive Strength Selection Register (PTDDS) .....................................128
6.7.5 Port E Registers ..............................................................................................................128
6.7.5.1 Port E Data Register (PTED) ........................................................................128
6.7.5.2 Port E Data Direction Register (PTEDD) .....................................................129
6.7.5.3 Port E Data Set Register (PTESET) ..............................................................129
6.7.5.4 Port E Data Clear Register (PTECLR) .........................................................130
6.7.5.5 Port E Toggle Register (PTETOG) ...............................................................130
6.7.5.6 Port E Pull Enable Register (PTEPE) ...........................................................130
6.7.5.7 Port E Slew Rate Enable Register (PTESE) .................................................131
6.7.5.8 Port E Drive Strength Selection Register (PTEDS) ......................................131
6.7.6 Port F Registers ...............................................................................................................132
6.7.6.1 Port F Data Register (PTFD) ........................................................................132
6.7.6.2 Port F Data Direction Register (PTFDD) .....................................................132
6.7.6.3 Port F Pull Enable Register (PTFPE) ............................................................132
6.7.6.4 Port F Slew Rate Enable Register (PTFSE) ..................................................133
6.7.6.5 Port F Drive Strength Selection Register (PTFDS) ......................................133
6.7.7 Port G Registers ..............................................................................................................134
6.7.7.1 Port G Data Register (PTGD) .......................................................................134
6.7.7.2 Port G Data Direction Register (PTGDD) ....................................................134
6.7.7.3 Port G Pull Enable Register (PTGPE) ..........................................................135
6.7.7.4 Port G Slew Rate Enable Register (PTGSE) ................................................135
6.7.7.5 Port G Drive Strength Selection Register (PTGDS) .....................................135
6.7.8 Port H Registers ..............................................................................................................136
6.7.8.1 Port H Data Register (PTHD) .......................................................................136
6.7.8.2 Port H Data Direction Register (PTHDD) ....................................................136
6.7.8.3 Port H Pull Enable Register (PTHPE) ..........................................................137
6.7.8.4 Port H Slew Rate Enable Register (PTHSE) ................................................137
6.7.8.5 Port H Drive Strength Selection Register (PTHDS) .....................................137
6.7.9 Port J Registers ...............................................................................................................138
6.7.9.1 Port J Data Register (PTJD) ..........................................................................138
6.7.9.2 Port J Data Direction Register (PTJDD) .......................................................138
6.7.9.3 Port J Pull Enable Register (PTJPE) .............................................................139
6.7.9.4 Port J Slew Rate Enable Register (PTJSE) ...................................................139
6.7.9.5 Port J Drive Strength Selection Register (PTJDS) ........................................139
6.7.10 Keyboard Interrupt 1 (KBI1) Registers ..........................................................................140
6.7.10.1 KBI1 Interrupt Status and Control Register (KBI1SC) ................................140
6.7.10.2 KBI1 Interrupt Pin Select Register (KBI1PE) ..............................................141
6.7.10.3 KBI1 Interrupt Edge Select Register (KBI1ES) ...........................................141
6.7.11 Keyboard Interrupt 1 (KBI2) Registers ..........................................................................141
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6.7.11.1 KBI2 Interrupt Status and Control Register (KBI2SC) ................................142
6.7.11.2 KBI2 Interrupt Pin Select Register (KBI2PE) ..............................................142
6.7.11.3 KBI2 Interrupt Edge Select Register (KBI2ES) ...........................................143
Chapter 7
ColdFire Core
7.1 Introduction ...................................................................................................................................145
7.1.1 Overview .........................................................................................................................145
7.2 Memory Map/Register Description ...............................................................................................146
7.2.1 Data Registers (D0–D7) ..................................................................................................147
7.2.2 Address Registers (A0–A6) ............................................................................................148
7.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) ..................................................148
7.2.4 Condition Code Register (CCR) .....................................................................................149
7.2.5 Program Counter (PC) ....................................................................................................150
7.2.6 Vector Base Register (VBR) ...........................................................................................150
7.2.7 CPU Configuration Register (CPUCR) ..........................................................................151
7.2.8 Status Register (SR) ........................................................................................................152
7.3 Functional Description ..................................................................................................................153
7.3.1 Instruction Set Architecture (ISA_C) .............................................................................153
7.3.2 Exception Processing Overview .....................................................................................154
7.3.2.1 Exception Stack Frame Definition ................................................................156
7.3.2.2 S08 and ColdFire Exception Processing Comparison ..................................157
7.3.3 Processor Exceptions ......................................................................................................159
7.3.3.1 Access Error Exception ................................................................................159
7.3.3.2 Address Error Exception ...............................................................................159
7.3.3.3 Illegal Instruction Exception .........................................................................160
7.3.3.4 Privilege Violation ........................................................................................161
7.3.3.5 Trace Exception ............................................................................................161
7.3.3.6 Unimplemented Line-A Opcode ...................................................................162
7.3.3.7 Unimplemented Line-F Opcode ...................................................................162
7.3.3.8 Debug Interrupt .............................................................................................162
7.3.3.9 RTE and Format Error Exception .................................................................162
7.3.3.10 TRAP Instruction Exception .........................................................................163
7.3.3.11 Unsupported Instruction Exception ..............................................................163
7.3.3.12 Interrupt Exception .......................................................................................163
7.3.3.13 Fault-on-Fault Halt .......................................................................................163
7.3.3.14 Reset Exception ............................................................................................164
7.3.4 Instruction Execution Timing .........................................................................................167
7.3.4.1 Timing Assumptions .....................................................................................167
7.3.4.2 MOVE Instruction Execution Times ............................................................168
7.3.4.3 Standard One Operand Instruction Execution Times ...................................169
7.3.4.4 Standard Two Operand Instruction Execution Times ...................................170
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7.3.4.5 Miscellaneous Instruction Execution Times .................................................171
7.3.4.6 Branch Instruction Execution Times .............................................................172
Chapter 8
Interrupt Controller (CF1_INTC)
8.1 Introduction ...................................................................................................................................173
8.1.1 Overview .........................................................................................................................174
8.1.2 Features ...........................................................................................................................177
8.1.3 Modes of Operation ........................................................................................................178
8.2 External Signal Description ..........................................................................................................178
8.3 Memory Map and Register Definition ..........................................................................................178
8.3.1 Memory Map ..................................................................................................................179
8.3.2 Register Descriptions ......................................................................................................179
8.3.2.1 INTC Force Interrupt Register (INTC_FRC) ...............................................179
8.3.2.2 INTC Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6}) .....
180
8.3.2.3 INTC Wake-up Control Register (INTC_WCR) ..........................................181
8.3.2.4 INTC Set Interrupt Force Register (INTC_SFRC) .......................................182
8.3.2.5 INTC Clear Interrupt Force Register (INTC_CFRC) ...................................183
8.3.2.6 INTC Software and Level-n IACK Registers (n = 1,2,3,...,7) ......................184
8.3.3 Interrupt Request Level and Priority Assignments .........................................................185
8.4 Functional Description ..................................................................................................................187
8.4.1 Handling of Non-Maskable Level 7 Interrupt Requests .................................................187
8.5 Initialization Information ..............................................................................................................188
8.6 Application Information ................................................................................................................188
8.6.1 Emulation of the HCS08’s 1-Level IRQ Handling .........................................................188
8.6.2 Using INTC_PL6P{7,6} Registers .................................................................................189
8.6.3 More on Software IACKs ...............................................................................................189
Chapter 9
Rapid GPIO (RGPIO)
9.1 Introduction ...................................................................................................................................193
9.1.1 Overview .........................................................................................................................195
9.1.2 Features ...........................................................................................................................197
9.1.3 Modes of Operation ........................................................................................................198
9.2 External Signal Description ..........................................................................................................198
9.2.1 Overview .........................................................................................................................198
9.2.2 Detailed Signal Descriptions ..........................................................................................198
9.3 Memory Map/Register Definition .................................................................................................199
9.3.1 Memory Map ..................................................................................................................199
9.3.2 Register Descriptions ......................................................................................................200
9.3.2.1 RGPIO Data Direction (RGPIO_DIR) .........................................................200
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9.3.2.2 RGPIO Data (RGPIO_DATA) ......................................................................200
9.3.2.3 RGPIO Pin Enable (RGPIO_ENB) ..............................................................201
9.3.2.4 RGPIO Clear Data (RGPIO_CLR) ...............................................................201
9.3.2.5 RGPIO Set Data (RGPIO_SET) ...................................................................202
9.3.2.6 RGPIO Toggle Data (RGPIO_TOG) ............................................................202
9.4 Functional Description ..................................................................................................................203
9.5 Initialization Information ..............................................................................................................203
9.6 Application Information ................................................................................................................203
9.6.1 Application 1: Simple Square-Wave Generation ............................................................203
9.6.2 Application 2: 16-bit Message Transmission using SPI Protocol ...................................204
Chapter 10
Analog Comparator 3V (ACMPVLPV1)
10.1 Introduction ...................................................................................................................................207
10.1.1 ACMP Configuration Information ..................................................................................207
10.1.2 ACMP/TPM Configuration Information ........................................................................207
10.1.3 ACMP Clock Gating .......................................................................................................207
10.1.4 Interrupt Vectors .............................................................................................................208
10.1.5 Features ...........................................................................................................................211
10.1.6 Modes of Operation ........................................................................................................211
10.1.6.1 Wait Mode Operation ....................................................................................211
10.1.6.2 Stop3 Mode Operation ..................................................................................211
10.1.6.3 Stop2 Mode Operation ..................................................................................211
10.1.6.4 Active Background Mode Operation ............................................................211
10.1.7 Block Diagram ................................................................................................................211
10.2 External Signal Description ..........................................................................................................212
10.3 Register Definition ........................................................................................................................212
10.3.1 Status and Control Register (ACMPxSC) .......................................................................212
10.4 Functional Description ..................................................................................................................213
10.5 Interrupts .......................................................................................................................................213
Chapter 11
Analog-to-Digital Converter (S08ADC12V1)
11.1 Introduction ...................................................................................................................................215
11.1.1 ADC Clock Gating ..........................................................................................................215
11.1.2 Module Configurations ...................................................................................................217
11.1.2.1 Channel Assignments ...................................................................................217
11.1.2.2 Alternate Clock .............................................................................................217
11.1.2.3 Hardware Trigger ..........................................................................................218
11.1.2.4 Temperature Sensor ......................................................................................218
11.1.3 Interrupt Vectors .............................................................................................................218
11.1.4 Features ...........................................................................................................................219
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11.1.5 Block Diagram ................................................................................................................219
11.2 External Signal Description ..........................................................................................................220
11.2.1 Analog Power (V
11.2.2 Analog Ground (V
11.2.3 Voltage Reference High (V
11.2.4 Voltage Reference Low (V
11.2.5 Analog Channel Inputs (ADx) ........................................................................................221
11.3 Register Definition ........................................................................................................................221
11.3.1 Status and Control Register 1 (ADCSC1) ......................................................................221
11.3.2 Status and Control Register 2 (ADCSC2) ......................................................................223
11.3.3 Data Result High Register (ADCRH) .............................................................................223
11.3.4 Data Result Low Register (ADCRL) ..............................................................................224
11.3.5 Compare Value High Register (ADCCVH) ....................................................................224
11.3.6 Compare Value Low Register (ADCCVL) .....................................................................225
11.3.7 Configuration Register (ADCCFG) ................................................................................225
11.3.8 Pin Control 1 Register (APCTL1) ..................................................................................226
11.3.9 Pin Control 2 Register (APCTL2) ..................................................................................227
11.3.10Pin Control 3 Register (APCTL3) ..................................................................................228
11.4 Functional Description ..................................................................................................................229
11.4.1 Clock Select and Divide Control ....................................................................................230
11.4.2 Input Select and Pin Control ...........................................................................................230
11.4.3 Hardware Trigger ............................................................................................................230
11.4.4 Conversion Control .........................................................................................................230
11.4.4.1 Initiating Conversions ................................................................................... 231
11.4.4.2 Completing Conversions ...............................................................................231
11.4.4.3 Aborting Conversions ...................................................................................231
11.4.4.4 Power Control ...............................................................................................232
11.4.4.5 Sample Time and Total Conversion Time ....................................................232
11.4.5 Automatic Compare Function .........................................................................................233
11.4.6 MCU Wait Mode Operation ............................................................................................233
11.4.7 MCU Stop3 Mode Operation ..........................................................................................234
11.4.7.1 Stop3 Mode With ADACK Disabled ............................................................234
11.4.7.2 Stop3 Mode With ADACK Enabled .............................................................234
11.4.8 MCU Stop2 Mode Operation ..........................................................................................234
11.5 Initialization Information ..............................................................................................................234
11.5.1 ADC Module Initialization Example .............................................................................235
11.5.1.1 Initialization Sequence .................................................................................. 235
11.5.1.2 Pseudo-Code Example ..................................................................................235
11.6 Application Information ................................................................................................................236
11.6.1 External Pins and Routing ..............................................................................................236
11.6.1.1 Analog Supply Pins ......................................................................................237
11.6.1.2 Analog Reference Pins ..................................................................................237
) ..................................................................................................221
DDAD
) .................................................................................................221
SSAD
) ...................................................................................221
REFH
) ....................................................................................221
REFL
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11.6.1.3 Analog Input Pins .........................................................................................237
11.6.2 Sources of Error ..............................................................................................................238
11.6.2.1 Sampling Error .............................................................................................. 238
11.6.2.2 Pin Leakage Error .........................................................................................238
11.6.2.3 Noise-Induced Errors ....................................................................................238
11.6.2.4 Code Width and Quantization Error .............................................................239
11.6.2.5 Linearity Errors ............................................................................................. 239
11.6.2.6 Code Jitter, Non-Monotonicity, and Missing Codes .....................................240
Chapter 12
Internal Clock Source (S08ICSV3)
12.1 Introduction ...................................................................................................................................243
12.1.1 External Oscillator ..........................................................................................................243
12.1.2 Stop2 Mode Considerations ............................................................................................243
12.1.3 Features ...........................................................................................................................247
12.1.4 Block Diagram ................................................................................................................248
12.1.5 Modes of Operation ........................................................................................................248
12.1.5.1 FLL Engaged Internal (FEI) .........................................................................248
12.1.5.2 FLL Engaged External (FEE) .......................................................................248
12.1.5.3 FLL Bypassed Internal (FBI) ........................................................................248
12.1.5.4 FLL Bypassed Internal Low Power (FBILP) ...............................................249
12.1.5.5 FLL Bypassed External (FBE) .....................................................................249
12.1.5.6 FLL Bypassed External Low Power (FBELP) .............................................249
12.1.5.7 Stop (STOP) ..................................................................................................249
12.2 External Signal Description ..........................................................................................................249
12.3 Register Definition ........................................................................................................................249
12.3.1 ICS Control Register 1 (ICSC1) .....................................................................................250
12.3.2 ICS Control Register 2 (ICSC2) .....................................................................................251
12.3.3 ICS Trim Register (ICSTRM) .........................................................................................251
12.3.4 ICS Status and Control (ICSSC) .....................................................................................252
12.4 Functional Description ..................................................................................................................254
12.4.1 Operational Modes ..........................................................................................................254
12.4.1.1 FLL Engaged Internal (FEI) .........................................................................254
12.4.1.2 FLL Engaged External (FEE) .......................................................................255
12.4.1.3 FLL Bypassed Internal (FBI) ........................................................................255
12.4.1.4 FLL Bypassed Internal Low Power (FBILP) ...............................................255
12.4.1.5 FLL Bypassed External (FBE) .....................................................................255
12.4.1.6 FLL Bypassed External Low Power (FBELP) .............................................256
12.4.1.7 Stop ...............................................................................................................256
12.4.2 Mode Switching ..............................................................................................................256
12.4.3 Bus Frequency Divider ...................................................................................................256
12.4.4 Low Power Bit Usage .....................................................................................................257
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12.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................257
12.4.6 Internal Reference Clock ................................................................................................257
12.4.7 External Reference Clock ...............................................................................................257
12.4.8 Fixed Frequency Clock ...................................................................................................258
12.4.9 The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source. ICSFFCLK frequency must be no more than 1/4 of the ICSOUT frequency to be valid. Local Clock 258
Chapter 13
Inter-Integrated Circuit (S08IICV2)
13.1 Introduction ...................................................................................................................................259
13.1.1 Module Configuration .....................................................................................................259
13.1.2 Interrupt Vectors .............................................................................................................259
13.1.3 Features ...........................................................................................................................262
13.1.4 Modes of Operation ........................................................................................................262
13.1.5 Block Diagram ................................................................................................................263
13.2 External Signal Description ..........................................................................................................263
13.2.1 SCL — Serial Clock Line ...............................................................................................263
13.2.2 SDA — Serial Data Line ................................................................................................263
13.3 Register Definition ........................................................................................................................263
13.3.1 IIC Address Register (IICA) ...........................................................................................264
13.3.2 IIC Frequency Divider Register (IICF) ..........................................................................264
13.3.3 IIC Control Register (IICC1) ..........................................................................................267
13.3.4 IIC Status Register (IICS) ...............................................................................................268
13.3.5 IIC Data I/O Register (IICD) ..........................................................................................269
13.3.6 IIC Control Register 2 (IICC2) .......................................................................................269
13.4 Functional Description ..................................................................................................................270
13.4.1 IIC Protocol .....................................................................................................................270
13.4.1.1 Start Signal ....................................................................................................271
13.4.1.2 Slave Address Transmission .........................................................................271
13.4.1.3 Data Transfer .................................................................................................272
13.4.1.4 Stop Signal ....................................................................................................272
13.4.1.5 Repeated Start Signal ....................................................................................272
13.4.1.6 Arbitration Procedure ...................................................................................272
13.4.1.7 Clock Synchronization .................................................................................. 273
13.4.1.8 Handshaking .................................................................................................273
13.4.1.9 Clock Stretching ............................................................................................273
13.4.2 10-bit Address .................................................................................................................274
13.4.2.1 Master-Transmitter Addresses a Slave-Receiver ..........................................274
13.4.2.2 Master-Receiver Addresses a Slave-Transmitter ..........................................274
13.4.3 General Call Address ......................................................................................................275
13.5 Resets ............................................................................................................................................275
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13.6 Interrupts .......................................................................................................................................275
13.6.1 Byte Transfer Interrupt ....................................................................................................275
13.6.2 Address Detect Interrupt .................................................................................................275
13.6.3 Arbitration Lost Interrupt ................................................................................................275
13.7 Initialization/Application Information ..........................................................................................277
Chapter 14
Real-Time Counter (S08RTCV1)
14.1 Introduction ...................................................................................................................................281
14.1.1 ADC Hardware Trigger ..................................................................................................281
14.1.2 RTC Clock Sources .........................................................................................................281
14.1.3 RTC Modes of Operation ................................................................................................281
14.1.3.1 RTC Status after Stop2 Wakeup ....................................................................281
14.1.3.2 Clocks in Stop Modes ...................................................................................281
14.1.4 RTC Clock Gating ..........................................................................................................281
14.1.5 Interrupt Vector ...............................................................................................................282
14.1.6 Features ...........................................................................................................................284
14.1.7 Modes of Operation ........................................................................................................284
14.1.7.1 Wait Mode .....................................................................................................284
14.1.7.2 Stop Modes ...................................................................................................284
14.1.7.3 Active Background Mode .............................................................................284
14.1.8 Block Diagram ................................................................................................................285
14.2 External Signal Description ..........................................................................................................285
14.3 Register Definition ........................................................................................................................285
14.3.1 RTC Status and Control Register (RTCSC) ....................................................................286
14.3.2 RTC Counter Register (RTCCNT) ..................................................................................287
14.3.3 RTC Modulo Register (RTCMOD) ................................................................................287
14.4 Functional Description ..................................................................................................................287
14.4.1 RTC Operation Example .................................................................................................288
14.5 Initialization/Application Information ..........................................................................................289
Chapter 15
Serial Communications Interface (S08SCIV4)
15.1 Introduction ...................................................................................................................................291
15.1.1 SCI Clock Gating ............................................................................................................291
15.1.2 Interrupt Vectors .............................................................................................................291
15.1.3 Features ...........................................................................................................................295
15.1.4 Modes of Operation ........................................................................................................295
15.1.5 Block Diagram ................................................................................................................296
15.2 Register Definition ........................................................................................................................298
15.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................298
15.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................299
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15.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................300
15.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................301
15.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................303
15.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................304
15.2.7 SCI Data Register (SCIxD) .............................................................................................305
15.3 Functional Description ..................................................................................................................305
15.3.1 Baud Rate Generation .....................................................................................................305
15.3.2 Transmitter Functional Description ................................................................................306
15.3.2.1 Send Break and Queued Idle ........................................................................306
15.3.3 Receiver Functional Description ....................................................................................307
15.3.3.1 Data Sampling Technique .............................................................................307
15.3.3.2 Receiver Wakeup Operation .........................................................................308
15.3.3.2.1Idle-Line Wakeup .....................................................................308
15.3.3.2.2Address-Mark Wakeup .............................................................309
15.3.4 Interrupts and Status Flags ..............................................................................................309
15.3.5 Additional SCI Functions ...............................................................................................310
15.3.5.1 8- and 9-Bit Data Modes ...............................................................................310
15.3.5.2 Stop Mode Operation ....................................................................................310
15.3.5.3 Loop Mode ....................................................................................................310
15.3.5.4 Single-Wire Operation ..................................................................................311
Chapter 16
Serial Peripheral Interface (S08SPIV3)
16.1 Introduction ...................................................................................................................................313
16.1.1 SPI Clock Gating ............................................................................................................313
16.1.2 Interrupt Vector ...............................................................................................................313
16.1.3 Features ...........................................................................................................................317
16.1.4 Block Diagrams ..............................................................................................................317
16.1.4.1 SPI System Block Diagram ..........................................................................317
16.1.4.2 SPI Module Block Diagram ..........................................................................318
16.1.5 SPI Baud Rate Generation ..............................................................................................319
16.2 External Signal Description ..........................................................................................................320
16.2.1 SPSCK — SPI Serial Clock ............................................................................................320
16.2.2 MOSI — Master Data Out, Slave Data In ......................................................................320
16.2.3 MISO — Master Data In, Slave Data Out ......................................................................320
16.2.4 SS
16.3 Modes of Operation .......................................................................................................................321
16.3.1 SPI in Stop Modes ..........................................................................................................321
16.4 Register Definition ........................................................................................................................321
16.4.1 SPI Control Register 1 (SPIxC1) ....................................................................................321
16.4.2 SPI Control Register 2 (SPIxC2) ....................................................................................322
16.4.3 SPI Baud Rate Register (SPIxBR) ..................................................................................323
— Slave Select ..........................................................................................................320
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16.4.4 SPI Status Register (SPIxS) ............................................................................................324
16.4.5 SPI Data Register (SPIxD) .............................................................................................325
16.5 Functional Description ..................................................................................................................325
16.5.1 SPI Clock Formats ..........................................................................................................326
16.5.2 SPI Interrupts ..................................................................................................................328
16.5.3 Mode Fault Detection .....................................................................................................329
Chapter 17
Timer/Pulse-Width Modulator (S08TPMV3)
17.1 Introduction ...................................................................................................................................331
17.1.1 ACMP/TPM Configuration Information ........................................................................331
17.1.2 TPM Clock Gating ..........................................................................................................331
17.1.3 Interrupt Vector ...............................................................................................................331
17.1.4 Features ...........................................................................................................................335
17.1.5 Modes of Operation ........................................................................................................335
17.1.6 Block Diagram ................................................................................................................336
17.2 Signal Description .........................................................................................................................338
17.2.1 Detailed Signal Descriptions ..........................................................................................338
17.2.1.1 EXTCLK — External Clock Source ............................................................339
17.2.1.2 TPMxCHn — TPM Channel n I/O Pin(s) ....................................................339
17.3 Register Definition ........................................................................................................................341
17.3.1 TPM Status and Control Register (TPMxSC) ................................................................341
17.3.2 TPM Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................342
17.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................343
17.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................344
17.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................346
17.4 Functional Description ..................................................................................................................347
17.4.1 Counter ............................................................................................................................347
17.4.1.1 Counter Clock Source ...................................................................................347
17.4.1.2 Counter Overflow and Modulo Reset ...........................................................348
17.4.1.3 Counting Modes ............................................................................................ 349
17.4.1.4 Manual Counter Reset ..................................................................................349
17.4.2 Channel Mode Selection .................................................................................................349
17.4.2.1 Input Capture Mode ......................................................................................349
17.4.2.2 Output Compare Mode .................................................................................349
17.4.2.3 Edge-Aligned PWM Mode ...........................................................................350
17.4.2.4 Center-Aligned PWM Mode .........................................................................351
17.5 Reset Overview .............................................................................................................................352
17.5.1 General ............................................................................................................................352
17.5.2 Description of Reset Operation .......................................................................................352
17.6 Interrupts .......................................................................................................................................352
17.6.1 General ............................................................................................................................352
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17.6.2 Description of Interrupt Operation .................................................................................353
17.6.2.1 Timer Overflow Interrupt (TOF) Description ...............................................353
17.6.2.1.1Normal Case .............................................................................353
17.6.2.1.2Center-Aligned PWM Case ......................................................354
17.6.2.2 Channel Event Interrupt Description ............................................................354
17.6.2.2.1Input Capture Events ................................................................354
17.6.2.2.2Output Compare Events ...........................................................354
17.6.2.2.3PWM End-of-Duty-Cycle Events ............................................354
Chapter 18
Version 1 ColdFire Debug (CF1_DEBUG)
18.1 Introduction ...................................................................................................................................355
18.1.1 Overview .........................................................................................................................356
18.1.2 Features ...........................................................................................................................357
18.1.3 Modes of Operations .......................................................................................................357
18.2 External Signal Descriptions .........................................................................................................359
18.3 Memory Map/Register Definition .................................................................................................360
18.3.1 Configuration/Status Register (CSR) ..............................................................................361
18.3.2 Extended Configuration/Status Register (XCSR) ...........................................................364
18.3.3 Configuration/Status Register 2 (CSR2) .........................................................................367
18.3.4 Configuration/Status Register 3 (CSR3) .........................................................................370
18.3.5 BDM Address Attribute Register (BAAR) .....................................................................371
18.3.6 Address Attribute Trigger Register (AATR) ...................................................................372
18.3.7 Trigger Definition Register (TDR) .................................................................................373
18.3.8 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) ..................................376
18.3.9 Address Breakpoint Registers (ABLR, ABHR) .............................................................378
18.3.10Data Breakpoint and Mask Registers (DBR, DBMR) ....................................................379
18.3.11Resulting Set of Possible Trigger Combinations ............................................................380
18.4 Functional Description ..................................................................................................................380
18.4.1 Background Debug Mode (BDM) ..................................................................................380
18.4.1.1 CPU Halt .......................................................................................................381
18.4.1.2 Background Debug Serial Interface Controller (BDC) ................................383
18.4.1.3 BDM Communication Details ......................................................................384
18.4.1.4 BDM Command Set Descriptions ................................................................387
18.4.1.5 BDM Command Set Summary .....................................................................390
18.4.1.5.1SYNC .......................................................................................392
18.4.1.5.2ACK_DISABLE ......................................................................393
18.4.1.5.3ACK_ENABLE .......................................................................393
18.4.1.5.4BACKGROUND .....................................................................394
18.4.1.5.5DUMP_MEM.sz, DUMP_MEM.sz_WS .................................394
18.4.1.5.6FILL_MEM.sz, FILL_MEM.sz_WS .......................................395
18.4.1.5.7GO ............................................................................................397
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18.4.1.5.8NOP ..........................................................................................397
18.4.1.5.9READ_CREG ..........................................................................397
18.4.1.5.10READ_DREG ........................................................................398
18.4.1.5.11READ_MEM.sz, READ_MEM.sz_WS ................................398
18.4.1.5.12READ_PSTB .........................................................................399
18.4.1.5.13READ_Rn ..............................................................................400
18.4.1.5.14READ_XCSR_BYTE ............................................................400
18.4.1.5.15READ_CSR2_BYTE .............................................................400
18.4.1.5.16READ_CSR3_BYTE .............................................................400
18.4.1.5.17SYNC_PC ..............................................................................401
18.4.1.5.18WRITE_CREG ......................................................................401
18.4.1.5.19WRITE_DREG ......................................................................402
18.4.1.5.20WRITE_MEM.sz, WRITE_MEM.sz_WS .............................402
18.4.1.5.21WRITE_Rn ............................................................................403
18.4.1.5.22WRITE_XCSR_BYTE ..........................................................404
18.4.1.5.23WRITE_CSR2_BYTE ...........................................................404
18.4.1.5.24WRITE_CSR3_BYTE ...........................................................404
18.4.1.6 Serial Interface Hardware Handshake Protocol ............................................404
18.4.1.7 Hardware Handshake Abort Procedure ........................................................406
18.4.2 Real-Time Debug Support ..............................................................................................409
18.4.3 Real-Time Trace Support ................................................................................................409
18.4.3.1 Begin Execution of Taken Branch (PST = 0x05) .........................................411
18.4.3.2 PST Trace Buffer (PSTB) .............................................................................413
18.4.3.3 PST/DDATA Example ..................................................................................413
18.4.3.4 Processor Status, Debug Data Definition ......................................................414
18.4.3.4.1User Instruction Set ..................................................................415
18.4.3.4.2Supervisor Instruction Set ........................................................418
18.4.4 Freescale-Recommended BDM Pinout ..........................................................................419
Appendix A
Revision History
A.1 Changes between Rev. 2 and Rev. 3 .............................................................................................421
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Chapter 1 Device Overview

The MCF51QE128, MCF51QE64, and MCF51QE32 are members of the low-cost, low-power, high-performance Version 1 (V1) ColdFire family of 32-bit microcontroller units (MCUs). All MCUs in the family use the enhanced V1 ColdFire core and are available with a variety of modules, memory sizes, and package types. CPU clock rates on these devices can reach 50.33 MHz. Peripherals operate up to
25.165 MHz.

1.1 Devices in the MCF51QE128/64/32 Series

Table 1-1 summarizes the feature set available in the MCF51QE128/64/32 series of MCUs.
t
Flash size (Kbytes) 128 64 32
RAM size (Kbytes) 8 8 8
Pin quantity 80 64 64 64
Version 1 ColdFire core with debug yes
ACMP1 yes
Table 1-1. MCF51QE128 Series Features by MCU and Package
Feature MCF51QE128 MCF51QE64 MCF51QE32
ACMP2 yes
ADC channels 24 20 20 20
ICS yes
IIC1 yes
IIC2 yes
KBI 16
Por t I/O
Rapid GPIO yes
COP yes
RTC yes
SCI1 yes
SCI2 yes
SPI1 yes
SPI2 yes
Interrupt Controller yes
1, 2
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Table 1-1. MCF51QE128 Series Features by MCU and Package (continued)
Feature MCF51QE128 MCF51QE64 MCF51QE32
External IRQ yes
Low-Voltage Detect (LVD) yes
TPM1 channels 3
TPM2 channels 3
TPM3 channels 6
XOSC yes
1
Port I/O count does not include the input-only PTA5/IRQ/TPM1CLK/RESET or the output-only PTA4/ACMP1O/BKGD/MS.
2
16 bits associated with Ports C and E are shadowed with ColdFire Rapid GPIO module.

1.2 MCU Block Diagram

The block diagram in Figure 1-1 shows the structure of the MCF51QE128/64/32 MCU.
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Chapter 1 Device Overview
TPM2CH2-0
TPM1CH2-0
ANALOG COMPARATOR
(ACMP1)
ACMP1O
ACMP1-
ACMP1+
V
SS
V
DD
IIC MODULE (IIC1)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
USER FLASH
USER RAM
128K / 64K
V1 ColdFire CORE
CPU
BDC / Debug
6-CHANNEL TIMER/PWM
MODULE (TPM3)
SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
VOLTAGE
REGULATOR
COP
-
LV D
OSCILLATOR (XOSC)
RESET
V
REFL
V
REFH
8K / 4K
BKGD/MS
INTERFACE (SCI1)
SERIAL COMMUNICATIONS
MISO1
SS1
SPSCK1
3-CHANNEL TIMER/PWM
MODULE (TPM2)
REAL TIME COUNTER (RTC)
Rapid GPIO
IRQ
PTA3/KBI1P3/SCL1/ADP3
PTA4/ACMP1O/BKGD/MS
PTA5/IRQ/TPM1CLK/RESET
PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1­PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PORT A
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
MOSI1
PTB3/KBI1P7/MOSI1/ADP7
PTB4/TPM2CH1/MISO1
PTB5/TPM1CH1/SS1
PTB2/KBI1P6/SPSCK1/ADP6 PTB1/KBI1P5/TxD1/ADP5 PTB0/KBI1P4/RxD1/ADP4
PORT B
PTB6/SDA1/XTAL
PTB7/SCL1/EXTAL
PTC3/RGPIO11/TPM3CH3
PTC4/RGPIO12/TPM3CH4/RSTO
PTC5/RGPIO13/TPM3CH5/ACMP2O
PTC2/RGPIO10/TPM3CH2 PTC1/RGPIO9/TPM3CH1 PTC0/RGPIO8/TPM3CH0
PORT C
PTC6/RGPIO14/RxD2/ACMP2+
PTC7/RGPIO15/TxD2/ACMP2-
PTD3/KBI2P3/SS2
PTD4/KBI2P4
PTD5/KBI2P5
PTD2/KBI2P2/MISO2 PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2
PORT D
PTD6/KBI2P6
PTD7/KBI2P7
PTE3/RGPIO3/SS1
PTE4/RGPIO4
PTE5/RGPIO5
PTE2/RGPIO2/MISO1 PTE1/RGPIO1/MOSI1
TPM2CLK
PORT E
PTE6/RGPIO6
PTE0/RGPIO0/TPM2CLK/SPSCK1
PTF3/ADP13
PTF4/ADP14
PTF5/ADP15
PTF2/ADP12 PTF1/ADP11 PTF0/ADP10
PORT F
PTF6/ADP16
PTF7/ADP17
PTG1
PTG2/ADP18
PTG3/ADP19
PORT G
PTG4/ADP20
PTG5/ADP21
PTG0
V
SS
V
DD
V
SSAD
V
DDAD
IP Bus Bridge
INTC
ANALOG COMPARATOR
(ACMP2)
INTERFACE (SCI2)
SERIAL COMMUNICATIONS
TPM3CH5-0
PTG6/ADP22
PTG7/ADP23
SOURCE (ICS)
INTERNAL CLOCK
PORT J
PORT H
PTJ1
PTJ2
PTJ3
PTJ4
PTJ5
PTJ0
PTJ6
PTJ7
PTH1
PTH2
PTH3
PTH4
PTH5
PTH0
PTH6/SCL2
PTH7/SDA2
IIC MODULE (IIC2)
ANALOG-TO-DIGITAL
CONVERTER (ADC)
24-CHANNEL,12-BIT
3-CHANNEL TIMER/PWM
MODULE (TPM1)
SDA2 SCL2
SERIAL PERIPHERAL
INTERFACE MODULE (SPI2)
MISO2
SS2
SPSCK2
MOSI2
EXTAL
XTAL
16
SDA1
SCL1
ACMP2-
ACMP2+
ACMP2O
RxD1
TxD1
RxD2
TxD2
TPM3CLK
3
TPM1CLK
PTE7/RGPIO7/TPM3CLK
Figure 1-1. MCF51QE128/64/32 Block Diagram
Freescale Semiconductor 25
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Table 1-2 provides the functional version of the on-chip modules
Table 1-2. Module Versions
Module Version
Analog Comparator (ACMP) 4
Analog-to-Digital Converter (ADC) 1
V1 ColdFire Core (CF1_CORE) 1
V1 ColdFire Interrupt Controller (CF1_INTC) 1
V1 ColdFire Debug Module (CF1_DEBUG) 1
General Purpose I/O (GPIO) 2
Inter-Integrated Circuit (IIC) 2
Internal Clock Source (ICS) 3
Keyboard Interrupt (KBI) 2
Low-Power Oscillator (OSCVLP) 1
Port Set/Clear (PSC) 1
Rapid GPIO (RGPIO) 1
Real-Time Counter (RTC) 1
Serial Communications Interface (SCI) 4
Serial Peripheral Interface (SPI) 3
Timer Pulse Width Modulator (TPM) 3
Voltage Regulator (PMCx)1

1.3 V1 ColdFire Core

The MCF51QE128/64/32 devices contain the Version 1 (V1) ColdFire core optimized for area and low-power. This CPU implements ColdFire instruction set architecture revision C (ISA_C):
• No hardware support for MAC/EMAC and DIV instructions
1
• Provides upward compatibility to all other ColdFire cores (V2–V5)
For more details on the V1 ColdFire core, see Chapter 7, “ColdFire Core”.

1.4 System Clocks

This section discusses on-chip clock generation and distribution for the MCF51QE128/64/32 devices.

1.4.1 Internal Clock Source (ICS) Module

Figure 1-2 shows a simplified view of the internal clock source module. For clarity, only one of three
available FLL modules is shown.
1. These operations can be emulated via software functions.
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DCO
Filter
RDIV
TRIM
/ 2
9
External Reference
IREFS
Clock Source
Block
CLKS
n=0-7
/ 2
n
n=0-3
/ 2
n
Internal
Reference
Clock
BDIV
9
ICSLCLK
ICSOUT
ICSIRCLK
EREFS
RANGE
EREFSTEN
HGO
Optional
IREFSTEN
ICSERCLK
Internal Clock Source Block
LP
ICSFFCLK
ERCLKEN
IRCLKEN
DCOOUT
FLL
RDIV_CLK
RTC
Figure 1-2. Simplified ICS Block Diagram

1.4.2 System Clock Distribution

Figure 1-3 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) used to drive the module function. All memory mapped registers associated with the modules (except RGPIO) are clocked with the peripheral clock (BUSCLK). The RGPIO registers are clocked with the CPU clock (ICSOUT). With the exception of the oscillator clock supplied directly to the RTC, the ICS supplies all clock sources:
• ICSOUT — This clock source is used throughout the core including the CPU. For consistency, it is known simply as the CPU clock. It is divided by two to generate the peripheral bus clock. Control bits in the ICS control registers determine which of three clock sources is connected:
— Internal reference clock — External reference clock — Frequency-locked loop (FLL) output See Chapter 12, “Internal Clock Source (S08ICSV3),” for details on configuring the ICSOUT
clock.
• ICSLCLK — This clock source is derived from the 10/20 MHz DCO (digitally controlled oscillator) of the ICS when the ICS is configured to run off of the internal or external reference clock. Development tools can select this internal self-clocked source (~10 MHz) to speed up BDC communications in systems where the bus clock is slow.
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TPM1 TPM2 TPM3
SCI1 &
SPI1 &
RAM
CPU &
ADC FLASH GPIO
ICS
ICSOUT
÷2
BUSCLK
ICSLCLK
ICSERCLK
COP
* The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency.
Flash has frequency requirements for program and erase operation. See the MCF51QE128 Data Sheet for details.
ADC has min and max frequency requirements. See the ADC chapter and the MCF51QE128 Data Sheet for details.
XOSC
EXTAL
XTAL
ACMP1 &
FFCLK*
ICSFFCLK
RTC
TPM1CLK
ICSIRCLK
÷2
PMC
IIC1 &
TPM3CLK
TPM2CLK
SYNC*
LPOCLK
BDC
1KHz LPO
OSCOUT
Debug
SCI2
SPI2 ACMP2
IIC2
INTC
RGPIO
Figure 1-3. System Clock Distribution Diagram
• OSCOUT — This is the direct output of the external oscillator module and can be selected as the real-time counter clock source. See Chapter 14, “Real-Time Counter (S08RTCV1),” for more information.
• ICSERCLK — This is the external reference clock and can be selected as the real-time counter clock source or the alternate clock for the ADC module. Section 11.4.7, “External Reference
Clock,” explains the ICSERCLK in more detail. See Chapter 11, “Analog-to-Digital Converter (S08ADC12V1),” for more information regarding the use of ICSERCLK with this module.
• ICSIRCLK — This is the internal reference clock and can be selected as the real-time counter clock source. Section 11.4.6, “Internal Reference Clock,” explains the ICSIRCLK in more detail. See
Chapter 14, “Real-Time Counter (S08RTCV1),” for more information regarding the use of
ICSIRCLK.
• ICSFFCLK — This generates the fixed frequency clock (FFCLK) after being synchronized to the bus clock. It can be selected as clock source for the TPM modules. The frequency of the ICSFFCLK is determined by the settings of the ICS. See Section 11.4.8, “Fixed Frequency Clock,” for details.
• LPOCLK — This clock is generated from an internal low-power oscillator that is completely independent of the ICS module. The LPOCLK can be selected as the clock source to the RTC or COP modules. See Chapter 14, “Real-Time Counter (S08RTCV1),” and Section 5.3.1, “Computer
Operating Properly (COP) Watchdog,” for details on using the LPOCLK with these modules.
•TPMxCLK — TPMxCLKs are optional external clock sources for the TPM modules. The TPMxCLK must be limited to 1/4 the frequency of the bus clock for synchronization. See
Section 16.2.1, “External TPM Clock Sources,” for more details.
28 Freescale Semiconductor
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The ADC module also has an internally generated asynchronous clock that allows it to run in stop mode (ADACK). This signal is not available externally and is not shown in this figure.

1.4.3 ICS Modes of Operation

There are seven modes of operation for the internal clock source (ICS) module: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. These are shown in Figure 1-4. The IREFS and CLKS fields are contained within the ICS module definition. The LP bit is part of the on-chip power management controller (PMC) block. It is the responsibility of the software to ensure that the system bus frequency is less than 125 kHz and the FLLs are disengaged prior to enabling switching the LP bit to enable FBELP and FBILP modes of operation.
The clock source for the BDC is controlled by the debug CLKSW bit, discussed later in this document. Choices for the BDC clock are ICSOUT and the output from the 10MHz bus / 20 MHz CPU clock FLL.
1.4.3.1 FLL Engaged Internal (FEI)
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from one of three on chip FLLs, which are controlled by the internal reference clock. Upon exiting reset, the default FLL generates the 10 MHz bus/20 MHz CPU clocks.
1.4.3.2 FLL Engaged External (FEE)
In FLL engaged external mode, the ICS supplies a clock derived from one of the three FLLs, which are controlled by an external reference clock.
1.4.3.3 FLL Bypassed Internal (FBI)
In FLL bypassed internal mode, the FLLs are enabled and controlled by the internal reference clock, but are bypassed. The ICS supplies a clock derived from the internal reference clock.
1.4.3.4 FLL Bypassed Internal Low-Power (FBILP)
In FLL bypassed internal low-power mode, the FLLs are disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock.
1.4.3.5 FLL Bypassed External (FBE)
In FLL bypassed external mode, the FLLs are enabled and controlled by an external reference clock, but are bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source.
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FLL Bypassed Internal Low­Power(FBILP)
IREFS=1 CLKS=00 LP=0
Entered from any state when MCU enters stop with ENBDM=0.
FLL Engaged Internal (FEI)
FLL Bypassed Internal (FBI)
FLL Bypassed External (FBE)
FLL Engaged External (FEE)
FLL Bypassed External Low­Power(FBELP)
IREFS=0 CLKS=00 LP=0
IREFS=0 CLKS=10 LP=0
Returns to state that was active before MCU entered stop, unless reset occurs while in stop.
IREFS=0 CLKS=10 LP=1
IREFS=1 CLKS=01 LP=0
IREFS=1 CLKS=01 LP=1
Stop
1.4.3.6 FLL Bypassed External Low-Power (FBELP)
In FLL bypassed external low-power mode, the FLLs are disabled and bypassed, and the ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source.
1.4.3.7 Stop (STOP)
In stop mode, the FLLs are disabled and the internal or external reference clocks can be selected to be enabled or disabled. The ICS does not provide an MCU clock source unless the debug ENBDM bit is set.
Figure 1-4. ICS Modes of Operation
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Chapter 2 Pins and Connections

This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals.

2.1 Device Pin Assignment

Figure 2-1 shows the 80-pin assignments for the MCF51QE128 devices. Figure 2-2 shows the 64-pin
assignments for the MCF51QE128/64/32 devices.
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Chapter 2 Pins and Connections
V
REFH
V
SSAD
V
DD
V
REFL
V
DDAD
V
SS
PTB7/SCL1/EXTAL
PTH7/SDA2
PTD0/KBI2P0/SPSCK2
PTD1/KBI2P1/MOSI2
PTE6/RGPIO6
PTB6/SDA1/XTAL
PTH6/SCL2
PTE7/RGPIO7/TPM3CLK
PTH1 PTH0
PTH3 PTH2
PTH5 PTH4
PTC2/RGPIO10/TPM3CH2
PTB4/TPM2CH1/MISO1
PTB5/TPM1CH1/SS1
PTC3/RGPIO11/TPM3CH3
PTD7/KBI2P7
PTC0/RGPIO8/TPM3CH0
PTC1/RGPIO9/TPM3CH1
PTD6/KBI2P6
PTD5/KBI2P5
PTB3/KBI1P7/MOSI1/ADP7
PTB2/KBI1P6/SPSCK1/ADP6
PTE5/RGPIO5
PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTD4/KBI2P4
V
DD
V
SS
PTA7/TPM2CH2/ADP9
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
PTA2/KBI1P2/SDA1/ADP2 PTA3/KBI1P3/SCL1/ADP3
PTA6/TPM1CH2/ADP8
PTD3/KBI2P3/SS2
PTD2/KBI2P2/MISO2
PTE4/RGPIO4
PTF0/ADP10 PTF1/ADP11
PTF2/ADP12 PTF3/ADP13
PTE2/RGPIO2/MISO1
PTA5/IRQ/TPM1CLK/RESE
T
PTA4/ACMP1O/BKGD/MS
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTC7/RGPIO15 /TxD2/ACMP2-
PTC5/RGPIO13/TPM3CH5/ACMP2O
PTC4/RGPIO12/TPM3CH4/RSTO
PTC6/RGPIO14/RxD2/ACMP2+
PTE0/RGPIO0/TPM2CLK/SPSCK1
PTE1/RGPIO1/MOSI1
PTE3/RGPIO3/SS1
PTG3/ADP19
PTG2/ADP18
PTG1
PTG0
PTG7/ADP23
PTG6/ADP22
PTG5/ADP21
PTG4/ADP20
PTJ4
PTJ5
PTJ6
PTJ7
PTJ1
PTJ0
PTJ3
PTJ2
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
Pins in bold are added from the next smaller package.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80797877767574737271706968676665646362
61
21222324252627282930313233343536373839
40
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Figure 2-1. 80-Pin LQFP
34 Freescale Semiconductor
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Chapter 2 Pins and Connections
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
171819202122232425262728293031
32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
646362616059585756555453525150
49
V
REFH
V
SSAD
V
DD
V
REFL
V
DDAD
V
SS
PTB7/SCL1/EXTAL
PTH7/SDA2
PTD0/KBI2P0/SPSCK2
PTD1/KBI2P1/MOSI2
PTE6/RGPIO6
PTB6/SDA1/XTAL
PTC2/RGPIO10/TPM3CH2
PTB4/TPM2CH1/MISO1
PTB5/TPM1CH1/SS1
PTC3/RGPIO11/TPM3CH3
PTD7/KBI2P7
PTC0/RGPIO8/TPM3CH0
PTC1/RGPIO9/TPM3CH1
PTD6/KBI2P6
PTD5/KBI2P5
PTB3/KBI1P7/MOSI1/ADP7
PTB2/KBI1P6/SPSCK1/ADP6
PTE5/RGPIO5
PTD4/KBI2P4
V
DD
V
SS
PTA7/TPM2CH2/ADP9
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
PTA2/KBI1P2/SDA11/ADP2 PTA3/KBI1P3/SCL1/ADP3
PTA6/TPM1CH2/ADP8
PTD3/KBI2P3/SS2
PTD2/KBI2P2/MISO2
PTE4/RGPIO4
PTE2/RGPIO2/MISO1
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
PTC7/RGPIO15/TxD2/ACMP2-
PTC5/RGPIO13/TPM3CH5/ACMP2O
PTC4/RGPIO12/TPM3CH4/RSTO
PTC6/RGPIO14/RxD2/ACMP2+
PTE0/RGPIO0/TPM2CLK/SPSCK1
PTE1/RGPIO1/MOSI1
PTE3/RGPIO3/SS1
PTF0/ADP10 PTF1/ADP11
PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTF2/ADP12 PTF3/ADP13
PTG3/ADP19
PTG2/ADP18
PTG1
PTG0
PTH6/SCL2
PTE7/RGPIO7/TPM3CLK
PTH1 PTH0

2.2 Recommended System Connections

Figure 2-3 shows pin connections common to MCF51QE128/64/32 application systems.
Figure 2-2. 64-Pin LQFP
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Freescale Semiconductor 35
Chapter 2 Pins and Connections
V
DD
V
SS
BKGD/MS
RESET/IRQ
OPTIONAL
MANUAL
RESET
PORT
A
V
DD
BACKGROUND HEADER
C2
C1
X1
R
F
R
S
C
BY
0.1 μF
SYSTEM POWER
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1­PTA2/KBI1P2/SDA1/ADP2 PTA3/KBI1P3/SCL1/ADP3 PTA4/ACMP1O/BKGD/MS PTA5/IRQ/TPM1CLK/RESET PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9
PORT
B
PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5 PTB2/KBI1P6/SPSCK1/ADP6 PTB3/KBI1P7/MOSI1/ADP7 PTB4/TPM2CH1/MISO1 PTB5/TPM1CH1/SS1 PTB6/SDA1/XTAL PTB7/SCL1/EXTAL
PORT
C
PTC0/RGPIO8/TPM3CH0 PTC1/RGPIO9/TPM3CH1 PTC2/RGPIO10TPM3CH2 PTC3/RGPIO11/TPM3CH3 PTC4/RGPIO12/TPM3CH4/RSTO PTC5/RGPIO13/TPM3CH5/ACMP2O PTC6/RGPIO14/RxD2/ACMP2+
D
PTD0/KBI2P0/SPSCK2 PTD1/KBI2P1/MOSI2 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 PTD4/KBI2P4 PTD5/KBI2P5 PTD6/KBI2P6 PTD7/KBI2P7
PORT
E
PTE0/RGPIO0/TPM2CLK/SPSCK1 PTE1/RGPIO1/MOSI1 PTE2/RGPIO2/MISO1 PTE3/RGPIO3/SS1 PTE4/RGPIO4 PTE5/RGPIO5 PTE6/RGPIO6 PTE7/RGPIO7/TPM3CLK
PORT
H
PTH0 PTH1 PTH2 PTH3 PTH4
PTH5 PTH6/SCL2 PTH7/SDA2
MCF51QE128
V
REFH
V
REFL
C
BYAD
0.1 μF
V
SSAD
V
DDAD
PTC7/RGPIO15/TxD2/ACMP2-
VDD
V
SS
C
BY
0.1 μF
C
BLK
10 μF
+
3 V
+
PORT
PTF0/ADP10 PTF1/ADP11 PTF2/ADP12 PTF3/ADP13 PTF4/ADP14 PTF5/ADP15 PTF6/ADP16 PTF7/ADP17
PORT
F
PTG0 PTG1 PTG2/ADP18 PTG3/ADP19 PTG4/ADP20 PTG5/ADP21 PTG6/ADP22 PTG7/ADP23
PORT
G
PORT
J
PTJ0 PTJ1 PTJ2 PTJ3 PTJ4 PTJ5 PTJ6 PTJ7
OPTIONAL EXTERNAL OSCILLATOR
OPTIONAL
EMC
PROTECTION
V
DD
4.7 kΩ–10 k
Ω
0.1 μF
XTAL
EXTAL
NOTES:
1
RESET pin can only be used to reset into user mode; it cannot be used to enter BDM. Entry into BDM is accomplished by holding BGKD low during POR or setting CSR2[BDFR] with BGKD held low after issuing the BDM write command.
2
RESET/IRQ features have optional internal pullup device.
3
RC filter on RESET/IRQ pin recommended for noisy environments.
(NOTE 3)
(NOTE 1)
(NOTE 2)
36 Freescale Semiconductor
Figure 2-3. Basic System Connections
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Chapter 2 Pins and Connections

2.2.1 Power

VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10μF tantalum capacitor , to provide bulk charge storage for the overall system and a 0.1μF ceramic bypass capacitor located as close to the MCU power pins as practical to suppress high-frequency noise. The MCF51QE128/64/32has two VDD pins. Each pin must have a bypass capacitor for best noise suppression.
V
DDAD
and V
are the analog power supply pins for the MCU. This voltage source supplies power to
SSAD
the ADC module. A 0.1μF ceramic bypass capacitor should be located as close to the MCU power pins as practical to suppress high-frequency noise.

2.2.2 Oscillator

Immediately after reset, the MCU uses an internally generated clock provided by the internal clock source (ICS) module. For more information on the ICS, see Chapter 12, “Internal Clock Source (S08ICSV3)”.
The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator. Optionally, an external clock source can be connected to the EXTAL input pin.
Refer to Figure 2-3 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors specifically designed for high-frequency applications.
RF is used to provide a bias path to keep the EXT AL input in its linear range during crystal startup; its value is not generally critical. T ypical systems use 1 MΩ to 10 MΩ . Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5pF to 25pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance that is the series combination of C1 and C2 (which are usually the same size). As a first-order approximation, use 10pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXT AL and XTAL).

2.2.3 RESET and RSTO

After a power-on reset (POR), the PTA5/IRQ/TPM1CLK/RESET pin defaults to a general-purpose input port pin, PTA5. Setting RSTPE in SOPT1 configures the pin to be the RESET RESET, the pin remains RESET until the next POR. The RESET pin can be used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET configured as an input with an internal pullup device automatically enabled.
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pin. After configured as
pin (RSTPE = 1), the pin is
Chapter 2 Pins and Connections
NOTE
The RESET pin does not contain a clamp diode to VDD and should not be driven above VDD.
NOTE
In EMC-sensitive applications, an external RC filter is recommended on the RESET pin, if enabled. See Figure 2-3 for an example.
After a power-on reset (POR), the PTC4/RGPIO12/TPM3CH4/RSTO pin defaults to a general-purpose port pin, P TC4. Setting RSTOPE in SOPT1 configures the pin as an open drain with internal pullup acting as reset out (RSTO). The RSTO pin reflects the current state of the internal MCU reset signal. As long as the MCU is not in a reset state, the RSTO pin is driven high. When an internal reset occurs and RSTPE is set, the RSTO pin is pulled low for as long as the internal reset signal is low. This allows other devices in the system to detect the MCU’s reset state.
When enabled as the RSTO pin (RSTOPE = 1), the pin is automatically configured as an output only . The RSTO pin can be enabled independently of the RESET pin. After being configured as RSTO, the pin remains in this mode until the next POR.
NOTE
The RSTO pullup should not be used as a pullup for components external to the MCU. Inputs to internal gates connected to this pin are resistively pulled high, but VDD is not seen at the pin itself.

2.2.4 Background / Mode Select (BKGD/MS)

During a power-on-reset (POR) or background debug force reset (see the BDFR bit in Section 18.3.3,
“Configuration/Status Register 2 (CSR2),” for more information), the PTA4/ACMP1O/BKGD/MS pin
functions as a mode select pin. Immediately after any reset, the pin functions as the background data pin and can be used for background debug communication.
The debug communication function is enabled when SOPT1[BKGDPE] is set. When enabled as the BKGD/MS pin (BKGDPE = 1), an internal pullup device is automatically enabled. BKGDPE is set following any reset of the MCU and must be cleared to use the PTA4/ACMP1O/BKGD/MS pin’s alternative pin functions.
If this pin is unconnected, the MCU enters normal operating mode at the rising edge of the internal reset after a POR or forced BDC reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a background debug force
1
, which forces the MCU to halt mode.
reset The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a
custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock can be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications.
1. Specifically, BKGD must be held low through the first 16 cycles after deassertion of the internal reset.
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Chapter 2 Pins and Connections
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speed-up pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD/MS pin.
2.2.5 ADC Reference Pins (V
The V
REFH
and V
pins are the voltage reference high and voltage reference low inputs, respectively ,
REFL
REFH
, V
REFL
)
for the ADC module.

2.2.6 General-Purpose I/O and Peripheral Ports

The MCF51QE128/64/32series of MCUs support up to 70 general-purpose I/O pins, 1 input-only pin, and 1 output-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, ACMP, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. When a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pull-up device. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pull-up devices enabled.
PTC4 is a special case I/O pin. When the PTC4/RGPIO12/TPM3CH4/RSTO pin is configured as RSTO, it is an open drain output with an internal pullup. The voltage observed on the pin is not pulled to VDD, and an external pullup resistor is recommended if this pin must drive off-chip signals.
PTA5/IRQ/TPM1CLK/RESET is also a special case I/O pin. It can only be configured as an input. When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from the port data registers, even though the peripheral controls the pin direction via the pin’ s output buffer enable. For information about controlling these pins as general-purpose I/O pins, see Chapter 6,
“Parallel Input/Output Control”.
NOTE
T o avoid extra current drain from floating input pins, the reset initialization routine in the application program should enable on-chip pullup devices or change the direction of unused or non-bonded pins to outputs so they do not float.
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Chapter 2 Pins and Connections
Table 2-1. Pin Assignment by Package and Pin Sharing Priority
Pin
Number
Lowest ←⎯ Priority ⎯→ Highest
80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4
1 1 PTD1 KBI2P1 MOSI2
2 2 PTD0 KBI2P0 SPSCK2
3 3 PTH7 SDA2
44 PTH6 SCL2
5— PTH5
6— PTH4
7 5 PTE7 RGPIO7 TPM3CLK
86 V
97 V
10 8 V
11 9 V
12 10 V
13 11 V
14 12 PTB7 SCL1 EXTAL
15 13 PTB6 SDA1 XTAL
16 — PTH3
17 — PTH2
18 14 PTH1
19 15 PTH0
20 16 PTE6 RGPIO6
21 17 PTE5 RGPIO5
22 18 PTB5 TPM1CH1 SS1
23 19 PTB4 TPM2CH1 MISO1
24 20 PTC3 RGPIO11 TPM3CH3
25 21 PTC2 RGPIO10 TPM3CH2
26 22 PTD7 KBI2P7
27 23 PTD6 KBI2P6
28 24 PTD5 KBI2P5
29 — PTJ7
30 — PTJ6
31 — PTJ5
32 — PTJ4
33 25 PTC1 RGPIO9 TPM3CH1
34 26 PTC0 RGPIO8 TPM3CH0
35 27 PTF7 ADP17
36 28 PTF6 ADP16
37 29 PTF5 ADP15
38 30 PTF4 ADP14
39 31 PTB3 KBI1P7 MOSI1
1
40 32 PTB2 KBI1P6 SPSCK1 ADP6
41 33 PTB1 KBI1P5 TxD1 ADP5
42 34 PTB0 KBI1P4 RxD1 ADP4
43 — PTJ3
DD
DDAD
REFH
REFL
SSAD
SS
ADP7
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Table 2-1. Pin Assignment by Package and Pin Sharing Priority (continued)
Pin
Number
Lowest ←⎯ Priority ⎯→ Highest
80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4
44 — PTJ2
45 35 PTF3 ADP13
46 36 PTF2 ADP12
47 37 PTA7 TPM2CH2 ADP9
48 38 PTA6 TPM1CH2 ADP8
49 39 PTE4 RGPIO4
50 40 VDD
51 41 VSS
52 42 PTF1 ADP11
53 43 PTF0 ADP10
54 — PTJ1
55 — PTJ0
56 44 PTD4 KBI2P4
57 45 PTD3 KBI2P3 SS2
58 46 PTD2 KBI2P2 MISO2
59 47 PTA3 KBI1P3 SCL1
60 48 PTA2 KBI1P2 SDA1 ADP2
61 49 PTA1 KBI1P1 TPM2CH0 ADP1 ACMP1-
62 50 PTA0 KBI1P0 TPM1CH0 ADP0 ACMP1+
63 51 PTC7 RGPIO15 TxD2 ACMP2-
64 52 PTC6 RGPIO14 RxD2 ACMP2+
65 — PTG7 ADP23
66 — PTG6 ADP22
67 — PTG5 ADP21
68 — PTG4 ADP20
69 53 PTE3 RGPIO3 SS1
70 54 PTE2 RGPIO2 MISO1
71 55 PTG3 ADP19
72 56 PTG2 ADP18
73 57 PTG1
74 58 PTG0
75 59 PTE1 RGPIO1 MOSI1
76 60 PTE0 RGPIO0 TPM2CLK SPSCK1
77 61 PTC5 RGPIO13 TPM3CH5 ACMP2O
78 62 PTC4 RGPIO12 TPM3CH4 RSTO
79 63 PTA5 IRQ TPM1CLK RESET
80 64 PTA4
1
SPI1 pins (SS1, MISO1, MOSI1, and SPSCK2) can be repositioned using
3
ACMP1O BKGD MS
2
ADP3
SOPT2[SPI1PS]. Default locations are PTB5, PTB4, PTB3, and PTB2, respectively.
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Chapter 2 Pins and Connections
2
IIC1 pins (SCL1 and SDA1) can be repositioned using SOPT2[IIC1PS]. Default locations are PTA3 and PTA2, respectively.
3
PTA4/ACMP1O/BKGD/MS is limited to output-only for the port I/O function.
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Chapter 3 Modes of Operation

3.1 Introduction

The operating modes of the MCF51QE128/64/32 are described in this chapter . Entry into each mode, exit from each mode, and functionality while in each of the modes are described.
The overall system mode is generally a function of a number of separate, but inter-related variables: debug mode, security mode, power mode, and clock mode. Clock modes were discussed in Section 1.4.3, “ICS
Modes of Operation”. This chapter explores the other dimensions of the system operating mode.

3.2 Features

• Debug mode for code development. For V1 ColdFire devices, such as MCF51QE128/64/32 , debug mode is mutually exclusive with use of secure mode (next item).
• Secure mode — BDC access to CPU resources is extremely restricted. It is possible to tell that the device has been secured, and to clear security, which involves mass erasing the on-chip flash memory. No other CPU access is allowed. Secure mode can be used in conjunction with each of the power modes below.
• Run mode — CPU clocks can be run at full speed and the internal supply is fully regulated.
• LPrun mode — CPU and peripheral clocks are restricted to 250 kHz CPU clock and 125 kHz bus clock maximum and the internal supply is in soft regulation.
• Wait mode — CPU shuts down to conserve power; peripheral clocks are running and full regulation is maintained.
• LPwait mode — CPU shuts down to conserve power; peripheral clocks are running at reduced speed (125 kHz maximum) and the internal voltage regulator is running in loose regulation mode.
• Stop modes — System (CPU and peripheral) clocks are stopped. — Stop4 — All internal circuits are powered (full regulation mode) and internal clock sources still
at max frequency for fastest recovery.
— Stop3 — All internal circuits are loosely regulated and clocks sources are at minimal values
(125 kHz maximum), providing a good compromise between power utilization and speed of recovery.
— Stop2 — Partial power-down of internal circuits; RAM content is retained. The lowest power
mode for this device. A reset is required to return from stop2 mode.
On the MCF51QE128/64/32 , wait, stop2, stop3, and stop4 are all entered via the CPU STOP instruction. See Table 3-1, Figure 3-2, and subsequent sections of this chapter for details.
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Chapter 3 Modes of Operation
STOP
SOPT1[STOPE]
SOPT1[WAITE]
SPMSC1[LVDE]
SPMSC1[LVDSE]
SPMSC2[PPDC]
In Stop Mode
Partial Power Down
Standby Enable
CSR2[ENBDM]
SPMSC2[LPR]
LVD O f f
Standby

3.3 Overview

The ColdFire CPU has two primary user modes of operation, run and stop. (The CPU also supports a halt mode that is used strictly for debug operations.) The STOP instruction is used to invoke stop and wait modes for this family of devices.
If the WAITE control bit is set when STOP is executed, the wait mode is entered. Otherwise, if the STOPE bit is set, the CPU enters one of the stop modes. It is illegal to execute a STOP instruction if neither STOPE or WAITE are set. This results in reset assertion if CPUCR[IRD] is cleared or an illegal instruction exception if CPUCR[IRD] is set.
The MCF51QE128/64/32 devices augment stop, wait, and run in a number of ways. The power management controller (PMC) can run the device in fully-regulated mode, standby mode, and partial power-down mode. Standby (loose regulation) or partial power-down can be programmed to occur naturally as a result of a STOP instruction. Additionally, standby mode can be explicitly invoked via the LPR (low-power) bit in the PMC. Use of standby is limited to bus frequencies less than 125 kHz; and neither standby nor partial power-down are allowed when the ENBDM bit is set to enable debugging in stop and wait modes.
During partial power-down mode, the regulator is in standby mode and much of the digital logic on the chip is switched off. These interactions can be seen schematically in Figure 3-1. This figure is for conceptual purposes only. It does not reflect any sequence or time dependencies between the PMC and other parts of the device, nor does it represent any actual design partitioning.
It is illegal for the software to have PPDC and LPR asserted concurrently. This restriction arises because the sequence of events from normal to low-power modes involves use of both bits. After entering a low-power mode, it is not possible to switch to another low-power mode.
44 Freescale Semiconductor
Figure 3-1. MCF51QE128/64/32 Power Modes - Conceptual Drawing
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Table 3-1. CPU / Power Mode Selections
Chapter 3 Modes of Operation
SOPT1
SIM
Mode of Operation
STOPE
Run mode - processor and peripherals clocked
normally.
LPrun mode with low voltage detect disabled ­processor and peripherals clocked at low
2
frequency Low voltage detects are not active.
Wait mode - processor clock nominally inactive, but peripherals are clocked.
LPwait mode - processor clock is inactive, peripherals are clocked at low frequency and the PMC is loosely regulating. Low voltage detects are not active.
Stop modes disabled; Illegal opcode reset if STOP instruction executed and CPUCR[IRD] is cleared, else illegal instruction exception is generated.
Stop4 - Either low-power modes have not been requested, or low voltage detects are enabled or ENBDM = 1.
Stop3 - Low voltage detect in stop is not enabled. Clocks must be at low frequency and are gated. The regulator is in loose regulation.
Stop2 - Low voltage detects are not active. If BDC is enabled, stop4 is invoked rather than stop2.
1
.
ENBDM is located in the upper byte of the XCSR register which is write-accessible only through BDC commands, see
xx
xx
x
x
0 0
1 0
1 0 0
1 0
CSR2
BDC
WAITE
1
10
Function
of BKGD/
MS at
reset
SPMSC1
PMC
1
LV DE
ENBDM
xxx
1 1xx
1 xxxx
0x
0
01
xxx
1 1xx
1 xxxx On
0x
1
⇒1 ⇒1 ⇒0 ⇒0 ⇒On
xxx
1 1 1 0
x
1 1 0 1
x
1 xxxx
1
0x
1 0
0x
SPMSC2
PMC
LPR
LV DS E
0x
10
0
0x
10
0
0 0
0
1 0
0 1N/A N/A Off
CPU and
Peripheral Clocks
PPDC
On. ICS in any
mode
Low freq required.
ICS in FBELP
mode.
Periph clocks on.
CPU clock on if
ENBDM=1.
CPU clock is off.
Periph clocks at
low speed.
ICS in FBELP.
Peripheral clocks
off. CPU clock on if
ENBDM=1.
CPU clock on.
Periph clocks off.
Low freq required.
ICS in FBELP
mode. CPU and
peripheral clocks
are gated off.
Effects on Sub-System
BDC Clock
On
Note: When not
needed, the BDC clock can be gated off at the discretion
of the processor.
The clock is
available within a
few cycles of
demand by the
processor, normally when a negative edge is
detected on
BKGD. The BDM
command
associated with
that negative edge
may not take
affect.
Function of
BKGD/MS at reset
BDC clock enabled
only if ENBDM=1
prior to entering
stop.
Off Loose Reg
Section 18.3.2, “Extended Configuration/Status Register (XCSR)”.
2
250 kHz maximum CPU frequency in LPrun; 125 kHz maximum peripheral clock frequency.
Switched
Power
Onx
Loose Reg
Onx
Loose Reg
⇒On
On
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Chapter 3 Modes of Operation
Mode Regulator State
Run Full On
Wait Full On
Stop4 Full On
LPrun Standby
LPwait Standby
Stop3 Standby
Stop2 Partial Power Off
Stop3
Stop2
LPwait
Stop4
Wait
Run LPrun
Figure 3-2. Allowable Power Mode Transitions for Mission Mode MCF51QE128/64/32
Figure 3-2 illustrates mission mode state transitions allowed between the legal states shown in Table 3-1.
PTA5/IRQ/TPM1CLK/RESET must be asserted low to exit stop2. Only interrupt assertion is necessary to exit the other stop and wait modes.
Figure 3-3 takes the same set of states and transitions shown in Figure 3-2 and adds the BDM halt mode
for development purposes. If BDM is enabled, the chip automatically shifts LP modes into their fully regulated equivalents. If software or debugger set the LPR bit in SPMSC2 while BDM is enabled, the LPRS bit reflects the fact that the regulator is not in standby. Similarly, the PPDF does not indicate a recovery from stop2 if ENBDM forced stop4 to occur in its place.
1
Stated another way , if ENBDM has been set via the BDM interface, then the power management controller keeps (or puts) the regulator in full regulation despite other settings in the contrary. The states shown in
Figure 3-3 then map as follows:
• LPrun ⇒ Run
•LPwait ⇒ Wait
• Stop3 ⇒ Stop4
• Stop2 ⇒ Stop4
From a software perspective (and disregarding PMC status bits), the system remains in the appropriate low-power state, and can be debugged as such.
See Section 3.7, “Wait Modes,” for a description of the various ways to enter halt mode.
1. This can have subtle impacts on recovery from stop. The IRQ input can wake the device from stop4 if it has been enabled for that purpose. That same pin wakes the device from stop2 even when the IRQ is not enabled (there is an asynchronous path to the power management controller in that state).
46 Freescale Semiconductor
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Figure 3-3. All Allowable Power Mode Transitions for MCF51QE128/64/32
Stop3
1
Stop2
LPwait
Stop4
Wait
Run LPrun
48
7
6
2
53
Halt
9
11
10
Table 3-2 defines triggers for the various state transitions shown in Figure 3-2.
Table 3-2 . Tr i g g ers fo r Transiti o n s Shown in Figure 3-2
Transition # From To Trigger
Chapter 3 Modes of Operation
Run LPrun
1
LPrun Run
Run Stop2
2
Stop2 Run
3
4
5
6
7
LPrun LPwait
LPwait LPrun Interrupt when LPWUI=0
LPrun Stop3 Execute STOP instruction
Stop3 LPrun Interrupt when LPWUI=0
LPwait Run Interrupt when LPWUI=1
Run LPwait Not supported.
Run Wait
Wait Run Interrupt
Run Stop4
Stop4 Run Interrupt
Configure settings shown in Ta bl e 3 - 1, switch LPR=1 last
Clear LPR
Interrupt when LPWUI=1
Negative transition on enabled BKGD/MS pin.
Pre-configure settings shown in Ta bl e 3 - 1, execute STOP instruction
1
Assert zero on PTA5/IRQ/TPM1CLK/RESET RTC timeout. Reload environment from RAM
Pre-configure settings shown in Ta bl e 3 - 1, execute STOP instruction
Pre-configure settings shown in Ta bl e 3 - 1, execute STOP instruction
Pre-configure settings shown in Ta bl e 3 - 1, execute STOP instruction
or
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Chapter 3 Modes of Operation
Table 3-2. Triggers for Transitions Shown in Figure 3-2 (continued)
Transition # From To Trigger
Stop3 Run Interrupt when LPWUI=1
8
Run Stop3
Stop4 Halt
9
Halt Stop4 Not supported.
Halt Run GO instruction issued via BDM
Pre-configure settings shown in Ta bl e 3 - 1, execute STOP instruction
When a BACKGROUND command is received through the BKGD/MS pin (ENBDM must equal one).
10
11
1
An analog connection from this pin to the on-chip regulator wakes up the regulator, which then initiates a power-on-reset sequence.
Run Halt
Wait Halt
Halt Wait Not supported.
When a BACKGROUND command is received through the BKGD/MS pin OR When a HALT instruction is executed OR When encountering a BDM breakpoint
When a BACKGROUND command is received through the BKGD/MS pin (ENBDM must equal one).
Individual power states are discussed in more detail in the following sections.

3.4 Debug Mode

Debug mode functions are managed through the background debug controller (BDC) in the Version 1 ColdFire core. The BDC provides the means for analyzing MCU operation during software development.
The debug interface is used to program a bootloader or user application program into the flash program memory before the MCU is operated in run mode for the first time. When the MCF51QE128/64/32 is shipped from the Freescale Semiconductor factory , the flash program memory is erased by default unless specifically noted, so there is no program that could be executed in run mode until the flash memory is initially programmed. The debug interface can also be used to erase and reprogram the flash memory after it has been previously programmed.
See Chapter 18, “Version 1 ColdFire Debug (CF1_DEBUG),” for more details regarding the debug interface.

3.5 Secure Mode

While the MCU is in secure mode, there are severe restrictions on which debug commands can be used. In this mode, only the upper byte of the core’s XCSR, CSR2, and CSR3 registers can be accessed. See
Chapter 18, “Version 1 ColdFire Debug (CF1_DEBUG),” for details.
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Chapter 3 Modes of Operation

3.6 Run Modes

3.6.1 Run Mode

Run mode is the normal operating mode for the MCF51QE128/64/32. This mode is selected when the BKGD/MS pin is high at the rising edge of the internal reset signal. Upon exiting reset, the CPU fetches the supervisor SR and initial PC from locations 0x(00)00_0000 and 0x(00)00_0004 in the memory map and executes code starting at the newly set value of the PC.

3.6.2 Low-Power Run Mode (LPrun)

In the low-power run mode, the on-chip voltage regulator is put into its standby (or loose regulation) state. In this state, the power consumption is reduced to a minimum that allows CPU functionality. Power consumption is reduced the most by disabling the clocks to all unused peripherals by clearing the corresponding bits in the SCGC1 and SCGC2 registers1.
Before entering this mode, the following conditions must be met:
•FBELP2 is the selected clock mode for the ICS. See Section 12.1.5.6, “FLL Bypassed External
Low Power (FBELP),” for more details.
• ICSC2[HGO] is cleared.
• The bus frequency is less than 125 kHz.
• The ADC must be in low-power mode (ADLPC=1) or disabled.
• Low-voltage detect must be disabled. The LVDE and/or LVDSE bit in SPMSC1 register must be cleared.
• Flash programming/erasing is not allowed
After these conditions are met, low-power run mode can be entered by setting SPMSC2[LPR]. T o re-enter standard run mode, clear the LPR bit. SPMSC2[LPRS] is a read-only status bit that can be used
to determine if the regulator is in full-regulation mode or not. When LPRS is cleared, the regulator is in full-regulation mode and the MCU can run at full speed in any clock mode.
Assuming that SOP T1[BKGDPE] is set to enable BKGD/MS, the device also switches from LPrun to run mode when it detects a negative transition on the BKGD/MS pin.
Low-power run mode also provides the option to return to full regulation if any interrupt occurs. This is done by setting SPMSC2[LPWUI]. The ICS can then be set for full speed immediately in the interrupt service routine.
3.6.2.1 BDM in Low-Power Run Mode
Low-power run mode cannot be entered when the MCU is in active background debug mode. If a device is in low-power run mode, a falling edge on an active BKGD/MS pin exits low-power run mode,
clears the LPR and LPRS bits, and returns the device to normal run mode.
1. System clock gating control registers 1 and 2
2. FLL bypassed external low-power
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Chapter 3 Modes of Operation

3.7 Wait Modes

3.7.1 Wait Mode

W ait mode is entered by executing a ST OP instruction after configuring the device as per Table 3-1. Upon execution of the STOP instruction, the CPU enters a low-power state in which it is not clocked.
The V1 ColdFire core does not differentiate between stop and wait modes. Both are stop from the core’s perspective. The difference between the two is at the device level. In stop mode, most peripheral clocks are shut down. In wait mode, they continue to run.
XCSR[ENBDM] must be set prior to entering wait mode if the device is required to respond to BDM commands once in wait.
When an interrupt request occurs, the CPU exits wait mode and resumes with exception processing, beginning with the stacking operations leading to the interrupt service routine.

3.7.2 Low-Power Wait Mode (LPwait)

Low-power wait mode is entered by executing a STOP instruction while the MCU is in low-power run mode and configured per Table 3-1. In the low-power wait mode, the on-chip voltage regulator remains in its standby state as in the low-power run mode. In this state, the power consumption is reduced to a minimum that allows most modules to maintain funtionality. Power consumption is reduced the most by disabling the clocks to all unused peripherals by clearing the corresponding bits in the SCGC registers.
Low-power run mode restrictions also apply to low-power wait mode. If the LPWUI bit is set when the STOP instruction is executed, the voltage regulator returns to full
regulation when wait mode is exited. The ICS can be set for full speed immediately in the interrupt service routine.
If the LPWUI bit is cleared when the STOP instruction is executed, the device returns to low-power run mode.
Any reset exits low-power wait mode, clears the LPR bit, and returns the device to normal run mode.
3.7.2.1 BDM in Low-Power Wait Mode
If a device is in low-power wait mode, a falling edge on an active BKGD/MS pin exits low-power wait mode, clears the LPR and LPRS bits, and returns the device to normal run mode.

3.8 Stop Modes

One of three stop modes is entered upon execution of a STOP instruction when SOP T1[STOPE] is set. The SOP T1[WAITE] bit must be clear, else wait mode is entered. In stop3 mode, the bus and CPU clocks are halted. If the ENBDM bit is set prior to entering stop4, only the peripheral clocks are halted. The ICS module can be configured to leave the reference clocks running. See Chapter 12, “Internal Clock Source
(S08ICSV3),” for more information.
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NOTE
If neither the WAITE nor STOPE bit is set when the CPU executes a STOP instruction, the MCU does not enter either of the stop modes. Instead, the MCU initiates an illegal opcode reset if CPUCR[IRD] is cleared or an illegal instruction exception if CPUCR[IRD] is set.
The stop modes are selected by setting the appropriate bits in the system power management status and control 2 (SPMSC2) register. Table 3-1 shows all of the control bits that affect mode selection under various conditions. The selected mode is entered following the execution of a STOP instruction.
Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop4 and enter halt mode if the ENBDM bit was set prior to entering stop. After entering halt mode, all background commands are available.

3.8.1 Stop2 Mode

Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM and
optionally the R TC. Upon entering stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.
Exit from stop2 is performed by driving the wake-up pin (P TA5/IRQ/TPM1CLK/RESET) on the MCU to zero.
NOTE
PTA5/IRQ/TPM1CLK/RESET
functions as an active-low wakeup input when the MCU is in stop2, as long as the pin is configured as an input before entering stop2. The pullup on this pin is not automatically enabled in stop2. To enable the internal pullup, set PTAPE[PTAPE5].
In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled. Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):
• All module control and status registers are reset, with the exception of the power management controller (SPMSC1/2/3), R TC, and debug trace buffer . Refer to the individual module chapters for more information on which other registers are unaffected by wake-up from stop2 mode.
• The L VD reset function is enabled and the MCU remains in the reset state if V
is below the L VD
DD
trip point (low trip point selected due to POR).
• The CPU initiates reset exception processing by fetching the vectors at 0x(00)00_0000 and 0x(00)00_0004.
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Chapter 3 Modes of Operation
In addition to the above, upon waking up from stop2, SPMSC2[PPDF] is set. This flag is used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to SPMSC2[PPDACK].
Wakeup from stop2 can be initiated with an RTC interrupt. Unlike most other modules on the chip, the RTC is not reset as a result of exiting stop2. This implies that the RTC interrupt is asserted (although masked) upon exit from stop2.
To maintain I/O states for pins configured as general-purpose I/O before entering stop2, restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, the pins switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, reconfigure the peripheral module that interfaces to the pin before writing to PPDACK. If the peripheral module is not enabled before writing to PPDACK, the pins are controlled by their associated port control registers when the I/O latches are opened.
3.8.1.1 Low-Range Oscillator Considerations for Stop2
If using a low-range oscillator during stop2, reconfigure the ICSC2 register before PPDACK is written. The low-range oscillator (ICSC2[RANGE] = 0) can operate in stop2 as the clock source for the RTC module. If the low-range oscillator is active when entering stop2, it remains active in stop2 regardless of the value of ICSC2[EREFSTEN]. T o disable the oscillator in stop2, switch the ICS into FBI or FEI mode before executing the STOP instruction.

3.8.2 Stop3 Mode

Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. The on-chip regulator is placed in standby state.
Stop3 can be exited by asserting RESET or by an interrupt from one of the following sources: the RTC, ADC, ACMP, IRQ, SCI, or KBI.
If stop3 is exited by the RESET
pin, the MCU is reset and operation resumes after taking the reset vector .
Exit by one of the internal interrupt sources results in the MCU taking the appropriate interrupt vector.

3.8.3 Stop4: Low Voltage Detect or BDM Enabled in Stop Mode

Stop4 is differentiated from stop2 and stop3 in that the on-chip regulator is fully engaged. Entry into halt mode from run mode is enabled if the XCSR[ENBDM] bit is set. This register is described
in Chapter 18, “Version 1 ColdFire Debug (CF1_DEBUG)”. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible. If you attempt to enter stop2 or stop3 with ENBDM set, the MCU enters stop4 instead (see Table 3-1 for details).
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Chapter 3 Modes of Operation
Stop4 is also entered if SPMSC1[LVDE, LVDSE] are set, enabling low voltage detect when the STOP instruction is executed. The LVD may only be used when the on-chip regulator is in full regulation mode. Thus, stop3 and stop2 modes are not compatible with use of the LVD.
The LVD system is capable of generating an interrupt or a reset when the supply voltage drops below the LVD voltage.
Stop4 can be exited by asserting RESET or by an interrupt from one of the following sources: the RTC, LVD, LVW, ADC, ACMPx, IRQ, SCI or the KBI.

3.9 On-Chip Peripheral Modules in Stop and Low-Power Modes

When the MCU enters any stop mode (wait not included), system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to
Section 3.8.1, “Stop2 Mode,” and Section 3.8.2, “Stop3 Mode,” for specific information on system
behavior in stop modes. When the MCU enters LPwait or LPrun modes, system clocks to the internal peripheral modules continue
based on the settings of the clock gating control registers (SCGC1 and SCGC2).
Table 3-3 defines terms used in Table 3-4 to describe operation of components on the chip in the various
low-power modes.
Table 3-3. Abbreviations used in Tab l e 3- 4
Voltage Regulator Clocked
Full Regulation FullOn FullNoClk
Soft Regulation SoftOn
Off N/A Off
1
Subject to module enables and settings of System Clock Gating Control Registers 1 and 2 (SCGC1 and SCGC2).
2
This ADC-specific mode defines the case where the device is fully regulated and the normal peripheral clock is stopped. In this case, the ADC can run using its internally generated asynchronous ADACK clock.
3
Analog modules must be in their low-power mode when the device is operated in this state.
4
This ADC-specific mode defines the case where the device is in soft regulation and the normal peripheral clock is stopped. In this case, the ADC can only be run using its low-power mode and internally generated asynchronous ADACK clock.
1
3
Not Clocked
FullADACK
SoftNoClk
Disabled
SoftADACK
2
4
Table 3-4. Low-Power Mode Behavior
Mode
Peripheral
Stop2 Stop3 Stop4 LPwait Wait LPrun
CF1_CORE Off SoftNoClk FullNoClk SoftNoClk FullNoClk SoftOn
RAM SoftNoClk SoftNoClk FullNoClk SoftNoClk FullNoClk SoftOn
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Chapter 3 Modes of Operation
Table 3-4. Low-Power Mode Behavior (continued)
Mode
Peripheral
Stop2 Stop3 Stop4 LPwait Wait LPrun
Flash Off SoftNoClk FullNoClk SoftNoClk FullNoClk SoftOn
Port I/O Registers Off SoftNoClk FullNoClk SoftOn FullOn SoftOn
1,2
ADC
Off SoftADACK
(Wake Up)
FULLADACK
(Wake Up)
SoftOn FullOn SoftOn
ACMPx
Off SoftNoClk
(Wake Up)
FullNoClk
(Wake Up)
SoftOn FullOn SoftOn
BDC Off SoftOn On SoftOn FullOn SoftOn
COP Off SoftNoClk FullNoClk SoftOn FullOn SoftOn
Crystal Oscillator RANGE=0
HGO=0
ICS Off Stop or FBELP
RANGE=0
HGO=0
All Modes RANGE=0
3
Stop or any
All Modes RANGE=0
HGO=0
FBELP Any mode FBELP
mode
IICx Off SoftNoClk FullNoClk SoftOn FullOn SoftOn
IRQ
Off (Wake Up via POR)
4
KBIx Off SoftNoClk
LV D/ LV W Off
SoftNoClk
(Wake Up)
FullNoClk
(Wake Up)
FullNoClk
(Wake Up)
(Wake Up)
Disabled On
SoftOn FullOn SoftOn
SoftOn FullOn SoftOn
Disabled FullOn Disabled
(Wake Up)
RTC Soft
Regulation,
LPOCLK if
enabled
(Wake Up
via POR)
SoftOn
(Wake Up)
Full
Regulation
LPOCLK,
ICSERCLK or
ICSIRCLK
only
SoftOn FullOn SoftOn
(Wake Up)
HGO=0
SCIx Off SoftNoClk FullNoClk SoftOn FullOn SoftOn
SPIx Off SoftNoClk FullNoClk SoftOn FullOn SoftOn
TPMx Off SoftNoClk FullNoClk SoftOn FullOn SoftOn
Voltage Regulator / PMC
Parital
Shutdown.
1 kHz osc if
Soft Regulation.
1 kHz osc if
enabled
Full
Regulation
1kHz osc on
SoftOn
1 kHz osc on
FullOn
1 kHz osc on
SoftOn
1 kHz osc on
enabled
LPI/O Pins States Held SoftNoClk FullNoClk SoftOn FullOn SoftOn
1
LP mode for the ADC is invoked by setting ADLPC=1. ADACK is selected via the ADCCFG[ADICLK] field in the ADC. See
Chapter 11, “Analog-to-Digital Converter (S08ADC12V1),” for details.
2
LVD must be enabled to run in stop if converting the bandgap channel.
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Chapter 3 Modes of Operation
3
FBELP refers to the ICS FLL bypassed external low-power state. See Chapter 12, “Internal Clock Source (S08ICSV3),” for more details.
4
The PTA5/IRQ/TPM1CLK/RESET pin also has a direct connection to the on-chip regulator wakeup input. Asserting this pin low while in stop2 triggers the PMC to wakeup. As a result, the device undergoes a power-on-reset sequence.
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Chapter 4
0x(00)02_0000
0x(00)00_0000
0x(00)01_FFFF
CPU Address
0x(00)7F_FFFF
0x(00)80_0000
0x(00)80_1FFF
0x(00)80_2000
0x(00)BF_FFFF
0x(FF)FF_8000
0x(FF)FF_FFFF
MCF51QE128
Slave
0x(00)01_0000
Peripherals
64 Kbytes
Flash
0x(00)00_0000
0x(00)00_FFFF
CPU Address
0x(00)7F_FFFF
0x(00)80_0000
Unimplemented
0x(00)BF_FFFF
0x(FF)FF_8000
0x(FF)FF_FFFF
MCF51QE64
0x(00)C0_0000
0x(00)C0_000F
ColdFire
Rapid GPIO
0x(00)C0_0000
0x(00)C0_000F
0x(00)C0_0010
0x(FF)FF_7FFF
0x(00)C0_0010
0x(FF)FF_7FFF
Unimplemented
Slave
RAM
8 Kbytes
Peripherals
128 Kbytes
Flash
Unimplemented
Unimplemented
ColdFire
Rapid GPIO
Unimplemented
Slave
RAM
8 Kbytes
0x(00)00_8000
Peripherals
32 Kbytes
Flash
0x(00)00_0000
0x(00)00_7FFF
CPU Address
0x(00)7F_FFFF
0x(00)80_0000
0x(00)80_1FFF
Unimplemented
0x(00)80_2000
0x(00)BF_FFFF
Unimplemented
0x(FF)FF_8000
0x(FF)FF_FFFF
MCF51QE32
ColdFire
Rapid GPIO
0x(00)C0_0000
0x(00)C0_000F
0x(00)C0_0010
0x(FF)FF_7FFF
Unimplemented
0x(00)80_1FFF
0x(00)80_2000
RAM
8 Kbytes
Unimplemented
Memory

4.1 MCF51QE128/64/32 Memory Map

As shown in Figure 4-1, on-chip memory in the MCF51QE128/64/32 series of MCUs consists of RAM and flash program memory for nonvolatile code and data storage, plus I/O and control/status registers.
NOTE
Version 1 ColdFire devices contain 24-bit internal address buses, while previous ColdFire cores have 32-bit internal address buses. Because there may be some resources that use a 32-bit address, this chapter shows 24-bit and 32-bit addresses by indicating the extra upper byte in parentheses.
Freescale Semiconductor 57
Figure 4-1. MCF51QE128/64/32 Memory Maps
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Chapter 4 Memory
Regions within the memory map are subject to restrictions with regard to the types of allowable accesses. These are outlined in Table 4-1. Non-supported access types terminate the bus cycle with an error and would typically generate a system reset in response to the error termination.
Table 4-1. CPU Access Type Allowed by Region
Read Write
Base Address Region
Byte Word Long Byte Word Long
0x(00)00_0000
0x(00)80_0000
0x(00)C0_0000
0x(FF)FF_8000
Flash
RAM
Rapid GPIO
Peripherals
xxx——x
xxxxxx
xxxxxx
xx—xx—
Consistent with past ColdFire devices, flash configuration data is located at 0x400. The slave peripherals section of the memory map is further broken into the following sub-sections:
0x(FF)FF_8000 – 0x(FF)FF_807F Direct-page peripheral regs 0x(FF)FF_9800 – 0x(FF)FF_98FF High-page peripheral regs 0x(FF)FF_FFC0 – 0x(FF)FF_FFFC Interrupt controller
The section of memory at 0x(00)C0_0000 is assigned for use by the ColdFire Rapid GPIO module. See
Section 4.2.2, “ColdFire Rapid GPIO Memory Map,” for the rapid GPIO memory map and Section 6.4, “V1 ColdFire Rapid GPIO Functionality,” for further details on the module.
The MCF51QE128/64/32 devices utilize an 8-bit peripheral bus. The bus bridge from the ColdFire system bus to the peripheral bus is capable of serializing 16-bit accesses into two 8-bit accesses. This can be used to speed access to properly aligned peripheral registers. Note, not all peripheral registers are aligned to take advantage of this feature.
CPU accesses to those parts of the memory map marked as unimplemented in Figure 4-1 result in an illegal address reset if CPUCR[ARD] is cleared or an address error exception if CPUCR[ARD] is set.
The lower 32K of flash memory and slave peripherals sections of the memory map are most efficiently accessed using the ColdFire absolute short addressing mode. RAM is most efficiently accessed using the A5-relative addressing mode (address register indirect with displacement mode).

4.2 Register Addresses and Bit Assignments

Peripheral registers in the MCF51QE128/64/32 are divided into two groups:
• Direct-page registers are located at 0x(FF)FF_8000 in the memory map.
• High-page registers are located at 0x(FF)FF_9800 in the memory map. There is no functional advantage to locating peripherals in the direct page versus the high page
peripheral space for the MCF51QE128/64/32. Both sets of registers may be efficiently accessed using the ColdFire absolute short addressing mode. The areas are differentiated to maintain documentation compatibility with the MC9S08QE128/64/32, where there are significant performance issues.
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Chapter 4 Memory
Byte 0x(00)00_0000 Byte 0x(00)00_0001 Byte 0x(00)00_0002 Byte 0x(00)00_0003
Word 0x(00)00_0000 Word 0x(00)00_0002
Longword 0x(00)00_0000
31 24 23 16 15 8 7 0
Byte 0x(00)00_0004 Byte 0x(00)00_0005 Byte 0x(00)00_0006 Byte 0x(00)00_0007
Word 0x(00)00_0004 Word 0x(00)00_0006
Longword 0x(00)00_0004
Byte 0x(FF)FF_FFFC Byte 0x(FF)FF_FFFD Byte 0x(FF)FF_FFFE Byte 0x(FF)FF_FFFF
Word 0x(FF)FF_FFFC Word 0x(FF)FF_FFFE
Longword 0x(FF)FF_FFFC
•
•
•
NOTE
Peripheral register locations for MCF51QE128/64/32 are shifted 0x(FF)FF_8000 compared with the MC9S08QE128/64/32 devices.
• The ColdFire interrupt controller module is mapped in the peripheral space and occupies a 64-byte space at the upper end of memory. Accordingly, its address decode is defined as 0x(FF)FF_FFC0–0x(FF)FF_FFFF. This 64-byte space includes the program-visible registers as well as the space used for interrupt acknowledge (IACK) cycles.
• There is a nonvolatile register area consisting of a 16-byte block locted in flash memory at 0x(00)00_0400–0x(00)00_040F. Nonvolatile register locations include:
— NVPROT and NVOPT are loaded into working registers at reset — An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are flash memory , they must be erased and programmed like other flash memory locations.
Table 4-2 is a summary of all user-accessible direct-page registers and control bits.
The register names in column two in Table 4-2, Table 4-3, Table 4-6, and Table 4-7 are shown in bold to set them apart from the bit names to the right. Cells not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. When writing to these bits, write a 0 unless otherwise specified.
Recall that ColdFire uses a big-endian, byte-addressable memory architecture. The most significant byte of each address is the lowest numbered as shown in Figure 4-2. Multi-byte operands (16-bit words and 32-bit longwords) are referenced using an address pointing to the most significant (first) byte.
Figure 4-2. ColdFire Memory Organization
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Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 1 of 4)
Address
Register
Name
Bit 7654321Bit 0
0x(FF)FF_8000 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
0x(FF)FF_8001 PTADD PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
0x(FF)FF_8002 PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
0x(FF)FF_8003 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
0x(FF)FF_8004 PTCD PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
0x(FF)FF_8005 PTCDD PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
0x(FF)FF_8006 PTDD PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
0x(FF)FF_8007 PTDDD PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
0x(FF)FF_8008 PTED PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
0x(FF)FF_8009 PTEDD PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
0x(FF)FF_800A PTFD PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
0x(FF)FF_800B PTFDD PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
0x(FF)FF_800C KBI1SC
0 0 0 0 KBF KBACK KBIE KBIMOD
0x(FF)FF_800D KBI1PE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
0x(FF)FF_800E KBI1ES KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0
0x(FF)FF_800F IRQSC 0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD
0x(FF)FF_8010 ADSC1 COCO AIEN ADCO ADCH
0x(FF)FF_8011 ADSC2 ADACT ADTRG ACFE ACFGT 0 0 0 0
0x(FF)FF_8012 ADRH 0 0 0 0 0 0 ADR9 ADR8
0x(FF)FF_8013 ADRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0x(FF)FF_8014 ADCVH 0 0 0 0 0 0 ADCV9 ADCV8
0x(FF)FF_8015 ADCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
0x(FF)FF_8016 ADCFG ADLPC ADIV ADLSMP MODE ADICLK
0x(FF)FF_8017 APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
0x(FF)FF_8018 APCTL2 ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8
0x(FF)FF_8019 APCTL3 ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16
0x(FF)FF_801A ACMP1SC ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0
0x(FF)FF_801B ACMP2SC ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0
0x(FF)FF_801C PTGD PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
0x(FF)FF_801D PTGDD PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
0x(FF)FF_801E PTHD PTHD7 PTHD6 PTHD5 PTHD4 PTHD3 PTHD2 PTHD1 PTHD0
0x(FF)FF_801F PTHDD PTHDD7 PTHDD6 PTHDD5 PTHDD4 PTHDD3 PTHDD2 PTHDD1 PTHDD0
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Table 4-2. Direct-Page Register Summary (Sheet 2 of 4)
Chapter 4 Memory
Address
Register
Name
Bit 7654321Bit 0
0x(FF)FF_8020 SCI1BDH LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8
0x(FF)FF_8021 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
0x(FF)FF_8022 SCI1C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
0x(FF)FF_8023 SCI1C2 TIE TCIE RIE ILIE TE RE RWU SBK
0x(FF)FF_8024 SCI1S1 TDRE TC RDRF IDLE OR NF FE PF
0x(FF)FF_8025 SCI1S2 LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF
0x(FF)FF_8026 SCI1C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE
0x(FF)FF_8027 SCI1D Bit 7654321Bit 0
0x(FF)FF_8028 SPI1C1 SPI1E SP1E SP1TIE MSTR CPOL CPHA SSOE LSBFE
0x(FF)FF_8029 SPI1C2 0 0 0 MODFEN BIDIROE 0 SPI1SWAI SP1C0
0x(FF)FF_802A SPI1BR 0 SP1PR2 SP1PR1 SP1PR0 0 SP1R2 SP1R1 SP1R0
0x(FF)FF_802B SPI1S SP1RF 0 SP1TEF MODF 0 0 0 0
0x(FF)FF_802C Reserved 0 0 0 0 0 0 0 0
0x(FF)FF_802D SPI1D Bit 7654321Bit 0
0x(FF)FF_802E PTJD PTJD7 PTJD6 PTJD5 PTJD4 PTJD3 PTJD2 PTJD1 PTJD0
0x(FF)FF_802F PTJDD PTJDD7 PTJDD6 PTJDD5 PTJDD4 PTJDD3 PTJDD2 PTJDD1 PTJDD0
0x(FF)FF_8030 IIC1A AD7 AD6 AD5 AD4 AD3 AD2 AD1 0
0x(FF)FF_8031 IIC1F MULT TAP2 TAP1
0x(FF)FF_8032 IIC1C1 IICEN IICIE MST TX TXAK RSTA 0 0
0x(FF)FF_8033 IIC1S TCF IAAS BUSY ARBL 0SRWIICIFRXAK
0x(FF)FF_8034 IIC1D DATA
0x(FF)FF_8035 IIC1C2 GCAEN ADEXT 0 0 0 AD10 AD9 AD8
0x(FF)FF_8036 Reserved
— — — — — — — —
0x(FF)FF_8037 ICSTEST RESERVED FOR FACTORY USE
0x(FF)FF_8038 ICSC1 CLKS RDIV IREFS IRCLKEN IREFSTEN
0x(FF)FF_8039 ICSC2 BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN
0x(FF)FF_803A ICSTRM TRIM
0x(FF)FF_803B ICSSC DFR DMX32 IREFST CLKST OSCINIT FTRIM
0x(FF)FF_803C KBI2SC 0 0 0 0 KBF KBACK KBIE KBIMOD
0x(FF)FF_803D KBI2PE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
0x(FF)FF_803E KBI2ES KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0
0x(FF)FF_803F Reserved — — — — — — — —
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Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 3 of 4)
Address
Register
Name
Bit 7654321Bit 0
0x(FF)FF_8040 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x(FF)FF_8041 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8042 TPM1CNTL Bit 7654321Bit 0
0x(FF)FF_8043 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8044 TPM1MODL Bit 7654321Bit 0
0x(FF)FF_8045 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x(FF)FF_8046 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8047 TPM1C0VL Bit 7654321Bit 0
0x(FF)FF_8048 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x(FF)FF_8049 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_804A TPM1C1VL Bit 7654321Bit 0
0x(FF)FF_804B TPM1C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0
0x(FF)FF_804C TPM1C2VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_804D TPM1C2VL Bit 7654321Bit 0
0x(FF)FF_804E-
0x(FF)FF_804F
Reserved
— — — — — — — —
0x(FF)FF_8050 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x(FF)FF_8051 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8052 TPM2CNTL Bit 7654321Bit 0
0x(FF)FF_8053 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8054 TPM2MODL Bit 7654321Bit 0
0x(FF)FF_8055 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A
0 0
0x(FF)FF_8056 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8057 TPM2C0VL Bit 7654321Bit 0
0x(FF)FF_8058 TPM2C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A
0 0
0x(FF)FF_8059 TPM2C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_805A TPM2C1VL Bit 7654321Bit 0
0x(FF)FF_805B TPM2C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A
0 0
0x(FF)FF_805C TPM2C2VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_805D TPM2C2VL Bit 7654321Bit 0
0x(FF)FF_805E-
0x(FF)FF_805F
Reserved
— — — — — — — —
0x(FF)FF_8060 TPM3SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
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Table 4-2. Direct-Page Register Summary (Sheet 4 of 4)
Chapter 4 Memory
Address
0x(FF)FF_8061 TPM3CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8062 TPM3CNTL Bit 7654321Bit 0
0x(FF)FF_8063 TPM3MODH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8064 TPM3MODL Bit 7654321Bit 0
0x(FF)FF_8065 TPM3C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x(FF)FF_8066 TPM3C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8067 TPM3C0VL Bit 7654321Bit 0
0x(FF)FF_8068 TPM3C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x(FF)FF_8069 TPM3C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_806A TPM3C1VL Bit 7654321Bit 0
0x(FF)FF_806B TPM3C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0
0x(FF)FF_806C TPM3C2VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_806D TPM3C2VL Bit 7654321Bit 0
0x(FF)FF_806E TPM3C3SC CH3F CH3IE MS3B MS3A ELS3B ELS3A 0 0
0x(FF)FF_806F TPM3C3VH Bit 15 14 13 12 11 10 9 Bit 8
Register
Name
Bit 7654321Bit 0
0x(FF)FF_8070 TPM3C3VL Bit 7654321Bit 0
0x(FF)FF_8071 TPM3C4SC CH4F CH4IE MS4B MS4A ELS4B ELS4A 0 0
0x(FF)FF_8072 TPM3C4VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8073 TPM3C4VL Bit 7654321Bit 0
0x(FF)FF_8074 TPM3C5SC CH5F CH5IE MS5B MS5A ELS5B ELS5A 0 0
0x(FF)FF_8075 TPM3C5VH Bit 15 14 13 12 11 10 9 Bit 8
0x(FF)FF_8076 TPM3C5VL Bit 7654321Bit 0
0x(FF)FF_8077-
0x(FF)FF_807F
Reserved
— — — — — — — —
Table 4-3. High-Page Register Summary (Sheet 1 of 5)
Address
0x(FF)FF_9800 SRS POR PIN COP ILOP ILAD
0x(FF)FF_9801 Reserved 0 0 0 0 0 0 0 0
0x(FF)FF_9802 SOPT1 COPE COPT STOPE WAITE
0x(FF)FF_9803 SOPT2 COPCLKS 0 0 0 SPI1PS ACIC2 IICPS ACIC1
Register
Name
Bit 7654321Bit 0
0LVD 0
0 RSTOPE BKGDPE RSTPE
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Table 4-3. High-Page Register Summary (Sheet 2 of 5)
Address
0x(FF)FF_9804
0x(FF)FF_9805
0x(FF)FF_9806 SDIDH
Register
Name
SIMCTSC
(Reserved)
SIMCO
(Reserved)
Bit 7654321Bit 0
TMODE TEST TRSTPE TC
0 0 0 0 0CSSPCOE0
0 0 0 0 ID[11:8]
0x(FF)FF_9807 SDIDL ID[7:0]
0x(FF)FF_9808 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0BGBE
0x(FF)FF_9809 SPMSC2 LPR LPRS LPWUI 0 PPDF PPDACK PPDE PPDC
0x(FF)FF_980A Reserved — — — — — — — —
0x(FF)FF_980B SPMSC3 LV WF LV WAC K LV DV LV WV LV WI E 0 0 0
0x(FF)FF_980C-
0x(FF)FF_980D
Reserved
— — — — — — — —
0x(FF)FF_980E SCGC1 TPM3 TPM2 TPM1 ADC IIC2 IIC1 SCI2 SCI1
0x(FF)FF_980F SCGC2
0x(FF)FF_9810-
0x(FF)FF_981F
Reserved
1 FLS IRQ KBIx ACMPx RTC SPI2 SPI1
— — — — — — — —
0x(FF)FF_9820 FCDIV FDIVLD PRDIV8 FDIV
0x(FF)FF_9821 FOPT KEYEN
0x(FF)FF_9822
0x(FF)FF_9823 FCNFG
FRSV0
(Reserved)
0 0 0 0 0 0 0 0
0 0 KEYACC 0 0 0 0 0
0 0 0 0SEC
0x(FF)FF_9824 FPROT FPS FPOPEN
0x(FF)FF_9825 FSTAT FCBEF FCCF FPVIOL FACCERR 0FBLANK0 0
0x(FF)FF_9826 FCMD
0x(FF)FF_9827
0x(FF)FF_9828
0x(FF)FF_9829
0x(FF)FF_982A
0x(FF)FF_982B
0x(FF)FF_982C
FRSV1
(Reserved)
FADDRHI
(Reserved)
FADDRLO
(Reserved)
FRSV2
(Reserved)
FRSV3
(Reserved)
FDATAHI1
(Reserved)
0FCMD
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
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Table 4-3. High-Page Register Summary (Sheet 3 of 5)
Address
0x(FF)FF_982D
0x(FF)FF_982E
0x(FF)FF_982F
0x(FF)FF_9830 RTCSC RTIF RTCLKS RTIE RTCPS
0x(FF)FF_9831 RTCCNT RTCCNT
0x(FF)FF_9832 RTCMOD RTCMOD
0x(FF)FF_9833-
0x(FF)FF_9837
0x(FF)FF_9838 SPI2C1 SPI2E SP2E SP2TIE MSTR CPOL CPHA SSOE LSBFE
0x(FF)FF_9839 SPI2C2
0x(FF)FF_983A SPI2BR 0 SP2PR2 SP2PR1 SP2PR0 0 SP2R2 SP2R1 SP2R0
0x(FF)FF_983B SPI2S SP2RF 0SP2TEFMODF 0 0 0 0
0x(FF)FF_983C Reserved 0 0 0 0 0 0 0 0
Register
Name
FDATALO1 (Reserved)
FDATAHI0
(Reserved)
FDATALO0 (Reserved)
Reserved
Bit 7654321Bit 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
— — — — — — — —
0 0 0 MODFEN BIDIROE 0 SPI2SWAI SP2C0
0x(FF)FF_983D SPI2D Bit 7654321Bit 0
0x(FF)FF_983E-
0x(FF)FF_983F
0x(FF)FF_9840 PTAPE PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
0x(FF)FF_9841 PTASE PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
0x(FF)FF_9842 PTADS PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
0x(FF)FF_9843 Reserved
0x(FF)FF_9844 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
0x(FF)FF_9845 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
0x(FF)FF_9846 PTBDS PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
0x(FF)FF_9847 Reserved — — — — — — — —
0x(FF)FF_9848 PTCPE PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
0x(FF)FF_9849 PTCSE PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
0x(FF)FF_984A PTCDS PTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0
0x(FF)FF_984B Reserved
Reserved
— — — — — — — —
— — — — — — — —
— — — — — — — —
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Table 4-3. High-Page Register Summary (Sheet 4 of 5)
Address
0x(FF)FF_984C PTDPE PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
0x(FF)FF_984D PTDSE PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
0x(FF)FF_984E PTDDS PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
0x(FF)FF_984F Reserved — — — — — — — —
0x(FF)FF_9850 PTEPE PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
0x(FF)FF_9851 PTESE PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
0x(FF)FF_9852 PTEDS PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0
0x(FF)FF_9853 Reserved — — — — — — — —
0x(FF)FF_9854 PTFPE PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
0x(FF)FF_9855 PTFSE PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
0x(FF)FF_9856 PTFDS PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0
0x(FF)FF_9857 Reserved — — — — — — — —
0x(FF)FF_9858 PTGPE PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
0x(FF)FF_9859 PTGSE PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
0x(FF)FF_985A PTGDS PTGDS7 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0
Register
Name
Bit 7654321Bit 0
0x(FF)FF_985B Reserved — — — — — — — —
0x(FF)FF_985C PTHPE PTHPE7 PTHPE6 PTHPE5 PTHPE4 PTHPE3 PTHPE2 PTHPE1 PTHPE0
0x(FF)FF_985D PTHSE PTHSE7 PTHSE6 PTHSE5 PTHSE4 PTHSE3 PTHSE2 PTHSE1 PTHSE0
0x(FF)FF_985E PTHDS PTHDS7 PTHDS6 PTHDS5 PTHDS4 PTHDS3 PTHDS2 PTHDS1 PTHDS0
0x(FF)FF_985F Reserved — — — — — — — —
0x(FF)FF_9860 PTJPE PTJPE7 PTJPE6 PTJPE5 PTJPE4 PTJPE3 PTJPE2 PTJPE1 PTJPE0
0x(FF)FF_9861 PTJSE PTJSE7 PTJSE6 PTJSE5 PTJSE4 PTJSE3 PTJSE2 PTJSE1 PTJSE0
0x(FF)FF_9862 PTJDS PTJDS7 PTJDS6 PTJDS5 PTJDS4 PTJDS3 PTJDS2 PTJDS1 PTJDS0
0x(FF)FF_9863-
0x(FF)FF_9867
0x(FF)FF_9868 IIC2A AD7 AD6 AD5 AD4 AD3 AD2 AD1
0x(FF)FF_9869 IIC2F MULT TAP2
0x(FF)FF_986A IIC2C1 IICEN IICIE MST TX TXAK RSTA 0 0
0x(FF)FF_986B IIC2S TCF IAAS BUSY ARBL 0 SRW IICIF RXAK
0x(FF)FF_986C IIC2D DATA
0x(FF)FF_986D IIC2C2 GCAEN ADEXT 0 0 0 AD10 AD9 AD8
0x(FF)FF_986E-
0x(FF)FF_986F
Reserved
Reserved
— — — — — — — —
0
TAP1
— — — — — — — —
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Table 4-3. High-Page Register Summary (Sheet 5 of 5)
Chapter 4 Memory
Address
0x(FF)FF_9870 SCI2BDH LBKDIE RXEDGIE 0 SBR[12:8]
0x(FF)FF_9871 SCI2BDL SBR[7:0]
0x(FF)FF_9872 SCI2C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
0x(FF)FF_9873 SCI2C2 TIE TCIE RIE ILIE TE RE RWU SBK
0x(FF)FF_9874 SCI2S1 TDRE TC RDRF IDLE OR NF FE PF
0x(FF)FF_9875 SCI2S2 LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF
0x(FF)FF_9876 SCI2C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE
0x(FF)FF_9877 SCI2D Bit 7654321Bit 0
0x(FF)FF_9878 PTCSET PTCSET7 PTCSET6 PTCSET5 PTCSET4 PTCSET3 PTCSET2 PTCSET1 PTCSET0
0x(FF)FF_9879 PTESET PTESET7 PTESET6 PTESET5 PTESET4 PTESET3 PTESET2 PTESET1 PTESET0
0x(FF)FF_987A PTCCLR PTCCLR7 PTCCLR6 PTCCLR5 PTCCLR4 PTCCLR3 PTCCLR2 PTCCLR1 PTCCLR0
0x(FF)FF_987B PTECLR PTECLR7 PTECLR6 PTECLR5 PTECLR4 PTECLR3 PTECLR2 PTECLR1 PTECLR0
0x(FF)FF_987C PTCTOG PTCTOG7 PTCTOG6 PTCTOG5 PTCTOG4 PTCTOG3 PTCTOG2 PTCTOG1 PTCTOG0
0x(FF)FF_987D PTETOG PTETOG7 PTETOG6 PTETOG5 PTETOG4 PTETOG3 PTETOG2 PTETOG1 PTETOG0
0x(FF)FF_987E-
0x(FF)FF_987F
Register
Name
Reserved
Bit 7654321Bit 0
— — — — — — — —

4.2.1 Flash Module Reserved Memory Locations

Several reserved flash memory locations, shown in Table 4-4, are used for storing values used by corresponding peripheral registers. These registers include an 8-byte backdoor key that can be used to gain access to secure memory resources. During reset events, the contents of the flash protection byte (NVPROT) and flash nonvolatile byte (NVOPT) in the reserved flash memory are transferred into the corresponding FPROT and FOPT registers in the high-page register area to control security and block protection options.
Table 4-4. Reserved Flash Memory Addresses
Address
0x(00)00_03FC
0x(00)00_0400
0x(00)00_0404
1
MSB
(0x0) (0x1) (0x2)
Reserved
FTRIM
(bit 0)
Backdoor comparison key bytes 0–3
byte0 byte1 byte2 byte3
Backdoor comparison key bytes 4–7
byte4 byte5 byte6 byte7
LSB (0x3)
TRIM
2
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Address
Table 4-4. Reserved Flash Memory Addresses
1
MSB
(0x0) (0x1) (0x2)
LSB (0x3)
2
0x(00)00_0408
0x(00)00_040C
1
MSB = most significant byte
2
LSB = least significant byte
Reserved NVPROT Reserved NVOPT
Reserved
Table 4-5. Reserved Flash Memory Addresses
Address Register76543210
0x(00)00_03FC–
0x(00)00_03FD
0x(00)00_03FE
0x(00)00_03FF
Reserved
Storage of
FTRIM
Storage of
ICSTRM
0x(00)00_0400–
0x(00)00_0407
0x(00)00_0408–
0x(00)00_040C
Reserved
0x(00)00_040D NVPROT
— — — — — — — —
0 0 0 0 0 0 0 FTRIM
TRIM
8-Byte Backdoor Comparison Key
— — — — — — — —
FPS FPOPEN
0x(00)00_040E
0x(00)00_040F
Reserved — — — — — — — —
NVOPT KEYEN 0 0 0 0 SEC
The factory trim values are stored in the flash information row (IFR)1 and are automatically loaded into the ICSTRM and ICSSC registers after any reset. The oscillator trim values stored in TRIM and FTRIM can be reprogrammed by third party programmers and must be copied into the corresponding ICS registers (ICSTRM and ICSSC) by user code to override the factory trim.
NOTE
When the MCU is in active BDM, the trim value in the IFR is not loaded. Instead, the ICSTRM register resets to 0x80 and ICSSC[FTRIM] resets to zero.
Provided the key enable (KEYEN) bit is set, the 8-byte comparison key can be used to temporarily disengage memory security . This key mechanism can be accessed only through user code running in secure memory (A security key cannot be entered directly through background debug commands). This security key can be disabled completely by clearing the KEYEN bit. If the security key is disabled, the only way
1. IFR — Nonvolatile information memory that can only be accessed during production test. During production test, system initialization, configuration, and test information is stored in the IFR. This information cannot be read or modified in normal user or background debug modes.
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to disengage security is by mass-erasing the flash (normally through the background debug interface) and verifying the flash is blank.

4.2.2 ColdFire Rapid GPIO Memory Map

The rapid GPIO module is mapped into a 16-byte area starting at location 0x(00)C0_0000. Its memory map is shown below in Table 4-6.
Table 4-6. V1 ColdFire Rapid GPIO Memory Map
Address
0x(00)C0_0000
0x(00)C0_0001 76543210
0x(00)C0_0002
0x(00)C0_0003 76543210
0x(00)C0_0004
0x(00)C0_0005 76543210
0x(00)C0_0006
0x(00)C0_0007 76543210
0x(00)C0_0008
0x(00)C0_0009 — — — — — — — —
0x(00)C0_000A
0x(00)C0_000B 76543210
0x(00)C0_000C
0x(00)C0_000D
0x(00)C0_000E
0x(00)C0_000F 76543210
Register
Name
RGPIO_DIR
RGPIO_DATA
RGPIO_ENB
RGPIO_CLR
Reserved
RGPIO_SET
Reserved
RGPIO_TOG
Bit 7654321Bit 0
15 14 13 12 11 10 9 8
15 14 13 12 11 10 9 8
15 14 13 12 11 10 9 8
15 14 13 12 11 10 9 8
— — — — — — — —
15 14 13 12 11 10 9 8
— — — — — — — —
— — — — — — — —
15 14 13 12 11 10 9 8

4.2.3 ColdFire Interrupt Controller Memory Map

The V1 ColdFire interrupt controller (CF1_INTC) register map is sparsely-populated, but retains compatibility with earlier ColdFire interrupt controller definitions. The CF1_INTC occupies the upper 64 bytes of the device memory map and all memory locations are accessed as 8-bit (byte) operands.
Table 4-7. V1 ColdFire Interrupt Controller Memory Map
Address Register Name msb Bit Number lsb
0x(FF)FF_FFC0–
0x(FF)FF_FFD2
0x(FF)FF_FFD3 INTC_FRC
0x(FF)FF_FFD4–
0x(FF)FF_FFD7
0x(FF)FF_FFD8 INTC_PL6P7
0x(FF)FF_FFD9 INTC_PL6P6
0x(FF)FF_FFDA Reserved
0x(FF)FF_FFDB INTC_WCR ENB
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Reserved
Reserved
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— — — — — — — —
0 LVL1 LVL2 LVL3 LVL4 LVL5 LVL6 LVL7
— — — — — — — —
0 0 0REQN
0 0 0REQN
— — — — — — — —
0 0 0 0MASK
Chapter 4 Memory
Address Register Name msb Bit Number lsb
0x(FF)FF_FFDC–
0x(FF)FF_FFDD
0x(FF)FF_FFDE INTC_SFRC
0x(FF)FF_FFDF INTC_CFRC
0x(FF)FF_FFE0 INTC_SWIACK
0x(FF)FF_FFE1–
0x(FF)FF_FFE3
0x(FF)FF_FFE4 INTC_LVL1IACK
0x(FF)FF_FFE5–
0x(FF)FF_FFE7
0x(FF)FF_FFE8 INTC_LVL2IACK
0x(FF)FF_FFE9–
0x(FF)FF_FFEB
0x(FF)FF_FFEC INTC_LVL3IACK
0x(FF)FF_FFED–
0x(FF)FF_FFEF
0x(FF)FF_FFF0 INTC_LVL4IACK
0x(FF)FF_FFF1–
0x(FF)FF_FFF3
0x(FF)FF_FFF4 INTC_LVL5IACK
0x(FF)FF_FFF5–
0x(FF)FF_FFF7
0x(FF)FF_FFF8 INTC_LVL6IACK
0x(FF)FF_FFF9–
0x(FF)FF_FFFB
0x(FF)FF_FFFC INTC_LVL7IACK
0x(FF)FF_FFFD–
0x(FF)FF_FFFF
Table 4-7. V1 ColdFire Interrupt Controller Memory Map (continued)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
— — — — — — — —
0 0 SET
0 0CLR
0 VECN
— — — — — — — —
0 VECN
— — — — — — — —
0 VECN
— — — — — — — —
0 VECN
— — — — — — — —
0 VECN
— — — — — — — —
0 VECN
— — — — — — — —
0 VECN
— — — — — — — —
0 VECN
— — — — — — — —

4.3 RAM

The MCF51QE128/64/32 includes up to 8 Kbytes of static RAM. RAM is most efficiently accessed using the A5-relative addressing mode (address register indirect with displacement mode). Any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET,etc.).
At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention (V
RAM
).

4.4 Flash

The flash memory is intended primarily for program storage and read-only data. In-circuit programming allows the operating program to be loaded into the flash memory after final assembly of the application product. It is possible to program the entire array through the single-wire background debug interface. Because no special voltages are needed for flash erase and programming operations, in-application programming is also possible through other software-controlled communication paths.
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Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The flash module includes a memory controller that executes commands to modify flash memory contents.
Array read access time is one bus cycle for bytes, aligned words, and aligned longwords. Multiple accesses are needed for misaligned words and longword operands. For flash memory, an erased bit reads 1 and a programmed bit reads 0. It is not possible to read from a flash block while any command is executing on that specific flash block.
CAUTION
A flash block address must be in the erased state before being programmed. Cumulative programming of bits within a flash block address is not allowed except for status field updates required in EEPROM emulation applications.
Flash memory on MCF51QE128/64/32 must be programmed 32-bits at a time when the low-voltage detect flag (LVDF) in the system power management status and control 1 register (SPMSC1) is clear. If SPMSC1[LVDF] is set, the programming sequence must be modified such that odd and even bytes are written separately. The MCF51QE128/64/32 flash memory is organized as two 16-bit wide blocks interleaved to yield a 32-bit data path. When programming flash when LVDF is set, alternate bytes must be set to 0xFF as shown in Table 4-8. Failure to adhere to these guidelines may result in a partially programmed flash array.
Table 4-8. Lov-Voltage Programming Sequence Example
Addresses Desired Value Values Programmed
0x00 – 0x03 0x00 – 0x03
0x04 – 0x07 0x04 – 0x07
0x08 – 0x0B 0x08 – 0x0B
0x0C – 0x0F 0x0C – 0x0F

4.4.1 Features

Features of the flash memory include:
• Flash size — MCF51QE128: 131,072 bytes (128 sectors of 1024 bytes each) — MCF51QE64: 65,536 bytes (64 sectors of 1024 bytes each) — MCF51QE32: 32,768 bytes (32 sectors of 1024 bytes each)
• Automated program and erase algorithm
0x5555_AAAA
0xCCCC_CCCC
0x1234_5678
0x9ABC_DEF0
0x55FF_AAFF 0xFF55_FFAA
0xCCFF_CCFF 0xFFCC_FFCC
0x12FF_56FF 0xFF34_FF78
0x9AFF_DEFF
0xFFBC_FFF0
• Fast program and sector erase operation
• Burst program command for faster flash array program times
• Single power supply program and erase
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• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection (on any 2-Kbyte memory boundary)
• Security feature to prevent unauthorized access to on-chip memory and resources
• Auto power-down for low-frequency read accesses

4.4.2 Register Descriptions

The flash module contains a set of 16 control and status registers located between 0x(00)00_0000 and 0x(00)00_000F. Detailed descriptions of each register bit are provided in the following sections.
4.4.2.1 Flash Clock Divider Register (FCDIV)
The FCDIV register controls the length of timed events in program and erase algorithms executed by the flash memory controller. All bits in the FCDIV register are readable and writable with restrictions as determined by the value of FDIVLD when writing to the FCDIV register.
76543210
R
FDIVLD PRDIV8 FDIV
W
Reset00000000
Figure 4-3. Flash Clock Divider Register (FCDIV)
Table 4-9. FCDIV Field Descriptions
Field Description
7
FDIVLD
6
PRDIV8
5–0
FDIV
Clock Divider Load Control. When writing to the FCDIV register for the first time after a reset, the value of the FDIVLD bit written controls the future ability to write to the FCDIV register: 0 Writing a 0 to FDIVLD locks the FCDIV register contents; all future writes to FCDIV are ignored. 1 Writing a 1 to FDIVLD keeps the FCDIV register writable; next write to FCDIV is allowed. When reading the FCDIV register, the value of the FDIVLD bit read indicates the following: 0 FCDIV register has not been written to since the last reset. 1 FCDIV register has been written to since the last reset.
Enable Prescalar by 8
0 The bus clock is directly fed into the clock divider. 1 The bus clock is divided by 8 before feeding into the clock divider.
Clock Divider Bits. The combination of PRDIV8 and FDIV[5:0] must divide the bus clock down to a frequency of 150 kHz–200 kHz. The minimum divide ratio is 2 (PRDIV8=0, FDIV=0x01) and the maximum divide ratio is 512 (PRDIV8=1, FDIV=0x3F). Refer to Section 4.5.1.1, “Writing the FCDIV Register” for more information.
.
4.4.2.2 Flash Options Register (FOPT and NVOPT)
The FOP T register holds all bits associated with the security of the MCU and flash module. All bits in the FOPT register are readable but are not writable.
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The FOPT register is loaded from the flash configuration field (see Section 4.2.1) during the reset sequence, indicated by F in Figure 4-4.
The security feature in the flash module is described in Section 4.5.5, “Security”.
76543210
R KEYEN 0 0 0 0 SEC
W
ResetFF0000FF
Figure 4-4. Flash Options Register (FOPT)
Table 4-10. FOPT Field Descriptions
Field Description
7–6
KEYEN
5–2 Reserved, should be cleared.
1–0
SEC
Backdoor Key Security Enable Bits. The KEYEN[1:0] bits define the enabling of backdoor key access to the flash module. 00 Disabled 01 Disabled (Preferred KEYEN state to disable Backdoor Key Access) 10 Enabled 11 Disabled
Flash Security Bits. The SEC[1:0] bits define the security state of the MCU. If the flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to the unsecured state. 00 Unsecured 01 Unsecured 10 Secured 11 Unsecured
4.4.2.3 Flash Configuration Register (FCNFG)
The FCNFG register gates the security backdoor writes. KEYACC is readable and writable while all remaining bits read 0 and are not writable. KEYACC is only
writable if KEYEN is set to the enabled state (see Section 4.4.2.2, “Flash Options Register (FOPT and
NVOPT)”).
NOTE
Flash array reads are allowed while KEYACC is set.
76543210
R0 0
KEYACC
W
Reset00000000
00000
Figure 4-5. Flash Configuration Register (FCNFG)
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Chapter 4 Memory
Table 4-11. FCNFG Field Descriptions
Field Description
7–6 Reserved, should be cleared.
5
KEYACC
4–0 Reserved, should be cleared.
Enable Security Key Writing 0 Writes to the flash block are interpreted as the start of a command write sequence. 1 Writes to the flash block are interpreted as keys to open the backdoor.
4.4.2.4 Flash Protection Register (FPROT and NVPROT)
The FPROT register defines which flash sectors are protected against program or erase operations. FPROT bits are readable and writable as long as the size of the protected flash memory is being increased. Any write to FPROT that attempts to decrease the size of the protected flash memory is ignored.
During the reset sequence, the FPROT register is loaded from the flash protection byte in the flash configuration field (see Section 4.2.1), indicated by F in Table 4-6. To change the flash protection loaded during the reset sequence, the flash sector containing the flash configuration field must be unprotected. Then, the flash protection byte must be reprogrammed.
Trying to alter data in any protected area in the flash memory results in a protection violation error and FSTAT[FPVIOL] is set. The mass erase of the flash array is not possible if any of the flash sectors contained in the flash array are protected.
76543210
R
W
ResetFFFFFFFF
Figure 4-6. Flash Protection Register (FPROT)
Table 4-12. FPROT Field Descriptions
Field Description
7–1
FPS
0
FPOPEN
Flash Protection Size. With FPOPEN set, the FPS bits determine the size of the protected flash address range as shown in Ta bl e 4 - 13 .
Flash Protection Open 0 Flash array fully protected. 1 Flash array protected address range determined by FPS bits.
Table 4-13. Flash Protection Address Range
FPS FPOPEN
FPS FPOPEN
Protected Address Range
Relative to Flash Array Base
Protected
Size
— 0 0x0_0000–0x1_FFFF 128 Kbytes
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Table 4-13. Flash Protection Address Range (continued)
FPS FPOPEN
0x00–0x3F
0x40 0x0_0000–0x1_F7FF 126 Kbytes
0x41 0x0_0000–0x1_EFFF 124 Kbytes
0x42 0x0_0000–0x1_E7FF 122 Kbytes
1
0x43 0x0_0000–0x1_DFFF 120 Kbytes
0x44 0x0_0000–0x1_D7FF 118 Kbytes
0x45 0x0_0000–0x1_CFFF 116 Kbytes
0x46 0x0_0000-0x1_C7FF 114 Kbytes
0x47
... ... ...
0x5B 0x0_0000–0x1_1FFF 72 Kbytes
0x5C 0x0_0000–0x1_17FF 70 Kbytes
0x5D 0x0_0000–0x1_0FFF 68 Kbytes
0x5E 0x0_0000–0x1_07FF 66 Kbytes
0x5F 0x0_0000–0x0_FFFF 64 Kbytes
Protected Address Range
Relative to Flash Array Base
0x0_0000–0x1_FFFF 128 Kbytes
0x0_0000–0x1_BFFF 112 Kbytes
Protected
Size
0x60 0x0_0000–0x0_F7FF 62 Kbytes
0x61 0x0_0000–0x0_EFFF 60 Kbytes
0x62 0x0_0000–0x0_E7FF 58 Kbytes
0x63 0x0_0000–0x0_DFFF 56 Kbytes
... ... ...
0x77 0x0_0000–0x0_3FFF 16 Kbytes
0x78 0x0_0000–0x0_37FF 14 Kbytes
0x79 0x0_0000–0x0_2FFF 12 Kbytes
0x7A 0x0_0000–0x0_27FF 10 Kbytes
0x7B 0x0_0000–0x0_1FFF 8 Kbytes
0x7C 0x0_0000–0x0_17FF 6 Kbytes
0x7D 0x0_0000–0x0_0FFF 4 Kbytes
0x7E 0x0_0000–0x0_07FF 2 Kbytes
0x7F No Protection 0 Kbytes
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Chapter 4 Memory
4.4.2.5 Flash Status Register (FSTAT)
The FSTAT register defines the operational status of the flash module. FCBEF, FPVIOL and FACCERR are readable and writable. FBLANK is readable and not writable. The remaining bits read 0 and are not writable.
76543210
R FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
Ww1c
Reset11000000
Field Description
w1c w1c
Figure 4-7. Flash Status Register (FSTAT)
Table 4-14. FSTAT Field Descriptions
7
FCBEF
6
FCCF
5
FPVIOL
4
FACCERR
3 Reserved, should be cleared.
Command Buffer Empty Flag. The FCBEF flag indicates that the command buffer is empty so that a new command write sequence can be started when performing burst programming. Writing a 0 to the FCBEF flag has no effect on FCBEF. Writing a 0 to FCBEF after writing an aligned address to the flash array memory, but before FCBEF is cleared, aborts a command write sequence and causes the FACCERR flag to be set. Writing a 0 to FCBEF outside of a command write sequence does not set the FACCERR flag. Writing a 1 to this bit clears it. 0 Command buffers are full. 1 Command buffers are ready to accept a new command.
Command Complete Flag. The FCCF flag indicates that there are no more commands pending. The FCCF flag is cleared when FCBEF is cleared and sets automatically upon completion of all active and pending commands. The FCCF flag does not set when an active program command completes and a pending burst program command is fetched from the command buffer. Writing to the FCCF flag has no effect on FCCF. 0 Command in progress. 1 All commands are completed.
Protection Violation Flag. The FPVIOL flag indicates an attempt was made to program or erase an address in a protected area of the flash memory during a command write sequence. Writing a 0 to the FPVIOL flag has no effect on FPVIOL. Writing a 1 to this bit clears it. While FPVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected. 1 Protection violation has occurred.
Access Error Flag. The FACCERR flag indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence (see Section 4.5.1.2, “Command Write Sequence”), issuing an illegal flash command (see Section 4.4.2.6, “Flash Command Register (FCMD)”), or the execution of a CPU STOP instruction while a command is executing (FCCF = 0). Writing a 0 to the FACCERR flag has no effect on FACCERR. Writing a 1 to this bit clears it. While FACCERR is set, it is not possible to launch a command or start a command write sequence. 0 No access error detected. 1 Access error has occurred.
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Table 4-14. FSTAT Field Descriptions (continued)
Field Description
Chapter 4 Memory
2
FBLANK
1–0 Reserved, should be cleared.
Flag Indicating the Erase Verify Operation Status. When the FCCF flag is set after completion of an erase verify command, the FBLANK flag indicates the result of the erase verify operation. The FBLANK flag is cleared by the flash module when FCBEF is cleared as part of a new valid command write sequence. Writing to the FBLANK flag has no effect on FBLANK. 0 Flash block verified as not erased. 1 Flash block verified as erased.
4.4.2.6 Flash Command Register (FCMD)
The FCMD register is the flash command register. All FCMD bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable.
76543210
R0
W
Reset00000000
Figure 4-8. Flash Command Register (FCMD)
Table 4-15. FCMD Field Descriptions
Field Description
FCMD
7 Reserved, should be cleared.
6–0
FCMD
Flash Command. Valid flash commands are shown below. Writing any command other than those listed sets the FACCERR flag in the FSTAT register. 0x05 Erase Verify 0x20 Program 0x25 Burst Program 0x40 Sector Erase 0x41 Mass Erase

4.5 Function Description

4.5.1 Flash Command Operations

Flash command operations execute program, erase, and erase verify algorithms described in this section. The program and erase algorithms are controlled by the flash memory controller whose time base, FCLK, is derived from the bus clock via a programmable divider.
The next sections describe:
1. How to write the FCDIV register to set FCLK
2. Command write sequences to program, erase, and erase verify operations on the flash memory
3. Valid flash commands
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Chapter 4 Memory
4. Effects resulting from illegal flash command write sequences or aborting flash operations
4.5.1.1 Writing the FCDIV Register
Prior to issuing any flash command after a reset, write the FCDIV register to divide the bus clock down to 150–200 kHz. The FCDIV[PRDIV8, FDIV] bits must be set as described in Figure 4-9.
For example, if the bus clock frequency is 25 MHz, FCDIV[FDIV] should be set to 0x0F (0011 1 1) and the FCDIV[PRDIV8] bit set to 1. The resulting FCLK frequency is then 195 kHz. In this case, the flash program and erase algorithm timings are increased over the optimum target by:
(200 - 195) ÷ 200 = 3% Eqn. 4-1
CAUTION
Program and erase command execution time increase proportionally with the period of FCLK. Programming or erasing the flash memory with FCLK less than 150 kHz should be avoided. Setting FCDIV to a value such that FCLK is less than 150 kHz can destroy the flash memory due to overstress. Setting FCDIV to a value where FCLK is greater than 200 kHz can result in incomplete programming or erasure of the flash memory cells.
If the FCDIV register is written, the FDIVLD bit is automatically set. If the FDIVLD bit is 0, the FCDIV register has not been written since the last reset. If the FCDIV register has not been written to, the flash command loaded during a command write sequence does not execute and FSTAT[FACCERR] is set.
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set PRDIV8 = 1
yes
no
PRDIV8 = 0 (reset)
≥ 12.8MHz?
FCLK = (PRDCLK)/(1+FDIV[5:0])
PRDCLK = bus_clock
PRDCLK = bus_clock/8
PRDCLK[kHz]/200
no
set FDIV[5:0] = PRDCLK[kHz]/200-1
yes
START
an integer?
set FDIV[5:0] = INT(PRDCLK[kHz]/200)
END
bus_clock
no
yes
0.3MHz?
bus_clock
ALL PROGRAM AND ERASE
COMMANDS IMPOSSIBLE
Note:
• FCLK is the clock of the flash timing control block
• INT(x) is the integer part of x (e.g. INT(4.323) = 4)
4.5.1.2 Command Write Sequence
The flash command controller supervises the command write sequence to execute program, erase, and
Figure 4-9. Determination Procedure for PRDIV8 and FDIV Bits
erase verify algorithms. Before starting a command write sequence, the F ACCERR and FPVIOL flags in the FSTAT register must
be clear and the FCBEF flag must be set (see Section 4.4.2.5). A command write sequence consists of three steps that must be strictly adhered to with writes to the flash
module not permitted between the steps. However, flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows:
1. Write to a valid address in the flash array memory.
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Chapter 4 Memory
2. Write a valid command to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the command.
After a command is launched, the completion of the command operation is indicated by the setting of FSTAT[FCCF]. The FCCF flag sets upon completion of all active and buffered burst program commands.

4.5.2 Flash Commands

Table 4-16 summarizes the valid flash commands along with the effects of the commands on the flash
block.
Table 4-16. Flash Command Description
FCMD
0x05 Erase Verify Verify all memory bytes in the flash array memory are erased.
0x20 Program Program an address in the flash array.
0x25 Burst Program Program an address in the flash array with the internal address incrementing after the
0x40 Sector Erase Erase all memory bytes in a sector of the flash array.
0x41 Mass Erase Erase all memory bytes in the flash array.
NVM
Command
Function on Flash Memory
If the flash array memory is erased, FSTAT[FBLANK] sets upon command completion.
program operation.
A mass erase of the full flash array is only possible when no protection is enabled prior to launching the command.
CAUTION
A flash block address must be in the erased state before being programmed. Cumulative programming of bits within a flash block address is not allowed except for status field updates required in EEPROM emulation applications.
4.5.2.1 Erase Verify Command
The erase verify operation verifies that the entire flash array memory is erased. An example flow to execute the erase verify operation is shown in Figure 4-10. The erase verify command
write sequence is as follows:
1. Write to an aligned flash block address to start the command write sequence for the erase verify command. The address and data written are ignored.
2. Write the erase verify command, 0x05, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the erase verify command.
After launching the erase verify command, FSTAT[FCCF] sets after the operation has completed. The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in the flash array memory plus several bus cycles as measured from the time the FCBEF flag is cleared until the FCCF flag is set. Upon completion of the erase verify operation, FSTAT[FBLANK] is set if all addresses in the flash array memory are verified to be erased. If any address in the flash array memory is not erased, the erase verify operation terminates and FSTAT[FBLANK] remains cleared.
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Chapter 4 Memory
Write: Flash Block Address
Write: FCMD register
Write: FSTAT register
1.
2.
3.
Write: FSTAT register
yes
no
Access Error and
no
Bit Polling for
Read: FSTAT register
yes
Read: FSTAT register
no
START
yes
FCBEF
Set?
Command
FCCF
Set?
FACCERR/FPVIOL
Set?
no
Erase Verify
yes
EXIT
Flash Block
FBLANK
Set?
Write: FCDIV register
Read: FCDIV register
yes
no
Clock Register
FDIVLD
Set?
Note: FCDIV needs to
Written Check
Protection Violation Check
Buffer Empty Check
and Dummy Data
Erase Verify Command 0x05
Clear FCBEF 0x80
Clear FACCERR/FPVIOL 0x30
Command Completion Check
Status
Erased
Flash Block Not Erased
EXIT
be set after each reset
4.5.2.2 Program Command
The program operation programs a previously erased address in the flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 4-11. The program command write sequence is as follows:
1. Write to an aligned flash block address to start the command write sequence for the program
2. Write the program command, 0x20, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the program
Freescale Semiconductor 81
command. The data written is programmed to the address written.
command.
Figure 4-10. Example Erase Verify Command Flow
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Chapter 4 Memory
Write: Flash Array Address
Write: FCMD register
Write: FSTAT register
1.
2.
3.
Write: FSTAT register
yes
no
Access Error and
no
Bit Polling for
Read: FSTAT register
yes
Read: FSTAT register
no
START
yes
FCBEF
Set?
Command
FCCF
Set?
FACCERR/FPVIOL
Set?
Write: FCDIV register
Read: FCDIV register
yes
no
Clock Register
FDIVLD
Set?
Note: FCDIV needs to
Written Check
Protection Violation Check
Buffer Empty Check
and Program Data
Program Command 0x20
Clear FCBEF 0x80
Clear FACCERR/FPVIOL 0x30
Command Completion Check
EXIT
be set after each reset
If an address to be programmed is in a protected area of the flash block, FSTAT[FPVIOL] sets and the program command does not launch. After the program command has successfully launched and the program operation has completed, FSTAT[FCCF] is set.
Figure 4-11. Example Program Command Flow
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Chapter 4 Memory
4.5.2.3 Burst Program Command
The burst program operation programs previously erased data in the flash memory using an embedded algorithm.
While burst programming, two internal data registers operate as a buffer and a register (2-stage FIFO) so that a second burst programming command along with the necessary data can be stored to the buffers while the first burst programming command remains in progress. This pipelined operation allows a time optimization when programming more than one consecutive address on a specific row in the flash array as the high voltage generation can be kept active in between two programming commands.
An example flow to execute the burst program operation is shown in Figure 4-12. The burst program command write sequence is as follows:
1. Write to an aligned flash block address to start the command write sequence for the burst program command. The data written is programmed to the address written.
2. Write the program burst command, 0x25, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the program burst command.
4. After the FCBEF flag in the FSTAT register returns to a 1, repeat steps 1 through 3. The address written is ignored but is incremented internally.
The burst program procedure can be used to program the entire flash memory even while crossing row boundaries within the flash array . If data to be burst programmed falls within a protected area of the flash array, FSTAT[FPVIOL] is set and the burst program command does not launch. After the burst program command has successfully launched and the burst program operation has completed, FST AT[FCCF] is set unless a new burst program command write sequence has been buffered. By executing a new burst program command write sequence on sequential addresses after the FCBEF flag in the FST AT register has been set, a greater than 50% faster programming time for the entire flash array can be effectively achieved when compared to using the basic program command.
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Chapter 4 Memory
Write: Flash Array Address
Write: FCMD register
Write: FSTAT register
1.
2.
3.
Write: FSTAT register
yes
no
Access Error and
no
Bit Polling for
Read: FSTAT register
yes
Read: FSTAT register
no
START
yes
FCBEF
Set?
Command
FCCF
Set?
FACCERR/FPVIOL
Set?
Write: FCDIV register
Read: FCDIV register
yes
no
Clock Register
FDIVLD
Set?
Note: FCDIV needs to
Written Check
Protection Violation Check
Buffer Empty Check
and Program Data
Burst Program Command 0x25
Clear FCBEF 0x80
Clear FACCERR/FPVIOL 0x30
Command Completion Check
EXIT
be set after each reset
no
Bit Polling for
Read: FSTAT register
yes
FCBEF
Set?
Command Buffer Empty Check
yes
Sequential
no
Next
Address?
Programming Decision
4.5.2.4 Sector Erase Command
The sector erase operation erases all addresses in a 1 Kbyte sector of flash memory using an embedded algorithm.
Figure 4-12. Example Burst Program Command Flow
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Chapter 4 Memory
Write: Flash Sector Address
Write: FCMD register
Write: FSTAT register
1.
2.
3.
Write: FSTAT register
yes
no
Access Error and
no
Bit Polling for
Read: FSTAT register
yes
Read: FSTAT register
no
START
yes
FCBEF
Set?
Command
FCCF
Set?
FACCERR/FPVIOL
Set?
Write: FCDIV register
Read: FCDIV register
yes
no
Clock Register
FDIVLD
Set?
Note: FCDIV needs to
Written Check
Protection Violation Check
Buffer Empty Check
and Dummy Data
Sector Erase Command 0x40
Clear FCBEF 0x80
Clear FACCERR/FPVIOL 0x30
Command Completion Check
EXIT
be set after each reset
An example flow to execute the sector erase operation is shown in Figure 4-13. The sector erase command write sequence is as follows:
1. Write to an aligned flash block address to start the command write sequence for the sector erase command. The flash address written determines the sector to be erased while the data written is ignored.
2. Write the sector erase command, 0x40, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the sector erase command.
If a flash sector to be erased is in a protected area of the flash block, FSTAT[FPVIOL] is set and the sector erase command does not launch. After the sector erase command has successfully launched and the sector erase operation has completed, FSTAT[FCCF] is set.
Figure 4-13. Example Sector Erase Command Flow
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Chapter 4 Memory
Write: Flash Memory Address
Write: FCMD register
Write: FSTAT register
1.
2.
3.
Write: FSTAT register
yes
no
Access Error and
no
Bit Polling for
Read: FSTAT register
yes
Read: FSTAT register
no
START
yes
FCBEF
Set?
Command
FCCF
Set?
FACCERR/FPVIOL
Set?
Write: FCDIV register
Read: FCDIV register
yes
no
Clock Register
FDIVLD
Set?
Note: FCDIV needs to
Written Check
Protection Violation Check
Buffer Empty Check
and Dummy Data
Mass Erase Command 0x41
Clear FCBEF 0x80
Clear FACCERR/FPVIOL 0x30
Command Completion Check
EXIT
be set after each reset
4.5.2.5 Mass Erase Command
The mass erase operation erases the entire flash array memory using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 4-14. The mass erase command write sequence is as follows:
1. Write to an aligned flash block address to start the command write sequence for the mass erase command. The address and data written is ignored.
2. Write the mass erase command, 0x41, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the mass erase command.
If the flash array memory to be mass erased contains any protected area, FSTAT[FPVIOL] is set and the mass erase command does not launch. After the mass erase command has successfully launched and the mass erase operation has completed, FSTAT[FCCF] is set.
Figure 4-14. Example Mass Erase Command Flow
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NOTE
The BDM can also perform a mass erase and verify command. See
Chapter 18, “Version 1 ColdFire Debug (CF1_DEBUG),” for details.

4.5.3 Illegal Flash Operations

4.5.3.1 Flash Access Violations
The FACCERR flag is set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort:
1. Writing to a flash address before initializing the FCDIV register.
2. Writing a byte, word, or misaligned longword to a valid flash address.
3. Writing to any flash register other than FCMD after writing to a flash address.
4. Writing to a second flash address in the same command write sequence.
5. Writing an invalid command to the FCMD register unless the address written was in a protected area of the flash array.
6. Writing a command other than burst program while FCBEF is set and FCCF is clear.
7. When security is enabled, writing a command other than erase verify or mass erase to the FCMD register when the write originates from a non-secure memory location or from the background debug mode.
8. Writing to a flash address after writing to the FCMD register.
9. Writing to any flash register other than FSTAT (to clear FCBEF) after writing to the FCMD register.
10. Writing a 0 to the FCBEF flag in the FSTAT register to abort a command write sequence.
The F ACCERR flag is also set if the MCU enters stop mode while any command is active (FCCF=0). The operation is aborted immediately and, if burst programming, any pending burst program command is purged (see Section 4.5.4.2, “Stop Modes”).
The FACCERR flag does not set if any flash register is read during a valid command write sequence. If the flash memory is read during execution of an algorithm (FCCF = 0), the read operation returns invalid
data and the FACCERR flag is not set. If the FACCERR flag is set in the FSTAT register, clear the FACCERR flag before starting another
command write sequence (see Section 4.4.2.5, “Flash Status Register (FSTAT)”).
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Chapter 4 Memory
4.5.3.2 Flash Protection Violations
The FPVIOL flag is set after the command is written to the FCMD register if any of the following illegal operations are attempted:
1. Writing the program command if the address written in the command write sequence was in a protected area of the flash array.
2. Writing the sector erase command if the address written in the command write sequence was in a protected area of the flash array.
3. Writing the mass erase command while any flash protection is enabled.
4. Writing an invalid command if the address written in the command write sequence was in a protected area of the flash array.
As a result of any of the above, the command write sequence immediately aborts. If FSTAT[FPVIOL] is set, clear the FPVIOL flag before starting another command write sequence (see Section 4.4.2.5, “Flash
Status Register (FSTAT)”).

4.5.4 Operating Modes

4.5.4.1 Wait Mode
If a command is active (FCCF = 0) when the MCU enters wait mode, the active command and any buffered command is completed.
4.5.4.2 Stop Modes
If a command is active (FCCF = 0) when the MCU enters any stop mode, the operation is aborted. If the operation is program or erase, the flash array data being programmed or erased may be corrupted and the FCCF and FACCERR flags are set. If active, the high voltage circuitry to the flash array is immediately switched off when entering stop mode. Upon exit from stop mode, the FCBEF flag is set and any buffered command is not launched. The F ACCERR flag must be cleared before starting a command write sequence (see Section 4.5.1.2, “Command Write Sequence”).
NOTE
As active commands are immediately aborted when the MCU enters stop mode, do not use the STOP instruction during program or erase operations.
Active commands continue when the MCU enters wait mode. Use of the STOP instruction when SOPT1[WAITE] is set is acceptable.
4.5.4.3 Background Debug Mode
In background debug mode, the FPROT register is writable without restrictions. If the MCU is unsecured, all flash commands listed in Table 4-16 can be executed. If the MCU is secured, only a compound mass erase and erase verify command can be executed. See Chapter 18, “Version 1 ColdFire Debug
(CF1_DEBUG),” for details.
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Chapter 4 Memory

4.5.5 Security

The flash module provides the necessary security information to the MCU. During each reset sequence, the flash module determines the security state of the MCU as defined in Section 4.2.1, “Flash Module
Reserved Memory Locations”.
The contents of the flash security byte in the flash configuration field (see Section 4.4.2.3) must be changed directly by programming the flash security byte location when the MCU is unsecured and the sector containing the flash security byte is unprotected. If the flash security byte is left in a secured state, any reset causes the MCU to initialize into a secure operating mode.
4.5.5.1 Unsecuring the MCU using Backdoor Key Access
The MCU may be unsecured by using the backdoor key access feature that requires knowledge of the contents of the backdoor keys (see Section 4.2.1). If the KEYEN[1:0] bits are in the enabled state (see
Section 4.4.2.2) and the KEY ACC bit is set, a write to a backdoor key address in the flash memory triggers
a comparison between the written data and the backdoor key data stored in the flash memory. If all backdoor keys are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the flash memory, the MCU is unsecured. The data must be written to the backdoor keys sequentially. Values 0x0000_0000 and 0xFFFF_FFFF are not permitted as backdoor keys. While the KEYACC bit is set, reads of the flash memory return valid data.
The user code stored in the flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state (see Section 4.4.2.2), the MCU can be unsecured by the backdoor key access sequence described below:
1. Set FCNFG[KEYACC].
2. Execute three NOP instructions to provide time for the backdoor state machine to load the starting address and number of keys required into the flash state machine.
3. Sequentially write the correct longwords to the flash address(es) containing the backdoor keys.
4. Clear the KEY A CC bit. Depending on the user code used to write the backdoor keys, a wait cycle (NOP) may be required before clearing the KEYACC bit.
5. If all data written match the backdoor keys, the MCU is unsecured and the SEC[1:0] bits in the NVOPT register are forced to an unsecured state.
The backdoor key access sequence is monitored by an internal security state machine. An illegal operation during the backdoor key access sequence causes the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU causes the security state machine to exit the lock state and allows a new backdoor key access sequence to be attempted. The following operations during the backdoor key access sequence lock the security state machine:
1. If any of the keys written does not match the backdoor keys programmed in the flash array.
2. If the keys are written in the wrong sequence.
3. If any of the keys written are all 0’s or all 1’s.
4. If the KEYACC bit does not remain set while the keys are written.
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Chapter 4 Memory
5. If any of the keys are written on successive MCU clock cycles.
6. Executing a STOP instruction before all keys have been written.
After the backdoor keys have been correctly matched, the MCU is unsecured. After the MCU is unsecured, the flash security byte can be programmed to the unsecure state, if desired.
In the unsecure state, you have full control of the contents of the backdoor keys by programming the associated addresses in the flash configuration field (see Section 4.2.1, “Flash Module Reserved Memory
Locations”).
The security as defined in the flash security byte is not changed by using the backdoor key access sequence to unsecure. The stored backdoor keys are unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the flash module is determined by the flash security byte. The backdoor key access sequence has no effect on the program and erase protections defined in the flash protection register (FPROT).
It is not possible to unsecure the MCU by using the backdoor key access sequence in background debug mode (BDM).

4.5.6 Resets

4.5.6.1 Flash Reset Sequence
On each reset, the flash module executes a reset sequence to hold CPU activity while reading the following resources from the flash block:
• MCU control parameters (see Section 4.2.1)
• Flash protection byte (see Section 4.2.1 and Section 4.4.2.4)
• Flash nonvolatile byte (see Section 4.2.1)
• Flash security byte (see Section 4.2.1 and Section 4.4.2.2)
4.5.6.2 Reset While Flash Command Active
If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the flash array address being programmed or the sector/block being erased is not guaranteed.
4.5.6.3 Program and Erase Times
Before any program or erase command can be accepted, the flash clock divider (FCDIV) must be written to set the internal clock for the flash module to a frequency (f
If the initial flash event is a mass erase and verify from BDM, then CSR3[31:24] must be loaded before the XCSR is written to initiate the erase and verify. The data in the XCSR and CSR3 is then loaded into the flash’s FCDIV register. (See Section 18.3.4, “Configuration/Status Register 3 (CSR3)”). However, if the first flash event is executed by the processor directly , the flash’ s FCDIV register is written directly , and the XCSR and CSR3 are not involved.
) between 150 kHz and 200 kHz.
FCLK
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Chapter 4 Memory
One period of the resulting clock (1/f
) is used by the command processor to time program and erase
FCLK
pulses. An integer number of these timing pulses are used by the command processor to complete a program or erase command.
Program and erase times are given in the MCF51QE128 Data Sheet, order number MCF51QE128DS.

4.6 Security

The MCF51QE128/64/32 includes circuitry to prevent unauthorized access to the contents of flash and RAM memory . When security is engaged, BDM access is restricted to the upper byte of the debug XCSR, CSR2, and CSR3 registers. RAM, flash memory , peripheral registers, and most of the CPU register set are not available via BDM. Programs executing from internal memory have normal access to all MCU memory locations and resources.
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01, SEC00) in the FOPT register. During reset, the contents of the nonvolatile location, NVOPT, are copied from flash into the working FOP T register in high-page register space. Engage security by programming the NVOP T location. This can be done at the same time the flash memory is programmed. The 1:1 state disengages security and the other three combinations engage security . Security is implemented differently than on the pin-compatible MC9S08QE128/64/32 family of devices. This is a result of differences inherent in the S08 and ColdFire MCU architectures.
Upon exiting reset, the XCSR[SEC] bit in the ColdFire CPU is set if the device is secured, cleared otherwise.
You can allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. The security key can be written by the CPU executing from internal memory. It cannot be entered without the cooperation of a secure user program. The procedure for this is detailed in Section 4.5.5.1, “Unsecuring
the MCU using Backdoor Key Access”.
Development tools unsecure devices via an alternate BDM-based methodology shown in Figure 4-15. Because RESET and BKGD pins can be reprogrammed via software, a power-on-reset is required to be absolutely certain of obtaining control of the device via BDM, which is a required prerequisite for clearing security. Other methods (outlined in red in Figure 4-15) can also be used, but may not work under all circumstances.
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Write CSR2[25:24]=11 to initiate BDM reset to halt or
write CSR2[25:24]=01 to initiate BDM reset to run
On-chip flash is erased and unsecure
Is XCSR[25] cleared
(erase/verify complete)
?
Ye s
No
Write XCSR[31:24] = 0x87 to initiate
erase/verify of flash memory
Set PRDIV8 and clock divider fields in CSR3
Delay ‘TBD’ cycles
Device is unsecure
1
1. The last three steps are optional, but recommended.
Ways to enter BDM halt mode:
1. BKGD=0 during POR BKGD=0 during external reset BKGD=0 during BDM reset BFHBR=1 during BDM reset Issue BACKGROUND command via BDM interface HALT instruction BDM breakpoint ColdFire fault-on-fault
Of these, only method 1 is guaranteed to work under all circumstances because of the ability to program
2.
3.
4.
5.
6.
7.
8.
XCSR[31:24] = 0x87
N = number of cycles for SIM to release internal reset. Adder of 16 imposed by ColdFire core.
STOP
XCSR[25] = 0
STOP
Secure state unknown, CPU halted,
FEI 10 MHz clock, synchronized to debugger
SYNC
Secure state unknown, CPU halted,
FEI 10 MHz clock, SYNC required
Hold BKGD=0, apply power, wait N+16 cycles
for POR to deassert
Secure state unknown/unpowered
BKGD=0 during reset ensures that ENBDM comes up ‘1’.
FLL enabled, internal reference (FEI) at 10MHz is reset default for the ICS.
Error condition check code or device.
Already
XCSR[31:24] ≠ 1000_01x1
Read XCSR
unsecured
Note: This write is required
different functions on the BKGD package pin.
Figure 4-15. Procedure for Clearing Security on MCF51QE128/64/32 via the BDM Port
92 Freescale Semiconductor
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Chapter 5 Resets, Interrupts, and General System Control

5.1 Introduction

This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt on the MCF51QE128/64/32. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this document. This section gathers basic information about all reset and interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer operating properly (COP) watchdog, are not part of on-chip peripheral systems with their own chapters.

5.2 Features

Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation
• System reset status (SRS) register to indicate source of most recent reset
• Separate interrupt vector for most modules (reduces polling overhead)

5.3 Microcontroller Reset

Resetting the MCU provides a way to start processing from a known set of initial conditions. When the ColdFire processor exits reset, it fetches initial 32-bit values for the supervisor stack pointer and program counter from locations 0x(00)00_0000 and 0x(00)00_0004 respectively . On-chip pe ripheral modules are disabled and I/O pins are initially configured as general-purpose high-impedance inputs with pull-up devices disabled.
The MCF51QE128/64/32 has the following sources for reset:
• Power-on reset (POR)
• External pin reset (PIN)
• Computer operating properly (COP) timer
• Illegal opcode detect (ILOP)
• Illegal address detect (ILAD)
• Low-voltage detect (LVD)
• Background debug forced reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS).
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Chapter 5 Resets, Interrupts, and General System Control

5.3.1 Computer Operating Properly (COP) Watchdog

The COP watchdog forces a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically . If the application program gets lost and fails to reset th e COP counter before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the SOPT1[COPE] bit is set enabling the COP watchdog (see Section 5.7.3, “System
Options Register 1 (SOPT1),” for additional information). If the COP watchdog is not used in an
application, it can be disabled by clearing COPE. The COP counter is reset by writing any value to the address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a reset signal to the COP counter.
The SOPT2[COPCLKS] bit selects the clock source used for the COP timer (see Section 5.7.4, “System
Options Register 2 (SOPT2),” for additional information). The clock source options are either the bus
clock or an internal 1-kHz clock source. With each clock source, there is an associated short and long time-out controlled by the SOP T1[COPT] bit. Table 5-1 summaries the control functions of the COPCLKS and COP T bits. The COP watchdog defaults to operation from the 1-kHz clock source and the associated long time-out (28 cycles).
Table 5-1. COP Configuration Options
Control Bits
Clock Source COP Overflow Count
COPCLKS COPT
00~1 kHz2
01~1 kHz2
10Bus 2
11Bus 2
1
Values are shown in this column based on t
LPO
=1ms.
5
cycles (32 ms)
8
cycles (256 ms)
13
cycles
18
cycles
1
1
Write to the write-once SOP T11 and SOP T2 registers during reset initialization to lock in the settings, even if the application uses the default reset settings of COPE, COPCLKS, and COPT. That way, they cannot be changed accidentally if the application program gets lost. The initial writes to SOP T1 and SOPT2 reset the COP counter.
The write to SRS that services (clears) the COP counter must not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails.
In the CPU halt state, the COP counter does not increment. When the bus clock source is selected, the COP counter does not increment while the system is in stop
mode. The COP counter resumes as soon as the MCU exits stop mode. When the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to stop mode.
The COP counter begins from zero after the MCU exits stop mode.
1. The SOPT1[WAITE] bit can be written multiple times. Other bits are write-once.
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Chapter 5 Resets, Interrupts, and General System Control

5.3.2 Illegal Operation Reset

By default, the V1 ColdFire core generates a MCU reset when attempting to execute an illegal instruction (except for the ILLEGAL opcode), illegal line-A instruction, illegal line-F instruction, or a supervisor instruction while in user mode (privilege violation). The user may set CPUCR[IRD] to generate the appropriate exception instead of forcing a reset.
NOTE
The attempted execution of the STOP instruction with SOPT[STOPE, WAITE] cleared is treated as an illegal instruction.
The attempted execution of the HALT instruction with XCSR[ENBDM] cleared is treated as an illegal instruction.

5.3.3 Illegal Address Reset

By default, the V1 ColdFire core generates a MCU reset when detecting an address error, bus error termination, R TE format error, or fault-on-fault condition. The user may set CPUCR[ARD] to generate the appropriate exception instead of forcing a reset, or simply halt the processor in response to the fault-on-fault condition.

5.4 Interrupts and Exceptions

The interrupt architecture of ColdFire utilizes a 3-bit encoded interrupt priority level sent from the interrupt controller to the core, providing seven levels of interrupt requests. Level seven represents the highest priority interrupt level, while level one is the lowest priority. For more information on exception processing, see Chapter 8, “Interrupt Controller (CF1_INTC)”.

5.4.1 External Interrupt Request (IRQ) Pin

External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used, so the IRQ pin (if enabled) can wake the MCU.
5.4.1.1 Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be set for the IRQ pin to act as the interrupt request (IRQ) input. As an IRQ input, you can choose the polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD) and whether an event causes an interrupt or only sets the IRQF flag that can be polled by software (IRQIE).
The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), configured as a pull-up or pull-down depending on the polarity chosen. If you want to use an external pull-up or pull-down, the IRQPDD can be set to turn off the internal device.
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Chapter 5 Resets, Interrupts, and General System Control
NOTE
This pin does not contain a clamp diode to VDD and should not be driven above VDD.
NOTE
The voltage measured on the internally pulled up RESET pin is not pulled to VDD. The internal gates connected to this pin are pulled to VDD. The RESET pullup should not be used to pull up components external to the MCU.
5.4.1.2 Edge and Level Sensitivity
The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In the edge and level detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level.
5.4.1.3 External Interrupt Initialization
When the IRQ pin is first enabled, it is possible to get a false interrupt flag. To prevent a false interrupt request during IRQ initialization, the user should do the following:
1. Mask interrupts by clearing IRQSC[IRQIE].
2. Select the pin polarity by setting the appropriate IRQSC[IRQEDG] bits.
3. If using internal pull-up/pull-down device, clear IRQSC[IRQPDD].
4. Enable the IRQ pin by setting IRQSC[IRQPE].
5. Write to IRQSC[IRQACK] to clear any false interrupts.
6. Set IRQSC[IRQIE] to enable interrupts.

5.5 Low-Voltage Detect (LVD) System

The MCF51QE128/64/32 includes a system to guard against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user-selectable trip voltage, high (V (V
). The LVD circuit is enabled when the SPMSC1[LVDE] bit is set and the trip voltage is selected
LVDL
by the SPMSC3[LVDV] bit. The LVD is disabled upon entering stop2 or stop3 modes unless the L VDSE bit is set. If LVDE and LVDSE are set when the STOP instruction is processed, the device enters stop4 mode. The LVD can be left enabled in this mode.

5.5.1 Power-On Reset Operation

When power is initially applied to the MCU or the supply voltage drops below the power-on reset re-arm voltage level, V holds the MCU in reset until the supply has risen above the LVD low threshold, V SRS[POR,LVD] bits are set following a POR.
, the POR circuit causes a reset condition. As the supply voltage rises, the LVD circuit
POR
. The
LVDL
LVDH
) or low
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Chapter 5 Resets, Interrupts, and General System Control

5.5.2 LVD Reset Operation

The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has occurred, the L VD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold. SRS[LVD] is set following an LVD reset or POR.

5.5.3 LVD Interrupt Operation

When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt operation (L VDE set, LVDIE set, and L VDRE clear), SPMSC1[L VDF] is set and an LVD interrupt request occurs. The LVDF bit is cleared by writing a 1 to the LVDACK bit in SPMSC1.

5.5.4 Low-Voltage Warning (LVW) Interrupt Operation

The LVD system has a low voltage warning flag (LVWF) to indicate the supply voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt associated with it, enabled by setting the SPMSC3[LVWIE] bit. If enabled, an LVW interrupt request occurs when the LVWF is set. LVWF is cleared by writing a 1 to the SPMSC3[LVWACK] bit. There are two user-selectable trip voltages for the LVW, one high (V
) and one low (V
LVWH
). The trip voltage is selected by SPMSC3[LVWV] bit.
LVWL

5.6 Peripheral Clock Gating

The MCF51QE128/64/32 includes a clock gating system to manage the bus clock sources to the individual peripherals. Using this system, you can enable or disable the bus clock to each of the peripherals at the clock source, eliminating unnecessary clocks to peripherals which are not in use. This reduces the overall run and wait mode currents.
Out of reset, all peripheral clocks are enabled. For lowest possible run or wait currents, software should disable the clock source to any peripheral not in use. The actual clock is enabled or disabled immediately following the write to the clock gating control registers (SCGC1, SCGC2). Any peripheral with a gated clock cannot be used unless its clock is enabled. Writing to the registers of a peripheral with a disabled clock has no effect.
NOTE
Software should disable the peripheral before disabling the clocks to the peripheral. After clocks are re-enabled to a peripheral, the peripheral registers need to be re-initialized by software.
In stop modes, the bus clock is disabled for all gated peripherals, regardless of the settings in the SCGC1 and SCGC2 registers.

5.7 Reset, Interrupt, and System Control Registers and Control Bits

One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems.
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Refer to Chapter 4, “Memory”, for the absolute address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation”.

5.7.1 Interrupt Pin Request Status and Control Register (IRQSC)

This direct page register includes status and control bits which are used to configure the IRQ function, report status, and acknowledge IRQ events.
76543210
R0
IRQPDD IRQEDG IRQPE
W IRQACK
Reset00000000
Figure 5-1. Interrupt Request Status and Control Register (IRQSC)
IRQF 0
IRQIE IRQMOD
Table 5-2. IRQSC Register Field Descriptions
Field Description
7 Reserved, should be cleared.
6
IRQPDD
5
IRQEDG
4
IRQPE
3
IRQF
2
IRQACK
Interrupt Request (IRQ) Pull Device Disable. This read/write control bit is used to disable the internal pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used. 0 IRQ pull device enabled if IRQPE = 1. 1 IRQ pull device disabled if IRQPE = 1.
Interrupt Request (IRQ) Edge Select. This read/write control bit selects the polarity of edges or levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensitive to edges and levels or only edges. When IRQEDG is set and the internal pull device is enabled, the pull-up device is reconfigured as an optional pull-down device. 0 IRQ is falling edge or falling edge/low-level sensitive. 1 IRQ is rising edge or rising edge/high-level sensitive.
IRQ Pin Enable. This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can be used as an external interrupt request. 0 IRQ pin function is disabled. 1 IRQ pin function is enabled.
IRQ Flag. This read-only status bit indicates when an interrupt request event has occurred. 0 No IRQ request. 1 IRQ event detected.
IRQ Acknowledge. This write-only bit acknowledges interrupt request events (write 1 to clear IRQF). Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.
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Table 5-2. IRQSC Register Field Descriptions (continued)
Field Description
1
IRQIE
0
IRQMOD
IRQ Interrupt Enable. This read/write control bit determines whether IRQ events generate an interrupt request. 0 Interrupt request when IRQF set is disabled (use polling). 1 Interrupt requested when IRQF is set.
IRQ Detection Mode. This read/write control bit selects edge-only detection or edge-and-level detection. The IRQEDG control bit determines the polarity of edges and levels detected as interrupt request events. See
Section 5.4.1.2, “Edge and Level Sensitivity” for more details.
0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels.

5.7.2 System Reset Status Register (SRS)

This high page register includes read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by setting CSR2[BDFR], none of the status bits in SRS are set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset.
76543210
R POR PIN COP ILOP ILAD 0 LVD 0
W Writing any value to SRS address clears COP watchdog timer.
POR:
LV D:
10000010
u0000010
Any other
reset:
1
Any of these reset sources active at the time of reset entry causes the corresponding bit(s) to be set; bits corresponding to sources not active at the time of reset entry are cleared.
0Note1Note
1
Note
1
Note
1
000
Figure 5-2. System Reset Status (SRS)
Table 5-3. SRS Register Field Descriptions
Field Description
7
POR
6
PIN
5
COP
Power-On Reset. Reset was caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 Reset not caused by POR. 1 POR caused reset.
External Reset Pin. Reset was caused by an active-low level on the external reset pin. 0 Reset not caused by external reset pin. 1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog. Reset was caused by the COP watchdog timer timing out. This reset source is blocked if COPE is cleared. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout.
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Table 5-3. SRS Register Field Descriptions (continued)
Field Description
4
ILOP
3
ILAD
2 Reserved, should be cleared.
1
LV D
0 Reserved, should be cleared.
Illegal Opcode. Reset was caused by an attempt to execute an unimplemented or illegal opcode. This includes any illegal instruction (except the ILLEGAL (0x4AFC) opcode) or a privilege violation (execution of a supervisor instruction in user mode. The STOP instruction is considered illegal if SOPT1[STOPE,WAITE] are cleared. The HALT instruction is considered illegal if the BDM interface is disabled (XCSR[ENBDM] = 0). All illegal opcode resets are enabled when CPUCR[IRD] is cleared. If CPUCR[IRD] is set, then the appropriate processor exception is generated instead of a reset. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode.
Illegal Address. Reset was caused by the processor's attempted access of an illegal address in the memory map, an address error, an RTE format error, or a fault-on-fault condition. All the illegal address resets are enabled when CPUCR[ARD] is cleared. When CPUCR[ARD] is set, the appropriate processor exception is generated instead of a reset, or if a fault-on-fault condition is reached, the processor simply halts. 0 Reset not caused by an illegal access. 1 Reset caused by an illegal access.
Low Voltage Detect. If LVDRE is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is also set by POR. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR.

5.7.3 System Options Register 1 (SOPT1)

All SOP T1 bit fields, except WAITE, are write-once. Therefore for the write-once bits, only the first write after reset is honored. Any subsequent attempt to write to these bit fields (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. All bit fields may be read at any time and W AITE is write-anytime. SOP T1 should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
76543210
R
COPE COPT STOPE WAITE
W
Reset:11010u11u
POR:11010010
LVR:11010010
1
u = unaffected
Figure 5-3. System Options Register 1 (SOPT1)
0
RSTOPE BKGDPE RSTPE
1
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