Freescale Semiconductor MC9S12G User guide

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MC9S12G Family Reference Manual and Data Sheet

S12 Microcontrollers

MC9S12GRMV1

Rev.1.23

February 1, 2013

freescale.com

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

freescale.com/

A full list of family members and options is included in the appendices.

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The following revision history table summarizes changes contained in this document.

Revision History

Date

Sep, 2012 1.14

Sep, 2012 1.15

Sep, 2012 1.16

Nov, 2012 1.17

Nov, 2012 1.18

Nov, 2012 1.19 • Corrected order of chapters

Revision

Level

• Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals)

• Updated Chapter 1, “Device Overview MC9S12G-Family” (Reason: corrected pinout diagram)

• Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals)

• Added Chapter 12, “Analog-to-Digital Converter (ADC12B8CV2)”

• Added Chapter 14, “Analog-to-Digital Converter (ADC12B12CV2)”

• Updated Chapter 11, “Analog-to-Digital Converter (ADC10B8CV2)” (Reason: Spec update)

• Updated Chapter 13, “Analog-to-Digital Converter (ADC10B12CV2)” (Reason: Spec update)

• Updated Chapter 15, “Analog-to-Digital Converter (ADC10B16CV2)” (Reason: Spec update)

• Updated Chapter 16, “Analog-to-Digital Converter (ADC12B16CV2)” (Reason: Spec update)

Description

Jan, 2013 1.20

Jan, 2013 1.21

Jan, 2012 1.22

Feb, 2012 1.23

• Updated Appendix A, “Electrical Characteristics” (Reason: Added AEC Grade 0 spec)

• Updated Appendix C, “Ordering and Shipping Information” (Reason: Added temperature option W)

• Separated description of 8-channel timer

• Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals)

• Updated Chapter 1, “Device Overview MC9S12G-Family” (Reason: added KGD option for the S12GA192 and the S12GA240)

• Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals)

• Up[dated Appendix C, “Ordering and Shipping Information” (Reason: Added KGD information)

• Added Appendix D, “Package and Die Information” (Reason: Added KGD information)

• Updated Appendix C, “Ordering and Shipping Information” (Reason: Removed KGD information)

• Added Appendix D, “Package and Die Information” (Reason: Updated KGD information)

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This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual

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Chapter 1 Device Overview MC9S12G-Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Chapter 2 Port Integration Module (S12GPIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Chapter 3 5V Analog Comparator (ACMPV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

Chapter 4 Reference Voltage Attenuator (RVAV1) . . . . . . . . . . . . . . . . . . . . . . . . . .263

Chapter 5 S12G Memory Map Controller (S12GMMCV1) . . . . . . . . . . . . . . . . . . . . .267

Chapter 6 Interrupt Module (S12SINTV1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

Chapter 7 Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . . . . . . . . . . .289

Chapter 8 S12S Debug Module (S12SDBGV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

Chapter 9 Security (S12XS9SECV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU) . . . . . . . . .361

Chapter 11 Analog-to-Digital Converter (ADC10B8CV2) . . . . . . . . . . . . . . . . . . . . . .419

Chapter 12 Analog-to-Digital Converter (ADC12B8CV2) . . . . . . . . . . . . . . . . . . . . . .443

Chapter 13 Analog-to-Digital Converter (ADC10B12CV2) . . . . . . . . . . . . . . . . . . . . .469

Chapter 14 Analog-to-Digital Converter (ADC12B12CV2) . . . . . . . . . . . . . . . . . . . . .495

Chapter 15 Analog-to-Digital Converter (ADC10B16CV2) . . . . . . . . . . . . . . . . . . . . .521

Chapter 16 Analog-to-Digital Converter (ADC12B16CV2) . . . . . . . . . . . . . . . . . . . . .547

Chapter 17 Digital Analog Converter (DAC_8B5V) . . . . . . . . . . . . . . . . . . . . . . . . . . .573

Chapter 18 Freescale’s Scalable Controller Area Network (S12MSCANV3) . . . . . .585

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2) . . . . . . . . . . . . . . . . . . . . . . .637

Chapter 20 Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . . . . . . . . . . .667

Chapter 21 Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . . . . . . . . . .705

Chapter 22 Timer Module (TIM16B6CV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .733

Chapter 23 Timer Module (TIM16B8CV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .751

Chapter 24 16 KByte Flash Module (S12FTMRG16K1V1) . . . . . . . . . . . . . . . . . . . . .779

Chapter 25 32 KByte Flash Module (S12FTMRG32K1V1) . . . . . . . . . . . . . . . . . . . . .827

Chapter 26 48 KByte Flash Module (S12FTMRG48K1V1) . . . . . . . . . . . . . . . . . . . . .879

Chapter 27 64 KByte Flash Module (S12FTMRG64K1V1) . . . . . . . . . . . . . . . . . . . . .931

Chapter 28 96 KByte Flash Module (S12FTMRG96K1V1) . . . . . . . . . . . . . . . . . . . . .983

Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1) . . . . . . . . . . . . . . . . . .1035

Chapter 30 192 KByte Flash Module (S12FTMRG192K2V1) . . . . . . . . . . . . . . . . . .1087

Chapter 31 240 KByte Flash Module (S12FTMRG240K2V1) . . . . . . . . . . . . . . . . . .1139

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Appendix A Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1191

Appendix B Detailed Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1249

Appendix C Ordering and Shipping Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .1269

Appendix D Package and Die Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1271

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Chapter 1

Device Overview MC9S12G-Family

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

1.2.1 MC9S12G-Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

1.2.2 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

1.3 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

1.3.1 S12 16-Bit Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

1.3.2 On-Chip Flash with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

1.3.3 On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

1.3.4 Port Integration Module (PIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

1.3.5 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.3.6 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.3.7 Internal Phase-Locked Loop (IPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.3.8 System Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1.3.9 Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1.3.10 Pulse Width Modulation Module (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1.3.11 Controller Area Network Module (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1.3.12 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

1.3.13 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

1.3.14 Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

1.3.15 Reference Voltage Attenuator (RVA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.3.16 Digital-to-Analog Converter Module (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.3.17 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.3.18 On-Chip Voltage Regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.3.19 Background Debug (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.3.20 Debugger (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

1.4 Key Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

1.6 Family Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

1.6.1 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

1.7 Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

1.7.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.7.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.7.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

1.8 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.8.1 S12GN16 and S12GN32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.8.2 S12GNA16 and S12GNA32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

1.8.3 S12GN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

1.8.4 S12G48 and S12G64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

1.8.5 S12GA48 and S12GA64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

1.8.6 S12G96 and S12G128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

1.8.7 S12GA96 and S12GA128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

1.8.8 S12G192 and S12G240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

1.8.9 S12GA192 and S12GA240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

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1.9 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

1.10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

1.10.1 Chip Conﬁguration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

1.10.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

1.11 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

1.12 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

1.12.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

1.12.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

1.12.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

1.13 COP Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

1.14 Autonomous Clock (ACLK) Conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

1.15 ADC External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

1.16 ADC Special Conversion Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

1.17 ADC Result Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

1.18 ADC VRH/VRL Signal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

1.19 BDM Clock Source Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Chapter 2

Port Integration Module (S12GPIMV1)

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

2.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

2.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

2.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

2.2 PIM Routing - External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

2.2.1 Package Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

2.2.2 Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

2.2.3 Signals and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

2.3 PIM Routing - Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

2.3.1 Pin BKGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

2.3.2 Pins PA7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

2.3.3 Pins PB7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

2.3.4 Pins PC7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

2.3.5 Pins PD7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

2.3.6 Pins PE1-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

2.3.7 Pins PT7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

2.3.8 Pins PS7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

2.3.9 Pins PM3-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

2.3.10 Pins PP7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

2.3.11 Pins PJ7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

2.3.12 Pins AD15-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

2.4 PIM Ports - Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

2.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

2.4.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

2.4.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

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2.5 PIM Ports - Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

2.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

2.5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

2.5.3 Pin Conﬁguration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

2.5.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

2.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

2.6.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

2.6.2 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

2.6.3 Enabling IRQ edge-sensitive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

2.6.4 ADC External Triggers ETRIG3-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

2.6.5 Emulation of Smaller Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Chapter 3

5V Analog Comparator (ACMPV1)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

3.4 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

3.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

3.6 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

3.6.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

3.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

3.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Chapter 4

Reference Voltage Attenuator (RVAV1)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

4.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

4.4 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

4.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

4.6 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

4.6.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

4.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

4.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Chapter 5

S12G Memory Map Controller (S12GMMCV1)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

5.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

5.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

5.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

5.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

5.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

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5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

5.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

5.4.1 MCU Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

5.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

5.4.3 Unimplemented and Reserved Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

5.4.4 Prioritization of Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

5.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Chapter 6

Interrupt Module (S12SINTV1)

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

6.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

6.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

6.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

6.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

6.4.1 S12S Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

6.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

6.4.3 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

6.4.4 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

6.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

6.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

6.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

6.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Chapter 7

Background Debug Module (S12SBDMV1)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

7.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

7.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

7.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

7.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

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7.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

7.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

7.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

7.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

7.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

7.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

7.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

7.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

7.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

7.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Chapter 8

S12S Debug Module (S12SDBGV2)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

8.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

8.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

8.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

8.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

8.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

8.4.1 S12SDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

8.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

8.4.3 Match Modes (Forced or Tagged) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

8.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

8.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

8.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

8.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

8.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

8.5.1 State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

8.5.2 Scenario 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

8.5.3 Scenario 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

8.5.4 Scenario 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

8.5.5 Scenario 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

8.5.6 Scenario 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

8.5.7 Scenario 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

8.5.8 Scenario 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

8.5.9 Scenario 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

8.5.10 Scenario 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

8.5.11 Scenario 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

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Chapter 9

Security (S12XS9SECV2)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

9.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

9.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

9.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

9.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

9.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Chapter 10

S12 Clock, Reset and Power Management Unit (S12CPMU)

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

10.1.3 S12CPMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

10.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

10.2.1

10.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

10.2.3 VDDR — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

10.2.4 VSS — Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

10.2.5 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

10.2.6 VDDX, VSSX— Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

10.2.7 VDD — Internal Regulator Output Supply (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . 370

10.2.8 VDDF — Internal Regulator Output Supply (NVM Logic) . . . . . . . . . . . . . . . . . . . . . 370

10.2.9

10.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

10.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

10.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

10.4.3 Stop Mode using PLLCLK as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

10.4.4 Full Stop Mode using Oscillator Clock as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 408

10.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

10.4.6 System Clock Conﬁgurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

10.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

10.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

10.5.3 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

10.5.4 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

10.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

API_EXTCLK

— API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

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10.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

10.7.1 General Initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

10.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Chapter 11

Analog-to-Digital Converter (ADC10B8CV2)

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

11.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

11.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

11.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

11.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

11.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

11.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

Chapter 12

Analog-to-Digital Converter (ADC12B8CV2)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

12.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

12.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

12.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

12.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

12.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

Chapter 13

Analog-to-Digital Converter (ADC10B12CV2)

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

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13.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

13.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

13.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

13.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

13.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

Chapter 14

Analog-to-Digital Converter (ADC12B12CV2)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

14.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

14.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

14.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

14.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

14.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

Chapter 15

Analog-to-Digital Converter (ADC10B16CV2)

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

15.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

15.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

15.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

15.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

15.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

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Chapter 16

Analog-to-Digital Converter (ADC12B16CV2)

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

16.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

16.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

16.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

16.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

16.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

16.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

16.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Chapter 17

Digital Analog Converter (DAC_8B5V)

17.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

17.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

17.2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

17.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

17.3.1 DACU Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

17.3.2 AMP Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

17.3.3 AMPP Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

17.3.4 AMPM Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

17.4 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

17.4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

17.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

17.5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

17.5.2 Mode “Off” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

17.5.3 Mode “Operational Ampliﬁer” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

17.5.4 Mode “Unbuffered DAC” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

17.5.5 Mode “Unbuffered DAC with Operational Ampliﬁer” . . . . . . . . . . . . . . . . . . . . . . . . . 580

17.5.6 Mode “Buffered DAC” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

17.5.7 Analog output voltage calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

Chapter 18

Freescale’s Scalable Controller Area Network (S12MSCANV3)

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

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18.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

18.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

18.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

18.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

18.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

18.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

18.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

18.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

18.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

18.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

18.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

18.4.3 Identiﬁer Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

18.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

18.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630

18.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

18.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

18.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

18.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

18.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

Chapter 19

Pulse-Width Modulator (S12PWM8B8CV2)

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

19.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

19.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

19.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

19.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

19.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

19.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

Chapter 20

Serial Communication Interface (S12SCIV5)

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

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20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

20.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

20.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

20.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

20.3.1 Module Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

20.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682

20.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

20.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

20.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

20.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

20.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

20.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

20.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

20.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

20.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

20.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

20.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

20.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

20.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

Chapter 21

Serial Peripheral Interface (S12SPIV5)

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

21.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

21.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

21.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

21.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

21.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

21.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

21.2.3

21.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

21.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

21.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

21.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

21.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

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21.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

21.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

21.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728

21.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729

Chapter 22

Timer Module (TIM16B6CV3)

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

22.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734

22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

22.2.1 IOC5 - IOC0 — Input Capture and Output Compare Channel 5-0 . . . . . . . . . . . . . . . . 735

22.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747

22.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748

22.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

22.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

22.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

22.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

22.6.1 Channel [5:0] Interrupt (C[5:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

22.6.2 Timer Overﬂow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

Chapter 23

Timer Module (TIM16B8CV3)

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

23.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

23.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

23.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

23.2.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 755

23.2.2 IOC6 - IOC0 — Input Capture and Output Compare Channel 6-0 . . . . . . . . . . . . . . . . 755

23.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

23.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

23.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756

23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

23.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

23.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

23.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

23.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775

23.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

23.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

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23.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

23.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

23.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

23.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

23.6.3 Pulse Accumulator Overﬂow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

23.6.4 Timer Overﬂow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

Chapter 24

16 KByte Flash Module (S12FTMRG16K1V1)

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

24.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780

24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780

24.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781

24.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782

24.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

24.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

24.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786

24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

24.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

24.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

24.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

24.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

24.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 808

24.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

24.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

24.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

24.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

24.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

24.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

24.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 825

24.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 826

24.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

Chapter 25

32 KByte Flash Module (S12FTMRG32K1V1)

25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

25.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

25.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

25.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830

25.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831

25.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831

25.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834

25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

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25.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

25.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

25.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854

25.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854

25.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 859

25.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860

25.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874

25.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

25.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

25.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

25.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

25.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 876

25.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 877

25.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877

Chapter 26

48 KByte Flash Module (S12FTMRG48K1V1)

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879

26.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880

26.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880

26.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882

26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882

26.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883

26.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883

26.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887

26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906

26.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906

26.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906

26.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907

26.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907

26.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 912

26.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

26.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927

26.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928

26.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928

26.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928

26.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928

26.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 929

26.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 930

26.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930

Chapter 27

64 KByte Flash Module (S12FTMRG64K1V1)

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931

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27.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932

27.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932

27.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

27.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934

27.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935

27.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935

27.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938

27.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957

27.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957

27.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957

27.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958

27.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958

27.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 963

27.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964

27.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978

27.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979

27.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979

27.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979

27.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979

27.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 980

27.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 981

27.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981

Chapter 28

96 KByte Flash Module (S12FTMRG96K1V1)

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983

28.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984

28.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984

28.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985

28.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986

28.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987

28.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987

28.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990

28.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009

28.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009

28.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009

28.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010

28.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010

28.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1015

28.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016

28.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030

28.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031

28.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031

28.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031

28.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031

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28.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1032

28.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1033

28.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033

Chapter 29

128 KByte Flash Module (S12FTMRG128K1V1)

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035

29.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036

29.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036

29.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037

29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038

29.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039

29.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039

29.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043

29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061

29.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061

29.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061

29.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062

29.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062

29.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1067

29.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068

29.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082

29.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083

29.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083

29.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083

29.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083

29.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1084

29.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1085

29.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085

Chapter 30

192 KByte Flash Module (S12FTMRG192K2V1)

30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087

30.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088

30.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088

30.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089

30.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090

30.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091

30.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091

30.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095

30.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113

30.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113

30.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113

30.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114

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30.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114

30.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1119

30.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120

30.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133

30.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134

30.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134

30.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135

30.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135

30.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1136

30.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1136

30.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136

Chapter 31

240 KByte Flash Module (S12FTMRG240K2V1)

31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139

31.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140

31.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140

31.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141

31.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142

31.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143

31.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143

31.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147

31.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165

31.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165

31.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165

31.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166

31.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166

31.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1171

31.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172

31.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185

31.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186

31.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186

31.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187

31.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187

31.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1188

31.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1188

31.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188

Appendix A

Electrical Characteristics

A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192

A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192

A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192

A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193

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A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193

A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194

A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194

A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195

A.1.8 Power Dissipation and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197

A.2 I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201

A.3 Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205

A.3.1 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205

A.4 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210

A.4.1 ADC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210

A.4.2 Factors Influencing Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211

A.4.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212

A.4.4 ADC Temperature Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222

A.5 ACMP Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222

A.6 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224

A.7 NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225

A.7.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225

A.7.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233

A.8 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234

A.8.1 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234

A.8.2 Electrical Characteristics for the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236

A.9 Electrical Characteristics for the IRC1M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236

A.10 Electrical Characteristics for the Oscillator (XOSCLCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238

A.11 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239

A.12 Electrical Specification for Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240

A.13 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242

A.14 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242

A.15 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243

A.15.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243

A.15.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245

A.16 ADC Conversion Result Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247

Appendix B

Detailed Register Address Map

B.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249

Appendix C

Ordering and Shipping Information

C.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269

Appendix D

Package and Die Information

D.1 100 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272

D.2 64 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275

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D.3 48 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278

D.4 48 QFN Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280

D.5 32 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283

D.6 20 TSSOP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286

D.7 KGD Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289

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Chapter 1 Device Overview MC9S12G-Family

Revision History

Version Number

Rev 0.25 18-Feb-2011 • Added Section 1.14, “Autonomous Clock (ACLK) Conﬁguration”

Rev 0.26 21-Feb-2011 • Updated Table 1-1(added temperatur sensor feature)

Rev 0.27 1-Apr-2011 • Typos and formatting

Rev 0.28 11-May-2011 •

Rev 0.29 10-Jan-2011 • Corrected Figure 1-4

Rev 0.30 10-Feb-2012 • Updated Table 1-5(added mask set 1N75C)

Rev 0.31 15-Mar-2012 • Updated Table 1-1 (added S12GSA devices)

Rev 0.32 07-May-2012 • Updated Section 1.19, “BDM Clock Source Connectivity”

Rev 0.33 27-Sep-2012 • Corrected Figure 1-4

Rev 0.34 25-Jan-2013 Added KGD option for the S12GA192 and the S12GA240

Revision

Date

Description of Changes

• Corrected Figure 1-15

• Corrected Figure 1-10

• Corrected Figure 1-16

• Corrected Figure 1-12

• Typos and formatting

• Updated Section 1.3.14, “Analog-to-Digital Converter Module (ADC)”

• Updated Table 1-38

• Typos and formatting

• Updated Figure 1-1

• Updated Table 1-5 (added S12GA devices)

• Added Section 1.8.2, “S12GNA16 and S12GNA32”

• Added Section 1.8.5, “S12GA48 and S12GA64”

• Added Section 1.8.7, “S12GA96 and S12GA128”

• Typos and formatting

• Corrected Figure 1-5

• Corrected Figure 1-6

• Updated Table 1-1

• Corrected Table 1-2

• Corrected Table 1-6

1.1 Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602

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Device Overview MC9S12G-Family

communication. Typical examples of these applications include body controllers, occupant detection, door modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family, including error correction code (ECC) on ﬂash memory, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance.

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efﬁciencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efﬁciency advantages currently enjoyed by users of Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in 100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and aims to maximize the amount of functionality especially for the lower pin count packages. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes.

1.2 Features

This section describes the key features of the MC9S12G-Family.

1.2.1 MC9S12G-Family Comparison

Table 1-1 provides a summary of different members of the MC9S12G-Family and their features. This

information is intended to provide an understanding of the range of functionality offered by this microcontroller family.

Table 1-1. MC9S12G-Family Overview

Feature

S12GN16

S12GNA16

S12GN32

S12GNA32

S12GN48

S12G48

S12GA48

S12G64

S12GA64

CPU CPU12V1

Flash memory [kBytes]

EEPROM [kBytes] 0.5 0.5 1 1 1.5 1.5 1.5 2233444444

RAM [kBytes] 112244444888811111111

MSCAN ————— 111111111111

SCI 11112222233333333

SPI 11112222233333333

16-Bit Timer channels

16 16 32 32 48 48 48 64 64 96 96 128 128 192 192 240 240

66666666688888888

S12G96

S12GA96

S12G128

S12GA128

S12G192

S12GA192

S12G240

S12GA240

8-Bit PWM channels 66666666688888888

10-Bit ADC channels 8 — 8 — 12 12 — 12 — 12 — 12 — 16 — 16 —

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Device Overview MC9S12G-Family

Table 1-1. MC9S12G-Family Overview

Feature

S12GN16

S12GNA16

S12GN32

S12GNA32

S12GN48

S12G48

S12GA48

S12G64

S12GA64

12-Bit ADC channels — 8 — 8 — — 12 — 12 — 12 — 12 — 16 — 16

Temperature Sensor ——————————————Yes—Yes

RVA ——————————————YES—YES

8-Bit DAC —————————————— 2 — 2

ACMP (analog comparator)

PLL Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

External osc Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Internal 1 MHz RC oscillator

20-pin TSSOP Yes — Yes ——————————————

32-pin LQFP Yes — Yes — Yes Yes — Yes —————————

48-pin LQFP Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

48-pin QFN Yes Yes Yes Yes —————————————

111111111————————

Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s

S12G96

S12GA96

S12G128

S12GA128

S12G192

S12GA192

S12G240

S12GA240

64-pin LQFP ————YesYesYesYesYesYesYesYesYesYesYesYesYes

100-pin LQFP —————————YesYesYesYesYesYesYesYes

KGD ——————————————Yes—Yes

Supply voltage 3.13 V – 5.5 V

Execution speed Static – 25 MHz

Not all peripherals are available in all package types

Table 1-2shows the maximum number of peripherals or peripheral channels per package type. Not all

peripherals are available at the same time. The maximum number of peripherals is also limited by the device chosen as per Table 1-1.

Table 1-2. Maximum Peripheral Availability per Package

Peripheral 20 TSSOP 32 LQFP

MSCAN — Yes Yes Yes Yes Yes

SCI0 Yes Yes Yes Yes Yes Yes

SCI1 — Yes Yes Yes Yes Yes

SCI2 — — Yes Yes Yes Yes

SPI0 Yes Yes Yes Yes Yes Yes

48 LQFP,

48 QFN

64 LQFP 100 LQFP KGD (Die)

SPI1 — — Yes Yes Yes Yes

SPI2 — — — Yes Yes Yes

Timer Channels 4 = 0 … 3 6 = 0 … 5 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7

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Device Overview MC9S12G-Family

Table 1-2. Maximum Peripheral Availability per Package

Peripheral 20 TSSOP 32 LQFP

8-Bit PWM Channels 4 = 0 … 3 6 = 0 … 5 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7

ADC channels 6 = 0 … 5 8 = 0 … 7 12 = 0 … 11 16 = 0 … 15 16 = 0 … 15 16 = 0 … 15

DAC0 — — Yes Yes Yes Yes

DAC1 — — Yes Yes Yes Yes

ACMP Yes Yes Yes Yes — —

Total GPIO 14 26 40 54 86 86

48 LQFP,

48 QFN

64 LQFP 100 LQFP KGD (Die)

1.2.2 Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip ﬂash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal ﬁlter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture, output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter (ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision ﬁxed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy

1.3 Module Features

The following sections provide more details of the modules implemented on the MC9S12G-Family family.

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Device Overview MC9S12G-Family

1.3.1 S12 16-Bit Central Processor Unit (CPU)

S12 CPU is a high-speed 16-bit processing unit:

• Full 16-bit data paths supports efﬁcient arithmetic operation and high-speed math execution

• Includes many single-byte instructions. This allows much more efﬁcient use of ROM space.

• Extensive set of indexed addressing capabilities, including: — Using the stack pointer as an indexing register in all indexed operations — Using the program counter as an indexing register in all but auto increment/decrement mode — Accumulator offsets using A, B, or D accumulators — Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)

1.3.2 On-Chip Flash with ECC

On-chip ﬂash memory on the MC9S12G-Family family features the following:

• Up to 240 Kbyte of program ﬂash memory — 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection — Erase sector size 512 bytes — Automated program and erase algorithm — User margin level setting for reads — Protection scheme to prevent accidental program or erase

• Up to 4 Kbyte EEPROM — 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection — Erase sector size 4 bytes — Automated program and erase algorithm — User margin level setting for reads

1.3.3 On-Chip SRAM

• Up to 11 Kbytes of general-purpose RAM

1.3.4 Port Integration Module (PIM)

• Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used as general-purpose I/O

• Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J and AD on per-pin basis

• Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis and on BKGD pin

• Control registers to enable/disable open-drain (wired-or) mode on ports S and M

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Device Overview MC9S12G-Family

• Interrupt ﬂag register for pin interrupts on ports P, J and AD

• Control register to conﬁgure

IRQ pin operation

• Routing register to support programmable signal redirection in 20 TSSOP only

• Routing register to support programmable signal redirection in 100 LQFP package only

• Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram routing of API_EXTCLK in all packages.

• Control register for free-running clock outputs

•

1.3.5 Main External Oscillator (XOSCLCP)

• Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals — Oscillator pins can be shared w/ GPIO functionality

1.3.6 Internal RC Oscillator (IRC)

• Trimmable internal reference clock. — Frequency: 1 MHz — Trimmed accuracy over –40˚C to +125˚C ambient temperature range:

±1.0% for temperature option C and V (see Table A-4) ±1.3% for temperature option M (see Table A-4)

1.3.7 Internal Phase-Locked Loop (IPLL)

• Phase-locked-loop clock frequency multiplier — No external components required — Reference divider and multiplier allow large variety of clock rates — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Conﬁgurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources:

– External 4–16 MHz resonator/crystal (XOSCLCP) – Internal 1 MHz RC oscillator (IRC)

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Device Overview MC9S12G-Family

1.3.8 System Integrity Support

• Power-on reset (POR)

• System reset generation

• Illegal address detection with reset

• Low-voltage detection with interrupt or reset

• Real time interrupt (RTI)

• Computer operating properly (COP) watchdog — Conﬁgurable as window COP for enhanced failure detection — Initialized out of reset using option bits located in ﬂash memory

• Clock monitor supervising the correct function of the oscillator

1.3.9 Timer (TIM)

• Up to eight x 16-bit channels for input capture or output compare

• 16-bit free-running counter with 7-bit precision prescaler

• In case of eight channel timer Version an additional 16-bit pulse accumulator is available

1.3.10 Pulse Width Modulation Module (PWM)

• Up to eight channel x 8-bit or up to four channel x 16-bit pulse width modulator — Programmable period and duty cycle per channel — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies

1.3.11 Controller Area Network Module (MSCAN)

• 1 Mbit per second, CAN 2.0 A, B software compatible — Standard and extended data frames — 0–8 bytes data length — Programmable bit rate up to 1 Mbps

• Five receive buffers with FIFO storage scheme

• Three transmit buffers with internal prioritization

• Flexible identiﬁer acceptance ﬁlter programmable as: — 2 x 32-bit — 4 x 16-bit — 8 x 8-bit

• Wakeup with integrated low pass ﬁlter option

• Loop back for self test

• Listen-only mode to monitor CAN bus

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Device Overview MC9S12G-Family

• Bus-off recovery by software intervention or automatically

• 16-bit time stamp of transmitted/received messages

1.3.12 Serial Communication Interface Module (SCI)

• Up to three SCI modules

• Full-duplex or single-wire operation

• Standard mark/space non-return-to-zero (NRZ) format

• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

• 13-bit baud rate selection

• Programmable character length

• Programmable polarity for transmitter and receiver

• Active edge receive wakeup

• Break detect and transmit collision detect supporting LIN 1.3, 2.0, 2.1 and SAE J2602

1.3.13 Serial Peripheral Interface Module (SPI)

• Up to three SPI modules

• Conﬁgurable 8- or 16-bit data size

• Full-duplex or single-wire bidirectional

• Double-buffered transmit and receive

• Master or slave mode

• MSB-ﬁrst or LSB-ﬁrst shifting

• Serial clock phase and polarity options

1.3.14 Analog-to-Digital Converter Module (ADC)

Up to 16-channel, 10-bit/12-bit1 analog-to-digital converter

— 3 us conversion time

— 8-/10 — Left or right justiﬁed result data — Wakeup from low power modes on analog comparison > or <= match — Continuous conversion mode — External triggers to initiate conversions via GPIO or peripheral outputs such as PWM or TIM — Multiple channel scans — Precision ﬁxed voltage reference for ADC conversions

-bit resolution

—

• Pins can also be used as digital I/O including wakeup capability

1. 12-bit resolution only available on S12GA192 and S12GA240 devices.

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Device Overview MC9S12G-Family

1.3.15 Reference Voltage Attenuator (RVA)

• Attenuation of ADC reference voltage with low long-term drift

1.3.16 Digital-to-Analog Converter Module (DAC)

• 1 digital-analog converter channel (per module) with: — 8 bit resolution — full and reduced output voltage range — buffered or unbuffered analog output voltage usable

• operational ampliﬁer stand alone usable

1.3.17 Analog Comparator (ACMP)

• Low offset, low long-term offset drift

• Selectable interrupt on rising, falling, or rising and falling edges of comparator output

• Option to output comparator signal on an external pin

• Option to trigger timer input capture events

1.3.18 On-Chip Voltage Regulator (VREG)

• Linear voltage regulator with bandgap reference

• Low-voltage detect (LVD) with low-voltage interrupt (LVI)

• Power-on reset (POR) circuit

• Low-voltage reset (LVR)

1.3.19 Background Debug (BDM)

• Non-intrusive memory access commands

• Supports in-circuit programming of on-chip nonvolatile memory

1.3.20 Debugger (DBG)

• Trace buffer with depth of 64 entries

• Three comparators (A, B and C) — Access address comparisons with optional data comparisons — Program counter comparisons — Exact address or address range comparisons

• Two types of comparator matches — Tagged This matches just before a speciﬁc instruction begins execution — Force This is valid on the ﬁrst instruction boundary after a match occurs

• Four trace modes

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Device Overview MC9S12G-Family

• Four stage state sequencer

1.4 Key Performance Parameters

The key performance parameters of S12G devices feature:

• Continuous Operating voltage of 3.15 V to 5.5 V

• Operating temperature (T

• Junction temperature (T

• Bus frequency (f

) of dc to 25 MHz

Bus

• Packaging: — 100-pin LQFP, 0.5 mm pitch, 14 mm x 14 mm outline — 64-pin LQFP, 0.5 mm pitch, 10 mm x 10 mm outline — 48-pin LQFP, 0.5 mm pitch, 7 mm x 7 mm outline — 48-pin QFN, 0.5 mm pitch, 7 mm x 7 mm outline — 32-pin LQFP, 0.8 mm pitch, 7 mm x 7 mm outline — 20 TSSOP, 0.65 mm pitch, 4.4 mm x 6.5 mm outline — Known good die (KGD), unpackaged

) of –40˚C to 125˚C

) of up to 150˚C

1.5 Block Diagram

Figure 1-1 shows a block diagram of the MC9S12G-Family.

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Device Overview MC9S12G-Family

PE0

PE1

PA[7:0]

PB[7:0]

PC[7:0]

PD[7:0]

VDDR

VSS

BKGD

RESET

TEST

16K … 240K bytes Flash with ECC

1K … 11K bytes RAM

0.5K … 4K bytes EEPROM with ECC

Voltage Regulator

Input: 3.13V – 5.5V

CPU12-V1

Single-wire Background

Debug Module

EXTAL

Low Power Pierce

PTE

PTA

Oscillator

XTAL

PLL with Frequency

Modulation option

Reset Generation

and Test Entry

3-5V IO Supply VDDX1/VSSX1

VDDX2/VSSX2 VDDX3/VSSX3

PTB

PTC

DACU AMPM AMP AMPP

DAC1

Digital-Analog

Converter

PTD

Debug Module 3 comparators

64 Byte Trace Buffer

Clock Monitor

COP Watchdog Real Time Interrupt Auton. Periodic Int.

Internal RC Oscillator

Interrupt Module

ACMP

Analog Comparator

DAC0

ADC 12-bit or 10-bit

8...16 ch. Analog-Digital Converter

Digital-Analog Converter

TIM

16-bit 6 … 8 channel Timer

PWM

8-bit 6 … 8 channel Pulse Width Modulator

CAN msCAN 2.0B SCI2 Asynchronous Serial IF

SCI0 Asynchronous Serial IF SCI1 Asynchronous Serial IF

SPI0

Synchronous Serial IF

SPI1

Synchronous Serial IF

SPI2

Synchronous Serial IF

AN[15:0]

IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7

PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6

PWM7

RXCAN

TXCAN

RXD

TXD

RXD

TXD

RXD

TXD MISO MOSI

SCK

MISO MOSI

SCK

SS MISO MOSI

SCK

VDDA VSSA VRH

RVA

PAD[15:0]

PTAD

(WU Int)

PT0 PT1 PT2 PT3 PT4

PTT

PT5 PT6 PT7

PP0 PP1 PP2 PP3 PP4 PP5 PP6

PTP (Wake-up Int)

PP7

PM0 PM1 PM2

PTM

PM3

PS0 PS1 PS2 PS3 PS4

PTS

PS5 PS6 PS7

PJ0 PJ1 PJ2 PJ3 PJ4 PJ5

PJ6

PTJ (Wake-up Int)

PJ7

Not all pins or all peripherals are available on all devices and packages.

Block Diagram shows the maximum configuration!

Rerouting options are not shown.

Figure 1-1. MC9S12G-Family Block Diagram

1.6 Family Memory Map

Table 1-3 shows the MC9S12G-Family register memory map.

Table 1-3. Device Register Memory Map

Address Module

0x0000–0x0009 PIM (Port Integration Module

) 10

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Size

(Bytes)

Device Overview MC9S12G-Family

Address Module

Size

(Bytes)

0x000A–0x000B MMC (Memory Map Control) 2

0x000C–0x000D PIM (Port Integration Module) 2

0x000E–0x000F Reserved 2

0x0010–0x0017 MMC (Memory Map Control) 8

0x0018–0x0019 Reserved 2

0x001A–0x001B Device ID register 2

0x001C–0x001F PIM (Port Integration Module) 4

0x0020–0x002F DBG (Debug Module) 16

0x0030–0x0033 Reserved 4

0x0034–0x003F CPMU (Clock and Power Management) 12

0x0040–0x006F TIM (Timer Module <= 8 channels) 48

0x0070–0x009F ADC (Analog to Digital Converter <= 16 channels) 48

0x00A0–0x00C7 PWM (Pulse-Width Modulator <= 8 channels) 40

0x00C8–0x00CF SCI0 (Serial Communication Interface) 8

0x00D0–0x00D7 SCI1 (Serial Communication Interface)

0x00D8–0x00DF SPI0 (Serial Peripheral Interface) 8

0x00E0–0x00E7 Reserved 8

0x00E8–0x00EF SCI2 (Serial Communication Interface)

0x00F0–0x00F7 SPI1 (Serial Peripheral Interface)

0x00F8–0x00FF SPI2 (Serial Peripheral Interface)

0x0100–0x0113 FTMRG control registers 20

0x0114–0x011F Reserved 12

0x0120 INT (Interrupt Module) 1

0x0121–0x013F Reserved 31

0x0140–0x017F CAN

0x0180–0x023F Reserved 192

0x0240–0x025F PIM (Port Integration Module) 32

0x0260–0x0261 ACMP (Analog Comparator)

0x0262–0x0275 PIM (Port Integration Module) 20

0x0276 RVA (Reference Voltage Attenuator)

0x0277–0x027F PIM (Port Integration Module) 9

0x0280–0x02EF Reserved 112

0x02F0–0x02FF CPMU (Clock and Power Management) 16

0x0300–0x03BF Reserved 192

0x03C0–0x03C7 DAC0 (Digital to Analog Converter)

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Device Overview MC9S12G-Family

Address Module

0x03C8–0x03CF DAC1 (Digital to Analog Converter)

0x03D0–0x03FF Reserved 48

The SCI1 is not available on the S12GN8, S12GN16, S12GN32, and S12GN32 devices

The SCI2 is not available on the S12GN8, S12GN16, S12GN32, S12GN32, S12G48, and S12G64 devices

The SPI1 is not available on the S12GN8, S12GN16, S12GN24, and S12GN32 devices

The SPI2 is not available on the S12GN8, S12GN16, S12GN32, S12GN32, S12G48, and S12G64 devices

The CAN is not available on the S12GN8, S12GN16, S12GN24, S12GN32, and S12GN48 devices

The ACMP is only available on the S12GN8, S12GN16, S12GN24, S12GN32, S12GN48,S12GN48, S12G48, and S12G64 devices

The RVA is only available on the S12GA192 and S12GA240 devices

DAC0 and DAC1 are only available on the S12GA192 and S12GA240 devices

Size

(Bytes)

NOTE

Reserved register space shown in Table 1-3 is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect. Read access to these locations returns zero.

Figure 1-2 shows S12G CPU and BDM local address translation to the global memory map as a graphical

representation. In conjunction Table 1-4 shows the address ranges and mapping to 256K global memory space for P-Flash, EEPROM and RAM. The whole 256K global memory space is visible through the P-Flash window located in the 64k local memory map located at 0x8000 - 0xBFFF using the PPAGE register.

Table 1-4. MC9S12G-Family Memory Parameters

Feature S12GN16 S12GN32

P-Flash size 16KB 32KB 48KB 64KB 96KB 128KB 192KB 240KB

PF_LOW 0x3C000 0x38000 0x34000 0x30000 0x28000 0x20000 0x10000 0x04000

PF_LOW_UNP (unpaged)

PPAGES

EEPROM [Bytes]

EEPROM_HI 0x05FF 0x07FF 0x09FF 0x0BFF 0x0FFF 0x13FF 0x13FF 0x13FF

0xC000 0x8000 0x4000 —————

0x0E -

0x0F

512 1024 1536 2048 3072 4096 4096 4096

0x0F

S12G48

S12GN48

0x0D -

0x0F

S12G64 S12G96 S12G128

0x0C -

0x0F

0x0A -

0x0F

0x08 -

0x0F

S12G192

S12GA192

0x04 -

0x0F

S12G240

S12GA240

0x01 -

0x0F

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Device Overview MC9S12G-Family

Table 1-4. MC9S12G-Family Memory Parameters

Feature S12GN16 S12GN32

S12G48

S12GN48

S12G64 S12G96 S12G128

S12G192

S12GA192

S12G240

S12GA240

RAM [Bytes] 1024 2048 4096 4096 8192 8192 11264 11264

RAM_LOW 0x3C00 0x3800 0x3000 0x3000 0x2000 0x2000 0x1400 0x1400

Unpaged Flash space left

Unpaged Flash

While for memory sizes <64K the whole 256k space could be addressed using the PPAGE, it is more efﬁcient to use

— — — 0x0C00-

0x2FFF

— — — 9KB 4KB 3KB — —

0x1000-

0x1FFF

0x1400-

0x1FFF

——

an unpaged memory model

Page 0xC

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0x0000 0x0400

Local CPU and BDM

Memory Map Global Memory Map

EEPROM

Flash Space

Page 0xC

EEPROM

Unimplemented

Device Overview MC9S12G-Family

0x0_0000 0x0_0400

0x4000

0x8000

0xC000

0xFFFF

RAM

Flash Space

Page 0xD

Paging Window

Flash Space

Page 0xF

RAM

NVMRES=0

Flash

Space

Page 0x1

Flash Space

Page 0x2

Flash Space

Page 0xC

Flash Space

Page 0xD

NVMRES=1

Internal

NVM

Resources

0x0_4000

0x0_8000

0x3_0000

0x3_4000

0x3_8000

Flash Space

Page 0xE

0x3_C000

Flash Space

Page 0xF

0x3_FFFF

Figure 1-2. MC9S12G Global Memory Map

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1.6.1 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the assigned part ID number and Mask Set number.

Table 1-5. Assigned Part ID Numbers

Device Mask Set Number Part ID

MC9S12GA240 0N95B 0xF080

MC9S12G240 0N95B 0xF080

MC9S12GA192 0N95B 0xF080

MC9S12G192 0N95B 0xF080

MC9S12GA128 0N51A 0xF180

MC9S12G128 0N51A 0xF180

MC9S12GA96 0N51A 0xF180

MC9S12G96 0N51A 0xF180

MC9S12GA64 0N75C 0xF280

MC9S12G64

0N75C

1N75C

MC9S12GA48 0N75C 0xF280

MC9S12G48

MC9S12GN48

0N75C

1N75C

0N75C

1N75C

MC9S12GNA32 0N48A 0xF380

MC9S12GN32

0N48A

1N48A

MC9S12GNA16 0N48A 0xF380

MC9S12GN16

Only available in 48-pin LQFP and 64-pin LQFP

Only available in 32-pin LQFP

Only available in 48-pin LQFP and 48-pin QFN

Only available in 20-pin TSSOP and 32-pin LQFP

0N48A

1N48A

0xF280

0xF281

0xF280

0xF281

0xF280

0xF281

0xF380

0xF381

0xF380

0xF381

1.7 Signal Description and Device Pinouts

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the individual IP blocks on the device.

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1.7.1 Pin Assignment Overview

Table 1-6 provides a summary of which ports are available for each package option.

Table 1-6. Port Availability by Package Option

Port 20 TSSOP 32 LQFP

Port AD/ADC Channels 6 8 12 16 16 16

Port A pins 000088

Port B pins 000088

Port C pins 000088

Port D pins 000088

Port E pins 222222

Port J 004888

Port M 022444

Port P 046888

Port S 468888

Port T 246888

Sum of Ports 14 26 40 54 86 86

I/O Power Pairs VDDX/VSSX 1/1 1/1 1/1 1/1 3/3 3/3

48 LQFP

48 QFN

64 LQFP 100 LQFP KGD (Die)

NOTE

To avoid current drawn from ﬂoating inputs, the input buffers of all non-bonded pins are disabled.

1.7.2 Detailed Signal Descriptions

This section describes the signal properties. The relation between signals and package pins is described in section 1.8 Device Pinouts.

1.7.2.1 RESET — External Reset Signal

The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The an internal pull-up device.

1.7.2.2 TEST — Test Pin

This input only pin is reserved for factory test. This pin has an internal pull-down device.

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NOTE

The TEST pin must be tied to ground in all applications.

1.7.2.3 BKGD / MODC — Background Debug and Mode Pin

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of

RESET. The BKGD pin has an internal pull-up device.

1.7.2.4 EXTAL, XTAL — Oscillator Signal

EXTAL and XTAL are the crystal driver and external clock signals. On reset all the device clocks are derived from the internal reference clock. XTAL is the oscillator output.

1.7.2.5 PAD[15:0] / KWAD[15:0] — Port AD Input Pins of ADC

PAD[15:0] are general-purpose input or output signals. These signals can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled.

1.7.2.6 PA[7:0] — Port A I/O Signals

PA[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled .

1.7.2.7 PB[7:0] — Port B I/O Signals

PB[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled .

1.7.2.8 PC[7:0] — Port C I/O Signals

PC[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled .

1.7.2.9 PD[7:0] — Port D I/O Signals

PD[7:0] are general-purpose input or output signals. The signals can have pull-up device, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled.

1.7.2.10 PE[1:0] — Port E I/O Signals

PE[1:0] are general-purpose input or output signals. The signals can have pull-down device, enabled by a single control bit for this signal group. Out of reset the pull-down devices are enabled.

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1.7.2.11 PJ[7:0] / KWJ[7:0] — Port J I/O Signals

PJ[7:0] are general-purpose input or output signals. The signals can be conﬁgured on per signal basis as interrupt inputs with wakeup capability (KWJ[7:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are enabled .

1.7.2.12 PM[3:0] — Port M I/O Signals

PM[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled. The signals can be conﬁgured on per pin basis to open-drain mode.

1.7.2.13 PP[7:0] / KWP[7:0] — Port P I/O Signals

PP[7:0] are general-purpose input or output signals. The signals can be conﬁgured on per signal basis as interrupt inputs with wakeup capability (KWP[7:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled .

1.7.2.14 PS[7:0] — Port S I/O Signals

PS[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull-up devices are enabled. The signals can be conﬁgured on per pin basis in open-drain mode.

1.7.2.15 PT[7:0] — Port TI/O Signals

PT[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled .

1.7.2.16 AN[15:0] — ADC Input Signals

AN[15:0] are the analog inputs of the Analog-to-Digital Converter.

1.7.2.17 ACMP Signals

1.7.2.17.1 ACMPP — Non-Inverting Analog Comparator Input

ACMPP is the non-inverting input of the analog comparator.

1.7.2.17.2 ACMPM — Inverting Analog Comparator Input

ACMPM is the inverting input of the analog comparator.

1.7.2.17.3 ACMPO — Analog Comparator Output

ACMPO is the output of the analog comparator.

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1.7.2.18 DAC Signals

1.7.2.18.1 DACU[1:0] Output Pins

These analog pins is used for the unbuffered analog output Voltages from the DAC0 and the DAC1 resistor network output, when the according mode is selected.

1.7.2.18.2 AMP[1:0] Output Pins

These analog pins are used for the buffered analog outputs Voltage from the operational ampliﬁer outputs, when the according mode is selected.

1.7.2.18.3 AMPP[1:0] Input Pins

These analog input pins areused as input signals for the operational ampliﬁers positive input pins when the according mode is selected.

1.7.2.18.4 AMPM[1:0] Input Pins

These analog input pins are used as input signals for the operational ampliﬁers negative input pin when the according mode is selected.

1.7.2.19 SPI Signals

1.7.2.19.1 SS[2:0] Signals

Those signals are associated with the slave select SS functionality of the serial peripheral interfaces SPI2-0.

1.7.2.19.2 SCK[2:0] Signals

Those signals are associated with the serial clock SCK functionality of the serial peripheral interfaces SPI2-0.

1.7.2.19.3 MISO[2:0] Signals

Those signals are associated with the MISO functionality of the serial peripheral interfaces SPI2-0. They act as master input during master mode or as slave output during slave mode.

1.7.2.19.4 MOSI[2:0] Signals

Those signals are associated with the MOSI functionality of the serial peripheral interfaces SPI2-0. They act as master output during master mode or as slave input during slave mode.

1.7.2.20 SCI Signals

1.7.2.20.1 RXD[2:0] Signals

Those signals are associated with the receive functionality of the serial communication interfaces SCI2-0.

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1.7.2.20.2 TXD[2:0] Signals

Those signals are associated with the transmit functionality of the serial communication interfaces SCI2-0.

1.7.2.21 CAN signals

1.7.2.21.1 RXCAN Signal

This signal is associated with the receive functionality of the scalable controller area network controller (MSCAN).

1.7.2.21.2 TXCAN Signal

This signal is associated with the transmit functionality of the scalable controller area network controller (MSCAN).

1.7.2.22 PWM[7:0] Signals

The signals PWM[7:0] are associated with the PWM module outputs.

1.7.2.23 Internal Clock outputs

1.7.2.23.1 ECLK

This signal is associated with the output of the divided bus clock (ECLK).

NOTE

This feature is only intended for debug purposes at room temperature. It must not be used for clocking external devices in an application.

1.7.2.23.2 ECLKX2

This signal is associated with the output of twice the bus clock (ECLKX2).

NOTE

This feature is only intended for debug purposes at room temperature. It must not be used for clocking external devices in an application.

1.7.2.23.3 API_EXTCLK

This signal is associated with the output of the API clock (API_EXTCLK).

1.7.2.24 IOC[7:0] Signals

The signals IOC[7:0] are associated with the input capture or output compare functionality of the timer (TIM) module.

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1.7.2.25 IRQ

This signal is associated with the maskable IRQ interrupt.

1.7.2.26 XIRQ

This signal is associated with the non-maskable XIRQ interrupt.

1.7.2.27 ETRIG[3:0]

These signals are inputs to the Analog-to-Digital Converter. Their purpose is to trigger ADC conversions.

1.7.3 Power Supply Pins

MC9S12G power and ground pins are described below. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible.

NOTE

All ground pins must be connected together in the application.

1.7.3.1 VDDX[3:1]/VDDX, VSSX[3:1]/VSSX— Power and Ground Pins for I/O Drivers

External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded. All VDDX pins are connected together internally. All VSSX pins are connected together internally.

NOTE

Not all VDDX[3:1]/VDDX and VSSX[3:1]VSSX pins are available on all packages. Refer to section 1.8 Device Pinouts for further details.

1.7.3.2 VDDR — Power Pin for Internal Voltage Regulator

Power supply input to the internal voltage regulator.

NOTE

On some packages VDDR is bonded to VDDX and the pin is named VDDXR. Refer to section 1.8 Device Pinouts for further details.

1.7.3.3 VSS — Core Ground Pin

The voltage supply of nominally 1.8V is derived from the internal voltage regulator. The return current path is through the VSS pin.

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1.7.3.4 VDDA, VSSA — Power Supply Pins for DAC,ACMP, RVA, ADC and Voltage Regulator

These are the power supply and ground input pins for the digital-to-analog converter, the analog comparator, the reference voltage attenuator, the analog-to-digital converter and the voltage regulator.

NOTE

On some packages VDDA is connected with VDDXR and the common pin is named VDDXRA. On some packages the VSSA is connected to VSSX and the common pin is named VSSXA. See section Section 1.8, “Device Pinouts” for further details.

1.7.3.5 VRH — Reference Voltage Input Pin

VRH is the reference voltage input pin for the digital-to-analog converter and the analog-to-digital converter. Refer to Section 1.18, “ADC VRH/VRL Signal Connection” for further details.

On some packages VRH is tied to VDDA or VDDXRA. Refer to section 1.8

Device Pinouts for further details.

1.7.3.6 Power and Ground Connection Summary

Table 1-7. Power and Ground Connection Summary

Mnemonic Nominal Voltage Description

VDDR 3.15V – 5.0 V External power supply for internal voltage regulator.

VSS 0V Return ground for the logic supply generated by the internal regulator

VDDX

[3:1]

VSSX

[3:1]

VDDX 3.15V – 5.0 V External power supply for I/O drivers, All packages except 100-pin feature 1 I/O supply.

VSSX 0V Return ground for I/O drivers. All packages except 100-pin provide 1 I/O ground pin.

VDDA 3.15V – 5.0 V External power supply for the analog-to-digital converter and for the reference circuit of the

VSSA 0V Return ground for VDDA analog supply

VDDXR 3.15V – 5.0 V External power supply for I/O drivers and internal voltage regulator. For the 48-pin package

VDDXRA 3.15V – 5.0 V External power supply for I/O drivers, internal voltage regulator and analog-to-digital

VSSXA 0V Return ground for I/O driver and VDDA analog supply

VRH 3.15V – 5.0 V Reference voltage for the analog-to-digital converter.

3.15V – 5.0 V External power supply for I/O drivers. The 100-pin package features 3 I/O supply pins.

0V Return ground for I/O drivers. The100-pin package provides 3 ground pins

internal voltage regulator.

the VDDX and VDDR supplies are combined on one pin.

converter. For the 20- and 32-pin package the VDDX, VDDR and VDDA supplies are combined on one pin.

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1.8 Device Pinouts

1.8.1 S12GN16 and S12GN32

1.8.1.1 Pinout 20-Pin TSSOP

SS0/TXD0/PWM3/ECLK/API_EXTCLK/ETRIG3/PS7

SCK0/IOC3/PS6

RESET

VRH/VDDXRA

VSSXA

EXTAL/RXD0/PWM0/IOC2/ETRIG0/PE0

VSS

XTAL/TXD0/PWM1/IOC3/ETRIG1/PE1

TEST

BKGD

1 2 3 4 5 6 7 8 9

S12GN16 S12GN32

20-Pin TSSOP

PS5/IOC2/MOSI0

PS4/ETRIG2/PWM2/RXD0/MISO0

PAD5/KWAD5/ETRIG3/PWM3/IOC3/TXD0/AN5/ACMPM

PAD4/KWAD4/ETRIG2/PWM2/IOC2/RXD0/AN4/ACMPP

PAD3/KWAD3/AN3/ACMPO

PAD2/KWAD2/AN2

PAD1/KWAD1/AN1

PAD0/KWAD0/AN0

PT0/IOC0/XIRQ

PT1/IOC1/IRQ

Figure 1-3. 20-Pin TSSOP Pinout for S12GN16 and S12GN32

Table 1-8. 20-Pin TSSOP Pinout for S12GN16 and S12GN32

Function

<----lowest-----PRIORITY-----highest---->

Package

2nd

Func.

3rd

Func.

4th

Func

5th

Func

6th

Func

7th

Func

8th

Func

1 PS6 IOC3 SCK0 — — — — — V

2 PS7 ETRIG3 API_EXTCLK ECLK PWM3 TXD0

SS0 — V

3 RESET — — — — — — — V

Power

Supply

DDX

4 VDDXRA VRH — — — — — — — — —

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PULLUP

Reset

State

5 VSSXA — — — — — — — — — —

6 PE0

ETRIG0 PWM0 IOC2 RXD0 EXTAL — — V

DDX

PUCR/PDPEE Down

7 VSS — — — — — — — — — —

8 PE1

9 TEST — — — — — — — N.A.

10 BKGD MODC — — — — — — V

11 PT1 IOC1

12 PT0 IOC0

13 PAD0 KWAD0 AN0 — — — — — V

14 PAD1 KWAD1 AN1 — — — — — V

15 PAD2 KWAD2 AN2 — — — — — V

ETRIG1 PWM1 IOC3 TXD0 XTAL — — PUCR/PDPEE Down

RESET pin Down

Always on Up

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

IRQ — — — — — V

XIRQ — — — — — V

DDX

DDA

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Table 1-8. 20-Pin TSSOP Pinout for S12GN16 and S12GN32

Function

<----lowest-----PRIORITY-----highest---->

Package

2nd

Func.

3rd

Func.

4th

Func

5th

Func

6th

Func

7th

Func

8th

Func

16 PAD3 KWAD3 AN3 ACMPO — — — — V

17 PAD4 KWAD4 ETRIG2 PWM2 IOC2 RXD0 AN4 ACMPP V

18 PAD5 KWAD5 ETRIG3 PWM3 IOC3 TXD0 AN5 ACMPM V

19 PS4 ETRIG2 PWM2 RXD0 MISO0 — — — V

20 PS5 IOC2 MOSI0 — — — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDA

DDX

Internal Pull

Resistor

CTRL

Reset

State

PER1AD/PPS1AD Disabled

PERS/PPSS Up

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1.8.1.2 Pinout 32-Pin LQFP

PM1

PM0

PS7/API_EXTCLK/ECLK/PWM5/SS0PS6/IOC5/SCK0

PS5/IOC4/MOSI0

PS4/PWM4/MISO0

PS1/TXD0

PS0/RXD0

RESET

VRH/VDDXRA

VSSXA

EXTAL/PE0

VSS

XTAL/PE1

TEST

BKGD

32313029282726

1 2

S12GN16

s12GN32

4 5

32-Pin LQFP

6 7 8

10111213141516

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

IOC3/PT3

IOC2/PT2

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PAD7/KWAD7/AN7/ACMPM

PAD6/KWAD6/AN6/ACMPP

PAD5/KWAD5/AN5/ACMPO

PAD4/KWAD4/AN4

PAD3/KWAD3/AN3

PAD2/KWAD2/AN2

PAD1/KWAD1/AN1

PAD0/KWAD0/AN0

Figure 1-4. 32-Pin LQFP OPinout for S12GN16 and S12GN32

Table 1-9. 32-Pin LQFP OPinout for S12GN16 and S12GN32

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

2 VDDXRA VRH — — — — — —

3 VSSXA — — — — — — —

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Internal Pull

Resistor

CTRL

PULLUP

Reset

State

Device Overview MC9S12G-Family

Table 1-9. 32-Pin LQFP OPinout for S12GN16 and S12GN32

Package Pin Pin

4 PE0

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

EXTAL — — — — PUCR/PDPEE Down

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

5 VSS — — — — — — —

6 PE1

7 TEST — — — — N.A.

8 BKGD MODC — — — V

9 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

10 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

11 PP2 KWP2 ETRIG2 PWM2 — V

12 PP3 KWP3 ETRIG3 PWM3 — V

13 PT3 IOC3 — — — V

14 PT2 IOC2 — — — V

15 PT1 IOC1

16 PT0 IOC0

17 PAD0 KWAD0 AN0 — — V

18 PAD1 KWAD1 AN1 — — V

19 PAD2 KWAD2 AN2 — — V

20 PAD3 KWAD3 AN3 — — V

21 PAD4 KWAD4 AN4 — — V

22 PAD5 KWAD5 AN5 ACMPO — V

23 PAD6 KWAD6 AN6 ACMPP — V

24 PAD7 KWAD7 AN7 ACMPM — V

25 PS0 RXD0 — — — V

26 PS1 TXD0 — — — V

27 PS4 PWM4 MISO0 — — V

28 PS5 IOC4 MOSI0 — — V

29 PS6 IOC5 SCK0 — — V

30 PS7 API_EXTCLK ECLK PWM5

31 PM0 — — — — V

32 PM1 — — — — V

XTAL — — — — PUCR/PDPEE Down

RESET pin Down

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PERS/PPSS Up

PERM/PPSM Disabled

IRQ — — V

XIRQ — — V

SS0 V

DDX

DDA

DDX

Reset

State

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The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

1.8.1.3 Pinout 48-Pin LQFP/QFN

PM1

PM0

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3

PS2

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST KWJ0/PJ0 KWJ1/PJ1 KWJ2/PJ2 KWJ3/PJ3

BKGD

4847464544434241403938

1 2 3 4 5 6 7 8

9 10 11 12

S12GN16 S12GN32

48-Pin LQFP/QFN

1314151617181920212223

IOC5/PT5

IOC4/PT4

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

IOC3/PT3

IOC2/PT2

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PAD7/KWAD7/AN7

PAD6/KWAD6/AN6

PAD5/KWAD5/AN5

PAD4/KWAD4/AN4

PAD11/KWAD11/ACMPM

PAD3/KWAD3/AN3

PAD10/KWAD10/ACMPP

PAD2/KWAD2/AN2

PAD9/KWAD9/ACMPO

PAD1/KWAD1/AN1

PAD8/KWAD8

PAD0/KWAD0/AN0

Figure 1-5. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32

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Table 1-10. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PULLUP

2 VDDXR — — — — — — —

3 VSSX — — — — — — —

4 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5 VSS — — — — — — —

6 PE1

7 TEST — — — — N.A.

8 PJ0 KWJ0 — — — V

9 PJ1 KWJ1 — — — V

10 PJ2 KWJ2 — — — V

11 PJ3 KWJ3 — — — V

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1

24 PT0 IOC0

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 — — — V

27 PAD1 KWAD1 AN1 — — V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

IRQ — — V

XIRQ — — V

DDX

DDA

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 67

Device Overview MC9S12G-Family

Table 1-10. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PAD9 KWAD9 ACMPO — — V

29 PAD2 KWAD2 AN2 — — V

30 PAD10 KWAD10 ACMPP V

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 — — — — V

42 PS3 — — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLK ECLK

SS0 — V

47 PM0 — — — — V

48 PM1 — — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERS/PPSS Up

PERM/PPSM Disabled

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

68 Freescale Semiconductor

1.8.2 S12GNA16 and S12GNA32

1.8.2.1 Pinout 48-Pin LQFP/QFN

PM1

PM0

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3

PS2

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

Device Overview MC9S12G-Family

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST KWJ0/PJ0 KWJ1/PJ1 KWJ2/PJ2 KWJ3/PJ3

BKGD

4847464544434241403938

1 2 3 4 5 6 7 8

9 10 11 12

S12GNA16 S12GNA32

48-Pin LQFP/QFN

1314151617181920212223

IOC5/PT5

IOC4/PT4

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

IOC3/PT3

IOC2/PT2

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PAD7/KWAD7/AN7

PAD6/KWAD6/AN6

PAD5/KWAD5/AN5

PAD4/KWAD4/AN4

PAD11/KWAD11/ACMPM

PAD3/KWAD3/AN3

PAD10/KWAD10/ACMPP

PAD2/KWAD2/AN2

PAD9/KWAD9/ACMPO

PAD1/KWAD1/AN1

PAD8/KWAD8

PAD0/KWAD0/AN0

Figure 1-6. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32

Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 69

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

Device Overview MC9S12G-Family

Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

2 VDDXR — — — — — — —

3 VSSX — — — — — — —

4 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5 VSS — — — — — — —

6 PE1

7 TEST — — — — N.A.

8 PJ0 KWJ0 — — — V

9 PJ1 KWJ1 — — — V

10 PJ2 KWJ2 — — — V

11 PJ3 KWJ3 — — — V

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1

24 PT0 IOC0

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 — — — V

27 PAD1 KWAD1 AN1 — — V

28 PAD9 KWAD9 ACMPO — — V

29 PAD2 KWAD2 AN2 — — V

30 PAD10 KWAD10 ACMPP V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

IRQ — — V

XIRQ — — V

DDX

DDA

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

70 Freescale Semiconductor

Device Overview MC9S12G-Family

Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 — — — — V

42 PS3 — — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLK ECLK

SS0 — V

47 PM0 — — — — V

48 PM1 — — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERS/PPSS Up

PERM/PPSM Disabled

Reset

State

1.8.3 S12GN48

1.8.3.1 Pinout 32-Pin LQFP

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 71

Device Overview MC9S12G-Family

PM1/TXD1

PM0/RXD1

PS7/API_EXTCLK/ECLK/PWM5/SS0

PS6/IOC5/SCK0

PS5/IOC4/MOSI0

PS4/PWM4/MISO0

PS1/TXD0

PS0/RXD0

RESET

VRH/VDDXRA

VSSXA

EXTAL/PE0

VSS

XTAL/PE1

TEST

BKGD

32313029282726

1 2

S12GN48

3 4

32-Pin LQFP

5 6 7 8

10111213141516

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

IOC3/PT3

IOC2/PT2

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

24 23 22 21 20 19 18 17

Figure 1-7. 32-Pin LQFP Pinout for S12GN48

PAD7/KWAD7/AN7/ACMPM PAD6/KWAD6/AN6/ACMPP PAD5/KWAD5/AN5/ACMPO PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0

Table 1-12. 32-Pin LQFP Pinout for S12GN48

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

2 VDDXRA VRH — — — — — —

3 VSSXA — — — — — — —

4 PE0

EXTAL — — — — PUCR/PDPEE Down

MC9S12G Family Reference Manual, Rev.1.23

72 Freescale Semiconductor

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

Table 1-12. 32-Pin LQFP Pinout for S12GN48

Device Overview MC9S12G-Family

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

5 VSS — — — — — — —

6 PE1

7 TEST — — — — N.A.

8 BKGD MODC — — — V

9 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

10 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

11 PP2 KWP2 ETRIG2 PWM2 — V

12 PP3 KWP3 ETRIG3 PWM3 — V

13 PT3 IOC3 — — — V

14 PT2 IOC2 — — — V

15 PT1 IOC1

16 PT0 IOC0

17 PAD0 KWAD0 AN0 — — V

18 PAD1 KWAD1 AN1 — — V

19 PAD2 KWAD2 AN2 — — V

20 PAD3 KWAD3 AN3 — — V

21 PAD4 KWAD4 AN4 — — V

22 PAD5 KWAD5 AN5 ACMPO — V

23 PAD6 KWAD6 AN6 ACMPP — V

24 PAD7 KWAD7 AN7 ACMPM — V

25 PS0 RXD0 — — — V

26 PS1 TXD0 — — — V

27 PS4 PWM4 MISO0 — — V

28 PS5 IOC4 MOSI0 — — V

29 PS6 IOC5 SCK0 — — V

30 PS7 API_EXTCLK ECLK PWM5

31 PM0 RXD1 — — — V

32 PM1 TXD1 — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

XTAL — — — — PUCR/PDPEE Down

RESET pin Down

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PERS/PPSS Up

PERM/PPSM Disabled

IRQ — — V

XIRQ — — V

SS0 V

DDX

DDA

DDX

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 73

Device Overview MC9S12G-Family

1.8.3.2 Pinout 48-Pin LQFP

PM1

PM0

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1/KWJ3/PJ3

BKGD

Figure 1-8. 48-Pin LQFP Pinout for S12GN48

4847464544434241403938

1 2 3 4 5 6 7 8

9 10 11 12

S12GN48

48-Pin LQFP

1314151617181920212223

IOC5/PT5

IOC4/PT4

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

IOC3/PT3

IOC2/PT2

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PAD7/KWAD7/AN7

PAD6/KWAD6/AN6

PAD5/KWAD5/AN5

PAD4/KWAD4/AN4

PAD11/KWAD11/AN11/ACMPM

PAD3/KWAD3/AN3

PAD10/KWAD10/AN10/ACMPP

PAD2/KWAD2/AN2

PAD9/KWAD9/AN9/ACMPO

PAD1/KWAD1/AN1

PAD8/KWAD8/AN8

PAD0/KWAD0/AN0

Table 1-13. 48-Pin LQFP Pinout for S12GN48

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

2 VDDXR — — — — — — —

MC9S12G Family Reference Manual, Rev.1.23

74 Freescale Semiconductor

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

Table 1-13. 48-Pin LQFP Pinout for S12GN48

Device Overview MC9S12G-Family

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

3 VSSX — — — — — — —

4 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5 VSS — — — — — — —

6 PE1

7 TEST — — — — N.A.

8 PJ0 KWJ0 MISO1 — — V

9 PJ1 KWJ1 MOSI1 — — V

10 PJ2 KWJ2 SCK1 — — V

11 PJ3 KWJ3 SS1 — — V

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1

24 PT0 IOC0

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 AN8 — — V

27 PAD1 KWAD1 AN1 — — V

28 PAD9 KWAD9 AN9 ACMPO — V

29 PAD2 KWAD2 AN2 — — V

30 PAD10 KWAD10 AN10 ACMPP V

31 PAD3 KWAD3 AN3 — — V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

IRQ — — V

XIRQ — — V

DDX

DDA

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 75

Device Overview MC9S12G-Family

Table 1-13. 48-Pin LQFP Pinout for S12GN48

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

32 PAD11 KWAD11 AN11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 RXD1 — — — V

42 PS3 TXD1 — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLK ECLK

SS0 — V

47 PM0 — — — — V

48 PM1 — — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERS/PPSS Up

PERM/PPSM Disabled

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

76 Freescale Semiconductor

1.8.3.3 Pinout 64-Pin LQFP

PJ7/KWJ7

PM3

PM2

PM1

PM0

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

Device Overview MC9S12G-Family

VDDA

VRH

KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4

RESET

VDDX

VDDR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1/KWJ3/PJ3

BKGD

646362616059585756555453525150

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

171819202122232425262728293031

S12GN48

64-Pin LQFP

PT7

PT6

KWP6/PP6

KWP7/PP7

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

PAD15/KWAD15

PAD7/KWAD7/AN7

PAD14/KWAD14

PAD6/KWAD6/AN6

PAD13/KWAD13

PAD5/KWAD5/AN5

PAD12/KWAD12

PAD4/KWAD4/AN4

PAD11/KWAD11/AN11/ACMPM

PAD3/KWAD3/AN3

PAD10/KWAD10/AN10/ACMPP

PAD2/KWAD2/AN2

PAD9/KWAD9/AN9/ACMPO

PAD1/KWAD1/AN1

PAD8/KWAD8/AN8

PAD0/KWAD0/AN0

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

Figure 1-9. 64-Pin LQFP Pinout for S12GN48

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 77

Device Overview MC9S12G-Family

Table 1-14. 64-Pin LQFP Pinout for S12GN48

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 PJ6 KWJ6 — — — V

2 PJ5 KWJ5 — — — V

3 PJ4 KWJ4 — — — V

4 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERJ/PPSJ Up

PULLUP

5 VDDX — — — — — — —

6 VDDR — — — — — — —

7 VSSX — — — — — — —

8 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

9 VSS — — — — — — —

10 PE1

11 TEST — — — — N.A.

12 PJ0 KWJ0 MISO1 — — V

13 PJ1 KWJ1 MOSI1 — — V

14 PJ2 KWJ2 SCK1 — — V

15 PJ3 KWJ3

16 BKGD MODC — — — V

17 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

19 PP2 KWP2 ETRIG2 PWM2 — V

20 PP3 KWP3 ETRIG3 PWM3 — V

21 PP4 KWP4 PWM4 — — V

22 PP5 KWP5 PWM5 — — V

23 PP6 KWP6 — — V

24 PP7 KWP7 — — V

25 PT7 — — — — V

26 PT6 — — — — V

27 PT5 IOC5 — — — V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

SS1 — — V

DDX

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

78 Freescale Semiconductor

Table 1-14. 64-Pin LQFP Pinout for S12GN48

Device Overview MC9S12G-Family

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PT4 IOC4 — — — V

29 PT3 IOC3 — — — V

30 PT2 IOC2 — — — V

31 PT1 IOC1

32 PT0 IOC0

IRQ — — V

XIRQ — — V

33 PAD0 KWAD0 AN0 — — V

34 PAD8 KWAD8 AN8 — — V

35 PAD1 KWAD1 AN1 — — V

36 PAD9 KWAD9 AN9 ACMPO — V

37 PAD2 KWAD2 AN2 — — V

38 PAD10 KWAD10 AN10 ACMPP — V

39 PAD3 KWAD3 AN3 — — V

40 PAD11 KWAD11 AN11 ACMPM — V

41 PAD4 KWAD4 AN4 — — V

42 PAD12 KWAD12 — — — V

43 PAD5 KWAD5 AN5 — — V

44 PAD13 KWAD13 — — — V

45 PAD6 KWAD6 AN6 — — V

46 PAD14 KWAD14 — — V

47 PAD7 KWAD7 AN7 — — V

48 PAD15 KWAD15 — — V

5th

Power

Supply

DDX

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0ADPPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

Internal Pull

Resistor

CTRL

PERT/PPST Disabled

49 VRH — — — — — — —

Reset

State

50 VDDA — — — — — — —

51 VSSA — — — — — — —

52 PS0 RXD0 — — — V

53 PS1 TXD0 — — — V

54 PS2 RXD1 — — — V

55 PS3 TXD1 — — — V

56 PS4 MISO0 — — — V

DDX

PERS/PPSS Up

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 79

Device Overview MC9S12G-Family

Table 1-14. 64-Pin LQFP Pinout for S12GN48

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

57 PS5 MOSI0 — — — V

58 PS6 SCK0 — — — V

59 PS7 API_EXTCLK ECLK

SS0 — V

60 PM0 — — — — V

61 PM1 — — — — V

62 PM2 — — — — V

63 PM3 — — — — V

64 PJ7 KWJ7 — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDX

PERM/PPSM Disabled

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PERJ/PPSJ Up

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

80 Freescale Semiconductor

1.8.4 S12G48 and S12G64

1.8.4.1 Pinout 32-Pin LQFP

PM1/TXD1/TXCAN

PM0/RXD1/RXCAN

PS7/API_EXTCLK/ECLK/PWM5/SS0

PS6/IOC5/SCK0

PS5/IOC4/MOSI0

PS4/PWM4/MISO0

PS1/TXD0

Device Overview MC9S12G-Family

PS0/RXD0

RESET

VRH/VDDXRA

VSSXA

EXTAL/PE0

VSS

XTAL/PE1

TEST

BKGD

32313029282726

1 2

S12G48

S12G64

4 5

32-Pin LQFP

6 7 8

10111213141516

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

IOC3/PT3

IOC2/PT2

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PAD7/KWAD7/AN7/ACMPM

PAD6/KWAD6/AN6/ACMPP

PAD5/KWAD5/AN5/ACMPO

PAD4/KWAD4/AN4

PAD3/KWAD3/AN3

PAD2/KWAD2/AN2

PAD1/KWAD1/AN1

PAD0/KWAD0/AN0

Figure 1-10. 32-Pin LQFP Pinout for S12G48 and S12G64

Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 81

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

Device Overview MC9S12G-Family

Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

2 VDDXRA VRH — — — — — —

3 VSSXA — — — — — — —

4 PE0

EXTAL — — — — PUCR/PDPEE Down

5 VSS — — — — — — —

6 PE1

7 TEST — — — — N.A.

8 BKGD MODC — — — V

9 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

10 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

11 PP2 KWP2 ETRIG2 PWM2 — V

12 PP3 KWP3 ETRIG3 PWM3 — V

13 PT3 IOC3 — — — V

14 PT2 IOC2 — — — V

15 PT1 IOC1

16 PT0 IOC0

17 PAD0 KWAD0 AN0 — — V

18 PAD1 KWAD1 AN1 — — V

19 PAD2 KWAD2 AN2 — — V

20 PAD3 KWAD3 AN3 — — V

21 PAD4 KWAD4 AN4 — — V

22 PAD5 KWAD5 AN5 ACMPO — V

23 PAD6 KWAD6 AN6 ACMPP — V

24 PAD7 KWAD7 AN7 ACMPM — V

25 PS0 RXD0 — — — V

26 PS1 TXD0 — — — V

27 PS4 PWM4 MISO0 — — V

28 PS5 IOC4 MOSI0 — — V

29 PS6 IOC5 SCK0 — — V

30 PS7 API_EXTCLK ECLK PWM5

XTAL — — — — PUCR/PDPEE Down

RESET pin Down

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PERS/PPSS Up

IRQ — — V

XIRQ — — V

SS0 V

DDX

DDA

DDX

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

82 Freescale Semiconductor

Device Overview MC9S12G-Family

Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

31 PM0 RXD1 RXCAN — — V

32 PM1 TXD1 TXCAN — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERM/PPSM Disabled

1.8.4.2 Pinout 48-Pin LQFP

PM1/TXCAN

PM0/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST

MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1/KWJ3/PJ3

BKGD

4847464544434241403938

1 2 3 4 5 6 7 8

9 10 11 12

S12G48 S12G64

48-Pin LQFP

1314151617181920212223

PAD7/KWAD7/AN7

PAD6/KWAD6/AN6

PAD5/KWAD5/AN5

PAD4/KWAD4/AN4

PAD11/KWAD11/AN11/ACMPM

PAD3/KWAD3/AN3

PAD10/KWAD10/AN10/ACMPP

PAD2/KWAD2/AN2

PAD9/KWAD9/AN9/ACMPO

PAD1/KWAD1/AN1

PAD8/KWAD8/AN8

PAD0/KWAD0/AN0

Reset

State

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ/IOC1/PT1

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

XIRQ/IOC0/PT0

Figure 1-11. 48-Pin LQFP Pinout for S12G48 and S12G64

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 83

Device Overview MC9S12G-Family

Table 1-16. 48-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PULLUP

2 VDDXR — — — — — — —

3 VSSX — — — — — — —

4 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5 VSS — — — — — — —

6 PE1

7 TEST — — — — N.A.

8 PJ0 KWJ0 — MISO1 — V

9 PJ1 KWJ1 — MOSI1 — V

10 PJ2 KWJ2 — SCK1 — V

11 PJ3 KWJ3 —

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1

24 PT0 IOC0

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 AN8 — — V

27 PAD1 KWAD1 AN1 — — V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

SS1 — V

IRQ — — V

XIRQ — — V

DDX

DDA

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

84 Freescale Semiconductor

Device Overview MC9S12G-Family

Table 1-16. 48-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PAD9 KWAD9 AN9 ACMPO — V

29 PAD2 KWAD2 AN2 — — V

30 PAD10 KWAD10 AN10 ACMPP V

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 AN11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 RXD1 — — — V

42 PS3 TXD1 — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLK ECLK

SS0 — V

47 PM0 RXCAN — — — V

48 PM1 TXCAN — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERS/PPSS Up

PERM/PPSM Disabled

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 85

Device Overview MC9S12G-Family

1.8.4.3 Pinout 64-Pin LQFP

PJ7/KWJ7

PM3

PM2

PM1/TXCAN

PM0/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA

VRH

KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4

RESET

VDDX

VDDR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1/KWJ3/PJ3

BKGD

646362616059585756555453525150

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

171819202122232425262728293031

S12G48 S12G64

64-pin LQFP

PT7

PT6

KWP6/PP6

KWP7/PP7

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

PAD15/KWAD15

PAD7/KWAD7/AN7

PAD14/KWAD14

PAD6/KWAD6/AN6

PAD13/KWAD13

PAD5/KWAD5/AN5

PAD12/KWAD12

PAD4/KWAD4/AN4

PAD11/KWAD11/AN11/ACMPM

PAD3/KWAD3/AN3

PAD10/KWAD10/AN10/ACMPP

PAD2/KWAD2/AN2

PAD9/KWAD9/AN9/ACMPO

PAD1/KWAD1/AN1

PAD8/KWAD8/AN8

PAD0/KWAD0/AN0

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

Figure 1-12. 64-Pin LQFP Pinout for S12G48 and S12G64

MC9S12G Family Reference Manual, Rev.1.23

86 Freescale Semiconductor

Device Overview MC9S12G-Family

Table 1-17. 64-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 PJ6 KWJ6 — — — V

2 PJ5 KWJ5 — — — V

3 PJ4 KWJ4 — — — V

4 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERJ/PPSJ Up

PULLUP

5 VDDX — — — — — — —

6 VDDR — — — — — — —

7 VSSX — — — — — — —

8 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

9 VSS — — — — — — —

10 PE1

11 TEST — — — — N.A.

12 PJ0 KWJ0 MISO1 — — V

13 PJ1 KWJ1 MOSI1 — — V

14 PJ2 KWJ2 SCK1 — — V

15 PJ3 KWJ3

16 BKGD MODC — — — V

17 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

19 PP2 KWP2 ETRIG2 PWM2 — V

20 PP3 KWP3 ETRIG3 PWM3 — V

21 PP4 KWP4 PWM4 — — V

22 PP5 KWP5 PWM5 — — V

23 PP6 KWP6 — — — V

24 PP7 KWP7 — — — V

25 PT7 — — — — V

26 PT6 — — — — V

27 PT5 IOC5 — — — V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

SS1 — — V

DDX

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 87

Device Overview MC9S12G-Family

Table 1-17. 64-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PT4 IOC4 — — — V

29 PT3 IOC3 — — — V

30 PT2 IOC2 — — — V

31 PT1 IOC1

32 PT0 IOC0

IRQ — — V

XIRQ — — V

33 PAD0 KWAD0 AN0 — — V

34 PAD8 KWAD8 AN8 — — V

35 PAD1 KWAD1 AN1 — — V

36 PAD9 KWAD9 AN9 ACMPO — V

37 PAD2 KWAD2 AN2 — — V

38 PAD10 KWAD10 AN10 ACMPP V

39 PAD3 KWAD3 AN3 — — V

40 PAD11 KWAD11 AN11 ACMPM V

41 PAD4 KWAD4 AN4 — — V

42 PAD12 KWAD12 — — — V

43 PAD5 KWAD5 AN5 — — V

44 PAD13 KWAD13 — — — V

45 PAD6 KWAD6 AN6 — — V

46 PAD14 KWAD14 — — — V

47 PAD7 KWAD7 AN7 — — V

48 PAD15 KWAD15 — — — V

5th

Power

Supply

DDX

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0ADPPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

Internal Pull

Resistor

CTRL

PERT/PPST Disabled

49 VRH — — — — — — —

Reset

State

50 VDDA — — — — — — —

51 VSSA — — — — — — —

52 PS0 RXD0 — — — V

53 PS1 TXD0 — — — V

54 PS2 RXD1 — — — V

55 PS3 TXD1 — — — V

56 PS4 MISO0 — — — V

DDX

PERS/PPSS Up

MC9S12G Family Reference Manual, Rev.1.23

88 Freescale Semiconductor

Device Overview MC9S12G-Family

Table 1-17. 64-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

57 PS5 MOSI0 — — — V

58 PS6 SCK0 — — — V

59 PS7 API_EXTCLK ECLK

SS0 — V

60 PM0 RXCAN — — — V

61 PM1 TXCAN — — — V

62 PM2 — — — — V

63 PM3 — — — — V

64 PJ7 KWJ7 — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDX

PERM/PPSM Disabled

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PERJ/PPSJ Up

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 89

Device Overview MC9S12G-Family

1.8.5 S12GA48 and S12GA64

1.8.5.1 Pinout 48-Pin LQFP

PM1/TXCAN

PS6/SCK0

PS5/MOSI0

PS7/API_EXTCLK/ECLK/SS0

PS4/MISO0

PM0/RXCAN

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST

MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1/KWJ3/PJ3

BKGD

4847464544434241403938

1 2 3 4 5 6 7 8

9 10 11 12

S12GA48 S12GA64

48-Pin LQFP

1314151617181920212223

IOC5/PT5

IOC4/PT4

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

IOC3/PT3

IOC2/PT2

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PAD7/KWAD7/AN7

PAD6/KWAD6/AN6

PAD5/KWAD5/AN5

PAD4/KWAD4/AN4

PAD11/KWAD11/AN11/ACMPM

PAD3/KWAD3/AN3

PAD10/KWAD10/AN10/ACMPP

PAD2/KWAD2/AN2

PAD9/KWAD9/AN9/ACMPO

PAD1/KWAD1/AN1

PAD8/KWAD8/AN8

PAD0/KWAD0/AN0

Figure 1-13. 48-Pin LQFP Pinout for S12GA48 and S12GA64

Table 1-18. 48-Pin LQFP Pinout for S12GA48 and S12GA64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

MC9S12G Family Reference Manual, Rev.1.23

90 Freescale Semiconductor

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

Device Overview MC9S12G-Family

Table 1-18. 48-Pin LQFP Pinout for S12GA48 and S12GA64

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

2 VDDXR — — — — — — —

3 VSSX — — — — — — —

4 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5 VSS — — — — — — —

6 PE1

7 TEST — — — — N.A.

8 PJ0 KWJ0 — MISO1 — V

9 PJ1 KWJ1 — MOSI1 — V

10 PJ2 KWJ2 — SCK1 — V

11 PJ3 KWJ3 —

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1

24 PT0 IOC0

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 AN8 — — V

27 PAD1 KWAD1 AN1 — — V

28 PAD9 KWAD9 AN9 ACMPO — V

29 PAD2 KWAD2 AN2 — — V

30 PAD10 KWAD10 AN10 ACMPP V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

SS1 — V

IRQ — — V

XIRQ — — V

DDX

DDA

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 91

Device Overview MC9S12G-Family

Table 1-18. 48-Pin LQFP Pinout for S12GA48 and S12GA64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 AN11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 RXD1 — — — V

42 PS3 TXD1 — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLK ECLK

SS0 — V

47 PM0 RXCAN — — — V

48 PM1 TXCAN — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERS/PPSS Up

PERM/PPSM Disabled

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

92 Freescale Semiconductor

1.8.5.2 Pinout 64-Pin LQFP

PJ7/KWJ7

PM3

PM2

PM1/TXCAN

PM0/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA

Device Overview MC9S12G-Family

VRH

KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4

RESET

VDDX

VDDR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1/KWJ3/PJ3

BKGD

646362616059585756555453525150

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

171819202122232425262728293031

S12GA48 S12GA64

64-pin LQFP

PT7

PT6

KWP6/PP6

KWP7/PP7

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

PAD15/KWAD15

PAD7/KWAD7/AN7

PAD14/KWAD14

PAD6/KWAD6/AN6

PAD13/KWAD13

PAD5/KWAD5/AN5

PAD12/KWAD12

PAD4/KWAD4/AN4

PAD11/KWAD11/AN11/ACMPM

PAD3/KWAD3/AN3

PAD10/KWAD10/AN10/ACMPP

PAD2/KWAD2/AN2

PAD9/KWAD9/AN9/ACMPO

PAD1/KWAD1/AN1

PAD8/KWAD8/AN8

PAD0/KWAD0/AN0

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

Figure 1-14. 64-Pin LQFP Pinout for S12GA48 and S12GA64

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Freescale Semiconductor 93

Device Overview MC9S12G-Family

Table 1-19. 64-Pin LQFP Pinout for S12GA48 and S12GA64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 PJ6 KWJ6 — — — V

2 PJ5 KWJ5 — — — V

3 PJ4 KWJ4 — — — V

4 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERJ/PPSJ Up

PULLUP

5 VDDX — — — — — — —

6 VDDR — — — — — — —

7 VSSX — — — — — — —

8 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

9 VSS — — — — — — —

10 PE1

11 TEST — — — — N.A.

12 PJ0 KWJ0 MISO1 — — V

13 PJ1 KWJ1 MOSI1 — — V

14 PJ2 KWJ2 SCK1 — — V

15 PJ3 KWJ3

16 BKGD MODC — — — V

17 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

19 PP2 KWP2 ETRIG2 PWM2 — V

20 PP3 KWP3 ETRIG3 PWM3 — V

21 PP4 KWP4 PWM4 — — V

22 PP5 KWP5 PWM5 — — V

23 PP6 KWP6 — — — V

24 PP7 KWP7 — — — V

25 PT7 — — — — V

26 PT6 — — — — V

27 PT5 IOC5 — — — V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

SS1 — — V

DDX

Reset

State

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94 Freescale Semiconductor

Device Overview MC9S12G-Family

Table 1-19. 64-Pin LQFP Pinout for S12GA48 and S12GA64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PT4 IOC4 — — — V

29 PT3 IOC3 — — — V

30 PT2 IOC2 — — — V

31 PT1 IOC1

32 PT0 IOC0

IRQ — — V

XIRQ — — V

33 PAD0 KWAD0 AN0 — — V

34 PAD8 KWAD8 AN8 — — V

35 PAD1 KWAD1 AN1 — — V

36 PAD9 KWAD9 AN9 ACMPO — V

37 PAD2 KWAD2 AN2 — — V

38 PAD10 KWAD10 AN10 ACMPP V

39 PAD3 KWAD3 AN3 — — V

40 PAD11 KWAD11 AN11 ACMPM V

41 PAD4 KWAD4 AN4 — — V

42 PAD12 KWAD12 — — — V

43 PAD5 KWAD5 AN5 — — V

44 PAD13 KWAD13 — — — V

45 PAD6 KWAD6 AN6 — — V

46 PAD14 KWAD14 — — — V

47 PAD7 KWAD7 AN7 — — V

48 PAD15 KWAD15 — — — V

5th

Power

Supply

DDX

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0ADPPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

Internal Pull

Resistor

CTRL

PERT/PPST Disabled

49 VRH — — — — — — —

Reset

State

50 VDDA — — — — — — —

51 VSSA — — — — — — —

52 PS0 RXD0 — — — V

53 PS1 TXD0 — — — V

54 PS2 RXD1 — — — V

55 PS3 TXD1 — — — V

56 PS4 MISO0 — — — V

DDX

PERS/PPSS Up

MC9S12G Family Reference Manual, Rev.1.23

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Device Overview MC9S12G-Family

Table 1-19. 64-Pin LQFP Pinout for S12GA48 and S12GA64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

57 PS5 MOSI0 — — — V

58 PS6 SCK0 — — — V

59 PS7 API_EXTCLK ECLK

SS0 — V

60 PM0 RXCAN — — — V

61 PM1 TXCAN — — — V

62 PM2 — — — — V

63 PM3 — — — — V

64 PJ7 KWJ7 — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDX

PERM/PPSM Disabled

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PERJ/PPSJ Up

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

96 Freescale Semiconductor

1.8.6 S12G96 and S12G128

1.8.6.1 Pinout 48-Pin LQFP

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PM1/TXD2/TXCAN

PM0/RXD2/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

Device Overview MC9S12G-Family

VDDA/VRH

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST

MISO1/PWM6/KWJ0/PJ0

MOSI1/IOC6/KWJ1/PJ1

SCK1/IOC7/KWJ2/PJ2 SS1/PWM7/KWJ3/PJ3

BKGD

Figure 1-15. 48-Pin LQFP Pinout for S12G96 and S12G128

4847464544434241403938

1 2 3 4 5 6 7 8

9 10 11 12

S12G96

S12G128

48-Pin LQFP

1314151617181920212223

IOC5/PT5

IOC4/PT4

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

IOC3/PT3

IOC2/PT2

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PAD7/KWAD7/AN7

PAD6/KWAD6/AN6

PAD5/KWAD5/AN5

PAD4/KWAD4/AN4

PAD11/KWAD11/AN11

PAD3/KWAD3/AN3

PAD10/KWAD10/AN10

PAD2/KWAD2/AN2

PAD9/KWAD9/AN9

PAD1/KWAD1/AN1

PAD8/KWAD8/AN8

PAD0/KWAD0/AN0

Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

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Freescale Semiconductor 97

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

Device Overview MC9S12G-Family

Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

2 VDDXR — — — — — — —

3 VSSX — — — — — — —

4 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5 VSS — — — — — — —

6 PE1

7 TEST — — — — N.A.

8 PJ0 KWJ0 PWM6 MISO1 — V

9 PJ1 KWJ1 IOC6 MOSI1 — V

10 PJ2 KWJ2 IOC7 SCK1 — V

11 PJ3 KWJ3 PWM7

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1

24 PT0 IOC0

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 AN8 — — V

27 PAD1 KWAD1 AN1 — — V

28 PAD9 KWAD9 AN9 — V

29 PAD2 KWAD2 AN2 — — V

30 PAD10 KWAD10 AN10 V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

SS1 — V

IRQ — — V

XIRQ — — V

DDX

DDA

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

98 Freescale Semiconductor

Device Overview MC9S12G-Family

Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 AN11 — — V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 RXD1 — — — V

42 PS3 TXD1 — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLK ECLK

SS0 — V

47 PM0 RXD2 RXCAN — — V

48 PM1 TXD2 TXCAN — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERS/PPSS Up

PERM/PPSM Disabled

Reset

State

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Device Overview MC9S12G-Family

1.8.6.2 Pinout 64-Pin LQFP

PJ7/KWJ7/SS2

PM3/TXD2

PM2/RXD2

PM1/TXCAN

PM0/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA

VRH

SCK2/KWJ6/PJ6 MOSI2/KWJ5/PJ5 MISO2/KWJ4/PJ4

RESET

VDDX

VDDR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1/KWJ3/PJ3

BKGD

646362616059585756555453525150

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

171819202122232425262728293031

S12G96

S12G128

64-Pin LQFP

IOC7/PT7

IOC6/PT6

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM6/KWP6/PP6

PWM7/KWP7/PP7

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

PAD15/KWAD15

PAD7/KWAD7/AN7

PAD14/KWAD14

PAD6/KWAD6/AN6

PAD13/KWAD13

PAD5/KWAD5/AN5

PAD12/KWAD12

PAD4/KWAD4/AN4

PAD11/KWAD11/AN11

PAD3/KWAD3/AN3

PAD10/KWAD10/AN10

PAD2/KWAD2/AN2

PAD9/KWAD9/AN9

PAD1/KWAD1/AN1

PAD8/KWAD8/AN8

PAD0/KWAD0/AN0

IRQ/IOC1/PT1

XIRQ/IOC0/PT0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

Figure 1-16. 64-Pin LQFP Pinout for S12G96 and S12G128

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100 Freescale Semiconductor

Device Overview MC9S12G-Family

Table 1-21. 64-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 PJ6 KWJ6 SCK2 — — V

2 PJ5 KWJ5 MOSI2 — — V

3 PJ4 KWJ4 MISO2 — — V

4 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERJ/PPSJ Up

PULLUP

5 VDDX — — — — — — —

6 VDDR — — — — — — —

7 VSSX — — — — — — —

8 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

9 VSS — — — — — — —

10 PE1

11 TEST — — — — N.A.

12 PJ0 KWJ0 MISO1 — — V

13 PJ1 KWJ1 MOSI1 — — V

14 PJ2 KWJ2 SCK1 — — V

15 PJ3 KWJ3

16 BKGD MODC — — — V

17 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V

18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

19 PP2 KWP2 ETRIG2 PWM2 — V

20 PP3 KWP3 ETRIG3 PWM3 — V

21 PP4 KWP4 PWM4 — — V

22 PP5 KWP5 PWM5 — — V

23 PP6 KWP6 PWM6 — — V

24 PP7 KWP7 PWM7 — — V

25 PT7 IOC7 — — — V

26 PT6 IOC6 — — — V

27 PT5 IOC5 — — — V

XTAL — — — V

DDX

PUCR/PDPEE Down

RESET pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

SS1 — — V

DDX

Reset

State

MC9S12G Family Reference Manual, Rev.1.23

Freescale Semiconductor 101

Device Overview MC9S12G-Family

Table 1-21. 64-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PT4 IOC4 — — — V

29 PT3 IOC3 — — — V

30 PT2 IOC2 — — — V

31 PT1 IOC1

32 PT0 IOC0

IRQ — — V

XIRQ — — V

33 PAD0 KWAD0 AN0 — — V

34 PAD8 KWAD8 AN8 — — V

35 PAD1 KWAD1 AN1 — — V

36 PAD9 KWAD9 AN9 — — V

37 PAD2 KWAD2 AN2 — — V

38 PAD10 KWAD10 AN10 — — V

39 PAD3 KWAD3 AN3 — — V

40 PAD11 KWAD11 AN11 — — V

41 PAD4 KWAD4 AN4 — — V

42 PAD12 KWAD12 — — V

43 PAD5 KWAD5 AN5 — — V

44 PAD13 KWAD13 — — V

45 PAD6 KWAD6 AN6 — — V

46 PAD14 KWAD14 — — V

47 PAD7 KWAD7 AN7 — — V

48 PAD15 KWAD15 — — V

5th

Power

Supply

DDX

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0ADPPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

Internal Pull

Resistor

CTRL

PERT/PPST Disabled

49 VRH — — — — — — —

Reset

State

50 VDDA — — — — — — —

51 VSSA — — — — — — —

52 PS0 RXD0 — — — V

53 PS1 TXD0 — — — V

54 PS2 RXD1 — — — V

55 PS3 TXD1 — — — V

56 PS4 MISO0 — — — V

DDX

PERS/PPSS Up

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102 Freescale Semiconductor

Freescale Semiconductor MC9S12G User guide

Specifications and Main Features

Frequently Asked Questions

User Manual

Chapter 1 Device Overview MC9S12G-Family

1.1 Introduction

1.2 Features

1.2.1 MC9S12G-Family Comparison

1.2.2 Chip-Level Features

1.3 Module Features

1.3.1 S12 16-Bit Central Processor Unit (CPU)

1.3.2 On-Chip Flash with ECC

1.3.3 On-Chip SRAM

1.3.4 Port Integration Module (PIM)

1.3.5 Main External Oscillator (XOSCLCP)

1.3.6 Internal RC Oscillator (IRC)

1.3.7 Internal Phase-Locked Loop (IPLL)

1.3.8 System Integrity Support

1.3.9 Timer (TIM)

1.3.10 Pulse Width Modulation Module (PWM)

1.3.11 Controller Area Network Module (MSCAN)

1.3.12 Serial Communication Interface Module (SCI)

1.3.13 Serial Peripheral Interface Module (SPI)

1.3.14 Analog-to-Digital Converter Module (ADC)

1.3.15 Reference Voltage Attenuator (RVA)

1.3.16 Digital-to-Analog Converter Module (DAC)

1.3.17 Analog Comparator (ACMP)

1.3.18 On-Chip Voltage Regulator (VREG)

1.3.19 Background Debug (BDM)

1.3.20 Debugger (DBG)

1.4 Key Performance Parameters

1.5 Block Diagram

1.6 Family Memory Map

1.6.1 Part ID Assignments

1.7 Signal Description and Device Pinouts

1.7.1 Pin Assignment Overview

1.7.2 Detailed Signal Descriptions

1.7.2.17 ACMP Signals

1.7.2.18 DAC Signals

1.7.2.19 SPI Signals

1.7.2.20 SCI Signals

1.7.2.21 CAN signals

1.7.2.22 PWM[7:0] Signals

1.7.2.23 Internal Clock outputs

1.7.2.24 IOC[7:0] Signals

1.7.2.25 IRQ

1.7.2.26 XIRQ

1.7.2.27 ETRIG[3:0]

1.7.3 Power Supply Pins

1.7.3.6 Power and Ground Connection Summary

1.8 Device Pinouts

1.8.1 S12GN16 and S12GN32

1.8.1.1 Pinout 20-Pin TSSOP

1.8.1.2 Pinout 32-Pin LQFP

1.8.1.3 Pinout 48-Pin LQFP/QFN

1.8.2 S12GNA16 and S12GNA32

1.8.2.1 Pinout 48-Pin LQFP/QFN

1.8.3 S12GN48

1.8.3.1 Pinout 32-Pin LQFP

1.8.3.2 Pinout 48-Pin LQFP

1.8.3.3 Pinout 64-Pin LQFP

1.8.4 S12G48 and S12G64

1.8.4.1 Pinout 32-Pin LQFP

1.8.4.2 Pinout 48-Pin LQFP

1.8.4.3 Pinout 64-Pin LQFP

1.8.5 S12GA48 and S12GA64

1.8.5.1 Pinout 48-Pin LQFP

1.8.5.2 Pinout 64-Pin LQFP

1.8.6 S12G96 and S12G128

1.8.6.1 Pinout 48-Pin LQFP

1.8.6.2 Pinout 64-Pin LQFP