Freescale Semiconductor MC9S08PA32, MC9S08PA60 Series Technical Data Manual

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Page 1

Freescale Semiconductor

Data Sheet: Technical Data

MC9S08PA60 Series

Support: MC9S08PA60 and MC9S08PA32

Key features

• 8-Bit S08 central processor unit (CPU) – Up to 20 MHz bus at 2.7 V to 5.5 V across

temperature range of -40 °C to 105 °C – Supporting up to 40 interrupt/reset sources – Supporting up to four-level nested interrupt – On-chip memory – Up to 60 KB flash read/program/erase over full

operating voltage and temperature – Up to 256 byte EEPROM; 2-byte erase sector;

program and erase while executing flash – Up to 4096 byte random-access memory (RAM) – Flash and RAM access protection

• Power-saving modes – One low-power stop mode; reduced power wait

mode

– Peripheral clock enable register can disable

clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode

• Clocks – Oscillator (XOSC) - loop-controlled Pierce

oscillator; crystal or ceramic resonator range of

31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz

– Internal clock source (ICS) - containing a

frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allowing 1% deviation across temperature range of 0 °C to 70 °C and 2% deviation across temperature range of -40 °C to 105 °C; up to 20 MHz

• System protection – Watchdog with independent clock source – Low-voltage detection with reset or interrupt;

selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset

Document Number: MC9S08PA60

Rev. 1, 10/9/2012

MC9S08PA60

• Development support – Single-wire background debug interface – Breakpoint capability to allow three breakpoints

setting during in-circuit debugging

– On-chip in-circuit emulator (ICE) debug module

containing two comparators and nine trigger modes

• Peripherals – ACMP - one analog comparator with both

positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering

– ADC - 16-channel, 12-bit resolution; 2.5 µs

conversion time; data buffers with optional watermark; automatic compare function; internal bandgap reference channel; operation in stop mode; optional hardware trigger

– CRC - programmable cyclic redundancy check

module

– FTM - three flex timer modulators modules

including one 6-channel and two 2-channel ones; 16-bit counter; each channel can be configured for input capture, output compare, edge- or center-aligned PWM mode

– IIC - One inter-integrated circuit module; up to

400 kbps; multi-master operation; programmable slave address; supporting broadcast mode and 10-bit addressing; supporting SMBUS and PMBUS

– MTIM - Two modulo timers with 8-bit prescaler

and overflow interrupt – RTC - 16-bit real timer counter (RTC) – SCI - three serial communication interface (SCI/

UART) modules optional 13-bit break; full

duplex non-return to zero (NRZ); LIN extension

support – SPI - one 8-bit and one 16-bit serial peripheral

interface (SPI) modules; full-duplex or single-

wire bidirectional; master or slave mode

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

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• Input/Output – 57 GPIOs including one output-only pin – Two 8-bit keyboard interrupt modules (KBI) – Two true open-drain output pins – Eight, ultra-high current sink pins supporting 20 mA source/sink current

• Package options – 64-pin LQFP; 64-pin QFP – 48-pin LQFP – 44-pin LQFP – 32-pin LQFP

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

2 Freescale Semiconductor, Inc.

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Table of Contents

1 Ordering parts...........................................................................4

1.1 Determining valid orderable parts......................................4

2 Part identification......................................................................4

2.1 Description.........................................................................4

2.2 Format...............................................................................4

2.3 Fields.................................................................................4

2.4 Example............................................................................5

3 Parameter Classification...........................................................5

4 Ratings......................................................................................5

4.1 Thermal handling ratings...................................................5

4.2 Moisture handling ratings..................................................6

4.3 ESD handling ratings.........................................................6

4.4 Voltage and current operating ratings...............................6

5 General.....................................................................................7

5.1 Nonswitching electrical specifications...............................7

5.1.1 DC characteristics.................................................7

5.1.2 Supply current characteristics...............................12

5.1.3 EMC performance.................................................13

5.2 Switching specifications.....................................................13

5.2.1 Control timing........................................................13

5.2.2 Debug trace timing specifications.........................14

5.2.3 FTM module timing...............................................15

5.3 Thermal specifications.......................................................16

5.3.1 Thermal characteristics.........................................16

6 Peripheral operating requirements and behaviors....................17

6.1 External oscillator (XOSC) and ICS characteristics...........17

6.2 NVM specifications............................................................19

6.3 Analog...............................................................................20

6.3.1 ADC characteristics...............................................20

6.3.2 Analog comparator (ACMP) electricals.................23

6.4 Communication interfaces.................................................24

6.4.1 SPI switching specifications..................................24

7 Dimensions...............................................................................27

7.1 Obtaining package dimensions.........................................27

8 Pinout........................................................................................28

8.1 Signal multiplexing and pin assignments...........................28

8.2 Device pin assignment......................................................31

9 Revision history.........................................................................34

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Freescale Semiconductor, Inc. 3

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Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PA60 and PA32.

Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: MC 9 S08 PA AA B CC

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid):

Field Description Values

MC Qualification status • MC = fully qualified, general market flow 9 Memory S08 Core • S08 = 8-bit CPU PA Device family • PA AA Approximate flash size in KB • 60 = 60 KB

• 32 = 32 KB

B Temperature range (°C) • V = –40 to 105

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MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

4 Freescale Semiconductor, Inc.

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Parameter Classification

Field Description Values

CC Package designator • QH = 64-pin QFP

• LH = 64-pin LQFP

• LF = 48-pin LQFP

• LD = 44-pin LQFP

• LC = 32-pin LQFP

2.4 Example

This is an example part number: MC9S08PA60VQH

3 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 1. Parameter Classifications

P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size

across process variations.

T Those parameters are achieved by design characterization on a small sample size from typical devices under

typical conditions unless otherwise noted. All values shown in the typical column are within this category.

D Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the parameter tables where appropriate.

Ratings

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes

STG

SDR

Freescale Semiconductor, Inc. 5

Storage temperature –55 150 °C 1 Solder temperature, lead-free — 260 °C 2

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 6

Ratings

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes

MSL Moisture sensitivity level — 3 — 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes

V V

HBM

CDM

LAT

Electrostatic discharge voltage, human body model -6000 +6000 V 1 Electrostatic discharge voltage, charged-device model -500 +500 V Latch-up current at ambient temperature of 105°C -100 +100 mA

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

4.4 Voltage and current operating ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in below table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled.

Symbol Description Min. Max. Unit

DIO

Supply voltage –0.3 5.8 V Maximum current into V Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 VDD + 0.3 V

Table continues on the next page...

— 120 mA

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

6 Freescale Semiconductor, Inc.

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Symbol Description Min. Max. Unit

AIO

DDA

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

General

Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all

port pins) Analog supply voltage VDD – 0.3 VDD + 0.3 V

–25 25 mA

General

5.1

Nonswitching electrical specifications

5.1.1 DC characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 2. DC characteristics

Symbol C Descriptions Min Typical

— — Operating voltage — 2.7 — 5.5 V

OHT

OLT

P Output high

voltage

C 3 V, I

P High current drive

C 3 V, I

D Output high

current

P Output low

voltage

C 3 V, I

P High current drive

C 3 V, I

D Output low

current

All I/O pins, low-drive

strength

pins, high-drive

strength

Max total IOH for all

ports

All I/O pins, low-drive

strength

pins, high-drive

strength

Max total IOL for all

ports

5 V, I

-2 mA

-0.6 mA

5 V, I

-20 mA

-6 mA

5 V, I

0.6 mA

5 V, I

=20 mA

load

5 V — — -100 mA 3 V — — -60

= 2

load

= 6

load

mA 5 V — — 100 mA 3 V — — 60

VDD - 1.5 — — V

VDD - 0.8 — — V

VDD - 1.5 — — V

VDD - 0.8 — — V

— — 1.5 V

— — 0.8 V

— — 1.5 V

— — 0.8 V

Max Unit

Table continues on the next page...

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Freescale Semiconductor, Inc. 7

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Nonswitching electrical specifications

Table 2. DC characteristics (continued)

Symbol C Descriptions Min Typical

hys

|IIn| P Input leakage

|IOZ| P Hi-Z (off-

OZTOT

RAM

P Input high

voltage

P Input low

voltage

C Input

All digital inputs VDD>4.1V 0.70 × V

VDD>2.7V 0.85 × V

All digital inputs VDD>4.1V — — 0.35 × V

VDD>2.7V — — 0.30 × V

All digital inputs — 0.06 × V

hysteresis

current

state) leakage

All input only pins

(per pin)

All input/output (per

pin)

VIN = VDD or

— 0.1 1 µA

current

| C Total leakage

combined for

All input only and I/O VIN = VDD or

— — 2 µA

all inputs and

Hi-Z pins

P Pullup

resistors

All digital inputs,

when enabled (all I/O

— 17.5 — 52.5 kΩ

pins other than PTA5/

IRQ/TCLK/RESET

P Pullup

resistors

D DC injection

4, 5, 6

current

PTA5/IRQ/TCLK/

— 17.5 — 52.5 kΩ

RESET

Single pin limit VIN < VSS,

Total MCU limit,

VIN > V

-0.2 — 2 mA

-5 — 25

includes sum of all

stressed pins C Input capacitance, all pins — — — 8 pF C RAM retention voltage — 2.0 — — V

Max Unit

— — V — —

— — mV

1. Typical values are measured at 25 °C. Characterized, not tested.

2. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support ultra high current output.

3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured externally on the pin.

4. All functional non-supply pins, except for PTA5, are internally clamped to VSS and VDD.

5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the large one.

6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is very low (which would reduce overall power consumption).

Table 3. LVD and POR Specification

Symbol C Description Min Typ Max Unit

POR

LVDH

D POR re-arm voltage C Falling low-voltage detect

threshold - high range (LVDV

= 1)

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MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

8 Freescale Semiconductor, Inc.

1.5 1.75 2.0 V

4.2 4.3 4.4 V

Page 9

Nonswitching electrical specifications

Table 3. LVD and POR Specification (continued)

Symbol C Description Min Typ Max Unit

LVW1H

LVW2H

LVW3H

LVW4H

HYSH

LVDL

LVDW1L

LVDW2L

LVDW3L

LVDW4L

HYSDL

HYSWL

C Falling low-

voltage

C Level 2 falling

warning threshold high range

Level 1 falling

(LVWV = 00)

(LVWV = 01)

C Level 3 falling

(LVWV = 10)

C Level 4 falling

(LVWV = 11)

C High range low-voltage

detect/warning hysteresis

C Falling low-voltage detect

threshold - low range (LVDV =

C Falling low-

voltage

C Level 2 falling

warning threshold -

low range

Level 1 falling

(LVWV = 00)

(LVWV = 01)

C Level 3 falling

(LVWV = 10)

C Level 4 falling

(LVWV = 11)

C Low range low-voltage detect

hysteresis

C Low range low-voltage

warning hysteresis

P Buffered bandgap output

4.3 4.4 4.5 V

4.5 4.5 4.6 V

4.6 4.6 4.7 V

4.7 4.7 4.8 V

— 100 — mV

2.56 2.61 2.66 V

2.62 2.7 2.78 V

2.72 2.8 2.88 V

2.82 2.9 2.98 V

2.92 3.0 3.08 V

— 40 — mV

— 80 — mV

1.14 1.16 1.18 V

1. Maximum is highest voltage that POR is guaranteed.

2. Rising thresholds are falling threshold + hysteresis.

3. voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Freescale Semiconductor, Inc. 9

Page 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

12345

IOH(mA)

VDD-VOH(V)

VDD=3V

VDD=5V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

510152025

IOH(mA)

VDD-VOH(V)

VDD=3V

VDD=5V

Nonswitching electrical specifications

Figure 1. Typical IOH Vs. VDD-V

Figure 2. Typical IOH Vs. VDD-VOH (High current drive)

10 Freescale Semiconductor, Inc.

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 11

0.1

0.2

0.3

0.4

0.5

0.6

12345

IOL(mA)

VOL(V)

VDD=3V

VDD=5V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

510152025

IOL(mA)

VOL(V)

VDD=3V

VDD=5V

Nonswitching electrical specifications

Figure 3. Typical IOL Vs. V

Figure 4. Typical IOL Vs. VOL (High current drive)

Freescale Semiconductor, Inc. 11

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 12

Nonswitching electrical specifications

5.1.2 Supply current characteristics

This section includes information about power supply current in various operating modes.

Table 4. Supply current characteristics

Num C Parameter Symbol Bus Freq VDD (V) Typical

1 C Run supply current FEI

mode, all modules on; run

C 10 MHz 7.2 —

from flash

20 MHz 5 12.6 — mA -40 to 105 °C

1 MHz 2.4 — C 20 MHz 3 9.6 — C 10 MHz 6.1 —

1 MHz 2.1 —

2 C Run supply current FEI

mode, all modules off &

C 10 MHz 6.2 —

gated; run from flash

20 MHz 5 10.5 — mA -40 to 105 °C

1 MHz 2.3 — C 20 MHz 3 7.4 — C 10 MHz 5.0 —

1 MHz 2.0 —

3 P Run supply current FBE

mode, all modules on; run

C 10 MHz 6.5 —

from RAM

20 MHz 5 12.1 14.8 mA -40 to 105 °C

1 MHz 1.8 — P 20 MHz 3 9.1 11.8 C 10 MHz 5.5 —

1 MHz 1.5 —

4 P Run supply current FBE

mode, all modules off &

C 10 MHz 5.4 —

gated; run from RAM

20 MHz 5 9.8 12.3 mA -40 to 105 °C

1 MHz 1.6 — P 20 MHz 3 6.9 9.2 C 10 MHz 4.4 —

1 MHz 1.4 —

5 C Wait mode current FEI

mode, all modules on

C 10 MHz 4.5 —

20 MHz 5 7.8 — mA -40 to 105 °C

1 MHz 1.3 — C 20 MHz 3 5.1 —

10 MHz 3.5 —

1 MHz 1.2 —

6 C Stop3 mode supply

current no clocks active

C — 3 3 — -40 to 105 °C

(except 1 kHz LPO

2, 3

clock)

S3I

— 5 3.8 — µA -40 to 105 °C

Max Unit Temp

Table continues on the next page...

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

12 Freescale Semiconductor, Inc.

Page 13

Switching specifications

Table 4. Supply current characteristics (continued)

Num C Parameter Symbol Bus Freq VDD (V) Typical

7 C ADC adder to stop3

C 3 40 —

8 C LVD adder to stop3

C 3 125 —

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

2. RTC adder cause <1 µA IDD increase typically, RTC clock source is 1 kHz LPO clock.

3. ACMP adder cause <1 µA IDD increase typically.

4. LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms.

ADLPC = 1

ADLSMP = 1

ADCO = 1

MODE = 10B

ADICLK = 11B

— — 5 44 — µA -40 to 105 °C

— — 5 130 — µA -40 to 105 °C

Max Unit Temp

5.1.3 EMC performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.

5.2

Switching specifications

5.2.1 Control timing

Table 5. Control timing

Num C Rating Symbol Min Typical

1 P Bus frequency (t 2 P Internal low power oscillator frequency f 3 D External reset pulse width t

4 D Reset low drive t 5 D BKGD/MS setup time after issuing background

debug force reset to enter user or BDM modes

6 D BKGD/MS hold time after issuing background

debug force reset to enter user or BDM modes

cyc

= 1/f

) f

Bus

LPO

extrst

rstdrv

MSSU

MSH

DC — 20 MHz

0.67 1.0 1.25 KHz

1.5 ×

Self_reset

34 × t

cyc

500 — — ns

100 — — ns

— — ns

Max Unit

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MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Freescale Semiconductor, Inc. 13

Page 14











 

extrst

RESET PIN

IHIL

KBIPx

ILIH

IRQ/KBIPx

Switching specifications

Table 5. Control timing (continued)

Num C Rating Symbol Min Typical

7 D IRQ pulse width Asynchronous

path

D Synchronous path t

8 D Keyboard interrupt pulse

width

Asynchronous

path

D Synchronous path t

9 C Port rise and fall time -

C t

Normal drive strength

(HDRVE_PTXx = 0) (load

— t

ILIH

IHIL

ILIH

IHIL

Rise

Fall

100 — — ns

1.5 × t

cyc

100 — — ns

1.5 × t

cyc

— 10.2 — ns — 9.5 — ns

= 50 pF) C Port rise and fall time C t

Extreme high drive

strength (HDRVE_PTXx =

1) (load = 50 pF)

— t

Rise

Fall

— 5.4 — ns — 4.6 — ns

1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.

2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.

3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of t VDD rises above V

4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.

LVD

Max Unit

— — ns

MSH

after

Figure 5. Reset timing

Figure 6. IRQ/KBIPx timing

5.2.2 Debug trace timing specifications

Table 6. Debug trace operating behaviors

Symbol Description Min. Max. Unit

cyc

t t

Clock period Frequency dependent MHz Low pulse width 2 — ns High pulse width 2 — ns Clock and data rise time — 3 ns Clock and data fall time — 3 ns

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MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

14 Freescale Semiconductor, Inc.

Page 15

Ts Ts

TRACE_CLKOUT

TRACE_D[3:0]

Switching specifications

Table 6. Debug trace operating behaviors (continued)

Symbol Description Min. Max. Unit

Data setup 3 — ns Data hold 2 — ns

Figure 7. TRACE_CLKOUT specifications

Figure 8. Trace data specifications

5.2.3 FTM module timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.

Table 7. FTM input timing

No. C Function Symbol Min Max Unit

1 D External clock

frequency

2 D External clock

period

3 D External clock

high time

4 D External clock

low time

5 D Input capture

pulse width

TCLK

clkh

ICPW

clkl

0 f

4 — t

1.5 — t

/4 Hz

Bus

cyc

Freescale Semiconductor, Inc. 15

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 16











 

TCLK

clkh

clkl

TCLK











 

ICPW

FTMCHn

ICPW

FTMCHn

Thermal specifications

5.3

Thermal specifications

Figure 9. Timer external clock

Figure 10. Timer input capture pulse

5.3.1 Thermal characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To take P power calculations, determine the difference between actual pin voltage and VSS or V and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.

Table 8. Thermal characteristics

Rating Symbol Value Unit

Operating temperature range

(packaged)

Junction temperature range T

64-pin LQFP θ

64-pin QFP θ 48-pin LQFP θ 44-pin LQFP θ 32-pin LQFP θ

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

16 Freescale Semiconductor, Inc.

Thermal resistance single-layer board

Table continues on the next page...

into account in

I/O

-40 to 105 °C

-40 to 150 °C

71 °C/W 61 °C/W 81 °C/W 75 °C/W 86 °C/W

Page 17

Peripheral operating requirements and behaviors

Table 8. Thermal characteristics (continued)

Rating Symbol Value Unit

Thermal resistance four-layer board

64-pin LQFP θ

64-pin QFP θ 48-pin LQFP θ 44-pin LQFP θ 32-pin LQFP θ

53 °C/W 47 °C/W 57 °C/W 53 °C/W 57 °C/W

The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Where: TA = Ambient temperature, °C

θJA = Package thermal resistance, junction-to-ambient, °C/W

PD = P P

= IDD × VDD, Watts - chip internal power

int

I/O

For most applications, P between PD and TJ (if P

+ P

int

I/O

= Power dissipation on input and output pins - user determined

<< P

I/O

is neglected) is:

I/O

and can be neglected. An approximate relationship

int

PD = K ÷ (TJ + 273 °C) Solving the equations above for K gives: K = PD × (TA + 273 °C) + θJA × (PD)

where K is a constant pertaining to the particular part. K can be determined by measuring PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can be obtained by solving the above equations iteratively for any value of TA.

6 Peripheral operating requirements and behaviors

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Freescale Semiconductor, Inc. 17

Page 18

Peripheral operating requirements and behaviors

6.1 External oscillator (XOSC) and ICS characteristics

Table 9. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient)

Num C Characteristic Symbol Min Typical

1 C Oscillator

C High range (RANGE = 1)

crystal or

resonator

C High range (RANGE = 1),

Low range (RANGE = 0) f

FEE or FBE mode

32 — 40 kHz

4 — 20 MHz

high gain (HGO = 1),

FBELP mode

C High range (RANGE = 1),

4 — 20 MHz

low power (HGO = 0),

FBELP mode 2 D Load capacitors C1, C2 See Note 3 D Feedback

resistor

Low Frequency, Low-Power

Mode

Low Frequency, High-Gain

— — — MΩ

— 10 — MΩ

Mode

High Frequency, Low-

— 1 — MΩ

Power Mode

High Frequency, High-Gain

— 1 — MΩ

Mode

4 D Series resistor -

Low Frequency

5 D Series resistor -

Low-Power Mode

High-Gain Mode — 200 — kΩ

Low-Power Mode

— — — kΩ

High Frequency D Series resistor D 8 MHz — 0 — kΩ D 16 MHz — 0 — kΩ

High

Frequency,

High-Gain Mode

6 C Crystal start-up

time Low range

C Low range, high power — 800 — ms

= 32.768 KHz

C High range, low power t

crystal; High

range = 20 MHz

C High range, high power — 1.5 — ms

crystal,

7 T Internal reference start-up time t 8 D Square wave

D FBELP mode 0 — 20 MHz

input clock

frequency

9 P Average internal reference frequency -

4 MHz — 0 — kΩ

Low range, low power t

FEE or FBE mode

CSTL

CSTH

IRST

extal

int_t

— 1000 — ms

— 3 — ms

— 20 50 µs

0.03125 — 5 MHz

— 32.768 — kHz

trimmed 10 P DCO output frequency range - trimmed f 11 P Total deviation

of DCO output

from trimmed

C Over fixed voltage and

frequency

Over full voltage and

temperature range

temperature range of 0 to

Δf

dco_t

16 — 20 MHz — — ±2.0 %f

70 °C

12 C FLL acquisition time5,

Acquire

— — 2 ms

Table continues on the next page...

Max Unit

±1.0

dco

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

18 Freescale Semiconductor, Inc.

Page 19

XOSC

EXTAL XTAL

Crystal or Resonator

Peripheral operating requirements and behaviors

Table 9. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient)

(continued)

Num C Characteristic Symbol Min Typical

13 C Long term jitter of DCO output clock

(averaged over 2 ms interval)

Jitter

— 0.02 0.2 %f

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz.

3. See crystal or resonator manufacturer's recommendation.

4. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =

5. This parameter is characterized and not tested on each device.

6. Proper PC board layout procedures must be followed to achieve specifications.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the C for a given interval.

Max Unit

Bus

percentage

Jitter

dco

6.2 NVM specifications

This section provides details about program/erase times and program-erase endurance for the flash and EEPROM memories.

C Characteristic Symbol Min

D Supply voltage for program/erase -40 °C

D Supply voltage for read operation V

Freescale Semiconductor, Inc. 19

to 105 °C

Figure 11. Typical crystal or resonator circuit

Table 10. Flash characteristics

prog/erase

Read

2.7 — 5.5 V

Table continues on the next page...

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Typical

Max

Unit

Page 20

Peripheral operating requirements and behaviors

Table 10. Flash characteristics (continued)

C Characteristic Symbol Min

D NVM Bus frequency f D NVM Operating frequency f D Erase Verify All Blocks t D Erase Verify Flash Block t D Erase Verify EEPROM Block t D Erase Verify Flash Section t D Erase Verify EEPROM Section t D Read Once t D Program Flash (2 word) t D Program Flash (4 word) t D Program Once t D Program EEPROM (1 Byte) t D Program EEPROM (2 Byte) t D Erase All Blocks t D Erase Flash Block t D Erase Flash Sector t D Erase EEPROM Sector t D Unsecure Flash t D Verify Backdoor Access Key t D Set User Margin Level t C FLASH Program/erase endurance TL to

TH = -40 °C to 105 °C

C EEPROM Program/erase endurance TL

to TH = -40 °C to 105 °C

C Data retention at an average junction

temperature of T

= 85°C after up to

Javg

10,000 program/erase cycles

NVMBUS

NVMOP

VFYALL

RD1BLK

RD1SEC

DRD1SEC

RDONCE

PGM2

PGM4

PGMONCE

DPGM1

DPGM2

ERSALL

ERSBLK

ERSPG

DERSPG

UNSECU

VFYKEY

MLOADU

FLPE

D_ret

Typical

Max

Unit

1 — 25 MHz

0.8 — 1.05 MHz — — 17030 t — — 16977 t — — 843 t — — 517 t

cyc

0.10 0.10 0.11 ms — — 455 t

cyc

0.12 0.12 0.14 ms

0.20 0.21 0.24 ms

0.02 0.02 0.02 ms

0.17 0.18 0.20 ms

96.01 100.78 125.80 ms

95.98 100.75 125.76 ms

19.10 20.05 25.05 ms

4.81 5.05 6.30 ms

96.01 100.78 125.80 ms — — 469 t — — 442 t

cyc

10 k 100 k — Cycles

50 k 500 k — Cycles

15 100 — years

1. Minimun times are based on maxmum f

2. Typical times are based on typical f

NVMOP

3. Maximum times are based on minimum f

4. t

= 1 / f

cyc

NVMBUS

and maximum f

NVMOP

and maximum f

NVMOP

NVMBUS

Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section.

6.3 Analog

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

20 Freescale Semiconductor, Inc.

Page 21

6.3.1 ADC characteristics

Table 11. 5 V 12-bit ADC operating conditions

Characteri

stic

Supply

voltage

Ground voltage

Input

voltage

Input

capacitance

Input

resistance

Analog source

resistance

ADC

conversion

clock

frequency

Conditions Symb Min Typ

Absolute V

Delta to VDD (VDD-V

Delta to VSS (VSS-V

DDAD

SSA

)

) ΔV

12-bit mode

• f

ADCK ADCK

> 4 MHz < 4 MHz

10-bit mode

• f

ADCK ADCK

> 4 MHz < 4 MHz

8-bit mode

(all valid f

ADCK

)

High speed (ADLPC=0) f

Low power (ADLPC=1) 0.4 — 4.0

ΔV

ADCK

DDA

SSA

ADIN

Peripheral operating requirements and behaviors

Max Unit Comment

2.7 — 5.5 V —

-100 0 +100 mV

REFL

— V

REFH

— 4.5 5.5 pF

— 3 5 kΩ —

— —

2 5

kΩ External to

— — 10

0.4 — 8.0 MHz —

MCU

1. Typical values assume V

= 5.0 V, Temp = 25°C, f

DDA

reference only and are not tested in production.

1. DC potential difference.

=1.0 MHz unless otherwise stated. Typical values are for

ADCK

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Freescale Semiconductor, Inc. 21

Page 22

ADC SAR

ENGINE

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

Pad leakage

due to input protection

ADIN

INPUT PIN

ADIN

Peripheral operating requirements and behaviors

Figure 12. ADC input impedance equivalency diagram

Table 12. 12-bit ADC Characteristics (V

Characteristic Conditions C Symb Min Typ

Supply current ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 Supply current Stop, reset, module

off

T I

DDA

DDAD

DDA

Table continues on the next page...

REFH

= V

DDA

, V

— 133 — µA

— 218 — µA

— 327 — µA

— 582 990 µA

— 0.011 1 µA

REFL

= V

)

SSA

Max Unit

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

22 Freescale Semiconductor, Inc.

Page 23

Peripheral operating requirements and behaviors

Table 12. 12-bit ADC Characteristics (V

Characteristic Conditions C Symb Min Typ

ADC asynchronous clock source

High speed (ADLPC = 0)

Low power (ADLPC

P f

ADACK

REFH

= V

DDA

, V

REFL

= V

) (continued)

SSA

Max Unit

2 3.3 5 MHz

1.25 2 3.3

= 1)

Conversion time (including sample time)

Short sample (ADLSMP = 0)

Long sample

T t

ADC

— 20 — ADCK

cycles

— 40 —

(ADLSMP = 1)

Sample time Short sample

(ADLSMP = 0) Long sample

T t

ADS

— 3.5 — ADCK

cycles

— 23.5 —

(ADLSMP = 1)

Total unadjusted Error

12-bit mode T E

TUE

— ±5.0 — LSB 10-bit mode P — ±1.5 ±2.0 8-bit mode P — ±0.7 ±1.0

Differential NonLiniarity

12-bit mode T DNL — ±1.0 — LSB 10-bit mode P — ±0.25 ±0.5 8-bit mode

P — ±0.15 ±0.25

Integral Non-Linearity 12-bit mode T INL — ±1.0 — LSB

10-bit mode T — ±0.3 ±0.5 8-bit mode T — ±0.15 ±0.25

Zero-scale error 12-bit mode C E

— ±2.0 — LSB 10-bit mode P — ±0.25 ±1.0 8-bit mode P — ±0.65 ±1.0

Full-scale error

12-bit mode T E

— ±2.5 — LSB 10-bit mode T — ±0.5 ±1.0 8-bit mode T — ±0.5 ±1.0

Quantization error ≤12 bit modes D E Input leakage error6all modes D E

— — ±0.5 LSB

IIn * R

Temp sensor slope -40°C– 25°C D m — 3.266 — mV/°C

25°C– 125°C — 3.638 —

Temp sensor voltage 25°C D V

TEMP25

— 1.396 — V

1. Typical values assume V

= 5.0 V, Temp = 25°C, f

DDA

=1.0 MHz unless otherwise stated. Typical values are for

ADCK

reference only and are not tested in production.

2. 1 LSB = (V

REFH

- V

REFL

)/2

3. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes

3. V

ADIN

= V

DDA

4. IIn = leakage current (refer to DC characteristics)

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Freescale Semiconductor, Inc. 23

Page 24

Peripheral operating requirements and behaviors

6.3.2 Analog comparator (ACMP) electricals

Table 13. Comparator electrical specifications

C Characteristic Symbol Min Typical Max Unit

D Supply voltage V T Supply current (Operation mode) I D Analog input voltage V P Analog input offset voltage V C Analog comparator hysteresis (HYST=0) V C Analog comparator hysteresis (HYST=1) V T Supply current (Off mode) I

DDAOFF

C Propagation Delay t

DDA

AIN

AIO

2.7 — 5.5 V — 10 20 µA

VSS - 0.3 — V

DDA

— — 40 mV — 15 20 mV — 20 30 mV — 60 — nA — 0.4 1 µs

6.4 Communication interfaces

6.4.1 SPI switching specifications

The serial peripheral interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes slew rate control is disabled and high drive strength is enabled for SPI output pins.

Table 14. SPI master mode timing

Num.Symbol Description Min. Max. Unit Comment

1 f

2 t

SPSCK

3 t 4 t 5 t

WSPSCK

6 t 7 t 8 t 9 t

Lead

Lag

Frequency of operation f

SPSCK period 2 x t Enable lead time 1/2 — t Enable lag time 1/2 — t Clock (SPSCK) high or low time t

/2048 f

Bus

- 30 1024 x t

Bus

/2 Hz f

Bus

2048 x t

Bus

ns t

SPSCK

ns — Data setup time (inputs) 15 — ns — Data hold time (inputs) 0 — ns — Data valid (after SPSCK edge) — 25 ns —

Data hold time (outputs) 0 — ns —

Table continues on the next page...

is the bus

Bus

clock

= 1/f

Bus

— —

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

24 Freescale Semiconductor, Inc.

Page 25

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT

LSB OUT

BIT 6 . . . 1

(CPOL 0)

(CPOL

SPSCK

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

1. If configured as an output.

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

MASTER MSB OUT

MASTER LSB OUT

BIT 6 . . . 1

10 11

PORT DATA

(CPOL

PORT DATA

(OUTPUT)

10 11 4

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

SPSCK

Peripheral operating requirements and behaviors

Table 14. SPI master mode timing (continued)

Num.Symbol Description Min. Max. Unit Comment

10 t

11 t

Rise time input — t Fall time input

- 25 ns —

Bus

Rise time output — 25 ns — Fall time output

Figure 13. SPI master mode timing (CPHA=0)

Freescale Semiconductor, Inc. 25

Figure 14. SPI master mode timing (CPHA=1)

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 26

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

(INPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

SLAVE MSB

SLAVE LSB OUT

BIT 6 . . . 1

(CPOL 0)

(CPOL

NOTE: Not defined!

SEE

NOTE

see

note

SPSCK

Peripheral operating requirements and behaviors

Table 15. SPI slave mode timing

Num.Symbol Description Min. Max. Unit Comment

1 f

2 t

SPSCK

3 t 4 t 5 t

WSPSCK

6 t 7 t 8 t

9 t

10 t 11 t 12 t

13 t

Lead

Lag

dis

Frequency of operation 0 f

/4 Hz f

Bus

is the bus clock as

Bus

defined in .

SPSCK period 4 x t

Bus

Enable lead time 1 — t Enable lag time 1 — t Clock (SPSCK) high or low time t

- 30 — ns —

Bus

— ns t

Bus

= 1/f

— —

Data setup time (inputs) 15 — ns — Data hold time (inputs) 25 — ns — Slave access time — t

Bus

ns Time to data active from

high-impedance state

Slave MISO disable time — t

Bus

ns Hold time to high-

impedance state Data valid (after SPSCK edge) — 25 ns — Data hold time (outputs) 0 — ns — Rise time input — t

- 25 ns —

Bus

Fall time input Rise time output — 25 ns — Fall time output

Bus

26 Freescale Semiconductor, Inc.

Figure 15. SPI slave mode timing (CPHA = 0)

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 27

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT SLAVE LSB OUT

BIT 6 . . . 1

12 13

(CPOL 0)

(CPOL

(INPUT)

12 13

NOTE: Not defined!

SLAVE

see

note

SPSCK

Figure 16. SPI slave mode timing (CPHA=1)

Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to www.freescale.com and perform a keyword search for

the drawing’s document number:

If you want the drawing for this package Then use this document number

32-pin LQFP 98ASH70029A 44-pin LQFP 98ASS23225W 48-pin LQFP 98ASH00962A

64-pin QFP 98ASB42844B

64-pin LQFP 98ASS23234W

Freescale Semiconductor, Inc. 27

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 28

Pinout

8.1 Signal multiplexing and pin assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.

Table 16. Pin availability by package pin-count

Pin Number Lowest Priority <-- --> Highest

64-LQFP

64-QFP

1 1 1 1 PTD1 KBI1P1 FTM2CH3 MOSI1 — 2 2 2 2 PTD0 3 — — — PTH7 — — — — 4 — — — PTH6 — — — — 5 3 3 — PTE7 — TCLK2 — — 6 4 4 — PTH2 — BUSOUT — — 7 5 5 3 — — — — V 8 6 6 4 — — — V

9 7 7 5 — — — V 10 8 8 6 — — — — V 11 9 9 7 PTB7 — SCL — EXTAL 12 10 10 8 PTB6 — SDA — XTAL 13 11 11 — — — — — V 14 — — — PTH1 15 — — — PTH0 16 12 — — PTE6 — — — — 17 13 — — PTE5 — — — — 18 14 12 9 PTB5 19 15 13 10 PTB4 20 16 14 11 PTC3 FTM2CH3 — ADP11 — 21 17 15 12 PTC2 FTM2CH2 — ADP10 — 22 18 16 — PTD7 KBI1P7 TXD2 — — 23 19 17 — PTD6 KBI1P6 RXD2 — — 24 20 18 — PTD5 KBI1P5 — — — 25 21 19 13 PTC1 — FTM2CH1 ADP9 — 26 22 20 14 PTC0 — FTM2CH0 ADP8 — 27 — — — PTF7 — — ADP15 —

48-LQFP 44-LQFP 32-LQFP Port Pin Alt 1 Alt 2 Alt 3 Alt 4

KBI1P0 FTM2CH2 SPSCK1 —

DDA

SSA

— FTM2CH1 — — — FTM2CH0 — —

FTM2CH5 SS0 — — FTM2CH4 MISO0 — —

V V

REFH

REFL

Table continues on the next page...

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

28 Freescale Semiconductor, Inc.

Page 29

Table 16. Pin availability by package pin-count (continued)

Pin Number Lowest Priority <-- --> Highest

64-LQFP

64-QFP

28 — — — PTF6 — — ADP14 — 29 — — — PTF5 — — ADP13 — 30 — — — PTF4 — — ADP12 — 31 23 21 15 PTB3 KBI0P7 MOSI0 ADP7 — 32 24 22 16 PTB2 KBI0P6 SPSCK0 ADP6 — 33 25 23 17 PTB1 KBI0P5 TXD0 ADP5 — 34 26 24 18 PTB0 KBI0P4 RXD0 ADP4 — 35 — — — PTF3 — — — — 36 — — — PTF2 — — — — 37 27 25 19 PTA7 FTM2FAULT2 — ADP3 — 38 28 26 20 PTA6 FTM2FAULT1 — ADP2 — 39 29 — — PTE4 — — — — 40 30 27 — — — — — V 41 31 28 — — — — — V 42 — — — PTF1 — — — — 43 — — — PTF0 — — — — 44 32 29 — PTD4 KBI1P4 — — — 45 33 30 21 PTD3 KBI1P3 SS1 — — 46 34 31 22 PTD2 KBI1P2 MISO1 — — 47 35 32 23 PTA3 KBI0P3 TXD0 SCL — 48 36 33 24 PTA2 49 37 34 25 PTA1 KBI0P1 FTM0CH1 ACMP1 ADP1 50 38 35 26 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0 51 39 36 27 PTC7 — TxD1 — — 52 40 37 28 PTC6 — RxD1 — — 53 41 — — PTE3 — SS0 — — 54 42 38 — PTE2 — MISO0 — — 55 — — — PTG3 — — — — 56 — — — PTG2 — — — — 57 — — — PTG1 — — — — 58 — — — PTG0 — — — — 59 43 39 — PTE1 60 44 40 — PTE0 61 45 41 29 PTC5 — FTM1CH1 — — 62 46 42 30 PTC4 — FTM1CH0 RTCO — 63 47 43 31 PTA5 IRQ TCLK0 — RESET 64 48 44 32 PTA4 — ACMPO BKGD MS

48-LQFP 44-LQFP 32-LQFP Port Pin Alt 1 Alt 2 Alt 3 Alt 4

KBI0P2 RXD0 SDA —

— MOSI0 — — — SPSCK0 TCLK1 —

Pinout

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Freescale Semiconductor, Inc. 29

Page 30

Pinout

1. This is a high current drive pin when operated as output.

2. This is a true open-drain pin when operated as output.

When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software must clear any associated flags before interrupts are enabled. The table above illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. Disable all modules that share a pin before enabling another module.

Note

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

30 Freescale Semiconductor, Inc.

Page 31

8.2 Device pin assignment

PTF0

PTF2

PTB1/KBI0P5/TxD0/ADP5

PTB2/KBI0P6/SPSCK0/ADP6

PTF6/ADP14

PTC3/FTM2CH3/ADP11

2. True open drain pins

PTE6

PTG3

PTF1

PTF3

PTB0/KBI0P4/RxD0/ADP4

PTB3/KBI0P7/MOSI0/ADP7

PTF4/ADP12

PTF5/ADP13

PTF7/ADP15

PTA7/FTM2FAULT2/ADP3

PTA6/FTM2FAULT1/ADP2

PTE4

PTD4/KBI1P4

PTD3/KBI1P3/SS1

PTD2/KBI1P2/MISO1

PTA3/KBI0P3/TxD0/SCL

PTA2/KBI0P2/RxD0/SDA

PTG0

PTG2

PTG1

PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTC7/TxD1

PTC6/RxD1

PTE3/SS0

PTE2/MISO0

PTE1/MOSI0

PTE0/SPSCK0/TCLK1

PTC5/FTM1CH1

PTC4/FTM1CH0/RTCO

PTA5/IRQ/TCLK0/RESET

PTA4/ACMPO/BKGD/MS

PTD1/KBI1P1/FTM2CH3/MOSI1

PTD0/KBI1P0/FTM2CH2/SPSCK1

PTH7 PTH6

PTE7/TCLK2

PTH2/BUSOUT

DDA /V

REFH

SSA /V

REFL

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTH1/FTM2CH1

PTH0/FTM2CH0

PTE5

PTB5/FTM2CH5/SS0

PTB4/FTM2CH4/MISO0

PTC2/FTM2CH2/ADP10

PTD7/KBI1P7/TxD2

PTD6/KBI1P6/RxD2

PTD5/KBI1P5

PTC1/FTM2CH1/ADP9

PTC0/FTM2CH0/ADP8

1. High source/sink current pins

Pins in bold are not available on less pi n-count packages.

212223242526272829

303132

1 2 3 4 5 6 7 8 9

13 14 15 16

36 35 34 33

595860

Pinout

Figure 17. MC9S08PA60 64-pin QFP and LQFP package

Freescale Semiconductor, Inc. 31

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 32

PTB1/KBI0P5/TxD0/ADP5

PTB2/KBI0P6/SPSCK0/ADP6

PTC3/FTM2CH3/ADP11

2. True open drain pins

PTE6

PTB0/KBI0P4/RxD0/ADP4

PTB3/KBI0P7/MOSI0/ADP7

PTA7/FTM2FAULT2/ADP3

PTA6/FTM2FAULT1/ADP2

PTE4

PTD4/KBI1P4

PTD3/KBI1P3/SS1

PTD2/KBI1P2/MISO1

PTA3/KBI0P3/TxD0/SCL

PTA2/KBI0P2/RxD0/SDA

PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTC7/TxD1

PTC6/RxD1

PTE3/SS0

PTE2/MISO0

PTE1/MOSI0

PTE0/SPSCK0/TCLK1

PTC5/FTM1CH1

PTC4/FTM1CH0

PTA5/IRQ/TCLK0/RESET

PTA4/ACMPO/BKGD/MS

PTD1/KBI1P1/FTM2CH3/MOSI1

PTD0/KBI1P0/FTM2CH2/SPSCK1

PTE7/TCLK2

PTH2/BUSOUT

DDA /V

REFH

SSA /V

REFL

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTE5

PTB5/FTM2CH5/SS0

PTB4/FTM2CH4/MISO0

PTC2/FTM2CH2/ADP10

PTD7/KBI1P7/TxD2

PTD6/KBI1P6/RxD2

PTD5/KBI1P5

PTC1/FTM2CH1/ADP9

PTC0/FTM2CH0/ADP8

1. High source/sink current pins

Pins in bold are not available on less pi n-count packages.

212223

1 2 3 4 5 6 7 8 9

394038

36 35 34 33

Pinout

Figure 18. MC9S08PA60 48-pin LQFP package

32 Freescale Semiconductor, Inc.

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 33

PTB1/KBI0P5/TxD0/ADP5

PTB2/KBI0P6/SPSCK0/ADP6

PTC3/FTM2CH3/ADP11

2. True open drain pins

PTB0/KBI0P4/RxD0/ADP4

PTB3/KBI0P7/MOSI0/ADP7

PTA7/FTM2FAULT2/ADP3

PTA6/FTM2FAULT1/ADP2

PTD4/KBI1P4

PTD3/KBI1P3/SS1

PTD2/KBI1P2/MISO1

PTA2/KBI0P2/RxD0/SDA

PTA1/KBI0P1/FTM1CH0/ACMP1/ADP1

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTC7/TxD1

PTC6/RxD1

PTE2/MISO0

PTE1/MOSI0

PTE0/SPSCK0/TCLK1

PTC5/FTM1CH1

PTC4/FTM1CH0

PTA5/IRQ/TCLK0/RESET

PTA4/ACMPO/BKGD/MS

PTD1/KBI1P1/FTM2CH3/MOSI1

PTD0/KBI1P0/FTM2CH2/SPSCK1

PTE7/TCLK2

PTH2/BUSOUT

DDA /V

REFH

SSA /V

REFL

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB5/FTM2CH5/SS0

PTB4/FTM2CH4/MISO0

PTC2/FTM2CH2/ADP10

PTD7/KBI1P7/TxD2

PTD6/KBI1P6/RxD2

PTD5/KBI1P5

PTC1/FTM2CH1/ADP9

PTC0/FTM2CH0/ADP8

1. High source/sink current pins

Pins in bold are not available on less pi n-count packages.

1 2 3 4 5 6 7 8 9

394038

PTA3/KBI0P3/TxD0/SCL2

Pinout

Figure 19. MC9S08PA60 44-pin LQFP package

Freescale Semiconductor, Inc. 33

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Page 34

PTB1/KBI0P5/TxD0/ADP5

PTB2/KBI0P6/SPSCK0/ADP6

PTC3/FTM2CH3/ADP11

2. True open drain pins

PTB0/KBI0P4/RxD0/ADP4

PTB3/KBI0P7/MOSI0/ADP7

PTA7/FTM2FAULT2/ADP3

PTA6/FTM2FAULT1/ADP2

PTD3/KBI1P3/SS1

PTD2/KBI1P2/MISO1

PTA2/KBI0P2/RxD0/SDA

PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTC7/TxD1

PTC6/RxD1

PTC5/FTM1CH1

PTC4/FTM1CH0

PTA5/IRQ/TCLK0/RESET

PTA4/ACMPO/BKGD/MS

PTD1/KBI1P1/FTM2CH3/MOSI1

PTD0/KBI1P0/FTM2CH2/SPSCK1

DDA /V

REFH

SSA /V

REFL

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB5/FTM2CH5/SS0

PTB4/FTM2CH4/MISO0

PTC2/FTM2CH2/ADP10

PTC1/FTM2CH1/ADP9

PTC0/FTM2CH0/ADP8

1. High source/sink current pins

1 2 3 4 5 6 7 8

PTA3/KBI0P3/TxD0/SCL2

Revision history

9 Revision history

The following table provides a revision history for this document.

Rev. No. Date Substantial Changes

34 Freescale Semiconductor, Inc.

Figure 20. MC9S08PA60 32-pin LQFP package

1 10/2012 Initial public release

MC9S08PA60 Series Data Sheet, Rev. 1, 10/9/2012.

Table 17. Revision history

Page 35

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Document Number: MC9S08PA60 Rev. 1, 10/9/2012