Freescale MC9S08QE8, MC9S08QE4 Data Sheet

32-Pin LQFP
Case 873A

28-Pin SOIC
751F-05

16-Pin PDIP
648

16-Pin TSSOP
948F

20-Pin SOIC
751D-07

查询MC9S08QE8供应商

Freescale Semiconductor

Document Number: MC9S08QE8

Data Sheet: Advance Information

MC9S08QE8 Series

Covers: MC9S08QE8 and
MC9S08QE4

Features

• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of

–40°C to 85°C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources

•On-Chip Memory
– Flash read/program/erase over full operating voltage and

temperature
– Random-Access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and

flash contents

• Power-Saving Modes
– Two low power stop modes
– Reduced power wait mode
– Low power run and wait modes allow peripherals to run while

voltage regulator is in standby

– Peripheral clock gating register can disable clocks to unused

modules, thereby reducing currents

– Very low power external oscillator that can be used in stop2 or

stop3 modes to provide accurate clock source to real time counter

–6 μs typical wake-up time from stop3 mode

• Clock Source Options
– Oscillator (XOSC) — Loop-Control Pierce oscillator; crystal or

ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to
16 MHz

– Internal Clock Source (ICS) — Internal clock source module

containing a frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of internal reference
allows 0.2% resolution and 2% deviation over temperature and
voltage; supporting bus frequencies from 1 MHz to 10 MHz

• System Protection
– Watchdog computer operating properly (COP) reset with option to

run from dedicated 1 kHz internal clock source or bus clock
– Low-Voltage warning with interrupt
– Low-Voltage detection with reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection

• Development Support
– Single-Wire background debug interface
– Breakpoint capability to allow single breakpoint setting during

in-circuit debugging (plus two more breakpoints in on-chip debug
module)

– On-Chip in-circuit emulator (ICE) debug module containing two

comparators and nine trigger modes; eight deep FIFO for storing
change-of-flow addresses and event-only data; debug module
supports both tag and force breakpoints

This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.

© Freescale Semiconductor, Inc., 2007–2008. All rights reserved.

Preliminary
Subject to Change Without Notice

• Peripherals
– ADC — 10-channel, 12-bit resolution; 2.5 μs conversion time;

automatic compare function; 1.7 mV/°C temperature sensor;
internal bandgap reference channel; operation in stop3; fully
functional from 3.6 V to 1.8 V

– ACMPx — Two analog comparators with selectable interrupt on

rising, falling, or either edge of comparator output; compare
option to fixed internal bandgap reference voltage; outputs can be
optionally routed to TPM module; operation in stop3

– SCI — Full-Duplex non-return to zero (NRZ); LIN master

extended break generation; LIN slave extended break detection;
wake-up on active edge

– SPI — Full-Duplex or single-wire bidirectional; double-buffered

transmit and receive; master or slave mode; MSB-first or
LSB-first shifting

– IIC — Up to 100 kbps with maximum bus loading; multi-master

operation; programmable slave address; interrupt driven
byte-by-byte data transfer; supporting broadcast mode and 10-bit
addressing

– TPMx — Two 3-channel (TPM1 and TPM2); selectable input

capture, output compare, or buffered edge- or center-aligned
PWM on each channel

– RTC — (Real-time counter) 8-bit modulus counter with binary or

decimal based prescaler; external clock source for precise time
base, time-of-day, calendar or task scheduling functions; free
running on-chip low power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes

• Input/Output
– 26 GPIOs, one output-only pin and one input-only pin
– Eight KBI interrupts with selectable polarity
– Hysteresis and configurable pullup device on all input pins;

configurable slew rate and drive strength on all output pins.

• Package Options
– 32-pin LQFP, 28-pin SOIC, 20-pin SOIC, 16-pin PDIP,

16-pin TSSOP

Rev. 3, 1/2008

Table of Contents

1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 8

3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 8

3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . 9

3.5 ESD Protection and Latch-Up Immunity . . . . . . 10

3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 11

3.7 Supply Current Characteristics . . . . . . . . . . . . . 15

3.8 External Oscillator (XOSCVLP) Characteristics 16

3.9 Internal Clock Source (ICS) Characteristics . . . 17

3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 18

3.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 19

3.10.2TPM Module Timing . . . . . . . . . . . . . . . . 20

4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .29

5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .20

3.11 Analog Comparator (ACMP) Electricals . . . . . . .23

3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .24

3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .27

3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .28

3.14.1Conducted Transient Susceptibility. . . . . .28

5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . .29

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

Rev Date Description of Changes

2 7 Nov 2007 Initial preliminary product preview release.

3 22 Jan 2008 Initial public release.

Related Documentation

Find the most current versions of all documents at: http://www.freescale.com

Reference Manual (MC9S08QE8RM)

Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor2

1 MCU Block Diagram

IIC MODULE (IIC)

USER FLASH

USER RAM

HCS08 CORE

CPU

BDC

PTB7/SCL/EXTAL

PORT B

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

COP

LVD

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

PTB4/TPM2CH1/MISO

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

VOLTAGE REGULATOR

PORT A

PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–

ANALOG COMPARATOR

(ACMP1)

LOW-POWER OSCILLATOR

20 MHz INTERNAL CLOCK

SOURCE (ICS)

31.25 kHz to 38.4 kHz
1 MHz to 16 MHz

(XOSCVLP)

V

SS

V

DD

ANALOG-TO-DIGITAL

CONVERTER (ADC12)

12-BIT

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PORT C

PTC7/ACMP2–

PTC6/ACMP2+

PTC5/ACMP2O

PTC4

REAL-TIME COUNTER

(MC9S08QE8 = 8192 BYTES)
(MC9S08QE4 = 4096 BYTES)

(MC9S08QE8 = 512 BYTES)
(MC9S08QE4 = 256 BYTES)

PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA4/ACMP1O/BKGD/MS

PTA5/IRQ/TCLK/RESET

IRQ

pins not available on 16-pin packages
pins not available on 16-pin or 20-pin packages

(RTC)

ANALOG COMPARATOR

(ACMP2)

PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8

PTC3

PTC2

PTC1/TPM2CH2

PTC0/TPM1CH2

PORT D

PTD3

PTD2

PTD1

PTD0

V

SSA/VREFL

V

DDA/VREFH

pins not available on 16-pin, 20-pin or 28-pin packages

BKGD/MS

IRQ

EXTAL

XTAL

V

REFL

V

REFH

SCL

SDA

SERIAL PERIPHERAL

INTERFACE MODULE (SPI)

MISO
MOSI
SPSCK

SS

INTERFACE MODULE (SCI)

SERIAL COMMUNICATIONS

RxD
TxD

DEBUG MODULE (DBG)

TCLK
TPM2CH0

TPM2CH1

ACMP1O
ACMP1–
ACMP1+

ACMP2O
ACMP2–
ACMP2+

ADP9–ADP0

TPM2CH2

TCLK
TPM1CH0

TPM1CH1

TPM1CH2

16-BIT TIMER PWM

MODULE (TPM1)

16-BIT TIMER PWM

MODULE (TPM2)

KEYBOARD INTERRUPT

MODULE (KBI)

KBIP7–KBIP0

V

SSA

V

DDA

V

SSA

V

DDA

Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device.

When PTA4 is configured as BKGD, pin becomes bi-directional.
For the 16-pin and 20-pin packages, V

SSA/VREFL

and V

DDA/VREFH

are double bonded to VSS and VDD respectively.

The block diagram, Figure 1, shows the structure of MC9S08QE8 series MCU.

MCU Block Diagram

Figure 1. MC9S08QE8 Series Block Diagram

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 3

Subject to Change Without Notice

Preliminary

Pin Assignments

PTD3

V

DDA/VREFH

1

2

3

4

5

6

7

8

V

SSA/VREFL

V

SS

19

18

17

10

11

12 13 14

15

9

24

32

16

252627

V

DD

20

21

22

23

31 30 29 28

PTA5/IRQ/TCLK/RESET

PTA4/ACMP1O/BKGD/MS

PTA7/TPM2CH2/ADP9

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTC0/TPM1CH2

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PTA2/KBIP2/SDA/ADP2

PTA3/KBIP3/SCL/ADP3

PTA1/KBIP1/TPM2CH0ADP1/ACMP1–

PTC1/TPM2CH2

PTC2

PTB4/TPM2CH1/MISO

PTC7/ACMP2–

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

PTC5/ACMP2O

PTC4

PTC3

PTD0

PTD1

PTB7/SCL/EXTAL

PTD2

PTA6/TPM1CH2/ADP8

PTC6/ACMP2+

Pins shown in bold type are lost in the next lower pin count package.

2 Pin Assignments

This section shows the pin assignments for the MC9S08QE8 series devices.

Figure 2. MC9S08QE8 Series in 32-LQFP

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor4

Pin Assignments

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PTC0/TPM1CH2

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PTA2/KBIP2/SDA/ADP2

PTA3/KBIP3/SCL/ADP3

PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA7/TPM2CH2/ADP9

PTA6/TPM1CH2/ADP8

PTB4/TPM2CH1/MISO

PTC3

PTA5/IRQ/TCLK/RESET

PTA4/ACMP1O/BKGD/MS

V

DD

V

SS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

PTC1/TPM2CH2

PTC6/ACMP2+

PTC7/ACMP2–

PTC2

PTC4

PTC5/ACMP2O

V

DDA/VREFH

V

SSA/VREFL

Pins shown in bold type are lost in the next lower pin count package.

1

2

3

4

5

6

7

8

9

10

11

13

14

PTC2

PTB4/TPM2CH1/MISO

PTC3

PTC0/TPM1CH2

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PTA2/KBIP2/SDA/ADP2

PTA3/KBIP3/SCL/ADP3

PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTC1/TPM2CH2

PTA5/IRQ/TCLK/RESET

PTA4/ACMP1O/BKGD/MS

V

DD

V

SS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

15

16

17

18

19

20

12

Pins shown in bold type are lost in the next lower pin count package.

Freescale Semiconductor 5

Figure 3. MC9S08QE8 Series in 28-pin SOIC Package

Figure 4. MC9S08QE8 Series in 20-pin SOIC Package

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Pin Assignments

1

2

3

4

5

6

7

8

9

10

11

13

14

PTB4/TPM2CH1/MISO

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PTA2/KBIP2/SDA/ADP2

PTA3/KBIP3/SCL/ADP3

PTA1/KBIP1/TPM2CH0ADP1/ACMP1–

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA5/IRQ/TCLK/RESET

PTA4/ACMP1O/BKGD/MS

V

DD

V

SS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

15

16

12

Figure 5. MC9S08QE8 Series in 16-pin PDIP and TSSOP Packages

MC9S08QE8 Series, Rev. 3

Subject to Change Without Notice

Preliminary

Freescale Semiconductor6

Table 2-1. Pin Availability by Package Pin-Count

Pin Number <-- Lowest Priority --> Highest

32 28 20 16 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

1 ———PTD1

2 ———PTD0

3533 V

46—— V

57—— V

6844 V

7955PTB7 SCL

8106 6PTB6 SDA

1

1

9 11 7 7 PTB5 TPM1CH1 SS

10 12 8 8 PTB4 TPM2CH1 MISO

11 13 9 — PTC3

12 14 10 — PTC2

13 15 11 — PTC1 TPM2CH2

14 16 12 — PTC0 TPM1CH2

2

3

15 17 13 9 PTB3 KBIP7 MOSI ADP7

16 18 14 10 PTB2 KBIP6 SPSCK ADP6

17 19 15 11 PTB1 KBIP5 TxD ADP5

18 20 16 12 PTB0 KBIP4 RxD ADP4

19 21 — — PTA7 TPM2CH2

20 22 — — PTA6 TPM1CH2

2

3

ADP9

ADP8

21———PTD3

22———PTD2

23 23 17 13 PTA3 KBIP3 SCL

24 24 18 14 PTA2 KBIP2 SDA

1

1

25 25 19 15 PTA1 KBIP1 TPM2CH0 ADP1

26 26 20 16 PTA0 KBIP0 TPM1CH0 ADP0

ADP3

ADP2

4

4

27 27 — — PTC7 ACMP2–

28 28 — — PTC6 ACMP2+

29 1 — — PTC5 ACMP2O

30 2 — — PTC4

31 3 1 1 PTA5 IRQ TCLK RESET

32 4 2 2 PTA4 ACMP1O BKGD MS

1

IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2, default reset locations
are PTA3 and PTA2.

2

TPM2CH2 pin can be repositioned using TPM2CH2PS in SOPT2, default reset location is
PTA7.

3

TPM1CH2 pin can be repositioned using TPM1CH2PS in SOPT2, default reset location is
PTA6.

4

If ADC and ACMP1 are enabled, both modules will have access to the pin.

DD

DDA/VREFH

SSA/VREFL

SS

EXTAL

XTAL

ACMP1–

ACMP1+

Pin Assignments

4

4

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 7

Preliminary

Subject to Change Without Notice

Electrical Characteristics

3 Electrical Characteristics

3.1 Introduction

This section contains electrical and timing specifications for the MC9S08QE8 series of microcontrollers available at the time
of publication.

3.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 2. Parameter Classifications

Those parameters are guaranteed during production testing on each individual device.

P

Those parameters are achieved by the design characterization by measuring a statistically relevant

C

sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this

T

category.

Those parameters are derived mainly from simulations.

D

NOTE

The classification is shown in the column labeled “C” in the parameter
tables where appropriate.

3.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V

or VDD) or the programmable pullup resistor associated with the pin is enabled.

SS

Table 3. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage V

Maximum current into V

Digital input voltage V

Instantaneous maximum current

Single pin limit (applies to all port pins)

Storage temperature range T

DD

1, 2, 3

DD

I

DD

In

I

D

stg

–0.3 to 3.8 V

120 mA

–0.3 to VDD+0.3 V

±25 mA

–55 to 150 °C

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor8

Electrical Characteristics

1

Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.

2

All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.

3

Power supply must maintain regulation within operating V

range during instantaneous and

DD

operating maximum current conditions. If positive injection current (VIn > VDD) is greater than

, the injection current may flow out of VDD and could result in external power supply going

I

DD

out of regulation. Ensure external V

load will shunt current greater than maximum injection

DD

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).

3.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P
the difference between actual pin voltage and V

or VDD and multiply by the pin current for each I/O pin. Except in cases of

SS

unusually high pin current (heavy loads), the difference between pin voltage and V

Table 4. Thermal Characteristics

Rating Symbol Value Unit

into account in power calculations, determine

I/O

or VDD will be very small.

SS

Operating temperature range
(packaged)

Maximum junction temperature T

Thermal resistance

Single-layer board

32-pin LQFP

28-pin SOIC 57

20-pin SOIC 71

16-pin PDIP 64

16-pin TSSOP 108

Thermal resistance

Four-layer board

32-pin LQFP

28-pin SOIC 42

20-pin SOIC 52

16-pin PDIP 47

16-pin TSSOP 78

The average chip-junction temperature (T

T

A

JM

θ

JA

θ

JA

) in °C can be obtained from:

J

TL to T

H

–40 to 85

95 °C

66

47

°C

°C/W

°C/W

T

= TA + (PD × θJA) Eqn. 1

J

where:

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 9

Subject to Change Without Notice

Preliminary

Electrical Characteristics

TA = Ambient temperature, °C
θ

= Package thermal resistance, junction-to-ambient, °C/W

JA

P

= P

D

P

int

P

I/O

For most applications, P

+ P

int

I/O

= IDD × VDD, Watts — chip internal power

= Power dissipation on input and output pins — user determined

<< P

I/O

and can be neglected. An approximate relationship between PD and TJ (if P

int

is:

P

= K ÷ (TJ + 273°C) Eqn. 2

D

Solving Equation 1 and Equation 2 for K gives:

is neglected)

I/O

K = P

× (TA + 273°C) + θJA × (PD)

D

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
for any value of T

. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively

A

.

A

2

(at equilibrium)

D

Eqn. 3

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.

Table 5. ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Human

Body

Series resistance R1 1500

Storage capacitance C 100 pF

Number of pulses per pin — 3 —

Ω

Series resistance R1 0

Machine

Latch-up

Storage capacitance C 200 pF

Number of pulses per pin — 3 —

Minimum input voltage limit — –2.5 V

Maximum input voltage limit — 7.5 V

Table 6. ESD and Latch-Up Protection Characteristics

No.

1 Human body model (HBM)

2 Machine model (MM)

Rating

1

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Symbol Min Max Unit

V

HBM

V

MM

Ω

±2000 — V

±200 — V

Freescale Semiconductor10

Electrical Characteristics

Table 6. ESD and Latch-Up Protection Characteristics (continued)

3 Charge device model (CDM)

4

1

Parameter is achieved by design characterization on a small sample size from typical devices

Latch-up current at TA = 85°CI

V

CDM

LAT

±500 — V

±100 — mA

under typical conditions unless otherwise noted.

3.6 DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 7. DC Characteristics

Num C Characteristic Symbol Condition Min. Typical

1 Operating Voltage 1.8 3.6 V

C

2

Output high
voltage

C

Output high

D

3

current

Max total I

C

4

Output low
voltage

C

Output low

D

current

P

6

7

8C

Input high
voltage

CV

P

Input low
voltage

CV

Input
hysteresis

Max total I

Input

9P

leakage
current

All I/O pins,

low-drive strength

All I/O pins,

high-drive strength

for all ports I

OH

All I/O pins,

low-drive strength

All I/O pins,

high-drive strength

for all ports I

OL

all digital inputs V

all digital inputs V

all digital inputs V

all input only pins

(Per pin)

V

OH

OHT

V

OL

OLT

IH

IL

hys

|IIn|VIn = VDD or V

VDD > 1.8 V,

= –2 mA

I

Load

VDD > 2.7 V,

I

= –10 mA

Load

VDD > 1.8V,

I

= –2 mA

Load

– 0.5 — —

V

DD

– 0.5 — —

V

DD

V

– 0.5 — —

DD

———100mA

VDD > 1.8 V,

I

= 0.6 mA

Load

V

> 2.7 V,

DD

I

= 10 mA

Load

> 1.8 V,

V

DD

= 3 mA

I

Load

——0.5

——0.5

——0.5

———100mA5

VDD > 2.7 V 0.70 x V

> 1.8 V 0.85 x V

DD

DD

DD

VDD > 2.7 V — — 0.35 x V

> 1.8 V — — 0.30 x V

DD

— 0.06 x V

SS

DD

—0.1 1μA

Hi-Z

10 P

(off-state)
leakage

all input/output

(per pin)

|V

|I

OZ

= V

or V

In

DD

SS

—0.1 1μA

current

all digital inputs, when

enabled (all I/O pins other

than

PTA5/IRQ/TCLK/RESET

R

PU,

R

PD

—

17.5 — 52.5 kΩ

11a P

Pullup,
Pulldown
resistors

1

Max. Unit

——

——

DD

DD

——mV

VP

VP

V

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 11

Preliminary

Subject to Change Without Notice

Electrical Characteristics

PULLUP RESISTOR TYPICALS

V

DD

(V)

PULL-UP RESISTOR (kΩ)

20

25

30

35

40

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

25°C

85°C

–40°C

PULLDOWN RESISTOR TYPICALS

V

DD

(V)

PULLDOWN RESISTANCE (k

Ω

)

20

25

30

35

40

1.8 2.3 2.8 3.3

25°C

85°C

–40°C

3.6

Table 7. DC Characteristics (continued)

1.84

1.92

1

Max. Unit

1.88

1.96

Num C Characteristic Symbol Condition Min. Typical

R

Pullup,

11b C

Pulldown

(PTA5/IRQ/TCLK/RESET)

resistors

Single pin limit

12 C

DC injection

3, 4,

current

5

Total MCU limit, includes

sum of all stressed pins

13 C Input Capacitance, all pins C

14 C RAM retention voltage V

15 C POR re-arm voltage

6

16 D POR re-arm time t

17 P Low-voltage detection threshold V

18 P Low-voltage warning threshold V

19 P

20 P Bandgap Voltage Reference

1

Typical values are measured at 25°C. Characterized, not tested

2

The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when

Low-voltage inhibit reset/recover
hysteresis

7

PU,

R

PD

(Note2)

I

IC

In

RAM

V

POR

POR

LV D

LV W

V

hys

V

BG

V

IN

— 17.5 — 52.5 kΩ

–0.2 — 0.2 mA

< VSS, V

IN

> V

DD

–5 — 5 mA

———8pF

——0.61.0V

— 0.9 1.4 2.0 V

—10——μs

VDD falling
VDD rising

VDD falling
VDD rising

1.80

1.88

2.08 2.14 2.24 V

——80—mV

— 1.151.171.18 V

measured externally on the pin.

3

All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.

4

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.

5

Power supply must maintain regulation within operating V

range during instantaneous and operating maximum current

DD

conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external V

load will shunt current greater than maximum

DD

injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).

6

Maximum is highest voltage that POR is guaranteed.

7

Factory trimmed at VDD = 3.0 V, Temp = 25 °C

V

Figure 6. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor12

Electrical Characteristics

TYPICAL VOL VS IOL AT V

DD

= 3.0 V

I

OL

(mA)

V

OL

(V)

0

0.2

0.4

0.6

0.8

1

1.2

0 5 10 15 20

TYPICAL VOL VS V

DD

VDD (V)

V

OL

(V)

0

0.05

0.1

0.15

0.2

1234

25°C

85°C

–40°C

25°C,

I

OL

= 2 mA

85°C,

I

OL

= 2 mA

–40°C,

I

OL

= 2 mA

TYPICAL VOL VS IOL AT V

DD

= 3.0 V

I

OL

(mA)

V

OL

(V)

0

0.2

0.4

0.6

0.8

1

0102030

TYPICAL VOL VS V

DD

VDD (V)

V

OL

(V)

0

0.1

0.2

0.3

0.4

1234

IOL = 6 mA

I

OL

= 3 mA

I

OL

= 10 mA

25°C

85°C

–40°C

25°C

85°C

–40°C

TYPICAL V

DD

– VOH VS IOH AT V

DD

= 3.0 V

I

OH

(mA))

0

0.2

0.4

0.6

0.8

1

1.2

–20–15–10–50

TYPICAL V

DD

– VOH VS VDD AT SPEC I

OH

VDD (V)

V

DD

– V

OH

(V)

0

0.05

0.1

0.15

0.2

0.25

1234

V

DD

– V

OH

(V)

25°C

85°C

–40°C

25°C,

I

OH

= 2 mA

85°C,

I

OH

= 2 mA

–40°C,

I

OH

= 2 mA

Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)

Figure 8. Typical Low-Side Driver (Sink) Characteristics

Figure 9. Typical High-Side (Source) Characteristics

Freescale Semiconductor 13

Subject to Change Without Notice

MC9S08QE8 Series, Rev. 3

Preliminary

— High Drive (PTxDSn = 1)

— Low Drive (PTxDSn = 0)

Electrical Characteristics

TYPICAL V

DD

– VOH VS IOH AT V

DD

= 3.0 V

I

OH

(mA)

0

0.2

0.4

0.6

0.8

–30–25–20–15–10–50

TYPICAL VDD – VOH VS V

DD

AT SPEC I

OH

VDD (V)

V

DD

– V

OH

(V)

0

0.1

0.2

0.3

0.4

1234

I

OH

= –10 mA

I

OH

= –6 mA

I

OH

= –3 mA

V

DD

– V

OH

(V)

25°C

85°C

–40°C

25°C

85°C

–40°C

Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor14