Freescale MC9S08QE8, MC9S08QE4 Data Sheet

32-Pin LQFP
Case 873A

28-Pin SOIC
751F-05

16-Pin PDIP
648

16-Pin TSSOP
948F

20-Pin SOIC
751D-07

查询MC9S08QE8供应商

Freescale Semiconductor

Document Number: MC9S08QE8

Data Sheet: Advance Information

MC9S08QE8 Series

Covers: MC9S08QE8 and
MC9S08QE4

Features

• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of

–40°C to 85°C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources

•On-Chip Memory
– Flash read/program/erase over full operating voltage and

temperature
– Random-Access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and

flash contents

• Power-Saving Modes
– Two low power stop modes
– Reduced power wait mode
– Low power run and wait modes allow peripherals to run while

voltage regulator is in standby

– Peripheral clock gating register can disable clocks to unused

modules, thereby reducing currents

– Very low power external oscillator that can be used in stop2 or

stop3 modes to provide accurate clock source to real time counter

–6 μs typical wake-up time from stop3 mode

• Clock Source Options
– Oscillator (XOSC) — Loop-Control Pierce oscillator; crystal or

ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to
16 MHz

– Internal Clock Source (ICS) — Internal clock source module

containing a frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of internal reference
allows 0.2% resolution and 2% deviation over temperature and
voltage; supporting bus frequencies from 1 MHz to 10 MHz

• System Protection
– Watchdog computer operating properly (COP) reset with option to

run from dedicated 1 kHz internal clock source or bus clock
– Low-Voltage warning with interrupt
– Low-Voltage detection with reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection

• Development Support
– Single-Wire background debug interface
– Breakpoint capability to allow single breakpoint setting during

in-circuit debugging (plus two more breakpoints in on-chip debug
module)

– On-Chip in-circuit emulator (ICE) debug module containing two

comparators and nine trigger modes; eight deep FIFO for storing
change-of-flow addresses and event-only data; debug module
supports both tag and force breakpoints

This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.

© Freescale Semiconductor, Inc., 2007–2008. All rights reserved.

Preliminary
Subject to Change Without Notice

• Peripherals
– ADC — 10-channel, 12-bit resolution; 2.5 μs conversion time;

automatic compare function; 1.7 mV/°C temperature sensor;
internal bandgap reference channel; operation in stop3; fully
functional from 3.6 V to 1.8 V

– ACMPx — Two analog comparators with selectable interrupt on

rising, falling, or either edge of comparator output; compare
option to fixed internal bandgap reference voltage; outputs can be
optionally routed to TPM module; operation in stop3

– SCI — Full-Duplex non-return to zero (NRZ); LIN master

extended break generation; LIN slave extended break detection;
wake-up on active edge

– SPI — Full-Duplex or single-wire bidirectional; double-buffered

transmit and receive; master or slave mode; MSB-first or
LSB-first shifting

– IIC — Up to 100 kbps with maximum bus loading; multi-master

operation; programmable slave address; interrupt driven
byte-by-byte data transfer; supporting broadcast mode and 10-bit
addressing

– TPMx — Two 3-channel (TPM1 and TPM2); selectable input

capture, output compare, or buffered edge- or center-aligned
PWM on each channel

– RTC — (Real-time counter) 8-bit modulus counter with binary or

decimal based prescaler; external clock source for precise time
base, time-of-day, calendar or task scheduling functions; free
running on-chip low power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes

• Input/Output
– 26 GPIOs, one output-only pin and one input-only pin
– Eight KBI interrupts with selectable polarity
– Hysteresis and configurable pullup device on all input pins;

configurable slew rate and drive strength on all output pins.

• Package Options
– 32-pin LQFP, 28-pin SOIC, 20-pin SOIC, 16-pin PDIP,

16-pin TSSOP

Rev. 3, 1/2008

Table of Contents

1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 8

3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 8

3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . 9

3.5 ESD Protection and Latch-Up Immunity . . . . . . 10

3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 11

3.7 Supply Current Characteristics . . . . . . . . . . . . . 15

3.8 External Oscillator (XOSCVLP) Characteristics 16

3.9 Internal Clock Source (ICS) Characteristics . . . 17

3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 18

3.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 19

3.10.2TPM Module Timing . . . . . . . . . . . . . . . . 20

4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .29

5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .20

3.11 Analog Comparator (ACMP) Electricals . . . . . . .23

3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .24

3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .27

3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .28

3.14.1Conducted Transient Susceptibility. . . . . .28

5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . .29

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

Rev Date Description of Changes

2 7 Nov 2007 Initial preliminary product preview release.

3 22 Jan 2008 Initial public release.

Related Documentation

Find the most current versions of all documents at: http://www.freescale.com

Reference Manual (MC9S08QE8RM)

Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor2

1 MCU Block Diagram

IIC MODULE (IIC)

USER FLASH

USER RAM

HCS08 CORE

CPU

BDC

PTB7/SCL/EXTAL

PORT B

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

COP

LVD

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

PTB4/TPM2CH1/MISO

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

VOLTAGE REGULATOR

PORT A

PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–

ANALOG COMPARATOR

(ACMP1)

LOW-POWER OSCILLATOR

20 MHz INTERNAL CLOCK

SOURCE (ICS)

31.25 kHz to 38.4 kHz
1 MHz to 16 MHz

(XOSCVLP)

V

SS

V

DD

ANALOG-TO-DIGITAL

CONVERTER (ADC12)

12-BIT

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PORT C

PTC7/ACMP2–

PTC6/ACMP2+

PTC5/ACMP2O

PTC4

REAL-TIME COUNTER

(MC9S08QE8 = 8192 BYTES)
(MC9S08QE4 = 4096 BYTES)

(MC9S08QE8 = 512 BYTES)
(MC9S08QE4 = 256 BYTES)

PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA4/ACMP1O/BKGD/MS

PTA5/IRQ/TCLK/RESET

IRQ

pins not available on 16-pin packages
pins not available on 16-pin or 20-pin packages

(RTC)

ANALOG COMPARATOR

(ACMP2)

PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8

PTC3

PTC2

PTC1/TPM2CH2

PTC0/TPM1CH2

PORT D

PTD3

PTD2

PTD1

PTD0

V

SSA/VREFL

V

DDA/VREFH

pins not available on 16-pin, 20-pin or 28-pin packages

BKGD/MS

IRQ

EXTAL

XTAL

V

REFL

V

REFH

SCL

SDA

SERIAL PERIPHERAL

INTERFACE MODULE (SPI)

MISO
MOSI
SPSCK

SS

INTERFACE MODULE (SCI)

SERIAL COMMUNICATIONS

RxD
TxD

DEBUG MODULE (DBG)

TCLK
TPM2CH0

TPM2CH1

ACMP1O
ACMP1–
ACMP1+

ACMP2O
ACMP2–
ACMP2+

ADP9–ADP0

TPM2CH2

TCLK
TPM1CH0

TPM1CH1

TPM1CH2

16-BIT TIMER PWM

MODULE (TPM1)

16-BIT TIMER PWM

MODULE (TPM2)

KEYBOARD INTERRUPT

MODULE (KBI)

KBIP7–KBIP0

V

SSA

V

DDA

V

SSA

V

DDA

Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device.

When PTA4 is configured as BKGD, pin becomes bi-directional.
For the 16-pin and 20-pin packages, V

SSA/VREFL

and V

DDA/VREFH

are double bonded to VSS and VDD respectively.

The block diagram, Figure 1, shows the structure of MC9S08QE8 series MCU.

MCU Block Diagram

Figure 1. MC9S08QE8 Series Block Diagram

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 3

Subject to Change Without Notice

Preliminary

Pin Assignments

PTD3

V

DDA/VREFH

1

2

3

4

5

6

7

8

V

SSA/VREFL

V

SS

19

18

17

10

11

12 13 14

15

9

24

32

16

252627

V

DD

20

21

22

23

31 30 29 28

PTA5/IRQ/TCLK/RESET

PTA4/ACMP1O/BKGD/MS

PTA7/TPM2CH2/ADP9

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTC0/TPM1CH2

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PTA2/KBIP2/SDA/ADP2

PTA3/KBIP3/SCL/ADP3

PTA1/KBIP1/TPM2CH0ADP1/ACMP1–

PTC1/TPM2CH2

PTC2

PTB4/TPM2CH1/MISO

PTC7/ACMP2–

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

PTC5/ACMP2O

PTC4

PTC3

PTD0

PTD1

PTB7/SCL/EXTAL

PTD2

PTA6/TPM1CH2/ADP8

PTC6/ACMP2+

Pins shown in bold type are lost in the next lower pin count package.

2 Pin Assignments

This section shows the pin assignments for the MC9S08QE8 series devices.

Figure 2. MC9S08QE8 Series in 32-LQFP

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor4

Pin Assignments

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PTC0/TPM1CH2

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PTA2/KBIP2/SDA/ADP2

PTA3/KBIP3/SCL/ADP3

PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA7/TPM2CH2/ADP9

PTA6/TPM1CH2/ADP8

PTB4/TPM2CH1/MISO

PTC3

PTA5/IRQ/TCLK/RESET

PTA4/ACMP1O/BKGD/MS

V

DD

V

SS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

PTC1/TPM2CH2

PTC6/ACMP2+

PTC7/ACMP2–

PTC2

PTC4

PTC5/ACMP2O

V

DDA/VREFH

V

SSA/VREFL

Pins shown in bold type are lost in the next lower pin count package.

1

2

3

4

5

6

7

8

9

10

11

13

14

PTC2

PTB4/TPM2CH1/MISO

PTC3

PTC0/TPM1CH2

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PTA2/KBIP2/SDA/ADP2

PTA3/KBIP3/SCL/ADP3

PTA1/KBIP1/TPM2CH0/ADP1/ACMP1–

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTC1/TPM2CH2

PTA5/IRQ/TCLK/RESET

PTA4/ACMP1O/BKGD/MS

V

DD

V

SS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

15

16

17

18

19

20

12

Pins shown in bold type are lost in the next lower pin count package.

Freescale Semiconductor 5

Figure 3. MC9S08QE8 Series in 28-pin SOIC Package

Figure 4. MC9S08QE8 Series in 20-pin SOIC Package

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Pin Assignments

1

2

3

4

5

6

7

8

9

10

11

13

14

PTB4/TPM2CH1/MISO

PTB3/KBIP7/MOSI/ADP7

PTB2/KBIP6/SPSCK/ADP6

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PTA2/KBIP2/SDA/ADP2

PTA3/KBIP3/SCL/ADP3

PTA1/KBIP1/TPM2CH0ADP1/ACMP1–

PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+

PTA5/IRQ/TCLK/RESET

PTA4/ACMP1O/BKGD/MS

V

DD

V

SS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB5/TPM1CH1/SS

15

16

12

Figure 5. MC9S08QE8 Series in 16-pin PDIP and TSSOP Packages

MC9S08QE8 Series, Rev. 3

Subject to Change Without Notice

Preliminary

Freescale Semiconductor6

Table 2-1. Pin Availability by Package Pin-Count

Pin Number <-- Lowest Priority --> Highest

32 28 20 16 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

1 ———PTD1

2 ———PTD0

3533 V

46—— V

57—— V

6844 V

7955PTB7 SCL

8106 6PTB6 SDA

1

1

9 11 7 7 PTB5 TPM1CH1 SS

10 12 8 8 PTB4 TPM2CH1 MISO

11 13 9 — PTC3

12 14 10 — PTC2

13 15 11 — PTC1 TPM2CH2

14 16 12 — PTC0 TPM1CH2

2

3

15 17 13 9 PTB3 KBIP7 MOSI ADP7

16 18 14 10 PTB2 KBIP6 SPSCK ADP6

17 19 15 11 PTB1 KBIP5 TxD ADP5

18 20 16 12 PTB0 KBIP4 RxD ADP4

19 21 — — PTA7 TPM2CH2

20 22 — — PTA6 TPM1CH2

2

3

ADP9

ADP8

21———PTD3

22———PTD2

23 23 17 13 PTA3 KBIP3 SCL

24 24 18 14 PTA2 KBIP2 SDA

1

1

25 25 19 15 PTA1 KBIP1 TPM2CH0 ADP1

26 26 20 16 PTA0 KBIP0 TPM1CH0 ADP0

ADP3

ADP2

4

4

27 27 — — PTC7 ACMP2–

28 28 — — PTC6 ACMP2+

29 1 — — PTC5 ACMP2O

30 2 — — PTC4

31 3 1 1 PTA5 IRQ TCLK RESET

32 4 2 2 PTA4 ACMP1O BKGD MS

1

IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2, default reset locations
are PTA3 and PTA2.

2

TPM2CH2 pin can be repositioned using TPM2CH2PS in SOPT2, default reset location is
PTA7.

3

TPM1CH2 pin can be repositioned using TPM1CH2PS in SOPT2, default reset location is
PTA6.

4

If ADC and ACMP1 are enabled, both modules will have access to the pin.

DD

DDA/VREFH

SSA/VREFL

SS

EXTAL

XTAL

ACMP1–

ACMP1+

Pin Assignments

4

4

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 7

Preliminary

Subject to Change Without Notice

Electrical Characteristics

3 Electrical Characteristics

3.1 Introduction

This section contains electrical and timing specifications for the MC9S08QE8 series of microcontrollers available at the time
of publication.

3.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 2. Parameter Classifications

Those parameters are guaranteed during production testing on each individual device.

P

Those parameters are achieved by the design characterization by measuring a statistically relevant

C

sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this

T

category.

Those parameters are derived mainly from simulations.

D

NOTE

The classification is shown in the column labeled “C” in the parameter
tables where appropriate.

3.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V

or VDD) or the programmable pullup resistor associated with the pin is enabled.

SS

Table 3. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage V

Maximum current into V

Digital input voltage V

Instantaneous maximum current

Single pin limit (applies to all port pins)

Storage temperature range T

DD

1, 2, 3

DD

I

DD

In

I

D

stg

–0.3 to 3.8 V

120 mA

–0.3 to VDD+0.3 V

±25 mA

–55 to 150 °C

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor8

Electrical Characteristics

1

Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.

2

All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.

3

Power supply must maintain regulation within operating V

range during instantaneous and

DD

operating maximum current conditions. If positive injection current (VIn > VDD) is greater than

, the injection current may flow out of VDD and could result in external power supply going

I

DD

out of regulation. Ensure external V

load will shunt current greater than maximum injection

DD

current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).

3.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P
the difference between actual pin voltage and V

or VDD and multiply by the pin current for each I/O pin. Except in cases of

SS

unusually high pin current (heavy loads), the difference between pin voltage and V

Table 4. Thermal Characteristics

Rating Symbol Value Unit

into account in power calculations, determine

I/O

or VDD will be very small.

SS

Operating temperature range
(packaged)

Maximum junction temperature T

Thermal resistance

Single-layer board

32-pin LQFP

28-pin SOIC 57

20-pin SOIC 71

16-pin PDIP 64

16-pin TSSOP 108

Thermal resistance

Four-layer board

32-pin LQFP

28-pin SOIC 42

20-pin SOIC 52

16-pin PDIP 47

16-pin TSSOP 78

The average chip-junction temperature (T

T

A

JM

θ

JA

θ

JA

) in °C can be obtained from:

J

TL to T

H

–40 to 85

95 °C

66

47

°C

°C/W

°C/W

T

= TA + (PD × θJA) Eqn. 1

J

where:

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 9

Subject to Change Without Notice

Preliminary

Electrical Characteristics

TA = Ambient temperature, °C
θ

= Package thermal resistance, junction-to-ambient, °C/W

JA

P

= P

D

P

int

P

I/O

For most applications, P

+ P

int

I/O

= IDD × VDD, Watts — chip internal power

= Power dissipation on input and output pins — user determined

<< P

I/O

and can be neglected. An approximate relationship between PD and TJ (if P

int

is:

P

= K ÷ (TJ + 273°C) Eqn. 2

D

Solving Equation 1 and Equation 2 for K gives:

is neglected)

I/O

K = P

× (TA + 273°C) + θJA × (PD)

D

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
for any value of T

. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively

A

.

A

2

(at equilibrium)

D

Eqn. 3

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.

Table 5. ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Human

Body

Series resistance R1 1500

Storage capacitance C 100 pF

Number of pulses per pin — 3 —

Ω

Series resistance R1 0

Machine

Latch-up

Storage capacitance C 200 pF

Number of pulses per pin — 3 —

Minimum input voltage limit — –2.5 V

Maximum input voltage limit — 7.5 V

Table 6. ESD and Latch-Up Protection Characteristics

No.

1 Human body model (HBM)

2 Machine model (MM)

Rating

1

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Symbol Min Max Unit

V

HBM

V

MM

Ω

±2000 — V

±200 — V

Freescale Semiconductor10

Electrical Characteristics

Table 6. ESD and Latch-Up Protection Characteristics (continued)

3 Charge device model (CDM)

4

1

Parameter is achieved by design characterization on a small sample size from typical devices

Latch-up current at TA = 85°CI

V

CDM

LAT

±500 — V

±100 — mA

under typical conditions unless otherwise noted.

3.6 DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 7. DC Characteristics

Num C Characteristic Symbol Condition Min. Typical

1 Operating Voltage 1.8 3.6 V

C

2

Output high
voltage

C

Output high

D

3

current

Max total I

C

4

Output low
voltage

C

Output low

D

current

P

6

7

8C

Input high
voltage

CV

P

Input low
voltage

CV

Input
hysteresis

Max total I

Input

9P

leakage
current

All I/O pins,

low-drive strength

All I/O pins,

high-drive strength

for all ports I

OH

All I/O pins,

low-drive strength

All I/O pins,

high-drive strength

for all ports I

OL

all digital inputs V

all digital inputs V

all digital inputs V

all input only pins

(Per pin)

V

OH

OHT

V

OL

OLT

IH

IL

hys

|IIn|VIn = VDD or V

VDD > 1.8 V,

= –2 mA

I

Load

VDD > 2.7 V,

I

= –10 mA

Load

VDD > 1.8V,

I

= –2 mA

Load

– 0.5 — —

V

DD

– 0.5 — —

V

DD

V

– 0.5 — —

DD

———100mA

VDD > 1.8 V,

I

= 0.6 mA

Load

V

> 2.7 V,

DD

I

= 10 mA

Load

> 1.8 V,

V

DD

= 3 mA

I

Load

——0.5

——0.5

——0.5

———100mA5

VDD > 2.7 V 0.70 x V

> 1.8 V 0.85 x V

DD

DD

DD

VDD > 2.7 V — — 0.35 x V

> 1.8 V — — 0.30 x V

DD

— 0.06 x V

SS

DD

—0.1 1μA

Hi-Z

10 P

(off-state)
leakage

all input/output

(per pin)

|V

|I

OZ

= V

or V

In

DD

SS

—0.1 1μA

current

all digital inputs, when

enabled (all I/O pins other

than

PTA5/IRQ/TCLK/RESET

R

PU,

R

PD

—

17.5 — 52.5 kΩ

11a P

Pullup,
Pulldown
resistors

1

Max. Unit

——

——

DD

DD

——mV

VP

VP

V

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 11

Preliminary

Subject to Change Without Notice

Electrical Characteristics

PULLUP RESISTOR TYPICALS

V

DD

(V)

PULL-UP RESISTOR (kΩ)

20

25

30

35

40

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

25°C

85°C

–40°C

PULLDOWN RESISTOR TYPICALS

V

DD

(V)

PULLDOWN RESISTANCE (k

Ω

)

20

25

30

35

40

1.8 2.3 2.8 3.3

25°C

85°C

–40°C

3.6

Table 7. DC Characteristics (continued)

1.84

1.92

1

Max. Unit

1.88

1.96

Num C Characteristic Symbol Condition Min. Typical

R

Pullup,

11b C

Pulldown

(PTA5/IRQ/TCLK/RESET)

resistors

Single pin limit

12 C

DC injection

3, 4,

current

5

Total MCU limit, includes

sum of all stressed pins

13 C Input Capacitance, all pins C

14 C RAM retention voltage V

15 C POR re-arm voltage

6

16 D POR re-arm time t

17 P Low-voltage detection threshold V

18 P Low-voltage warning threshold V

19 P

20 P Bandgap Voltage Reference

1

Typical values are measured at 25°C. Characterized, not tested

2

The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when

Low-voltage inhibit reset/recover
hysteresis

7

PU,

R

PD

(Note2)

I

IC

In

RAM

V

POR

POR

LV D

LV W

V

hys

V

BG

V

IN

— 17.5 — 52.5 kΩ

–0.2 — 0.2 mA

< VSS, V

IN

> V

DD

–5 — 5 mA

———8pF

——0.61.0V

— 0.9 1.4 2.0 V

—10——μs

VDD falling
VDD rising

VDD falling
VDD rising

1.80

1.88

2.08 2.14 2.24 V

——80—mV

— 1.151.171.18 V

measured externally on the pin.

3

All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.

4

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.

5

Power supply must maintain regulation within operating V

range during instantaneous and operating maximum current

DD

conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external V

load will shunt current greater than maximum

DD

injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).

6

Maximum is highest voltage that POR is guaranteed.

7

Factory trimmed at VDD = 3.0 V, Temp = 25 °C

V

Figure 6. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor12

Electrical Characteristics

TYPICAL VOL VS IOL AT V

DD

= 3.0 V

I

OL

(mA)

V

OL

(V)

0

0.2

0.4

0.6

0.8

1

1.2

0 5 10 15 20

TYPICAL VOL VS V

DD

VDD (V)

V

OL

(V)

0

0.05

0.1

0.15

0.2

1234

25°C

85°C

–40°C

25°C,

I

OL

= 2 mA

85°C,

I

OL

= 2 mA

–40°C,

I

OL

= 2 mA

TYPICAL VOL VS IOL AT V

DD

= 3.0 V

I

OL

(mA)

V

OL

(V)

0

0.2

0.4

0.6

0.8

1

0102030

TYPICAL VOL VS V

DD

VDD (V)

V

OL

(V)

0

0.1

0.2

0.3

0.4

1234

IOL = 6 mA

I

OL

= 3 mA

I

OL

= 10 mA

25°C

85°C

–40°C

25°C

85°C

–40°C

TYPICAL V

DD

– VOH VS IOH AT V

DD

= 3.0 V

I

OH

(mA))

0

0.2

0.4

0.6

0.8

1

1.2

–20–15–10–50

TYPICAL V

DD

– VOH VS VDD AT SPEC I

OH

VDD (V)

V

DD

– V

OH

(V)

0

0.05

0.1

0.15

0.2

0.25

1234

V

DD

– V

OH

(V)

25°C

85°C

–40°C

25°C,

I

OH

= 2 mA

85°C,

I

OH

= 2 mA

–40°C,

I

OH

= 2 mA

Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)

Figure 8. Typical Low-Side Driver (Sink) Characteristics

Figure 9. Typical High-Side (Source) Characteristics

Freescale Semiconductor 13

Subject to Change Without Notice

MC9S08QE8 Series, Rev. 3

Preliminary

— High Drive (PTxDSn = 1)

— Low Drive (PTxDSn = 0)

Electrical Characteristics

TYPICAL V

DD

– VOH VS IOH AT V

DD

= 3.0 V

I

OH

(mA)

0

0.2

0.4

0.6

0.8

–30–25–20–15–10–50

TYPICAL VDD – VOH VS V

DD

AT SPEC I

OH

VDD (V)

V

DD

– V

OH

(V)

0

0.1

0.2

0.3

0.4

1234

I

OH

= –10 mA

I

OH

= –6 mA

I

OH

= –3 mA

V

DD

– V

OH

(V)

25°C

85°C

–40°C

25°C

85°C

–40°C

Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor14

3.7 Supply Current Characteristics

This section includes information about power supply current in various operating modes.

Table 8. Supply Current Characteristics

Electrical Characteristics

Num C

P

1

T 1 MHz 0.80 —

T

2

T 1 MHz 0.51 —

T

3

T

T

4

T

T

5

T

T

6

T1 MHz290—

7T

P

8

C — 2 250 2000 –40 to 85°C

P

9

C — 2 350 5500 –40 to 85°C

10 T

11 T

Parameter

Run supply current
FEI mode, all modules on

Run supply current
FEI mode, all modules off

Run supply current
LPRS=0, all modules off

Symbol

RI

RI

RI

Run supply current
LPRS=1, all modules off; running

RI

from Flash

Run supply current
LPRS=1, all modules off; running

RI

from RAM

Wait mode supply current
FEI mode, all modules off

Wait mode supply current
LPRS = 1, all modules off

WI

WI

Stop2 mode supply current S2I

Stop3 mode supply current
no clocks active

S3I

RTC using LPO — — —

Stop2 and

Stop 3 adders:

RTC using low

power crystal

Bus

Freq

10 MHz

DD

10 MHz

DD

16 kHz

FBILP

DD

16 kHz

FBELP

16 kHz

FBILP

DD

16 kHz

FBELP

16 kHz

FBILP

DD

16 kHz

FBELP

10 MHz

DD

DD

16 kHz

FBELP

— 3 300 2500

DD

— 3 400 6000

DD

———

V

DD

(V)

Typical

1

Max Unit

5.60 8.2

3

3.60 —

3

165 —

3

105 —

77 —

3

21 —

77 —

3

7.3 —

570 —

3

31—μA –40 to 85°C

200

500

—nA

—nA

oscillator

12 T

EREFSTEN=1 — —

300 — nA

13 T IREFSTEN=1 — — 70 — μA

14 T LVD — —

15 T ACMP

16 T ADC

1

Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.

2

Also applies to LPRun and LPWait modes.

3

ADC current measured on V

Stop3 adders:

2

——

3

——

pin on 28-pin and 32-pin devices, adder to VDD on 16-pin and 20-pin packages.

DDA

3

100

20

0.007

— μA

— μA

— μA –40 to 85°C

Temp

(°C)

mA

–40 to 85°C

mA –40 to 85°C

μA –40 to 85°C

μA –40 to 85°C

μA –40 to 85°C

μA –40 to 85°C

–40 to 85°C

nA

–40 to 85°C

nA

–40 to 85°C

–40 to 85°C

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 15

Preliminary

Subject to Change Without Notice

Electrical Characteristics

3.8 External Oscillator (XOSCVLP) Characteristics

Refer to Figure 11 and Figure 12 for crystal or resonator circuits.

Table 9. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient)

Num C Characteristic Symbol Min. Typical

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

f

1C

Load capacitors

2D

Feedback resistor

3D

Series resistor —

4D

Crystal start-up time

5C

Low range (RANGE = 0)
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)

Low range (RANGE=0), low power (HGO=0)
Other oscillator settings

Low range, low power (RANGE=0, HGO=0)

2

Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)

Low range, low power (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)

≥ 8 MHz
4 MHz
1 MHz

4

Low range, low power
Low range, high gain
High range, low power
High range, high gain

lo

f

hi

f

hi

C

1,C2

R

F

2

R

S

t

CSTL

t

CSTH

32

—
—
—

—
—
—

—
—
—

—
—
—
—

—
1
1

—

—

See Note

See Note3

—

10

1

—

100

0

0
0
0

600
400

5

15

1

Max. Unit

38.4
16

8

2

—
—
—

—
—
—

0
10
20

—
—
—
—

kHz
MHz
MHz

MΩ

kΩ

ms

Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)

6D

FEE mode

f

extal

FBE or FBELP mode

1

Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.

2

Load capacitors (C

3

See crystal or resonator manufacturer’s recommendation.

4

Proper PC board layout procedures must be followed to achieve specifications.

), feedback resistor (RF) and series resistor (

1,C2

R

) are incorporated internally when RANGE = HGO = 0.

S

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

0.03125
0

—
—

2020MHz

MHz

Freescale Semiconductor16

Electrical Characteristics

XOSCVLP

EXTAL XTAL

Crystal or Resonator

R

S

C

2

R

F

C

1

XOSCVLP

EXTAL XTAL

Crystal or Resonator

Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain

Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Power

3.9 Internal Clock Source (ICS) Characteristics

Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)

Num C Characteristic Symbol Min. Typical1Max. Unit

1P

2P

3T

4P

5P

6C

7C

Average internal reference frequency — factory trimmed

= 3.6 V and temperature = 25°C

at V

DD

Internal reference frequency — user trimmed f

Internal reference start-up time t

DCO output frequency range — trimmed

DCO output frequency
Reference = 32768 Hz and DMX32 = 1

Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)

Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)

f

int_ft

int_ut

IRST

2

2

f

dco_u

f

dco_DMX32

Δf

dco_res_t

Δf

dco_res_t

— 32.768 — kHz

31.25 — 39.06 kHz

—60100μs

48 — 60 MHz

— 59.77 — MHz

— ± 0.1 ± 0.2

— ± 0.2 ± 0.4

%f

%f

dco

dco

Freescale Semiconductor 17

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Electrical Characteristics

TBD

-2.00%

-1.50%

-1.00%

-0.50%

0.00%

0.50%

1.00%

-60 -40 -20 0 20 40 60 80 100 120

Temperature

Deviation (%)

Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)

Num C Characteristic Symbol Min. Typical1Max. Unit

8C

9C

10 C

11 C

1

Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.

2

The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.

3

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing

Total deviation of trimmed DCO output frequency over voltage
and temperature

Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0

FLL acquisition time

3

°C to 70 °C

Long term jitter of DCO output clock (averaged over 2-ms

interval)

4

Δf

dco_t

Δf

dco_t

t

Acquire

C

Jitter

—

— ± 0.5 ± 1

—— 1ms

— 0.02 0.2

+ 0.5

-1.0

± 2

from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.

4

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

Bus

.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V

and VSS and variation in crystal oscillator frequency increase the C

DD

percentage for a

Jitter

given interval.

%f

%f

%f

dco

dco

dco

Figure 13. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)

3.10 AC Characteristics

This section describes timing characteristics for each peripheral system.

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor18

3.10.1 Control Timing

t

extrst

RESET PIN

Electrical Characteristics

Table 11. Control Timing

Num C Rating Symbol Min Typical

1D

Bus frequency (t

cyc

= 1/f

2 D Internal low power oscillator period

3D

External reset pulse width

4 D Reset low drive

5D

6D

BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes

BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes

IRQ pulse width

7D

Asynchronous path
Synchronous path

8 D Keyboard interrupt pulse width

Asynchronous path
Synchronous path

)f

Bus

2

3

2

4

2

4

Bus

t

LPO

t

extrs t

t

rstdrv

t

MSSU

t

MSH

t

ILIH, tIHIL

t

ILIH, tIHIL

dc — 10 MHz

700 — 1300 μs

100 — — ns

34 x t

500 — — ns

100 — — μs

100

1.5 × t

100

1.5 × t

cyc

cyc

cyc

1

Max Unit

——ns

—
—

—
—

—
—

—
—

Port rise and fall time —

Low output drive (PTxDS = 0) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)

9C

5

t

Rise

, t

Fall

—
—

16
23

—
—

Port rise and fall time —

High output drive (PTxDS = 1) (load = 50 pF)

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

1

Typical values are based on characterization data at V

2

This is the shortest pulse that is guaranteed to be recognized as a reset pin request.

3

To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
rises above V

4

This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

LV D

.

5

t

Rise

, t

Fall

—
—

= 3.0V, 25°C unless otherwise stated.

DD

5
9

—
—

MSH

after VDD

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.

5

Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.

ns

ns

ns

ns

Figure 14. Reset Timing

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 19

Subject to Change Without Notice

Preliminary

Electrical Characteristics

t

IHIL

KBIPx

t

ILIH

IRQ/KBIPx

t

TCLK

t

clkh

t

clkl

TCLK

t

ICPW

TPMCHn

t

ICPW

TPMCHn

Figure 15. IRQ/KBIPx Timing

3.10.2 TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.

Table 12. TPM Input Timing

No. C Function Symbol Min Max Unit

1 D External clock frequency f

2 D External clock period t

3 D External clock high time t

4 D External clock low time t

5 D Input capture pulse width t

Figure 16. Timer External Clock

TCLK

TCLK

clkh

clkl

ICPW

0f

4—t

1.5 — t

1.5 — t

1.5 — t

/4 Hz

Bus

cyc

cyc

cyc

cyc

Figure 17. Timer Input Capture Pulse

3.10.3 SPI Timing

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Table 13 and Figure 18 through Figure 21 describe the timing requirements for the SPI system.

Freescale Semiconductor20

Electrical Characteristics

Table 13. SPI Timing

No. C Function Symbol Min Max Unit

Operating frequency

—D

Master
Slave

SPSCK period

1D

Master
Slave

Enable lead time

2D

Master
Slave

Enable lag time

3D

Master
Slave

Clock (SPSCK) high or low time

4D

Master

t

Slave

Data setup time (inputs)

5D

Master
Slave

Data hold time (inputs)

6D

Master
Slave

7 D Slave access time t

8 D Slave MISO disable time t

Data valid (after SPSCK edge)

9D

Master
Slave

Data hold time (outputs)

10 D

Master
Slave

Rise time

11 D

Input
Output

Fall time

12 D

Input
Output

f

op

t

SPSCK

t

Lead

t

Lag

WSPSCK

t

SU

t

HI

a

dis

t

v

t

HO

t

RI

t

RO

t

FI

t

FO

f

Bus

t

cyc

t

cyc

/2048

0

2
4

1/2

1

1/2

1

– 30

– 30

15
15

0

25

f

Bus

f

Bus

2048

—

—
—

—
—

1024 t

—

—
—

—
—

/2
/4

cyc

—1t

—1t

—
—

0
0

—
—

—
—

t

t

cyc

cyc

25
25

—
—

– 25

25

– 25

25

Hz

t

cyc

t

cyc

t

SPSCK

t

cyc

t

SPSCK

t

cyc

ns
ns

ns
ns

ns
ns

cyc

cyc

ns
ns

ns
ns

ns
ns

ns
ns

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 21

Preliminary

Subject to Change Without Notice

Electrical Characteristics

SPSCK

(OUTPUT)

SPSCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

SS

1

(OUTPUT)

MSB IN

2

BIT 6 . . . 1

LSB IN

MSB OUT

2

LSB OUT

BIT 6 . . . 1

(CPOL = 0)

(CPOL = 1)

NOTES:

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

1. SS

output mode (DDS7 = 1, SSOE = 1).

1

2 3

4

5

6

9 10

11

12

4

9

SPSCK

(OUTPUT)

SPSCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MSB IN

(2)

BIT 6 . . . 1

LSB IN

MASTER MSB OUT

(2)

MASTER LSB OUT

BIT 6 . . . 1

PORT DATA

(CPOL = 0)

(CPOL = 1)

PORT DATA

SS

(1)

(OUTPUT)

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

NOTES:

2

1

12

11

3

4 4

11

12

5

6

9 10

Figure 18. SPI Master Timing (CPHA = 0)

Figure 19. SPI Master Timing (CPHA =1)

MC9S08QE8 Series, Rev. 3

Subject to Change Without Notice

Preliminary

Freescale Semiconductor22

Figure 20. SPI Slave Timing (CPHA = 0)

SPSCK

(INPUT)

SPSCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

SS

(INPUT)

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT

SLAVE LSB OUT

BIT 6 . . . 1

(CPOL = 0)

(CPOL = 1)

NOTE:

SLAVE

SEE

NOTE

1. Not defined but normally MSB of character just received

1

2

3

4

5

6

7

8

9

10

11

12

4

11

12

10

SPSCK

(INPUT)

SPSCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT

SLAVE LSB OUT

BIT 6 . . . 1

SEE

(CPOL = 0)

(CPOL = 1)

SS

(INPUT)

NOTE:

SLAVE

NOTE

1. Not defined but normally LSB of character just received

1

2

3

4

5

6

7

8

9 10

11

12

4

11

12

Electrical Characteristics

3.11 Analog Comparator (ACMP) Electricals

C Characteristic Symbol Min Typical Max Unit

D Supply voltage

P Supply current (active)

Freescale Semiconductor 23

Figure 21. SPI Slave Timing (CPHA = 1)

Table 14. Analog Comparator Electrical Specifications

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

V

DD

I

DDAC

1.8 — 3.6 V

—2035μA

Electrical Characteristics

Table 14. Analog Comparator Electrical Specifications (continued)

C Characteristic Symbol Min Typical Max Unit

D Analog input voltage V

P Analog input offset voltage V

Analog comparator hysteresis V

C

P Analog input leakage current

I

C Analog comparator initialization delay t

AIN

AIO

H

ALKG

AINIT

VSS – 0.3 — V

3.12 ADC Characteristics

Characteristic Conditions Symb Min Typ

Supply voltage Absolute V

Delta to V

Ground voltage Delta to V

Ref Voltage
High

—V

Input Voltage — V

Input
Capacitance

—C

Table 15. 12-bit ADC Operating Conditions

1.8 — 3.6 V —

–100 0 +100 mV —

–100 0 +100 mV —

1.8 V

V

REFL

—4.55.5pF —

(VDD-V

DD

(VSS-V

SS

DDAD

SSAD

DDAD

2

ΔV

)

2

)

ΔV

DDAD

SSAD

REFH

ADIN

ADIN

DD

V

—2040mV

3.0 9.0 15.0

mV

——1.0μA

——1.0μs

1

Max Unit Comment

DDAD

—V

V

DDAD

REFH

V—

V—

Input
Resistance

Analog Source
Resistance

ADC

—R

12 bit mode

> 4MHz

f

ADCK

f

< 4MHz

ADCK

f

> 4MHz

ADCK

< 4MHz

f

ADCK

8 bit mode (all valid f

ADCK

High Speed (ADLPC=0)
Conversion
Clock Freq.

1

Typical values assume V

Low Power (ADLPC=1)

= 3.0 V, Temp = 25 °C, f

DDAD

reference only and are not tested in production.

2

DC potential difference.

ADIN

R

AS

—5 7kΩ —

—
—

—
—

2
5

kΩ External to MCU10 bit mode
—
—

—
—

5

10

)——10

0.4 — 8.0

f

ADCK

0.4 — 4.0

=1.0 MHz unless otherwise stated. Typical values are for

ADCK

MHz —

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor24

Electrical Characteristics

+
–

+

–

V

AS

R

AS

C

AS

V

ADIN

Z

AS

Pad
leakage
due to
input
protection

Z

ADIN

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

R

ADIN

ADC SAR

ENGINE

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

INPUT PIN

R

ADIN

C

ADIN

INPUT PIN

R

ADIN

INPUT PIN

R

ADIN

Figure 22. ADC Input Impedance Equivalency Diagram

Table 16. 12-bit ADC Characteristics (V

C Characteristic Conditions Symbol Min. Typical

Supply Current
ADLPC=1

T

ADLSMP=1

—I

DDAD

ADCO=1

Supply Current
ADLPC=1

T

ADLSMP=0

—I

DDAD

ADCO=1

Supply Current
ADLPC=0

T

ADLSMP=1
ADCO=1

Supply Current
ADLPC=0

P

P

C

ADLSMP=0
ADCO=1

ADC
Asynchronous
Clock Source

—I

—I

High Speed
(ADLPC=0)

Low Power

DDAD

DDAD

f

ADACK

(ADLPC=1)

— 120 — μA—

— 202 — μA

— 288 — μA

—0.532 1 mA

23.35

1.25 2 3.3

REFH

= V

DDAD

1

, V

REFL

= V

SSAD

)

Max. Unit Comment

t

ADACK

1/f

MHz

—

—

—

=

ADACK

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 25

Preliminary

Subject to Change Without Notice

Electrical Characteristics

Table 16. 12-bit ADC Characteristics (V

C Characteristic Conditions Symbol Min. Typical

Conversion

P

Time (Including
sample time)

C

P

Sample Time

C

T Total

Short Sample
(ADLSMP=0)

Long Sample
(ADLSMP=1)

Short Sample
(ADLSMP=0)

Long Sample
(ADLSMP=1)

12 bit mode

t

ADC

t

ADS

REFH

= V

DDAD

, V

= V

REFL

1

Max. Unit Comment

—20—

—40—

—3.5—

— 23.5 —

— ±3.0 —

Unadjusted

P 10 bit mode — ±1 ±2.5

Error
(28-pin and
32-pin

T 8 bit mode — ±0.5 ±1.0

E

TUE

packages)

T Total

Unadjusted

P 10 bit mode — ±1.5 ±3.5

Error
(16-pin and
20-pin

T 8 bit mode — ±0.7 ±1.5

12 bit mode

E

TUE

— ±4.0 —

package)

) (continued)

SSAD

ADCK
cycles

ADCK
cycles

LSB

LSB

See ADC

chapter in the

QE8 Reference

Manual for

conversion time

variances

For 28-pin and

32-pin packages

2

Includes

quantization

For 16-pin and

20-pin packages

2

Includes

quantization

only.

only.

T

Differential
Non-Linearity

T 8 bit mode

T

Integral
Non-Linearity

12 bit mode

12 bit mode

— ±1.75 —

3

3

DNL

— ±0.5 ±1.0

— ±0.3 ±0.5

— ±1.5 —

INL

T 8 bit mode — ±0.3 ±0.5

T

Zero-Scale

P 10 bit mode — ±0.5 ±1.5

Error

12 bit mode

— ±1.5 —

E

ZS

T 8 bit mode — ±0.5 ±0.5

T

Full-Scale

P 10 bit mode — ±0.5 ±1

Error

12 bit mode

— ±1.0 —

E

FS

T 8 bit mode — ±0.5 ±0.5

D

Quantization
Error

12 bit mode

E

Q

— –1 to 0 —

8 bit mode — — ±0.5

LSB

LSB

LSB

LSB

LSB

2

2

2

2

2

V

V

ADIN

ADIN

—P 10 bit mode

—C 10 bit mode — ±0.5 ±1.0

= V

= V

—10 bit mode — — ±0.5

SSAD

DDAD

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor26

Electrical Characteristics

Table 16. 12-bit ADC Characteristics (V

C Characteristic Conditions Symbol Min. Typical

12 bit mode

Input Leakage

D

Error

10 bit mode — ±0.2 ±4

E

IL

REFH

= V

DDAD

, V

= V

REFL

1

Max. Unit Comment

— ±2—

) (continued)

SSAD

LSB

2

8 bit mode — ±0.1 ±1.2

Temp Sensor

D

Slope

Temp Sensor

D

Voltage

1

Typical values assume V

–40°C to 25°C

m

25°C to 85°C—1.769—

25°CV

= 3.0 V, Temp = 25 °C, f

DDAD

TEMP25

ADCK

—1.646—

mV/°C

— 701.2 — mV

=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

2

1 LSB = (V

3

Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes

4

Based on input pad leakage current. Refer to pad electricals.

REFH

– V

REFL

)/2

N

3.13 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash memory.

Program and erase operations do not require any special power sources other than the normal V
information about program/erase operations, see the Memory section.

Table 17. Flash Characteristics

supply. For more detailed

DD

Pad leakage4

*R

AS

C Characteristic Symbol Min Typical Max Unit

Supply voltage for program/erase

D

–40°C to 85°CV

D Supply voltage for read operation V

D Internal FCLK frequency

1

D Internal FCLK period (1/FCLK) t

P Byte program time (random location)

P Byte program time (burst mode)

P Page erase time

P Mass erase time

Byte program current

Page erase current

Program/erase endurance

C

TL to TH = –40°C to + 85°C

2

2

3

3

4

2

2

prog/erase

Read

f

FCLK

Fcyc

t

prog

t

Burst

t

Page

t

Mass

RI

DDBP

RI

DDPE

— 10,000 —

1.8

1.8 — 3.6 V

150 — 200 kHz

5—6.67μs

—4—mA

—6—mA

T = 25°C

C Data retention

1

The frequency of this clock is controlled by a software setting.

2

These values are hardware state machine controlled. User code does not need to count cycles. This information supplied

5

t

D_ret

15 100 — years

—

9t

4t

4000 t

20,000 t

100,000

3.6 V

Fcyc

Fcyc

Fcyc

Fcyc

—

cycles

—

for calculating approximate time to program and erase.

MC9S08QE8 Series, Rev. 3

Freescale Semiconductor 27

Preliminary

Subject to Change Without Notice

Electrical Characteristics

3

The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.

4

Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.

5

Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

3.14 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.

3.14.1 Conducted Transient Susceptibility

Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 18.

Table 1 8. Conducted Susceptibility, EFT/B

Parameter Symbol Conditions

VDD = 3.3 V
Conducted susceptibility, electrical
fast transient/burst (EFT/B)

1

Data based on qualification test results. Not tested in production.

V

CS_EFT

TA = +25oC

package type

32 LQFP

The susceptibility performance classification is described in Table 19.

Table 19. Susceptibility Performance Classification

Result Performance Criteria

A No failure The MCU performs as designed during and after exposure.

B

C Soft failure

Self-recovering

failure

The MCU does not perform as designed during exposure. The MCU returns
automatically to normal operation after exposure is removed.

The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET

f

OSC/fBUS

8 MHz
crystal

8 MHz bus

Result

A2.3

B4.0

C>4.0

D>4.0

Amplitude

pin is asserted.

1

(Min)

Unit

kV

MC9S08QE8 Series, Rev. 3

Preliminary

Subject to Change Without Notice

Freescale Semiconductor28

Table 19. Susceptibility Performance Classification (continued)

MC

Temperature range

Family

Memory

Status

Core

(C = –40°C to 85°C)

(9 = Flash-based)

9

S08

XX

(MC = Fully Qualified)

Package designator (see Ta b le 2 0 )

Approximate flash size in Kbytes

QE

8C

Result Performance Criteria

Ordering Information

D Hard failure

E Damage

The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.

The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.

4 Ordering Information

This section contains ordering information for the device numbering system.

Example of the device numbering system:

5 Package Information

Table 20. Package Descriptions

Pin Count Package Type Abbreviation Designator Case No. Document No.

32 Low Quad Flat Package LQFP LC 873A 98ASH70029A

28 Small Outline Integrated Circuit SOIC WL 751F 98ASB42345B

20 Small Outline Integrated Circuit SOIC WJ 751D 98ASB42343B

16 Plastic Dual In-line Package PDIP PG 648 98ASB42431B

16 Thin Shrink Small Outline Package TSSOP TG 948F 98ASH70247A

5.1 Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 20.

Freescale Semiconductor 29

MC9S08QE8 Series, Rev. 3

Subject to Change Without Notice

Preliminary

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© Freescale Semiconductor, Inc. 2007–2008. All rights reserved.

Document Number: MC9S08QE8

Rev. 3
1/2008

Preliminary
Subject to Change Without Notice