Freescale MC9S08GT16A, MC9S08GT8A Data Sheet

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MC9S08GT16A MC9S08GT8A

Data Sheet

HCS08 Microcontrollers

MC9S08GT16A Rev. 1 7/2006

freescale.com

MC9S08GT16A/GT8A Features

8-Bit HCS08 Central Processor Unit (CPU)

• 40-MHz HCS08 CPU

• HC08 instruction set with added BGND instruction

• Support for up to 32 interrupt/reset sources

Memory Options

• FLASH read/program/erase down to 1.8 V

• Up to 16K FLASH; up to 2K RAM

Power-Saving Modes

• Three very low power stop modes

• Reduced power wait mode

• Very low power real time interrupt for use in run, wait, and stop

Clock Source Options

• Clock sources to internal hardware frequency locked-loop (FLL): internal, external, crystal, or resonator

• Internal clock with ±0.2% trimming resolution and ±0.5% deviation across voltage or across temperature

System Protection

• Software selectable pullups on ports when used as input

• Internal pullup on RESET and IRQ pin to reduce customer system cost

• Up to 38 general-purpose input/output (I/O) pins, plus one output-only pin, depending on package selection

Development Support

• Background debugging system

• Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module)

• On-chip, in-circuit emulation (ICE) debug module with real-time bus capture. On-chip ICE debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-ﬂow addresses and event-only data.

• Single-wire background debug interface

Package Options

• 48-pin QFN

• 44-pin QFP

• 42-pin PSDIP

• 32-pin QFN

• Optional watchdog computer operating properly (COP) reset

• Low-voltage detection with reset or interrupt

• Illegal opcode detection with reset

• Illegal address detection with reset

• FLASH block protect and security

Peripherals

• ATD — 8-channel, 10-bit analog-to-digital converter

• SCI — Two serial communications interface modules

• SPI — Serial peripheral interface module

• IIC — Inter-integrated circuit bus module

• Timer —One 3-channel timer PWM module (TPM) plus one 2-channel TPM

• KBI — 8-pin keyboard interrupt module

Input/Output

• 8 high-current pins (20 mA each)

MC9S08GT16A/GT8A Data Sheet

Covers: MC9S08GT16A

MC9S08GT8A

MC9S08GT16A

Rev. 1

7/2006

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://freescale.com

The following revision history table summarizes changes contained in this document.

Revision

Number

1 07/17/2006 Initial public release

Revision

Date

Description of Changes

Technology licensed from SST.

List of Chapters

Chapter 1 Device Overview ......................................................................19

Chapter 2 Pins and Connections .............................................................23

Chapter 3 Modes of Operation .................................................................33

Chapter 4 Memory .....................................................................................41

Chapter 5 Resets, Interrupts, and System Configuration .....................63

Chapter 6 Parallel Input/Output ...............................................................79

Chapter 7 Keyboard Interrupt (S08KBIV1) ..............................................99

Chapter 8 Central Processor Unit (S08CPUV2) ....................................105

Chapter 9 Internal Clock Generator (S08ICGV4) ..................................125

Chapter 10 Timer/PWM (S08TPMV2) ......................................................153

Chapter 11 Serial Communications Interface (S08SCIV1)..................... 169

Chapter 12 Serial Peripheral Interface (S08SPIV3) ................................187

Chapter 13 Inter-Integrated Circuit (S08IICV1) .......................................205

Chapter 14 Analog-to-Digital Converter (S08ATDV3) ............................221

Chapter 15 Development Support ...........................................................237

Appendix A Electrical Characteristics......................................................259

Appendix B Ordering Information and Mechanical Drawings................285

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Contents

Section Number Title Page

Chapter 1

Device Overview

1.1 Introduction .....................................................................................................................................19

1.1.1 Devices in the MC9S08GT16A/GT8A Series ..................................................................19

1.1.2 MCU Block Diagram ........................................................................................................19

1.2 System Clock Distribution ..............................................................................................................21

Chapter 2

Pins and Connections

2.1 Introduction .....................................................................................................................................23

2.2 Device Pin Assignment ...................................................................................................................23

2.3 Recommended System Connections ...............................................................................................27

2.3.1 V

2.3.2 PTG1/XTAL, PTG2/EXTAL — Oscillator ......................................................................28

2.3.3

2.3.4 PTG0/BKGD/MS — Background / Mode Select .............................................................29

2.3.5 IRQ — External Interrupt Request Pin .............................................................................30

2.3.6 General-Purpose I/O and Peripheral Ports ........................................................................30

2.3.7 Signal Properties Summary ...............................................................................................31

, VSS, V

RESET — External Reset Pin ...........................................................................................29

DDAD

, V

SSAD

, V

REFH

, V

— Power and Voltage References ...............28

REFL

Chapter 3

Modes of Operation

3.1 Introduction .....................................................................................................................................33

3.1.1 Features .............................................................................................................................33

3.2 Run Mode ........................................................................................................................................33

3.3 Active Background Mode ................................................................................................................33

3.4 Wait Mode .......................................................................................................................................34

3.5 Stop Modes ......................................................................................................................................35

3.5.1 Stop1 Mode .......................................................................................................................35

3.5.2 Stop2 Mode .......................................................................................................................35

3.5.3 Stop3 Mode .......................................................................................................................36

3.5.4 Active BDM Enabled in Stop Mode .................................................................................37

3.5.5 LVD Enabled in Stop Mode ..............................................................................................37

3.5.6 On-Chip Peripheral Modules in Stop Modes ....................................................................38

MC9S08GT16A/GT8A Data Sheet, Rev. 1

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Section Number Title Page

Chapter 4

Memory

4.1 MC9S08GT16A/GT8A Memory Map ............................................................................................41

4.1.1 Reset and Interrupt Vector Assignments ...........................................................................42

4.2 Register Addresses and Bit Assignments ........................................................................................43

4.3 RAM ................................................................................................................................................48

4.4 FLASH ............................................................................................................................................48

4.4.1 Features .............................................................................................................................48

4.4.2 Program and Erase Times .................................................................................................49

4.4.3 Program and Erase Command Execution .........................................................................49

4.4.4 Burst Program Execution ..................................................................................................51

4.4.5 Access Errors ....................................................................................................................53

4.4.6 FLASH Block Protection ..................................................................................................53

4.4.7 Vector Redirection ............................................................................................................54

4.5 Security ............................................................................................................................................54

4.6 Register Deﬁnition ..........................................................................................................................56

4.6.1 FLASH Clock Divider Register (FCDIV) ........................................................................56

4.6.2 FLASH Options Register (FOPT and NVOPT) ................................................................57

4.6.3 FLASH Conﬁguration Register (FCNFG) ........................................................................58

4.6.4 FLASH Protection Register (FPROT and NVPROT) .......................................................58

4.6.5 FLASH Status Register (FSTAT) ......................................................................................59

4.6.6 FLASH Command Register (FCMD) ...............................................................................60

Chapter 5

Resets, Interrupts, and System Configuration

5.1 Introduction .....................................................................................................................................63

5.1.1 Features .............................................................................................................................63

5.2 MCU Reset ......................................................................................................................................63

5.3 Computer Operating Properly (COP) Watchdog .............................................................................64

5.4 Interrupts .........................................................................................................................................64

5.4.1 Interrupt Stack Frame .......................................................................................................65

5.4.2 IRQ — External Interrupt Request Pin .............................................................................66

5.4.2.1 Pin Conﬁguration Options ..............................................................................66

5.4.2.2 Edge and Level Sensitivity ..............................................................................67

5.4.3 Interrupt Vectors, Sources, and Local Masks ....................................................................67

5.5 Low-Voltage Detect (LVD) System ................................................................................................69

5.5.1 Power-On Reset Operation ...............................................................................................69

5.5.2 LVD Reset Operation ........................................................................................................69

5.5.3 LVD Interrupt Operation ...................................................................................................69

5.5.4 Low-Voltage Warning (LVW) ...........................................................................................69

5.6 Real-Time Interrupt (RTI) ...............................................................................................................69

5.7 Register Deﬁnition ..........................................................................................................................70

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Section Number Title Page

5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................71

5.7.2 System Reset Status Register (SRS) .................................................................................72

5.7.3 System Background Debug Force Reset Register (SBDFR) ............................................73

5.7.4 System Options Register (SOPT) .....................................................................................74

5.7.5 System Device Identiﬁcation Register (SDIDH, SDIDL) ................................................75

5.7.6 System Real-Time Interrupt Status and Control Register (SRTISC) ................................76

5.7.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................77

5.7.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................78

Chapter 6

Parallel Input/Output

6.1 Introduction .....................................................................................................................................79

6.1.1 Features .............................................................................................................................79

6.1.2 Block Diagram ..................................................................................................................81

6.2 External Signal Description ............................................................................................................82

6.2.1 Port A and Keyboard Interrupts ........................................................................................82

6.2.2 Port B and Analog to Digital Converter Inputs .................................................................82

6.2.3 Port C and SCI2, IIC, and High-Current Drivers ..............................................................83

6.2.4 Port D, TPM1 and TPM2 ..................................................................................................83

6.2.5 Port E, SCI1, and SPI ........................................................................................................84

6.2.6 Port G, BKGD/MS, and Oscillator ...................................................................................84

6.3 Parallel I/O Controls ........................................................................................................................85

6.3.1 Data Direction Control ......................................................................................................85

6.3.2 Internal Pullup Control .....................................................................................................85

6.3.3 Slew Rate Control .............................................................................................................85

6.4 Stop Modes ......................................................................................................................................86

6.5 Register Deﬁnition ..........................................................................................................................86

6.5.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) .................................................86

6.5.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) .................................................89

6.5.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) .................................................91

6.5.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ...............................................93

6.5.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) ..................................................95

6.5.6 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) ...............................................97

Chapter 7

Keyboard Interrupt (S08KBIV1)

7.1 Introduction .....................................................................................................................................99

7.1.1 Port A and Keyboard Interrupt Pins ..................................................................................99

7.1.2 Features .............................................................................................................................99

7.1.3 KBI Block Diagram ........................................................................................................101

7.2 Register Deﬁnition ........................................................................................................................101

7.2.1 KBI Status and Control Register (KBISC) .....................................................................102

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7.2.2 KBI Pin Enable Register (KBIPE) ..................................................................................103

7.3 Functional Description ..................................................................................................................103

7.3.1 Pin Enables ......................................................................................................................103

7.3.2 Edge and Level Sensitivity ..............................................................................................103

7.3.3 KBI Interrupt Controls ....................................................................................................104

Chapter 8

Central Processor Unit (S08CPUV2)

8.1 Introduction ...................................................................................................................................105

8.1.1 Features ...........................................................................................................................105

8.2 Programmer’s Model and CPU Registers .....................................................................................106

8.2.1 Accumulator (A) .............................................................................................................106

8.2.2 Index Register (H:X) .......................................................................................................106

8.2.3 Stack Pointer (SP) ...........................................................................................................107

8.2.4 Program Counter (PC) ....................................................................................................107

8.2.5 Condition Code Register (CCR) .....................................................................................107

8.3 Addressing Modes .........................................................................................................................109

8.3.1 Inherent Addressing Mode (INH) ...................................................................................109

8.3.2 Relative Addressing Mode (REL) ...................................................................................109

8.3.3 Immediate Addressing Mode (IMM) ..............................................................................109

8.3.4 Direct Addressing Mode (DIR) ......................................................................................109

8.3.5 Extended Addressing Mode (EXT) ................................................................................110

8.3.6 Indexed Addressing Mode ..............................................................................................110

8.3.6.1 Indexed, No Offset (IX) ................................................................................110

8.3.6.2 Indexed, No Offset with Post Increment (IX+) .............................................110

8.3.6.3 Indexed, 8-Bit Offset (IX1) ...........................................................................110

8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .......................................110

8.3.6.5 Indexed, 16-Bit Offset (IX2) .........................................................................110

8.3.6.6 SP-Relative, 8-Bit Offset (SP1) ....................................................................110

8.3.6.7 SP-Relative, 16-Bit Offset (SP2) ..................................................................111

8.4 Special Operations .........................................................................................................................111

8.4.1 Reset Sequence ...............................................................................................................111

8.4.2 Interrupt Sequence ..........................................................................................................111

8.4.3 Wait Mode Operation ......................................................................................................112

8.4.4 Stop Mode Operation ......................................................................................................112

8.4.5 BGND Instruction ...........................................................................................................113

8.5 HCS08 Instruction Set Summary ..................................................................................................114

MC9S08GT16A/GT8A Data Sheet, Rev. 1

12 Freescale Semiconductor

Section Number Title Page

Chapter 9

Internal Clock Generator (S08ICGV4)

9.1 Introduction ...................................................................................................................................125

9.1.1 Features ...........................................................................................................................127

9.1.2 Modes of Operation ........................................................................................................128

9.1.3 Block Diagram ................................................................................................................129

9.2 External Signal Description ..........................................................................................................129

9.2.1 EXTAL — External Reference Clock / Oscillator Input ................................................129

9.2.2 XTAL — Oscillator Output ............................................................................................129

9.2.3 External Clock Connections ...........................................................................................130

9.2.4 External Crystal/Resonator Connections ........................................................................130

9.3 Register Deﬁnition ........................................................................................................................131

9.3.1 ICG Control Register 1 (ICGC1) ....................................................................................131

9.3.2 ICG Control Register 2 (ICGC2) ....................................................................................133

9.3.3 ICG Status Register 1 (ICGS1) .......................................................................................134

9.3.4 ICG Status Register 2 (ICGS2) .......................................................................................135

9.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ..................................................................135

9.3.6 ICG Trim Register (ICGTRM) .......................................................................................136

9.4 Functional Description ..................................................................................................................136

9.4.1 Off Mode (Off) ................................................................................................................137

9.4.1.1 BDM Active ..................................................................................................137

9.4.1.2 OSCSTEN Bit Set .........................................................................................137

9.4.1.3 Stop/Off Mode Recovery ..............................................................................137

9.4.2 Self-Clocked Mode (SCM) .............................................................................................137

9.4.3 FLL Engaged, Internal Clock (FEI) Mode .....................................................................138

9.4.4 FLL Engaged Internal Unlocked ....................................................................................139

9.4.5 FLL Engaged Internal Locked ........................................................................................139

9.4.6 FLL Bypassed, External Clock (FBE) Mode ..................................................................139

9.4.7 FLL Engaged, External Clock (FEE) Mode ...................................................................139

9.4.7.1 FLL Engaged External Unlocked .................................................................140

9.4.7.2 FLL Engaged External Locked .....................................................................140

9.4.8 FLL Lock and Loss-of-Lock Detection ..........................................................................140

9.4.9 FLL Loss-of-Clock Detection .........................................................................................141

9.4.10 Clock Mode Requirements .............................................................................................142

9.4.11 Fixed Frequency Clock ...................................................................................................143

9.4.12 High Gain Oscillator .......................................................................................................143

9.5 Initialization/Application Information ..........................................................................................143

9.5.1 Introduction .....................................................................................................................143

9.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ...........................145

9.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ..............................147

9.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ......................149

9.5.5 Example #4: Internal Clock Generator Trim ..................................................................151

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 13

Section Number Title Page

Chapter 10

Timer/PWM (S08TPMV2)

10.1 Introduction ...................................................................................................................................153

10.1.1 Features ...........................................................................................................................153

10.1.2 Features ...........................................................................................................................155

10.1.3 Block Diagram ................................................................................................................155

10.2 External Signal Description ..........................................................................................................157

10.2.1 External TPM Clock Sources ..........................................................................................157

10.2.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................157

10.3 Register Deﬁnition ........................................................................................................................157

10.3.1 Timer x Status and Control Register (TPMxSC) ............................................................158

10.3.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ................................................159

10.3.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ...............................160

10.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) ......................................161

10.3.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ......................................162

10.4 Functional Description ..................................................................................................................163

10.4.1 Counter ............................................................................................................................163

10.4.2 Channel Mode Selection .................................................................................................164

10.4.2.1 Input Capture Mode ......................................................................................164

10.4.2.2 Output Compare Mode .................................................................................165

10.4.2.3 Edge-Aligned PWM Mode ...........................................................................165

10.4.3 Center-Aligned PWM Mode ...........................................................................................166

10.5 TPM Interrupts ..............................................................................................................................167

10.5.1 Clearing Timer Interrupt Flags .......................................................................................167

10.5.2 Timer Overﬂow Interrupt Description ............................................................................167

10.5.3 Channel Event Interrupt Description ..............................................................................168

10.5.4 PWM End-of-Duty-Cycle Events ...................................................................................168

Chapter 11

Serial Communications Interface (S08SCIV1)

11.1 Introduction ...................................................................................................................................169

11.1.1 Features ...........................................................................................................................171

11.1.2 Modes of Operation ........................................................................................................171

11.1.3 Block Diagram ................................................................................................................172

11.2 Register Deﬁnition ........................................................................................................................174

11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) ..........................................................174

11.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................175

11.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................176

11.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................177

11.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................179

11.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................179

11.2.7 SCI Data Register (SCIxD) .............................................................................................180

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Section Number Title Page

11.3 Functional Description ..................................................................................................................181

11.3.1 Baud Rate Generation .....................................................................................................181

11.3.2 Transmitter Functional Description ................................................................................181

11.3.2.1 Send Break and Queued Idle .........................................................................182

11.3.3 Receiver Functional Description .....................................................................................182

11.3.3.1 Data Sampling Technique .............................................................................183

11.3.3.2 Receiver Wakeup Operation .........................................................................183

11.3.3.2.1Idle-Line Wakeup .....................................................................184

11.3.3.2.2Address-Mark Wakeup .............................................................184

11.3.4 Interrupts and Status Flags ..............................................................................................184

11.3.5 Additional SCI Functions ...............................................................................................185

11.3.5.1 8- and 9-Bit Data Modes ...............................................................................185

11.3.5.2 Stop Mode Operation ....................................................................................185

11.3.5.3 Loop Mode ....................................................................................................186

11.3.5.4 Single-Wire Operation ..................................................................................186

Chapter 12

Serial Peripheral Interface (S08SPIV3)

12.1 Introduction ...................................................................................................................................187

12.1.1 Features ...........................................................................................................................189

12.1.2 Block Diagrams ..............................................................................................................190

12.1.2.1 SPI System Block Diagram ..........................................................................190

12.1.2.2 SPI Module Block Diagram ..........................................................................190

12.1.3 SPI Baud Rate Generation ..............................................................................................191

12.2 External Signal Description ..........................................................................................................192

12.2.1 SPSCK — SPI Serial Clock ............................................................................................192

12.2.2 MOSI — Master Data Out, Slave Data In ......................................................................192

12.2.3 MISO — Master Data In, Slave Data Out ......................................................................192

12.2.4

12.3 Modes of Operation .......................................................................................................................193

12.3.1 SPI in Stop Modes ..........................................................................................................193

12.4 Register Deﬁnition ........................................................................................................................193

12.4.1 SPI Control Register 1 (SPIC1) ......................................................................................193

12.4.2 SPI Control Register 2 (SPIC2) ......................................................................................194

12.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................195

12.4.4 SPI Status Register (SPIS) ..............................................................................................196

12.4.5 SPI Data Register (SPID) ................................................................................................197

12.5 Functional Description ..................................................................................................................198

12.5.1 SPI Clock Formats ..........................................................................................................198

12.5.2 SPI Interrupts ..................................................................................................................201

12.5.3 Mode Fault Detection .....................................................................................................201

12.6 Initialization/Application Information ..........................................................................................201

SS — Slave Select ...........................................................................................................192

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 15

Section Number Title Page

12.6.1 SPI Module Initialization Example .................................................................................201

12.6.1.1 Initialization Sequence ..................................................................................201

12.6.1.2 Pseudo—Code Example ...............................................................................202

Chapter 13

Inter-Integrated Circuit (S08IICV1)

13.1 Introduction ...................................................................................................................................205

13.1.1 Features ...........................................................................................................................207

13.1.2 Modes of Operation ........................................................................................................207

13.1.3 Block Diagram ................................................................................................................208

13.2 External Signal Description ..........................................................................................................208

13.2.1 SCL — Serial Clock Line ...............................................................................................208

13.2.2 SDA — Serial Data Line ................................................................................................208

13.3 Register Deﬁnition ........................................................................................................................208

13.3.1 IIC Address Register (IICA) ...........................................................................................209

13.3.2 IIC Frequency Divider Register (IICF) ...........................................................................209

13.3.3 IIC Control Register (IICC) ............................................................................................212

13.3.4 IIC Status Register (IICS) ...............................................................................................213

13.3.5 IIC Data I/O Register (IICD) ..........................................................................................214

13.4 Functional Description ..................................................................................................................215

13.4.1 IIC Protocol .....................................................................................................................215

13.4.1.1 START Signal ...............................................................................................216

13.4.1.2 Slave Address Transmission .........................................................................216

13.4.1.3 Data Transfer .................................................................................................216

13.4.1.4 STOP Signal ..................................................................................................217

13.4.1.5 Repeated START Signal ...............................................................................217

13.4.1.6 Arbitration Procedure ....................................................................................217

13.4.1.7 Clock Synchronization ..................................................................................217

13.4.1.8 Handshaking .................................................................................................218

13.4.1.9 Clock Stretching ............................................................................................218

13.5 Resets ............................................................................................................................................218

13.6 Interrupts .......................................................................................................................................218

13.6.1 Byte Transfer Interrupt ....................................................................................................219

13.6.2 Address Detect Interrupt .................................................................................................219

13.6.3 Arbitration Lost Interrupt ................................................................................................219

Chapter 14

Analog-to-Digital Converter (S08ATDV3)

14.1 Introduction ...................................................................................................................................223

14.1.1 Features ...........................................................................................................................223

14.1.2 Modes of Operation ........................................................................................................223

14.1.2.1 Stop Mode .....................................................................................................223

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14.1.2.2 Power Down Mode .......................................................................................223

14.1.3 Block Diagram ................................................................................................................223

14.2 External Signal Description ..........................................................................................................224

14.2.1 ADP7–ADP0 — Channel Input Pins ..............................................................................225

14.2.2 V

14.2.3 V

REFH

DDAD

, V

14.3 Register Deﬁnition ........................................................................................................................225

14.3.1 ATD Control (ATDC) .....................................................................................................225

14.3.2 ATD Status and Control (ATDSC) ..................................................................................228

14.3.3 ATD Result Data (ATDRH, ATDRL) .............................................................................229

14.3.4 ATD Pin Enable (ATDPE) ..............................................................................................229

14.4 Functional Description ..................................................................................................................230

14.4.1 Mode Control ..................................................................................................................230

14.4.2 Sample and Hold .............................................................................................................230

14.4.3 Analog Input Multiplexer ................................................................................................232

14.4.4 ATD Module Accuracy Deﬁnitions ................................................................................232

14.5 Resets ............................................................................................................................................235

14.6 Interrupts .......................................................................................................................................235

— ATD Reference Pins .........................................................................225

REFL

SSAD

— ATD Supply Pins ............................................................................225

Chapter 15

Development Support

15.1 Introduction ...................................................................................................................................237

15.1.1 Features ...........................................................................................................................238

15.2 Background Debug Controller (BDC) ..........................................................................................238

15.2.1 BKGD Pin Description ...................................................................................................239

15.2.2 Communication Details ..................................................................................................240

15.2.3 BDC Commands .............................................................................................................244

15.2.4 BDC Hardware Breakpoint .............................................................................................246

15.3 On-Chip Debug System (DBG) ....................................................................................................247

15.3.1 Comparators A and B ......................................................................................................247

15.3.2 Bus Capture Information and FIFO Operation ...............................................................247

15.3.3 Change-of-Flow Information ..........................................................................................248

15.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................248

15.3.5 Trigger Modes .................................................................................................................249

15.3.6 Hardware Breakpoints ....................................................................................................251

15.4 Register Deﬁnition ........................................................................................................................251

15.4.1 BDC Registers and Control Bits .....................................................................................251

15.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................252

15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................253

15.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................253

15.4.3 DBG Registers and Control Bits .....................................................................................254

15.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................254

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Freescale Semiconductor 17

Section Number Title Page

15.4.3.2 Debug Comparator A Low Register (DBGCAL) .........................................254

15.4.3.3 Debug Comparator B High Register (DBGCBH) .........................................254

15.4.3.4 Debug Comparator B Low Register (DBGCBL) ..........................................254

15.4.3.5 Debug FIFO High Register (DBGFH) ..........................................................255

15.4.3.6 Debug FIFO Low Register (DBGFL) ...........................................................255

15.4.3.7 Debug Control Register (DBGC) ..................................................................256

15.4.3.8 Debug Trigger Register (DBGT) ..................................................................257

15.4.3.9 Debug Status Register (DBGS) .....................................................................258

Appendix A

Electrical Characteristics

A.1 Introduction ...................................................................................................................................259

A.2 Parameter Classification ................................................................................................................259

A.3 Absolute Maximum Ratings ..........................................................................................................259

A.4 Thermal Characteristics .................................................................................................................260

A.5 Electrostatic Discharge (ESD) Protection Characteristics ............................................................262

A.6 DC Characteristics .........................................................................................................................262

A.7 Supply Current Characteristics ......................................................................................................266

A.8 ATD Characteristics ......................................................................................................................272

A.9 Internal Clock Generation Module Characteristics .......................................................................274

A.9.1 ICG Frequency Specifications ........................................................................................275

A.10 AC Characteristics .........................................................................................................................276

A.10.1 Control Timing ...............................................................................................................277

A.10.2 Timer/PWM (TPM) Module Timing ..............................................................................278

A.10.3 SPI Timing ......................................................................................................................280

A.11 FLASH Specifications ...................................................................................................................283

Appendix B

Ordering Information and Mechanical Drawings

B.1 Ordering Information ....................................................................................................................285

B.1.1 Device Numbering Scheme ............................................................................................285

B.2 Mechanical Drawings ....................................................................................................................285

MC9S08GT16A/GT8A Data Sheet, Rev. 1

18 Freescale Semiconductor

Chapter 1 Device Overview

1.1 Introduction

The MC9S08GT16A/GT8A are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types (see Table 1-1).

1.1.1 Devices in the MC9S08GT16A/GT8A Series

Table 1-1 lists the devices available in the MC9S08GT16A/GT8A series and summarizes the differences

among them.

Table 1-1. Devices in the MC9S08GT16A/GT8A Series

Device FLASH RAM TPM ATD KBI I/O Packages

(1) 3-ch, (1) 2-ch, 16-bit 8 8 39 48 QFN

MC9S08GT16A 16K 2K

MC9S08GT8A 8K 1K (1) 3-ch, (1) 2-ch, 16-bit 8 8 39 48 QFN

(2) 2-ch, 16-bit 8 8 36 44 QFP

(2) 2-ch, 16-bit 8 8 34 42 SDIP

(1) 2-ch, (1) 1-ch, 16-bit 4 4 24 32 QFN

(2) 2-ch, 16-bit 8 8 36 44 QFP

(2) 2-ch, 16-bit 8 8 34 42 SDIP

(1) 2-ch, (1) 1-ch, 16-bit 4 4 24 32 QFN

1.1.2 MCU Block Diagram

This block diagrams show the structure of the MC9S08GT16A/GT8A MCUs.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 19

Device Overview

RESET

NOTE 4

IRQ

NOTES 2, 3

HCS08 CORE

CPU

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

RTI

IRQ LVD

BDC

COP

BKGD

REFL

REFH

SSAD

DDAD

8-BIT KEYBOARD INTERRUPT (KBI)

10-BIT

ANALOG-TO-DIGITAL

CONVERTER (ATD)

INTER-IC (IIC)

SERIAL COMMUNICATIONS

INTERFACE (SCI2)

SCL

SDA

RXD2

TXD2

PORT A

PORT B

PORT C

PTA7/KBIP7– PTA4/KBIP4

PTA3/KBIP3– PTA0/KBIP0

PTB7/ADP7– PTB4/ADP4

PTB3/ADP3– PTB0/ADP0

PTC7 PTC6 PTC5 PTC4 PTC3/SCL PTC2/SDA

PTC1/RxD2 PTC0/TxD2

NOTE 6

NOTE 5

USER FLASH

(GT16A = 16,384 BYTES)

(GT8A = 8192 BYTES)

USER RAM

(GT16A = 2048 BYTES)

(GT8A = 1024 BYTES)

ON-CHIP ICE

DEBUG

MODULE (DBG)

INTERNAL CLOCK

GENERATOR (ICG)

LOW-POWER OSCILLATOR

VOLTAGE

REGULATOR

2-CHANNEL TIMER/PWM

(TPM2)

3-CHANNEL TIMER/PWM

(TPM1)

SERIAL PERIPHERAL

INTERFACE (SPI)

SERIAL COMMUNICATIONS

INTERFACE (SCI1)

EXTAL

XTAL

BKGD

= Pins not available in 44-, 42-, or 32-pin packages = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages

CH1 CH0

CH0

CH1 CH2

SPSCK

MOSI MISO

RXD1 TXD1

PORT D

PORT E

PORT G

PTD4/TPM2CH1 PTD3/TPM2CLK/TPM2CH0

PTD2/TPM1CH2 PTD1/TPM1CH1 PTD0/TPM1CLK/TPM1CH0

PTE5/SPSCK PTE4/MOSI PTE3/MISO PTE2/SS

PTE1/RxD1 PTE0/TxD1

PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS

NOTES:

1. Port pins are software configurable with pullup device if input port.

2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).

3. IRQ does not have a clamp diode to V

4. Pin contains integrated pullup device.

. IRQ should not be driven above VDD.

5. High current drive

6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).

Figure 1-1. MC9S08GT16A/GT8A Block Diagram

MC9S08GT16A/GT8A Data Sheet, Rev. 1

20 Freescale Semiconductor

Table 1-2 lists the functional versions of the on-chip modules.

Table 1-2. Block Versions

Module Version

Analog-to-Digital Converter (ATD) 3

Internal Clock Generator (ICG) 4

Inter-Integrated Circuit (IIC) 1

Keyboard Interrupt (KBI) 1

Serial Communications Interface (SCI) 1

Serial Peripheral Interface (SPI) 3

Timer Pulse-Width Modulator (TPM) 2

Central Processing Unit (CPU) 2

1.2 System Clock Distribution

Device Overview

ICG

ICGERCLK

FFE

SYSTEM

CONTROL

LOGIC

RTI

TPM1 TPM2 IIC SCI1 SCI2 SPI

÷2

FIXED FREQ CLOCK (XCLK)

ICGOUT

ICGLCLK*

* ICGLCLK is the alternate BDC clock source for the MC9S08GT16A/GT8A.

÷2

CPU

BUSCLK

BDC

COP

Figure 1-2. System Clock Distribution Diagram

ATD

ATD has min and max frequency requirements. See Chapter 14, “Ana-

log-to-Digital Converter (S08ATDV3)”

and Appendix A, “Electrical

Characteristics.”

RAM FLASH

FLASH has frequency requirements for program and erase operation. See Appendix A, “Electrical

Characteristics”.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 21

Device Overview

Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simpliﬁed clock connection diagram. The ICG supplies the clock sources:

• ICGOUT is an output of the ICG module. It is one of the following: — The external crystal oscillator — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop

sub-module

Control bits inside the ICG determine which source is connected.

• FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the ﬁxed-frequency clock will be the ICGERCLK. Otherwise the ﬁxed-frequency clock will be BUSCLK.

• ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow.

• ICGERCLK — External reference clock can be selected as the real-time interrupt clock source.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

22 Freescale Semiconductor

Chapter 2 Pins and Connections

2.1 Introduction

This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals.

2.2 Device Pin Assignment

DDAD

RESET

PTC0/TxD2

PTC1/RxD2

PTC2/SDA

PTC3/SCL

PTC4

PTC5

PTC6

PTC7

PTE0/TxD1

PTE1/RxD1

IRQ

SSAD

PTG2/EXTAL

PTG1/XTAL

PTG3

PTG0/BKGD/MS

PTA6/KBIP6

PTA7/KBIP7

PTA4/KBIP4

PTA5/KBIP5

PTA2/KBIP2

PTA3/KBIP3

PTB0/ADP0

PTA1/KBIP1

PTA0/KBIP0

PTB7/ADP7

PTB6/ADP6

PTB5/ADP5

PTB4/ADP4

PTB3/ADP3

PTB2/ADP2

PTB1/ADP1

REFL

REFH

SS2

PTD1/TPM1CH1

PTD2/TPM1CH2

PTD0/TPM1CLK/TPM1CH0

PTD3/TPM2CLK/TPM2CH0

PTD4/TPM2CH1

PTE2/SS

PTE4/MOSI

PTE3/MISO

SS1

PTE5/SPSCK

Figure 2-1. MC9S08GT16A/GT8A in 48-Pin QFN Package

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 23

Pins and Connections

RESET

PTC0/TxD2

PTC1/RxD2

PTC2/SDA

PTC3/SCL

PTC4

PTC5

PTC6

PTE0/TxD1

PTE1/RxD1

IRQ

PTG2/EXTAL

PTG1/XTAL

PTG0/BKGD/MS

SSAD

DDAD

PTA5/KBIP5

PTA6/KBIP6

PTA7/KBIP7

PTA4/KBIP4

PTA2/KBIP2

PTA3/KBIP3

PTA1/KBIP1

PTA0/KBIP0

REFL

REFH

PTB7/ADP7

PTB6/ADP6

PTB5/ADP5

PTB4/ADP4

PTB3/ADP3

PTB2/ADP2

PTB1/ADP1

PTE2/SS

PTE3/MISO

PTE4/MOSI

PTE5/SPSCK

PTD1/TPM1CH1

PTD0/TPM1CLK/TPM1CH0

PTD3/TPM2CLK/TPM2CH0

PTB0/ADP0

PTD4/TPM2CH1

Figure 2-2. MC9S08GT16A/GT8A in 44-Pin QFP Package

MC9S08GT16A/GT8A Data Sheet, Rev. 1

24 Freescale Semiconductor

Pins and Connections

DDAD

SSAD

PTG0/BKGD/MS

PTG1/XTAL

PTG2/EXTAL

RESET

PTC0/TxD2

PTC1/RXD2

PTC2/SDA

PTC3/SCL

PTC4

PTE0/TxD1

PTE1/RxD1

IRQ

PTE2/

PTE3/MISO

PTE4/MOSI

15 28

16 27

17 26

PTA7/KBIP7

PTA6/KBIP6

PTA5/KBIP5

PTA4/KBIP4

PTA3/KBIP3

PTA2/KBIP2

PTA1/KBIP1

PTA0/KBIP0

REFL

REFH

PTB7/ADP7

PTB6/ADP6

PTB5/ADP5

PTB4/ADP4

PTB3/ADP3

PTB2/ADP2

PTB1/ADP1

PTE5/SPSCK

PTD0/TPM1CLK/TPM1CH0

Figure 2-3. MC9S08GT16A/GT8A in 42-Pin SDIP Package

18 25

19 24

20 23

21 22

PTB0/ADP0

PTD4/TPM2CH1

PTD3/TPM2CLK/TPM2CH0

PTD1/TPM1CH1

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 25

Pins and Connections

RESET

PTC0/TxD2

PTC1/RxD2

PTC2/SDA

PTC3/SCL

PTE0/TxD1

PTE1/RxD1

IRQ

PTG2/EXTAL

PTG1/XTAL

PTG0/BKGD

31 30 29

DDAD

SSAD

12 13 14

PTA6/KBIP6

PTA7/KBIP7

PTA5/KBIP5

PTB3/ADP3

PTB2/ADP2

PTB0/ADP0

PTA4/KBIP4

REFL

REFH

PTB1/ADP1

PTD3/TPM2CLK/TPM2CH0

PTE2/SS

PTE3/MISO

PTE4/MOSI

PTE5/SPSCK

PTD1/TPM1CH1

PTD0/TPM1CLK/TPM1CH0

Figure 2-4. MC9S08GT16A/GT8A in 32-Pin QFN Package

MC9S08GT16A/GT8A Data Sheet, Rev. 1

26 Freescale Semiconductor

Pins and Connections

2.3 Recommended System Connections

Figure 2-5 shows pin connections that are common to almost all MC9S08GT16A application systems. A

more detailed discussion of system connections follows.

SYSTEM POWER

BACKGROUND HEADER

OPTIONAL

MANUAL

RESET

3 V

BLK

10 µF

BKGD/MS

ASYNCHRONOUS

INTERRUPT

INPUT

0.1 µF

4.7 kΩ–10 kΩ

0.1 µF

4.7 kΩ–10 kΩ

0.1 µF

BYAD

0.1 µF

REFH

DDAD

SSAD

REFL

MC9S08GT16A

NOTE4

RESET

NOTE 3

IRQ NOTE 3

PORT

PTA0/KBIP0

PTA1/KBIP1

PTA2/KBIP2

PTA3/KBIP3

PTA4/KBIP4

PTA5/KBIP5

PTA6/KBIP6

PTA7/KBIP7

PTB0/ADP0

PTB1/ADP1

PTB2/ADP2

PTB3/ADP3

PTB4/ADP4

PTB5/ADP5

PTB6/ADP6

PTB7/ADP7

PTC0/TxD2

PTC1/RxD2

PTC2/SDA

PTC3/SCL

PTC4

PTC5

PTC6

PTC7

I/O AND

PERIPHERAL

INTERFACE TO

APPLICATION

SYSTEM

PTD0/TPM1CLK/TPM1CH0

PTD1/TPM1CH1

PTD2/TPM1CH2

PTD3/TPM2CLK/TPM2CH0

PTD4/TPM2CH1

PTE0/TxD1

PTE1/RxD1

PTE2/

PTE3/MISO

PTE4/MOSI

PTE5/SPSCK

NOTE 1

PTG0/BKDG/MS

PTG2/EXTAL

PTG1/XTAL

PTG3

XTAL

EXTAL

PORT

NOTES:

1. Not required if using the internal oscillator option.

2. The 48-pin QFN has 2 V

3. RC filters on

RESET and IRQ are recommended for EMC-sensitive applications and systems.

pins (V

SS1

and V

), both of which must be connected to GND.

SS2

Figure 2-5. Basic System Connections

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 27

Pins and Connections

2.3.1 VDD, VSS, V

DDAD

, V

SSAD

, V

REFH

, V

— Power and Voltage

REFL

References

VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU.

Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-µF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-µF ceramic bypass capacitor located as close to the MCU power pins as practical to suppress high-frequency noise.

NOTE

The 48-pin QFN version of the MC9S08GT16A/GT8A has two adjacent

pins. Both pins must be connected to ground with zero impedance

between them.

DDAD

and V the ATD. A 0.1-µF ceramic bypass capacitor should be located as close to the MCU power pins as practical to suppress high-frequency noise.

REFH

and V

V performance, they must be connected directly to V

are the analog power supply pins for the MCU. This voltage source supplies power to

SSAD

are the reference voltages for the analog-to-digital converter and for most accurate

REFL

DDAD

and V

with the shortest traces possible.

SSAD

2.3.2 PTG1/XTAL, PTG2/EXTAL — Oscillator

Immediately after reset, the MCU uses an internally generated clock (self-clocked mode — f

Self_reset

is approximately equivalent to an 8-MHz crystal rate. This frequency source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information on the ICG, see Chapter 9, “Internal Clock Generator (S08ICGV4).”

The oscillator amplitude on XTAL and EXTAL is gain limited for low-power oscillation. Typically, these pins have a 1-V peak-to-peak signal. For noisy environments, the high gain output (HGO) bit can be set to enable rail-to-rail oscillation.

The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin, and the XTAL output pin can be used as general I/O. The external oscillator amplitude must not exceed V

Refer to Figure 2-5 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors, and some metal ﬁlm resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are speciﬁcally designed for high-frequency applications.

is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its

value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup.

), that

MC9S08GT16A/GT8A Data Sheet, Rev. 1

28 Freescale Semiconductor

Pins and Connections

C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a speciﬁc crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically speciﬁes a load capacitance which is the series combination of C1 and C2 which are usually the same size. As a ﬁrst-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL).

2.3.3 RESET — External Reset Pin

RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).

Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for approximately 34 cycles of f 38 cycles of f

Self_reset

later. If reset was caused by an internal source such as low-voltage reset or watchdog

Self_reset

timeout, the circuitry expects the reset pin sample to return a logic 1. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (SRS).

, released, and sampled again approximately

For EMC-sensitive applications, an external RC ﬁlter is recommended on the

RESET pin. See Figure 2-5

for an example.

2.3.4 PTG0/BKGD/MS — Background / Mode Select

The background/mode select (BKGD/MS) shares its function with an I/O port pin. While in reset, the pin functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and can be used for background debug communication. While functioning as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control. When used as an I/O port (PTG0) the pin is limited to output only.

If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the rising edge of reset which forces the MCU to active background mode.

The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the maximum bus clock rate, so there should never be any signiﬁcant capacitance connected to the BKGD/MS pin that could interfere with background serial communications.

Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 29

Pins and Connections

2.3.5 IRQ — External Interrupt Request Pin

IRQ is a dedicated pin with both pullup and pulldown devices built in. This pin has no output capabilities. After a system reset, the IRQ pin is disabled and must be enabled before use. See Section 5.4.2, “IRQ —

External Interrupt Request Pin” for more details.

For EMC-sensitive applications, an external RC ﬁlter is recommended on the IRQ pin. See Figure 2-5 for an example.

2.3.6 General-Purpose I/O and Peripheral Ports

The remaining 36 pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and serial I/O systems. (Three of these pins are not bonded out on the 44-pin package, ﬁve are not bonded out on the 42-pin package, and 15 are not bonded out on the 32-pin package.) Immediately after reset, all 36 of these pins are conﬁgured as high-impedance general-purpose inputs with internal pullup devices disabled.

NOTE

To avoid extra current drain from ﬂoating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not ﬂoat.

For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel

Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the

appropriate section from Table 2-1.

Table 2-1. Pin Sharing References

Port Pins Alternate Function

PTA7–PTA0 KBIP7–KBIP0 Chapter 7, “Keyboard Interrupt (S08KBIV1)”

PTB7–PTB0 ADP7–ADP0 Chapter 14, “Analog-to-Digital Converter (S08ATDV3)”

PTC7–PTC4

PTC3–PTC2 SCL–SDA Chapter 13, “Inter-Integrated Circuit (S08IICV1)”

PTC1–PTC0 RxD2–TxD2 Chapter 11, “Serial Communications Interface (S08SCIV1)”

PTD4–PTD3 TPM2CH1–TPM2CH0, TPM2CLK Chapter 10, “Timer/PWM (S08TPMV2)”

PTD2–PTD0 TPM1CH2–TPM1CH0, TPM1CLK Chapter 10, “Timer/PWM (S08TPMV2)”

PTE5 PTE4 PTE3 PTE2

PTE1–PTE0 RxD1–TxD1 Chapter 11, “Serial Communications Interface (S08SCIV1)”

PTG3

PTG2–PTG1 EXTAL–XTAL Chapter 9, “Internal Clock Generator (S08ICGV4)”

PTG0 BKGD/MS Chapter 15, “Development Support”

See this section for information about modules that share these pins.

SPSCK MISO MOSI SS

Chapter 12, “Serial Peripheral Interface (S08SPIV3)”

Reference

MC9S08GT16A/GT8A Data Sheet, Rev. 1

30 Freescale Semiconductor

Pins and Connections

When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. See Chapter 6, “Parallel Input/Output,” for details.

Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4 pins are controlled by the KBI module and are conﬁgured for rising-edge/high-level sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is conﬁgured as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device rather than a pullup device.

2.3.7 Signal Properties Summary

Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the

common pin interfaces are hardwired to internal circuits.

Table 2-2. Signal Properties

Name

DDAD

SSAD

REFH

REFL

RESET

IRQ

PTA0/KBIP0 I/O N SWC SWC

PTA1/KBIP1 I/O N SWC SWC

PTA2/KBIP2 I/O N SWC SWC

PTA3/KBIP3 I/O N SWC SWC

PTA4/KBIP4 I/O N SWC SWC Pullup/pulldown active when KBI pin

PTA5/KBIP5 I/O N SWC SWC

PTA6/KBIP6 I/O N SWC SWC

PTA7/KBIP7 I/O N SWC SWC

PTB0/ADP0 I/O N SWC SWC

PTB1/ADP1 I/O N SWC SWC

PTB2/ADP2 I/O N SWC SWC

High Current

Dir

I/O Y N Y Pin contains integrated pullup.

I— — Y

———

Output

Slew

Pull-Up

The 48-pin QFN package has two V

SS1

and V

— V

IRQPE must be set to enable IRQ function. IRQ does not have a clamp diode to V

IRQ should not be driven above V Pullup/pulldown active when IRQ pin

function enabled. Pullup forced on when IRQ enabled for falling edges; pulldown forced on when IRQ enabled for rising edges.

function enabled. Pullup forced on when KBIPx enabled for falling edges; pulldown forced on when KBIPx enabled for rising edges.

Comments

SS2

pins

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 31

Pins and Connections

Table 2-2. Signal Properties (continued)

Name

Dir

High Current

Output

Slew

Pull-Up

PTB3/ADP3 I/O N SWC SWC

PTB4/ADP4 I/O N SWC SWC Not available on 32-pin pkg

PTB5/ADP5 I/O N SWC SWC Not available on 32-pin pkg

PTB6/ADP6 I/O N SWC SWC Not available on 32-pin pkg

PTB7/ADP7 I/O N SWC SWC Not available on 32-pin pkg

PTC0/TxD2 I/O Y SWC SWC

PTC1/RxD2 I/O Y SWC SWC

When pin is conﬁgured for SCI function, pin is conﬁgured for partial output drive.

PTC2/SDA I/O Y SWC SWC

PTC3/SCL I/O Y SWC SWC

PTC4 I/O Y SWC SWC Not available on 32-pin pkg

PTC5 I/O Y SWC SWC Not available on 32-pin or 42-pin pkg

PTC6 I/O Y SWC SWC Not available on 32-pin or 42-pin pkg

PTC7 I/O Y SWC SWC Not available on 32-pin, 42- or 44-pin pkg

PTD0/TPM1CLK/TPM1CH0 I/O N SWC SWC

PTD1/TPM1CH1 I/O N SWC SWC

PTD2/TPM1CH2 I/O N SWC SWC Not available on 32-pin, 42- or 44-pin pkg

PTD3/TPM2CLK/TPM2CH0 I/O N SWC SWC

PTD4/TPM2CH1 I/O N SWC SWC Not available on 32-pin pkg

PTE0/TxD1 I/O N SWC SWC

PTE1/RxD1 I/O N SWC SWC

PTE2/

I/O N SWC SWC

PTE3/MISO I/O N SWC SWC

PTE4/MOSI I/O N SWC SWC

PTE5/SPSCK I/O N SWC SWC

PTG0/BKGD/MS O N SWC SWC

PTG1/XTAL I/O N SWC SWC

PTG2/EXTAL I/O N SWC SWC

Pullup enabled and slew rate disabled when BDM function enabled.

Pullup and slew rate disabled when XTAL pin function.

Pullup and slew rate disabled when EXTAL pin function.

PTG3 I/O N SWC SWC Not available on 32-pin, 42-, or 44-pin pkg

SWC is software controlled slew rate, the register is associated with the respective port.

SWC is software controlled pullup resistor, the register is associated with the respective port.

Comments

MC9S08GT16A/GT8A Data Sheet, Rev. 1

32 Freescale Semiconductor

Chapter 3 Modes of Operation

3.1 Introduction

The operating modes of the MC9S08GT16A/GT8A are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described.

3.1.1 Features

• Active background mode for code development

• Wait mode: — CPU shuts down to conserve power — System clocks running — Full voltage regulation maintained

• Stop modes: — Stop1 — Full power down of internal circuits for maximum power savings — Stop2 — Partial power down of internal circuits, RAM contents retained — Stop3 — All internal circuits powered for fast recovery

3.2 Run Mode

This is the normal operating mode for the MC9S08GT16A/GT8A. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset.

3.3 Active Background Mode

The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip ICE debug module (DBG), provide the means for analyzing MCU operation during software development.

Active background mode is entered in any of ﬁve ways:

• When the BKGD/MS pin is low at the rising edge of reset

• When a BACKGROUND command is received through the BKGD pin

• When a BGND instruction is executed

• When encountering a BDC breakpoint

• When encountering a DBG breakpoint

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 33

Modes of Operation

After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program.

Background commands are of two types:

• Non-intrusive commands, deﬁned as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed while the MCU is in the active background mode. Non-intrusive commands include:

— Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command

• Active background commands, which can be executed only while the MCU is in active background mode. Active background commands include commands to:

— Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user’s application program (GO)

The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the ﬁrst time. When the MC9S08GT16A/GT8A is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless speciﬁcally noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed. The active background mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed.

For additional information about the active background mode, refer to Chapter 15, “Development

Support.”

3.4 Wait Mode

Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.

While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

34 Freescale Semiconductor

Modes of Operation

3.5 Stop Modes

One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.

Table 3-1 summarizes the behavior of the MCU in each of the stop modes.

Table 3-1. Stop Mode Behavior

CPU, Digital

Mode PDC PPDC

Peripherals,

FLASH

RAM ICG ATD Regulator I/O Pins RTI

Stop1 1 0 Off Off Off Disabled

Stop2 1 1 Off Standby Off Disabled Standby States

Stop3 0 Don’t

care

Either ATD stop mode or power-down mode depending on the state of ATDPU.

Crystal oscillator can be conﬁgured to run in stop3. Please see the ICG registers.

Standby Standby Off

Disabled Standby States

Off Reset Off

Optionally on

held

Optionally on

held

3.5.1 Stop1 Mode

The stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry of the MCU to be powered down. Stop1 can be entered only if the LVD circuit is not enabled in stop modes (either LVDE or LVDSE not set).

When the MCU is in stop1 mode, all internal circuits that are powered from the voltage regulator are turned off. The voltage regulator is in a low-power standby state, as is the ATD.

Exit from stop1 is performed by asserting either of the wake-up pins on the MCU: always an active low input when the MCU is in stop1, regardless of how it was conﬁgured before entering stop1.

Entering stop1 mode automatically asserts LVD. Stop1 cannot be exited until V must rise above the LVI rearm voltage).

RESET or IRQ. IRQ is

LVDH/L

rising (V

Upon wake-up from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will take the reset vector.

3.5.2 Stop2 Mode

The stop2 mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in stop modes (either LVDE or LVDSE not set).

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 35

Modes of Operation

Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped registers they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2, these values can be restored by user software before pin latches are opened.

When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ATD. Upon entry into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting stop2 mode until a 1 is written to PPDACK in SPMSC2.

Exit from stop2 is performed by asserting either of the wake-up pins:

RESET or IRQ, or by an RTI interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of how it was conﬁgured before entering stop2.

Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized.

After waking up from stop2, the PPDF bit in SPMSC2 is set. This ﬂag may be used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to PPDACK in SPMSC2.

To maintain I/O state for pins that were conﬁgured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states.

For pins that were conﬁgured as peripheral I/O, the user must reconﬁgure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened.

3.5.3 Stop3 Mode

Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The ICG is turned off, the ATD is disabled, and the voltage regulator is put in standby. The states of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained.

Exit from stop3 is performed by asserting interrupt. The asynchronous interrupt pins are the IRQ or KBI pins.

If stop3 is exited by means of the

RESET pin, then the MCU will be reset and operation will resume after taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in the MCU taking the appropriate interrupt vector.

A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function

MC9S08GT16A/GT8A Data Sheet, Rev. 1

36 Freescale Semiconductor

RESET, an asynchronous interrupt pin, or through the real-time

Modes of Operation

and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop.

3.5.4 Active BDM Enabled in Stop Mode

Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in the Chapter 15, “Development Support,” section of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3.

Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After the device enters background debug mode, all background commands are available. The table below summarizes the behavior of the MCU in stop when entry into the background debug mode is enabled.

Table 3-2. BDM Enabled Stop Mode Behavior

CPU, Digital

Mode PDC PPDC

Stop3 Don’t

care

Either ATD stop mode or power-down mode depending on the state of ATDPU.

Don’t

care

Peripherals,

FLASH

Standby Standby Active Disabled

RAM ICG ATD Regulator I/O Pins RTI

Active States

Optionally on

held

3.5.5 LVD Enabled in Stop Mode

The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in SPMSC1 when the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE = 1), the MCU will instead enter stop3. The table below summarizes the behavior of the MCU in stop when the LVD is enabled.

Table 3-3. LVD Enabled Stop Mode Behavior

CPU, Digital

Mode PDC PPDC

Stop3 Don’t

care

Either ATD stop mode or power-down mode depending on the state of ATDPU.

Don’t

care

Peripherals,

FLASH

Standby Standby Standby Disabled

RAM ICG ATD Regulator I/O Pins RTI

Active States

Optionally on

held

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 37

Modes of Operation

3.5.6 On-Chip Peripheral Modules in Stop Modes

When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.5.1, “Stop1

Mode,” Section 3.5.2, “Stop2 Mode,” and Section 3.5.3, “Stop3 Mode,” for speciﬁc information on system

behavior in stop modes.

I/O Pins

• All I/O pin states remain unchanged when the MCU enters stop3 mode.

• If the MCU is conﬁgured to go into stop2 mode, all I/O pins states are latched before entering stop.

• If the MCU is conﬁgured to go into stop1 mode, all I/O pins are forced to their default reset state upon entry into stop.

Memory

• All RAM and register contents are preserved while the MCU is in stop3 mode.

• All registers will be reset upon wake-up from stop2, but the contents of RAM are preserved and pin states remain latched until the PPDACK bit is written. The user may save any memory-mapped register data into RAM before entering stop2 and restore the data upon exit from stop2.

• All registers will be reset upon wake-up from stop1 and the contents of RAM are not preserved. The MCU must be initialized as upon reset. The contents of the FLASH memory are nonvolatile and are preserved in any of the stop modes.

ICG — In stop3 mode, the ICG enters its low-power standby state. Either the oscillator or the internal reference may be kept running when the ICG is in standby by setting the appropriate control bit. In both stop2 and stop1 modes, the ICG is turned off. Neither the oscillator nor the internal reference can be kept running in stop2 or stop1, even if enabled within the ICG module.

TPM — When the MCU enters stop mode, the clock to the TPM1 and TPM2 modules stop. The modules halt operation. If the MCU is conﬁgured to go into stop2 or stop1 mode, the TPM modules will be reset upon wake-up from stop and must be reinitialized.

ATD — When the MCU enters stop mode, the ATD will enter a low-power standby state

. No conversion

operation will occur while in stop. If the MCU is conﬁgured to go into stop2 or stop1 mode, the ATD will be reset upon wake-up from stop and must be reinitialized.

KBI — During stop3, the KBI pins that are enabled continue to function as interrupt sources that are capable of waking the MCU from stop3. The KBI is disabled in stop1 and stop2 and must be reinitialized after waking up from either of these modes.

SCI — When the MCU enters stop mode, the clocks to the SCI1 and SCI2 modules stop. The modules halt operation. If the MCU is conﬁgured to go into stop2 or stop1 mode, the SCI modules will be reset upon wake-up from stop and must be reinitialized.

SPI — When the MCU enters stop mode, the clocks to the SPI module stop. The module halts operation. If the MCU is conﬁgured to go into stop2 or stop1 mode, the SPI module will be reset upon wake-up from stop and must be reinitialized.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

38 Freescale Semiconductor

Modes of Operation

IIC — When the MCU enters stop mode, the clocks to the IIC module stops. The module halts operation. If the MCU is conﬁgured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized.

Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD is enabled in stop mode or BDM is enabled.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 39

Modes of Operation

MC9S08GT16A/GT8A Data Sheet, Rev. 1

40 Freescale Semiconductor

Chapter 4 Memory

4.1 MC9S08GT16A/GT8A Memory Map

As shown in Figure 4-1, on-chip memory in the MC9S08GT16A/GT8A series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups:

• Direct-page registers (0x0000 through 0x007F)

• High-page registers (0x1800 through 0x182B)

• Nonvolatile registers (0xFFB0 through 0xFFBF)

DIRECT PAGE REGISTERS

RAM 2048 BYTES

UNIMPLEMENTED

3968 BYTES

HIGH PAGE REGISTERS

UNIMPLEMENTED

42964 BYTES

FLASH

16384 BYTES

MC9S08GT16A

0x0000

0x007F 0x0080

0x087F 0x0880

0x17FF 0x1800

0x182B 0x182C

0xBFFF

0xC000

0xFFFF

DIRECT PAGE REGISTERS

RAM 1024 BYTES

Reserved 1024 BYTES

UNIMPLEMENTED UNIMPLEMENTED

4992 BYTES

3968 BYTES

HIGH PAGE REGISTERS

UNIMPLEMENTED

42964 BYTES

Reserved

8192 BYTES

FLASH

8192 BYTES

MC9S08GT8A

0x0000

0x007F 0x0080

0x047F 0x0480

0x087F 0x0880

0x17FF

0x1800

0x182B

0x182C

0xBFFF

0xC000

0xDFFF

0xE000

0xFFFF

Figure 4-1. MC9S08GT16A/GT8A Memory Map

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 41

Memory

4.1.1 Reset and Interrupt Vector Assignments

Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table

are the labels used in the Freescale-provided equate ﬁle for the MC9S08GT16A/GT8A. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets,

Interrupts, and System Conﬁguration.”

Table 4-1. Reset and Interrupt Vectors

Address

(High/Low)

0xFFC0:FFC1

Unused Vector Space

(available for user program)

0xFFCA:FFCB

0xFFCC:FFCD RTI Vrti

0xFFCE:FFCF IIC Viic

0xFFD0:FFD1 ATD Conversion Vatd

0xFFD2:FFD3 Keyboard Vkeyboard

0xFFD4:FFD5 SCI2 Transmit Vsci2tx

0xFFD6:FFD7 SCI2 Receive Vsci2rx

0xFFD8:FFD9 SCI2 Error Vsci2err

0xFFDA:FFDB SCI1 Transmit Vsci1tx

0xFFDC:FFDD SCI1 Receive Vsci1rx

0xFFDE:FFDF SCI1 Error Vsci1err

0xFFE0:FFE1 SPI Vspi

0xFFE2:FFE3 TPM2 Overﬂow Vtpm2ovf

0xFFE4:FFE9

0xFFEA:FFEB TPM2 Channel 1 Vtpm2ch1

0xFFEC:FFED TPM2 Channel 0 Vtpm2ch0

0xFFEE:FFEF TPM1 Overﬂow Vtpm1ovf

0xFFF0:FFF1 TPM1 Channel 2 Vtpm1ch2

0xFFF2:FFF3 TPM1 Channel 1 Vtpm1ch1

0xFFF4:FFF5 TPM1 Channel 0 Vtpm1ch0

0xFFF6:FFF7 ICG Vicg

0xFFF8:FFF9 Low Voltage Detect Vlvd

0xFFFA:FFFB IRQ Virq

0xFFFC:FFFD SWI Vswi

0xFFFE:FFFF Reset Vreset

(available for user program)

Vector Vector Name

Unused Vector Space

MC9S08GT16A/GT8A Data Sheet, Rev. 1

42 Freescale Semiconductor

Memory

4.2 Register Addresses and Bit Assignments

The registers in the MC9S08GT16A/GT8A are divided into these three groups:

• Direct-page registers are located in the ﬁrst 128 locations in the memory map, so they are accessible with efﬁcient direct addressing mode instructions.

• High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables.

• The nonvolatile register area consists of a block of 16 locations in FLASH memory at 0xFFB0–0xFFBF.

Nonvolatile register locations include: — Three values which are loaded into working registers at reset — An 8-byte backdoor comparison key which optionally allows a user to gain controlled access

to secure memory

Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations.

Direct-page registers can be accessed with efﬁcient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits.

The direct page registers in Table 4-2 can use the more efﬁcient direct addressing mode which only requires the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In

Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart

from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 43

Memory

Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)

Address Register Name Bit 7 654321Bit 0

0x0000 PTAD

0x0001 PTAPE

0x0002 PTASE

0x0003 PTADD

0x0004 PTBD

0x0005 PTBPE

0x0006 PTBSE

0x0007 PTBDD

0x0008 PTCD

0x0009 PTCPE

0x000A PTCSE

0x000B PTCDD

0x000C PTDD

0x000D PTDPE

0x000E PTDSE

0x000F PTDDD

0x0010 PTED

0x0011 PTEPE

0x0012 PTESE

0x0013 PTEDD

0x0014 IRQSC

0x0015 Reserved

0x0016 KBISC

0x0017 KBIPE

0x0018 SCI1BDH

0x0019 SCI1BDL

0x001A SCI1C1

0x001B SCI1C2

0x001C SCI1S1

0x001D SCI1S2

0x001E SCI1C3

0x001F SCI1D

0x0020 SCI2BDH

0x0021 SCI2BDL

0x0022 SCI2C1

0x0023 SCI2C2

0x0024 SCI2S1

0x0025 SCI2S2

0x0026 SCI2C3

0x0027 SCI2D

PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0

PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0

PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0

PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0

PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0

PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0

PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0

PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0

PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0

PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0

PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0

PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0

0 0 0 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0

0 0 0 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0

0 0 0 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0

0 0 0 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0

0 0 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0

0 0 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0

0 0 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0

0 0 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0

0 0 IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD

— — — — — — — —

KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBF KBACK KBIE KBIMOD

KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0

0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8

SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

LOOPS SCISWAI RSRC M WAKE ILT PE PT

TIE TCIE RIE ILIE TE RE RWU SBK

TDRE TC RDRF IDLE OR NF FE PF

0 0 0 0 0 0 0 RAF

R8 T8 TXDIR 0 ORIE NEIE FEIE PEIE

Bit 7 654321Bit 0

0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8

SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

LOOPS SCISWAI RSRC M WAKE ILT PE PT

TIE TCIE RIE ILIE TE RE RWU SBK

TDRE TC RDRF IDLE OR NF FE PF

0 0 0 0 0 0 0 RAF

R8 T8 TXDIR 0 ORIE NEIE FEIE PEIE

Bit 7 654321Bit 0

MC9S08GT16A/GT8A Data Sheet, Rev. 1

44 Freescale Semiconductor

Memory

Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)

Address Register Name Bit 7 654321Bit 0

0x0028 SPIC1

0x0029 SPIC2

0x002A SPIBR

0x002B SPIS

0x002C Reserved

0x002D SPID

0x002E Reserved

0x002F Reserved

0x0030 TPM1SC

0x0031 TPM1CNTH

0x0032 TPM1CNTL

0x0033 TPM1MODH

0x0034 TPM1MODL

0x0035 TPM1C0SC

0x0036 TPM1C0VH

0x0037 TPM1C0VL

0x0038 TPM1C1SC

0x0039 TPM1C1VH

0x003A TPM1C1VL

0x003B TPM1C2SC

0x003C TPM1C2VH

0x003D TPM1C2VL

0x003E– 0x0043

Reserved

0x0044 PTGD

0x0045 PTGPE

0x0046 PTGSE

0x0047 PTGDD

0x0048 ICGC1

0x0049 ICGC2

0x004A ICGS1

0x004B ICGS2

0x004C ICGFLTU

0x004D ICGFLTL

0x004E ICGTRM

0x004F Reserved

0x0050 ATDC

0x0051 ATDSC

0x0052 ATDRH

0x0053 ATDRL

SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE

0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0

0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0

SPRF 0 SPTEF MODF 0 0 0 0

0 0 0 0 0 0 0 0

Bit 7 654321Bit 0

0 0 0 0 0 0 0 0

TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

— —

0 0 0 0 PTGD3 PTGD2 PTGD1 PTGD0

0 0 0 0 PTGPE3 PTGPE2 PTGPE1 PTGPE0

0 0 0 0 PTGSE3 PTGSE2 PTGSE1 PTGSE0

0 0 0 0 PTGDD3 PTGDD2 PTGDD1 PTGDD0

HGO RANGE REFS CLKS OSCSTEN LOCD 0

LOLRE MFD LOCRE RFD

CLKST REFST LOLS LOCK LOCS ERCS ICGIF

0 0 0 0 0 0 0 DCOS

0 0 0 0FLT

0 0 0 0 0 0 0 0

ATDPU DJM RES8 SGN PRS

CCF ATDIE ATDCO ATDCH

Bit 7 654321Bit 0

— —

FLT

TRIM

— —

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 45

Memory

Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)

Address Register Name Bit 7 654321Bit 0

0x0054 ATDPE

0x0055– 0x0057

Reserved

0x0058 IICA

0x0059 IICF

0x005A IICC

0x005B IICS

0x005C IICD

0x005D– 0x005F

Reserved

0x0060 TPM2SC

0x0061 TPM2CNTH

0x0062 TPM2CNTL

0x0063 TPM2MODH

0x0064 TPM2MODL

0x0065 TPM2C0SC

0x0066 TPM2C0VH

0x0067 TPM2C0VL

0x0068 TPM2C1SC

0x0069 TPM2C1VH

0x006A TPM2C1VL

0x006B– 0x007F

Reserved

ATDPE7 ATDPE6 ATDPE5 ATDPE4 ATDPE3 ATDPE2 ATDPE1 ATDPE0

— —

MULT ICR

IICEN IICIE MST TX TXAK RSTA 0 0

TCF IAAS BUSY ARBL 0 SRW IICIF RXAK

— —

TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

— —

ADDR 0

DATA

— —

High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800.

Table 4-3. High-Page Register Summary

Address Register Name Bit 7 654321Bit 0

0x1800 SRS

0x1801 SBDFR

0x1802 SOPT 0x1803 –

0x1805

Reserved

0x1806 SDIDH

0x1807 SDIDL

0x1808 SRTISC

0x1809 SPMSC1

0x180A SPMSC2

0x180B– 0x180F

Reserved

0x1810 DBGCAH

POR PIN COP ILOP ILAD ICG LVD 0

0 0 0 0 0 0 0 BDFR

COPE COPT STOPE — 0 0 BKGDPE —

— —

ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

RTIF RTIACK RTICLKS RTIE 0 RTIS2 RTIS1 RTIS0

LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0 0

LVWF LVWACK LVDV LVWV PPDF PPDACK PDC PPDC

— —

Bit 15 14 13 12 11 10 9 Bit 8

— —

MC9S08GT16A/GT8A Data Sheet, Rev. 1

— —

ID11 ID10 ID9 ID8

— —

46 Freescale Semiconductor

Memory

Table 4-3. High-Page Register Summary (continued)

Address Register Name Bit 7 654321Bit 0

0x1811 DBGCAL

0x1812 DBGCBH

0x1813 DBGCBL

0x1814 DBGFH

0x1815 DBGFL

0x1816 DBGC

0x1817 DBGT

0x1818 DBGS

0x1819– 0x181F

Reserved

0x1820 FCDIV

0x1821 FOPT

0x1822 Reserved

0x1823 FCNFG

0x1824 FPROT

0x1825 FSTAT

0x1826 FCMD

0x1827– 0x182B

Reserved

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN

TRGSEL BEGIN 0 0 TRG3 TRG2 TRG1 TRG0

AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0

— —

DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0

KEYEN FNORED 0 0 0 0 SEC01 SEC00

— — — — — — — —

0 0 KEYACC 0 0 0 0 0

FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS

FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0

FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0

— —

Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options.

Table 4-4. Nonvolatile Register Summary

Address Register Name Bit 7 654321Bit 0

0xFFB0 – 0xFFB7

0xFFB8 – 0xFFBC

0xFFBD NVPROT

0xFFBE NVICGTRM

0xFFBF NVOPT

NVICGTRM is the factory trim value. This value must be copied to ICGTRM in user code.

NVBACKKEY

Reserved

8-Byte Comparison Key

— —

FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS

KEYEN FNORED 0 0 0 0 SEC01 SEC00

— —

NVTRIM

— —

Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the

MC9S08GT16A/GT8A Data Sheet, Rev. 1

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Memory

only way to disengage security is by mass erasing the FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0).

4.3 RAM

The MC9S08GT16A/GT8A includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efﬁcient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred.

The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention.

For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08GT16A/GT8A, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate ﬁle).

LDHX #RamLast+1 ;point one past RAM TXS ;SP<-(H:X-1)

When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or through code executing from non-secure memory. See Section 4.5, “Security,” for a detailed description of the security feature.

4.4 FLASH

The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after ﬁnal assembly of the application product. It is possible to program the entire array through the single-wire background debug interface. Because no special voltages are needed for FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMV1/D.

4.4.1 Features

Features of the FLASH memory include:

• FLASH Size — MC9S08GT16A — 16384 bytes (32 pages of 512 bytes each) — MC9S08GT8A — 8192 bytes (16 pages of 512 bytes each)

• Single power supply program and erase down to 1.8 V

• Command interface for fast program and erase operation

• Up to 100,000 program/erase cycles at typical voltage and temperature

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Memory

• Flexible block protection

• Security feature for FLASH and RAM

• Auto power-down for low-frequency read accesses

4.4.2 Program and Erase Times

Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must be written to set the internal clock for the FLASH module to a frequency (f 200 kHz (see Table 4.6.1). This register can be written only once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error ﬂag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting clock (1/f

) is used by the command processor to time program and erase pulses. An integer number

FCLK

of these timing pulses is used by the command processor to complete a program or erase command.

Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency

of FCLK (f

). The time for one cycle of FCLK is t

FCLK

of cycles of FCLK and as an absolute time for the case where t

FCLK

= 1/f

FCLK

. The times are shown as a number

FCLK

=5µs. Program and erase times shown include overhead for the command state machine and enabling and disabling of program and erase voltages.

) between 150 kHz and

FCLK

Table 4-5. Program and Erase Times

Parameter Cycles of FCLK Time if FCLK = 200 kHz

Byte program 9 45 µs

Byte program (burst) 4

Page erase 4000 20 ms

Mass erase 20,000 100 ms

Excluding start/end overhead

20 µs

4.4.3 Program and Erase Command Execution

The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error ﬂags cleared before beginning command execution. The command execution steps are:

1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into the FLASH interface. This write is a required ﬁrst step in any command sequence. For erase and blank check commands, the value of the data is not important. For page erase commands, the address may be any address in the 512-byte page of FLASH to be erased. For mass erase and blank check commands, the address can be any address in the FLASH memory. Whole pages of 512 bytes are the smallest blocks of FLASH that may be erased.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

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Memory

NOTE

Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits in a byte which is already programmed is not allowed without ﬁrst erasing the page in which the byte resides or mass erasing the entire FLASH memory. Programming without ﬁrst erasing may disturb data stored in the FLASH.

2. Write the command code for the desired command to FCMD. The ﬁve valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). The command code is latched into the command buffer.

3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data information).

A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to the memory array and before writing the 1 that clears FCBEF and launches the complete command. Aborting a command in this way sets the FACCERR access error ﬂag which must be cleared before starting a new command.

A strictly monitored procedure must be adhered to, or the command will not be accepted. This minimizes the possibility of any unintended change to the FLASH memory contents. The command complete ﬂag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command. Figure 4-2 is a ﬂowchart for executing all of the commands except for burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

50 Freescale Semiconductor

Memory

WRITE TO FCDIV

FACCERR ?

CLEAR ERROR

WRITE TO FLASH

TO BUFFER ADDRESS AND DATA

WRITE COMMAND TO FCMD

WRITE 1 TO FCBEF

TO LAUNCH COMMAND

AND CLEAR FCBEF

FPVIOL OR FACCERR ?

(Note 1)

START

(Note 2)

Note 1: Required only once after reset.

Note 2: Wait at least four bus cycles

before checking FCBEF or FCCF.

YES

ERROR EXIT

FCCF ?

DONE

Figure 4-2. FLASH Program and Erase Flowchart

4.4.4 Burst Program Execution

The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the high voltage to the FLASH array does not need to be disabled between program operations. Ordinarily, when a program or erase command is issued, an internal charge pump associated with the FLASH memory must be enabled to supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if the following two conditions are met:

1. The next burst program command has been queued before the current program operation has completed.

2. The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero.

The ﬁrst byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst

MC9S08GT16A/GT8A Data Sheet, Rev. 1

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Memory

program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. This is because the high voltage to the array must be disabled and then enabled again. If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array.

WRITE TO FCDIV

FACCERR ?

CLEAR ERROR

FCBEF ?

WRITE TO FLASH

TO BUFFER ADDRESS AND DATA

WRITE COMMAND ($25) TO FCMD

WRITE 1 TO FCBEF

TO LAUNCH COMMAND

AND CLEAR FCBEF

(Note 1)

START

(Note 2)

Note 1: Required only once after reset.

Note 2: Wait at least four bus cycles before

checking FCBEF or FCCF.

FPVIO OR

FACCERR ?

YES

NEW BURST COMMAND ?

FCCF ?

DONE

YES

ERROR EXIT

Figure 4-3. FLASH Burst Program Flowchart

MC9S08GT16A/GT8A Data Sheet, Rev. 1

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Memory

4.4.5 Access Errors

An access error occurs whenever the command execution protocol is violated.

Any of the following speciﬁc actions will cause the access error ﬂag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.

• Writing to a FLASH address before the internal FLASH clock frequency has been set by writing to the FCDIV register

• Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the command buffer is empty.)

• Writing a second time to a FLASH address before launching the previous command (There is only one write to FLASH for every command.)

• Writing a second time to FCMD before launching the previous command (There is only one write to FCMD for every command.)

• Writing to any FLASH control register other than FCMD after writing to a FLASH address

• Writing any command code other than the ﬁve allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to FCMD

• Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear FCBEF and launch the command) after writing the command to FCMD

• The MCU enters stop mode while a program or erase command is in progress (The command is aborted.)

• Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with a background debug command while the MCU is secured (The background debug controller can only do blank check and mass erase commands when the MCU is secure.)

• Writing 0 to FCBEF to cancel a partial command

4.4.6 FLASH Block Protection

The block protection feature prevents the protected region of FLASH from program or erase changes. Block protection is controlled through the FLASH Protection Register (FPROT). When enabled, block protection begins at any 512 byte boundary and continues through 0xFFFF. (see Section 4.6.4, “FLASH

Protection Register (FPROT and NVPROT)”).

After exit from reset, FPROT is loaded with the contents of the NVPROT location which is in the nonvolatile register block of the FLASH memory. FPROT cannot be changed directly from application software so a runaway program cannot alter the block protection settings. Since NVPROT is within the last 512 bytes of FLASH, if any amount of memory is protected, NVPROT is itself protected and cannot be altered (intentionally or unintentionally) by the application software. FPROT can be written through background debug commands which allows a way to erase and reprogram a protected FLASH memory.

The block protection mechanism is illustrated below. The FPS bits are used as the upper bits of the last address of unprotected memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits as shown. For example, in order to protect the last 8192 bytes of memory (addresses 0xE000 through 0xFFFF), the FPS bits must be set to 1101 111 which results in the value 0xDFFF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 53

Memory

NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xDE must be programmed into NVPROT to protect addresses 0xE000 through 0xFFFF.

FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1

A15 A14 A13 A12 A11 A10 A9 A81A7 A6 A5 A4 A3 A2 A1 A0

Figure 4-4. Block Protection Mechanism

111

11111

One use for block protection is to block protect an area of FLASH memory for a bootloader program. This bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation.

4.4.7 Vector Redirection

Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at address 0xFFBF to zero. For redirection to occur, at least some portion but not all of the FLASH memory must be block protected by programming the NVPROT register located at address 0xFFBD. All of the interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, while the reset vector (0xFFFE:FFFF) is not.

For example, if 512 bytes of FLASH are protected, the protected address region is from 0xFE00 through 0xFFFF. The interrupt vectors (0xFFC0–0xFFFD) are redirected to the locations 0xFDC0–0xFDFD. Now, if an SPI interrupt is taken for instance, the values in the locations 0xFDE0:FDE1 are used for the vector instead of the values in the locations 0xFFE0:FFE1. This allows the user to reprogram the unprotected portion of the FLASH with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged.

4.5 Security

The MC9S08GT16A/GT8A includes circuitry to prevent unauthorized access to the contents of FLASH and RAM memory. When security is engaged, FLASH and RAM are considered secure resources. Direct-page registers, high-page registers, and the background debug controller are considered unsecured resources. Programs executing within secure memory have normal access to any MCU memory locations and resources. Attempts to access a secure memory location with a program executing from an unsecured memory space or through the background debug interface are blocked (writes are ignored and reads return all 0s).

Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into the working FOPT register in high-page register space. A user engages security by programming the NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state disengages security while the other three combinations engage security. Notice the erased state (1:1)

MC9S08GT16A/GT8A Data Sheet, Rev. 1

54 Freescale Semiconductor

Memory

makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain unsecured after a subsequent reset.

The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug controller can still be used for background memory access commands, but the MCU cannot enter active background mode except by holding BKGD/MS low at the rising edge of reset.

A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there is no way to disengage security without completely erasing all FLASH locations. If KEYEN is 1, a secure user program can temporarily disengage security by:

1. Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the ﬁrst step in a FLASH program or erase command.

2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations. These writes must be done in order, starting with the value for NVBACKKEY and ending with NVBACKKEY+7. STHX should not be used for these writes because these writes cannot be done on adjacent bus cycles. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O.

3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the key stored in the FLASH locations, SEC01:SEC00 are automatically changed to 1:0 and security will be disengaged until the next reset.

The security key can be written only from RAM, so it cannot be entered through background commands without the cooperation of a secure user program.

The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in FLASH memory locations in the nonvolatile register space so users can program these locations exactly as they would program any other FLASH memory location. The nonvolatile registers are in the same 512-byte block of FLASH as the reset and interrupt vectors, so block protecting that space also block protects the backdoor comparison key. Block protects cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key.

Security can always be disengaged through the background debug interface by performing these steps:

1. Disable any block protections by writing FPROT. FPROT can be written only with background debug commands, not from application software.

2. Mass erase FLASH, if necessary.

3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next reset.

To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0.

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Memory

4.6 Register Deﬁnition

The FLASH module has registers in the high-page register space, three locations in the nonvolatile register space in FLASH memory that are copied into three corresponding high-page control registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and Table 4-4 for the absolute address assignments for all FLASH registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header ﬁle normally is used to translate these names into the appropriate absolute addresses.

4.6.1 FLASH Clock Divider Register (FCDIV)

Bit 7 of this register is a read-only status ﬂag. Bits 6 through 0 may be read at any time but can be written only one time. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits.

76543210

R DIVLD

Reset 00000000

PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0

= Unimplemented or Reserved

Figure 4-5. FLASH Clock Divider Register (FCDIV)

Table 4-6. FCDIV Field Descriptions

Field Description

DIVLD

PRDIV8

DIV[5:0]

Divisor Loaded Status Flag — When set, this read-only status ﬂag indicates that the FCDIV register has been written since reset. Reset clears this bit and the ﬁrst write to this register causes this bit to become set regardless of the data written. 0 FCDIV has not been written since reset; erase and program operations disabled for FLASH. 1 FCDIV has been written since reset; erase and program operations enabled for FLASH.

Prescale (Divide) FLASH Clock by 8

0 Clock input to the FLASH clock divider is the bus rate clock. 1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.

Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 ﬁeld plus one. The resulting frequency of the internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5 µs to 6.7 µs. The automated programming logic uses an integer number of these pulses to complete an erase or program operation. See Equation 4-1 and Equation 4-2. Table 4-7 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.

if PRDIV8 = 0 — f

FCLK

= f

÷ ([DIV5:DIV0] + 1) Eqn. 4-1

Bus

if PRDIV8 = 1 — f

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56 Freescale Semiconductor

FCLK

= f

÷ (8 × ([DIV5:DIV0] + 1)) Eqn. 4-2

Bus

Table 4-7. FLASH Clock Divider Settings

Memory

Bus

20 MHz 1 12 192.3 kHz 5.2 µs

10 MHz 0 49 200 kHz 5 µs

8 MHz 0 39 200 kHz 5 µs

4 MHz 0 19 200 kHz 5 µs

2 MHz 0 9 200 kHz 5 µs

1 MHz 0 4 200 kHz 5 µs

200 kHz 0 0 200 kHz 5 µs

150 kHz 0 0 150 kHz 6.7 µs

PRDIV8

(Binary)

DIV5:DIV0

(Decimal)

FCLK

Program/Erase Timing Pulse

(5 µs Min, 6.7 µs Max)

4.6.2 FLASH Options Register (FOPT and NVOPT)

During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. Bits 5 through 2 are not used and always read 0. This register may be read at any time, but writes have no meaning or effect. To change the value in this register, erase and reprogram the NVOPT location in FLASH memory as usual and then issue a new MCU reset.

76543210

KEYEN FNORED

0000SEC01 SEC00

Reset This register is loaded from nonvolatile location NVOPT during reset.

= Unimplemented or Reserved

Figure 4-6. FLASH Options Register (FOPT)

Table 4-8. FOPT Field Descriptions

Field Description

KEYEN

Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to disengage security. The backdoor key mechanism is accessible only from user (secured) ﬁrmware. BDM commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed information about the backdoor key mechanism, refer to Section 4.5, “Security.” 0 No backdoor key access allowed. 1 If user ﬁrmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through

NVBACKKEY+7, in that order), security is temporarily disengaged until the next MCU reset.

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Table 4-8. FOPT Field Descriptions (continued)

Field Description

FNORED

1:0

SEC0[1:0]

Vector Redirection Disable — When this bit is 1, vector redirection is disabled. 0 Vector redirection enabled. 1 Vector redirection disabled.

Security State Code — This 2-bit ﬁeld determines the security state of the MCU as shown below. When the MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the background debug interface. For more detailed information about security, refer to Section 4.5, “Security.” 00 Secure 01 Secure 10 Unsecured 11 Secure SEC0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of FLASH.

4.6.3 FLASH Conﬁguration Register (FCNFG)

Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written.

76543210

R0 0

KEYACC

Reset 00000000

= Unimplemented or Reserved

00000

Figure 4-7. FLASH Conﬁguration Register (FCNFG)

Table 4-9. FCNFG Field Descriptions

Field Description

KEYACC

Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed information about the backdoor key mechanism, refer to Section 4.5, “Security.” 0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command. 1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.

Reads of the FLASH return invalid data.

4.6.4 FLASH Protection Register (FPROT and NVPROT)

During reset, the contents of the nonvolatile location NVPROT are copied from FLASH into FPROT. This register may be read at any time, but user program writes have no meaning or effect. Background debug commands can write to FPROT.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

58 Freescale Semiconductor

76543210

R FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS

W Note

(1)

Note

(1)

Note

(1)

Note

(1)

Note

(1)

Note

(1)

Reset This register is loaded from nonvolatile location NVPROT during reset.

Figure 4-8. FLASH Protection Register (FPROT)

Background commands can be used to change the contents of these bits in FPROT.

Table 4-10. FPROT Field Descriptions

Field Description

Note

(1)

Memory

Note

(1)

7:1

FPS[7:1]

FLASH Protect Select Bits — When FPDIS = 0, this 7-bit ﬁeld determines the ending address of unprotected FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or programmed.

FPDIS

FLASH Protection Disable

0 FLASH block speciﬁed by FPS2:FPS0 is block protected (program and erase not allowed). 1 No FLASH block is protected.

4.6.5 FLASH Status Register (FSTAT)

Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining ﬁve bits are status bits that can be read at any time. Writes to these bits have special meanings that are discussed in the bit descriptions.

76543210

FCBEF

Reset 11000000

FCCF

FPVIOL FACCERR

= Unimplemented or Reserved

Figure 4-9. FLASH Status Register (FSTAT)

0 FBLANK 0 0

Table 4-11. FSTAT Field Descriptions

Field Description

FCBEF

FCCF

Freescale Semiconductor 59

FLASH Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. Only burst program commands can be buffered. 0 Command buffer is full (not ready for additional commands). 1 A new burst program command may be written to the command buffer.

FLASH Command Complete Flag — FCCF is set automatically when the command buffer is empty and no command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a command). Writing to FCCF has no meaning or effect. 0 Command in progress 1 All commands complete

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Memory

Table 4-11. FSTAT Field Descriptions (continued)

Field Description

FPVIOL

FACCERR

FBLANK

Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL. 0 No protection violation. 1 An attempt was made to erase or program a protected location.

Access Error Flag — FACCERR is set automatically when the proper command sequence is not followed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of the exact actions that are considered access errors, see Section 4.4.5, “Access Errors.” FACCERR is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect. 0 No access error has occurred. 1 An access error has occurred.

FLASH Veriﬁed as All Blank (Erased) Flag — FBLANK is set automatically at the conclusion of a blank check command if the entire FLASH array was veriﬁed to be erased. FBLANK is cleared by clearing FCBEF to write a new valid command. Writing to FBLANK has no meaning or effect. 0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH array is not

completely erased.

1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is

completely erased (all 0xFF).

4.6.6 FLASH Command Register (FCMD)

Only ﬁve command codes are recognized in normal user modes as shown in Table 4-13. Refer to

Section 4.4.3, “Program and Erase Command Execution” for a detailed discussion of FLASH

programming and erase operations.

76543210

R00000000

W FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0

Reset 00000000

Figure 4-10. FLASH Command Register (FCMD)

Table 4-12. FCMD Field Descriptions

Field Description

7:0

FCMD[7:0]

FLASH Command Bits -- See Table 4-13 for a description of FCMD[7:0].

MC9S08GT16A/GT8A Data Sheet, Rev. 1

60 Freescale Semiconductor

Memory

Table 4-13. FLASH Commands

Command FCMD Equate File Label

Blank check 0x05 mBlank

Byte program 0x20 mByteProg

Byte program — burst mode 0x25 mBurstProg

Page erase (512 bytes/page) 0x40 mPageErase

Mass erase (all FLASH) 0x41 mMassErase

All other command codes are illegal and generate an access error.

It is not necessary to perform a blank check command after a mass erase operation. Blank check is required only as part of the security unlocking mechanism.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 61

Memory

MC9S08GT16A/GT8A Data Sheet, Rev. 1

62 Freescale Semiconductor

Chapter 5 Resets, Interrupts, and System Conﬁguration

5.1 Introduction

This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08GT16A/GT8A. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data manual. This section gathers basic information about all reset and interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral systems with their own sections but are part of the system control logic.

5.1.1 Features

Reset and interrupt features include:

• Multiple sources of reset for ﬂexible system conﬁguration and reliable operation: — Power-on detection (POR) — Low voltage detection (LVD) with enable — External — COP watchdog with enable and two timeout choices

RESET pin with enable

— Illegal opcode — Illegal address — Serial command from a background debug host

• Reset status register (SRS) to indicate source of most recent reset

• Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-1)

5.2 MCU Reset

Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially conﬁgured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the condition code register (CCR) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.

The MC9S08GT16A/GT8A has eight sources for reset:

• Power-on reset (POR)

• Low-voltage detect (LVD)

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 63

Resets, Interrupts, and System Conﬁguration

• Computer operating properly (COP) watchdog timer

• Illegal opcode detect

• Illegal address detect

• Background debug forced reset

• The reset pin (

RESET)

• Clock generator loss of lock and loss of clock reset

Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) module switches to self-clocked mode with the frequency of f

Self_reset

selected. The reset pin is driven low for 34 internal bus cycles where the internal bus frequency is half the ICG frequency. After the 34 cycles are completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset pin is the cause of the MCU reset.

5.3 Computer Operating Properly (COP) Watchdog

The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it times out, a system reset is generated to force the system back to a known starting point. The COP watchdog is enabled by the COPE bit in SOPT (see Section 5.7.4, “System Options Register (SOPT)” for additional information). The COP timer is reset by writing any value to the address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a reset signal to the COP timer.

After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE bit in the write-once SOPT register. Also, the COPT bit can be used to choose one of two timeout periods

or 213cycles of the bus rate clock). Even if the application will use the reset default settings in COPE

(2 and COPT, the user should still write to write-once SOPT during reset initialization to lock in the settings. That way, they cannot be changed accidentally if the application program gets lost.

The write to SRS that services (clears) the COP timer should not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails.

When the MCU is in active background mode, the COP timer is temporarily disabled.

5.4 Interrupts

Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such as an edge on the IRQ pin or a timer-overﬂow event. The debug module can also generate an SWI under certain circumstances.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

64 Freescale Semiconductor

Resets, Interrupts, and System Conﬁguration

If an event occurs in an enabled interrupt source, an associated read-only status ﬂag will become set. The CPU will not respond until and unless the local interrupt enable is set to 1 to enable the interrupt. The I bit in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset, which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.

When the CPU receives a qualiﬁed interrupt request, it completes the current instruction before responding to the interrupt. The interrupt sequence follows the same cycle-by-cycle sequence as the SWI instruction and consists of:

• Saving the CPU registers on the stack

• Setting the I bit in the CCR to mask further interrupts

• Fetching the interrupt vector for the highest-priority interrupt that is currently pending

• Filling the instruction queue with the ﬁrst three bytes of program information starting from the address fetched from the interrupt vector locations

While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit may be cleared inside an ISR (after clearing the status ﬂag that generated the interrupt) so that other interrupts can be serviced without waiting for the ﬁrst service routine to ﬁnish. This practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difﬁcult to debug.

The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the stack.

NOTE

For compatibility with the M68HC08, the H register is not automatically saved and restored. It is good programming practice to push H onto the stack at the start of the interrupt service routine (ISR) and restore it just before the RTI that is used to return from the ISR.

When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced ﬁrst (see Table 5-1).

5.4.1 Interrupt Stack Frame

Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer

(SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After stacking, the SP points at the next available location on the stack which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 65

Resets, Interrupts, and System Conﬁguration

UNSTACKING

ORDER

STACKING

ORDER

CONDITION CODE REGISTER

ACCUMULATOR

INDEX REGISTER (LOW BYTE X)

PROGRAM COUNTER HIGH

PROGRAM COUNTER LOW

* High byte (H) of index register is not automatically stacked.

TOWARD LOWER ADDRESSES

SP AFTER INTERRUPT STACKING

SP BEFORE THE INTERRUPT

TOWARD HIGHER ADDRESSES

Figure 5-1. Interrupt Stack Frame

When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of the RTI sequence, the CPU ﬁlls the instruction pipeline by reading three bytes of program information, starting from the PC address just recovered from the stack.

The status ﬂag causing the interrupt must be acknowledged (cleared) before returning from the ISR. Typically, the ﬂag should be cleared at the beginning of the ISR so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current ISR.

5.4.2 IRQ — External Interrupt Request Pin

External interrupts are managed by the IRQSC status and control register. When the IRQ function is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled) can wake the MCU.

5.4.2.1 Pin Conﬁguration Options

The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 for the IRQ pin to act as the interrupt request (IRQ) input. When the pin is conﬁgured as an IRQ input, the user can choose the polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event causes an interrupt or only sets the IRQF ﬂag (which can be polled by software).

When the IRQ pin is conﬁgured to detect rising edges, an optional pulldown resistor is available rather than a pullup resistor. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is conﬁgured to act as the IRQ input.

NOTE

The voltage measured on the pulled up IRQ pin may be as low as V

0.7 V. The internal gates connected to this pin are pulled all the way to V All other pins with enabled pullup resistors will have an unloaded measurement of V

–

MC9S08GT16A/GT8A Data Sheet, Rev. 1

66 Freescale Semiconductor

Resets, Interrupts, and System Conﬁguration

5.4.2.2 Edge and Level Sensitivity

The IRQMOD control bit re-conﬁgures the detection logic so it detects edge events and pin levels. In this edge detection mode, the IRQF status ﬂag becomes set when an edge is detected (when the IRQ pin changes from the deasserted to the asserted level), but the ﬂag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level.

5.4.3 Interrupt Vectors, Sources, and Local Masks

Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the

bottom of the table. The high-order byte of the address for the interrupt service routine is located at the ﬁrst address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address.

When an interrupt condition occurs, an associated ﬂag bit becomes set. If the associated local interrupt enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will ﬁnish the current instruction, stack the PCL, PCH, X, A, and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 67

Resets, Interrupts, and System Conﬁguration

Table 5-1. Vector Summary

Vector

Priority

Lower

Higher

Vector

Number

through

31 25 0xFFCC/FFCD Vrti System

24 0xFFCE/FFCF Viic IIC IICIS IICIE IIC control 23 0xFFD0/FFD1 Vatd ATD COCO AIEN AD conversion

22 0xFFD2/FFD3 Vkeyboard KBI KBF KBIE Keyboard pins 21 0xFFD4/FFD5 Vsci2tx SCI2 TDRE

20 0xFFD6/FFD7 Vsci2rx SCI2 IDLE

19 0xFFD8/FFD9 Vsci2err SCI2 OR

18 0xFFDA/FFDB Vsci1tx SCI1 TDRE

17 0xFFDC/FFDD Vsci1rx SCI1 IDLE

16 0xFFDE/FFDF Vsci1err SCI1 OR

15 0xFFE0/FFE1 Vspi SPI SPIF

14 0xFFE2/FFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overﬂow 11

through

13 10 0xFFEA/FFEB Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1

9 0xFFEC/FFED Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0 8 0xFFEE/FFEF Vtpm1ovf TPM1 TOF TOIE TPM1 overﬂow 7 0xFFF0/FFF1 Vtpm1ch2 TPM1 CH2F CH2IE TPM1 channel 2 6 0xFFF2/FFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1 5 0xFFF4/FFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0 4 0xFFF6/FFF7 Vicg ICG ICGIF

3 0xFFF8/FFF9 Vlvd System

2 0xFFFA/FFFB Virq IRQ IRQF IRQIE IRQ pin 1 0xFFFC/FFFD Vswi Core SWI

0 0xFFFE/FFFF Vreset System

Address

(High/Low)

0xFFC0/FFC1

through

0xFFCA/FFCB

0xFFEC/FFED

through

0xFFE4/FFE5

Vector Name Module Source Enable Description

Unused Vector Space

(available for user program)

RTIF RTIE Real-time interrupt

control

complete

control

TIE

RDRF

NF FE PF

RDRF

NF FE PF

MODF

SPTEF

Unused Vector Space

(available for user program)

(LOLS/LOCS)

LVDF LVDIE Low-voltage detect

Instruction

COP

LV D

RESET pin

Illegal opcode

TCIE

ILIE RIE

ORIE

NFIE FEIE PFIE

TIE

TCIE

ILIE RIE

ORIE

NFIE FEIE PFIE

SPIE SPIE

SPTIE

LOLRE/LOCRE ICG

— Software interrupt

COPE

LVDRE

— —

SCI2 transmit

SCI2 receive

SCI2 error

SCI1 transmit

SCI1 receive

SCI1 error

SPI

Watchdog timer

Low-voltage detect

External pin

Illegal opcode

MC9S08GT16A/GT8A Data Sheet, Rev. 1

68 Freescale Semiconductor

Resets, Interrupts, and System Conﬁguration

5.5 Low-Voltage Detect (LVD) System

The MC9S08GT16A/GT8A includes a system to protect against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system comprises a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (V or low (V

). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected

LVDL

by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless the LVDSE bit is set. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2, and the current consumption in stop3 with the LVD enabled will be greater.

5.5.1 Power-On Reset Operation

LVDH

)

When power is initially applied to the MCU, or when the supply voltage drops below the V

POR

level, the POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in reset until the supply has risen above the V

level. Both the POR bit and the LVD bit in SRS are set

LVDL

following a POR.

5.5.2 LVD Reset Operation

The LVD can be conﬁgured to generate a reset upon detection of a low voltage condition by setting LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following either an LVD reset or POR.

5.5.3 LVD Interrupt Operation

When a low voltage condition is detected and the LVD circuit is conﬁgured for interrupt operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur.

5.5.4 Low-Voltage Warning (LVW)

The LVD system has a low voltage warning ﬂag to indicate to the user that the supply voltage is approaching, but is still above, the LVD voltage. The LVW does not have an interrupt associated with it. There are two user selectable trip voltages for the LVW, one high (V voltage is selected by LVWV in SPMSC2.

) and one low (V

LVWH

LVWL

). The trip

5.6 Real-Time Interrupt (RTI)

The real-time interrupt function can be used to generate periodic interrupts based on a multiple of the source clock's period. The RTI has two source clock choices, the external clock input (ICGERCLK) to the ICG or the RTI's own internal clock. The RTI can be used in run, wait, stop2 and stop3 modes. It is not available in stop1 mode.

In run and wait modes, only the external clock can be used as the RTI's clock source. In stop2 mode, only the internal RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 69

Resets, Interrupts, and System Conﬁguration

When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and conﬁgured for low bandwidth operation (RANGE = 0).

The SRTISC register includes a read-only status ﬂag, a write-only acknowledge bit, and a 3-bit control value (RTIS2:RTIS1:RTIS0) used to select one of seven RTI periods. The RTI has a local interrupt enable, RTIE, to allow masking of the real-time interrupt. The module can be disabled by writing 0:0:0 to RTIS2:RTIS1:RTIS0 in which case the clock source input is disabled and no interrupts will be generated. See Section 5.7.6, “System Real-Time Interrupt Status and Control Register (SRTISC),” for detailed information about this register.

5.7 Register Deﬁnition

One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems.

Refer to the direct-page register summary in Chapter 4, “Memory” of this data sheet for the absolute address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header ﬁle is used to translate these names into the appropriate absolute addresses.

Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in

Chapter 3, “Modes of Operation.”

MC9S08GT16A/GT8A Data Sheet, Rev. 1

70 Freescale Semiconductor

Resets, Interrupts, and System Conﬁguration

5.7.1 Interrupt Pin Request Status and Control Register (IRQSC)

This direct page register includes two unimplemented bits which always read 0, four read/write bits, one read-only status bit, and one write-only bit. These bits are used to conﬁgure the IRQ function, report status, and acknowledge IRQ events.

76543210

R0 0

IRQEDG IRQPE

W IRQACK

Reset 00000000

= Unimplemented or Reserved

Figure 5-2. Interrupt Request Status and Control Register (IRQSC)

Table 5-2. IRQSC Field Descriptions

Field Description

IRQF 0

IRQIE IRQMOD

IRQEDG

IRQPE

IRQF

IRQACK

IRQIE

IRQMOD

Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is conﬁgured to detect rising edges, the optional pullup resistor is re-conﬁgured as an optional pulldown resistor. 0 IRQ is falling edge or falling edge/low-level sensitive. 1 IRQ is rising edge or rising edge/high-level sensitive.

IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down resistor is enabled depending on the state of the IRQMOD bit. 0 IRQ pin function is disabled. 1 IRQ pin function is enabled.

IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred. 0 No IRQ request. 1 IRQ event detected.

IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF). Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.

IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate a hardware interrupt request. 0 Hardware interrupt requests from IRQF disabled (use polling). 1 Hardware interrupt requested whenever IRQF = 1.

IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See Section 5.4.2.2, “Edge and Level Sensitivity” for more details. 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 71

Resets, Interrupts, and System Conﬁguration

5.7.2 System Reset Status Register (SRS)

This register includes six read-only status ﬂags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset.

76543210

POR PIN COP ILOP

W Writing any value to SIMRS address clears COP watchdog timer.

ILAD ICG LVD 0

Power-on

reset:

Low-voltage

reset:

Any other

reset:

Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset will be cleared.

10000010

U0000010

0 Note

U = Unaffected by reset

(1)

Note

(1)

Note

(1)

0 Note

(1)

Figure 5-3. System Reset Status (SRS)

Table 5-3. SRS Field Descriptions

Field Description

POR

Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 Reset not caused by POR. 1 POR caused reset.

External Reset Pin — Reset was caused by an active-low level on the external reset pin. 0 Reset not caused by external reset pin. 1 Reset came from external reset pin.

COP

ILOP

72 Freescale Semiconductor

Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out. This reset source may be blocked by COPE = 0. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout.

Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Table 5-3. SRS Field Descriptions (continued)

Field Description

Resets, Interrupts, and System Conﬁguration

ILAD

ICG

LV D

Illegal Address — Reset was caused by an attempt to access a designated illegal address. 0 Reset not caused by an illegal address access. 1 Reset caused by an illegal address access.

Illegal address areas in the MC9S08GT16A are:

• 0x0880 - 0x17FF — Gap from end of RAM to start of high page registers

• 0x182C - 0xBFFF — Gap from end of high page registers to start of Flash memory

Unused and reserved locations in register areas are not considered designated illegaladdresses and do not triggerillegal address resets.

Internal Clock Generation Module Reset — Reset was caused by an ICG module reset. 0 Reset not caused by ICG module. 1 Reset caused by ICG module.

Low Voltage Detect — If the LVD reset is enabled (LVDE = LVDRE = 1) and the supply drops below the LVD trip voltage, an LVD reset occurs. The LVD function is disabled when the MCU enters stop. To maintain LVD operation in stop, the LVDSE bit must be set. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR.

5.7.3 System Background Debug Force Reset Register (SBDFR)

This register contains a single write-only control bit. A serial background command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00.

76543210

R00000000

W BDFR

Reset 00000000

= Unimplemented or Reserved

BDFR is writable only through serial background debug commands, not from user programs.

Note

(1)

Figure 5-4. System Background Debug Force Reset Register (SBDFR)

Table 5-4. SBDFR Field Descriptions

Field Description

BDFR

Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 73

Resets, Interrupts, and System Conﬁguration

5.7.4 System Options Register (SOPT)

This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a write-once register so only the ﬁrst write after reset is honored. Any subsequent attempt to write to SOPT (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT should be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.

76543210

COPE COPT STOPE

Reset 11010011

= Unimplemented or Reserved

Figure 5-5. System Options Register (SOPT)

Table 5-5. SOPT Field Descriptions

Field Description

BKGDPE

COPE

COPT

STOPE

BKGDPE

COP Watchdog Enable — This write-once bit defaults to 1 after reset. 0 COP watchdog timer disabled. 1 COP watchdog timer enabled (force reset on timeout).

COP Watchdog Timeout — This write-once bit defaults to 1 after reset. 0 Short timeout period selected (2 1 Long timeout period selected (2

Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled. 1 Stop mode enabled.

Background Debug Mode Pin Enable — The BKGDPE bit enables the PTG0/BKGD/MS pin to function as BKGD/MS. When the bit is clear, the pin will function as PTG0, which is an output-only general-purpose I/O. This pin always defaults to BKGD/MS function after any reset. 0 BKGD pin disabled. 1 BKGD pin enabled.

cycles of BUSCLK).

MC9S08GT16A/GT8A Data Sheet, Rev. 1

74 Freescale Semiconductor

Resets, Interrupts, and System Conﬁguration

5.7.5 System Device Identiﬁcation Register (SDIDH, SDIDL)

This read-only register is included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where speciﬁc memory blocks, registers, and control bits are located in a target MCU.

76543210

R ID11 ID10 ID9 ID8

Reset 00000000

= Unimplemented or Reserved

Figure 5-6. System Device Identiﬁcation Register High (SDIDH)

Table 5-6. SDIDH Field Descriptions

Field Description

3:0

ID[11:8]

R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

Reset 00001101

Part Identiﬁcation Number — Each derivative in the HCS08 Family has a unique identiﬁcation number. The MC9S08GT16A/GT8A is hard coded to the value 0x00D. See also ID bits in Table 5-7.

76543210

= Unimplemented or Reserved

Figure 5-7. System Device Identiﬁcation Register Low (SDIDL)

Table 5-7. SDIDL Field Descriptions

Field Description

7:0

ID[7:0]

Part Identiﬁcation Number — Each derivative in the HCS08 Family has a unique identiﬁcation number. The MC9S08GT16A/GT8A is hard coded to the value 0x00D. See also ID bits in Table 5-6.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 75

Resets, Interrupts, and System Conﬁguration

5.7.6 System Real-Time Interrupt Status and Control Register (SRTISC)

This register contains one read-only status ﬂag, one write-only acknowledge bit, three read/write delay selects, and three unimplemented bits, which always read 0.

76543210

RTIF

RTICLKS RTIE

RTIACK

Reset 00000000

= Unimplemented or Reserved

Figure 5-8. System RTI Status and Control Register (SRTISC)

Table 5-8. SRTISC Field Descriptions

Field Description

RTIS2 RTIS1 RTIS0

RTIF

Real-Time Interrupt Flag — This read-only status bit indicates the periodic wakeup timer has timed out. 0 Periodic wakeup timer not timed out. 1 Periodic wakeup timer timed out.

RTIACK

RTICLKS

Real-Time Interrupt Acknowledge — This write-only bit is used to acknowledge real-time interrupt request (write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0.

Real-Time Interrupt Clock Select — This read/write bit selects the clock source for the real-time interrupt. 0 Real-time interrupt request clock source is internal oscillator. 1 Real-time interrupt request clock source is external clock.

RTIE

Real-Time Interrupt Enable — This read-write bit enables real-time interrupts. 0 Real-time interrupts disabled. 1 Real-time interrupts enabled.

2:0

RTIS[2:0]

Real-Time Interrupt Period Selects — These read/write bits select the wakeup period for the RTI. One clock source for the real-time interrupt is its own internal clock source, which oscillates with a period of approximately t

and is independent of other MCU clock sources. Using an external clock source the delays will be crystal

RTI

frequency divided by value in RTIS2:RTIS1:RTIS0. See Table 5-9.

Table 5-9. Real-Time Interrupt Period

RTIS2:RTIS1:RTIS0

Internal Clock Source

= 1.15 ms, Nominal)

RTI

0:0:0 9.2 ms Disable periodic wakeup timer

0:0:1 18.4 ms

0:1:0 36.8 ms

0:1:1 73.6 ms

1:0:0 147.2 ms

1:0:1 294.4 ms

1:1:0 588.8 ms

1:1:1 1177.6 ms

See Table A-12 t

is based on the external clock source, resonator, or crystal selected by the ICG conﬁguration. See Table A-11 for details.

ext

in Appendix A, “Electrical Characteristics,” for the tolerance on these values.

RTI

External Clock Source

Period = t

ext

x 256

x 1024

x 2048

x 4096

x 8192

x 16384

x 32768

MC9S08GT16A/GT8A Data Sheet, Rev. 1

76 Freescale Semiconductor

Resets, Interrupts, and System Conﬁguration

5.7.7 System Power Management Status and Control 1 Register (SPMSC1)

76543210

R LVDF 0

W LVD AC K

LVDIE

LVDRE

Note

(1)

LVDSE

Note

(1)

LVDE

Note

(1)

Reset 00011100

= Unimplemented or Reserved

This bit can be written only one time after reset. Additional writes are ignored.

Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)

Table 5-10. SPMSC1 Field Descriptions

Field Description

LVDF

LV DAC K

LVDIE

LVDRE

LVDSE

LVDE

Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.

Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors

(write 1 to clear LVDF). Reads always return 0.

Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF. 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVDF = 1.

Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset (provided LVDE = 1). 0 LVDF does not generate hardware resets. 1 Force an MCU reset when LVDF = 1.

Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode.

Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualiﬁes the operation of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 77

Resets, Interrupts, and System Conﬁguration

5.7.8 System Power Management Status and Control 2 Register (SPMSC2)

This register is used to report the status of the low voltage warning function, and to conﬁgure the stop mode behavior of the MCU.

76543210

LVWF

LV DV LV WV

LV WACK PPDACK

PPDF

PDC PPDC

Power-on

reset:0Note

LVD reset: 0

Any other

reset:0Note

LVWF will be set in the case when V

Note

(1)

Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)

Field Description

LVWF

LV WACK

LV DV

LVWV

PPDF

Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status. 0 Low voltage warning not present. 1 Low voltage warning is present or was present.

Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge. Writing a 1 to LVWACK clears LVWF to 0 if a low voltage warning is not present.

Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V 0 Low trip point selected (V 1 High trip point selected (V

Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V 0 Low trip point selected (V 1 High trip point selected (V

Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode. 0 Not stop2 mode recovery. 1 Stop2 mode recovery.

0000000

0UU0000

= Unimplemented or Reserved U = Unaffected by reset

transitions below the trip point or after reset and V

Supply

is already below V

Supply

LV W

Table 5-11. SPMSC2 Field Descriptions

LV D

LV W

LV D

LV W

= V

LVDL

LVDH

LVWL

LVWH

Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.

PPDACK

PDC

Power Down Control — The write-once PDC bit controls entry into the power down (stop2 and stop1) modes. 0 Power down modes are disabled. 1 Power down modes are enabled.

PPDC

Partial Power Down Control — The write-once PPDC bit controls which power down mode, stop1 or stop2, is selected. 0 Stop1, full power down, mode enabled if PDC set. 1 Stop2, partial power down, mode enabled if PDC set.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

78 Freescale Semiconductor

Chapter 6 Parallel Input/Output

6.1 Introduction

This section explains software controls related to parallel input/output (I/O). The MC9S08GT16A/GT8A has six I/O ports which include a total of up to 39 general-purpose I/O pins (one pin, PTG0, is output only). See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins.

Many of these pins are shared with on-chip peripherals such as timer systems, external interrupts, or keyboard interrupts. When these other modules are not controlling the port pins, they revert to general-purpose I/O control. For each I/O pin, a port data bit provides access to input (read) and output (write) data, a data direction bit controls the direction of the pin, and a pullup enable bit enables an internal pullup device (provided the pin is conﬁgured as an input), and a slew rate control bit controls the rise and fall times of the pins.

Pins that are not used in the application must be terminated. This prevents excess current caused by ﬂoating inputs and enhances immunity during noise or transient events. Termination methods include:

• Conﬁguring unused pins as outputs driving high or low

• Conﬁguring unused pins as inputs and using internal or external pullups

Never connect unused pins to V

Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from ﬂoating input pins, the user’s reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not ﬂoat.

or VSS.

NOTE

6.1.1 Features

Parallel I/O features, depending on package choice, include:

• A total of 39 general-purpose I/O pins in six ports (PTG0 is output only)

• High-current drivers on port C pins

• Hysteresis input buffers

• Software-controlled pullups on each input pin

• Software-controlled slew rate output buffers

• Eight port A pins shared with KBI

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 79

Parallel Input/Output

• Eight port B pins shared with ATD

• Eight high-current port C pins shared with SCI2 and IIC

• Five port D pins shared with TPM1 and TPM2

• Six port E pins shared with SCI1 and SPI

• Four port G pins shared with EXTAL, XTAL, and BKGD/MS

MC9S08GT16A/GT8A Data Sheet, Rev. 1

80 Freescale Semiconductor

6.1.2 Block Diagram

HCS08 CORE

RESET

NOTE 4

IRQ

NOTES 2, 3

CPU

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

RTI

IRQ LVD

BDC

COP

BKGD

REFL

REFH

SSAD

DDAD

8-BIT KEYBOARD INTERRUPT (KBI)

ANALOG-TO-DIGITAL

CONVERTER (ATD)

INTER-IC (IIC)

SERIAL COMMUNICATIONS

INTERFACE (SCI2)

10-BIT

SCL SDA

RXD2

TXD2

PORT A

PORT B

PORT C

Parallel Input/Output

PTA7/KBIP7– PTA4/KBIP4

PTA3/KBIP3– PTA0/KBIP0

PTB7/ADP7– PTB4/ADP4

PTB3/ADP3– PTB0/ADP0

PTC7 PTC6 PTC5 PTC4 PTC3/SCL PTC2/SDA

PTC1/RxD2 PTC0/TxD2

NOTE 6

NOTE 5

USER FLASH

(GT16A = 16,384 BYTES)

(GT8A = 8192 BYTES)

USER RAM

(GT16A = 2048 BYTES)

(GT8A = 1024 BYTES)

ON-CHIP ICE

DEBUG

MODULE (DBG)

INTERNAL CLOCK

GENERATOR (ICG)

LOW-POWER OSCILLATOR

VOLTAGE

REGULATOR

2-CHANNEL TIMER/PWM

(TPM2)

3-CHANNEL TIMER/PWM

(TPM1)

SERIAL PERIPHERAL

INTERFACE (SPI)

SERIAL COMMUNICATIONS

INTERFACE (SCI1)

EXTAL

XTAL

BKGD

= Pins not available in 44-, 42-, or 32-pin packages = Pins not available in 42- or 32-pin packages = Pins not available in 32-pin packages

CH1 CH0

CH0

CH1 CH2

SPSCK

MOSI MISO

RXD1

TXD1

PORT D

PORT E

PORT G

PTD4/TPM2CH1 PTD3/TPM2CLK/TPM2CH0

PTD2/TPM1CH2 PTD1/TPM1CH1 PTD0/TPM1CLK/TPM1CH0

PTE5/SPSCK PTE4/MOSI PTE3/MISO PTE2/SS

PTE1/RxD1 PTE0/TxD1

PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS

NOTES:

1. Port pins are software configurable with pullup device if input port.

2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).

3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.

4. Pin contains integrated pullup device.

5. High current drive

6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).

Figure 6-1. Block Diagram Highlighting Parallel Input/Output Pins

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 81

Parallel Input/Output

6.2 External Signal Description

The MC9S08GT16A/GT8A has a total of 39 parallel I/O pins (one is output only) in six 8-bit ports (PTA–PTE, PTG). Not all pins are bonded out in all packages. Consult the pin assignment in Chapter 2,

“Pins and Connections,” for available parallel I/O pins. All of these pins are available for general-purpose

I/O when they are not used by other on-chip peripheral systems.

After reset, BKGD/MS is enabled and therefore is not usable as an output pin until BKGDPE in SOPT is cleared. The rest of the peripheral functions are disabled. After reset, all data direction and pullup enable controls are set to 0s. These pins default to being high-impedance inputs with on-chip pullup devices disabled.

The following paragraphs discuss each port and the software controls that determine each pin’s use.

6.2.1 Port A and Keyboard Interrupts

Port A Bit 7 654321Bit 0

MCU Pin:

PTA7/

KBIP7

PTA6/

KBIP6

Figure 6-2. Port A Pin Names

PTA5/

KBIP5

PTA4/

KBIP4

PTA3/

KBIP3

PTA2/

KBIP2

PTA1/

KBIP1

PTA0/

KBIP0

Port A is an 8-bit port shared among the KBI keyboard interrupt inputs and general-purpose I/O. Any pins enabled as KBI inputs will be forced to act as inputs.

Port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction (PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers. Refer to Section 6.3, “Parallel

I/O Controls,” for more information about general-purpose I/O control.

Port A can be conﬁgured to be keyboard interrupt input pins. Refer to Chapter 7, “Keyboard Interrupt

(S08KBIV1),” for more information about using port A pins as keyboard interrupts pins.

6.2.2 Port B and Analog to Digital Converter Inputs

Port B Bit 7 654321Bit 0

MCU Pin:

PTB7/

ADP7

Port B is an 8-bit port shared among the ATD inputs and general-purpose I/O. Any pin enabled as an ATD input will be forced to act as an input.

PTB6/

ADP6

Figure 6-3. Port B Pin Names

PTB5/ ADP5

PTB4/

ADP4

PTB3/

ADP3

PTB2/

ADP2

PTB1/

ADP1

PTB0/

ADP0

Port B pins are available as general-purpose I/O pins controlled by the port B data (PTBD), data direction (PTBDD), pullup enable (PTBPE), and slew rate control (PTBSE) registers. Refer to Section 6.3, “Parallel

I/O Controls,” for more information about general-purpose I/O control.

When the ATD module is enabled, analog pin enables are used to specify which pins on port B will be used as ATD inputs. Refer to Chapter 14, “Analog-to-Digital Converter (S08ATDV3),” for more information about using port B pins as ATD pins.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

82 Freescale Semiconductor

Parallel Input/Output

6.2.3 Port C and SCI2, IIC, and High-Current Drivers

Port C Bit 7 6 5 3321Bit 0

MCU Pin:

PTC7 PTC6 PTC5 PTC4 PTC3/

SCL

Figure 6-4. Port C Pin Names

PTC2/

SDA

PTC1/

RxD2

PTC0/

TxD2

Port C is an 8-bit port which is shared among the SCI2 and IIC modules, and general-purpose I/O. When SCI2 or IIC modules are enabled, the pin direction will be controlled by the module or function. Port C has high current output drivers.

Port C pins are available as general-purpose I/O pins controlled by the port C data (PTCD), data direction (PTCDD), pullup enable (PTCPE), and slew rate control (PTCSE) registers. Refer to Section 6.3, “Parallel

I/O Controls,” for more information about general-purpose I/O control.

When the SCI2 module is enabled, PTC0 serves as the SCI2 module’s transmit pin (TxD2) and PTC1 serves as the receive pin (RxD2). Refer to Chapter 11, “Serial Communications Interface (S08SCIV1),” for more information about using PTC0 and PTC1 as SCI pins

When the IIC module is enabled, PTC2 serves as the IIC modules’s serial data input/output pin (SDA) and PTC3 serves as the clock pin (SCL). Refer to Chapter 13, “Inter-Integrated Circuit (S08IICV1),” for more information about using PTC2 and PTC3 as IIC pins.

6.2.4 Port D, TPM1 and TPM2

Port D Bit 7 654321Bit 0

MCU Pin:

0 0 0 PTD4/

TPM2CH1

Figure 6-5. Port D Pin Names

PTD3/

TPM2CLK/

TPM2CH0

PTD2/

TPM1CH2

PTD1/

TPM1CH1

PTD0/

TPM1CLK/

TPM1CH0

Port D is an 5-bit port shared with the two TPM modules, TPM1 and TPM2, and general-purpose I/O. When the TPM1 or TPM2 modules are enabled in output compare or input capture modes of operation, the pin direction will be controlled by the module function.

Port D pins are available as general-purpose I/O pins controlled by the port D data (PTDD), data direction (PTDDD), pullup enable (PTDPE), and slew rate control (PTDSE) registers. Refer to Section 6.3, “Parallel

I/O Controls,” for more information about general-purpose I/O control.

The TPM2 module can be conﬁgured to use PTD4–PTD3 as either input capture, output compare, PWM, or external clock input pins (PTD3 only). Refer to Chapter 10, “Timer/PWM (S08TPMV2),” for more information about using PTD4–PTD3 as timer pins.

The TPM1 module can be conﬁgured to use PTD2–PTD0 as either input capture, output compare, PWM, or external clock input pins (PTD0 only). Refer to Chapter 10, “Timer/PWM (S08TPMV2),” for more information about using PTD2–PTD0 as timer pins.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 83

Parallel Input/Output

6.2.5 Port E, SCI1, and SPI

Port E Bit 7 6 5 4 3 2 1 Bit 0

MCU Pin:

0 0 PTE5/

SPSCK

Figure 6-6. Port E Pin Names

PTE4/

MOSI

PTE3/

MISO

PTE2/SSPTE1/

RxD1

PTE0/

TxD1

Port E is an 6-bit port shared with the SCI1 module, SPI1 module, and general-purpose I/O. When the SCI or SPI modules are enabled, the pin direction will be controlled by the module function.

Port E pins are available as general-purpose I/O pins controlled by the port E data (PTED), data direction (PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. Refer to Section 6.3, “Parallel

I/O Controls” for more information about general-purpose I/O control.

When the SCI1 module is enabled, PTE0 serves as the SCI1 module’s transmit pin (TxD1) and PTE1 serves as the receive pin (RxD1). Refer to Chapter 11, “Serial Communications Interface (S08SCIV1)” for more information about using PTE0 and PTE1 as SCI pins.

When the SPI module is enabled, PTE2 serves as the SPI module’s slave select pin (

SS1), PTE3 serves as the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5 serves as the SPI clock pin (SPSCK1). Refer to Chapter 12, “Serial Peripheral Interface (S08SPIV3) for more information about using PTE5–PTE2 as SPI pins.

6.2.6 Port G, BKGD/MS, and Oscillator

Port G Bit 7 6 5 4 3 2 1 Bit 0

MCU Pin:

0 0 0 0 PTG3 PTG2/

EXTAL

Figure 6-7. Port G Pin Names

PTG1/

XTAL

PTG0/

BKGD/MS

Port G is an 4-bit port which is shared among the background/mode select function, oscillator, and general-purpose I/O. When the background/mode select function or oscillator is enabled, the pin direction will be controlled by the module function.

Port G pins are available as general-purpose I/O pins controlled by the port G data (PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers. Refer to Section 6.3, “Parallel

I/O Controls,” for more information about general-purpose I/O control.

The internal pullup for PTG0 is enabled when the background/mode select function is enabled, regardless of the state of PTGPE0. During reset, the BKGD/MS pin functions as a mode select pin. After the MCU

exits reset, the BKGD/MS pin becomes the background communications input/output pin. The PTG0 can

be conﬁgured to be a general-purpose output pin. Refer to Section 5.7.4, “System Options Register

(SOPT),” for selecting BKGD or PTG0. Refer to Chapter 3, “Modes of Operation,”, Chapter 5, “Resets, Interrupts, and System Conﬁguration,” and Chapter 15, “Development Support,” for more information

about using this pin.

The ICG module can be conﬁgured to use PTG2–PTG1 ports as crystal oscillator or external clock pins.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

84 Freescale Semiconductor

Parallel Input/Output

Refer to Chapter 9, “Internal Clock Generator (S08ICGV4),” for more information about using these pins as oscillator pins.

6.3 Parallel I/O Controls

Provided no on-chip peripheral is controlling a port pin, the pins operate as general-purpose I/O pins that are accessed and controlled by a data register (PTxD), a data direction register (PTxDD), a pullup enable register (PTxPE), and a slew rate control register (PTxSE) where x is A, B, C, D, E, or G.

Reads of the data register return the pin value (if PTxDDn = 0) or the contents of the port data register (if PTxDDn = 1). Writes to the port data register are latched into the port register whether the pin is controlled by an on-chip peripheral or the pin is conﬁgured as an input. If the corresponding pin is not controlled by a peripheral and is conﬁgured as an output, this level will be driven out the port pin.

6.3.1 Data Direction Control

The data direction control bits determine whether the pin output driver is enabled, and they control what is read for port data register reads. Each port pin has a data direction control bit. When PTxDDn = 0, the corresponding pin is an input and reads of PTxD return the pin value. When PTxDDn = 1, the corresponding pin is an output and reads of PTxD return the last value written to the port data register. When a peripheral module or system function is in control of a port pin, the data direction control still controls what is returned for reads of the port data register, even though the peripheral system has overriding control of the actual pin direction.

For the MC9S08GT16A/GT8A MCU, reads of PTG0/BKGD/MS will return the value on the output pin.

It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register.

6.3.2 Internal Pullup Control

An internal pullup device can be enabled for each port pin that is conﬁgured as an input (PTxDDn = 0). The pullup device is available for a peripheral module to use, provided the peripheral is enabled and is an input function as long as the PTxDDn = 0.

For the four conﬁgurable KBI module inputs on PTA7–PTA4, when a pin is conﬁgured to detect rising edges, the port pullup enable associated with the pin (PTAPEn) selects a pulldown rather than a pullup device.

6.3.3 Slew Rate Control

Slew rate control can be enabled for each port pin that is conﬁgured as an output (PTxDDn = 1) or if a peripheral module is enabled and its function is an output. Not all peripheral modules’ outputs have slew rate control; refer to Chapter 2, “Pins and Connections,” for more information about which pins have slew rate control.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 85

Parallel Input/Output

6.4 Stop Modes

Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An explanation of I/O behavior for the various stop modes follows:

• When the MCU enters stop1 mode, all internal registers including general-purpose I/O control and data registers are powered down. All of the general-purpose I/O pins assume their reset state: output buffers and pullups turned off. Upon exit from stop1, all I/O must be initialized as if the MCU had been reset.

• When the MCU enters stop2 mode, the internal registers are powered down as in stop1 but the I/O pin states are latched and held. For example, a port pin that is an output driving low continues to function as an output driving low even though its associated data direction and output data registers are powered down internally. Upon exit from stop2, the pins continue to hold their states until a 1 is written to the PPDACK bit. To avoid discontinuity in the pin state following exit from stop2, the user must restore the port control and data registers to the values they held before entering stop2. These values can be stored in RAM before entering stop2 because the RAM is maintained during stop2.

• In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user.

6.5 Register Deﬁnition

This section provides information about all registers and control bits associated with the parallel I/O ports.

Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header ﬁle normally is used to translate these names into the appropriate absolute addresses.

6.5.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD)

Port A includes eight pins shared between general-purpose I/O and the KBI module. Port A pins used as general-purpose I/O pins are controlled by the port A data (PTAD), data direction (PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers.

If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of PTAD will return the logic value of the corresponding pin, provided PTADD is 0.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

86 Freescale Semiconductor

Parallel Input/Output

76543210

PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0

Reset 00000000

Figure 6-8. Port A Data Register (PTAD)

Table 6-1. PTAD Field Descriptions

Field Description

7:0

PTAD[7:0]

Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are conﬁgured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are conﬁgured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also conﬁgures all port pins as high-impedance inputs with pullups disabled.

76543210

PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0

Reset 00000000

Figure 6-9. Pullup Enable for Port A (PTAPE)

Table 6-2. PTAPE Field Descriptions

Field Description

7:0

PTAPE[7:0]

Pullup Enable for Port A Bits — For port A pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled provided the corresponding PTADDn is 0. For port A pins that are conﬁgured as outputs, these bits are ignored and the internal pullup devices are disabled. When any of bits 7 through 4 of port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices. 0 Internal pullup device disabled. 1 Internal pullup device enabled.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 87

Parallel Input/Output

76543210

PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0

Reset 00000000

Figure 6-10. Slew Rate Control Enable for Port A (PTASE)

Table 6-3. PTASE Field Descriptions

Field Description

7:0

PTASE[7:0]

Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. For port A pins that are conﬁgured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled.

76543210

PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0

Reset 00000000

Figure 6-11. Data Direction for Port A (PTADD)

Table 6-4. PTADD Field Descriptions

Field Description

7:0

PTADD[7:0]

Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

88 Freescale Semiconductor

Parallel Input/Output

6.5.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD)

Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as general-purpose I/O pins are controlled by the port B data (PTBD), data direction (PTBDD), pullup enable (PTBPE), and slew rate control (PTBSE) registers.

If the ATD takes control of a port B pin, the corresponding PTBDD, PTBSE, and PTBPE bits are ignored. When a port B pin is being used as an ATD pin, reads of PTBD will return a 0 of the corresponding pin, provided PTBDD is 0.

76543210

PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0

Reset 00000000

Figure 6-12. Port B Data Register (PTBD)

Table 6-5. PTBD Field Descriptions

Field Description

7:0

PTBD[7:0]

Reset 00000000

Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B pins that are conﬁgured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port B pins that are conﬁgured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also conﬁgures all port pins as high-impedance inputs with pullups disabled.

76543210

PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0

Figure 6-13. Pullup Enable for Port B (PTBPE)

Table 6-6. PTBPE Field Descriptions

Field Description

7:0

PTBPE[7:0]

Pullup Enable for Port B Bits — For port B pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. For port B pins that are conﬁgured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 89

Parallel Input/Output

76543210

PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0

Reset 00000000

Figure 6-14. Data Direction for Port A (PTBSE)

Table 6-7. PTBSE Field Descriptions

Field Description

7:0

PTBSE[7:0]

Slew Rate Control Enable for Port B Bits — For port B pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. For port B pins that are conﬁgured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled.

76543210

PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0

Reset 00000000

Figure 6-15. Data Direction for Port B (PTBDD)

Table 6-8. PTBDD Field Descriptions

Field Description

7:0

PTBDD[7:0]

Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

90 Freescale Semiconductor

Parallel Input/Output

6.5.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD)

Port C includes eight general-purpose I/O pins that share with the SCI2 and IIC modules. Port C pins used as general-purpose I/O pins are controlled by the port C data (PTCD), data direction (PTCDD), pullup enable (PTCPE), and slew rate control (PTCSE) registers.

If the SCI2 takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to provide slew rate on the SCI2 transmit pin, TxD2. PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the SCI2 receive pin, RxD2.

If the IIC takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to provide slew rate on the IIC serial data pin (SDA), when in output mode and the IIC clock pin (SCL). PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the IIC serial data pin, when in receive mode.

Reads of PTCD will return the logic value of the corresponding pin, provided PTCDD is 0.

76543210

PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0

Reset 00000000

Figure 6-16. Port C Data Register (PTCD)

Table 6-9. PTCD Field Descriptions

Field Description

7:0

PTCD[7:0]

Port C Data Register Bits— For port C pins that are inputs, reads return the logic level on the pin. For port C pins that are conﬁgured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port C pins that are conﬁgured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also conﬁgures all port pins as high-impedance inputs with pullups disabled.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 91

Parallel Input/Output

76543210

PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0

Reset 00000000

Figure 6-17. Pullup Enable for Port C (PTCPE)

Table 6-10. PTCPE Field Descriptions

Field Description

7:0

PTCPE[7:0]

Pullup Enable for Port C Bits — For port C pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. For port C pins that are conﬁgured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled.

76543210

PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0

Reset 00000000

Figure 6-18. Slew Rate Control Enable for Port C (PTCSE)

Table 6-11. PTCSE Field Descriptions

Field Description

7:0

PTCSE[7:0]

Slew Rate Control Enable for Port C Bits — For port C pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. For port B pins that are conﬁgured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled.

76543210

PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0

Reset 00000000

Figure 6-19. Data Direction for Port C (PTCDD)

Table 6-12. PTCDD Field Descriptions

Field Description

7:0

PTCDD[7:0]

92 Freescale Semiconductor

Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Parallel Input/Output

6.5.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD)

Port D includes ﬁve pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as general-purpose I/O pins are controlled by the port D data (PTDD), data direction (PTDDD), pullup enable (PTDPE), and slew rate control (PTDSE) registers.

If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored. When the TPM is in output compare mode, the corresponding PTDSE can be used to provide slew rate on the pin. When the TPM is in input capture mode, the corresponding PTDPE can be used, provided the corresponding PTDDD bit is 0, to provide a pullup device on the pin.

Reads of PTDD will return the logic value of the corresponding pin, provided PTDDD is 0.

76543210

Reset 00000000

000

PTDD4 PTDD3 PTDD2 PTDD1 PTDD0

Figure 6-20. Port D Data Register (PTDD)

Table 6-13. PTDD Field Descriptions

Field Description

4:0

PTDD[4:0]

Reset 00000000

Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D pins that are conﬁgured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port D pins that are conﬁgured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also conﬁgures all port pins as high-impedance inputs with pullups disabled.

76543210

000

PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0

Figure 6-21. Pullup Enable for Port D (PTDPE)

Table 6-14. PTDPE Field Descriptions

Field Description

4:0

PTDPE[4:0]

Pullup Enable for Port D Bits — For port D pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. For port D pins that are conﬁgured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 93

Parallel Input/Output

76543210

Reset 00000000

000

PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0

Figure 6-22. Slew Rate Control Enable for Port D (PTDSE)

Table 6-15. PTDSE Field Descriptions

Field Description

4:0

PTDSE[4:0]

Reset 00000000

Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. For port D pins that are conﬁgured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled.

76543210

000

PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0

Figure 6-23. Data Direction for Port D (PTDDD)

Table 6-16. PTDDD Field Descriptions

Field Description

4:0

PTDDD[4:0]

Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

94 Freescale Semiconductor

Parallel Input/Output

6.5.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD)

Port E includes six general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers.

If the SCI1 takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to provide slew rate on the SCI1 transmit pin, TxD1. PTEPE can be used, provided the corresponding PTEDD bit is 0, to provide a pullup device on the SCI1 receive pin, RxD1.

If the SPI takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to provide slew rate on the SPI serial output pin (MOSI or MISO) and serial clock pin (SPSCK) depending on the SPI operational mode. PTEPE can be used, provided the corresponding PTEDD bit is 0, to provide a pullup device on the SPI serial input pins (MOSI or MISO) and slave select pin ( SPI operational mode.

Reads of PTED will return the logic value of the corresponding pin, provided PTEDD is 0.

76543210

PTED5 PTED4 PTED3 PTED2 PTED1 PTED0

SS) depending on the

Reset 00000000

Figure 6-24. Port E Data Register (PTED)

Table 6-17. PTED Field Descriptions

Field Description

5:0

PTED[5:0]

Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E pins that are conﬁgured as outputs, reads return the last value written to this register. Writes are latched into all bits in this register. For port E pins that are conﬁgured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also conﬁgures all port pins as high-impedance inputs with pullups disabled.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 95

Parallel Input/Output

76543210

Reset 00000000

PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0

Figure 6-25. Pullup Enable for Port E (PTEPE)

Table 6-18. PTEPE Field Descriptions

Field Description

5:0

PTEPE[5:0]

Reset 00000000

Pullup Enable for Port E Bits — For port E pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. For port E pins that are conﬁgured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled.

76543210

PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0

Figure 6-26. Slew Rate Control Enable for Port E (PTESE)

Table 6-19. PTESE Field Descriptions

Field Description

5:0

PTESE[5:0]

Slew Rate Control Enable for Port E Bits — For port E pins that are outputs, these read/write control bits

determine whether the slew rate controlled outputs are enabled. For port E pins that are conﬁgured as inputs,

these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled.

76543210

Reset 00000000

PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0

Figure 6-27. Data Direction for Port E (PTEDD)

Table 6-20. PTEDD Field Descriptions

Field Description

5:0

PTEDD[5:0]

96 Freescale Semiconductor

Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for

PTED reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Parallel Input/Output

6.5.6 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD)

Port G includes four general-purpose I/O pins that are shared with BKGD/MS function and the oscillator or external clock pins. Port G pins used as general-purpose I/O pins are controlled by the port G data (PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers.

Port pin PTG0, while in reset, defaults to the BKGD/MS pin. After the MCU is exits reset, PTG0 can be conﬁgured to be a general-purpose output pin. When BKGD/MS takes control of PTG0, the corresponding PTGDD, PTGPE, and PTGPSE bits are ignored.

Port pins PTG1 and PTG2 can be conﬁgured to be oscillator or external clock pins. When the oscillator takes control of a port G pin, the corresponding PTGD, PTGDD, PTGSE, and PTGPE bits are ignored.

Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD is 0.

76543210

Reset 00000000

0000

PTGD3 PTGD2 PTGD1 PTGD0

Figure 6-28. Port PTG Data Register (PTGD)

Table 6-21. PTGD Field Descriptions

Field Description

3:0

PTGD[3:0]

Reset 00000000

Port PTG Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G pins that are conﬁgured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port G pins that are conﬁgured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also conﬁgures all port pins as high-impedance inputs with pullups disabled.

76543210

0000

PTGPE3 PTGPE2 PTGPE1 PTGPE0

Figure 6-29. Pullup Enable for Port G (PTGPE)

Table 6-22. PTGPE Field Descriptions

Field Description

3:0

PTGPE[3:0]

Pullup Enable for Port G Bits — For port G pins that are inputs, these read/write control bits determine whether internal pullup devices are enabled. For port G pins that are conﬁgured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 97

Parallel Input/Output

76543210

0000

PTGSE3 PTGSE2 PTGSE1 PTGSE0

Reset 00000000

Figure 6-30. Slew Rate Control Enable for Port G (PTGSE)

Table 6-23. PTGSE Field Descriptions

Field Description

3:0

PTGSE[3:0]

Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. For port G pins that are conﬁgured as inputs, these bits are ignored. 0 Slew rate control disabled. 1 Slew rate control enabled.

76543210

0000

PTGDD3 PTGDD2 PTGDD1

PTGDD0

(1)

Note

Reset 00000000

Figure 6-31. Data Direction for Port G (PTGDD)

Although PTGDD0 is implemented, this bit actually has no effect on the operation of PTG0/BKGD.

Table 6-24. PTGDD Field Descriptions

Field Description

3:0

PTGDD[3:0]

Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for PTGD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.

MC9S08GT16A/GT8A Data Sheet, Rev. 1

98 Freescale Semiconductor

Chapter 7 Keyboard Interrupt (S08KBIV1)

7.1 Introduction

The MC9S08GT16A/GT8A has one KBI module with eight keyboard interrupt inputs that share port A pins. See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins.

7.1.1 Port A and Keyboard Interrupt Pins

MCU Pin:

PTA7/

KBIP7

PTA6/ KBIP6

Figure 7-1. Port A Pin Names

PTA5/

KBIP5

PTA4/ KBIP4

PTA3/ KBIP3

PTA2/ KBIP2

PTA1/ KBIP1

PTA0/ KBIP0

The following paragraphs discuss controlling the keyboard interrupt pins.

Port A is an 8-bit port which is shared among the KBI keyboard interrupt inputs and general-purpose I/O. The eight KBIPEn control bits in the KBIPE register allow selection of any combination of port A pins to be assigned as KBI inputs. Any pins which are enabled as KBI inputs will be forced to act as inputs and the remaining port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction (PTADD), and pullup enable (PTAPE) registers.

KBI inputs can be conﬁgured for edge-only sensitivity or edge-and-level sensitivity. Bits 3 through 0 of port A are falling-edge/low-level sensitive while bits 7 through 4 can be conﬁgured for rising-edge/high-level or for falling-edge/low-level sensitivity.

The eight PTAPEn control bits in the PTAPE register allow you to select whether an internal pullup device is enabled on each port A pin that is conﬁgured as an input. When any of bits 7 through 4 of port A are enabled as KBI inputs and are conﬁgured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices.

An enabled keyboard interrupt can be used to wake the MCU from wait or standby (stop3).

7.1.2 Features

The keyboard interrupt (KBI) module features include:

• Keyboard interrupts selectable on eight port pins: — Four falling-edge/low-level sensitive

— Four falling-edge/low-level or rising-edge/high-level sensitive — Choice of edge-only or edge-and-level sensitivity — Common interrupt ﬂag and interrupt enable control — Capable of waking up the MCU from stop3 or wait mode

MC9S08GT16A/GT8A Data Sheet, Rev. 1

Freescale Semiconductor 99

Keyboard Interrupt (S08KBIV1)

HCS08 CORE

CPU

HCS08 SYSTEM CONTROL

RESET

NOTE 4

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

RTI

IRQ

IRQ LVD

NOTES 2, 3

BDC

COP

BKGD

REFL

REFH

SSAD

DDAD

8-BIT KEYBOARD

INTERRUPT (KBI)

10-BIT

ANALOG-TO-DIGITAL

CONVERTER (ATD)

INTER-IC (IIC)

SERIAL COMMUNICATIONS

INTERFACE (SCI2)

SCL

SDA

RXD2

TXD2

PORT A

PORT B

PORT C

PTA7/KBIP7–

PTA4/KBIP4

PTA3/KBIP3– PTA0/KBIP0

PTB7/ADP7– PTB4/ADP4

PTB3/ADP3– PTB0/ADP0

PTC7 PTC6 PTC5 PTC4 PTC3/SCL PTC2/SDA

PTC1/RxD2 PTC0/TxD2

NOTE 6

NOTE 5

USER FLASH

(GT16A = 16,384 BYTES)

(GT8A = 8192 BYTES)

USER RAM

(GT16A = 2048 BYTES)

(GT8A = 1024 BYTES)

ON-CHIP ICE

DEBUG

MODULE (DBG)

2-CHANNEL TIMER/PWM

(TPM2)

3-CHANNEL TIMER/PWM

(TPM1)

SERIAL PERIPHERAL

INTERFACE (SPI)

SERIAL COMMUNICATIONS

INTERFACE (SCI1)

CH1 CH0

CH0

CH1 CH2

SPSCK

MOSI MISO

RXD1 TXD1

PORT D

PORT E

PTD4/TPM2CH1 PTD3/TPM2CLK/TPM2CH0

PTD2/TPM1CH2 PTD1/TPM1CH1 PTD0/TPM1CLK/TPM1CH0

PTE5/SPSCK PTE4/MOSI PTE3/MISO PTE2/

PTE1/RxD1 PTE0/TxD1

INTERNAL CLOCK

GENERATOR (ICG)

EXTAL

LOW-POWER OSCILLATOR

VOLTAGE

REGULATOR

= Pins not available in 44-, 42-, or 32-pin packages = Pins not available in 42- or 32-pin packages

XTAL

BKGD

PORT G

PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS

= Pins not available in 32-pin packages

NOTES:

1. Port pins are software configurable with pullup device if input port.

2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).

3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.

4. Pin contains integrated pullup device.

5. High current drive

6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).

Figure 7-2. Block Diagram Highlighting the KBI Module

MC9S08GT16A/GT8A Data Sheet, Rev. 1

100 Freescale Semiconductor

Freescale MC9S08GT16A, MC9S08GT8A Data Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Chapter 1 Device Overview

1.1 Introduction

1.1.1 Devices in the MC9S08GT16A/GT8A Series

1.1.2 MCU Block Diagram

1.2 System Clock Distribution

Chapter 2 Pins and Connections

2.1 Introduction

2.2 Device Pin Assignment

2.3 Recommended System Connections

2.3.6 General-Purpose I/O and Peripheral Ports

2.3.7 Signal Properties Summary

Chapter 3 Modes of Operation

3.1 Introduction

3.1.1 Features

3.2 Run Mode

3.3 Active Background Mode

3.4 Wait Mode

3.5 Stop Modes

3.5.1 Stop1 Mode

3.5.2 Stop2 Mode

3.5.3 Stop3 Mode

3.5.4 Active BDM Enabled in Stop Mode

3.5.5 LVD Enabled in Stop Mode

3.5.6 On-Chip Peripheral Modules in Stop Modes

Chapter 4 Memory

4.1 MC9S08GT16A/GT8A Memory Map

4.1.1 Reset and Interrupt Vector Assignments

4.2 Register Addresses and Bit Assignments

4.3 RAM

4.4 FLASH

4.4.1 Features

4.4.2 Program and Erase Times

4.4.3 Program and Erase Command Execution

4.4.4 Burst Program Execution

4.4.5 Access Errors

4.4.6 FLASH Block Protection

4.4.7 Vector Redirection

4.5 Security

4.6.1 FLASH Clock Divider Register (FCDIV)

4.6.2 FLASH Options Register (FOPT and NVOPT)

4.6.4 FLASH Protection Register (FPROT and NVPROT)

4.6.5 FLASH Status Register (FSTAT)

4.6.6 FLASH Command Register (FCMD)

5.1 Introduction

5.1.1 Features

5.2 MCU Reset

5.3 Computer Operating Properly (COP) Watchdog

5.4 Interrupts

5.4.1 Interrupt Stack Frame

5.4.2.2 Edge and Level Sensitivity

5.4.3 Interrupt Vectors, Sources, and Local Masks

5.5 Low-Voltage Detect (LVD) System

5.5.1 Power-On Reset Operation

5.5.2 LVD Reset Operation

5.5.3 LVD Interrupt Operation

5.5.4 Low-Voltage Warning (LVW)

5.6 Real-Time Interrupt (RTI)

5.7.1 Interrupt Pin Request Status and Control Register (IRQSC)

5.7.2 System Reset Status Register (SRS)

5.7.3 System Background Debug Force Reset Register (SBDFR)

5.7.4 System Options Register (SOPT)

5.7.6 System Real-Time Interrupt Status and Control Register (SRTISC)

5.7.7 System Power Management Status and Control 1 Register (SPMSC1)

5.7.8 System Power Management Status and Control 2 Register (SPMSC2)

Chapter 6 Parallel Input/Output

6.1 Introduction

6.1.1 Features

6.1.2 Block Diagram

6.2 External Signal Description

6.2.1 Port A and Keyboard Interrupts

6.2.2 Port B and Analog to Digital Converter Inputs

6.2.3 Port C and SCI2, IIC, and High-Current Drivers

6.2.4 Port D, TPM1 and TPM2

6.2.5 Port E, SCI1, and SPI

6.2.6 Port G, BKGD/MS, and Oscillator

6.3 Parallel I/O Controls