Freescale MC9S08GT16A, MC9S08GT8A Data Sheet
MC9S08GT16A
MC9S08GT8A
Data Sheet
HCS08
Microcontrollers
MC9S08GT16A
Rev. 1
7/2006
freescale.com
MC9S08GT16A/GT8A Features
8-Bit HCS08 Central Processor Unit (CPU)
• 40-MHz HCS08 CPU
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
Memory Options
• FLASH read/program/erase down to 1.8 V
• Up to 16K FLASH; up to 2K RAM
Power-Saving Modes
• Three very low power stop modes
• Reduced power wait mode
• Very low power real time interrupt for use in run,
wait, and stop
Clock Source Options
• Clock sources to internal hardware frequency
locked-loop (FLL): internal, external, crystal, or
resonator
• Internal clock with ±0.2% trimming resolution and
±0.5% deviation across voltage or across
temperature
System Protection
• Software selectable pullups on ports when used as
input
• Internal pullup on RESET and IRQ pin to reduce
customer system cost
• Up to 38 general-purpose input/output (I/O) pins,
plus one output-only pin, depending on package
selection
Development Support
• Background debugging system
• Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
• On-chip, in-circuit emulation (ICE) debug module
with real-time bus capture. On-chip ICE debug
module containing two comparators and nine trigger
modes. Eight deep FIFO for storing change-of-flow
addresses and event-only data.
• Single-wire background debug interface
Package Options
• 48-pin QFN
• 44-pin QFP
• 42-pin PSDIP
• 32-pin QFN
• Optional watchdog computer operating properly
(COP) reset
• Low-voltage detection with reset or interrupt
• Illegal opcode detection with reset
• Illegal address detection with reset
• FLASH block protect and security
Peripherals
• ATD — 8-channel, 10-bit analog-to-digital
converter
• SCI — Two serial communications interface
modules
• SPI — Serial peripheral interface module
• IIC — Inter-integrated circuit bus module
• Timer —One 3-channel timer PWM module (TPM)
plus one 2-channel TPM
• KBI — 8-pin keyboard interrupt module
Input/Output
• 8 high-current pins (20 mA each)
MC9S08GT16A/GT8A Data Sheet
Covers: MC9S08GT16A
MC9S08GT8A
MC9S08GT16A
Rev. 1
7/2006
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document.
Revision
Number
1 07/17/2006 Initial public release
Revision
Date
Description of Changes
© Freescale Semiconductor, Inc., 2006. All rights reserved.
This product incorporates SuperFlash
®
Technology licensed from SST.
List of Chapters
Chapter 1 Device Overview ......................................................................19
Chapter 2 Pins and Connections .............................................................23
Chapter 3 Modes of Operation .................................................................33
Chapter 4 Memory .....................................................................................41
Chapter 5 Resets, Interrupts, and System Configuration .....................63
Chapter 6 Parallel Input/Output ...............................................................79
Chapter 7 Keyboard Interrupt (S08KBIV1) ..............................................99
Chapter 8 Central Processor Unit (S08CPUV2) ....................................105
Chapter 9 Internal Clock Generator (S08ICGV4) ..................................125
Chapter 10 Timer/PWM (S08TPMV2) ......................................................153
Chapter 11 Serial Communications Interface (S08SCIV1)..................... 169
Chapter 12 Serial Peripheral Interface (S08SPIV3) ................................187
Chapter 13 Inter-Integrated Circuit (S08IICV1) .......................................205
Chapter 14 Analog-to-Digital Converter (S08ATDV3) ............................221
Chapter 15 Development Support ...........................................................237
Appendix A Electrical Characteristics......................................................259
Appendix B Ordering Information and Mechanical Drawings................285
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 7
Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Introduction .....................................................................................................................................19
1.1.1 Devices in the MC9S08GT16A/GT8A Series ..................................................................19
1.1.2 MCU Block Diagram ........................................................................................................19
1.2 System Clock Distribution ..............................................................................................................21
Chapter 2
Pins and Connections
2.1 Introduction .....................................................................................................................................23
2.2 Device Pin Assignment ...................................................................................................................23
2.3 Recommended System Connections ...............................................................................................27
2.3.1 V
2.3.2 PTG1/XTAL, PTG2/EXTAL — Oscillator ......................................................................28
2.3.3
2.3.4 PTG0/BKGD/MS — Background / Mode Select .............................................................29
2.3.5 IRQ — External Interrupt Request Pin .............................................................................30
2.3.6 General-Purpose I/O and Peripheral Ports ........................................................................30
2.3.7 Signal Properties Summary ...............................................................................................31
, VSS, V
DD
RESET — External Reset Pin ...........................................................................................29
DDAD
, V
SSAD
, V
REFH
, V
— Power and Voltage References ...............28
REFL
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................33
3.1.1 Features .............................................................................................................................33
3.2 Run Mode ........................................................................................................................................33
3.3 Active Background Mode ................................................................................................................33
3.4 Wait Mode .......................................................................................................................................34
3.5 Stop Modes ......................................................................................................................................35
3.5.1 Stop1 Mode .......................................................................................................................35
3.5.2 Stop2 Mode .......................................................................................................................35
3.5.3 Stop3 Mode .......................................................................................................................36
3.5.4 Active BDM Enabled in Stop Mode .................................................................................37
3.5.5 LVD Enabled in Stop Mode ..............................................................................................37
3.5.6 On-Chip Peripheral Modules in Stop Modes ....................................................................38
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor NON-DISCLOSURE AGREEMENT REQUIRED 9
Section Number Title Page
Chapter 4
Memory
4.1 MC9S08GT16A/GT8A Memory Map ............................................................................................41
4.1.1 Reset and Interrupt Vector Assignments ...........................................................................42
4.2 Register Addresses and Bit Assignments ........................................................................................43
4.3 RAM ................................................................................................................................................48
4.4 FLASH ............................................................................................................................................48
4.4.1 Features .............................................................................................................................48
4.4.2 Program and Erase Times .................................................................................................49
4.4.3 Program and Erase Command Execution .........................................................................49
4.4.4 Burst Program Execution ..................................................................................................51
4.4.5 Access Errors ....................................................................................................................53
4.4.6 FLASH Block Protection ..................................................................................................53
4.4.7 Vector Redirection ............................................................................................................54
4.5 Security ............................................................................................................................................54
4.6 Register Definition ..........................................................................................................................56
4.6.1 FLASH Clock Divider Register (FCDIV) ........................................................................56
4.6.2 FLASH Options Register (FOPT and NVOPT) ................................................................57
4.6.3 FLASH Configuration Register (FCNFG) ........................................................................58
4.6.4 FLASH Protection Register (FPROT and NVPROT) .......................................................58
4.6.5 FLASH Status Register (FSTAT) ......................................................................................59
4.6.6 FLASH Command Register (FCMD) ...............................................................................60
Chapter 5
Resets, Interrupts, and System Configuration
5.1 Introduction .....................................................................................................................................63
5.1.1 Features .............................................................................................................................63
5.2 MCU Reset ......................................................................................................................................63
5.3 Computer Operating Properly (COP) Watchdog .............................................................................64
5.4 Interrupts .........................................................................................................................................64
5.4.1 Interrupt Stack Frame .......................................................................................................65
5.4.2 IRQ — External Interrupt Request Pin .............................................................................66
5.4.2.1 Pin Configuration Options ..............................................................................66
5.4.2.2 Edge and Level Sensitivity ..............................................................................67
5.4.3 Interrupt Vectors, Sources, and Local Masks ....................................................................67
5.5 Low-Voltage Detect (LVD) System ................................................................................................69
5.5.1 Power-On Reset Operation ...............................................................................................69
5.5.2 LVD Reset Operation ........................................................................................................69
5.5.3 LVD Interrupt Operation ...................................................................................................69
5.5.4 Low-Voltage Warning (LVW) ...........................................................................................69
5.6 Real-Time Interrupt (RTI) ...............................................................................................................69
5.7 Register Definition ..........................................................................................................................70
MC9S08GT16A/GT8A Data Sheet, Rev. 1
10 Freescale Semiconductor
Section Number Title Page
5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................71
5.7.2 System Reset Status Register (SRS) .................................................................................72
5.7.3 System Background Debug Force Reset Register (SBDFR) ............................................73
5.7.4 System Options Register (SOPT) .....................................................................................74
5.7.5 System Device Identification Register (SDIDH, SDIDL) ................................................75
5.7.6 System Real-Time Interrupt Status and Control Register (SRTISC) ................................76
5.7.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................77
5.7.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................78
Chapter 6
Parallel Input/Output
6.1 Introduction .....................................................................................................................................79
6.1.1 Features .............................................................................................................................79
6.1.2 Block Diagram ..................................................................................................................81
6.2 External Signal Description ............................................................................................................82
6.2.1 Port A and Keyboard Interrupts ........................................................................................82
6.2.2 Port B and Analog to Digital Converter Inputs .................................................................82
6.2.3 Port C and SCI2, IIC, and High-Current Drivers ..............................................................83
6.2.4 Port D, TPM1 and TPM2 ..................................................................................................83
6.2.5 Port E, SCI1, and SPI ........................................................................................................84
6.2.6 Port G, BKGD/MS, and Oscillator ...................................................................................84
6.3 Parallel I/O Controls ........................................................................................................................85
6.3.1 Data Direction Control ......................................................................................................85
6.3.2 Internal Pullup Control .....................................................................................................85
6.3.3 Slew Rate Control .............................................................................................................85
6.4 Stop Modes ......................................................................................................................................86
6.5 Register Definition ..........................................................................................................................86
6.5.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) .................................................86
6.5.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) .................................................89
6.5.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) .................................................91
6.5.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ...............................................93
6.5.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) ..................................................95
6.5.6 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) ...............................................97
Chapter 7
Keyboard Interrupt (S08KBIV1)
7.1 Introduction .....................................................................................................................................99
7.1.1 Port A and Keyboard Interrupt Pins ..................................................................................99
7.1.2 Features .............................................................................................................................99
7.1.3 KBI Block Diagram ........................................................................................................101
7.2 Register Definition ........................................................................................................................101
7.2.1 KBI Status and Control Register (KBISC) .....................................................................102
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Freescale Semiconductor 11
Section Number Title Page
7.2.2 KBI Pin Enable Register (KBIPE) ..................................................................................103
7.3 Functional Description ..................................................................................................................103
7.3.1 Pin Enables ......................................................................................................................103
7.3.2 Edge and Level Sensitivity ..............................................................................................103
7.3.3 KBI Interrupt Controls ....................................................................................................104
Chapter 8
Central Processor Unit (S08CPUV2)
8.1 Introduction ...................................................................................................................................105
8.1.1 Features ...........................................................................................................................105
8.2 Programmer’s Model and CPU Registers .....................................................................................106
8.2.1 Accumulator (A) .............................................................................................................106
8.2.2 Index Register (H:X) .......................................................................................................106
8.2.3 Stack Pointer (SP) ...........................................................................................................107
8.2.4 Program Counter (PC) ....................................................................................................107
8.2.5 Condition Code Register (CCR) .....................................................................................107
8.3 Addressing Modes .........................................................................................................................109
8.3.1 Inherent Addressing Mode (INH) ...................................................................................109
8.3.2 Relative Addressing Mode (REL) ...................................................................................109
8.3.3 Immediate Addressing Mode (IMM) ..............................................................................109
8.3.4 Direct Addressing Mode (DIR) ......................................................................................109
8.3.5 Extended Addressing Mode (EXT) ................................................................................110
8.3.6 Indexed Addressing Mode ..............................................................................................110
8.3.6.1 Indexed, No Offset (IX) ................................................................................110
8.3.6.2 Indexed, No Offset with Post Increment (IX+) .............................................110
8.3.6.3 Indexed, 8-Bit Offset (IX1) ...........................................................................110
8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .......................................110
8.3.6.5 Indexed, 16-Bit Offset (IX2) .........................................................................110
8.3.6.6 SP-Relative, 8-Bit Offset (SP1) ....................................................................110
8.3.6.7 SP-Relative, 16-Bit Offset (SP2) ..................................................................111
8.4 Special Operations .........................................................................................................................111
8.4.1 Reset Sequence ...............................................................................................................111
8.4.2 Interrupt Sequence ..........................................................................................................111
8.4.3 Wait Mode Operation ......................................................................................................112
8.4.4 Stop Mode Operation ......................................................................................................112
8.4.5 BGND Instruction ...........................................................................................................113
8.5 HCS08 Instruction Set Summary ..................................................................................................114
MC9S08GT16A/GT8A Data Sheet, Rev. 1
12 Freescale Semiconductor
Section Number Title Page
Chapter 9
Internal Clock Generator (S08ICGV4)
9.1 Introduction ...................................................................................................................................125
9.1.1 Features ...........................................................................................................................127
9.1.2 Modes of Operation ........................................................................................................128
9.1.3 Block Diagram ................................................................................................................129
9.2 External Signal Description ..........................................................................................................129
9.2.1 EXTAL — External Reference Clock / Oscillator Input ................................................129
9.2.2 XTAL — Oscillator Output ............................................................................................129
9.2.3 External Clock Connections ...........................................................................................130
9.2.4 External Crystal/Resonator Connections ........................................................................130
9.3 Register Definition ........................................................................................................................131
9.3.1 ICG Control Register 1 (ICGC1) ....................................................................................131
9.3.2 ICG Control Register 2 (ICGC2) ....................................................................................133
9.3.3 ICG Status Register 1 (ICGS1) .......................................................................................134
9.3.4 ICG Status Register 2 (ICGS2) .......................................................................................135
9.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ..................................................................135
9.3.6 ICG Trim Register (ICGTRM) .......................................................................................136
9.4 Functional Description ..................................................................................................................136
9.4.1 Off Mode (Off) ................................................................................................................137
9.4.1.1 BDM Active ..................................................................................................137
9.4.1.2 OSCSTEN Bit Set .........................................................................................137
9.4.1.3 Stop/Off Mode Recovery ..............................................................................137
9.4.2 Self-Clocked Mode (SCM) .............................................................................................137
9.4.3 FLL Engaged, Internal Clock (FEI) Mode .....................................................................138
9.4.4 FLL Engaged Internal Unlocked ....................................................................................139
9.4.5 FLL Engaged Internal Locked ........................................................................................139
9.4.6 FLL Bypassed, External Clock (FBE) Mode ..................................................................139
9.4.7 FLL Engaged, External Clock (FEE) Mode ...................................................................139
9.4.7.1 FLL Engaged External Unlocked .................................................................140
9.4.7.2 FLL Engaged External Locked .....................................................................140
9.4.8 FLL Lock and Loss-of-Lock Detection ..........................................................................140
9.4.9 FLL Loss-of-Clock Detection .........................................................................................141
9.4.10 Clock Mode Requirements .............................................................................................142
9.4.11 Fixed Frequency Clock ...................................................................................................143
9.4.12 High Gain Oscillator .......................................................................................................143
9.5 Initialization/Application Information ..........................................................................................143
9.5.1 Introduction .....................................................................................................................143
9.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ...........................145
9.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ..............................147
9.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ......................149
9.5.5 Example #4: Internal Clock Generator Trim ..................................................................151
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 13
Section Number Title Page
Chapter 10
Timer/PWM (S08TPMV2)
10.1 Introduction ...................................................................................................................................153
10.1.1 Features ...........................................................................................................................153
10.1.2 Features ...........................................................................................................................155
10.1.3 Block Diagram ................................................................................................................155
10.2 External Signal Description ..........................................................................................................157
10.2.1 External TPM Clock Sources ..........................................................................................157
10.2.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................157
10.3 Register Definition ........................................................................................................................157
10.3.1 Timer x Status and Control Register (TPMxSC) ............................................................158
10.3.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ................................................159
10.3.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ...............................160
10.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) ......................................161
10.3.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ......................................162
10.4 Functional Description ..................................................................................................................163
10.4.1 Counter ............................................................................................................................163
10.4.2 Channel Mode Selection .................................................................................................164
10.4.2.1 Input Capture Mode ......................................................................................164
10.4.2.2 Output Compare Mode .................................................................................165
10.4.2.3 Edge-Aligned PWM Mode ...........................................................................165
10.4.3 Center-Aligned PWM Mode ...........................................................................................166
10.5 TPM Interrupts ..............................................................................................................................167
10.5.1 Clearing Timer Interrupt Flags .......................................................................................167
10.5.2 Timer Overflow Interrupt Description ............................................................................167
10.5.3 Channel Event Interrupt Description ..............................................................................168
10.5.4 PWM End-of-Duty-Cycle Events ...................................................................................168
Chapter 11
Serial Communications Interface (S08SCIV1)
11.1 Introduction ...................................................................................................................................169
11.1.1 Features ...........................................................................................................................171
11.1.2 Modes of Operation ........................................................................................................171
11.1.3 Block Diagram ................................................................................................................172
11.2 Register Definition ........................................................................................................................174
11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) ..........................................................174
11.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................175
11.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................176
11.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................177
11.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................179
11.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................179
11.2.7 SCI Data Register (SCIxD) .............................................................................................180
MC9S08GT16A/GT8A Data Sheet, Rev. 1
14 Freescale Semiconductor
Section Number Title Page
11.3 Functional Description ..................................................................................................................181
11.3.1 Baud Rate Generation .....................................................................................................181
11.3.2 Transmitter Functional Description ................................................................................181
11.3.2.1 Send Break and Queued Idle .........................................................................182
11.3.3 Receiver Functional Description .....................................................................................182
11.3.3.1 Data Sampling Technique .............................................................................183
11.3.3.2 Receiver Wakeup Operation .........................................................................183
11.3.3.2.1Idle-Line Wakeup .....................................................................184
11.3.3.2.2Address-Mark Wakeup .............................................................184
11.3.4 Interrupts and Status Flags ..............................................................................................184
11.3.5 Additional SCI Functions ...............................................................................................185
11.3.5.1 8- and 9-Bit Data Modes ...............................................................................185
11.3.5.2 Stop Mode Operation ....................................................................................185
11.3.5.3 Loop Mode ....................................................................................................186
11.3.5.4 Single-Wire Operation ..................................................................................186
Chapter 12
Serial Peripheral Interface (S08SPIV3)
12.1 Introduction ...................................................................................................................................187
12.1.1 Features ...........................................................................................................................189
12.1.2 Block Diagrams ..............................................................................................................190
12.1.2.1 SPI System Block Diagram ..........................................................................190
12.1.2.2 SPI Module Block Diagram ..........................................................................190
12.1.3 SPI Baud Rate Generation ..............................................................................................191
12.2 External Signal Description ..........................................................................................................192
12.2.1 SPSCK — SPI Serial Clock ............................................................................................192
12.2.2 MOSI — Master Data Out, Slave Data In ......................................................................192
12.2.3 MISO — Master Data In, Slave Data Out ......................................................................192
12.2.4
12.3 Modes of Operation .......................................................................................................................193
12.3.1 SPI in Stop Modes ..........................................................................................................193
12.4 Register Definition ........................................................................................................................193
12.4.1 SPI Control Register 1 (SPIC1) ......................................................................................193
12.4.2 SPI Control Register 2 (SPIC2) ......................................................................................194
12.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................195
12.4.4 SPI Status Register (SPIS) ..............................................................................................196
12.4.5 SPI Data Register (SPID) ................................................................................................197
12.5 Functional Description ..................................................................................................................198
12.5.1 SPI Clock Formats ..........................................................................................................198
12.5.2 SPI Interrupts ..................................................................................................................201
12.5.3 Mode Fault Detection .....................................................................................................201
12.6 Initialization/Application Information ..........................................................................................201
SS — Slave Select ...........................................................................................................192
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 15
Section Number Title Page
12.6.1 SPI Module Initialization Example .................................................................................201
12.6.1.1 Initialization Sequence ..................................................................................201
12.6.1.2 Pseudo—Code Example ...............................................................................202
Chapter 13
Inter-Integrated Circuit (S08IICV1)
13.1 Introduction ...................................................................................................................................205
13.1.1 Features ...........................................................................................................................207
13.1.2 Modes of Operation ........................................................................................................207
13.1.3 Block Diagram ................................................................................................................208
13.2 External Signal Description ..........................................................................................................208
13.2.1 SCL — Serial Clock Line ...............................................................................................208
13.2.2 SDA — Serial Data Line ................................................................................................208
13.3 Register Definition ........................................................................................................................208
13.3.1 IIC Address Register (IICA) ...........................................................................................209
13.3.2 IIC Frequency Divider Register (IICF) ...........................................................................209
13.3.3 IIC Control Register (IICC) ............................................................................................212
13.3.4 IIC Status Register (IICS) ...............................................................................................213
13.3.5 IIC Data I/O Register (IICD) ..........................................................................................214
13.4 Functional Description ..................................................................................................................215
13.4.1 IIC Protocol .....................................................................................................................215
13.4.1.1 START Signal ...............................................................................................216
13.4.1.2 Slave Address Transmission .........................................................................216
13.4.1.3 Data Transfer .................................................................................................216
13.4.1.4 STOP Signal ..................................................................................................217
13.4.1.5 Repeated START Signal ...............................................................................217
13.4.1.6 Arbitration Procedure ....................................................................................217
13.4.1.7 Clock Synchronization ..................................................................................217
13.4.1.8 Handshaking .................................................................................................218
13.4.1.9 Clock Stretching ............................................................................................218
13.5 Resets ............................................................................................................................................218
13.6 Interrupts .......................................................................................................................................218
13.6.1 Byte Transfer Interrupt ....................................................................................................219
13.6.2 Address Detect Interrupt .................................................................................................219
13.6.3 Arbitration Lost Interrupt ................................................................................................219
Chapter 14
Analog-to-Digital Converter (S08ATDV3)
14.1 Introduction ...................................................................................................................................223
14.1.1 Features ...........................................................................................................................223
14.1.2 Modes of Operation ........................................................................................................223
14.1.2.1 Stop Mode .....................................................................................................223
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16 Freescale Semiconductor
Section Number Title Page
14.1.2.2 Power Down Mode .......................................................................................223
14.1.3 Block Diagram ................................................................................................................223
14.2 External Signal Description ..........................................................................................................224
14.2.1 ADP7–ADP0 — Channel Input Pins ..............................................................................225
14.2.2 V
14.2.3 V
REFH
DDAD
, V
, V
14.3 Register Definition ........................................................................................................................225
14.3.1 ATD Control (ATDC) .....................................................................................................225
14.3.2 ATD Status and Control (ATDSC) ..................................................................................228
14.3.3 ATD Result Data (ATDRH, ATDRL) .............................................................................229
14.3.4 ATD Pin Enable (ATDPE) ..............................................................................................229
14.4 Functional Description ..................................................................................................................230
14.4.1 Mode Control ..................................................................................................................230
14.4.2 Sample and Hold .............................................................................................................230
14.4.3 Analog Input Multiplexer ................................................................................................232
14.4.4 ATD Module Accuracy Definitions ................................................................................232
14.5 Resets ............................................................................................................................................235
14.6 Interrupts .......................................................................................................................................235
— ATD Reference Pins .........................................................................225
REFL
SSAD
— ATD Supply Pins ............................................................................225
Chapter 15
Development Support
15.1 Introduction ...................................................................................................................................237
15.1.1 Features ...........................................................................................................................238
15.2 Background Debug Controller (BDC) ..........................................................................................238
15.2.1 BKGD Pin Description ...................................................................................................239
15.2.2 Communication Details ..................................................................................................240
15.2.3 BDC Commands .............................................................................................................244
15.2.4 BDC Hardware Breakpoint .............................................................................................246
15.3 On-Chip Debug System (DBG) ....................................................................................................247
15.3.1 Comparators A and B ......................................................................................................247
15.3.2 Bus Capture Information and FIFO Operation ...............................................................247
15.3.3 Change-of-Flow Information ..........................................................................................248
15.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................248
15.3.5 Trigger Modes .................................................................................................................249
15.3.6 Hardware Breakpoints ....................................................................................................251
15.4 Register Definition ........................................................................................................................251
15.4.1 BDC Registers and Control Bits .....................................................................................251
15.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................252
15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................253
15.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................253
15.4.3 DBG Registers and Control Bits .....................................................................................254
15.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................254
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 17
Section Number Title Page
15.4.3.2 Debug Comparator A Low Register (DBGCAL) .........................................254
15.4.3.3 Debug Comparator B High Register (DBGCBH) .........................................254
15.4.3.4 Debug Comparator B Low Register (DBGCBL) ..........................................254
15.4.3.5 Debug FIFO High Register (DBGFH) ..........................................................255
15.4.3.6 Debug FIFO Low Register (DBGFL) ...........................................................255
15.4.3.7 Debug Control Register (DBGC) ..................................................................256
15.4.3.8 Debug Trigger Register (DBGT) ..................................................................257
15.4.3.9 Debug Status Register (DBGS) .....................................................................258
Appendix A
Electrical Characteristics
A.1 Introduction ...................................................................................................................................259
A.2 Parameter Classification ................................................................................................................259
A.3 Absolute Maximum Ratings ..........................................................................................................259
A.4 Thermal Characteristics .................................................................................................................260
A.5 Electrostatic Discharge (ESD) Protection Characteristics ............................................................262
A.6 DC Characteristics .........................................................................................................................262
A.7 Supply Current Characteristics ......................................................................................................266
A.8 ATD Characteristics ......................................................................................................................272
A.9 Internal Clock Generation Module Characteristics .......................................................................274
A.9.1 ICG Frequency Specifications ........................................................................................275
A.10 AC Characteristics .........................................................................................................................276
A.10.1 Control Timing ...............................................................................................................277
A.10.2 Timer/PWM (TPM) Module Timing ..............................................................................278
A.10.3 SPI Timing ......................................................................................................................280
A.11 FLASH Specifications ...................................................................................................................283
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information ....................................................................................................................285
B.1.1 Device Numbering Scheme ............................................................................................285
B.2 Mechanical Drawings ....................................................................................................................285
MC9S08GT16A/GT8A Data Sheet, Rev. 1
18 Freescale Semiconductor
Chapter 1 Device Overview
1.1 Introduction
The MC9S08GT16A/GT8A are members of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types (see Table 1-1).
1.1.1 Devices in the MC9S08GT16A/GT8A Series
Table 1-1 lists the devices available in the MC9S08GT16A/GT8A series and summarizes the differences
among them.
Table 1-1. Devices in the MC9S08GT16A/GT8A Series
Device FLASH RAM TPM ATD KBI I/O Packages
(1) 3-ch, (1) 2-ch, 16-bit 8 8 39 48 QFN
MC9S08GT16A 16K 2K
MC9S08GT8A 8K 1K (1) 3-ch, (1) 2-ch, 16-bit 8 8 39 48 QFN
(2) 2-ch, 16-bit 8 8 36 44 QFP
(2) 2-ch, 16-bit 8 8 34 42 SDIP
(1) 2-ch, (1) 1-ch, 16-bit 4 4 24 32 QFN
(2) 2-ch, 16-bit 8 8 36 44 QFP
(2) 2-ch, 16-bit 8 8 34 42 SDIP
(1) 2-ch, (1) 1-ch, 16-bit 4 4 24 32 QFN
1.1.2 MCU Block Diagram
This block diagrams show the structure of the MC9S08GT16A/GT8A MCUs.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 19
Device Overview
RESET
NOTE 4
IRQ
NOTES 2, 3
HCS08 CORE
CPU
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
IRQ LVD
BDC
COP
BKGD
REFL
V
REFH
V
SSAD
DDAD
V
V
8-BIT KEYBOARD
INTERRUPT (KBI)
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD)
INTER-IC (IIC)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
8
8
SCL
SDA
RXD2
TXD2
PORT A
PORT B
4
4
4
4
PORT C
PTA7/KBIP7–
PTA4/KBIP4
PTA3/KBIP3–
PTA0/KBIP0
PTB7/ADP7–
PTB4/ADP4
PTB3/ADP3–
PTB0/ADP0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL
PTC2/SDA
PTC1/RxD2
PTC0/TxD2
NOTE 6
NOTE 5
USER FLASH
(GT16A = 16,384 BYTES)
(GT8A = 8192 BYTES)
USER RAM
(GT16A = 2048 BYTES)
(GT8A = 1024 BYTES)
ON-CHIP ICE
DEBUG
MODULE (DBG)
INTERNAL CLOCK
GENERATOR (ICG)
LOW-POWER OSCILLATOR
V
DD
V
SS
V
SS
VOLTAGE
REGULATOR
2-CHANNEL TIMER/PWM
(TPM2)
3-CHANNEL TIMER/PWM
(TPM1)
SERIAL PERIPHERAL
INTERFACE (SPI)
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
EXTAL
XTAL
BKGD
= Pins not available in 44-, 42-, or 32-pin packages
= Pins not available in 42- or 32-pin packages
= Pins not available in 32-pin packages
CH1
CH0
CH0
CH1
CH2
SPSCK
MOSI
MISO
SS
RXD1
TXD1
PORT D
PORT E
PORT G
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to V
4. Pin contains integrated pullup device.
. IRQ should not be driven above VDD.
DD
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 1-1. MC9S08GT16A/GT8A Block Diagram
MC9S08GT16A/GT8A Data Sheet, Rev. 1
20 Freescale Semiconductor
Table 1-2 lists the functional versions of the on-chip modules.
Table 1-2. Block Versions
Module Version
Analog-to-Digital Converter (ATD) 3
Internal Clock Generator (ICG) 4
Inter-Integrated Circuit (IIC) 1
Keyboard Interrupt (KBI) 1
Serial Communications Interface (SCI) 1
Serial Peripheral Interface (SPI) 3
Timer Pulse-Width Modulator (TPM) 2
Central Processing Unit (CPU) 2
1.2 System Clock Distribution
Device Overview
ICG
ICGERCLK
FFE
SYSTEM
CONTROL
LOGIC
RTI
TPM1 TPM2 IIC SCI1 SCI2 SPI
÷2
FIXED FREQ CLOCK (XCLK)
ICGOUT
ICGLCLK*
* ICGLCLK is the alternate BDC clock source for the MC9S08GT16A/GT8A.
÷2
CPU
BUSCLK
BDC
COP
Figure 1-2. System Clock Distribution Diagram
ATD
ATD has min and max
frequency requirements.
See Chapter 14, “Ana-
log-to-Digital Converter
(S08ATDV3)”
and Appendix A, “Electrical
Characteristics.”
RAM FLASH
FLASH has frequency
requirements for program
and erase operation.
See Appendix A, “Electrical
Characteristics”.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 21
Device Overview
Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock
connection diagram. The ICG supplies the clock sources:
• ICGOUT is an output of the ICG module. It is one of the following:
— The external crystal oscillator
— An external clock source
— The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop
sub-module
Control bits inside the ICG determine which source is connected.
• FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency
of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK.
Otherwise the fixed-frequency clock will be BUSCLK.
• ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed
up BDC communications in systems where the bus clock is slow.
• ICGERCLK — External reference clock can be selected as the real-time interrupt clock source.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
22 Freescale Semiconductor
Chapter 2 Pins and Connections
2.1 Introduction
This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
2.2 Device Pin Assignment
DDAD
RESET
PTC0/TxD2
PTC1/RxD2
PTC2/SDA
PTC3/SCL
PTC4
PTC5
PTC6
PTC7
PTE0/TxD1
PTE1/RxD1
IRQ
SSAD
PTG2/EXTAL
PTG1/XTAL
PTG3
47
48
1
2
3
4
5
6
7
8
9
10
11
12
14
13
PTG0/BKGD/MS
46
45
15
16
V
V
44
43
17
18
PTA6/KBIP6
PTA7/KBIP7
42
41
19
20
PTA4/KBIP4
PTA5/KBIP5
40
39
21
22
23
PTA2/KBIP2
PTA3/KBIP3
37
38
36
35
34
33
32
31
30
29
28
27
26
PTB0/ADP0
25
24
PTA1/KBIP1
PTA0/KBIP0
V
V
PTB7/ADP7
PTB6/ADP6
PTB5/ADP5
PTB4/ADP4
PTB3/ADP3
PTB2/ADP2
PTB1/ADP1
REFL
REFH
SS2
V
DD
V
PTD1/TPM1CH1
PTD2/TPM1CH2
PTD0/TPM1CLK/TPM1CH0
PTD3/TPM2CLK/TPM2CH0
PTD4/TPM2CH1
PTE2/SS
PTE4/MOSI
PTE3/MISO
SS1
V
PTE5/SPSCK
Figure 2-1. MC9S08GT16A/GT8A in 48-Pin QFN Package
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 23
Pins and Connections
RESET
PTC0/TxD2
PTC1/RxD2
PTC2/SDA
PTC3/SCL
PTC4
PTC5
PTC6
PTE0/TxD1
PTE1/RxD1
IRQ
1
11
PTG2/EXTAL
44
2
3
4
5
6
7
8
9
10
12
PTG1/XTAL
PTG0/BKGD/MS
43
42
13
14
SSAD
V
41
15
DDAD
V
40
16
PTA5/KBIP5
PTA6/KBIP6
PTA7/KBIP7
39
38
17
18
19
PTA4/KBIP4
37
36
20
PTA2/KBIP2
PTA3/KBIP3
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PTA1/KBIP1
PTA0/KBIP0
V
REFL
V
REFH
PTB7/ADP7
PTB6/ADP6
PTB5/ADP5
PTB4/ADP4
PTB3/ADP3
PTB2/ADP2
PTB1/ADP1
SS
DD
V
V
PTE2/SS
PTE3/MISO
PTE4/MOSI
PTE5/SPSCK
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTD3/TPM2CLK/TPM2CH0
PTB0/ADP0
PTD4/TPM2CH1
Figure 2-2. MC9S08GT16A/GT8A in 44-Pin QFP Package
MC9S08GT16A/GT8A Data Sheet, Rev. 1
24 Freescale Semiconductor
Pins and Connections
V
DDAD
V
SSAD
PTG0/BKGD/MS
PTG1/XTAL
PTG2/EXTAL
RESET
PTC0/TxD2
PTC1/RXD2
PTC2/SDA
PTC3/SCL
PTC4
PTE0/TxD1
PTE1/RxD1
IRQ
PTE2/
SS
PTE3/MISO
PTE4/MOSI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
15 28
16 27
17 26
PTA7/KBIP7
PTA6/KBIP6
PTA5/KBIP5
PTA4/KBIP4
PTA3/KBIP3
PTA2/KBIP2
PTA1/KBIP1
PTA0/KBIP0
V
REFL
V
REFH
PTB7/ADP7
PTB6/ADP6
PTB5/ADP5
PTB4/ADP4
PTB3/ADP3
PTB2/ADP2
PTB1/ADP1
PTE5/SPSCK
V
SS
V
DD
PTD0/TPM1CLK/TPM1CH0
Figure 2-3. MC9S08GT16A/GT8A in 42-Pin SDIP Package
18 25
19 24
20 23
21 22
PTB0/ADP0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
PTD1/TPM1CH1
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 25
Pins and Connections
RESET
PTC0/TxD2
PTC1/RxD2
PTC2/SDA
PTC3/SCL
PTE0/TxD1
PTE1/RxD1
IRQ
PTG2/EXTAL
32
1
2
3
4
5
6
7
8
9
PTG1/XTAL
PTG0/BKGD
31 30 29
11
10
DDAD
SSAD
V
V
28
12 13 14
SS
V
PTA6/KBIP6
PTA7/KBIP7
26
27
15
DD
V
PTA5/KBIP5
25
24
V
23
22
V
21
PTB3/ADP3
20
PTB2/ADP2
19
18
PTB0/ADP0
17
16
PTA4/KBIP4
REFL
REFH
PTB1/ADP1
PTD3/TPM2CLK/TPM2CH0
PTE2/SS
PTE3/MISO
PTE4/MOSI
PTE5/SPSCK
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
Figure 2-4. MC9S08GT16A/GT8A in 32-Pin QFN Package
MC9S08GT16A/GT8A Data Sheet, Rev. 1
26 Freescale Semiconductor
Pins and Connections
2.3 Recommended System Connections
Figure 2-5 shows pin connections that are common to almost all MC9S08GT16A application systems. A
more detailed discussion of system connections follows.
SYSTEM
POWER
BACKGROUND HEADER
V
DD
OPTIONAL
MANUAL
RESET
V
+
3 V
C
BLK
10 µF
BKGD/MS
+
ASYNCHRONOUS
INTERRUPT
INPUT
DD
C
0.1 µF
V
DD
4.7 kΩ–10 kΩ
0.1 µF
V
DD
4.7 kΩ–10 kΩ
0.1 µF
C
BYAD
0.1 µF
BY
V
V
V
V
V
V
V
REFH
DDAD
SSAD
REFL
DD
SS
SS
MC9S08GT16A
NOTE4
RESET
NOTE 3
IRQ
NOTE 3
PORT
A
PORT
B
PORT
C
PTA0/KBIP0
PTA1/KBIP1
PTA2/KBIP2
PTA3/KBIP3
PTA4/KBIP4
PTA5/KBIP5
PTA6/KBIP6
PTA7/KBIP7
PTB0/ADP0
PTB1/ADP1
PTB2/ADP2
PTB3/ADP3
PTB4/ADP4
PTB5/ADP5
PTB6/ADP6
PTB7/ADP7
PTC0/TxD2
PTC1/RxD2
PTC2/SDA
PTC3/SCL
PTC4
PTC5
PTC6
PTC7
I/O AND
PERIPHERAL
INTERFACE TO
APPLICATION
SYSTEM
PTD0/TPM1CLK/TPM1CH0
PTD1/TPM1CH1
PTD2/TPM1CH2
PTD3/TPM2CLK/TPM2CH0
PTD4/TPM2CH1
PTE0/TxD1
PTE1/RxD1
SS
PTE2/
PTE3/MISO
PTE4/MOSI
PTE5/SPSCK
NOTE 1
C1
X1
PTG0/BKDG/MS
PTG2/EXTAL
R
F
C2
PTG1/XTAL
PTG3
R
S
XTAL
EXTAL
PORT
G
PORT
D
PORT
E
NOTES:
1. Not required if using the internal oscillator option.
2. The 48-pin QFN has 2 V
3. RC filters on
RESET and IRQ are recommended for EMC-sensitive applications and systems.
pins (V
SS
SS1
and V
), both of which must be connected to GND.
SS2
Figure 2-5. Basic System Connections
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 27
Pins and Connections
2.3.1 VDD, VSS, V
DDAD
, V
SSAD
, V
REFH
, V
— Power and Voltage
REFL
References
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-µF tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-µF ceramic bypass capacitor located as close to the MCU power pins as
practical to suppress high-frequency noise.
NOTE
The 48-pin QFN version of the MC9S08GT16A/GT8A has two adjacent
pins. Both pins must be connected to ground with zero impedance
V
SS
between them.
V
DDAD
and V
the ATD. A 0.1-µF ceramic bypass capacitor should be located as close to the MCU power pins as practical
to suppress high-frequency noise.
REFH
and V
V
performance, they must be connected directly to V
are the analog power supply pins for the MCU. This voltage source supplies power to
SSAD
are the reference voltages for the analog-to-digital converter and for most accurate
REFL
DDAD
and V
with the shortest traces possible.
SSAD
2.3.2 PTG1/XTAL, PTG2/EXTAL — Oscillator
Immediately after reset, the MCU uses an internally generated clock (self-clocked mode — f
Self_reset
is approximately equivalent to an 8-MHz crystal rate. This frequency source is used during reset startup
and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay.
This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the
MCU. For more information on the ICG, see Chapter 9, “Internal Clock Generator (S08ICGV4).”
The oscillator amplitude on XTAL and EXTAL is gain limited for low-power oscillation. Typically, these
pins have a 1-V peak-to-peak signal. For noisy environments, the high gain output (HGO) bit can be set to
enable rail-to-rail oscillation.
The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in
either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or
ceramic resonator, an external oscillator can be connected to the EXTAL input pin, and the XTAL output
pin can be used as general I/O. The external oscillator amplitude must not exceed V
DD
.
Refer to Figure 2-5 for the following discussion. RS (when used) and RF should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
R
F
value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity
and lower values reduce gain and (in extreme cases) could prevent startup.
), that
MC9S08GT16A/GT8A Data Sheet, Rev. 1
28 Freescale Semiconductor
Pins and Connections
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C1 and C2 which are usually the same size. As a first-order approximation,
use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and
XTAL).
2.3.3 RESET — External Reset Pin
RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver,
and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
debug connector so a development system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for approximately 34 cycles of f
38 cycles of f
Self_reset
later. If reset was caused by an internal source such as low-voltage reset or watchdog
Self_reset
timeout, the circuitry expects the reset pin sample to return a logic 1. The reset circuitry decodes the cause
of reset and records it by setting a corresponding bit in the system control reset status register (SRS).
, released, and sampled again approximately
For EMC-sensitive applications, an external RC filter is recommended on the
RESET pin. See Figure 2-5
for an example.
2.3.4 PTG0/BKGD/MS — Background / Mode Select
The background/mode select (BKGD/MS) shares its function with an I/O port pin. While in reset, the pin
functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and
can be used for background debug communication. While functioning as a background/mode select pin,
the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew
rate control. When used as an I/O port (PTG0) the pin is limited to output only.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the maximum bus clock rate, so there should never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 29
Pins and Connections
2.3.5 IRQ — External Interrupt Request Pin
IRQ is a dedicated pin with both pullup and pulldown devices built in. This pin has no output capabilities.
After a system reset, the IRQ pin is disabled and must be enabled before use. See Section 5.4.2, “IRQ —
External Interrupt Request Pin” for more details.
For EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-5 for
an example.
2.3.6 General-Purpose I/O and Peripheral Ports
The remaining 36 pins are shared among general-purpose I/O and on-chip peripheral functions such as
timers and serial I/O systems. (Three of these pins are not bonded out on the 44-pin package, five are not
bonded out on the 42-pin package, and 15 are not bonded out on the 32-pin package.) Immediately after
reset, all 36 of these pins are configured as high-impedance general-purpose inputs with internal pullup
devices disabled.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unused pins to outputs so the pins do not
float.
For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate section from Table 2-1.
Table 2-1. Pin Sharing References
Port Pins Alternate Function
PTA7–PTA0 KBIP7–KBIP0 Chapter 7, “Keyboard Interrupt (S08KBIV1)”
PTB7–PTB0 ADP7–ADP0 Chapter 14, “Analog-to-Digital Converter (S08ATDV3)”
PTC7–PTC4
PTC3–PTC2 SCL–SDA Chapter 13, “Inter-Integrated Circuit (S08IICV1)”
PTC1–PTC0 RxD2–TxD2 Chapter 11, “Serial Communications Interface (S08SCIV1)”
PTD4–PTD3 TPM2CH1–TPM2CH0, TPM2CLK Chapter 10, “Timer/PWM (S08TPMV2)”
PTD2–PTD0 TPM1CH2–TPM1CH0, TPM1CLK Chapter 10, “Timer/PWM (S08TPMV2)”
PTE5
PTE4
PTE3
PTE2
PTE1–PTE0 RxD1–TxD1 Chapter 11, “Serial Communications Interface (S08SCIV1)”
PTG3
PTG2–PTG1 EXTAL–XTAL Chapter 9, “Internal Clock Generator (S08ICGV4)”
PTG0 BKGD/MS Chapter 15, “Development Support”
1
See this section for information about modules that share these pins.
SPSCK
MISO
MOSI
SS
Chapter 12, “Serial Peripheral Interface (S08SPIV3)”
Reference
1
MC9S08GT16A/GT8A Data Sheet, Rev. 1
30 Freescale Semiconductor
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