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MC9S08AW48
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Freescale MC9S08AW60, MC9S08AW48, MC9S08AW32, MC9S08AW16 Data Sheet

MC9S08AW60 MC9S08AW48 MC9S08AW32 MC9S08AW16
Advance Information Data Sheet
HCS08 Microcontrollers
MC9S08AW60 Rev.1.0 1/2006
freescale.com
8-Bit HCS08 Central Processor Unit (CPU)
• 40-MHz HCS08 CPU (central processor unit)
• 20-MHz internal bus frequency
• HC08 instruction set with added BGND instruction
• Single-wire background debug mode interface
• Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module)
• On-chip real-time in-circuit emulation (ICE) with two comparators (plus one in BDM), nine trigger modes, and on-chip bus capture buffer. Typically shows approximately 50 instructions before or after the trigger point.
• Support for up to 32 interrupt/reset sources
Memory Options
• Up to 60 KB of on-chip in-circuit programmable FLASH memory with block protection and security options
• Up to 2 KB of on-chip RAM
Clock Source Options
• Clock source options include crystal, resonator, external clock, or internally generated clock with precision NVM trimming
System Protection
• Optional computer operating properly (COP) reset
• Low-voltage detection with reset or interrupt
• Illegal opcode detection with reset
• Illegal address detection with reset (some devices don’t have illegal addresses)
Power-Saving Modes
• Wait plus two stops
• IIC — Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; capable of higher baudrates with reduced loading
• Timers — One 2-channel and one 6-channel 16-bit timer/pulse-width modulator (TPM) module: Selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centered PWM (CPWM) on all channels
• KBI — 8-pin keyboard interrupt module
Input/Output
• Up to 54 general-purpose input/output (I/O) pins
• Software selectable pullups on ports when used as inputs
• Software selectable slew rate control on ports when used as outputs
• Software selectable drive strength on ports when used as outputs
• Master reset pin and power-on reset (POR)
• Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost
Package Options:
MC9S08AW60/48/32
• 64-pin quad flat package (QFP)
• 64-pin low-profile quad flat package (LQFP)
• 48-pin low-profile quad flat package (QFN)
• 44-pin low-profile quad flat package (LQFP)
MC9S08AW16
• 48-pin low-profile quad flat package (QFN)
• 44-pin low-profile quad flat package (LQFP)
Peripherals
• ADC — 16-channel, 10-bit analog-to-digital converter with automatic compare function
• SCI — Two serial communications interface modules with optional 13-bit break
• SPI — Serial peripheral interface module
MC9S08AW60 Data Sheet, Rev.1.0
4 Freescale Semiconductor
MC9S08AW60
Advance Information Data Sheet
Covers MC9S08AW60
MC9S08AW48 MC9S08AW32 MC9S08AW16
MC9S08AW60
Rev.1.0
1/2006
This document contains information on a new product. Specifications and information herein are subject to change without notice.

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision
Number
1.0 1/30/2006 Initial external release.
Revision
Date
Description of Changes
This product incorporates SuperFlash® technology licensed from SST.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006. All rights reserved.
Chapters
Chapter 1 Introduction......................................................................................19
Chapter 2 Pins and Connections.....................................................................23
Chapter 3 Modes of Operation.........................................................................33
Chapter 4 Memory.............................................................................................39
Chapter 5 Resets, Interrupts, and System Configuration ............................. 63
Chapter 6 Parallel Input/Output ....................................................................... 79
Chapter 7 Central Processor Unit (S08CPUV2)............................................107
Chapter 8 Internal Clock Generator (S08ICGV4) .......................................... 127
Chapter 9 Keyboard Interrupt (S08KBIV1)....................................................155
Chapter 10 Timer/PWM (S08TPMV2) ............................................................... 163
Chapter 11 Serial Communications Interface (S08SCIV2).............................179
Chapter 12 Serial Peripheral Interface (S08SPIV3) ........................................ 197
Chapter 13 Inter-Integrated Circuit (S08IICV1) ............................................... 215
Chapter 14 Analog-to-Digital Converter (S08ADC10V1)................................ 231
Chapter 15 Development Support ................................................................... 257
Appendix A Electrical Characteristics and Timing Specifications ............... 279
Appendix B Ordering Information and Mechanical Drawings.......................305
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 7
Chapter 1
Introduction
1.1 Overview .........................................................................................................................................19
1.2 MCU Block Diagrams .....................................................................................................................19
1.3 System Clock Distribution ..............................................................................................................21
Chapter 2
Pins and Connections
2.1 Introduction .....................................................................................................................................23
2.2 Device Pin Assignment ...................................................................................................................24
2.3 Recommended System Connections ...............................................................................................26
2.3.1 Power (V
, 2 x VSS, V
DD
DDAD
, V
) .........................................................................28
SSAD
2.3.2 Oscillator (XTAL, EXTAL) ............................................................................................28
2.3.3
RESET ............................................................................................................................28
2.3.4 Background/Mode Select (BKGD/MS) .........................................................................29
2.3.5 ADC Reference Pins (V
REFH
, V
) ...........................................................................29
REFL
2.3.6 External Interrupt Pin (IRQ) ...........................................................................................29
2.3.7 General-Purpose I/O and Peripheral Ports .....................................................................30
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................33
3.2 Features ...........................................................................................................................................33
3.3 Run Mode ........................................................................................................................................33
3.4 Active Background Mode ................................................................................................................33
3.5 Wait Mode .......................................................................................................................................34
3.6 Stop Modes ......................................................................................................................................34
3.6.1 Stop2 Mode ....................................................................................................................35
3.6.2 Stop3 Mode ....................................................................................................................36
3.6.3 Active BDM Enabled in Stop Mode ...............................................................................36
3.6.4 LVD Enabled in Stop Mode ...........................................................................................37
3.6.5 On-Chip Peripheral Modules in Stop Modes .................................................................37
Chapter 4
Memory
4.1 MC9S08AW60/48/32/16 Memory Map ..........................................................................................39
4.1.1 Reset and Interrupt Vector Assignments ........................................................................42
4.2 Register Addresses and Bit Assignments ........................................................................................43
4.3 RAM ................................................................................................................................................49
4.4 FLASH ............................................................................................................................................49
4.4.1 Features ...........................................................................................................................50
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 9
4.4.2 Program and Erase Times ...............................................................................................50
4.4.3 Program and Erase Command Execution .......................................................................51
4.4.4 Burst Program Execution ...............................................................................................52
4.4.5 Access Errors ..................................................................................................................54
4.4.6 FLASH Block Protection ...............................................................................................54
4.4.7 Vector Redirection ..........................................................................................................55
4.5 Security ............................................................................................................................................55
4.6 FLASH Registers and Control Bits .................................................................................................57
4.6.1 FLASH Clock Divider Register (FCDIV) ......................................................................57
4.6.2 FLASH Options Register (FOPT and NVOPT) .............................................................58
4.6.3 FLASH Configuration Register (FCNFG) .....................................................................59
4.6.4 FLASH Protection Register (FPROT and NVPROT) ....................................................60
4.6.5 FLASH Status Register (FSTAT) ...................................................................................60
4.6.6 FLASH Command Register (FCMD) ............................................................................62
Chapter 5
Resets, Interrupts, and System Configuration
5.1 Introduction .....................................................................................................................................63
5.2 Features ...........................................................................................................................................63
5.3 MCU Reset ......................................................................................................................................63
5.4 Computer Operating Properly (COP) Watchdog .............................................................................64
5.5 Interrupts .........................................................................................................................................64
5.5.1 Interrupt Stack Frame .....................................................................................................65
5.5.2 External Interrupt Request (IRQ) Pin .............................................................................66
5.5.3 Interrupt Vectors, Sources, and Local Masks .................................................................67
5.6 Low-Voltage Detect (LVD) System ................................................................................................69
5.6.1 Power-On Reset Operation .............................................................................................69
5.6.2 LVD Reset Operation .....................................................................................................69
5.6.3 LVD Interrupt Operation ................................................................................................69
5.6.4 Low-Voltage Warning (LVW) ........................................................................................69
5.7 Real-Time Interrupt (RTI) ...............................................................................................................69
5.8 MCLK Output .................................................................................................................................70
5.9 Reset, Interrupt, and System Control Registers and Control Bits ...................................................70
5.9.1 Interrupt Pin Request Status and Control Register (IRQSC) .........................................71
5.9.2 System Reset Status Register (SRS) ...............................................................................72
5.9.3 System Background Debug Force Reset Register (SBDFR) ..........................................73
5.9.4 System Options Register (SOPT) ...................................................................................73
5.9.5 System MCLK Control Register (SMCLK) ...................................................................74
5.9.6 System Device Identification Register (SDIDH, SDIDL) ..............................................75
5.9.7 System Real-Time Interrupt Status and Control Register (SRTISC) .............................76
5.9.8 System Power Management Status and Control 1 Register (SPMSC1) .........................77
5.9.9 System Power Management Status and Control 2 Register (SPMSC2) .........................78
MC9S08AW60 Data Sheet, Rev.1.0
10 Freescale Semiconductor
Chapter 6
Parallel Input/Output
6.1 Introduction .....................................................................................................................................79
6.2 Features ...........................................................................................................................................79
6.3 Pin Descriptions ..............................................................................................................................80
6.3.1 Port A ..............................................................................................................................80
6.3.2 Port B ..............................................................................................................................80
6.3.3 Port C ..............................................................................................................................81
6.3.4 Port D ..............................................................................................................................81
6.3.5 Port E ..............................................................................................................................82
6.3.6 Port F ..............................................................................................................................83
6.3.7 Port G ..............................................................................................................................83
6.4 Parallel I/O Control .........................................................................................................................84
6.5 Pin Control ......................................................................................................................................85
6.5.1 Internal Pullup Enable ....................................................................................................85
6.5.2 Output Slew Rate Control Enable ..................................................................................85
6.5.3 Output Drive Strength Select ..........................................................................................85
6.6 Pin Behavior in Stop Modes ............................................................................................................86
6.7 Parallel I/O and Pin Control Registers ............................................................................................86
6.7.1 Port A I/O Registers (PTAD and PTADD) .....................................................................86
6.7.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) ..............................................87
6.7.3 Port B I/O Registers (PTBD and PTBDD) .....................................................................89
6.7.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) ..............................................90
6.7.5 Port C I/O Registers (PTCD and PTCDD) .....................................................................92
6.7.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) ..............................................93
6.7.7 Port D I/O Registers (PTDD and PTDDD) ....................................................................95
6.7.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) .............................................96
6.7.9 Port E I/O Registers (PTED and PTEDD) ......................................................................98
6.7.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) ...............................................99
6.7.11 Port F I/O Registers (PTFD and PTFDD) ....................................................................101
6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) ..............................................102
6.7.13 Port G I/O Registers (PTGD and PTGDD) ..................................................................104
6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ...........................................105
Chapter 7
Central Processor Unit (S08CPUV2)
7.1 Introduction ...................................................................................................................................107
7.1.1 Features .........................................................................................................................107
7.2 Programmer’s Model and CPU Registers .....................................................................................108
7.2.1 Accumulator (A) ...........................................................................................................108
7.2.2 Index Register (H:X) ....................................................................................................108
7.2.3 Stack Pointer (SP) .........................................................................................................109
7.2.4 Program Counter (PC) ..................................................................................................109
7.2.5 Condition Code Register (CCR) ...................................................................................109
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 11
7.3 Addressing Modes .........................................................................................................................110
7.3.1 Inherent Addressing Mode (INH) ................................................................................111
7.3.2 Relative Addressing Mode (REL) ................................................................................111
7.3.3 Immediate Addressing Mode (IMM) ...........................................................................111
7.3.4 Direct Addressing Mode (DIR) ....................................................................................111
7.3.5 Extended Addressing Mode (EXT) ..............................................................................111
7.3.6 Indexed Addressing Mode ............................................................................................111
7.4 Special Operations .........................................................................................................................112
7.4.1 Reset Sequence .............................................................................................................113
7.4.2 Interrupt Sequence ........................................................................................................113
7.4.3 Wait Mode Operation ...................................................................................................114
7.4.4 Stop Mode Operation ...................................................................................................114
7.4.5 BGND Instruction ........................................................................................................114
7.5 HCS08 Instruction Set Summary ..................................................................................................115
Chapter 8
Internal Clock Generator (S08ICGV4)
8.1 Introduction ...................................................................................................................................129
8.1.1 Features .........................................................................................................................130
8.1.2 Modes of Operation ......................................................................................................130
8.2 External Signal Description ..........................................................................................................131
8.2.1 EXTAL — External Reference Clock / Oscillator Input ..............................................131
8.2.2 XTAL — Oscillator Output ..........................................................................................131
8.2.3 External Clock Connections .........................................................................................131
8.2.4 External Crystal/Resonator Connections ......................................................................132
8.3 Register Definition ........................................................................................................................132
8.3.1 ICG Control Register 1 (ICGC1) .................................................................................133
8.3.2 ICG Control Register 2 (ICGC2) .................................................................................135
8.3.3 ICG Status Register 1 (ICGS1) ....................................................................................136
8.3.4 ICG Status Register 2 (ICGS2) ....................................................................................137
8.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ...............................................................137
8.3.6 ICG Trim Register (ICGTRM) .....................................................................................138
8.4 Functional Description ..................................................................................................................138
8.4.1 Off Mode (Off) .............................................................................................................139
8.4.2 Self-Clocked Mode (SCM) ...........................................................................................139
8.4.3 FLL Engaged, Internal Clock (FEI) Mode ...................................................................140
8.4.4 FLL Engaged Internal Unlocked ..................................................................................141
8.4.5 FLL Engaged Internal Locked ......................................................................................141
8.4.6 FLL Bypassed, External Clock (FBE) Mode ...............................................................141
8.4.7 FLL Engaged, External Clock (FEE) Mode .................................................................141
8.4.8 FLL Lock and Loss-of-Lock Detection ........................................................................142
8.4.9 FLL Loss-of-Clock Detection ......................................................................................143
8.4.10 Clock Mode Requirements ...........................................................................................144
8.4.11 Fixed Frequency Clock .................................................................................................145
8.4.12 High Gain Oscillator .....................................................................................................145
MC9S08AW60 Data Sheet, Rev.1.0
12 Freescale Semiconductor
8.5 Initialization/Application Information ..........................................................................................145
8.5.1 Introduction ..................................................................................................................145
8.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ........................147
8.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ............................149
8.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ....................151
8.5.5 Example #4: Internal Clock Generator Trim ................................................................153
Chapter 9
Keyboard Interrupt (S08KBIV1)
9.1 Introduction ...................................................................................................................................155
9.2 Keyboard Pin Sharing ....................................................................................................................155
9.3 Features .........................................................................................................................................156
9.3.1 KBI Block Diagram ......................................................................................................158
9.4 Register Definition ........................................................................................................................158
9.4.1 KBI Status and Control Register (KBI1SC) .................................................................159
9.4.2 KBI Pin Enable Register (KBI1PE) .............................................................................160
9.5 Functional Description ..................................................................................................................160
9.5.1 Pin Enables ...................................................................................................................160
9.5.2 Edge and Level Sensitivity ...........................................................................................160
9.5.3 KBI Interrupt Controls .................................................................................................161
Chapter 10
Timer/PWM (S08TPMV2)
10.1 Introduction ...................................................................................................................................163
10.2 Features .........................................................................................................................................163
10.2.1 Block Diagram ..............................................................................................................165
10.3 External Signal Description ..........................................................................................................166
10.3.1 External TPM Clock Sources .......................................................................................166
10.3.2 TPMxCHn — TPMx Channel n I/O Pins .....................................................................166
10.4 Register Definition ........................................................................................................................166
10.4.1 Timer x Status and Control Register (TPMxSC) ..........................................................167
10.4.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) .............................................168
10.4.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) .............................169
10.4.4 Timer x Channel n Status and Control Register (TPMxCnSC) ....................................170
10.4.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ....................................171
10.5 Functional Description ..................................................................................................................172
10.5.1 Counter .........................................................................................................................172
10.5.2 Channel Mode Selection ...............................................................................................173
10.5.3 Center-Aligned PWM Mode ........................................................................................175
10.6 TPM Interrupts ..............................................................................................................................176
10.6.1 Clearing Timer Interrupt Flags .....................................................................................176
10.6.2 Timer Overflow Interrupt Description ..........................................................................176
10.6.3 Channel Event Interrupt Description ............................................................................177
10.6.4 PWM End-of-Duty-Cycle Events .................................................................................177
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 13
Chapter 11
Serial Communications Interface (S08SCIV2)
11.1 Introduction ...................................................................................................................................179
11.1.1 Features .........................................................................................................................181
11.1.2 Modes of Operation ......................................................................................................181
11.1.3 Block Diagram ..............................................................................................................182
11.2 Register Definition ........................................................................................................................184
11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) ........................................................184
11.2.2 SCI Control Register 1 (SCIxC1) .................................................................................185
11.2.3 SCI Control Register 2 (SCIxC2) .................................................................................186
11.2.4 SCI Status Register 1 (SCIxS1) ....................................................................................187
11.2.5 SCI Status Register 2 (SCIxS2) ....................................................................................189
11.2.6 SCI Control Register 3 (SCIxC3) .................................................................................189
11.2.7 SCI Data Register (SCIxD) ..........................................................................................190
11.3 Functional Description ..................................................................................................................191
11.3.1 Baud Rate Generation ...................................................................................................191
11.3.2 Transmitter Functional Description ..............................................................................191
11.3.3 Receiver Functional Description ..................................................................................193
11.3.4 Interrupts and Status Flags ...........................................................................................194
11.4 Additional SCI Functions ..............................................................................................................195
11.4.1 8- and 9-Bit Data Modes ..............................................................................................195
11.4.2 Stop Mode Operation ...................................................................................................196
11.4.3 Loop Mode ...................................................................................................................196
11.4.4 Single-Wire Operation ..................................................................................................196
Chapter 12
Serial Peripheral Interface (S08SPIV3)
12.1 Introduction ...................................................................................................................................199
12.1.1 Features .........................................................................................................................200
12.1.2 Block Diagrams ............................................................................................................200
12.1.3 SPI Baud Rate Generation ............................................................................................202
12.2 External Signal Description ..........................................................................................................203
12.2.1 SPSCK — SPI Serial Clock .........................................................................................203
12.2.2 MOSI — Master Data Out, Slave Data In ....................................................................203
12.2.3 MISO — Master Data In, Slave Data Out ....................................................................203
12.2.4
12.3 Register Definition ........................................................................................................................204
12.3.1 SPI Control Register 1 (SPI1C1) ..................................................................................204
12.3.2 SPI Control Register 2 (SPI1C2) ..................................................................................205
12.3.3 SPI Baud Rate Register (SPI1BR) ...............................................................................206
12.3.4 SPI Status Register (SPI1S) ..........................................................................................207
12.3.5 SPI Data Register (SPI1D) ...........................................................................................208
12.4 Functional Description ..................................................................................................................208
12.4.1 SPI Clock Formats ........................................................................................................209
12.4.2 SPI Interrupts ................................................................................................................211
SS — Slave Select ........................................................................................................203
MC9S08AW60 Data Sheet, Rev.1.0
14 Freescale Semiconductor
12.4.3 Mode Fault Detection ...................................................................................................212
12.5 Initialization/Application Information ..........................................................................................212
12.5.1 SPI Module Initialization Example ..............................................................................212
Chapter 13
Inter-Integrated Circuit (S08IICV1)
13.1 Introduction ...................................................................................................................................215
13.1.1 Features .........................................................................................................................217
13.1.2 Modes of Operation ......................................................................................................217
13.1.3 Block Diagram ..............................................................................................................218
13.2 External Signal Description ..........................................................................................................218
13.2.1 SCL — Serial Clock Line .............................................................................................218
13.2.2 SDA — Serial Data Line ..............................................................................................218
13.3 Register Definition ........................................................................................................................218
13.3.1 IIC Address Register (IIC1A) .......................................................................................219
13.3.2 IIC Frequency Divider Register (IIC1F) ......................................................................219
13.3.3 IIC Control Register (IIC1C) ........................................................................................222
13.3.4 IIC Status Register (IIC1S) ..........................................................................................223
13.3.5 IIC Data I/O Register (IIC1D) ......................................................................................224
13.4 Functional Description ..................................................................................................................225
13.4.1 IIC Protocol ..................................................................................................................225
13.5 Resets ............................................................................................................................................228
13.6 Interrupts .......................................................................................................................................228
13.6.1 Byte Transfer Interrupt .................................................................................................229
13.6.2 Address Detect Interrupt ...............................................................................................229
13.6.3 Arbitration Lost Interrupt .............................................................................................229
Chapter 14
Analog-to-Digital Converter (S08ADC10V1)
14.1 Overview .......................................................................................................................................231
14.2 Channel Assignments ....................................................................................................................231
14.2.1 Alternate Clock .............................................................................................................232
14.2.2 Hardware Trigger ..........................................................................................................232
14.2.3 Features .........................................................................................................................234
14.2.4 Block Diagram ..............................................................................................................234
14.3 External Signal Description ..........................................................................................................235
14.3.1 Analog Power (V
14.3.2 Analog Ground (V
14.3.3 Voltage Reference High (V
14.3.4 Voltage Reference Low (V
14.3.5 Analog Channel Inputs (ADx) ......................................................................................236
14.4 Register Definition ........................................................................................................................236
14.4.1 Status and Control Register 1 (ADC1SC1) ..................................................................236
14.4.2 Status and Control Register 2 (ADC1SC2) ..................................................................238
14.4.3 Data Result High Register (ADC1RH) ........................................................................239
) ................................................................................................236
DDAD
) ..............................................................................................236
SSAD
) .................................................................................236
REFH
) ..................................................................................236
REFL
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 15
14.4.4 Data Result Low Register (ADC1RL) ..........................................................................239
14.4.5 Compare Value High Register (ADC1CVH) ................................................................240
14.4.6 Compare Value Low Register (ADC1CVL) .................................................................240
14.4.7 Configuration Register (ADC1CFG) ............................................................................240
14.4.8 Pin Control 1 Register (APCTL1) ................................................................................242
14.4.9 Pin Control 2 Register (APCTL2) ................................................................................243
14.4.10 Pin Control 3 Register (APCTL3) ................................................................................244
14.5 Functional Description ..................................................................................................................245
14.5.1 Clock Select and Divide Control ..................................................................................245
14.5.2 Input Select and Pin Control .........................................................................................246
14.5.3 Hardware Trigger ..........................................................................................................246
14.5.4 Conversion Control .......................................................................................................246
14.5.5 Automatic Compare Function ......................................................................................249
14.5.6 MCU Wait Mode Operation .........................................................................................249
14.5.7 MCU Stop3 Mode Operation .......................................................................................249
14.5.8 MCU Stop1 and Stop2 Mode Operation ......................................................................250
14.6 Initialization Information ..............................................................................................................250
14.6.1 ADC Module Initialization Example ...........................................................................250
14.7 Application Information ................................................................................................................252
14.7.1 External Pins and Routing ............................................................................................252
14.7.2 Sources of Error ............................................................................................................254
Chapter 15
Development Support
15.1 Introduction ...................................................................................................................................257
15.1.1 Features .........................................................................................................................257
15.2 Background Debug Controller (BDC) ..........................................................................................258
15.2.1 BKGD Pin Description .................................................................................................258
15.2.2 Communication Details ................................................................................................259
15.2.3 BDC Commands ...........................................................................................................263
15.2.4 BDC Hardware Breakpoint ..........................................................................................265
15.3 On-Chip Debug System (DBG) ....................................................................................................266
15.3.1 Comparators A and B ...................................................................................................266
15.3.2 Bus Capture Information and FIFO Operation .............................................................266
15.3.3 Change-of-Flow Information ........................................................................................267
15.3.4 Tag vs. Force Breakpoints and Triggers .......................................................................267
15.3.5 Trigger Modes ..............................................................................................................268
15.3.6 Hardware Breakpoints ..................................................................................................270
15.4 Register Definition ........................................................................................................................270
15.4.1 BDC Registers and Control Bits ...................................................................................270
15.4.2 System Background Debug Force Reset Register (SBDFR) ........................................272
15.4.3 DBG Registers and Control Bits ..................................................................................273
MC9S08AW60 Data Sheet, Rev.1.0
16 Freescale Semiconductor
Appendix A
Electrical Characteristics and Timing Specifications
A.1 Introduction ....................................................................................................................................279
A.2 Parameter Classification.................................................................................................................279
A.3 Absolute Maximum Ratings...........................................................................................................279
A.4 Thermal Characteristics..................................................................................................................281
A.5 ESD Protection and Latch-Up Immunity .......................................................................................282
A.6 DC Characteristics..........................................................................................................................283
A.7 Supply Current Characteristics.......................................................................................................287
A.8 ADC Characteristics.......................................................................................................................289
A.9 Internal Clock Generation Module Characteristics........................................................................292
A.9.1 ICG Frequency Specifications.......................................................................................293
A.10 AC Characteristics..........................................................................................................................295
A.10.1 Control Timing..............................................................................................................295
A.10.2 Timer/PWM (TPM) Module Timing.............................................................................296
A.11 SPI Characteristics .........................................................................................................................298
A.12 FLASH Specifications....................................................................................................................301
A.13 EMC Performance..........................................................................................................................302
A.13.1 Radiated Emissions .......................................................................................................302
A.13.2 Conducted Transient Susceptibility...............................................................................302
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information .....................................................................................................................305
B.2 Orderable Part Numbering System ................................................................................................305
B.3 Mechanical Drawings.....................................................................................................................305
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 17
MC9S08AW60 Data Sheet, Rev.1.0
18 Freescale Semiconductor

Chapter 1 Introduction

1.1 Overview

The MC9S08AW60, MC9S08AW48, MC9S08AW32, and MC9S08AW16 are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for memory sizes and package types.
Table 1-2 summarizes the peripheral availability per package type for the devices available in the
MC9S08AW60/48/32/16 series.
Table 1-1. Devices in the MC9S08AW60/48/32/16 Series
Device FLASH RAM Package
MC9S08AW60 63,280
MC9S08AW48 49,152
MC9S08AW32 32,768
MC9S08AW16 16,384 1024
Table 1-2. Peripherals Available per Package Type
2048
Package Options
64 QFP
64 LQFP
48 QFN
44 LQFP
Feature 64-pin 48-pin 44-pin
ADC 16-ch 8-ch 8-ch
IIC yes yes yes
IRQ yes yes yes
KBI1 8 7 6
SCI1 yes yes yes
SCI2 yes yes yes
SPI1 yes yes yes
TPM1 6-ch 4-ch 4-ch
TPM1CLK yes no no
TPM2 2-ch 2-ch 2-ch
TPM2CLK yes no no
I/O pins 54 38 34

1.2 MCU Block Diagrams

The block diagram shows the structure of the MC9S08AW60/48/32/16 MCU.
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 19
Chapter 1 Introduction
BKGD/MS
RESET
IRQ
V
DDAD
V
SSAD
V
REFL
V
REFH
V
DD
V
SS
NOTES:
HCS08 CORE
BDC
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
USER FLASH
(AW60 = 63,280 BYTES) (AW48 = 49,152 BYTES) (AW32 = 32,768 BYTES) (AW16 = 16,384 BYTES)
USER RAM
AW60/48/32 = 2048 BYTES
AW16 = 1024 BYTES
INTERNAL CLOCK
GENERATOR (ICG)
LOW-POWER OSCILLATOR
VOLTAGE
REGULATOR
CPU
DEBUG
MODULE (DBG)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI2)
IIC MODULE (IIC1)
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC1)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
6-CHANNEL TIMER/PWM
MODULE (TPM1)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI1)
2-CHANNEL TIMER/PWM
MODULE (TPM2)
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
RxD2
TxD2
SDA1
SCL1
AD1P7–AD1P0
8
AD1P15–AD1P8
SPSCK1
MOSI1
MISO1
SS1
TPM1CLK
TPM1CH5– TPM1CH0
RxD1 TxD1
TPM2CLK
TPM2CH1–TPM2CH0
KBI1P7–KBI1P5
KBI1P4–KBI1P0
EXTAL
XTAL
1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1)
3. IRQ does not have a clamp diode to V
4. Pin contains integrated pullup device.
. IRQ should not be driven above VDD.
DD
5. Pins PTD7, PTD3, PTD2, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1).
8
PTA7– PTA0
PORT A
8
PTB7/AD1P7–
PORT B
PORT C
8
PORT D
6
2
3
5
PORT E
PORT F
PORT G
PTB0/AD1P0
PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK
PTC1/SDA1
PTC0/SCL1
PTD7/AD1P15/KBI1P7 PTD6/AD1P14/TPM1CLK PTD5/AD1P13 PTD4/AD1P12/TPM2CLK PTD3/AD1P11/KBI1P6 PTD2/AD1P10/KBI1P5 PTD1/AD1P9 PTD0/AD1P8
PTE7/SPSCK1
PTE6/MOSI1
PTE5/MISO1
PTE4/SS1
PTE3/TPM1CH1
PTE2/TPM1CH0
PTE1/RxD1
PTE0/TxD1
PTF7 PTF6
PTF5/TPM2CH1 PTF4/TPM2CH0
PTF3/TPM1CH5 PTF2/TPM1CH4
PTF1/TPM1CH3 PTF0/TPM1CH2
PTG6/EXTAL PTG5/XTAL
PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0
Figure 1-1. MC9S08AW60/48/32/16 Block Diagram
MC9S08AW60 Data Sheet, Rev.1.0
20 Freescale Semiconductor
Table 1-3 lists the functional versions of the on-chip modules.
Table 1-3. Versions of On-Chip Modules
Module Version
Analog-to-Digital Converter (ADC) 1
Internal Clock Generator (ICG) 4
Inter-Integrated Circuit (IIC) 1
Keyboard Interrupt (KBI) 1
Serial Communications Interface (SCI) 2
Serial Peripheral Interface (SPI) 3
Timer Pulse-Width Modulator (TPM) 2
Central Processing Unit (CPU) 2
Debug Module (DBG) 2

1.3 System Clock Distribution

Chapter 1 Introduction
ICG
ICGERCLK
FFE
SYSTEM
CONTROL
LOGIC
RTI
TPM1 TPM2 IIC1 SCI1 SCI2 SPI1
÷2
FIXED FREQ CLOCK (XCLK)
ICGOUT
ICGLCLK*
* ICGLCLK is the alternate BDC clock source for the MC9S08AW60/48/32/16.
÷2
CPU
BUSCLK
BDC
Figure 1-2. System Clock Distribution Diagram
ADC1
ADC has min and max frequency requirements. See Chapter 14,
“Analog-to-Digital Converter (S08ADC10V1) and Appendix A, “Electrical Characteristics and Timing Specifications
RAM FLASH
FLASH has frequency requirements for program and erase operation. See Appendix A, “Electrical
Characteristics and Timing Specifications.
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 21
Chapter 1 Introduction
Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock connection diagram. The ICG supplies the clock sources:
• ICGOUT is an output of the ICG module. It is one of the following: — The external crystal oscillator — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop
sub-module
— Control bits inside the ICG determine which source is connected.
• FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be ICGERCLK/2. Otherwise the fixed-frequency clock will be BUSCLK.
• ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow.
• ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. Can also be used as the ALTCLK input to the ADC module.
MC9S08AW60 Data Sheet, Rev.1.0
22 Freescale Semiconductor

Chapter 2 Pins and Connections

2.1 Introduction

This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals.
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 23
Chapter 2 Pins and Connections

2.2 Device Pin Assignment

PTC4
IRQ
RESET
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF2/TPM1CH4
PTF3/TPM1CH5
PTF4/TPM2CH0
PTC6
PTF7
PTF5/TPM2CH1
PTF6
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
1
PTC5/RxD2
64
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PTC3/TxD2
PTC2/MCLK
63 62 61
PTC1/SDA1
PTC0/SCL1
59
60
SS
PTG6/EXTAL
V
57
58
64-Pin QFP
64-Pin LQFP
PTG5/XTAL
BKGD/MS
56
REFL
V
REFH
V
PTD6/TPM1CLK/AD1P14
PTD7/KBI1P7/AD1P15
PTD5/AD1P13
PTD4/TPM2CLK/AD1P12
PTG4/KBI1P4
49
505152535455
47
46
45
44
43
42
41
40
39
38
37
36
35
34
PTG3/KBI1P3
48
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
V
SSAD
V
DDAD
PTD1/AD1P9
PTD0/AD1P8
PTB7/AD1P7
PTB6/AD1P6
PTB5/AD1P5
PTB4/AD1P4
PTB3/AD1P3
PTB2/AD1P2
PTB1/AD1P1
PTB0/AD1P0
PTE3/TPM1CH1
16
17
18
PTE4/SS1
19
20 21 22
PTE6/MOSI1
PTE5/MISO1
PTE7/SPSCK1
23
DD
SS
V
V
PTG1/KBI1P1
PTG0/KBI1P0
27
26
PTA024PTA125PTA2
PTG2/KBI1P2
28 29 30 31
PTA4
PTA3
32
PTA5
PTA6
PTA7
33
Figure 2-1. MC9S08AW60/48/32/16 in 64-Pin QFP/LQFP Package
MC9S08AW60 Data Sheet, Rev.1.0
24 Freescale Semiconductor
PTC4
IRQ
RESET
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF4/TPM2CH0
PTF5/TPM2CH1
PTF6
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
1
2
3
4
5
6
7
8
9
10
11
12
PTC5/RxD2
PTC3/TxD2
47
48
14
13
PTE4/SS1
PTE5/MISO1
PTC1/SDA1
PTC2/MCLK
46
45
15
16
PTE6/MOSI1
PTE7/SPSCK1
SS
PTG6/EXTAL
V
PTC0/SCL1
44
43
42
48-Pin QFN
17
18
19
SS
DD
V
V
PTG0/KBI1P0
PTG5/XTAL
BKGD/MS
41
40
20
21
PTG2/KBI1P2
PTG1/KBI1P1
22
PTA0
REFL
V
39
V
38
23
PTA1
REFH
Chapter 2 Pins and Connections
PTG4/KB1IP4
37
PTG3/KBI1P3
36
PTD3/KBI1P6/AD1P11
35
PTD2/KBI1P5/AD1P10
34
V
33
SSAD
V
32
DDAD
PTD1/AD1P9
31
PTD0/AD1P8
30
PTB3/AD1P3
29
PTB2/AD1P2
28
27
PTB1/AD1P1
PTB0/AD1P0
26
PTA7
25
24
PTA2
Figure 2-2. MC9S08AW60/48/32/16 in 48-Pin QFN Package
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 25
Chapter 2 Pins and Connections
PTC4
IRQ
RESET
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF4/TPM2CH0
PTF5/TPM2CH1
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
11
1
PTC5/RxD2
44
2
3
4
5
6
7
8
9
10
12
PTE4/SS1
PTC3/TxD2
PTC2/MCLK
43 42 41
14
13
PTE6/MOSI1
PTE5/MISO1
PTC0/SCL1
PTC1/SDA1
40
44-Pin LQFP
15 16 17
SS
V
PTE7/SPSCK1
SS
V
39
DD
V
PTG6/EXTAL
PTG5/XTAL
37
38
18
PTG1/KBI1P1
PTG0/KBI1P0
REFL
BKGD/MS
V
35
36
20 21
PTA019PTA1
PTG2/KBI1P2
REFH
V
34
PTG3/KBI1P3
33
32
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
31
V
30
29
28
27
26
25
24
22
SSAD
V
DDAD
PTD1/AD1P9
PTD0/AD1P8
PTB3/AD1P3
PTB2/AD1P2
PTB1/AD1P1
PTB0/AD1P0
23
Figure 2-3. MC9S08AW60/48/32/16 in 44-Pin LQFP Package

2.3 Recommended System Connections

Figure 2-4 shows pin connections that are common to almost all MC9S08AW60/48/32/16 application
systems.
MC9S08AW60 Data Sheet, Rev.1.0
26 Freescale Semiconductor
SYSTEM POWER
5 V
Chapter 2 Pins and Connections
V
REFH
DDAD
SSAD
REFL
DD
MC9S08AW60
PORT
A
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
C
BYAD
0.1 µF
V
V
DD
+
C
BLK
10 µF
+
C
BY
0.1 µF
V
V
V
VSS(x2)
PTA7
V
DD
NOTES:
1. Not required if using the internal clock option.
2. These are the same pins as PTG5 and PTG6
3. RC filters on RESET and IRQ are recommended for EMC-sensitive applications.
NOTE 1
C1
X1
BACKGROUND HEADER
OPTIONAL
MANUAL
RESET
ASYNCHRONOUS
INTERRUPT
INPUT
R
F
C2
1
V
DD
4.7 kΩ–10 kΩ
0.1 µF
PTG0/KBI1P0
PTG1/KBI1P1
PTG2/KBI1P2
PTG3/KBI1P3
PTG4/KBI1P4
PTG5/XTAL
PTG6/EXTAL
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF2/TPM1CH4
PTF3/TPM1CH5
PTF4/TPM2CH0
PTF5/TPM2CH1
PTF6
PTF7
R
S
XTAL NOTE 2
EXTAL NOTE 2
PORT
B
PTB0/AD1P0
PTB1/AD1P1
PTB2/AD1P2
PTB3/AD1P3
PTB4/AD1P4
PTB5/AD1P5
I/O AND
PERIPHERAL
INTERFACE TO
APPLICATION
SYSTEM
V
DD
4.7 kΩ– 10 kΩ
BKGD/MS
RESET NOTE 3
PORT
C
PTB6/AD1P6
PTB7/AD1P7
PTC0/SCL1
PTC1/SDA1
PTC2/MCLK
PTC3/TxD2
PTC4
PTC5/RxD2
PTC6
IRQ
0.1 µF
NOTE 3
PTD0/AD1P8
PTD1/AD1P9
PTD2/AD1P10/KBI1P5
PORT
G
PORT
D
PTD3/AD1P11/KBI1P6
PTD4/AD1P12/TPM2CLK
PTD5/AD1P13
PTD6/AD1P14/TPM1CLK
PTD7/AD1P15/KBI1P7
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PORT
F
PORT
E
PTE3/TPM1CH1
PTE4/
SS1
PTE5/MISO1
PTE6/MOSI1
PTE7/SPSCK1
Figure 2-4. Basic System Connections
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 27
Chapter 2 Pins and Connections
2.3.1 Power (VDD, 2 x VSS, V
DDAD
, V
SSAD
)
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-µF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-µF ceramic bypass capacitor located as near to the paired V
DD
and V
SS
power pins as practical to suppress high-frequency noise. The MC9S08AW60 has a second VSSpin. This pin should be connected to the system ground plane or to the primary V
pin through a low-impedance
SS
connection.
V
DDAD
and V
are the analog power supply pins for the MCU. This voltage source supplies power to
SSAD
the ADC module. A 0.1-µF ceramic bypass capacitor should be located as near to the analog power pins as practical to suppress high-frequency noise.

2.3.2 Oscillator (XTAL, EXTAL)

Out of reset the MCU uses an internally generated clock (self-clocked mode — f
Self_reset
about 8-MHz crystal rate. This frequency source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information on the ICG, see the Chapter 8, “Internal Clock Generator (S08ICGV4).”
) equivalent to
The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin.
Refer to Figure 2-4 for the following discussion. R
(when used) and RF should be low-inductance
S
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications.
is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
R
F
value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 which are usually the same size. As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL).

2.3.3 RESET

RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
MC9S08AW60 Data Sheet, Rev.1.0
28 Freescale Semiconductor
Chapter 2 Pins and Connections
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for approximately 34 bus cycles, released, and sampled again approximately 38 bus cycles later. If reset was caused by an internal source such as low-voltage reset or watchdog timeout, the circuitry expects the reset pin sample to return a logic 1. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (SRS).
In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-4 for an example.

2.3.4 Background/Mode Select (BKGD/MS)

While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and can be used for background debug communication. While functioning as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin.
2.3.5 ADC Reference Pins (V
The V
REFH
and V
pins are the voltage reference high and voltage reference low inputs respectively
REFL
REFH
, V
REFL
)
for the ADC module.

2.3.6 External Interrupt Pin (IRQ)

The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions. If the IRQ function is not enabled, this pin does not perform any function.
When IRQ is configured as the IRQ input and is set to detect rising edges, a pulldown device rather than a pullup device is enabled.
In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-4 for an example.
MC9S08AW60 Data Sheet, Rev.1.0
Freescale Semiconductor 29
Chapter 2 Pins and Connections

2.3.7 General-Purpose I/O and Peripheral Ports

The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and serial I/O systems. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled.
NOTE
To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float.
For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate chapter from Table 2-1.
Table 2-1. Pin Sharing Priority
Lowest <- Pin Function Priority -> Highest
Port Pins Alternate Function Alternate Function
PTB7–PTB0 AD1P7–AD1P0 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)”
PTC5, PTC3 RxD2–TxD2 Chapter 11, “Serial Communications Interface (S08SCIV2)”
PTC2 MCLK Chapter 5, “Resets, Interrupts, and System Configuration”
PTC1–PTC0 SCL1–SDA1 Chapter 13, “Inter-Integrated Circuit (S08IICV1)”
PTD7 KBI1P7 AD1P15 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)”
Chapter 9, “Keyboard Interrupt (S08KBIV1)”
PTD6 TPM1CLK AD1P14 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)”
Chapter 10, “Timer/PWM (S08TPMV2)”
PTD5 AD1P13 AD1P13 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)”
PTD4 TPM2CLK AD1P12 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)”
Chapter 10, “Timer/PWM (S08TPMV2)”
PTD3–PTD2 KBI1P6–KBI1P5 AD1P11–AD1P10 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)”
Chapter 9, “Keyboard Interrupt (S08KBIV1)”
PTD1–PTD0 AD1P9–AD1P8 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)”
PTE7 PTE6 PTE5 PTE4
PTE3–PTE2 TPM1CH1–
PTE1–PTE0 RxD1–TxD1 Chapter 11, “Serial Communications Interface (S08SCIV2)”
PTF5–PTF4 TPM2CH1–
PTF3–PTF0 TPM1CH5–
PTG4–PTG0 KBI1P4–KBI1P0 Chapter 9, “Keyboard Interrupt (S08KBIV1)”
PTG6–PTG5 EXTAL–XTAL Chapter 8, “Internal Clock Generator (S08ICGV4)”
1
See the listed chapter for information about modules that share these pins.
SPSCK1 MOSI1 MISO1 SS1
TPM1CH0
TPM2CH0
TPM1CH2
Chapter 12, “Serial Peripheral Interface (S08SPIV3)”
Chapter 10, “Timer/PWM (S08TPMV2)”
Chapter 10, “Timer/PWM (S08TPMV2)”
Chapter 10, “Timer/PWM (S08TPMV2)”
Reference
1
MC9S08AW60 Data Sheet, Rev.1.0
30 Freescale Semiconductor
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