MC9S08AC60
MC9S08AC48
MC9S08AC32
Data Sheet
HCS08
Microcontrollers
MC9S08AC60
Rev. 2
3/2008
freescale.com
MC9S08AC60 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
• 40-MHz HCS08 CPU (central processor unit)
• 20-MHz internal bus frequency
• HC08 instruction set with added BGND instruction
Development Support
• Background debugging system
• Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
• On-chip in-circuit emulator (ICE) Debug module
containing two comparators and nine trigger
modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data.
Supports both tag and force breakpoints.
• Support for up to 32 interrupt/reset sources
Memory Options
• Up to 60 KB of on-chip FLASH memory with
security options
• Up to 2 KB of on-chip RAM
Clock Source Options
• Clock source options include crystal, resonator,
external clock, or internally generated clock with
precision NVM trimming using ICG module
System Protection
• Optional watchdog computer operating properly
(COP) reset with option to run from independent
1kHz internal clock source or bus clock
• Low-voltage detection with reset or interrupt
• Illegal opcode detection with reset
• Cyclic Redundancy Check (CRC) Module to
support fast cyclic redundancy checks on
memory.
Power-Saving Modes
• Wait plus two stops
Peripherals
• ADC — Up to 16-channel, 10-bit analog-to-digital
converter with automatic compare function
• SCI — Two serial communications interface
modules with optional 13-bit break. supports LIN
2.0 Protocol and SAE J2602; Master extended
break generation; Slave e xtended break detection
• SPI — Serial peripheral interface module
• IIC — Inter-integrated circuit bus module to
operate at up to 100 kbps with maximum bus
loading; capable of higher baudrates with reduced
loading. 10-bit address extension option.
• Timers — Up to two 2-channel and one 6-channel
16-bit timer/pulse-width modulator (TPM) module:
Selectable input capture, output compare, and
edge-aligned PWM capability on each channel.
Each timer module may be configured for
buffered, centered PWM (CPWM) on all channels
• KBI — Up to 8-pin keyboard interrupt module
• CRC - Hardware CRC generation using a 16-bit
shift register
Input/Output
• Up to 54 general-purpose input/output (I/O) pins
• Software selectable pullups on ports when used
as inputs
• Software selectable slew rate control on ports
when used as outputs
• Software selectable drive strength on ports when
used as outputs
• Master reset pin and power-on reset (POR)
• Internal pullup on
pins to reduce customer system cost
RESET, IRQ, and BKGD/MS
Package Options
• 64-pin quad flat package (QFP)
• 64-pin low-profile quad flat package (
• 48-pin quad flat pack no lead package (QFN)
• 44-pin low-profile quad flat package (LQFP)
• 32-pin low-profile quad flat package (LQFP)
LQFP)
MC9S08AC60 Series Data Sheet
Covers MC9S08AC60
MC9S08AC48
MC9S08AC32
MC9S08AC60 Series
Rev. 2
3/2008
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision
Number
1 2/2008 Preliminary customer release.
2 3/2008 Market Launch Release.
Revision
Date
Description of Changes
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
MC9S08AC60 Series Data Sheet, Rev. 2
6 Freescale Semiconductor
List of Chapters
Chapter Title Page
Chapter 1 Introduction..............................................................................19
Chapter 2 Pins and Connections.............................................................25
Chapter 3 Modes of Operation.................................................................35
Chapter 4 Memory.....................................................................................41
Chapter 5 Resets, Interrupts, and System Configuration .....................65
Chapter 6 Parallel Input/Output ...............................................................83
Chapter 7 Central Processor Unit (S08CPUV2)....................................107
Chapter 8 Cyclic Redundancy Check (S08CRCV1)..............................127
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)........................135
Chapter 10 Internal Clock Generator (S08ICGV4)..................................161
Chapter 11 Inter-Integrated Circuit (S08IICV2).......................................189
Chapter 12 Keyboard Interrupt (S08KBIV1)............................................209
Chapter 13 Serial Communications Interface (S08SCIV4).....................215
Chapter 14 Serial Peripheral Interface (S08SPIV3) ................................235
Chapter 15 Timer/PWM (S08TPMV3) .......................................................251
Chapter 16 Development Support ...........................................................281
Appendix A Electrical Characteristics and Timing Specifications.......303
Appendix B Ordering Information and Mechanical Drawings...............329
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 7
Contents
Section Number Title Page
Chapter 1
Introduction
1.1 Overview .........................................................................................................................................19
1.2 MCU Block Diagrams .....................................................................................................................20
1.3 System Clock Distribution ..............................................................................................................22
Chapter 2
Pins and Connections
2.1 Introduction .....................................................................................................................................25
2.2 Device Pin Assignment ...................................................................................................................25
2.3 Recommended System Connections ...............................................................................................29
2.3.1 Power (V
2.3.2 Oscillator (XTAL, EXTAL) ..............................................................................................31
2.3.3
2.3.4 Background/Mode Select (BKGD/MS) ............................................................................32
2.3.5 ADC Reference Pins (V
2.3.6 External Interrupt Pin (IRQ) .............................................................................................32
2.3.7 General-Purpose I/O and Peripheral Ports ........................................................................33
RESET Pin ........................................................................................................................31
, VSS, V
DD
DDAD
REFH
, V
) ..................................................................................31
SSAD
, V
) ..............................................................................32
REFL
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................35
3.2 Features ...........................................................................................................................................35
3.3 Run Mode ........................................................................................................................................35
3.4 Active Background Mode ................................................................................................................35
3.5 Wait Mode .......................................................................................................................................36
3.6 Stop Modes ......................................................................................................................................36
3.6.1 Stop2 Mode .......................................................................................................................37
3.6.2 Stop3 Mode .......................................................................................................................38
3.6.3 Active BDM Enabled in Stop Mode .................................................................................38
3.6.4 LVD Enabled in Stop Mode ..............................................................................................39
3.6.5 On-Chip Peripheral Modules in Stop Modes ....................................................................39
Chapter 4
Memory
4.1 MC9S08AC60 Series Memory Map ...............................................................................................41
4.1.1 Reset and Interrupt Vector Assignments ...........................................................................43
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 9
Section Number Title Page
4.2 Register Addresses and Bit Assignments ........................................................................................44
4.3 RAM ................................................................................................................................................50
4.4 FLASH ............................................................................................................................................51
4.4.1 Features .............................................................................................................................51
4.4.2 Program and Erase Times .................................................................................................51
4.4.3 Program and Erase Command Execution .........................................................................52
4.4.4 Burst Program Execution ..................................................................................................53
4.4.5 Access Errors ....................................................................................................................55
4.4.6 FLASH Block Protection ..................................................................................................55
4.4.7 Vector Redirection ............................................................................................................56
4.5 Security ............................................................................................................................................56
4.6 FLASH Registers and Control Bits .................................................................................................57
4.6.1 FLASH Clock Divider Register (FCDIV) ........................................................................57
4.6.2 FLASH Options Register (FOPT and NVOPT) ................................................................59
4.6.3 FLASH Configuration Register (FCNFG) ........................................................................59
4.6.4 FLASH Protection Register (FPROT and NVPROT) .......................................................61
4.6.5 FLASH Status Register (FSTAT) ......................................................................................61
4.6.6 FLASH Command Register (FCMD) ...............................................................................62
Chapter 5
Resets, Interrupts, and System Configuration
5.1 Introduction .....................................................................................................................................65
5.2 Features ...........................................................................................................................................65
5.3 MCU Reset ......................................................................................................................................65
5.4 Computer Operating Properly (COP) Watchdog .............................................................................66
5.5 Interrupts .........................................................................................................................................67
5.5.1 Interrupt Stack Frame .......................................................................................................68
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................69
5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................69
5.6 Low-Voltage Detect (LVD) System ................................................................................................71
5.6.1 Power-On Reset Operation ...............................................................................................71
5.6.2 LVD Reset Operation ........................................................................................................71
5.6.3 LVD Interrupt Operation ...................................................................................................71
5.6.4 Low-Voltage Warning (LVW) ...........................................................................................71
5.7 Real-Time Interrupt (RTI) ...............................................................................................................71
5.8 MCLK Output .................................................................................................................................72
5.9 Reset, Interrupt, and System Control Registers and Control Bits ...................................................72
5.9.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................73
5.9.2 System Reset Status Register (SRS) .................................................................................74
5.9.3 System Background Debug Force Reset Register (SBDFR) ............................................75
5.9.4 System Options Register (SOPT) .....................................................................................75
5.9.5 System MCLK Control Register (SMCLK) .....................................................................76
MC9S08AC60 Series Data Sheet, Rev. 2
10 Freescale Semiconductor
Section Number Title Page
5.9.6 System Device Identification Register (SDIDH, SDIDL) ................................................77
5.9.7 System Real-Time Interrupt Status and Control Register (SRTISC) ................................78
5.9.8 System Power Management Status and Control 1 Register (SPMSC1) ...........................79
5.9.9 System Power Management Status and Control 2 Register (SPMSC2) ...........................80
5.9.10 System Options Register 2 (SOPT2) ................................................................................81
Chapter 6
Parallel Input/Output
6.1 Introduction .....................................................................................................................................83
6.2 Pin Descriptions ..............................................................................................................................83
6.3 Parallel I/O Control .........................................................................................................................83
6.4 Pin Control ......................................................................................................................................84
6.4.1 Internal Pullup Enable .......................................................................................................85
6.4.2 Output Slew Rate Control Enable .....................................................................................85
6.4.3 Output Drive Strength Select ............................................................................................85
6.5 Pin Behavior in Stop Modes ............................................................................................................86
6.6 Parallel I/O and Pin Control Registers ............................................................................................86
6.6.1 Port A I/O Registers (PTAD and PTADD) .......................................................................86
6.6.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) .................................................87
6.6.3 Port B I/O Registers (PTBD and PTBDD) .......................................................................89
6.6.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) .................................................90
6.6.5 Port C I/O Registers (PTCD and PTCDD) .......................................................................92
6.6.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) .................................................93
6.6.7 Port D I/O Registers (PTDD and PTDDD) .......................................................................95
6.6.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) ................................................96
6.6.9 Port E I/O Registers (PTED and PTEDD) ........................................................................98
6.6.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) ..................................................99
6.6.11 Port F I/O Registers (PTFD and PTFDD) .......................................................................101
6.6.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) ................................................102
6.6.13 Port G I/O Registers (PTGD and PTGDD) .....................................................................104
6.6.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ..............................................105
Chapter 7
Central Processor Unit (S08CPUV2)
7.1 Introduction ...................................................................................................................................107
7.1.1 Features ...........................................................................................................................107
7.2 Programmer’s Model and CPU Registers .....................................................................................108
7.2.1 Accumulator (A) .............................................................................................................108
7.2.2 Index Register (H:X) .......................................................................................................108
7.2.3 Stack Pointer (SP) ...........................................................................................................109
7.2.4 Program Counter (PC) ....................................................................................................109
7.2.5 Condition Code Register (CCR) .....................................................................................109
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 11
Section Number Title Page
7.3 Addressing Modes .........................................................................................................................111
7.3.1 Inherent Addressing Mode (INH) ...................................................................................111
7.3.2 Relative Addressing Mode (REL) ...................................................................................111
7.3.3 Immediate Addressing Mode (IMM) ..............................................................................111
7.3.4 Direct Addressing Mode (DIR) ......................................................................................111
7.3.5 Extended Addressing Mode (EXT) ................................................................................112
7.3.6 Indexed Addressing Mode ..............................................................................................112
7.4 Special Operations .........................................................................................................................113
7.4.1 Reset Sequence ...............................................................................................................113
7.4.2 Interrupt Sequence ..........................................................................................................113
7.4.3 Wait Mode Operation ......................................................................................................114
7.4.4 Stop Mode Operation ......................................................................................................114
7.4.5 BGND Instruction ...........................................................................................................115
7.5 HCS08 Instruction Set Summary ..................................................................................................116
Chapter 8
Cyclic Redundancy Check (S08CRCV1)
8.1 Introduction ...................................................................................................................................127
8.1.1 Features ...........................................................................................................................127
8.1.2 Modes of Operation ........................................................................................................129
8.1.3 Block Diagram ................................................................................................................129
8.2 External Signal Description ..........................................................................................................129
8.3 Register Definition .......................................................................................................................130
8.3.1 Memory Map ..................................................................................................................130
8.3.2 Register Descriptions ......................................................................................................130
8.4 Functional Description ..................................................................................................................131
8.4.1 ITU-T (CCITT) Recommendations and Expected CRC Results ....................................132
8.5 Initialization Information ..............................................................................................................133
Chapter 9
Analog-to-Digital Converter (S08ADC10V1)
9.1 Overview .......................................................................................................................................135
9.2 Channel Assignments ....................................................................................................................135
9.2.1 Alternate Clock ...............................................................................................................136
9.2.2 Hardware Trigger ............................................................................................................136
9.2.3 Temperature Sensor ........................................................................................................137
9.2.4 Features ...........................................................................................................................139
9.2.5 Block Diagram ................................................................................................................139
9.3 External Signal Description ..........................................................................................................140
9.3.1 Analog Power (V
9.3.2 Analog Ground (V
9.3.3 Voltage Reference High (V
12 Freescale Semiconductor
) ..................................................................................................141
DDAD
) .................................................................................................141
SSAD
) ...................................................................................141
REFH
MC9S08AC60 Series Data Sheet, Rev. 2
Section Number Title Page
9.3.4 Voltage Reference Low (V
) .....................................................................................141
REFL
9.3.5 Analog Channel Inputs (ADx) ........................................................................................141
9.4 Register Definition ........................................................................................................................141
9.4.1 Status and Control Register 1 (ADCSC1) ......................................................................141
9.4.2 Status and Control Register 2 (ADCSC2) ......................................................................143
9.4.3 Data Result High Register (ADCRH) .............................................................................144
9.4.4 Data Result Low Register (ADCRL) ..............................................................................144
9.4.5 Compare Value High Register (ADCCVH) ....................................................................145
9.4.6 Compare Value Low Register (ADCCVL) .....................................................................145
9.4.7 Configuration Register (ADCCFG) ................................................................................145
9.4.8 Pin Control 1 Register (APCTL1) ..................................................................................147
9.4.9 Pin Control 2 Register (APCTL2) ..................................................................................148
9.5 Functional Description ..................................................................................................................149
9.5.1 Clock Select and Divide Control ....................................................................................149
9.5.2 Input Select and Pin Control ...........................................................................................150
9.5.3 Hardware Trigger ............................................................................................................150
9.5.4 Conversion Control .........................................................................................................150
9.5.5 Automatic Compare Function .........................................................................................153
9.5.6 MCU Wait Mode Operation ............................................................................................153
9.5.7 MCU Stop3 Mode Operation ..........................................................................................153
9.5.8 MCU Stop1 and Stop2 Mode Operation .........................................................................154
9.6 Initialization Information ..............................................................................................................154
9.6.1 ADC Module Initialization Example .............................................................................154
9.7 Application Information ................................................................................................................156
9.7.1 External Pins and Routing ..............................................................................................156
9.7.2 Sources of Error ..............................................................................................................158
Chapter 10
Internal Clock Generator (S08ICGV4)
10.1 Introduction ...................................................................................................................................161
10.2 Introduction ...................................................................................................................................164
10.2.1 Features ...........................................................................................................................164
10.2.2 Modes of Operation ........................................................................................................165
10.2.3 Block Diagram ................................................................................................................166
10.3 External Signal Description ..........................................................................................................166
10.3.1 EXTAL — External Reference Clock / Oscillator Input ................................................166
10.3.2 XTAL — Oscillator Output ............................................................................................166
10.3.3 External Clock Connections ...........................................................................................167
10.3.4 External Crystal/Resonator Connections ........................................................................167
10.4 Register Definition ........................................................................................................................168
10.4.1 ICG Control Register 1 (ICGC1) ....................................................................................168
10.4.2 ICG Control Register 2 (ICGC2) ....................................................................................170
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 13
Section Number Title Page
10.4.3 ICG Status Register 1 (ICGS1) .......................................................................................171
10.4.4 ICG Status Register 2 (ICGS2) .......................................................................................172
10.4.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ..................................................................172
10.4.6 ICG Trim Register (ICGTRM) .......................................................................................173
10.5 Functional Description ..................................................................................................................173
10.5.1 Off Mode (Off) ................................................................................................................174
10.5.2 Self-Clocked Mode (SCM) .............................................................................................174
10.5.3 FLL Engaged, Internal Clock (FEI) Mode .....................................................................175
10.5.4 FLL Engaged Internal Unlocked ....................................................................................176
10.5.5 FLL Engaged Internal Locked ........................................................................................176
10.5.6 FLL Bypassed, External Clock (FBE) Mode ..................................................................176
10.5.7 FLL Engaged, External Clock (FEE) Mode ...................................................................176
10.5.8 FLL Lock and Loss-of-Lock Detection ..........................................................................177
10.5.9 FLL Loss-of-Clock Detection .........................................................................................178
10.5.10Clock Mode Requirements .............................................................................................179
10.5.11Fixed Frequency Clock ...................................................................................................180
10.5.12High Gain Oscillator .......................................................................................................180
10.6 Initialization/Application Information ..........................................................................................180
10.6.1 Introduction .....................................................................................................................180
10.6.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ...........................182
10.6.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ..............................184
10.6.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ......................186
10.6.5 Example #4: Internal Clock Generator Trim ..................................................................188
Chapter 11
Inter-Integrated Circuit (S08IICV2)
11.1 Introduction ...................................................................................................................................189
11.1.1 Features ...........................................................................................................................191
11.1.2 Modes of Operation ........................................................................................................191
11.1.3 Block Diagram ................................................................................................................192
11.2 External Signal Description ..........................................................................................................192
11.2.1 SCL — Serial Clock Line ...............................................................................................192
11.2.2 SDA — Serial Data Line ................................................................................................192
11.3 Register Definition ........................................................................................................................192
11.3.1 IIC Address Register (IICA) ...........................................................................................193
11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................193
11.3.3 IIC Control Register (IICC1) ..........................................................................................196
11.3.4 IIC Status Register (IICS) ...............................................................................................197
11.3.5 IIC Data I/O Register (IICD) ..........................................................................................198
11.3.6 IIC Control Register 2 (IICC2) .......................................................................................198
11.4 Functional Description ..................................................................................................................199
11.4.1 IIC Protocol .....................................................................................................................199
MC9S08AC60 Series Data Sheet, Rev. 2
14 Freescale Semiconductor
Section Number Title Page
11.4.2 10-bit Address .................................................................................................................203
11.4.3 General Call Address ......................................................................................................204
11.5 Resets ............................................................................................................................................204
11.6 Interrupts .......................................................................................................................................204
11.6.1 Byte Transfer Interrupt ....................................................................................................204
11.6.2 Address Detect Interrupt .................................................................................................204
11.6.3 Arbitration Lost Interrupt ................................................................................................204
11.7 Initialization/Application Information ..........................................................................................206
Chapter 12
Keyboard Interrupt (S08KBIV1)
12.1 Introduction ...................................................................................................................................209
12.1.1 Features ...........................................................................................................................209
12.1.2 KBI Block Diagram ........................................................................................................211
12.2 Register Definition ........................................................................................................................211
12.2.1 KBI Status and Control Register (KBISC) .....................................................................212
12.2.2 KBI Pin Enable Register (KBIPE) ..................................................................................213
12.3 Functional Description ..................................................................................................................213
12.3.1 Pin Enables ......................................................................................................................213
12.3.2 Edge and Level Sensitivity ..............................................................................................213
12.3.3 KBI Interrupt Controls ....................................................................................................214
Chapter 13
Serial Communications Interface (S08SCIV4)
13.1 Introduction ...................................................................................................................................215
13.1.1 Features ...........................................................................................................................217
13.1.2 Modes of Operation ........................................................................................................217
13.1.3 Block Diagram ................................................................................................................218
13.2 Register Definition ........................................................................................................................220
13.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................220
13.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................221
13.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................222
13.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................223
13.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................225
13.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................226
13.2.7 SCI Data Register (SCIxD) .............................................................................................227
13.3 Functional Description ..................................................................................................................227
13.3.1 Baud Rate Generation .....................................................................................................227
13.3.2 Transmitter Functional Description ................................................................................228
13.3.3 Receiver Functional Description .....................................................................................229
13.3.4 Interrupts and Status Flags ..............................................................................................231
13.3.5 Additional SCI Functions ...............................................................................................232
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 15
Section Number Title Page
Chapter 14
Serial Peripheral Interface (S08SPIV3)
14.1 Introduction ...................................................................................................................................235
14.1.1 Features ...........................................................................................................................237
14.1.2 Block Diagrams ..............................................................................................................237
14.1.3 SPI Baud Rate Generation ..............................................................................................239
14.2 External Signal Description ..........................................................................................................240
14.2.1 SPSCK — SPI Serial Clock ............................................................................................240
14.2.2 MOSI — Master Data Out, Slave Data In ......................................................................240
14.2.3 MISO — Master Data In, Slave Data Out ......................................................................240
14.2.4 SS — Slave Select ...........................................................................................................240
14.3 Modes of Operation .......................................................................................................................241
14.3.1 SPI in Stop Modes ..........................................................................................................241
14.4 Register Definition ........................................................................................................................241
14.4.1 SPI Control Register 1 (SPIC1) ......................................................................................241
14.4.2 SPI Control Register 2 (SPIC2) ......................................................................................242
14.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................243
14.4.4 SPI Status Register (SPIS) ..............................................................................................244
14.4.5 SPI Data Register (SPID) ................................................................................................245
14.5 Functional Description ..................................................................................................................246
14.5.1 SPI Clock Formats ..........................................................................................................246
14.5.2 SPI Interrupts ..................................................................................................................249
14.5.3 Mode Fault Detection .....................................................................................................249
Chapter 15
Timer/PWM (S08TPMV3)
15.1 Introduction ...................................................................................................................................251
15.2 Features .........................................................................................................................................251
15.3 TPMV3 Differences from Previous Versions ................................................................................253
15.3.1 Migrating from TPMV1 ..................................................................................................255
15.3.2 Features ...........................................................................................................................256
15.3.3 Modes of Operation ........................................................................................................256
15.3.4 Block Diagram ................................................................................................................257
15.4 Signal Description .........................................................................................................................259
15.4.1 Detailed Signal Descriptions ...........................................................................................259
15.5 Register Definition ........................................................................................................................263
15.5.1 TPM Status and Control Register (TPMxSC) ................................................................263
15.5.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................264
15.5.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................265
15.5.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................266
15.5.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................268
15.6 Functional Description ..................................................................................................................269
MC9S08AC60 Series Data Sheet, Rev. 2
16 Freescale Semiconductor
Section Number Title Page
15.6.1 Counter ............................................................................................................................270
15.6.2 Channel Mode Selection .................................................................................................272
15.7 Reset Overview .............................................................................................................................275
15.7.1 General ............................................................................................................................275
15.7.2 Description of Reset Operation .......................................................................................275
15.8 Interrupts .......................................................................................................................................275
15.8.1 General ............................................................................................................................275
15.8.2 Description of Interrupt Operation ..................................................................................276
15.9 The Differences from TPM v2 to TPM v3 ....................................................................................277
Chapter 16
Development Support
16.1 Introduction ...................................................................................................................................281
16.1.1 Features ...........................................................................................................................282
16.2 Background Debug Controller (BDC) ..........................................................................................282
16.2.1 BKGD Pin Description ...................................................................................................283
16.2.2 Communication Details ..................................................................................................284
16.2.3 BDC Commands .............................................................................................................288
16.2.4 BDC Hardware Breakpoint .............................................................................................290
16.3 On-Chip Debug System (DBG) ....................................................................................................291
16.3.1 Comparators A and B ......................................................................................................291
16.3.2 Bus Capture Information and FIFO Operation ...............................................................291
16.3.3 Change-of-Flow Information ..........................................................................................292
16.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................292
16.3.5 Trigger Modes .................................................................................................................293
16.3.6 Hardware Breakpoints ....................................................................................................295
16.4 Register Definition ........................................................................................................................295
16.4.1 BDC Registers and Control Bits .....................................................................................295
16.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................297
16.4.3 DBG Registers and Control Bits .....................................................................................298
Appendix A
Electrical Characteristics and Timing Specifications
A.1 Introduction....................................................................................................................................303
A.2 Parameter Classification.................................................................................................................303
A.3 Absolute Maximum Ratings...........................................................................................................304
A.4 Thermal Characteristics..................................................................................................................305
A.5 ESD Protection and Latch-Up Immunity.......................................................................................306
A.6 DC Characteristics..........................................................................................................................308
A.7 Supply Current Characteristics.......................................................................................................311
A.8 ADC Characteristics.......................................................................................................................314
A.9 Internal Clock Generation Module Characteristics........................................................................317
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 17
Section Number Title Page
A.9.1 ICG Frequency Specifications.........................................................................................318
A.10 AC Characteristics..........................................................................................................................320
A.10.1 Control Timing ................................................................................................................320
A.10.2 Timer/PWM (TPM) Module Timing...............................................................................321
A.11 SPI Characteristics .........................................................................................................................323
A.12 FLASH Specifications....................................................................................................................326
A.13 EMC Performance..........................................................................................................................327
A.13.1 Conducted Transient Susceptibility.................................................................................327
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information .....................................................................................................................329
B.2 Orderable Part Numbering System ................................................................................................329
B.3 Mechanical Drawings.....................................................................................................................329
MC9S08AC60 Series Data Sheet, Rev. 2
18 Freescale Semiconductor
Chapter 1 Introduction
1.1 Overview
The MC9S08AC60 Series are members of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for
memory sizes and package types.
Table 1-1. Devices in the MC9S08AC60 Series
Device FLASH RAM Package
64 QFP
64 LQFP
MC9S08AC60 63,280
49,152
MC9S08AC48
32,768
MC9S08AC32
2048
48 QFN
44 LQFP
32 LQFP
64 QFP
64 LQFP
48 QFN
44 LQFP
32 LQFP
64 QFP
64 LQFP
48 QFN
44 LQFP
32 LQFP
Table 1-2 summarizes the feature set available in the MC9S08AC60 Series of MCUs.
Table 1-2. MC9S08AC60 Series Peripherals Available per Package Type
MC9S08AC60/48/32
Feature 64-pin 48-pin 44-pin 32-pin
CRC yes
ADC 16-ch 8-ch 6-ch
IIC yes
IRQ yes
KBI1 8764
SCI1 yes
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 19
Chapter 1 Introduction
Table 1-2. MC9S08AC60 Series Peripherals Available per Package Type
MC9S08AC60/48/32
Feature 64-pin 48-pin 44-pin 32-pin
SCI2 yes no
SPI1 yes
TPM1 6-ch 4-ch 2-ch
TPM1CLK
TPM2 2-ch
TPM2CLK
TPM3 2-ch
TPMCLK
I/O pins 54 38 34 22
1
TPMCLK, TPM1CLK, and TPM2CLK options are configured via software using the TPMCCFG bit; out of
reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively.
Reference the TPM chapter for a functional description of the TPMxCLK signal.
1
1
1
yes no
yes no
yes
1.2 MCU Block Diagrams
The block diagram shows the structure of the MC9S08AC60 Series MCU.
MC9S08AC60 Series Data Sheet, Rev. 2
20 Freescale Semiconductor
Chapter 1 Introduction
HCS08 CORE
BKGD/MS
RESET
IRQ/TPMCLK
V
DDAD
V
SSAD
V
REFL
V
REFH
V
DD
V
SS
BDC
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
USER FLASH
63,280 BYTES
49,152
32,768
USER RAM
2048 BYTES
INTERNAL CLOCK
GENERATOR (ICG)
LOW-POWER OSCILLATOR
VOLTAGE
REGULATOR
CPU
BYTES
BYTES
TPMCLK
Notes:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ is enabled
ICE DEBUG
MODULE (DBG)
CYCLIC REDUNDANCY
CHECK MODULE (CRC)
2-CHANNEL TIMER/PWM
MODULE (TPM3)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI2)
IIC MODULE (IIC1)
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC1)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
6-CHANNEL TIMER/PWM
MODULE (TPM1)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI1)
2-CHANNEL TIMER/PWM
MODULE (TPM2)
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
TPM3CH1
TPM3CH0
RxD2
TxD2
SDA1
SCL1
8
AD1P[7:0]
8
AD1P[15:8]
SPSCK1
MOSI1
MISO1
SS1
TPM1CH1
TPM1CH0
TPM1CLK
TPM1CH[5:2]
RxD1
TxD1
TPM2CH1
TPM2CH0
TPM2CLK
3
KBI1P[7:5]
KBI1P[4:0]
5
EXTAL
XTAL
8
PTA[7:0]
PORT A
6
PTB[7:2]/AD1P[7:2]
PTB1/TPM3CH1/AD1P1
PORT B
PTB0/TPM3CH0/AD1P0
PTC6
PTC5/RxD2
PTC4
PTC3/TxD2
PORT C
PTC2/MCLK
PTC1/SDA1
PTC0/SCL1
PTD7/KBI1P7/AD1P15
PTD6/TPM1CLK/AD1P14
PTD5/AD1P13
PTD4/TPM2CLK/AD1P12
PTD3/KBI1P6/AD1P11
PORT D
PORT E
PORT F
PORT G
PTD2/KBI1P5/AD1P10
PTD1/AD1P9
PTD0/AD1P8
PTE7/SPSCK1
PTE6/MOSI1
PTE5/MISO1
PTE4/
PTE3/TPM1CH1
PTE2/TPM1CH0
PTE1/RxD1
PTE0/TxD1
PTF[7:6]
PTF5/TPM2CH1
PTF4/TPM2CH0
PTF3/TPM1CH5
PTF2/TPM1CH4
PTF1/TPM1CH3
PTF0/TPM1CH2
PTG6/EXTAL
PTG5/XTAL
PTG4/KBI1P4
PTG3/KBI1P3
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
SS1
(IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1)
3. Pin contains integrated pullup device.
4. PTD3, PTD2, PTD7, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled
(KBIPEn = 1) and rising edge is selected (KBEDGn = 1).
5. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and
TPMCLK are available to TPM1, TPM2, and TPM3 respectively.
Figure 1-1. MC9S08AC60 Series Block Diagram
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 21
Chapter 1 Introduction
Table 1 lists the functional versions of the on-chip modules.
Table 1. Versions of On-Chip Modules
Module Version
Cyclic Redundancy Check Generator (CRC) 1
Analog-to-Digital Converter (ADC) 1
Internal Clock Generator (ICG) 4
Inter-Integrated Circuit (IIC) 2
Keyboard Interrupt (KBI) 1
Serial Communications Interface (SCI) 4
Serial Peripheral Interface (SPI) 3
Timer Pulse-Width Modulator (TPM) 3
Central Processing Unit (CPU) 2
Debug Module (DBG) 2
1.3 System Clock Distribution
TPM1CLK TPM2CLK
ICG
ICGERCLK
FFE
ICGOUT
ICGLCLK*
SYSTEM
CONTROL
LOGIC
RTI
TPM1 TPM2 IIC1 SCI1 SCI2 SPI1
÷2
XCLK**
1 kHz
÷2
CPU
BUSCLK
COP
* ICGLCLK is the alternate BDC clock source for the MC9S08AC60 Series.
**
BDC
Fixed frequency clock.
TPM3
Figure 1-2. System Clock Distribution Diagram
TPMCLK
ADC1
RAM FLASH
CRC
Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock
connection diagram. The ICG supplies the clock sources:
• ICGOUT is an output of the ICG module. It is one of the following:
— The external crystal oscillator
MC9S08AC60 Series Data Sheet, Rev. 2
22 Freescale Semiconductor
Chapter 1 Introduction
— An external clock source
— The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop
sub-module
— Control bits inside the ICG determine which source is connected.
• FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency
of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be ICGERCLK/2.
Otherwise the fixed-frequency clock will be BUSCLK.
• ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed
up BDC communications in systems where the bus clock is slow.
• ICGERCLK — External reference clock can be selected as the real-time interrupt clock source.
Can also be used as the ALTCLK input to the ADC module.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 23
Chapter 1 Introduction
MC9S08AC60 Series Data Sheet, Rev. 2
24 Freescale Semiconductor
Chapter 2 Pins and Connections
2.1 Introduction
This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
2.2 Device Pin Assignment
Figure 2-1. shows the 64-pin package assignments for the MC9S08AC60 Series devices.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 25
Chapter 2 Pins and Connections
PTC4
IRQ/TPMCLK
RESET
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF2/TPM1CH4
PTF3/TPM1CH5
PTF4/TPM2CH0
PTC6
PTF7
PTF5/TPM2CH1
PTF6
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
1
64
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PTC5/RxD2
PTC3/TxD2
63 62 61
PTC1/SDA1
PTC2/MCLK
PTC0/SCL1
59
60
SS
PTG6/EXTAL
V
57
58
64-Pin QFP
64-Pin LQFP
PTG5/XTAL
BKGD/MS
56
REFL
V
REFH
V
PTD6/TPM1CLK/AD1P14
PTD7/KBI1P7/AD1P15
PTD5/AD1P13
PTD4/TPM2CLK/AD1P12
PTG4/KBI1P4
49
505152535455
47
46
45
44
43
42
41
40
39
38
37
36
35
34
PTG3/KBI1P3
48
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
V
SSAD
V
DDAD
PTD1/AD1P9
PTD0/AD1P8
PTB7/AD1P7
PTB6/AD1P6
PTB5/AD1P5
PTB4/AD1P4
PTB3/AD1P3
PTB2/AD1P2
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
PTE3/TPM1CH1
16
19
18
20 21 22
23
27
26
28 29 30 31
17
DD
SS
V
V
PTA024PTA125PTA2
PTA3
PTA4
PTE4/SS1
PTE6/MOSI1
PTE5/MISO1
PTE7/SPSCK1
PTG0/KBI1P0
PTG2/KBI1P2
PTG1/KBI1P1
Figure 2-1. MC9S08AC60 Series in 64-Pin QFP or LQFP Package
MC9S08AC60 Series Data Sheet, Rev. 2
PTA5
PTA7
33
32
PTA6
26 Freescale Semiconductor
Chapter 2 Pins and Connections
Figure 2-2 shows the 48-pin QFN pin assignments for the MC9S08AC60 Series device.
REFH
REFL
BKGD/MS
V
40
39
21
22
PTA0
PTG2/KBI1P2
V
38
23
PTA1
PTG4/KB1IP4
37
PTG3/KBI1P3
36
PTD3/KBI1P6/AD1P11
35
PTD2/KBI1P5/AD1P10
34
V
33
SSAD
V
32
DDAD
PTD1/AD1P9
31
PTD0/AD1P8
30
PTB3/AD1P3
29
PTB2/AD1P2
28
27
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
26
PTA7
25
24
PTA2
PTC4
IRQ/TPMCLK
RESET
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF4/TPM2CH0
PTF5/TPM2CH1
PTF6
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
1
2
3
4
5
6
7
8
9
10
11
12
PTC5/RxD2
PTC3/TxD2
47
48
14
13
PTE4/SS1
PTE5/MISO1
PTC1/SDA1
PTC2/MCLK
46
45
15
16
PTE6/MOSI1
PTE7/SPSCK1
SS
PTG6/EXTAL
V
PTC0/SCL1
44
43
42
48-Pin QFN
17
18
19
SS
DD
V
V
PTG0/KBI1P0
PTG5/XTAL
41
20
PTG1/KBI1P1
Figure 2-2. MC9S08AC60 Series in 48-Pin QFN Package
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 27
Chapter 2 Pins and Connections
Figure 2-3. shows the 44-pin LQFP pin assignments for the MC9S08AC60 Series device.
PTC4
IRQ/TPMCLK
RESET
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF4/TPM2CH0
PTF5/TPM2CH1
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
PTC5/RxD2
PTC3/TxD2
PTC1/SDA1
PTC2/MCLK
SS
V
PTC0/SCL1
PTG6/EXTAL
PTG5/XTAL
BKGD/MS
44
1
43 42 41
39
40
36
37
38
2
3
4
5
6
44-Pin LQFP
7
8
9
10
11
14
13
15 16 17
18
20 21
12
SS
DD
V
V
REFL
V
35
PTA019PTA1
REFH
V
34
PTG3/KBI1P3
33
32
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
31
V
30
29
28
27
26
25
24
SSAD
V
DDAD
PTD1/AD1P9
PTD0/AD1P8
PTB3/AD1P3
PTB2/AD1P2
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
23
22
PTE4/SS1
PTE6/MOSI1
PTE5/MISO1
PTE7/SPSCK1
PTG0/KBI1P0
PTG2/KBI1P2
PTG1/KBI1P1
Figure 2-3. MC9S08AC60 Series in 44-Pin LQFP Package
MC9S08AC60 Series Data Sheet, Rev. 2
28 Freescale Semiconductor
Chapter 2 Pins and Connections
Figure 2-4. shows the 32-pin LQFP pin assignments for the MC9S08AC60 Series device.
IRQ/TPMCLK
RESET
PTF4/TPM2CH0
PTF5/TPM2CH1
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
SS
PTG6/EXTAL
V
PTC0/SCL1
PTC1/SDA1
32
1
31 30 29 28
2
3
4
5
6
7
8
10
9
PTE4/SS1
PTE5/MISO1
32-Pin LQFP
11
PTE6/MOSI1
PTG5/XTAL
12 13 14
SS
V
PTE7/SPSCK1
BKGD/MS
26
27
15
DD
V
REFL
V
PTG0/KBI1P0
Figure 2-4. MC9S08AC60 Series in 32-Pin LQFP Package
2.3 Recommended System Connections
REFH
V
25
24
23
22
21
20
19
18
17
16
PTG1/KBI1P1
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
V
SSAD
V
DDAD
PTB3/AD1P3
PTB2/AD1P2
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
Figure 2-5 shows pin connections that are common to almost all MC9S08AC60 Series application
systems.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 29
Chapter 2 Pins and Connections
SYSTEM
POWER
+
C
5 V
10 μF
BLK
V
REFH
DDAD
SSAD
DD
SS
(x2)
MC9S08AC60
PORT
A
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
C
BYAD
0.1 μF
V
V
DD
V
V
REFL
V
+
C
BY
0.1 μF
V
PTA7
NOTE 1
V
DD
NOTES:
1. Not required if
using the internal
clock option.
2. These are the
same pins as
PTG5 and PTG6
3. RC filters on
RESET and IRQ
are recommended
for EMC-sensitive
applications.
C1
X1
BACKGROUND HEADER
OPTIONAL
MANUAL
RESET
ASYNCHRONOUS
INTERRUPT
INPUT
R
F
C2
1
V
DD
4.7 kΩ–10 kΩ
0.1 μF
PTG0/KBI1P0
PTG1/KBI1P1
PTG2/KBI1P2
PTG3/KBI1P3
PTG4/KBI1P4
PTG5/XTAL
PTG6/EXTAL
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF2/TPM1CH4
PTF3/TPM1CH5
PTF4/TPM2CH0
PTF5/TPM2CH1
PTF6
PTF7
R
S
XTAL
NOTE 2
EXTAL
NOTE 2
PORT
B
PTB0/AD1P0
PTB1/AD1P1
PTB2/AD1P2
PTB3/AD1P3
PTB4/AD1P4
PTB5/AD1P5
I/O AND
PERIPHERAL
INTERFACE TO
APPLICATION
SYSTEM
V
DD
4.7 kΩ–
10 kΩ
0.1 μF
BKGD/MS
RESET
IRQ
NOTE 1
PORT
C
PTB6/AD1P6
PTB7/AD1P7
PTC0/SCL1
PTC1/SDA1
PTC2/MCLK
PTC3/TxD2
PTC4
PTC5/RxD2
PTC6
PTD0/AD1P8
PTD1/AD1P9
PTD2/KBI1P5/AD1P10
PORT
G
PORT
D
PTD3/KBI1P6/AD1P11
PTD4/TPM2CLK/AD1P12
PTD5/AD1P13
PTD6/TPM1CLK/AD1P14
PTD7/KBI1P7/AD1P15
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PORT
F
PORT
E
PTE3/TPM1CH1
PTE4/
SS1
PTE5/MISO1
PTE6/MOSI1
PTE7/SPSCK1
Figure 2-5. Basic System Connections
MC9S08AC60 Series Data Sheet, Rev. 2
30 Freescale Semiconductor
Chapter 2 Pins and Connections
2.3.1 Power (VDD, VSS, V
DDAD
, V
SSAD
)
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor , such as a 10-μF tantalum capacitor , to pro vide bulk char ge storage
for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the paired V
DD
and V
SS
power pins as practical to suppress high-frequency noise. The MC9S08AC60 has a second VSS pin. This
pin should be connected to the system ground plane or to the primary V
pin through a low-impedance
SS
connection.
V
DDAD
and V
are the analog power supply pins for the MCU. This voltage source supplies po wer to
SSAD
the ADC module. A 0.1-μF ceramic bypass capacitor should be located as near to the analog power pins
as practical to suppress high-frequency noise.
2.3.2 Oscillator (XTAL, EXTAL)
Out of reset the MCU uses an internally generated clock (self-clocked mode — f
Self_reset
about 8-MHz crystal rate. This frequency source is used during reset startup and can be enabled as the
clock source for stop recovery to avoid the need for a long crystal startup delay. This MCU also contains
a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information
on the ICG, see Chapter 10, “Internal Clock Generator (S08ICGV4).”
) equivalent to
The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in
either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or
ceramic resonator, an external oscillator can be connected to the EXTAL input pin.
Refer to Figure 2-5 for the following discussion. R
(when used) and RF should be low-inductance
S
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
R
F
value is not generally critical. T ypical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity
and lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C1 and C2 which are usually the same size. As a first-order approximation,
use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and
XTAL).
2.3.3 RESET Pin
RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output dri ver ,
and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 31
Chapter 2 Pins and Connections
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
debug connector so a dev elopment system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever an y reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for approximately 34 cycles of f
Self_reset
. The reset circuitry decodes the cause of reset and
records it by setting a corresponding bit in the system control reset status register (SRS).
In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-5 for
an example.
2.3.4 Background/Mode Select (BKGD/MS)
While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises the pin
functions as the background pin and can be used for background debug communication. While functioning
as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, and no output
slew rate control. When the pin functions as a background pin, it includes a high current output driver.
When the pin functions as a mode select pin it is input only, and therefore does not include a standard
output driver.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header , it can hold BKGD/MS lo w
during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the bus clock rate, so there should ne ver be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and f all
times on the BKGD pin.
2.3.5 ADC Reference Pins (V
The V
REFH
and V
pins are the voltage reference high and voltage reference low inputs respectively
REFL
REFH
, V
REFL
)
for the ADC module.
2.3.6 External Interrupt Pin (IRQ)
The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions.
If the IRQ function is not enabled, this pin can still be configured as the TPMCLK (see the TPM chapter).
In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-5 for
an example.
MC9S08AC60 Series Data Sheet, Rev. 2
32 Freescale Semiconductor
Chapter 2 Pins and Connections
2.3.7 General-Purpose I/O and Peripheral Ports
The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers
and serial I/O systems. Immediately after reset, all of these pins are configured as high-impedance
general-purpose inputs with internal pullup devices disabled.
NOTE
To avoid e xtra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unused pins to outputs so the pins do not
float.
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unconnected pins to outputs so the pins
do not float.
For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output.”
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See the Chapter 6, “Parallel Input/Output” chapter for more details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenev er the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTD7, PTD3,
PTD2, and PTG4 pins are controlled by the KBI module and are configured for rising-edge/high-level
sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. Similarly,
when IRQ is configured as the IRQ input and is set to detect rising edges, the pullup enable control bit
enables a pulldown device rather than a pullup device.
NOTE
When an alternative function is first enabled it is possible to get a spurious
edge to the module, user software should clear out any associated flags
before interrupts are enabled. Table 2-1 illustrates the priority if multiple
modules are enabled. The highest priority module will have control ov er the
pin. Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module. It is
recommended that all modules that share a pin be disabled before enabling
another module.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 33
Chapter 2 Pins and Connections
Table 2-1. Pin Availability by Package Pin-Count
Pin Number <-- Lowest Priority --> Highest
64 48 44 32 Port Pin Alt 1 Alt 2
1 1 1 — PTC4
2 2 2 1 IRQ TPMCLK
1
3332RESET
4 4 4 — PTF0 TPM1CH2
5 5 5 — PTF1 TPM1CH3
6 — — — PTF2 TPM1CH4
7 — — — PTF3 TPM1CH5
8 6 6 3 PTF4 TPM2CH0
9 — — — PTC6
10 — — — PTF7
11 7 7 4 PTF5 TPM2CH1
12 8 — — PTF6
13 9 8 5 PTE0 TxD1
14 10 9 6 PTE1 RxD1
15 11 10 7 PTE2 TPM1CH0
16 12 11 8 PTE3 TPM1CH1
17 13 12 9 PTE4 SS1
18 14 13 10 PTE5 MISO1
19 15 14 11 PTE6 MOSI1
20 16 15 12 PTE7 SPSCK1
21 17 16 13 V
22 18 17 14 V
SS
DD
23 19 18 15 PTG0 KBI1P0
24 20 19 16 PTG1 KBI1P1
25 21 20 — PTG2 KBI1P2
26 22 21 — PTA0
27 23 22 — PTA1
28 24 — — PTA2
29 — — — PTA3
30 — — — PTA4
31 — — — PTA5
32 — — — PTA6
Pin Number <-- Lowest Priority --> Highest
64 48 44 32 Port Pin Alt 1 Alt 2
33 25 — — PTA7
34 26 23 17 PTB0 TPM3CH0 AD1P0
35 27 24 18 PTB1 TPM3CH1 AD1P1
36 28 25 19 PTB2 AD1P2
37 29 26 20 PTB3 AD1P3
38 — — — PTB4 AD1P4
39 — — — PTB5 AD1P5
40 — — — PTB6 AD1P6
41 — — — PTB7 AD1P7
42 30 27 — PTD0 AD1P8
43 31 28 — PTD1 AD1P9
44 32 29 21 V
45 33 30 22 V
DDAD
SSAD
46 34 31 23 PTD2 KBI1P5 AD1P10
47 35 32 24 PTD3 KBI1P6 AD1P11
48 36 33 — PTG3 KBI1P3
49 37 — — PTG4 KBI1P4
50 — — — PTD4 TPM2CLK AD1P12
51 — — — PTD5 AD1P13
52 — — — PTD6 TPM1CLK AD1P14
53 — — — PTD7 KBI1P7 AD1P15
54 38 34 25 V
55 39 35 26 V
REFH
REFL
56 40 36 27 BKGD MS
57 41 37 28 PTG5 XTAL
58 42 38 29 PTG6 EXTAL
59 43 39 30 V
SS
60 44 40 31 PTC0 SCL1
61 45 41 32 PTC1 SDA1
62 46 42 — PTC2 MCLK
63 47 43 — PTC3 TxD2
64 48 44 — PTC5 RxD2
1. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK
are available to TPM1, TPM2, and TPM3 respectively.
MC9S08AC60 Series Data Sheet, Rev. 2
34 Freescale Semiconductor
Chapter 3 Modes of Operation
3.1 Introduction
The operating modes of the MC9S08AC60 Series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each of the modes are described.
3.2 Features
• Active background mode for code development
• Wait mode:
— CPU shuts down to conserve power
— System clocks running
— Full voltage regulation maintained
• Stop modes:
— System clocks stopped; voltage regulator in standby
— Stop2 — Partial power down of internal circuits, RAM contents retained
— Stop3 — All internal circuits powered for fast recovery
3.3 Run Mode
This is the normal operating mode for the MC9S08AC60 Series. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset.
3.4 Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip ICE debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
• When the BKGD/MS pin is low at the rising edge of reset
• When a BACKGROUND command is received through the BKGD pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
• When encountering a DBG breakpoint
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 35
Chapter 3 Modes of Operation
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user’s application program.
Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed when the MCU is in the active background
mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can only be ex ecuted while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user’s application program (GO)
3.5 Wait Mode
W ait mode is entered by e xecuting a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
3.6 Stop Modes
One of two stop modes is entered upon execution of a ST OP instruction when the STOPE bit in the system
option register is set. In both stop modes, all internal clocks are halted. If the STOPE bit is not set when
the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal
opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
Some HCS08 devices that are designed for low v oltage operation (1.8V to 3.6V) also include stop1 mode.
The MC9S08AC60 Series of devices operates at 2.7 V to 5.5 V and does not include stop1 mode.
MC9S08AC60 Series Data Sheet, Rev. 2
36 Freescale Semiconductor
Table 3-1 summarizes the behavior of the MCU in each of the stop modes.
Table 3-1. Stop Mode Behavior
CPU, Digital
Mode PPDC
Peripherals,
FLASH
RAM ICG ADC Regulator I/O Pins RTI
Chapter 3 Modes of Operation
Stop2 1 Off Standby Off Disabled Standby States
1
Stop3 0 Standby Standby Off
1
Crystal oscillator can be configured to run in stop3. Please see the ICG registers.
Optionally on Standby States
held
held
Optionally on
Optionally on
3.6.1 Stop2 Mode
The stop2 mode provides very low standby power consumption and maintains the contents of RAM and
the current state of all of the I/O pins. T o enter stop2, the user must e xecute a ST OP instruction with stop2
selected (PPDC = 1) and stop mode enabled (STOPE = 1). In addition, the LVD must not be enabled to
operate in stop (LVDSE = LVDE = 1). If the LVD is enabled in stop, then the MCU enters stop3 upon the
execution of the STOP instruction regardless of the state of PPDC.
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as an y other
memory-mapped registers which they want to restore after exit of stop2, to locations in RAM. Upon exit
of stop2, these values can be restored by user software before pin latches are opened.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage re gulator are turned
off, except for the RAM. The v oltage regulator is in a lo w-power standby state, as is the ADC. Upon entry
into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting
stop2 mode until a logic 1 is written to PPDACK in SPMSC2.
Exit from stop2 is done by asserting either of the wake-up pins:
RESET or IRQ, or by an RTI interrupt.
IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured before
entering stop2.
Upon wake-up from stop2 mode, the MCU will start up as from a power -on reset (POR) e xcept pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is
written to PPDACK in SPMSC2.
To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the
contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to
the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the
register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch
to their reset states.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 37
Chapter 3 Modes of Operation
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, b ut in
that case the real-time interrupt cannot wake the MCU from stop.
3.6.2 Stop3 Mode
To enter stop3, the user must execute a STOP instruction with stop3 selected (PPDC = 0) and stop mode
enabled (STOPE = 1). Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator
itself, are halted. The ICG enters its standby state, as does the voltage regulator and the ADC. The states
of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are
not latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic
driving the pins being maintained.
Exit from stop3 is done by asserting
RESET, an asynchronous interrupt pin, or through the real-time
interrupt (RTI). The asynchronous interrupt pins are the IRQ or KBI pins. Exit from stop3 can also
facilitated by the SCI reciever interrupt, the ADC, and LVI.
If stop3 is exited by means of the
RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector . Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, b ut in
that case the real-time interrupt cannot wake the MCU from stop.
3.6.3 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in Chapter 16, “Development Support” of this data sheet. If ENBDM is set when
the CPU executes a STOP instruction, the system clocks to the background deb ug logic remain active when
the MCU enters stop mode so background debug communication is still possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation. If the user
attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
MC9S08AC60 Series Data Sheet, Rev. 2
38 Freescale Semiconductor
Chapter 3 Modes of Operation
commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the
background debug mode is enabled.
Table 3-2. BDM Enabled Stop Mode Behavior
CPU, Digital
Mode PPDC
Peripherals,
FLASH
RAM ICG ADC Regulator I/O Pins RTI
Stop3 x Standby Standby Active Optionally on Active States
held
Optionally on
3.6.4 LVD Enabled in Stop Mode
The L VD system is capable of generating either an interrupt or a reset when the supply voltage drops belo w
the LVD voltage. If the L VD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage
regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for
stop, the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when the
LVD is enabled.
Table 3-3. LVD Enabled Stop Mode Behavior
CPU, Digital
Mode PPDC
Stop3 x Standby Standby Off Optionally on Active States
Peripherals,
FLASH
RAM ICG ADC Regulator I/O Pins RTI
Optionally on
held
3.6.5 On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop2
Mode,” and Section 3.6.2, “Stop3 Mode,” for specific information on system behavior in stop modes.
Table 3-4. Stop Mode Behavior
Peripheral
Stop2 Stop3
CPU Off Standby
RAM Standby Standby
FLASH Off Standby
Parallel Port Registers Off Standby
ADC Off Optionally On
ICG Off Optionally On
IIC Off Standby
RTI Optionally on
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 39
Mode
1
2
3
Optionally on
3
Chapter 3 Modes of Operation
Table 3-4. Stop Mode Behavior (continued)
Peripheral
Mode
Stop2 Stop3
SCI Off Standby
SPI Off Standby
TPM Off Standby
System Voltage Regulator Standby Standby
I/O Pins States Held States Held
1
Requires the asynchronous ADC clock and LVD to be enabled, else in standby.
2
OSCSTEN set in ICGC1, else in standby.
3
RTIS[2:0] in SRTISC does not equal 0 before entering stop, else off.
MC9S08AC60 Series Data Sheet, Rev. 2
40 Freescale Semiconductor
Chapter 4 Memory
4.1 MC9S08AC60 Series Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08AC60 Series series of MCUs consists of RAM,
FLASH program memory for nonv olatile data storage, plus I/O and control/status re gisters. The re gisters
are divided into three groups:
• Direct-page registers ($0000 through $006F)
• High-page registers ($1800 through $185F)
• Nonvolatile registers ($FFB0 through $FFBF)
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 41
Chapter 4 Memory
$0000
DIRECT PAGE REGISTERS
$006F
$0070
$086F
$0870
$17FF
$1800
HIGH PAGE REGISTERS
$185F
$1860
RAM
2048 BYTES
FLASH
3984 BYTES
FLASH
59,296 BYTES
$0000
$006F
$0070
$086F
$0870
$17FF
$1800
$185F
$1860
$3FFF
$4000
DIRECT PAGE REGISTERS
RAM
2048 BYTES
RESERVED
3984 BYTES
HIGH PAGE REGISTERS
RESERVED
10,144 BYTES
FLASH
49,152 BYTES
$0000
$006F
$0070
$086F
$0870
$17FF
$1800
$185F
$1860
$7FFF
$8000
DIRECT PAGE REGISTERS
RAM
2048 BYTES
RESERVED
3984 BYTES
HIGH PAGE REGISTERS
RESERVED
26,528 BYTES
FLASH
32,768 BYTES
$FFFF
MC9S08AC60
$FFFF
MC9S08AC48
Figure 4-1. MC9S08AC60 Series Memory Map
$FFFF
MC9S08AC32
MC9S08AC60 Series Data Sheet, Rev. 2
42 Freescale Semiconductor
Chapter 4 Memory
4.1.1 Reset and Interrupt Vector Assignments
Figure 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale-provided equate file for the MC9S08AC60 Series. For more details
about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets,
Interrupts, and System Configuration.”
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low)
0xFFC0:FFC1
through
0xFFC4:FFC5
0xFFC6:FFC7 TPM3 overflow Vtpm3ovf
0xFFC8:FFC9 TPM3 channel 1 Vtpm3ch1
0xFFCA:FFCB TPM3 channel 0 Vtpm3ch0
0xFFCC:FFCD RTI Vrti
0xFFCE:FFCF IIC1 Viic1
0xFFD0:FFD1 ADC1 conversion Vadc1
0xFFD2:FFD3 KBI1 Vkeyboard1
0xFFD4:FFD5 SCI2 transmit Vsci2tx
0xFFD6:FFD7 SCI2 receive Vsci2rx
0xFFD8:FFD9 SCI2 error Vsci2err
0xFFDA:FFDB SCI1 transmit Vsci1tx
0xFFDC:FFDD SCI1 receive Vsci1rx
0xFFDE:FFDF SCI1 error Vsci1err
0xFFE0:FFE1 SPI1 Vspi1
0xFFE2:FFE3 TPM2 overflow Vtpm2ovf
0xFFE4:FFE5 TPM2 channel 1 Vtpm2ch1
0xFFE6:FFE7 TPM2 channel 0 Vtpm2ch0
0xFFE8:FFE9 TPM1 overflow Vtpm1ovf
0xFFEA:FFEB TPM1 channel 5 Vtpm1ch5
0xFFEC:FFED TPM1 channel 4 Vtpm1ch4
0xFFEE:FFEF TPM1 channel 3 Vtpm1ch3
0xFFF0:FFF1 TPM1 channel 2 Vtpm1ch2
0xFFF2:FFF3 TPM1 channel 1 Vtpm1ch1
0xFFF4:FFF5 TPM1 channel 0 Vtpm1ch0
0xFFF6:FFF7 ICG Vicg
0xFFF8:FFF9 Low voltage detect Vlvd
0xFFFA:FFFB IRQ Virq
0xFFFC:FFFD SWI Vswi
0xFFFE:FFFF Reset Vreset
(available for user program)
Vector Vector Name
Unused Vector Space
—
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 43
Chapter 4 Memory
4.2 Register Addresses and Bit Assignments
The registers in the MC9S08AC60 Series are divided into these three groups:
• Direct-page registers are located in the first 112 locations in the memory map, so they are
accessible with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and variables.
• The nonvolatile register area consists of a block of 16 locations in FLASH memory at
$FFB0–$FFBF.
Nonvolatile register locations include:
— Three values which are loaded into working registers at reset
— An 8-byte backdoor comparison key which optionally allows a user to gain controlled access
to secure memory
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only
requires the lower byte of the address. Because of this, the lower byte of the address in column one is
shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In
Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart
from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with
a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.
MC9S08AC60 Series Data Sheet, Rev. 2
44 Freescale Semiconductor
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
Address Register Name Bit 7 654321Bit 0
0x0000 PTAD
0x0001 PTADD
0x0002 PTBD
0x0003 PTBDD
0x0004 PTCD
0x0005 PTCDD
0x0006 PTDD
0x0007 PTDDD
0x0008 PTED
0x0009 PTEDD
0x000A PTFD
0x000B PTFDD
0x000C PTGD
0x000D PTGDD
0x000E–
0x000F
Reserved
0x0010 ADC1SC1
0x0011 ADC1SC2
0x0012 ADC1RH
0x0013 ADC1RL
0x0014 ADC1CVH
0x0015 ADC1CVL
0x0016 ADC1CFG
0x0017 APCTL1
0x0018 APCTL2
0x0019–
0x001B
Reserved
0x001C IRQSC
0x001D Reserved
0x001E KBISC
0x001F KBIPE
0x0020 TPM1SC
0x0021 TPM1CNTH
0x0022 TPM1CNTL
0x0023 TPM1MODH
0x0024 TPM1MODL
0x0025 TPM1C0SC
0x0026 TPM1C0VH
0x0027 TPM1C0VL
0x0028 TPM1C1SC
PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
0 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
0 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
0 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
0 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
—
—
COCO AIEN ADCO ADCH
ADACT ADTRG ACFE ACFGT 0 0 R R
0 0 0 0 0 0 ADR9 ADR8
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0 0 0 0 0 0 ADCV9 ADCV8
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
ADLPC ADIV ADLSMP MODE ADICLK
ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8
—
—
0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD
— — — — — — — —
KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBF KBACK KBIE KBIMOD
KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 45
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)
Address Register Name Bit 7 654321Bit 0
0x0029 TPM1C1VH
0x002A TPM1C1VL
0x002B TPM1C2SC
0x002C TPM1C2VH
0x002D TPM1C2VL
0x002E TPM1C3SC
0x002F TPM1C3VH
0x0030 TPM1C3VL
0x0031 TPM1C4SC
0x0032 TPM1C4VH
0x0033 TPM1C4VL
0x0034 TPM1C5SC
0x0035 TPM1C5VH
0x0036 TPM1C5VL
0x0037 Reserved
0x0038 SCI1BDH
0x0039 SCI1BDL
0x003A SCI1C1
0x003B SCI1C2
0x003C SCI1S1
0x003D SCI1S2
0x003E SCI1C3
0x003F SCI1D
0x0040 SCI2BDH
0x0041 SCI2BDL
0x0042 SCI2C1
0x0043 SCI2C2
0x0044 SCI2S1
0x0045 SCI2S2
0x0046 SCI2C3
0x0047 SCI2D
0x0048 ICGC1
0x0049 ICGC2
0x004A ICGS1
0x004B ICGS2
0x004C ICGFLTU
0x004D ICGFLTL
0x004E ICGTRM
0x004F Reserved
0x0050 SPI1C1
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH3F CH3IE MS3B MS3A ELS3B ELS3A 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH4F CH4IE MS4B MS4A ELS4B ELS4A 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH3F CH5IE MS5B MS5A ELS5B ELS5A 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
— — — — — — — —
LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
LOOPS SCISWAI RSRC M WAKE ILT PE PT
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE PF
LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF
R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE
Bit 7 654321Bit 0
LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
LOOPS SCISWAI RSRC M WAKE ILT PE PT
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE PF
LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF
R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE
Bit 7 654321Bit 0
HGO RANGE REFS CLKS OSCSTEN LOCD 0
LOLRE MFD LOCRE RFD
CLKST REFST LOLS LOCK LOCS ERCS ICGIF
0 0 0 0 0 0 0 DCOS
0 0 0 0FLT
FLT
TRIM
— — — — — — — —
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
MC9S08AC60 Series Data Sheet, Rev. 2
46 Freescale Semiconductor
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
Address Register Name Bit 7 654321Bit 0
0x0051 SPI1C2
0x0052 SPI1BR
0x0053 SPI1S
0x0054 Reserved
0x0055 SPI1D
0x0056 CRCH
0x0057 CRCL
0x0058 IIC1A
0x0059 IIC1F
0x005A IIC1C1
0x005B IIC1S
0x005C IIC1D
0x005D IIC1C2
0x005E–
0x005F
Reserved
0x0060 TPM2SC
0x0061 TPM2CNTH
0x0062 TPM2CNTL
0x0063 TPM2MODH
0x0064 TPM2MODL
0x0065 TPM2C0SC
0x0066 TPM2C0VH
0x0067 TPM2C0VL
0x0068 TPM2C1SC
0x0069 TPM2C1VH
0x006A TPM2C1VL
0x006B–
0x006F
Reserved
0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0
0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0
SPRF 0 SPTEF MODF 0 0 0 0
0 0 0 0 0 0 0 0
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
ADDR 0
MULT ICR
IICEN IICIE MST TX TXAK RSTA 0 0
TCF IAAS BUSY ARBL 0 SRW IICIF RXAK
DA TA
GCAEN ADEXT 0 0 0 AD10 AD9 AD8
—
—
TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
Table 4-3. High-Page Register Summary (Sheet 1 of 3)
Address Register Name Bit 7 654321Bit 0
0x1800 SRS
0x1801 SBDFR
0x1802 SOPT
0x1803 SMCLK
0x1804 –
0x1805
Reserved
0x1806 SDIDH
Freescale Semiconductor 47
POR PIN COP ILOP 0 ICG LVD 0
0 0 0 0 0 0 0 BDFR
COPE COPT STOPE — 0 0 — —
0 0 0 MPE 0 MCSEL
—
—
REV3 REV2 REV1 REV0 ID11 ID10 ID9 ID8
—
—
MC9S08AC60 Series Data Sheet, Rev. 2
—
—
—
—
—
—
—
—
—
—
—
—
Chapter 4 Memory
Table 4-3. High-Page Register Summary (Sheet 2 of 3)
Address Register Name Bit 7 654321Bit 0
0x1807 SDIDL
0x1808 SRTISC
0x1809 SPMSC1
0x180A SPMSC2
0x180B Reserved
0x180C SOPT2
0x180D–
0x180F
Reserved
0x1810 DBGCAH
0x1811 DBGCAL
0x1812 DBGCBH
0x1813 DBGCBL
0x1814 DBGFH
0x1815 DBGFL
0x1816 DBGC
0x1817 DBGT
0x1818 DBGS
0x1819–
0x181F
Reserved
0x1820 FCDIV
0x1821 FOPT
0x1822 Reserved
0x1823 FCNFG
0x1824 FPROT
0x1825 FSTAT
0x1826 FCMD
0x1827–
0x182F
Reserved
0x1830 TPM3SC
0x1831 TPM3CNTH
0x1832 TPM3CNTL
0x1833 TPM3MODH
0x1834 TPM3MODL
0x1835 TPM3C0SC
0x1836 TPM3C0VH
0x1837 TPM3C0VL
0x1838 TPM3C1SC
0x1839 TPM3C1VH
0x183A TPM3C1VL
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RTIF RTIACK RTICLKS RTIE 0 RTIS2 RTIS1 RTIS0
—
—
—
—
—
—
1
BGBE
LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0
LVWF LVWACK LVDV LVWV PPDF PPDACK — PPDC
— — — — — — — —
COPCLKS — — —
—
—
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN
TRGSEL BEGIN 0 0 TRG3 TRG2 TRG1 TRG0
AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0
—
—
DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
KEYEN FNORED 0 0 0 0 SEC01 SEC00
— — — — — — — —
0 0 KEYACC 0 0 0 0 0
FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS
FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0
—
—
TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TPMCCFG
—
—
—
—
—
—
— — —
—
—
—
—
—
—
—
—
—
—
—
—
MC9S08AC60 Series Data Sheet, Rev. 2
48 Freescale Semiconductor
Chapter 4 Memory
Table 4-3. High-Page Register Summary (Sheet 3 of 3)
Address Register Name Bit 7 654321Bit 0
0x183B
0x183F
Reserved
0x1840 PTAPE
0x1841 PTASE
0x1842 PTADS
0x1843 Reserved
0x1844 PTBPE
0x1845 PTBSE
0x1846 PTBDS
0x1847 Reserved
0x1848 PTCPE
0x1849 PTCSE
0x184A PTCDS
0x184B Reserved
0x184C PTDPE
0x184D PTDSE
0x184E PTDDS
0x184F Reserved
0x1850 PTEPE
0x1851 PTESE
0x1852 PTEDS
0x1853 Reserved
0x1854 PTFPE
0x1855 PTFSE
0x1856 PTFDS
0x1857 Reserved
0x1858 PTGPE
0x1859 PTGSE
0x185A PTGDS
0x185B–
0x185F
1
This reserved bit must always be written to 0.
Reserved
—
—
PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
— — — — — — — —
PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
— — — — — — — —
0 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
0 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
0 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0
— — — — — — — —
PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
— — — — — — — —
PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0
— — — — — — — —
PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0
— — — — — — — —
0 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
0 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
0 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers
include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources.
During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH
memory are transferred into corresponding FPRO T and FOPT working re gisters in the high-page registers
to control security and block protection options.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 49
Chapter 4 Memory
Table 4-4. Nonvolatile Register Summary
Address Register Name Bit 7 654321Bit 0
$FFB0 –
$FFB7
$FFB8 –
$FFBB
$FFBC Reserved for stor-
$FFBD NVPROT
$FFBE Reserved for stor-
$FFBF NVOPT
NVBACKKEY
Reserved
age of 250 kHz
ICGTRM value
age of 243 kHz
ICGTRM value
8-Byte Comparison Key
— — — — — — — —
— — — — — — — —
FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS
— — — — — — — —
KEYEN FNORED 0 0 0 0 SEC01 SEC00
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security . This key mechanism can be accessed only through user code running in secure
memory . (A security ke y cannot be entered directly through background deb ug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the FLASH if needed (normally through the background
debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC01:SEC00) to the unsecured state (1:0).
4.3 RAM
The MC9S08AC60 Series includes static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on, the
contents of RAM are uninitialized. RAM data is unaffected by any reset pro vided that the supply voltage
does not drop below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08AC60 Series, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale-provided equate file).
LDHX #RamLast+1 ;point one past RAM
TXS ;SP<-(H:X-1)
MC9S08AC60 Series Data Sheet, Rev. 2
50 Freescale Semiconductor
Chapter 4 Memory
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See Section 4.5, “Security” for a detailed
description of the security feature.
4.4 FLASH
The FLASH memory is intended primarily for program storage. In-circuit programming allows the
operating program to be loaded into the FLASH memory after final assembly of the application product.
It is possible to program the entire array through the single-wire background debug interface. Because no
special voltages are needed for FLASH erase and programming operations, in-application programming
is also possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1/D.
4.4.1 Features
Features of the FLASH memory include:
• FLASH Size
— MC9S08AC60 — 61268 bytes (120 pages of 512 bytes each)
— MC9S08AC48 — 49152 bytes (96 pages of 512 bytes each)
— MC9S08AC32 — 32768 bytes (64 pages of 512 bytes each)
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection
• Security feature for FLASH and RAM
• Auto power-down for low-frequency read accesses
4.4.2 Program and Erase Times
Before any program or erase command can be accepted, the FLASH clock divider re gister (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (f
200 kHz (see Table 4.6.1). This register can be written only once, so normally this write is done during
reset initialization. FCDIV cannot be written if the access error flag, F A CCERR in FSTA T, is set. The user
must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting
clock (1/f
) is used by the command processor to time program and erase pulses. An integer number
FCLK
of these timing pulses is used by the command processor to complete a program or erase command.
) between 150 kHz and
FCLK
Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (f
). The time for one cycle of FCLK is t
FCLK
of cycles of FCLK and as an absolute time for the case where t
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 51
FCLK
= 1/f
FCLK
. The times are shown as a number
FCLK
= 5 μs. Program and erase times
Chapter 4 Memory
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-5. Program and Erase Times
Parameter Cycles of FCLK Time if FCLK = 200 kHz
Byte program 9 45 μs
Byte program (burst) 4
Page erase 4000 20 ms
Mass erase 20,000 100 ms
1
Excluding start/end overhead
20 μs
1
4.4.3 Program and Erase Command Execution
The steps for executing any of the commands are listed belo w . The FCDIV re gister must be initialized and
any error flags cleared before beginning command execution. The command execution steps are:
1. Write a data value to an address in the FLASH array. The address and data information from this
write is latched into the FLASH interface. This write is a required first step in any command
sequence. For erase and blank check commands, the value of the data is not important. For page
erase commands, the address may be any address in the 512-byte page of FLASH to be erased. For
mass erase and blank check commands, the address can be any address in the FLASH memory.
Whole pages of 512 bytes are the smallest blocks of FLASH that may be erased. In the 60K
version, there are two instances where the size of a block that is accessible to the user is less than
512 bytes: the first page following RAM, and the first page following the high page re gisters. These
pages are overlapped by the RAM and high page registers, respectively.
NOTE
Do not program any byte in the FLASH more than once after a successful
erase operation. Reprogramming bits in a byte which is already
programmed is not allowed without first erasing the page in which the byte
resides or mass erasing the entire FLASH memory. Programming without
first erasing may disturb data stored in the FLASH.
2. Write the command code for the desired command to FCMD. The five valid commands are blank
check ($05), byte program ($20), burst program ($25), page erase ($40), and mass erase ($41).
The command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to
the memory array and before writing the 1 that clears FCBEF and launches the complete command.
Aborting a command in this way sets the FACCERR access error flag which must be cleared before
starting a new command.
A strictly monitored procedure must be adhered to, or the command will not be accepted. This minimizes
the possibility of any unintended change to the FLASH memory contents. The command complete flag
(FCCF) indicates when a command is complete. The command sequence must be completed by clearing
MC9S08AC60 Series Data Sheet, Rev. 2
52 Freescale Semiconductor
Chapter 4 Memory
FCBEF to launch the command. Figure 4-2 is a flowchart for executing all of the commands except for
burst programming. The FCDIV register must be initialized before using any FLASH commands. This
must be done only once following a reset.
START
FACCERR ?
CLEAR ERROR
WRITE TO FCDIV
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF
FPVIO OR
FACCERR ?
0
(1)
NO
FCCF ?
1
DONE
0
(1)
Only required once
after reset.
(2)
Wait at least four bus cycles before
(2)
checking FCBEF or FCCF.
YES
ERROR EXIT
Figure 4-2. FLASH Program and Erase Flowchart
4.4.4 Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the FLASH
array does not need to be disabled between program operations. Ordinarily, when a program or erase
command is issued, an internal charge pump associated with the FLASH memory must be enabled to
supply high voltage to the array. Upon completion of the command, the charge pump is turned of f. When
a burst program command is issued, the charge pump is enabled and then remains enabled after completion
of the burst program operation if the following two conditions are met:
1. The next burst program command has been queued before the current program operation has
completed.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 53
Chapter 4 Memory
2. The next sequential address selects a byte on the same physical row as the current byte being
programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by
addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero.
The first byte of a series of sequential bytes being programmed in burst mode will take the same amount
of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst
program time provided that the conditions above are met. In the case the next sequential address is the
beginning of a new ro w, the program time for that byte will be the standard time instead of the burst time.
This is because the high voltage to the array must be disabled and then enabled again. If a new burst
command has not been queued before the current command completes, then the charge pump will be
disabled and high voltage removed from the array.
START
FACCERR ?
1
CLEAR ERROR
WRITE TO FCDIV
FCBEF ?
1
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF
FPVIO OR
FACCERR ?
YES
NEW BURST COMMAND ?
NO
NO
0
(1)
(2)
(1)
Only required once
after reset.
0
(2)
Wait at least four bus cycles before
checking FCBEF or FCCF.
YES
ERROR EXIT
0
FCCF ?
1
DONE
Figure 4-3. FLASH Burst Program Flowchart
MC9S08AC60 Series Data Sheet, Rev. 2
54 Freescale Semiconductor
Chapter 4 Memory
4.4.5 Access Errors
An access error occurs whenever the command execution protocol is violated.
• Any of the following specific actions will cause the access error flag (FACCERR) in FSTA T to be
set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can
be processed.
• Writing to a FLASH address before the internal FLASH clock frequency has been set by writing
to the FCDIV register
• Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
• Writing a second time to a FLASH address before launching the previous command (There is only
one write to FLASH for every command.)
• Writing a second time to FCMD before launching the previous command (There is only one write
to FCMD for every command.)
• Writing to any FLASH control register other than FCMD after writing to a FLASH address
• Writing any command code other than the five allowed codes ($05, $20, $25, $40, or $41) to
FCMD
• Writing any FLASH control register other than the write to FSTA T (to clear FCBEF and launch the
command) after writing the command to FCMD
• The MCU enters stop mode while a program or erase command is in progress (The command is
aborted.)
• Writing the byte program, burst program, or page erase command code ($20, $25, or $40) with a
background debug command while the MCU is secured (The background debug controller can
only do blank check and mass erase commands when the MCU is secure.)
• Writing 0 to FCBEF to cancel a partial command
4.4.6 FLASH Block Protection
Block protection prevents program or erase changes for FLASH memory locations in a designated address
range. Mass erase is disabled when any block of FLASH is protected. The MC9S08AC60 Series allows a
block of memory at the end of FLASH, and/or the entire FLASH memory to be block protected. A disable
control bit and a 3-bit control field, allows the user to set the size of this block. A separate control bit allows
block protection of the entire FLASH memory array. All seven of these control bits are located in the
FPROT register (see Section 4.6.4, “FLASH Protection Register (FPROT and NVPROT)”).
At reset, the high-page register (FPROT) is loaded with the contents of the NVPROT location which is in
the nonvolatile register block of the FLASH memory. The value in FPROT cannot be changed directly
from application software so a runaway program cannot alter the block protection settings. If the last 512
bytes of FLASH which includes the NVPROT register is protected, the application program cannot alter
the block protection settings (intentionally or unintentionally). The FPROT control bits can be written by
background debug commands to allow a way to erase a protected FLASH memory.
One use for block protection is to block protect an area of FLASH memory for a bootloader program. This
bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because
the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and
reprogram operation.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 55
Chapter 4 Memory
4.4.7 Vector Redirection
Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector
redirection allows users to modify interrupt vector information without unprotecting bootloader and reset
vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register
located at address $FFBF to zero. For redirection to occur, at least some portion b ut not all of the FLASH
memory must be block protected by programming the NVPRO T register located at address $FFBD. All of
the interrupt vectors (memory locations $FFC0–$FFFD) are redirected, while the reset vector
($FFFE:FFFF) is not. When more than 32K is protected, vector redirection must not be enabled.
For example, if 512 bytes of FLASH are protected, the protected address region is from $FE00 through
$FFFF. The interrupt vectors ($FFC0–$FFFD) are redirected to the locations $FDC0–$FDFD. Now, if an
SPI interrupt is taken for instance, the values in the locations $FDE0:FDE1 are used for the vector instead
of the values in the locations $FFE0:FFE1. This allows the user to reprogram the unprotected portion of
the FLASH with new program code including new interrupt v ector values while leaving the protected area,
which includes the default vector locations, unchanged.
4.5 Security
The MC9S08AC60 Series includes circuitry to pre vent unauthorized access to the contents of FLASH and
RAM memory . When security is engaged, FLASH and RAM are considered secure resources. Direct-page
registers, high-page registers, and the background debug controller are considered unsecured resources.
Programs executing within secure memory have normal access to any MCU memory locations and
resources. Attempts to access a secure memory location with a program executing from an unsecured
memory space or through the background debug interface are blocked (writes are ignored and reads return
all 0s).
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in
the FOPT register . During reset, the contents of the nonvolatile location NV OPT are copied from FLASH
into the working FOPT register in high-page register space. A user engages security by programming the
NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state
disengages security while the other three combinations engage security. Notice the erased state (1:1)
makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to
immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU
to remain unsecured after a subsequent reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can still be used for background memory access commands, but the MCU cannot enter active
background mode except by holding BKGD/MS low at the rising edge of reset.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor
security key. If the non volatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there
is no way to disengage security without completely erasing all FLASH locations. If KEYEN is 1, a secure
user program can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret writes to
the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to
be compared against the key rather than as the first step in a FLASH program or erase command.
MC9S08AC60 Series Data Sheet, Rev. 2
56 Freescale Semiconductor
Chapter 4 Memory
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations.
These writes must be done in order, starting with the value for NVBACKKEY and ending with
NVBA CKKEY+7. STHX should not be used for these writes because these writes cannot be done
on adjacent bus cycles. User software normally would get the key codes from outside the MCU
system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the
key stored in the FLASH locations, SEC01:SEC00 are automatically changed to 1:0 and security
will be disengaged until the next reset.
The security key can be written only from RAM, so it cannot be entered through background commands
without the cooperation of a secure user program. The FLASH memory cannot be accessed by read
operations while KEYACC is set.
The backdoor comparison key (NVB A CKKEY through NVB A CKKEY+7) is located in FLASH memory
locations in the nonv olatile register space so users can program these locations just as they w ould program
any other FLASH memory location. The nonvolatile registers are in the same 512-byte block of FLASH
as the reset and interrupt vectors, so block protecting that space also block protects the backdoor
comparison key. Block protects cannot be changed from user application programs, so if the vector space
is block protected, the backdoor security key mechanism cannot permanently change the block protect,
security settings, or the backdoor key.
Security can always be disengaged through the background debug interface by performing these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with background
debug commands, not from application software.
2. Mass erase FLASH, if necessary.
3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next
reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0.
4.6 FLASH Registers and Control Bits
The FLASH module has nine 8-bit registers in the high-page register space, three locations in the
nonvolatile register space in FLASH memory that are copied into three corresponding high-page control
registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and
Table 4-4 for the absolute address assignments for all FLASH registers. This section refers to registers and
control bits only by their names. A Freescale-provided equate or header file normally is used to translate
these names into the appropriate absolute addresses.
4.6.1 FLASH Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written
only one time. Before any erase or programming operations are possible, write to this register to set the
frequency of the clock for the nonvolatile memory system within acceptable limits.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 57
Chapter 4 Memory
76543210
R DIVLD
PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-4. FLASH Clock Divider Register (FCDIV)
Table 4-6. FCDIV Field Descriptions
Field Description
7
DIVLD
6
PRDIV8
5
DIV[5:0]
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
Divisor for FLASH Clock Divider — The FLASH clock divider divides the b us rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5 μs
to 6.7 μs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See Equation 4-1 and Equation 4-2. Table 4-7
sho ws the appropriate values for PRDIV8 and
DIV5:DIV0 for selected bus frequencies.
if PRDIV8 = 0 — f
if PRDIV8 = 1 — f
FCLK
FCLK
= f
= f
÷ ([DIV5:DIV0] + 1) Eqn. 4-1
Bus
÷ (8 × ([DIV5:DIV0] + 1)) Eqn. 4-2
Bus
Table 4-7. FLASH Clock Divider Settings
f
Bus
PRDIV8
(Binary)
20 MHz 1 12 192.3 kHz 5.2 μs
10 MHz 0 49 200 kHz 5 μs
8 MHz 0 39 200 kHz 5 μs
4 MHz 0 19 200 kHz 5 μs
2 MHz 0 9 200 kHz 5 μs
1 MHz 0 4 200 kHz 5 μs
200 kHz 0 0 200 kHz 5 μs
150 kHz 0 0 150 kHz 6.7 μs
DIV5:DIV0
(Decimal)
f
FCLK
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
MC9S08AC60 Series Data Sheet, Rev. 2
58 Freescale Semiconductor
Chapter 4 Memory
4.6.2 FLASH Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. Bits 5
through 2 are not used and always read 0. This register may be read at any time, b ut writes have no meaning
or effect. T o change the v alue in this register , erase and reprogram the NVOPT location in FLASH memory
as usual and then issue a new MCU reset.
R
W
Reset This register is loaded from nonvolatile location NVOPT during reset.
76543210
KEYEN FNORED
= Unimplemented or Reserved
0000SEC01 SEC00
Figure 4-5. FLASH Options Register (FOPT)
Table 4-8. FOPT Field Descriptions
Field Description
7
KEYEN
6
FNORED
1:0
SEC0[1:0]
Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to
disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM
commands cannot be used to write key comparison values that would unlock the bac kdoor key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5, “Security.”
0 No backdoor key access allowed.
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through
NVBACKKEY+7, in that order), security is temporarily disengaged until the next MCU reset.
Vector Redirection Disable — When this bit is 1, vector redirection is disabled.
0 Vector redirection enabled.
1 Vector redirection disabled.
Security State Code — This 2-bit field determines the security state of the MCU as shown below. When the
MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any
unsecured source including the background debug interf ace. For more detailed information about security , ref er
to Section 4.5, “Security.”
00 Secure
01 Secure
10 Unsecured
11 Secure
SEC0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of FLASH.
4.6.3 FLASH Configuration Register (FCNFG)
Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 59
Chapter 4 Memory
R0 0
76543210
00000
KEYACC
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-6. FLASH Configuration Register (FCNFG)
Table 4-9. FCNFG Field Descriptions
Field Description
5
KEYACC
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5, “Security.”
0 Writes to $FFB0–$FFB7 are interpreted as the start of a FLASH programming or erase command.
1 Writes to NVBACKKEY ($FFB0–$FFB7) are interpreted as comparison key writes.
Reads of the FLASH return invalid data.
MC9S08AC60 Series Data Sheet, Rev. 2
60 Freescale Semiconductor
Chapter 4 Memory
4.6.4 FLASH Protection Register (FPROT and NVPROT)
During reset, the contents of the nonv olatile location NVPROT is copied from FLASH into FPROT. This
register may be read at any time, but user program writes have no meaning or effect. Background debug
commands can write to FPROT.
76543210
R FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS
W
Reset This register is loaded from nonvolatile location NVPROT during reset.
1
Background commands can be used to change the contents of these bits in FPROT.
Field Description
(1)
(1) (1) (1) (1) (1) (1) (1)
Figure 4-7. FLASH Protection Register (FPROT)
Table 4-10. FPROT Register Field Descriptions
7:1
FPS[7:1]
0
FPDIS
FLASH Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected
FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or
programmed.
FLASH Protection Disable
0 FLASH block specified by FPS[7:1] is block protected (program and erase not allowed).
1 No FLASH block is protected.
4.6.5 FLASH Status Register (FSTAT)
Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits
that can be read at any time. Writes to these bits have special meanings that are discussed in the bit
descriptions.
R
W
Reset 11000000
76543210
FCBEF
FCCF
FPVIOL FACCERR
= Unimplemented or Reserved
0 FBLANK 0 0
Figure 4-8. FLASH Status Register (FSTAT)
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 61
Chapter 4 Memory
Table 4-11. FSTAT Field Descriptions
Field Description
7
FCBEF
6
FCCF
5
FPVIOL
4
FACCERR
2
FBLANK
FLASH Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the
command buffer is empty so that a new command sequence can be executed when performing burst
programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to
the array for programming. Only burst program commands can be buffered.
0 Command buffer is full (not ready for additional commands).
1 A new burst program command may be written to the command buffer.
FLASH Command Complete Flag — FCCF is set automatically when the command buffer is empty and no
command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to
FCBEF to register a command). Writing to FCCF has no meaning or effect.
0 Command in progress
1 All commands complete
Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that
attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is
cleared by writing a 1 to FPVIOL.
0 No protection violation.
1 An attempt was made to erase or program a protected location.
Access Error Flag — FACCERR is set automatically when the proper command sequence is not followed
exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV
register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed
discussion of the exact actions that are considered access errors, see Section 4.4.5, “Access Errors. ” F A CCERR
is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
0 No access error has occurred.
1 An access error has occurred.
FLASH Verified as All Blank (Erased) Flag — FBLANK is set automatically at the conclusion of a b lank check
command if the entire FLASH array was v erified to be erased. FBLANK is cleared b y clearing FCBEF to write a
new valid command. Writing to FBLANK has no meaning or effect.
0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH array is not
completely erased.
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is
completely erased (all $FF).
4.6.6 FLASH Command Register (FCMD)
Only five command codes are recognized in normal user modes as shown in Table 4-13. Refer to
Section 4.4.3, “Program and Erase Command Execution” for a detailed discussion of FLASH
programming and erase operations.
R00000000
W FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0
Reset 00000000
62 Freescale Semiconductor
76543210
Figure 4-9. FLASH Command Register (FCMD)
MC9S08AC60 Series Data Sheet, Rev. 2
Table 4-12. FCMD Field Descriptions
Field Description
Chapter 4 Memory
7:0
FCMD[7:0]
See Table 4-13 for a description of FCMD[7:0].
Table 4-13. FLASH Commands
Command FCMD Equate File Label
Blank check $05 mBlank
Byte program $20 mByteProg
Byte program — burst mode $25 mBurstProg
Page erase (512 bytes/page) $40 mPageErase
Mass erase (all FLASH) $41 mMassErase
All other command codes are illegal and generate an access error.
It is not necessary to perform a blank check command after a mass erase operation. Only blank check is
required as part of the security unlocking mechanism.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 63
Chapter 4 Memory
MC9S08AC60 Series Data Sheet, Rev. 2
64 Freescale Semiconductor
Chapter 5
Resets, Interrupts, and System Configuration
5.1 Introduction
This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08AC60 Series. Some interrupt sources from peripheral modules are discussed in greater
detail within other chapters of this data manual. This chapter gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems with their own sections but are part of the system control logic.
5.2 Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation:
— Power-on detection (POR)
— Low voltage detection (LVD) with enable
— External
— COP watchdog with enable and two timeout choices
RESET pin
— Illegal opcode
— Serial command from a background debug host
• Reset status register (SRS) to indicate source of most recent reset
• Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-11)
5.3 MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
The MC9S08AC60 Series has several sources for reset:
• Power-on reset (POR)
• Low-voltage detect (LVD)
• Computer operating properly (COP) timer
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 65
Chapter 5 Resets, Interrupts, and System Configuration
• Illegal opcode detect
• Background debug forced reset
• The reset pin (
RESET)
• Clock generator loss of lock and loss of clock reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register . Whenever the MCU enters reset, the internal clock generator (ICG) module
switches to self-clocked mode with the frequency of f
Self_reset
selected. The reset pin is driven low for 34
bus cycles where the internal bus frequency is half the ICG frequency. After the 34 bus cycles are
completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low
externally . After the pin is released, it is sampled after another 38 bus c ycles to determine whether the reset
pin is the cause of the MCU reset.
5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically . If the application program gets lost and f ails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT enabling the COP watchdog (see Section 5.9.4, “System
Options Register (SOPT), ” for additional information). If the COP w atchdog is not used in an application,
it can be disabled by clearing COPE. The COP counter is reset by writing any value to the address of SRS.
This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is
decoded and sends a reset signal to the COP counter.
The COPCLKS bit in SOPT2 (see Section 5.9.10, “System Options Register 2 (SOPT2),” for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1-kHz clock source. With each clock source, there is an associated short and long
time-out controlled by COPT in SOPT. Table 5-1 summaries the control functions of the COPCLKS and
COPT bits. The COP watchdog defaults to operation from the bus clock source and the associated long
18
time-out (2
cycles).
Table 5-1. COP Configuration Options
Control Bits
COPCLKS COPT
00
01
10
11
1
Values are shown in this column based on t
Section A.10.1, “Control Timing,” for the tolerance of this value.
Clock Source COP Overflow Count
~1 kHz
~1 kHz
Bus
Bus
= 1 ms. See t
RTI
5
cycles (32 ms)
2
8
2
cycles (256 ms)
13
2
cycles
18
2
cycles
in the appendix
RTI
1
1
MC9S08AC60 Series Data Sheet, Rev. 2
66 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and System Configuration
Even if the application will use the reset default settings of COPE, COPCLKS, and COPT, the user must
write to the write-once SOPT and SOPT2 registers during reset initialization to lock in the settings. That
way, they cannot be changed accidentally if the application program gets lost. The initial writes to SOPT
and SOPT2 will reset the COP counter.
The write to SRS that services (clears) the COP counter must not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
In background debug mode, the COP counter will not increment.
When the bus clock source is selected, the COP counter does not increment while the system is in stop
mode. The COP counter resumes as soon as the MCU exits stop mode.
When the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to stop mode.
The COP counter begins from zero after the MCU exits stop mode.
5.5 Interrupts
Interrupts provide a way to sav e the current CPU status and re gisters, e x ecute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other
than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware ev ents
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. The
I bit in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after
reset which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer
and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction and
consists of:
• Saving the CPU registers on the stack
• Setting the I bit in the CCR to mask further interrupts
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending
• Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another
interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally , the I bit is restored to 0
when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit may be cleared
inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be
serviced without waiting for the first service routine to finish. This practice is not recommended for anyone
other than the most experienced programmers because it can lead to subtle program errors that are difficult
to debug.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 67
Chapter 5 Resets, Interrupts, and System Configuration
The interrupt service routine ends with a return-from-interrupt (R TI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the
stack.
NOTE
For compatibility with the M68HC08, the H register is not automatically
saved and restored. It is good programming practice to push H onto the stack
at the start of the interrupt service routine (ISR) and restore it immediately
before the RTI that is used to return from the ISR.
When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced
first (see Table 5-2).
5.5.1 Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next av ailable byte location on the stack. The current v alues of CPU re gisters are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next av ailable location on the stack which is the address that is one less than
the address where the CCR was saved. The PC v alue that is stack ed is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
UNSTACKING
ORDER
5
4
3
2
1
STACKING
ORDER
70
1
2
3
4
5
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
* High byte (H) of index register is not automatically stacked.
TOWARD LOWER ADDRESSES
SP AFTER
INTERRUPT STACKING
*
SP BEFORE
THE INTERRUPT
TOWARD HIGHER ADDRESSES
Figure 5-1. Interrupt Stack Frame
When an R TI instruction is executed, these v alues are recov ered from the stack in rev erse order . As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
T ypically, the flag should be cleared at the beginning of the ISR so that if another interrupt is generated by
this same source, it will be registered so it can be serviced after completion of the current ISR.
MC9S08AC60 Series Data Sheet, Rev. 2
68 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and System Configuration
5.5.2 External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQSC status and control register. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level e vents. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1 Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 in order for the IRQ pin to act as
the interrupt request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels
detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an
event causes an interrupt or only sets the IRQF flag which can be polled by software.
The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), configured as a pull-up
or pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-do wn,
the IRQPDD can be written to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act
as the IRQ input.
NOTE
• The voltage measured on the pulled up IRQ pin may be as low as
-0.7 V. The internal gates connected to this pin are pulled all the
V
DD
way to V
unloaded measurement of V
. All other pins with the enabled pullup resistor will have an
DD
.
DD
• When enabling the IRQ pin for use, the IRQF will be set, and should be
cleared prior to enabling the interrupt. When configuring the pin for
falling edge and level sensitivity in a 5V system, it is necessary to wait
at least 6 cycles between clearing the flag and enabling the interrupt.
5.5.2.2 Edge and Level Sensitivity
The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In this
edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the deasserted to the asserted level), b ut the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.5.3 Interrupt Vectors, Sources, and Local Masks
Table 5-2 provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 69
Chapter 5 Resets, Interrupts, and System Configuration
registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
Table 5-2. Vector Summary
Vector
Priority
Lower
Higher
Vector
No.
29 –310xFFC0/FFC1 –
28 0xFFC6/FFC7 Vtpm3ovf TPM3 TOF TOIE TPM3 overflow
27 0xFFC8/FFC9 Vtpm3ch1 TPM3 CH1F CH1IE TPM3 channel 1
26 0xFFCA/FFCB Vtpm3ch0 TPM3 CH0F CH0IF TPM3 channel 0
25 0xFFCC/FFCD Vrti System
24 0xFFCE/FFCF Viic1 IIC1 IICIF IICIE IIC1
23 0xFFD0/FFD1 Vadc1 ADC1 COCO AIEN ADC1
22 0xFFD2/FFD3 Vkeyboard 1 KBI1 KBF KBIE KBI1 pins
21 0xFFD4/FFD5 Vsci2tx SCI2 TDRE, TC TIE, TCIE SCI2 transmit
20 0xFFD6/FFD7 Vsci2rx SCI2 IDLE, RDRF,
19 0xFFD8/FFD9 Vsci2err SCI2 OR, NF, FE, PF ORIE, NFIE, FEIE,
18 0xFFDA/FFDB Vsci1tx SCI1 TDRE
17 0xFFDC/FFDD Vsci1rx SCI1 IDLE, RDRF,
16 0xFFDE/FFDF Vsci1err SCI1 OR, NF, FE, PF ORIE, NFIE, FEIE,
15 0xFFE0/FFE1 Vspi1 SPI1 SPIF, MODF,
14 0xFFE2/FFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overflow
13 0xFFE4/FFE5 Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1
12 0xFFE6/FFE7 Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0
11 0xFFE8/FFE9 Vtpm1ovf TPM1 TOF TOIE TPM1 overflow
10 0xFFEA/FFEB Vtpm1ch5 TPM1 CH5F CH5IE TPM1 channel 5
9 0xFFEC/FFED Vtpm1ch4 TPM1 CH4F CH4IE TPM1 channel 4
8 0xFFEE/FFEF Vtpm1ch3 TPM1 CH3F CH3IE TPM1 channel 3
7 0xFFF0/FFF1 Vtpm1ch2 TPM1 CH2F CH2IE TPM1 channel 2
6 0xFFF2/FFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1
5 0xFFF4/FFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0
4 0xFFF6/FFF7 Vicg ICG ICGIF
3 0xFFF8/FFF9 Vlvd System
2 0xFFFA/FFFB Virq IRQ IRQF IRQIE IRQ pin
1 0xFFFC/FFFD Vswi Core SWI Instruction — Software interrupt
0 0xFFFE/FFFF Vreset System
Address
(High/Low)
0xFFC4/0xFFC5
Vector Name Module Source Enable Description
Unused vector space
(available for user program)
RTIF RTIE Real-time
control
control
control
ILIE, RIE, LBKDIE,
LDBKDIF,
RXEDGIF
TC
LDBKDIF,
RXEDGIF
SPTEF
(LOLS/LOCS)
LVDF LVDIE Low-voltage
COP
LVD
RESET pin
Illegal opcode
RXEDGIE
PFIE
TIE
TCIE
ILIE, RIE, LBKDIE,
RXEDGIE
PFIE
SPIE, SPIE, SPTIE SPI1
LOLRE/LOCRE ICG
COPE
LVDRE
—
—
interrupt
SCI2 receive
SCI2 error
SCI1 transmit
SCI1 receive
SCI1 error
detect
Watchdog timer
Low-voltage
detect
External pin
Illegal opcode
MC9S08AC60 Series Data Sheet, Rev. 2
70 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and System Configuration
5.6 Low-Voltage Detect (LVD) System
The MC9S08AC60 Series includes a system to protect against low voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either
high (V
LVDH
) or low (V
voltage is selected by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless
the LVDSE bit is set. If LVDSE and LVDE are both set, then the MCU cannot enter stop2, and the current
consumption in stop3 with the LVD enabled will be greater.
5.6.1 Power-On Reset Operation
). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip
LVDL
When power is initially applied to the MCU, or when the supply voltage drops below the V
level, the
POR
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in
reset until the supply has risen above the V
level. Both the POR bit and the LVD bit in SRS are set
LVDL
following a POR.
5.6.2 LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
L VDRE to 1. After an LVD reset has occurred, the L VD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
either an LVD reset or POR.
5.6.3 LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE
set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur.
5.6.4 Low-Voltage Warning (LVW)
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching, but is still above, the LVD voltage. The LVW does not have an interrupt associated with it.
There are two user selectable trip voltages for the LVW , one high (V
) and one low (V
LVWH
voltage is selected by LVWV in SPMSC2. Setting the LVW trip voltage equal to the LVD trip voltage is
not recommended. Typical use of the LVW would be to select V
LVWH
and V
LVDL
.
LVWL
). The trip
5.7 Real-Time Interrupt (RTI)
The real-time interrupt function can be used to generate periodic interrupts. The RTI can accept two
sources of clocks, the 1-kHz internal clock or an external clock if available. The 1-kHz internal clock
source is completely independent of any bus clock source and is used only by the R TI module and, on some
MCUs, the COP watchdog. T o use an external clock source, it must be a vailable and acti ve. The R TICLKS
bit in SRTISC is used to select the RTI clock source.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 71
Chapter 5 Resets, Interrupts, and System Configuration
Either R TI clock source can be used when the MCU is in run, wait or stop3 mode. When using the external
oscillator in stop3, it must be enabled in stop (OSCSTEN = 1) and configured for low bandwidth operation
(RANGE = 0). Only the internal 1-kHz clock source can be selected to wake the MCU from stop2 mode.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS2:RTIS1:RTIS0) used to disable the clock source to the real-time interrupt or select one of
seven wakeup periods. The RTI has a local interrupt enable, RTIE, to allow masking of the real-time
interrupt. The RTI can be disabled by writing each bit of RTIS to zeroes, and no interrupts will be
generated. See Section 5.9.7, “System Real-Time Interrupt Status and Control Register (SRTISC),” for
detailed information about this register.
5.8 MCLK Output
The PTC2 pin is shared with the MCLK clock output. Setting the pin enable bit, MPE, causes the PTC2
pin to output a divided version of the internal MCU bus clock. The divide ratio is determined by the
MCSEL bits. When MPE is set, the PTC2 pin is forced to operate as an output pin regardless of the state
of the port data direction control bit for the pin. If the MCSEL bits are all 0s, the pin is driven low. The
slew rate and drive strength for the pin are controlled by PTCSE2 and PTCDS2, respectively. The
maximum clock output frequency is limited if slew rate control is enabled, see the electrical chapter for
pin rise and fall times with slew rate enabled.
5.9 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page re gister space
are related to reset and interrupt systems.
Refer to the direct-page register summary in Chapter 4, “Memory,” of this data sheet for the absolute
address assignments for all registers. This section refers to registers and control bits only by their names.
A Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”
MC9S08AC60 Series Data Sheet, Rev. 2
72 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and System Configuration
5.9.1 Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
76543210
R0
IRQPDD IRQEDG IRQPE
W IRQACK
Reset 00000000
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
Table 5-3. IRQSC Register Field Descriptions
Field Description
IRQF 0
IRQIE IRQMOD
6
IRQPDD
5
IRQEDG
4
IRQPE
3
IRQF
2
IRQACK
1
IRQIE
Interrupt Request (IRQ) Pull Device Disable—This read/write control bit is used to disable the internal pullup
device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and lev els or only edges. When the IRQ pin is enabled as the IRQ input and is configured
to detect rising edges, the optional pullup resistor is re-configured as an optional pulldown resistor.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down
resistor is enabled depending on the state of the IRQMOD bit.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request ev ents (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return logic 0. If edge-and-level detection is selected
(IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate a hardware
interrupt request.
0 Hardware interrupt requests from IRQF disabled (use polling).
1 Hardware interrupt requested whenever IRQF = 1.
0
IRQMOD
Freescale Semiconductor 73
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See Section 5.5.2.2, “Edge and Level Sensitivity” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
MC9S08AC60 Series Data Sheet, Rev. 2
Chapter 5 Resets, Interrupts, and System Configuration
5.9.2 System Reset Status Register (SRS)
This register includes read-only status flags to indicate the source of the most recent reset. When a debug
host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set.
Writing any value to this register address clears the COP w atchdog timer without affecting the contents of
this register. The reset state of these bits depends on what caused the MCU to reset.
76543210
R POR PIN COP ILOP Reserved ICG LVD 0
W Writing any value to SIMRS address clears COP watchdog timer.
POR10000010
LVR:
Any other
U0000010
0
(1)
(1) (1)
0
(1)
00
reset:
U = Unaffected by reset
1
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding
to sources that are not active at the time of reset will be cleared.
Figure 5-3. System Reset Status (SRS)
Table 5-4. SRS Register Field Descriptions
Field Description
7
POR
6
PIN
5
COP
Power -On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage w as
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) W atchdog — Reset was caused b y the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP
74 Freescale Semiconductor
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
MC9S08AC60 Series Data Sheet, Rev. 2
Chapter 5 Resets, Interrupts, and System Configuration
Table 5-4. SRS Register Field Descriptions (continued)
Field Description
2
ICG
1
LVD
Internal Clock Generation Module Reset — Reset was caused by an ICG module reset.
0 Reset not caused by ICG module.
1 Reset caused by ICG module.
Low Voltage Detect — If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage,
an LVD reset will occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
5.9.3 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
76543210
R00000000
W BDFR
Reset 00000000
= Unimplemented or Reserved
1
BDFR is writable only through serial background debug commands, not from user programs.
1
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
Table 5-5. SBDFR Register Field Descriptions
Field Description
0
BDFR
Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing logic 1 to this bit f orces an MCU reset. This
bit cannot be written from a user program.
5.9.4 System Options Register (SOPT)
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
should be written during the user’ s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 75
Chapter 5 Resets, Interrupts, and System Configuration
76543210
R
COPE COPT STOPE
W
Reset 11010011
= Unimplemented or Reserved
00
Figure 5-5. System Options Register (SOPT)
Table 5-6. SOPT Register Field Descriptions
Field Description
7
COPE
6
COPT
5
STOPE
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit defaults to 1 after reset.
0 Short timeout period selected.
1 Long timeout period selected.
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
5.9.5 System MCLK Control Register (SMCLK)
This register is used to control the MCLK clock output.
76543210
R000
MPE
W
Reset 00000000
= Unimplemented or Reserved
Figure 5-6. System MCLK Control Register (SMCLK)
0
MCSEL
Table 5-7. SMCLK Register Field Descriptions
Field Description
4
MPE
2:0
MCSEL
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all z ero and
MPE is set, the pin is driven low. See Equation 5-1.
MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL) Eqn. 5-1
MC9S08AC60 Series Data Sheet, Rev. 2
76 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and System Configuration
5.9.6 System Device Identification Register (SDIDH, SDIDL)
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
76543210
R ID11 ID10 ID9 ID8
W
Reset
————
0000
= Unimplemented or Reserved
Figure 5-7. System Device Identification Register — High (SDIDH)
Table 5-8. SDIDH Register Field Descriptions
Field Description
7:4
Reserved
3:0
ID[11:8]
R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
W
Reset 00011101
Bits 7:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect.
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08AC60 Series is hard coded to the value 0x001D. See also ID bits in Table 5-9.
76543210
= Unimplemented or Reserved
Figure 5-8. System Device Identification Register — Low (SDIDL)
Table 5-9. SDIDL Register Field Descriptions
Field Description
7:0
ID[7:0]
Freescale Semiconductor 77
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08AC60 Series is hard coded to the value 0x001D. See also ID bits in Table 5-8.
MC9S08AC60 Series Data Sheet, Rev. 2
Chapter 5 Resets, Interrupts, and System Configuration
5.9.7 System Real-Time Interrupt Status and Control Register (SRTISC)
This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay
selects, and three unimplemented bits, which always read 0.
76543210
R RTIF 0
W
Reset 00000000
RTIACK
= Unimplemented or Reserved
RTICLKS RTIE
Figure 5-9. System RTI Status and Control Register (SRTISC)
Table 5-10. SRTISC Register Field Descriptions
Field Description
0
RTIS2 RTIS1 RTIS0
7
RTIF
6
RTIACK
5
RTICLKS
4
RTIE
2:0
RTIS[2:0]
Real-Time Interrupt Flag — This read-only status bit indicates the periodic wakeup timer has timed out.
0 Periodic wakeup timer not timed out.
1 Periodic wakeup timer timed out.
Real-Time Interrupt Acknowledge — This write-only bit is used to acknowledge real-time interrupt request
(write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return logic 0.
Real-Time Interrupt Clock Select — This read/write bit selects the clock source for the real-time interrupt.
0 Real-time interrupt request clock source is internal 1-kHz oscillator.
1 Real-time interrupt request clock source is external clock.
Real-Time Interrupt Enable — This read-write bit enables real-time interrupts.
0 Real-time interrupts disabled.
1 Real-time interrupts enabled.
Real-Time Interrupt Delay Selects — These read/write bits select the wakeup delay for the RTI. The clock
source for the real-time interrupt is a self-clocked source which oscillates at about 1 kHz, is independent of other
MCU clock sources. Using external clock source the delays will be crystal frequency divided by value in
RTIS2:RTIS1:RTIS0. See Table 5-11.
Table 5-11. Real-Time Interrupt Frequency
RTIS2:RTIS1:RTIS0 1-kHz Clock Source Delay
0:0:0 Disable periodic wakeup timer Disable periodic wakeup timer
0:0:1 8 ms divide by 256
0:1:0 32 ms divide by 1024
0:1:1 64 ms divide by 2048
1:0:0 128 ms divide by 4096
1:0:1 256 ms divide by 8192
1:1:0 512 ms divide by 16384
1:1:1 1.024 s divide by 32768
1
Normal values are shown in this column based on f
Specifications,” f
for the tolerance on these values.
RTI
= 1 kHz. See Appendix A, “Electrical Characteristics and Timing
RTI
1
Using External Clock Source Delay
(Crystal Frequency)
MC9S08AC60 Series Data Sheet, Rev. 2
78 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and System Configuration
5.9.8 System P ower Management Status and Control 1 Register (SPMSC1)
7654321
R LVDF 0
LVDIE LVDRE
(2)
LVDSE
(2)
LVDE
(2)
1
0
BGBE
W LVDACK
Reset 00011100
= Unimplemented or Reserved
1
Bit 1 is a reserved bit that must always be written to 0.
2
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-12. SPMSC1 Register Field Descriptions
Field Description
7
LVDF
6
LVDACK
5
LVDIE
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4
LVDRE
3
LVDSE
2
LVDE
0
BGBE
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
Low-V oltage Detect Stop Enable — Pro vided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
Bandgap Buffer Enable — The BGBE bit is used to enable an internal buffer f or the bandgap v oltage reference
for use by the ADC module on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 79
Chapter 5 Resets, Interrupts, and System Configuration
5.9.9 System P ower Management Status and Control 2 Register (SPMSC2)
This register is used to report the status of the low v oltage warning function, and to configure the stop mode
behavior of the MCU.
76543210
R LVWF 0
LVDV
1
LVWV
W LVWACK PPDACK
Power-on
0
0000000
(3)
reset:
LVD
0
0UU0000
(2)
reset:
Any other
0
0UU0000
(2)
reset:
= Unimplemented or Reserved U = Unaffected by reset
1
This bit can be written only one time after POR. Additional writes are ignored.
2
This bit can be written only one time after reset. Additional writes are ignored.
3
LVWF will be set in the case when V
transitions below the trip point or after reset and V
Supply
PPDF 0
is already below V
Supply
PPDC
LVW
2
.
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
Table 5-13. SPMSC2 Register Field Descriptions
Field Description
7
LVWF
6
LVWACK
5
LVDV
4
LVWV
3
PPDF
2
PPDACK
0
PPDC
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge.
Writing a 1 to LVWACK clears LVWF to a 0 if a low voltage warning is not present.
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
LVD
LVD
= V
= V
LVDL
LVDH
).
).
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
LVW
LVW
= V
= V
LVWL
LVWH
).
).
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
Partial Power Down Control — The write-once PPDC bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.
LVD
).
LVW
).
MC9S08AC60 Series Data Sheet, Rev. 2
80 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and System Configuration
5.9.10 System Options Register 2 (SOPT2)
This high page register contains bits to configure MCU specific features on the MC9S08AC60 Series
devices.
R
W
Reset: 10001000
76543210
COPCLKS
1
000
= Unimplemented or Reserved
TPMCCFG
000
Figure 5-12. System Options Register 2 (SOPT2)
1
This bit can be written only one time after reset. Additional writes are ignored.
Table 5-14. SOPT2 Register Field Descriptions
Field Description
7
COPCLKS
3
TPMCCFG
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
TPM Clock Configuration — Configures the timer/pulse-width modulator clock signal.
0 TPMCLK is available to TPM1, TPM2, and TPM3 via the IRQ pin; TPMCLK1 and TPMCLK2 are not available.
1 TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 81
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08AC60 Series Data Sheet, Rev. 2
82 Freescale Semiconductor
Chapter 6 Parallel Input/Output
6.1 Introduction
This chapter explains software controls related to parallel input/output (I/O). The MC9S08AC60 Series
has seven I/O ports which include a total of up to 54 general-purpose I/O pins. See Chapter 2, “Pins and
Connections” for more information about the logic and hardware aspects of these pins.
Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or
keyboard interrupts. When these other modules are not controlling the port pins, they revert to
general-purpose I/O control.
NOTE
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unconnected pins to outputs so the pins
do not float.
6.2 Pin Descriptions
The MC9S08AC60 Series has a total of 54 parallel I/O pins in seven ports (PTA–PTG). Not all pins are
bonded out in all packages. Consult the pin assignment in Chapter 2, “Pins and Connections,” for a vailable
parallel I/O pins. All of these pins are available for general-purpose I/O when they are not used by other
on-chip peripheral systems.
After reset, the shared peripheral functions are disabled so that the pins are controlled by the parallel I/O.
All of the parallel I/O are configured as inputs (PTxDDn = 0). The pin control functions for each pin are
configured as follows: slew rate control disabled (PTxSEn = 0), lo w driv e strength selected (PTxDSn = 0),
and internal pullups disabled (PTxPEn = 0).
6.3 Parallel I/O Control
Reading and writing of parallel I/O is done through the port data registers. The direction, input or output,
is controlled through the port data direction registers. The parallel I/O port function for an individual pin
is illustrated in the block diagram below.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 83
Chapter 6 Parallel Input/Output
Port Read
Data
PTxDDn
QD
PTxDn
QD
Output Enable
Output Data
1
0
Synchronizer
Input Data
BUSCLK
Figure 6-1. Parallel I/O Block Diagram
The data direction control bits determine whether the pin output driver is enabled, and they control what
is read for port data register reads. Each port pin has a data direction register bit. When PTxDDn = 0, the
corresponding pin is an input and reads of PTxD return the pin value. When PTxDDn = 1, the
corresponding pin is an output and reads of PTxD return the last value written to the port data register.
When a peripheral module or system function is in control of a port pin, the data direction register bit still
controls what is returned for reads of the port data register, even though the peripheral system has
overriding control of the actual pin direction.
When a shared analog function is enabled for a pin, all digital pin functions are disabled. A read of the port
data register returns a value of 0 for any bits which have shared analog functions enabled. In general,
whenever a pin is shared with both an alternate digital function and an analog function, the analog function
has priority such that if both the digital and analog functions are enabled, the analog function controls the
pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
6.4 Pin Control
The pin control registers are located in the high page register block of the memory . These registers are used
to control pullups, slew rate, and drive strength for the I/O pins. The pin control registers operate
independently of the parallel I/O registers.
MC9S08AC60 Series Data Sheet, Rev. 2
84 Freescale Semiconductor
Chapter 6 Parallel Input/Output
6.4.1 Internal Pullup Enable
An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the
pullup enable registers (PTxPEn). The pullup device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral function regardless of the state of the corresponding
pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
6.4.2 Output Slew Rate Control Enable
Slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate
control registers (PTxSEn). When enabled, slew control limits the rate at which an output can transition in
order to reduce EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
6.4.3 Output Drive Strength Select
An output pin can be selected to have high output dri ve strength by setting the corresponding bit in one of
the drive strength select registers (PTxDSn). When high drive is selected a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high dri v e, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this the EMC emissions may be affected by enabling pins as high drive.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 85
Chapter 6 Parallel Input/Output
6.5 Pin Behavior in Stop Modes
Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An
explanation of I/O behavior for the various stop modes follows:
• Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was ex ecuted. CPU register status and the state of I/O registers should
be saved in RAM before the STOP instruction is e x ecuted to place the MCU in stop2 mode. Upon
recovery from stop2 mode, before accessing any I/O, the user should e xamine the state of the PPDF
bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had
occurred. If the PPDF bit is 1, I/O data previously stored in RAM, before the STOP instruction was
executed, peripherals may require being initialized and restored to their pre-stop condition. The
user must then write a 1 to the PPDA CK bit in the SPMSC2 register . Access to I/O is now permitted
again in the user’s application program.
• In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.
6.6 Parallel I/O and Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports and pin control
functions. These parallel I/O registers are located in page zero of the memory map and the pin control
registers are located in the high page register section of memory.
Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and pin
control registers. This section refers to registers and control bits only by their names. A Freescale-provided
equate or header file normally is used to translate these names into the appropriate absolute addresses.
6.6.1 Port A I/O Registers (PTAD and PTADD)
Port A parallel I/O function is controlled by the registers listed below.
76543210
R
PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
W
Reset 00000000
Figure 6-2. Port A Data Register (PTAD)
Table 6-1. PTAD Register Field Descriptions
Field Description
7:0
PTADn
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
MC9S08AC60 Series Data Sheet, Rev. 2
86 Freescale Semiconductor
Chapter 6 Parallel Input/Output
76543210
R
PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
W
Reset 00000000
Figure 6-3. Data Direction for Port A Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
Field Description
7, 2:0
PTADDn
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.6.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS)
In addition to the I/O control, port A pins are controlled by the registers listed below.
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R
PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
W
Reset 00000000
Figure 6-4. Internal Pullup Enable for Port A (PTAPE)
Table 6-3. PTADD Register Field Descriptions
Field Description
7:0
PTAPEn
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 87
Chapter 6 Parallel Input/Output
76543210
R
PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
W
Reset 00000000
Figure 6-5. Slew Rate Control Enable for Port A (PTASE)
Table 6-4. PTASE Register Field Descriptions
Field Description
7:0
PTASEn]
Output Slew Rate Control Enable for P ort A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
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R
PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
W
Reset 00000000
Figure 6-6. Drive Strength Selection for Port A (PTADS)
Table 6-5. PTADS Register Field Descriptions
Field Description
7:0
PTADSn
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
88 Freescale Semiconductor
Chapter 6 Parallel Input/Output
6.6.3 Port B I/O Registers (PTBD and PTBDD)
Port B parallel I/O function is controlled by the registers in this section.
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PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
W
Reset 00000000
Figure 6-7. Port B Data Register (PTBD)
Table 6-6. PTBD Register Field Descriptions
Field Description
7:0
PTBD[7:0]
R
W
Reset 00000000
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
76543210
PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
Figure 6-8. Data Direction for Port B (PTBDD)
Table 6-7. PTBDD Register Field Descriptions
Field Description
7:0
PTBDD[7:0]
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 89
Chapter 6 Parallel Input/Output
6.6.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS)
In addition to the I/O control, port B pins are controlled by the registers listed below.
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R
PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
W
Reset 00000000
Figure 6-9. Internal Pullup Enable for Port B (PTBPE)
Table 6-8. PTBPE Register Field Descriptions
Field Description
7:0
PTBPE[7:0]
R
W
Reset 00000000
Internal Pullup Enable for Port B Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTB pin. F or port B pins that are configured as outputs, these bits have no eff ect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port B bit n.
1 Internal pullup device enabled for port B bit n.
76543210
PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
Figure 6-10. Output Slew Rate Control Enable (PTBSE)
Table 6-9. PTBSE Register Field Descriptions
Field Description
7:0
PTBSE[7:0]
Output Slew Rate Control Enable for Port B Bits— Each of these control bits determine whether output slew
rate control is enabled for the associated PTB pin. F or port B pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
90 Freescale Semiconductor
Chapter 6 Parallel Input/Output
76543210
R
PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
W
Reset 00000000
Figure 6-11. Internal Drive Strength Selection for Port B (PTBDS)
Table 6-10. PTBDS Register Field Descriptions
Field Description
7:0
PTBDS[7:0]
Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high
output drive for the associated PTB pin.
0 Low output drive enabled for port B bit n.
1 High output drive enabled for port B bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 91
Chapter 6 Parallel Input/Output
6.6.5 Port C I/O Registers (PTCD and PTCDD)
Port C parallel I/O function is controlled by the registers listed below.
76543210
R0
W
Reset 00000000
Field Description
PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
Figure 6-12. Port C Data Register (PTCD)
Table 6-11. PTCD Register Field Descriptions
6:0
PTCD[6:0]
R0
W
Reset 00000000
Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
76543210
PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
Figure 6-13. Data Direction for Port C (PTCDD)
Table 6-12. PTCDD Register Field Descriptions
Field Description
6:0
PTCDD[6:0]
Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for
PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
MC9S08AC60 Series Data Sheet, Rev. 2
92 Freescale Semiconductor
Chapter 6 Parallel Input/Output
6.6.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS)
In addition to the I/O control, port C pins are controlled by the registers listed below.
76543210
R0
W
Reset 00000000
Field Description
PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
Figure 6-14. Internal Pullup Enable for Port C (PTCPE)
Table 6-13. PTCPE Register Field Descriptions
6:0
PTCPE[6:0]
R0
W
Reset 00000000
Internal Pullup Enable for Port C Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTC pin. F or port C pins that are configured as outputs, these bits have no eff ect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port C bit n.
1 Internal pullup device enabled for port C bit n.
76543210
PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
Figure 6-15. Output Slew Rate Control Enable for Port C (PTCSE)
Table 6-14. PTCSE Register Field Descriptions
Field Description
6:0
PTCSE[6:0]
Output Slew Rate Control Enable for P ort C Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTC pin. F or port C pins that are configured as inputs, these bits hav e
no effect.
0 Output slew rate control disabled for port C bit n.
1 Output slew rate control enabled for port C bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 93
Chapter 6 Parallel Input/Output
76543210
R0
PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0
W
Reset 00000000
Figure 6-16. Output Drive Strength Selection for Port C (PTCDS)
Table 6-15. PTCDS Register Field Descriptions
Field Description
6:0
PTCDS[6:0]
Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high
output drive for the associated PTC pin.
0 Low output drive enabled for port C bit n.
1 High output drive enabled for port C bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
94 Freescale Semiconductor
Chapter 6 Parallel Input/Output
6.6.7 Port D I/O Registers (PTDD and PTDDD)
Port D parallel I/O function is controlled by the registers listed below.
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R
PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
W
Reset 00000000
Figure 6-17. Port D Data Register (PTDD)
Table 6-16. PTDD Register Field Descriptions
Field Description
7:0
PTDD[7:0]
R
W
Reset 00000000
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
76543210
PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
Figure 6-18. Data Direction for Port D (PTDDD)
Table 6-17. PTDDD Register Field Descriptions
Field Description
7:0
PTDDD[7:0]
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 95
Chapter 6 Parallel Input/Output
6.6.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS)
In addition to the I/O control, port D pins are controlled by the registers listed below.
76543210
R
PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
W
Reset 00000000
Figure 6-19. Internal Pullup Enable for Port D (PTDPE)
Table 6-18. PTDPE Register Field Descriptions
Field Description
7:0
PTDPE[7:0]
R
W
Reset 00000000
Internal Pullup Enable for Port D Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTD pin. F or port D pins that are configured as outputs, these bits have no eff ect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port D bit n.
1 Internal pullup device enabled for port D bit n.
76543210
PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
Figure 6-20. Output Slew Rate Control Enable for Port D (PTDSE)
Table 6-19. PTDSE Register Field Descriptions
Field Description
7:0
PTDSE[7:0]
Output Slew Rate Control Enable for P ort D Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTD pin. F or port D pins that are configured as inputs, these bits hav e
no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
96 Freescale Semiconductor
Chapter 6 Parallel Input/Output
76543210
R
PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
W
Reset 00000000
Figure 6-21. Output Drive Strength Selection for Port D (PTDDS)
Table 6-20. PTDDS Register Field Descriptions
Field Description
7:0
PTDDS[7:0]
Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
output drive for the associated PTD pin.
0 Low output drive enabled for port D bit n.
1 High output drive enabled for port D bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 97
Chapter 6 Parallel Input/Output
6.6.9 Port E I/O Registers (PTED and PTEDD)
Port E parallel I/O function is controlled by the registers listed below.
76543210
R
PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
W
Reset 00000000
Figure 6-22. Port E Data Register (PTED)
Table 6-21. PTED Register Field Descriptions
Field Description
7:0
PTED[7:0]
R
W
Reset 00000000
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
76543210
PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
Figure 6-23. Data Direction for Port E (PTEDD)
Table 6-22. PTEDD Register Field Descriptions
Field Description
7:0
PTEDD[7:0]
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
MC9S08AC60 Series Data Sheet, Rev. 2
98 Freescale Semiconductor
Chapter 6 Parallel Input/Output
6.6.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS)
In addition to the I/O control, port E pins are controlled by the registers listed below.
76543210
R
PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
W
Reset 00000000
Figure 6-24. Internal Pullup Enable for Port E (PTEPE)
Table 6-23. PTEPE Register Field Descriptions
Field Description
7:0
PTEPE[7:0]
R
W
Reset 00000000
Internal Pullup Enable for Port E Bits— Each of these control bits determines if the internal pullup device is
enabled for the associated PTE pin. F or port E pins that are configured as outputs, these bits have no eff ect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port E bit n.
1 Internal pullup device enabled for port E bit n.
76543210
PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
Figure 6-25. Output Slew Rate Control Enable for Port E (PTESE)
Table 6-24. PTESE Register Field Descriptions
Field Description
7:0
PTESE[7:0]
Output Slew Rate Control Enable for P ort E Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTE pin. F or port E pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor 99
Chapter 6 Parallel Input/Output
76543210
R
PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0
W
Reset 00000000
Figure 6-26. Output Drive Strength Selection for Port E (PTEDS)
Table 6-25. PTEDS Register Field Descriptions
Field Description
7:0
PTEDS[7:0]
Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high
output drive for the associated PTE pin.
0 Low output drive enabled for port E bit n.
1 High output drive enabled for port E bit n.
MC9S08AC60 Series Data Sheet, Rev. 2
100 Freescale Semiconductor
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