Freescale MC9328MXS Advance Information

Freescale Semiconductor

Advance Information

MC9328MXS

MC9328MXS/D

Rev. 0, 1/2005

MC9328MXS

Package Information

Plastic Package

(PBGA–225)

Ordering Information

See Table 2 on page 4

1 Introduction

The i.MX (Media Extensions) series provides a leap in performance with an ARM9™ microprocessor core and highly integrated system functions. The i.MX products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities.

The i.MX processor features the advanced and powerefficient ARM920T™ core that operates at speeds up to 100 MHz. Integrated modules, which include a USB device and an LCD controller, support a suite of peripherals to enhance portable products. It is packaged in a 225-contact PBGA package. Figure 1 shows the functional block diagram of the i.MX processor.

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Signals and Connections . . . . . . . . . . . . . . . . . . . . 5

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Pin-Out and Package Information . . . . . . . . . . . .69

Contact Information . . . . . . . . . . . . . . . . . Last Page

Introduction

Figure 1. MC9328MXS Functional Block Diagram

1.1 Conventions

This document uses the following conventions:

• OVERBAR

• Logic level one is a voltage that corresponds to Boolean true (1) state.

• Logic level zero is a voltage that corresponds to Boolean false (0) state.

•To set a bit or bits means to establish logic level one.

•To clear a bit or bits means to establish logic level zero.

•A signal is an electronic construct whose state conveys or changes in state convey information.

•A pin is an external physical connection. The same pin can be used to connect a number of signals.

• Asserted means that a discrete signal is in active logic state.

— Active low signals change from logic level one to logic level zero.

— Active high signals change from logic level zero to logic level one.

• Negated means that an asserted discrete signal changes logic state.

— Active low signals change from logic level zero to logic level one.

— Active high signals change from logic level one to logic level zero.

• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out.

is used to indicate a signal that is active when pulled low: for example, RESET.

• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal.

MC9328MXS Advance Information, Rev. 0

2 Freescale Semiconductor

Introduction

1.2 Features

To support a wide variety of applications, the i.MX processor offers a robust array of features, including the following:

• ARM920T™ Microprocessor Core

• AHB to IP Bus Interfaces (AIPIs)

• External Interface Module (EIM)

• SDRAM Controller (SDRAMC)

• DPLL Clock and Power Control Module

• Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)

• Serial Peripheral Interface (SPI)

• Two General-Purpose 32-bit Counters/Timers

• Watchdog Timer

• Real-Time Clock/Sampling Timer (RTC)

• LCD Controller (LCDC)

• Pulse-Width Modulation (PWM) Module

• Universal Serial Bus (USB) Device

• Direct Memory Access Controller (DMAC)

• Synchronous Serial Interface and Inter-IC Sound (SSI/I

• Inter-IC (I

C) Bus Module

S) Module

• General-Purpose I/O (GPIO) Ports

• Bootstrap Mode

• Power Management Features

• Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O

• 225-contact PBGA Package

1.3 Target Applications

The i.MX processor is targeted for advanced information appliances, smart phones, Web browsers, and messaging applications.

1.4 Revision History

Table 1 provides revision history for this release. This history includes technical content revisions only and not stylistic or grammatical changes.

Table 1. MC9328MXS Data Sheet Revision History for Rev. 0

Revision

Initial Release

MC9328MXS Advance Information, Rev. 0

Freescale Semiconductor 3

Introduction

1.5 Reference Documents

The following documents are required for a complete description of the MC9328MXS and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall products, the following documents are helpful when used in conjunction with this document.

ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)

ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)

ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)

EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)

MC9328MXS Product Brief (order number MC9328MXSP/D)

MC9328MXS Reference Manual (order number MC9328MXSRM/D)

The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.

1.6 Ordering Information

Table 2 provides ordering information for the 225-contact PBGA package.

Table 2. MC9328MXS Ordering Information

Package Type Frequency Temperature Solderball Type Order Number

225-contact PBGA 100 MHz

1. Contact your distribution center or Freescale sales office.

-40OC to 85OC

C to 70OC

Standard MC9328MXSCVF10(R2)

Pb-free

Standard MC9328MXSVF10(R2)

Pb-free

See Note

MC9328MXS Advance Information, Rev. 0

4 Freescale Semiconductor

Signals and Connections

2 Signals and Connections

Table 3 identifies and describes the i.MX processor signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to.

Table 3. MC9328MXS Signal Descriptions

Signal Name Function/Notes

External Bus/Chip-Select (EIM)

A[24:0] Address bus signals

D[31:0] Data bus signals

EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].

EB1 Byte Strobe—Active low external enable byte signal that controls D [23:16].

EB2 Byte Strobe—Active low external enable byte signal that controls D [15:8].

EB3 LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].

OE Memory Output Enable—Active low output enables external data bus.

CS [5:0] Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the

Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.

ECB Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an

on-going burst sequence and initiate a new (long first access) burst sequence.

LBA Active low signal sent by a flash device causing the external burst device to latch the starting burst

address.

BCLK (burst clock) Clock signal sent to external synchronous memories (such as burst flash) during burst mode.

RW RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE

input signal by external DRAM.

DTACK DTACK signal—The external input data acknowledge signal. When using the external DTACK signal

as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed.

Bootstrap

BOOT [3:0] System Boot Mode Select—The operational system boot mode of the i.MX processor upon system

reset is determined by the settings of these pins.

SDRAM Controller

SDBA [4:0] SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These

signals are logically equivalent to core address p_addr [25:21] in SDRAM cycles.

SDIBA [3:0] SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These

signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.

MA [11:10] SDRAM address signals

MA [9:0] SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected

on SDRAM cycles.

DQM [3:0] SDRAM data enable

CSD0 SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are

selectable by programming the system control register.

CSD1 SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by

programming the system control register. By default, CSD1 is selected, so it can be used as boot chip-select by properly configuring BOOT [3:0] input pins.

RAS SDRAM Row Address Select signal

MC9328MXS Advance Information, Rev. 0

Freescale Semiconductor 5

Signals and Connections

Table 3. MC9328MXS Signal Descriptions (Continued)

Signal Name Function/Notes

CAS SDRAM Column Address Select signal

SDWE SDRAM Write Enable signal

SDCKE0 SDRAM Clock Enable 0

SDCKE1 SDRAM Clock Enable 1

SDCLK SDRAM Clock

RESET_SF Not Used

Clocks and Resets

EXTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is

shut down.

XTAL16M Crystal output

EXTAL32K 32 kHz crystal input

XTAL32K 32 kHz crystal output

CLKO Clock Out signal selected from internal clock signals.

RESET_IN Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all

modules (except the reset module and the clock control module) are reset.

RESET_OUT Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from

the following sources: Power-on reset, External reset (RESET_IN

POR Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally

generated by an external RC circuit designed to detect a power-up event.

JTAG

), and Watchdog time-out.

TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

TDO Serial Output for test instructions and data. Changes on the falling edge of TCK.

TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK.

TCK Test Clock to synchronize test logic and control register access through the JTAG port.

TMS Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge

of TCK.

DMA

BIG_ENDIAN Big Endian—Input signal that determines the configuration of the external chip-select space. If it is

driven logic-high at reset, the external chip-select space will be configured to little endian. If it is driven logic-low at reset, the external chip-select space will be configured to big endian.

DMA_REQ External DMA request pin.

ETM

ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.

ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.

ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM

mode.

ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK(burst clock), PA17, A [19:16].

ETMTRACEPKT [7:0] are selected in ETM mode.

LCD Controller

LD [15:0] LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.

MC9328MXS Advance Information, Rev. 0

6 Freescale Semiconductor

Signals and Connections

Table 3. MC9328MXS Signal Descriptions (Continued)

Signal Name Function/Notes

FLM/VSYNC Frame Sync or Vsync—This signal also serves as the clock signal output for the gate

driver (dedicated signal SPS for Sharp panel HR-TFT).

LP/HSYNC Line pulse or H sync

LSCLK Shift clock

ACD/OE Alternate crystal direction/output enable.

CONTRAST This signal is used to control the LCD bias voltage as contrast control.

SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal).

PS Control signal output for source driver (Sharp panel dedicated signal).

CLS Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated

signal).

REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal).

SPI 1

SPI1_MOSI Master Out/Slave In

SPI1_MISO Slave In/Master Out

SPI1_SS Slave Select (Selectable polarity)

SPI1_SCLK Serial Clock

SPI1_SPI_RDY Serial Data Ready

General Purpose Timers

TIN Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers

simultaneously.

TMR2OUT Timer 2 Output

USB Device

USBD_VMO USB Minus Output

USBD_VPO USB Plus Output

USBD_VM USB Minus Input

USBD_VP USB Plus Input

USBD_SUSPND USB Suspend Output

USBD_RCV USB Receive Data

USBD_OE USB OE

USBD_AFE USB Analog Front End Enable

UARTs – IrDA/Auto-Bauding

UART1_RXD Receive Data

UART1_TXD Transmit Data

UART1_RTS Request to Send

UART1_CTS Clear to Send

UART2_RXD Receive Data

UART2_TXD Transmit Data

UART2_RTS Request to Send

UART2_CTS Clear to Send

UART2_DSR Data Set Ready

MC9328MXS Advance Information, Rev. 0

Freescale Semiconductor 7

Signals and Connections

Table 3. MC9328MXS Signal Descriptions (Continued)

Signal Name Function/Notes

UART2_RI Ring Indicator

UART2_DCD Data Carrier Detect

UART2_DTR Data Terminal Ready

Serial Audio Port – SSI (configurable to I2S protocol)

SSI_TXDAT Transmit Data

SSI_RXDAT Receive Data

SSI_TXCLK Transmit Serial Clock

SSI_RXCLK Receive Serial Clock

SSI_TXFS Transmit Frame Sync

SSI_RXFS Receive Frame Sync

I2C

I2C_SCL I2C Clock

I2C_SDA I2C Data

PWM

PWMO PWM Output

Test Function

TRISTATE Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input

with a 1 k ohm resistor to ground. (TRI-STATE® is a registered trademark of National Semiconductor.)

General Purpose Input/Output

PA[14:3] Dedicated GPIO

PB[13:8] Dedicated GPIO

Digital Supply Pins

NVDD Digital Supply for the I/O pins

NVSS Digital Ground for the I/O pins

Supply Pins – Analog Modules

AVDD Supply for analog blocks

AVSS Quiet ground for analog blocks

Internal Power Supply

QVDD Power supply pins for silicon internal circuitry

QVSS Ground pins for silicon internal circuitry

Substrate Supply Pins

SVDD Supply routed through substrate of package; not to be bonded

SGND Ground routed through substrate of package; not to be bonded

MC9328MXS Advance Information, Rev. 0

8 Freescale Semiconductor

Specifications

3 Specifications

This section contains the electrical specifications and timing diagrams for the i.MX processor.

3.1 Maximum Ratings

Table 4 provides information on maximum ratings which are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on page 9 or the DC Characteristics table.

Table 4. Maximum Ratings

Symbol Rating Minimum Maximum Unit

NVDD DC I/O Supply Voltage -0.3 3.3 V

QVDD DC Internal (core = 100 MHz) Supply Voltage -0.3 1.9 V

AVDD DC Analog Supply Voltage -0.3 3.3 V

BTRFVDD DC Bluetooth Supply Voltage -0.3 3.3 V

VESD_HBM ESD immunity with HBM (human body model) – 2000 V

VESD_MM ESD immunity with MM (machine model) – 100 V

ILatchup Latch-up immunity – 200 mA

Test Storage temperature -55 150 °C

Pmax Power Consumption

1. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM

2. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS application at 100MHz, and where the whole image is running out of SDRAM. QVDD at

1.9V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.

core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.

800

1300

3.2 Recommended Operating Range

Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MX processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system.

Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the AVDD pins from other VDD pins.

For more information about I/O pads grouping per VDD, please refer to Table 3 on page 5.

Table 5. Recommended Operating Range

Symbol Rating Minimum Maximum Unit

Freescale Semiconductor 9

Operating temperature range MC9328MXSVF10

MC9328MXS Advance Information, Rev. 0

070°C

Specifications

Table 5. Recommended Operating Range (Continued)

Symbol Rating Minimum Maximum Unit

NVDD I/O supply voltage (if using SPI, LCD, and USBd which are only 3 V

NVDD I/O supply voltage (if not using the peripherals listed above) 1.70 3.30 V

QVDD Internal supply voltage (Core = 100 MHz) 1.70 1.90 V

AVDD Analog supply voltage 1.70 3.30 V

Operating temperature range MC9328MXSCVF10

interfaces)

-40 85 °C

2.70 3.30 V

3.3 Power Sequence Requirements

For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of application note AN2537 on the i.MX application processor website.

3.4 DC Electrical Characteristics

Table 6 contains both maximum and minimum DC characteristics of the i.MX processor.

Table 6. Maximum and Minimum DC Characteristics

Number or

Symbol

Parameter Min Typical Max Unit

Iop Full running operating current at 1.8V for QVDD, 3.3V for

NVDD/AVDD (Core = 96 MHz, System = 96 MHz, driving TFT display panel, and OS with MMU enabled memory system is running on external SDRAM).

Sidd

Standby current

(Core = 100 MHz, QVDD = 1.8V, temp = 25

Standby current

(Core = 100 MHz, QVDD = 1.8V, temp = 55

Standby current

(Core = 100 MHz, QVDD = 1.9V, temp = 25°C)

Standby current

(Core = 100 MHz, QVDD = 1.9V, temp = 55

Input high voltage 0.7V

Input low voltage – – 0.4 V

Output high voltage (IOH= 2.0 mA) 0.7V

Output low voltage (IOL= -2.5 mA) – – 0.4 V

Input low leakage current (VIN= GND, no pull-up or pull-down)

°C)

– QVDD at

1.8V = 120mA;

NVDD+AVDD at

3.0V = 30mA

–25 –µA

–45 –µA

–35 –µA

–60 –µA

––±1µA

–Vdd+0.2V

–VddV

–mA

MC9328MXS Advance Information, Rev. 0

10 Freescale Semiconductor

Table 6. Maximum and Minimum DC Characteristics (Continued)

Specifications

Number or

Symbol

Input high leakage current (VIN=VDD, no pull-up or pull-down)

Output high current (VOH=0.8VDD, VDD=1.8V)

Output low current

=0.4V, VDD=1.8V)

Output leakage current (V

out=VDD

Input capacitance – – 5 pF

Output capacitance – – 5 pF

, output is high impedence)

Parameter Min Typical Max Unit

––±1µA

––4.0mA

-4.0 – – mA

––±5µA

3.5 AC Electrical Characteristics

The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 100 MHz) with an operating supply voltage from V

DD min

to V

DD max

under an operating temperature from TL to TH. All timing is measured at 30 pF loading.

Table 7. Tristate Signal Timing

Pin Parameter Minimum Maximum Unit

TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z – 20.8 ns

Table 8. 32k/16M Oscillator Signal Timing

Parameter Minimum RMS Maximum Unit

EXTAL32k input jitter (peak to peak) – 5 20 ns

EXTAL32k startup time 800 – – ms

EXTAL16M input jitter (peak to peak)

EXTAL16M startup time

1. The 16 MHz oscillator is not recommended for use in new designs.

–TBDTBD–

TBD – – –

MC9328MXS Advance Information, Rev. 0

Freescale Semiconductor 11

Specifications

3.6 Embedded Trace Macrocell

All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift register comprised of the following:

• 32-bit data field

• 7-bit address field

• A read/write bit

The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit.

A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used in Figure 2.

TRACECLK

(Half-Rate Clocking Mode)

Output Trace Port

Valid Data

Figure 2. Trace Port Timing Diagram

Table 9. Trace Port Timing Diagram Parameter Table

Ref No.

1 CLK frequency 0 85 0 100 MHz

2a Clock high time 1.3 – 2 – ns

Parameter

Minimum Maximum Minimum Maximum

1.8 ± 0.1 V 3.0 ± 0.3 V Unit

2b Clock low time 3 – 2 – ns

3a Clock rise time – 4 – 3 ns

3b Clock fall time – 3 – 3 ns

4a Output hold time 2.28 – 2 – ns

4b Output setup time 3.42 – 3 – ns

MC9328MXS Advance Information, Rev. 0

12 Freescale Semiconductor

3.7 DPLL Timing Specifications

Specifications

Parameters of the DPLL are given in Table 10. In this table, T and T

is the output double clock period.

dck

is a reference clock period after the pre-divider

ref

Table 10. DPLL Specifications

Parameter Test Conditions Minimum Typical Maximum Unit

Reference clock freq range Vcc = 1.8V 5 – 100 MHz

Pre-divider output clock freq range

Double clock freq range Vcc = 1.8V 80 – 220 MHz

Pre-divider factor (PD) – 1 – 16 –

Total multiplication factor (MF) Includes both integer and fractional parts 5 – 15 –

MF integer part – 5 – 15 –

MF numerator Should be less than the denominator 0 – 1022 –

MF denominator – 1 – 1023 –

Pre-multiplier lock-in time – – – 312.5

Freq lock-in time after full reset

Vcc = 1.8V 5 – 30 MHz

FOL mode for non-integer MF (does not include pre-multi lock-in time)

250 280

(56 µs)

300 T

µsec

ref

Freq lock-in time after partial reset

Phase lock-in time after full reset

Phase lock-in time after partial reset

Freq jitter (p-p) – – 0.005

Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V – 1.0

Power supply voltage – 1.7 – 2.5 V

Power dissipation FOL mode, integer MF,

FOL mode for non-integer MF (does not include pre-multi lock-in time)

FPL mode and integer MF (does not include pre-multi lock-in time)

= 100 MHz, Vcc = 1.8V

dck

220 250

(50 µs)

300 350

(70 µs)

270 320

(64 µs)

(0.01%)

(10%)

––4mW

270 T

400 T

370 T

0.01 2•T

1.5 ns

ref

dck

MC9328MXS Advance Information, Rev. 0

Freescale Semiconductor 13

Specifications

3.8 Reset Module

The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4.

NOTE:

Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent forward biasing.

90% AVDD

POR

10% AVDD

RESET_POR

RESET_DRAM

HRESET

RESET_OUT

CLK32

HCLK

Exact 300ms

Figure 3. Timing Relationship with POR

7 cycles @ CLK32

14 cycles @ CLK32

MC9328MXS Advance Information, Rev. 0

14 Freescale Semiconductor

RESET_IN

Specifications

HRESET

RESET_OUT

CLK32

Ref No.

HCLK

Figure 4. Timing Relationship with RESET_IN

Table 11. Reset Module Timing Parameter Table

1.8 ± 0.1 V 3.0 ± 0.3 V

Parameter

Min Max Min Max

14 cycles @ CLK32

Unit

1 Width of input POWER_ON_RESET

2 Width of internal POWER_ON_RESET

note

–

300 300 300 300 ms

note

––

(CLK32 at 32 kHz)

3 7K to 32K-cycle stretcher for SDRAM reset 7 7 7 7 Cycles of

CLK32

4 14K to 32K-cycle stretcher for internal system reset

HRESERT

and output reset at pin RESET_OUT

5 Width of external hard-reset RESET_IN

14 14 14 14 Cycles of

CLK32

4 – 4 – Cycles of

CLK32

6 4K to 32K-cycle qualifier 4 4 4 4 Cycles of

CLK32

1. POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal. If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in calculating timing for the start-up process.

MC9328MXS Advance Information, Rev. 0

Freescale Semiconductor 15

Specifications

3.9 External Interface Module

The External Interface Module (EIM) handles the interface to devices external to the i.MX processor, including the generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 on page 16 defines the parameters of signals.

(HCLK) Bus Clock

1a 1b

Address

Chip-select

Read (Write

)

2a 2b

3b3a

(rising edge)

(falling edge)

(rising edge)

(falling edge)

(negated falling edge)

LBA

(negated rising edge)

BCLK (burst clock) - rising edge

BCLK (burst clock) - falling edge

Read Data

Write Data (negated falling)

Write Data (negated rising)

DTACK_B

4a 4b

4c 4d

5a 5b

5c 5d

7a 7b

10a

Figure 5. EIM Bus Timing Diagram

Table 12. EIM Bus Timing Parameter Table

1.8 ± 0.1 V 3.0 ± 0.3 V

Ref No. Parameter

Min Typical Max Min Typical Max

1a Clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns

1b Clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns

MC9328MXS Advance Information, Rev. 0

16 Freescale Semiconductor

Unit

Specifications

Table 12. EIM Bus Timing Parameter Table (Continued)

1.8 ± 0.1 V 3.0 ± 0.3 V

Ref No. Parameter

Min Typical Max Min Typical Max

2a Clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns

2b Clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns

3a Clock fall to Read (Write) Valid 1.35 2.79 6.52 1.3 2.7 6.3 ns

3b Clock fall to Read (Write

4a Clock

4b Clock

4c Clock

4d Clock

5a Clock

5b Clock

5c Clock

5d Clock

6a Clock

6b Clock

6c Clock

7a Clock

7b Clock

7c Clock

7d Clock

rise to Output Enable Valid 2.32 2.62 6.85 2.3 2.6 6.8 ns

rise to Output Enable Invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns

fall to Output Enable Valid 2.38 2.69 7.04 2.3 2.6 6.8 ns

fall to Output Enable Invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns

rise to Enable Bytes Valid 1.91 2.52 5.54 1.9 2.5 5.5 ns

rise to Enable Bytes Invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns

fall to Enable Bytes Valid 1.97 2.59 5.69 1.9 2.5 5.5 ns

fall to Enable Bytes Invalid 1.76 2.48 5.38 1.7 2.4 5.2 ns

fall to Load Burst Address Valid 2.07 2.79 6.73 2.0 2.7 6.5 ns

fall to Load Burst Address Invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns

rise to Load Burst Address Invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns

rise to Burst Clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns

rise to Burst Clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns

fall to Burst Clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns

fall to Burst Clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns

8a Read Data setup time 5.54 – – 5.5 – – ns

) Invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns

Unit

8b Read Data hold time 0 – – 0 – – ns

9a Clock

9b Clock

9c Clock

10a DTACK

rise to Write Data Valid 1.81 2.72 6.85 1.8 2.7 6.8 ns

fall to Write Data Invalid 1.45 2.48 5.69 1.4 2.4 5.5 ns

rise to Write Data Invalid 1.63 – – 1.62 – – ns

setup time 2.52 – – 2.5 – – ns

1. Clock refers to the system clock signal, HCLK, generated from the System DPLL

MC9328MXS Advance Information, Rev. 0

Freescale Semiconductor 17

Specifications

3.9.1 DTACK Signal Description

The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK

signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal

function when the external DTACK signal is used for data acknowledgement.

3.9.2 DTACK Signal Timing

Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of measure for this figure are found in the associated tables.

MC9328MXS Advance Information, Rev. 0

18 Freescale Semiconductor

3.9.2.1 DTACK Read Cycle without DMA

Specifications

Address

CS5

programmable

min 0ns

DTACK

DATABUS

(input to i.MX)

Figure 6. DTACK Read Cycle without DMA

Table 13. Read Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz

Number Characteristic

3.0 ± 0.3 V

Unit

Minimum Maximum

1 OE and EB assertion time See note 3 – ns

2 CS5

3 OE

4 D

5 D

6 Data hold timing after OE

7 Data ready after DTACK

8 OE negated to CS negated 0.5T-0.68 0.5T-0.06 ns

9 OE negated after EB negated 0.06 0.18 ns

10 DTACK

Note:

1. DTACK

2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

3. OE EBC bit in CS5L register is clear.

4. Address becomes valid and CS

5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.

asserted means DTACK becomes low level.

and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when

pulse width 3T – ns

negated to address inactive 46.39 – ns

TACK asserted after CS5 asserted – 1019T ns

TACK asserted to OE negated 3T+1.83 4T+6.6 ns

negated 0–ns

asserted 0Tns

pulse width 1T 3T ns

asserts at the start of read access cycle.

MC9328MXS Advance Information, Rev. 0

Freescale Semiconductor 19

Specifications

3.9.2.2 DTACK Read Cycle DMA Enabled

Address

CS5

programmable

min 0ns

(logic high)

DTACK

DATABUS

(input to i.MX)

Figure 7. DTACK Read Cycle DMA Enabled

Table 14. Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz

3.0 ± 0.3 V

Number Characteristic

Minimum Maximum

1OE

2CS

3OE

4 Address inactive before CS

7 Data hold timing after OE

8 Data ready after DTACK is asserted – T ns

9CS

10 OE negate after EB negate 0.06 0.18 ns

11 DTACK pulse width 1T 3T ns

Note:

1. DTACK

2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

3. OE EBC bit in CS5L register is clear.

4. Address becomes valid and CS

5. The external DTACK

asserted means DTACK becomes low level.

and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when

and EB assertion time See note 3 – ns

pulse width 3T – ns

negated before CS5 is negated 0.5T-0.68 0.5T-0.06 ns

negated – 0.3 ns

TACK asserted after CS5 asserted – 1019T ns

TACK asserted to OE negated 3T+1.83 4T+6.6 ns

negated 0 – ns

deactive to next CS active T – ns

asserts at the start of read access cycle.

input requirement is eliminated when CS5 is programmed to use internal wait state.

Unit

MC9328MXS Advance Information, Rev. 0

20 Freescale Semiconductor

3.9.2.3 DTACK Write Cycle without DMA

Address

Specifications

CS5

programmable

min 0ns

(logic high)

DTACK

Databus

(input to i.MX)

programmable min 0ns

Figure 8. DTACK Write Cycle without DMA

Table 15. Write Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz

Number Characteristic

Minimum Maximum

3.0 ± 0.3 V

Unit

1CS5

2EB assertion time See note 3 – ns

3CS5 pulse width 3T – ns

4RW negated before CS5 is negated 1.5T-2.44 1.5T-0.8 ns

5RW

6DTACK asserted after CS5 asserted – 1019T ns

7DTACK asserted to RW negated 2T+2.37 3T+6.6 ns

8 Data hold timing after RW

9 Data ready after CS5 is asserted – T ns

10 EB negated after CS5 is negated 0.5T 0.5T+0.5 ns

11 DTACK pulse width 1T 3T ns

Note:

1. DTACK

2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

3. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.

4. Address becomes valid and RW

5. The external DTACK

asserted means DTACK becomes low level.

assertion time See note 3 – ns

negated to address inactive 57.31 – ns

negated 1.5T-3.99 – ns

asserts at the start of write access cycle.

input requirement is eliminated when CS5 is programmed to use internal wait state.

MC9328MXS Advance Information, Rev. 0

Freescale Semiconductor 21

Specifications

3.9.2.4 DTACK Write Cycle DMA Enabled

Address

programmable

(logic high)

DTACK

CS5

min 0ns

programmable

min 0ns

DATABUS

(output to i.MX)

Figure 9. DTACK Write Cycle DMA Enabled

Table 16. Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz

Number Characteristic

3.0 ± 0.3 V

Minimum Maximum

Unit

2EB

3CS5

4RW

5 Address inactive after C

8 Data hold timing after RW

9 Data ready after CS5

10 CS

11 EB

12 DTACK

Note:

1. DTACK

2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.

3. CS5

4. Address becomes valid and RW

5.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.

S5 assertion time See note 3 – ns

assertion time See note 3 – ns

pulse width 3T – ns

negated before CS5 is negated 1.5T-2.44 1.5T-0.8 ns

S negated – 0.3 ns

TACK asserted after CS5 asserted – 1019T ns

TACK asserted to RW negated 2T+2.37 3T+6.6 ns

negated 1.5T-3.99 – ns

is asserted – T ns

deactive to next CS active T – ns

negate after CS negate 0.5T 0.5T+0.5 ns

pulse width 1T 3T ns

asserted means DTACK becomes low level.

asserts at the start of write access cycle.

MC9328MXS Advance Information, Rev. 0

22 Freescale Semiconductor

+ 51 hidden pages

Freescale MC9328MXS Advance Information

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Conventions

1.2 Features

1.3 Target Applications

1.4 Revision History

1.5 Reference Documents

1.6 Ordering Information

2 Signals and Connections

3 Specifications

3.1 Maximum Ratings

3.2 Recommended Operating Range

3.3 Power Sequence Requirements

3.4 DC Electrical Characteristics

3.5 AC Electrical Characteristics

3.6 Embedded Trace Macrocell

3.7 DPLL Timing Specifications

3.8 Reset Module

3.9 External Interface Module

3.9.1 DTACK Signal Description

3.9.2 DTACK Signal Timing

3.9.2.1 DTACK Read Cycle without DMA

3.9.2.2 DTACK Read Cycle DMA Enabled

3.9.2.3 DTACK Write Cycle without DMA

3.9.2.4 DTACK Write Cycle DMA Enabled