Page 1
Freescale Semiconductor
Advance Information
MC9328MXS
MC9328MXS/D
Rev. 0, 1/2005
MC9328MXS
Package Information
Plastic Package
(PBGA–225)
Ordering Information
See Table 2 on page 4
1 Introduction
The i.MX (Media Extensions) series provides a leap in
performance with an ARM9™ microprocessor core and
highly integrated system functions. The i.MX products
specifically address the requirements of the personal,
portable product market by providing intelligent integrated
peripherals, an advanced processor core, and power
management capabilities.
The i.MX processor features the advanced and powerefficient ARM920T™ core that operates at speeds up to
100 MHz. Integrated modules, which include a USB device
and an LCD controller, support a suite of peripherals to
enhance portable products. It is packaged in a 225-contact
PBGA package. Figure 1 shows the functional block diagram
of the i.MX processor.
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signals and Connections . . . . . . . . . . . . . . . . . . . . 5
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pin-Out and Package Information . . . . . . . . . . . .69
Contact Information . . . . . . . . . . . . . . . . . Last Page
© Freescale Semiconductor, Inc., 2005. All rights reserved.
This document contains information on a new product. Specifications and information herein are
subject to change without notice.
Page 2
Introduction
Figure 1. MC9328MXS Functional Block Diagram
1.1 Conventions
This document uses the following conventions:
• OVERBAR
• Logic level one is a voltage that corresponds to Boolean true (1) state.
• Logic level zero is a voltage that corresponds to Boolean false (0) state.
•To set a bit or bits means to establish logic level one.
•To clear a bit or bits means to establish logic level zero.
•A signal is an electronic construct whose state conveys or changes in state convey information.
•A pin is an external physical connection. The same pin can be used to connect a number of signals.
• Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
• Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.
is used to indicate a signal that is active when pulled low: for example, RESET.
• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are
hexadecimal.
MC9328MXS Advance Information, Rev. 0
2 Freescale Semiconductor
Page 3
Introduction
1.2 Features
To support a wide variety of applications, the i.MX processor offers a robust array of features, including the
following:
• ARM920T™ Microprocessor Core
• AHB to IP Bus Interfaces (AIPIs)
• External Interface Module (EIM)
• SDRAM Controller (SDRAMC)
• DPLL Clock and Power Control Module
• Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)
• Serial Peripheral Interface (SPI)
• Two General-Purpose 32-bit Counters/Timers
• Watchdog Timer
• Real-Time Clock/Sampling Timer (RTC)
• LCD Controller (LCDC)
• Pulse-Width Modulation (PWM) Module
• Universal Serial Bus (USB) Device
• Direct Memory Access Controller (DMAC)
• Synchronous Serial Interface and Inter-IC Sound (SSI/I
2
• Inter-IC (I
C) Bus Module
2
S) Module
• General-Purpose I/O (GPIO) Ports
• Bootstrap Mode
• Power Management Features
• Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O
• 225-contact PBGA Package
1.3 Target Applications
The i.MX processor is targeted for advanced information appliances, smart phones, Web browsers, and messaging
applications.
1.4 Revision History
Table 1 provides revision history for this release. This history includes technical content revisions only and not
stylistic or grammatical changes.
Table 1. MC9328MXS Data Sheet Revision History for Rev. 0
Revision
Initial Release
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 3
Page 4
Introduction
1.5 Reference Documents
The following documents are required for a complete description of the MC9328MXS and are necessary to design
properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall
products, the following documents are helpful when used in conjunction with this document.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MXS Product Brief (order number MC9328MXSP/D)
MC9328MXS Reference Manual (order number MC9328MXSRM/D)
The Freescale manuals are available on the Freescale Semiconductors Web site at
http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or
printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.
1.6 Ordering Information
Table 2 provides ordering information for the 225-contact PBGA package.
Table 2. MC9328MXS Ordering Information
Package Type Frequency Temperature Solderball Type Order Number
225-contact PBGA 100 MHz
1. Contact your distribution center or Freescale sales office.
-40OC to 85OC
O
0
C to 70OC
Standard MC9328MXSCVF10(R2)
Pb-free
Standard MC9328MXSVF10(R2)
Pb-free
See Note
See Note
1
1
MC9328MXS Advance Information, Rev. 0
4 Freescale Semiconductor
Page 5
Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the i.MX processor signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.
Table 3. MC9328MXS Signal Descriptions
Signal Name Function/Notes
External Bus/Chip-Select (EIM)
A[24:0] Address bus signals
D[31:0] Data bus signals
EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
EB1 Byte Strobe—Active low external enable byte signal that controls D [23:16].
EB2 Byte Strobe—Active low external enable byte signal that controls D [15:8].
EB3 LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
OE Memory Output Enable—Active low output enables external data bus.
CS [5:0] Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock) Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE
input signal by external DRAM.
DTACK DTACK signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is
not terminated by the external DTACK signal after 1022 clock counts have elapsed.
Bootstrap
BOOT [3:0] System Boot Mode Select—The operational system boot mode of the i.MX processor upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0] SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These
signals are logically equivalent to core address p_addr [25:21] in SDRAM cycles.
SDIBA [3:0] SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These
signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.
MA [11:10] SDRAM address signals
MA [9:0] SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected
on SDRAM cycles.
DQM [3:0] SDRAM data enable
CSD0 SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are
selectable by programming the system control register.
CSD1 SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by
programming the system control register. By default, CSD1 is selected, so it can be used as boot
chip-select by properly configuring BOOT [3:0] input pins.
RAS SDRAM Row Address Select signal
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 5
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Signals and Connections
Table 3. MC9328MXS Signal Descriptions (Continued)
Signal Name Function/Notes
CAS SDRAM Column Address Select signal
SDWE SDRAM Write Enable signal
SDCKE0 SDRAM Clock Enable 0
SDCKE1 SDRAM Clock Enable 1
SDCLK SDRAM Clock
RESET_SF Not Used
Clocks and Resets
EXTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is
shut down.
XTAL16M Crystal output
EXTAL32K 32 kHz crystal input
XTAL32K 32 kHz crystal output
CLKO Clock Out signal selected from internal clock signals.
RESET_IN Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
RESET_OUT Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from
the following sources: Power-on reset, External reset (RESET_IN
POR Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
JTAG
), and Watchdog time-out.
TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK Test Clock to synchronize test logic and control register access through the JTAG port.
TMS Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge
of TCK.
DMA
BIG_ENDIAN Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to little endian. If it is
driven logic-low at reset, the external chip-select space will be configured to big endian.
DMA_REQ External DMA request pin.
ETM
ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK(burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
LCD Controller
LD [15:0] LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
MC9328MXS Advance Information, Rev. 0
6 Freescale Semiconductor
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Signals and Connections
Table 3. MC9328MXS Signal Descriptions (Continued)
Signal Name Function/Notes
FLM/VSYNC Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC Line pulse or H sync
LSCLK Shift clock
ACD/OE Alternate crystal direction/output enable.
CONTRAST This signal is used to control the LCD bias voltage as contrast control.
SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal).
PS Control signal output for source driver (Sharp panel dedicated signal).
CLS Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated
signal).
REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SPI 1
SPI1_MOSI Master Out/Slave In
SPI1_MISO Slave In/Master Out
SPI1_SS Slave Select (Selectable polarity)
SPI1_SCLK Serial Clock
SPI1_SPI_RDY Serial Data Ready
General Purpose Timers
TIN Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers
simultaneously.
TMR2OUT Timer 2 Output
USB Device
USBD_VMO USB Minus Output
USBD_VPO USB Plus Output
USBD_VM USB Minus Input
USBD_VP USB Plus Input
USBD_SUSPND USB Suspend Output
USBD_RCV USB Receive Data
USBD_OE USB OE
USBD_AFE USB Analog Front End Enable
UARTs – IrDA/Auto-Bauding
UART1_RXD Receive Data
UART1_TXD Transmit Data
UART1_RTS Request to Send
UART1_CTS Clear to Send
UART2_RXD Receive Data
UART2_TXD Transmit Data
UART2_RTS Request to Send
UART2_CTS Clear to Send
UART2_DSR Data Set Ready
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 7
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Signals and Connections
Table 3. MC9328MXS Signal Descriptions (Continued)
Signal Name Function/Notes
UART2_RI Ring Indicator
UART2_DCD Data Carrier Detect
UART2_DTR Data Terminal Ready
Serial Audio Port – SSI (configurable to I2S protocol)
SSI_TXDAT Transmit Data
SSI_RXDAT Receive Data
SSI_TXCLK Transmit Serial Clock
SSI_RXCLK Receive Serial Clock
SSI_TXFS Transmit Frame Sync
SSI_RXFS Receive Frame Sync
I2C
I2C_SCL I2C Clock
I2C_SDA I2C Data
PWM
PWMO PWM Output
Test Function
TRISTATE Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input
with a 1 k ohm resistor to ground. (TRI-STATE® is a registered trademark of National
Semiconductor.)
General Purpose Input/Output
PA[14:3] Dedicated GPIO
PB[13:8] Dedicated GPIO
Digital Supply Pins
NVDD Digital Supply for the I/O pins
NVSS Digital Ground for the I/O pins
Supply Pins – Analog Modules
AVDD Supply for analog blocks
AVSS Quiet ground for analog blocks
Internal Power Supply
QVDD Power supply pins for silicon internal circuitry
QVSS Ground pins for silicon internal circuitry
Substrate Supply Pins
SVDD Supply routed through substrate of package; not to be bonded
SGND Ground routed through substrate of package; not to be bonded
MC9328MXS Advance Information, Rev. 0
8 Freescale Semiconductor
Page 9
Specifications
3 Specifications
This section contains the electrical specifications and timing diagrams for the i.MX processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings which are those values beyond which damage to the device may
occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on
page 9 or the DC Characteristics table.
Table 4. Maximum Ratings
Symbol Rating Minimum Maximum Unit
NVDD DC I/O Supply Voltage -0.3 3.3 V
QVDD DC Internal (core = 100 MHz) Supply Voltage -0.3 1.9 V
AVDD DC Analog Supply Voltage -0.3 3.3 V
BTRFVDD DC Bluetooth Supply Voltage -0.3 3.3 V
VESD_HBM ESD immunity with HBM (human body model) – 2000 V
VESD_MM ESD immunity with MM (machine model) – 100 V
ILatchup Latch-up immunity – 200 mA
Test Storage temperature -55 150 °C
Pmax Power Consumption
1. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches
from the ARM
2. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches
from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core
running its heaviest OS application at 100MHz, and where the whole image is running out of SDRAM. QVDD at
1.9V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment,
max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.
®
core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
800
1
1300
2
mW
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MX processor
has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal
logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides
power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the
AVDD pins from other VDD pins.
For more information about I/O pads grouping per VDD, please refer to Table 3 on page 5.
Table 5. Recommended Operating Range
Symbol Rating Minimum Maximum Unit
T
A
Freescale Semiconductor 9
Operating temperature range
MC9328MXSVF10
MC9328MXS Advance Information, Rev. 0
070°C
Page 10
Specifications
Table 5. Recommended Operating Range (Continued)
Symbol Rating Minimum Maximum Unit
T
A
NVDD I/O supply voltage (if using SPI, LCD, and USBd which are only 3 V
NVDD I/O supply voltage (if not using the peripherals listed above) 1.70 3.30 V
QVDD Internal supply voltage (Core = 100 MHz) 1.70 1.90 V
AVDD Analog supply voltage 1.70 3.30 V
Operating temperature range
MC9328MXSCVF10
interfaces)
-40 85 °C
2.70 3.30 V
3.3 Power Sequence Requirements
For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of
application note AN2537 on the i.MX application processor website.
3.4 DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the i.MX processor.
Table 6. Maximum and Minimum DC Characteristics
Number or
Symbol
Parameter Min Typical Max Unit
Iop Full running operating current at 1.8V for QVDD, 3.3V for
NVDD/AVDD (Core = 96 MHz, System = 96 MHz, driving
TFT display panel, and OS with MMU enabled memory
system is running on external SDRAM).
Sidd
Sidd
Sidd
Sidd
V
V
V
OH
V
OL
I
IL
IH
IL
Standby current
1
(Core = 100 MHz, QVDD = 1.8V, temp = 25
Standby current
2
(Core = 100 MHz, QVDD = 1.8V, temp = 55
Standby current
3
(Core = 100 MHz, QVDD = 1.9V, temp = 25°C)
Standby current
4
(Core = 100 MHz, QVDD = 1.9V, temp = 55
Input high voltage 0.7V
Input low voltage – – 0.4 V
Output high voltage (IOH= 2.0 mA) 0.7V
Output low voltage (IOL= -2.5 mA) – – 0.4 V
Input low leakage current
(VIN= GND, no pull-up or pull-down)
°C)
°C)
°C)
– QVDD at
1.8V = 120mA;
NVDD+AVDD at
3.0V = 30mA
–25 –µA
–45 –µA
–35 –µA
–60 –µA
DD
DD
––±1µA
–Vdd+0.2V
–VddV
–mA
MC9328MXS Advance Information, Rev. 0
10 Freescale Semiconductor
Page 11
Table 6. Maximum and Minimum DC Characteristics (Continued)
Specifications
Number or
Symbol
I
IH
I
OH
I
OL
I
OZ
C
i
C
o
Input high leakage current
(VIN=VDD, no pull-up or pull-down)
Output high current
(VOH=0.8VDD, VDD=1.8V)
Output low current
=0.4V, VDD=1.8V)
(V
OL
Output leakage current
(V
out=VDD
Input capacitance – – 5 pF
Output capacitance – – 5 pF
, output is high impedence)
Parameter Min Typical Max Unit
––±1µA
––4.0mA
-4.0 – – mA
––±5µA
3.5 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are
specified relative to an appropriate edge of other signals. All timing specifications are specified at a system
operating frequency from 0 MHz to 96 MHz (core operating frequency 100 MHz) with an operating supply voltage
from V
DD min
to V
DD max
under an operating temperature from TL to TH. All timing is measured at 30 pF loading.
Table 7. Tristate Signal Timing
Pin Parameter Minimum Maximum Unit
TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z – 20.8 ns
Table 8. 32k/16M Oscillator Signal Timing
Parameter Minimum RMS Maximum Unit
EXTAL32k input jitter (peak to peak) – 5 20 ns
EXTAL32k startup time 800 – – ms
EXTAL16M input jitter (peak to peak)
EXTAL16M startup time
1. The 16 MHz oscillator is not recommended for use in new designs.
1
1
–TBDTBD–
TBD – – –
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 11
Page 12
Specifications
3.6 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift
register comprised of the following:
• 32-bit data field
• 7-bit address field
• A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field,
and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field
is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing
diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used in Figure 2.
TRACECLK
TRACECLK
(Half-Rate Clocking Mode)
Output Trace Port
3a
2a
2b
3b
Valid Data
4a
1
Valid Data
4b
Figure 2. Trace Port Timing Diagram
Table 9. Trace Port Timing Diagram Parameter Table
Ref
No.
1 CLK frequency 0 85 0 100 MHz
2a Clock high time 1.3 – 2 – ns
Parameter
Minimum Maximum Minimum Maximum
1.8 ± 0.1 V 3.0 ± 0.3 V
Unit
2b Clock low time 3 – 2 – ns
3a Clock rise time – 4 – 3 ns
3b Clock fall time – 3 – 3 ns
4a Output hold time 2.28 – 2 – ns
4b Output setup time 3.42 – 3 – ns
MC9328MXS Advance Information, Rev. 0
12 Freescale Semiconductor
Page 13
3.7 DPLL Timing Specifications
Specifications
Parameters of the DPLL are given in Table 10. In this table, T
and T
is the output double clock period.
dck
is a reference clock period after the pre-divider
ref
Table 10. DPLL Specifications
Parameter Test Conditions Minimum Typical Maximum Unit
Reference clock freq range Vcc = 1.8V 5 – 100 MHz
Pre-divider output clock
freq range
Double clock freq range Vcc = 1.8V 80 – 220 MHz
Pre-divider factor (PD) – 1 – 16 –
Total multiplication factor (MF) Includes both integer and fractional parts 5 – 15 –
MF integer part – 5 – 15 –
MF numerator Should be less than the denominator 0 – 1022 –
MF denominator – 1 – 1023 –
Pre-multiplier lock-in time – – – 312.5
Freq lock-in time after
full reset
Vcc = 1.8V 5 – 30 MHz
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
250 280
(56 µs)
300 T
µsec
ref
Freq lock-in time after
partial reset
Phase lock-in time after
full reset
Phase lock-in time after
partial reset
Freq jitter (p-p) – – 0.005
Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V – 1.0
Power supply voltage – 1.7 – 2.5 V
Power dissipation FOL mode, integer MF,
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
FPL mode and integer MF (does not
include pre-multi lock-in time)
FPL mode and integer MF (does not
include pre-multi lock-in time)
f
= 100 MHz, Vcc = 1.8V
dck
220 250
(50 µs)
300 350
(70 µs)
270 320
(64 µs)
(0.01%)
(10%)
––4mW
270 T
400 T
370 T
0.01 2•T
1.5 ns
ref
ref
ref
dck
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 13
Page 14
Specifications
3.8 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4.
NOTE:
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up
to prevent forward biasing.
90% AVDD
1
POR
10% AVDD
RESET_POR
RESET_DRAM
HRESET
RESET_OUT
CLK32
HCLK
2
Exact 300ms
3
Figure 3. Timing Relationship with POR
7 cycles @ CLK32
4
14 cycles @ CLK32
MC9328MXS Advance Information, Rev. 0
14 Freescale Semiconductor
Page 15
RESET_IN
Specifications
5
HRESET
RESET_OUT
CLK32
Ref
No.
HCLK
6
Figure 4. Timing Relationship with RESET_IN
Table 11. Reset Module Timing Parameter Table
1.8 ± 0.1 V 3.0 ± 0.3 V
Parameter
Min Max Min Max
14 cycles @ CLK32
4
Unit
1 Width of input POWER_ON_RESET
2 Width of internal POWER_ON_RESET
note
1
–
300 300 300 300 ms
note
1
––
(CLK32 at 32 kHz)
3 7K to 32K-cycle stretcher for SDRAM reset 7 7 7 7 Cycles of
CLK32
4 14K to 32K-cycle stretcher for internal system reset
HRESERT
and output reset at pin RESET_OUT
5 Width of external hard-reset RESET_IN
14 14 14 14 Cycles of
CLK32
4 – 4 – Cycles of
CLK32
6 4K to 32K-cycle qualifier 4 4 4 4 Cycles of
CLK32
1. POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for
crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of
supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of
start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored
in calculating timing for the start-up process.
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 15
Page 16
Specifications
3.9 External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the i.MX processor, including the
generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in
Figure 5, and Table 12 on page 16 defines the parameters of signals.
(HCLK) Bus Clock
1a 1b
Address
Chip-select
Read (Write
)
2a 2b
3b3a
(rising edge)
OE
(falling edge)
OE
EB
(rising edge)
EB
(falling edge)
(negated falling edge)
LBA
LBA
(negated rising edge)
BCLK (burst clock) - rising edge
BCLK (burst clock) - falling edge
Read Data
Write Data (negated falling)
Write Data (negated rising)
DTACK_B
4a 4b
4c 4d
5a 5b
5c 5d
6a
6a
7a 7b
7c
9a
9a
10a
6c
7d
8a
9c
10a
6b
8b
9b
Figure 5. EIM Bus Timing Diagram
Table 12. EIM Bus Timing Parameter Table
1.8 ± 0.1 V 3.0 ± 0.3 V
Ref No. Parameter
Min Typical Max Min Typical Max
1a Clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns
1b Clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns
MC9328MXS Advance Information, Rev. 0
16 Freescale Semiconductor
Unit
Page 17
Specifications
Table 12. EIM Bus Timing Parameter Table (Continued)
1.8 ± 0.1 V 3.0 ± 0.3 V
Ref No. Parameter
Min Typical Max Min Typical Max
2a Clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns
2b Clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns
3a Clock fall to Read (Write) Valid 1.35 2.79 6.52 1.3 2.7 6.3 ns
3b Clock fall to Read (Write
1
4a Clock
4b Clock
4c Clock
4d Clock
5a Clock
5b Clock
5c Clock
5d Clock
6a Clock
6b Clock
6c Clock
7a Clock
7b Clock
7c Clock
7d Clock
rise to Output Enable Valid 2.32 2.62 6.85 2.3 2.6 6.8 ns
1
rise to Output Enable Invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns
1
fall to Output Enable Valid 2.38 2.69 7.04 2.3 2.6 6.8 ns
1
fall to Output Enable Invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns
1
rise to Enable Bytes Valid 1.91 2.52 5.54 1.9 2.5 5.5 ns
1
rise to Enable Bytes Invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns
1
fall to Enable Bytes Valid 1.97 2.59 5.69 1.9 2.5 5.5 ns
1
fall to Enable Bytes Invalid 1.76 2.48 5.38 1.7 2.4 5.2 ns
1
fall to Load Burst Address Valid 2.07 2.79 6.73 2.0 2.7 6.5 ns
1
fall to Load Burst Address Invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns
1
rise to Load Burst Address Invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns
1
rise to Burst Clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns
1
rise to Burst Clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns
1
fall to Burst Clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns
1
fall to Burst Clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns
8a Read Data setup time 5.54 – – 5.5 – – ns
) Invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns
Unit
8b Read Data hold time 0 – – 0 – – ns
1
9a Clock
9b Clock
9c Clock
10a DTACK
rise to Write Data Valid 1.81 2.72 6.85 1.8 2.7 6.8 ns
1
fall to Write Data Invalid 1.45 2.48 5.69 1.4 2.4 5.5 ns
1
rise to Write Data Invalid 1.63 – – 1.62 – – ns
setup time 2.52 – – 2.5 – – ns
1. Clock refers to the system clock signal, HCLK, generated from the System DPLL
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 17
Page 18
Specifications
3.9.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a
data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the
external DTACK
signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal
function when the external DTACK signal is used for data acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of
measure for this figure are found in the associated tables.
MC9328MXS Advance Information, Rev. 0
18 Freescale Semiconductor
Page 19
3.9.2.1 DTACK Read Cycle without DMA
Specifications
Address
CS5
1
programmable
EB
OE
min 0ns
4
DTACK
DATABUS
(input to i.MX)
Figure 6. DTACK Read Cycle without DMA
Table 13. Read Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number Characteristic
3
2
8
9
5
10
6
7
3.0 ± 0.3 V
Unit
Minimum Maximum
1 OE and EB assertion time See note 3 – ns
2 CS5
3 OE
4 D
5 D
6 Data hold timing after OE
7 Data ready after DTACK
8 OE negated to CS negated 0.5T-0.68 0.5T-0.06 ns
9 OE negated after EB negated 0.06 0.18 ns
10 DTACK
Note:
1. DTACK
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
3. OE
EBC bit in CS5L register is clear.
4. Address becomes valid and CS
5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
asserted means DTACK becomes low level.
and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
pulse width 3T – ns
negated to address inactive 46.39 – ns
TACK asserted after CS5 asserted – 1019T ns
TACK asserted to OE negated 3T+1.83 4T+6.6 ns
negated 0–ns
asserted 0Tns
pulse width 1T 3T ns
asserts at the start of read access cycle.
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 19
Page 20
Specifications
3.9.2.2 DTACK Read Cycle DMA Enabled
Address
CS5
1
2
9
10
programmable
4
EB
min 0ns
3
6
7
(logic high)
RW
OE
5
DTACK
11
DATABUS
(input to i.MX)
8
Figure 7. DTACK Read Cycle DMA Enabled
Table 14. Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz
3.0 ± 0.3 V
Number Characteristic
Minimum Maximum
1OE
2CS
3OE
4 Address inactive before CS
5D
6D
7 Data hold timing after OE
8 Data ready after DTACK is asserted – T ns
9CS
10 OE negate after EB negate 0.06 0.18 ns
11 DTACK pulse width 1T 3T ns
Note:
1. DTACK
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
3. OE
EBC bit in CS5L register is clear.
4. Address becomes valid and CS
5. The external DTACK
asserted means DTACK becomes low level.
and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
and EB assertion time See note 3 – ns
pulse width 3T – ns
negated before CS5 is negated 0.5T-0.68 0.5T-0.06 ns
negated – 0.3 ns
TACK asserted after CS5 asserted – 1019T ns
TACK asserted to OE negated 3T+1.83 4T+6.6 ns
negated 0 – ns
deactive to next CS active T – ns
asserts at the start of read access cycle.
input requirement is eliminated when CS5 is programmed to use internal wait state.
Unit
MC9328MXS Advance Information, Rev. 0
20 Freescale Semiconductor
Page 21
3.9.2.3 DTACK Write Cycle without DMA
Address
Specifications
5
1
CS5
programmable
min 0ns
2
EB
RW
(logic high)
OE
DTACK
Databus
(input to i.MX)
programmable
min 0ns
6
9
Figure 8. DTACK Write Cycle without DMA
Table 15. Write Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number Characteristic
3
10
4
7
11
Minimum Maximum
8
3.0 ± 0.3 V
Unit
1CS5
2EB assertion time See note 3 – ns
3CS5 pulse width 3T – ns
4RW negated before CS5 is negated 1.5T-2.44 1.5T-0.8 ns
5RW
6DTACK asserted after CS5 asserted – 1019T ns
7DTACK asserted to RW negated 2T+2.37 3T+6.6 ns
8 Data hold timing after RW
9 Data ready after CS5 is asserted – T ns
10 EB negated after CS5 is negated 0.5T 0.5T+0.5 ns
11 DTACK pulse width 1T 3T ns
Note:
1. DTACK
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
3. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.
4. Address becomes valid and RW
5. The external DTACK
asserted means DTACK becomes low level.
assertion time See note 3 – ns
negated to address inactive 57.31 – ns
negated 1.5T-3.99 – ns
asserts at the start of write access cycle.
input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 21
Page 22
Specifications
3.9.2.4 DTACK Write Cycle DMA Enabled
Address
5
1
programmable
(logic high)
OE
DTACK
CS5
2
EB
RW
min 0ns
programmable
min 0ns
6
9
DATABUS
(output to i.MX)
Figure 9. DTACK Write Cycle DMA Enabled
Table 16. Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number Characteristic
3
4
7
12
3.0 ± 0.3 V
Minimum Maximum
8
10
11
Unit
1C
2EB
3CS5
4RW
5 Address inactive after C
6D
7D
8 Data hold timing after RW
9 Data ready after CS5
10 CS
11 EB
12 DTACK
Note:
1. DTACK
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.
3. CS5
4. Address becomes valid and RW
5.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
S5 assertion time See note 3 – ns
assertion time See note 3 – ns
pulse width 3T – ns
negated before CS5 is negated 1.5T-2.44 1.5T-0.8 ns
S negated – 0.3 ns
TACK asserted after CS5 asserted – 1019T ns
TACK asserted to RW negated 2T+2.37 3T+6.6 ns
negated 1.5T-3.99 – ns
is asserted – T ns
deactive to next CS active T – ns
negate after CS negate 0.5T 0.5T+0.5 ns
pulse width 1T 3T ns
asserted means DTACK becomes low level.
asserts at the start of write access cycle.
MC9328MXS Advance Information, Rev. 0
22 Freescale Semiconductor
Page 23
3.9.2.5 WAIT Read Cycle without DMA
Specifications
3
Address
2
CS5
EB
1
programmable
min 0ns
9
8
5
OE
4
WAIT
67
DATABUS
(input to i.MX)
1110
Figure 10. WAIT Read Cycle without DMA
Table 17. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 ± 0.3 V
Number Characteristic
Minimum Maximum
1OE and EB assertion time See note 2 – ns
2CS5
3OE
4 Wait asserted after OE
5 Wait asserted to OE
6 Data hold timing after OE
7 Data ready after wait asserted 0 T ns
8 OE negated to CS negated 1.5T-0.68 1.5T-0.06 ns
9 OE negated after EB negated 0.06 0.18 ns
10 Become low after CS5 asserted 0 1019T ns
11 Wait pulse width 1T 1020T ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
2. OE
EBC bit in CS5L register is clear.
3. Address becomes valid and CS
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
pulse width 3T – ns
negated to address inactive 56.81 57.28 ns
asserted – 1020T ns
negated 2T+1.57 3T+7.33 ns
negated T-1.49 – ns
asserts at the start of read access cycle.
Unit
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 23
Page 24
Specifications
3.9.2.6 WAIT Read Cycle DMA Enabled
Address
CS5
EB
1
programmable
min 0ns
2
9
10
3
6
4
OE
(logic high)
RW
WAIT
DATABUS
(input to i.MX)
11
5
7
8
12
Figure 11. WAIT Read Cycle DMA Enabled
Table 18. WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 ± 0.3 V
Number Characteristic
Minimum Maximum
1OE and EB assertion time See note 2 – ns
2CS
3OE
4 Address inactived before CS
5 Wait asserted after CS5
6Wait asserted to OE
7 Data hold timing after OE
8 Data ready after wait is asserted – T ns
9CS
10 OE negate after EB negate 0.06 0.18 ns
11 Wait becomes low after CS5 asserted 0 1019T ns
12 Wait pulse width 1T 1020T ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
2. OE
EBC bit in CS5L register is clear.
3. Address becomes valid and CS
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
pulse width 3T – ns
negated before CS5 is negated 1.5T-0.68 1.5T-0.06 ns
negated – 0.05 ns
asserted – 1020T ns
negated 2T+1.57 3T+7.33 ns
negated T-1.49 – ns
deactive to next CS active T ns
asserts at the start of read access cycle.
Unit
MC9328MXS Advance Information, Rev. 0
24 Freescale Semiconductor
Page 25
3.9.2.7 WAIT Write Cycle without DMA
Specifications
Address
1
3
programmable
CS5
EB
RW
(logic high)
OE
WAIT
DATABUS
(output to i.MX)
2
min 0ns
programmable
min 0ns
9
11
10
7
4
6
12
8
Figure 12. WAIT Write Cycle without DMA
Table 19. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 ± 0.3 V
Number Characteristic
Minimum Maximum
5
Unit
1CS5
2EB
3CS5
4RW
5RW
6 Wait asserted after CS5
7 Wait asserted to RW
8 Data hold timing after RW
9 Data ready after CS5
10 EB
11 Wait becomes low after CS5
12 Wait pulse width 1T 1020T ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
assertion can be controlled by CSA bits. EB assertion can also be programable by WEA bits in CS5L register.
2. CS5
3. Address becomes valid and RW
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
assertion time See note 2 – ns
assertion time See note 2 – ns
pulse width 3T – ns
negated before CS5 is negated 2.5T-3.63 2.5T-1.16 ns
negated to Address inactive 64.22 – ns
asserted – 1020T ns
negated T+2.66 2T+7.96 ns
negated 2T+0.03 – ns
is asserted – T ns
negated after CS5 is negated 0.5T 0.5T+0.5 ns
asserted 0 1019T ns
asserts at the start of write access cycle.
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 25
Page 26
Specifications
3.9.2.8 WAIT Write Cycle DMA Enabled
5
10
11
Address
1
CS5
3
programmable
min 0ns
2
programmable
EB
RW
OE
(logic high)
WAIT
DATABUS
(output to i.MX)
min 0ns
12
9
7
4
6
13
8
Figure 13. WAIT Write Cycle DMA Enabled
Table 20. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 ± 0.3 V
Number Characteristic
Minimum Maximum
Unit
1 CS5
2EB
3CS5
4RW
5 Address inactived after CS
6 Wait asserted after CS5
7 Wait asserted to RW
8 Data hold timing after RW
9 Data ready after CS5
10 CS
11 EB
12 Wait becomes low after CS5
13 Wait pulse width 1T 1020T ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
assertion can be controlled by CSA bits. EB assertion also can be programable by WEA bits in CS5L register.
2. CS5
3. Address becomes valid and RW
4.The external wait input requirement is eliminated when CS5
assertion time See note 2 – ns
assertion time See note 2 – ns
pulse width 3T – ns
negated before CS5 is negated 2.5T-3.63 2.5T-1.16 ns
negated – 0.09 ns
asserted – 1020T ns
negated T+2.66 2T+7.96 ns
negated 2T+0.03 – ns
is asserted – T ns
deactive to next CS active T – ns
negate after CS negate 0.5T 0.5T+0.5
asserted 0 1019T ns
asserts at the start of write access cycle.
is programmed to use internal wait state.
MC9328MXS Advance Information, Rev. 0
26 Freescale Semiconductor
Page 27
3.9.3 EIM External Bus Timing
The following timing diagrams show the timing of accesses to memory or a peripheral.
hclk
hsel_weim_cs[0]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS2
R/W
LBA
Seq/Nonseq
Read
V1
Last Valid Data
Last Valid Address
V1
V1
Read
OE
EBx1 (EBC2=0)
1
(EBC2=1)
EBx
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
V1
Figure 14. WSC = 1, A.HALF/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 27
Page 28
Specifications
hsel_weim_cs[0]
hclk
htrans
hwrite
haddr
hready
hwdata
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS0
R/W
Nonseq
Write
V1
Last Valid Data
Last Valid Address
Write Data (V1) Unknown
Last Valid Data
V1
Write
LBA
OE
EB
DATA
Last Valid Data Write Data (V1)
Figure 15. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MC9328MXS Advance Information, Rev. 0
28 Freescale Semiconductor
Page 29
hclk
hsel_weim_cs[0]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS
R/W
LBA
Nonseq
Read
V1
Last Valid Data
Address V1
0
Read
Address V1 + 2Last Valid Addr
V1 Word
OE
EBx1 (EBC2=0)
1
(EBC2=1)
EBx
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
1/2 Half Word 2/2 Half Word
Figure 16. WSC = 1, OEA = 1, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 29
Page 30
Specifications
hsel_weim_cs[0]
hclk
htrans
hwrite
haddr
hready
hwdata
Internal signals - shown only for illustrative purposes
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
CS0
R/W
Nonseq
Write
V1
Last Valid Data
Write Data (V1 Word)
Last Valid Data
Address V1
Address V1 + 2Last Valid Addr
Write
LBA
OE
EB
DATA
1/2 Half Word 2/2 Half Word
Figure 17. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
30 Freescale Semiconductor
Page 31
hclk
hsel_weim_cs[3]
Specifications
htrans
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
hwrite
haddr
[3]
CS
R/W
BA
Nonseq
Read
V1
Last Valid Data
Address V1
V1 Word
Address V1 + 2Last Valid Addr
Read
OE
EBx1 (EBC2=0)
1
(EBC2=1)
EBx
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
1/2 Half Word 2/2 Half Word
Figure 18. WSC = 3, OEA = 2, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 31
Page 32
Specifications
hsel_weim_cs[3]
hclk
htrans
hwrite
haddr
hready
hwdata
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS
R/W
Last Valid
3
Nonseq
Write
V1
Data
Write Data (V1 Word)
Address V1
Last Valid Data
Address V1 + 2Last Valid Addr
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word 2/2 Half Word
Figure 19. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
32 Freescale Semiconductor
Page 33
hclk
hsel_weim_cs[2]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS
R/W
LBA
Nonseq
Read
V1
Last Valid Data
Address V1
2
Read
Address V1 + 2Last Valid Addr
V1 Word
OE
EBx1 (EBC2=0)
1
(EBC2=1)
EBx
weim_data_in
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
1/2 Half Word 2/2 Half Word
Figure 20. WSC = 3, OEA = 4, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 33
Page 34
Specifications
hsel_weim_cs[2]
hclk
htrans
hwrite
haddr
hready
hwdata
Internal signals - shown only for illustrative purposes
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
CS
R/W
Last Valid
2
Nonseq
Write
V1
Data
Address V1
Write Data (V1 Word)
Last Valid Data
Address V1 + 2Last Valid Addr
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word 2/2 Half Word
Figure 21. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
34 Freescale Semiconductor
Page 35
hclk
hsel_weim_cs[2]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS
R/W
LBA
Nonseq
Read
V1
Last Valid Data
Address V1
2
Read
Address V1 + 2Last Valid Addr
V1 Word
OE
EBx1 (EBC2=0)
1
(EBC2=1)
EBx
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
1/2 Half Word 2/2 Half Word
Figure 22. WSC = 3, OEN = 2, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 35
Page 36
Specifications
hclk
hsel_weim_cs[2]
htrans
hwrite
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
haddr
CS2
R/W
LBA
Nonseq
Read
V1
Last Valid Data
Address V1
V1 Word
Address V1 + 2Last Valid Addr
Read
OE
EBx1 (EBC2=0)
1
(EBC2=1)
EBx
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
1/2 Half Word 2/2 Half Word
Figure 23. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
36 Freescale Semiconductor
Page 37
hclk
hsel_weim_cs[2]
Specifications
htrans
hwrite
haddr
hready
hwdata
Internal signals - shown only for illustrative purposes
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
CS2
R/W
Nonseq
Write
V1
Last Valid
Data
Address V1
Write Data (V1 Word)
Last Valid Data
Write
Unknown
Address V1 + 2Last Valid Addr
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word 2/2 Half Word
Figure 24. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 37
Page 38
Specifications
hsel_weim_cs[2]
hclk
htrans
hwrite
haddr
hready
hwdata
Internal signals - shown only for illustrative purposes
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
CS2
R/W
Nonseq
Write
V1
Last Valid
Data
Write Data (V1 Word)
Address V1
Unknown
Last Valid Data
Address V1 + 2Last Valid Addr
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word 2/2 Half Word
Figure 25. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
38 Freescale Semiconductor
Page 39
hclk
hsel_weim_cs[2]
Specifications
hready
hwdata
Internal signals - shown only for illustrative purposes
weim_hrdata
weim_hready
BCLK (burst clock)
htrans
hwrite
haddr
ADDR
CS2
R/W
Nonseq
Read
V1
Last Valid Data
Last Valid Data Read Data
Read
Nonseq
Write
V8
Address V1
Write Data
Address V8Last Valid Addr
Write
LBA
OE
1
EBx
(EBC2=0)
1
EBx
(EBC2=1)
DATA
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Last Valid Data Write Data
Read Data
Figure 26. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 39
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Specifications
Read WriteIdle
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
Internal signals - shown only for illustrative purposes
BCLK (burst clock)
hwdata
weim_hrdata
weim_hready
ADDR
CS
R/W
Nonseq
Read
V1
Last Valid Data
Last Valid Data
2
Read
Nonseq
Write
V8
Write Data
Read Data
Address V1 Address V8Last Valid Addr
Write
LBA
OE
EBx1 (EBC2=0)
1
EBx
(EBC2=1)
DATA
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Read Data
Last Valid Data Write Data
Figure 27. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MC9328MXS Advance Information, Rev. 0
40 Freescale Semiconductor
Page 41
hclk
hsel_weim_cs[4]
Specifications
htrans
hwrite
haddr
hready
hwdata
Internal signals - shown only for illustrative purposes
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
CS
R/W
Nonseq
Write
V1
Last Valid
Data
Write Data (Word)
Last Valid Data
Address V1 Address V1 + 2Last Valid Addr
Write
LBA
OE
EB
DATA
Last Valid Data Write Data (1/2 Half Word) Write Data (2/2 Half Word)
Figure 28. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 41
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Specifications
hclk
hsel_weim_cs[4]
htrans
hwrite
haddr
hready
Internal signals - shown only for illustrative purposes
BCLK (burst clock)
hwdata
weim_hrdata
weim_hready
ADDR
CS
R/W
Nonseq
Read
V1
Last Valid Data
Last Valid Data Read Data
Address V1 Address V8Last Valid Addr
4
Read
Nonseq
Write
V8
Write Data
Write
LBA
OE
1
EBx
(EBC2=0)
1
EBx
(EBC2=1)
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Read Data
Figure 29. WSC = 3, CSA = 1, A.HALF/E.HALF
MC9328MXS Advance Information, Rev. 0
Write DataLast Valid DataDATA
42 Freescale Semiconductor
Page 43
hclk
hsel_weim_cs[4]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS4
R/W
LBA
Nonseq
Read
V1
Last Valid Data
Idle
Seq
Read
V2
Address V1
Read
Read Data (V1)
CNC
Read Data (V2)
Address V2Last Valid
OE
1
EBx
(EBC2=0)
1
EBx
(EBC2=1)
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Read Data
(V1)
Read Data
(V2)
Figure 30. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 43
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Specifications
hsel_weim_cs[4]
hclk
htrans
hwrite
haddr
hready
hwdata
Internal signals - shown only for illustrative purposes
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
CS4
R/W
Nonseq
Read
V1
Last Valid Data
Last Valid Data
Idle
Read
Nonseq
Write
V8
Write Data
Read Data
Address V1 Address V8Last Valid Addr
CNC
Write
LBA
OE
1
(EBC2=0)
EBx
1
EBx
(EBC2=1)
DATA
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Last Valid Data Write Data
Read Data
Figure 31. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MC9328MXS Advance Information, Rev. 0
44 Freescale Semiconductor
Page 45
hclk
hsel_weim_cs[2]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS2
R/W
LBA
Nonseq Nonse
Read Read
V1 V5
Address V1Last Valid Addr Address V5
Idle
Read
OE
EBx1 (EBC2=0)
1
EBx
(EBC2=1)
ECB
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
V1 Word V2 Word V5 Word V6 Word
Figure 32. WSC = 3, SYNC = 1, A.HALF/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 45
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Specifications
hclk
hsel_weim_cs[2]
htrans
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
hwrite
haddr
CS2
R/W
LBA
Nonseq Seq
Read
V1
Last Valid Data V1 Word V2 Word V3 Word V4 Word
Read Read Read
V2 V3 V4
Seq Seq
Address V1Last Valid Addr
Read
Idle
OE
1
(EBC2=0)
EBx
1
EBx
(EBC2=1)
ECB
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
V1 Word V2 Word V3 Word V4 Word
Figure 33. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
MC9328MXS Advance Information, Rev. 0
46 Freescale Semiconductor
Page 47
hclk
hsel_weim_cs[2]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS2
R/W
LBA
Nonseq
Read
V1
Last Valid Data V1 Word V2 Word
Address V1Last Valid
Seq
Read
V2
Address V2
Read
Idle
OE
1
(EBC2=0)
EBx
1
EBx
(EBC2=1)
ECB
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
V1 1/2 V1 2/2 V2 1/2 V2 2/2
Figure 34. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 47
Page 48
Specifications
hclk
hsel_weim_cs[2]
htrans
hwrite
haddr
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS2
R/W
LBA
Non
seq
Read
V1
Last
Seq
Read
V2
Last Valid Data V1 Word V2 Word
Address V1
Read
Idle
OE
EBx1 (EBC2=0)
1
EBx
(EBC2=1)
ECB
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
V1 1/2 V1 2/2 V2 1/2 V2 2/2
Figure 35. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
48 Freescale Semiconductor
Page 49
hclk
hsel_weim_cs[2]
Specifications
htrans
hwrite
haddr
hready
weim_hrdata
Internal signals - shown only for illustrative purposes
weim_hready
BCLK (burst clock)
ADDR
CS2
R/W
LBA
Non
seq
Read
V1
Last
Seq
Read
V2
Last Valid Data V1 Word V2 Word
Address V1
Read
Idle
OE
1
EBx
(EBC2=0)
1
EBx
(EBC2=1)
ECB
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
V1 1/2 V1 2/2 V2 1/2 V2 2/2
Figure 36. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 49
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Specifications
3.9.4 Non-TFT Panel Timing
T1
VSYN
T2
T3
XMAX
T4
HSYN
SCLK
Ts
LD[15:0]
Figure 37. Non-TFT Panel Timing
Table 21. Non TFT Panel Timing Diagram
Symbol Parameter
T1 HSYN to VSYN delay 0 HWAIT2+2 Tpix
Allowed Register Minimum
Value
Actual Value Unit
T1
T2
T2 HSYN pulse width 0 HWIDTH+1 Tpix
T3 VSYN to SCLK – 0<= T3<=Ts –
T4 SCLK to HSYN 0 HWAIT1+1 Tpix
• VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all
these 3 signals are active high.
• Ts is the shift clock period.
• Ts = Tpix * (panel data bus width).
• Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).
• Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.
• Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
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Specifications
3.10 SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI module is configured as a master, two
control signals are used for data transfer rate control: the SS
SPI1 Sample Period Control Register (PERIODREG1) can also be programmed to a fixed data transfer rate. When
the SPI module is configured as a slave, the user can configure the SPI1 Control Register (CONTROLREG1) to
match the external SPI master’s timing. In this configuration, SS
into or load data out to the internal data shift registers, as well as to increment the data FIFO. Figure 38 through
Figure 42 show the timing relationship of the master SPI using different triggering mechanisms.
signal (output) and the SPI_RDY signal (input). The
becomes an input signal, and is used to latch data
SPIRDY
SCLK, MOSI, MISO
Figure 38. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 39. Master SPI Timing Diagram Using SPI_RDY
SS
2
1
3
5
4
Level Trigger
(output)
SS
SCLK, MOSI, MISO
Figure 40. Master SPI Timing Diagram Ignore SPI_RDY
SS (input)
SCLK, MOSI, MISO
Level Trigger
Figure 41. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 51
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Specifications
SS
(input)
6
SCLK, MOSI, MISO
7
Figure 42. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
Table 22. Timing Parameter Table for Figure 38 through Figure 42
3.0 ± 0.3 V
Ref No. Parameter
1 SPI_RDY
2SS
3 Last SCLK edge to SS output high 2 • Tsclk – ns
4SS
5SS
6SS input low to first SCLK edge T – ns
7SS
to SS output low
output low to first SCLK edge
output high to SPI_RDY low 0 – ns
output pulse width
input pulse width T – ns
Minimum Maximum
1
2T
3 • Tsclk
Tsclk + WAIT
2
3
–ns
–ns
–ns
Unit
1. T = CSPI system clock period (PERCLK2).
2. Tsclk = Period of SCLK.
3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.
3.11 LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller
with various display configurations, refer to the LCD controller chapter of the i.MX Reference Manual.
LSCLK
1
LD[15:0]
Figure 43. SCLK to LD Timing Diagram
Table 23. LCDC SCLK Timing Parameter Table
3.0 ± 0.3 V
Ref
No. Parameter
1 SCLK to LD valid – 2 ns
UnitMinimum Maximum
MC9328MXS Advance Information, Rev. 0
52 Freescale Semiconductor
Page 53
T1
T3
Specifications
Display regionNon-display region
T4
VSYN
HSYN
OE
LD[15:0]
HSYN
SCLK
OE
LD[15:0]
VSYN
T2
Line Y
T5
T6
T8
(1,1)
T9 T10
(1,2)
XMAX
Line 1 Line Y
T7
(1,X)
Figure 44. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Table 24. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Symbol Description Minimum Corresponding Register Value Unit
T1 End of OE to beginning of VSYN T5+T6
+T7+T9
T2 HSYN period XMAX+5 XMAX+T5+T6+T7+T9+T10 Ts
T3 VSYN pulse width T2 VWIDTH·(T2) Ts
T4 End of VSYN to beginning of OE 2 VWAIT2·(T2) Ts
T5 HSYN pulse width 1 HWIDTH+1 Ts
T6 End of HSYN to beginning to T9 1 HWAIT2+1 Ts
T7 End of OE to beginning of HSYN 1 HWAIT1+1 Ts
T8 SCLK to valid LD data -3 3 ns
T9 End of HSYN idle2 to VSYN edge
22Ts
(for non-display region)
T9 End of HSYN idle2 to VSYN edge
11Ts
(for Display region)
(VWAIT1·T2)+T5+T6+T7+T9 Ts
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 53
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Specifications
Table 24. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol Description Minimum Corresponding Register Value Unit
T10 VSYN to OE active (Sharp = 0) when VWAIT2 = 0 1 1 Ts
T10 VSYN to OE active (Sharp = 1) when VWAIT2 = 0 2 2 Ts
Note:
• Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
• VSYN, HSYN and OE can be programmed as active high or active low. In Figure 44, all 3 signals are active low.
• The polarity of SCLK and LD[15:0] can also be programmed.
• SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 44, SCLK is always
active.
• For T9 non-display region, VSYN is non-active. It is used as an reference.
• XMAX is defined in pixels.
MC9328MXS Advance Information, Rev. 0
54 Freescale Semiconductor
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Specifications
3.12 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal
is passed through a divider and a prescaler before being input to the counter. The output is available at the pulsewidth modulator output (PWMO) external pin. Its timing diagram is shown in Figure 45 and the parameters are
listed in Table 25.
System Clock
PWM Output
Table 25. PWM Output Timing Parameter Table
Ref
No.
1 System CLK frequency
2a Clock high time
2b Clock low time
3a Clock fall time
Parameter
1
3.3 – 5/10 – ns
1
7.5 – 5/10 – ns
1
2a
1
2b
3a
4a
Figure 45. PWM Output Timing Diagram
1.8 ± 0.1 V 3.0 ± 0.3 V
Minimum Maximum Minimum Maximum
1
0870100MHz
–5–5/10ns
3b
4b
Unit
3b Clock rise time
4a Output delay time
4b Output setup time
1. CL of PWMO = 30 pF
1
1
1
–6.67–5/10ns
5.7 – 5 – ns
5.7 – 5 – ns
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 55
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Specifications
3.13 SDRAM Controller
This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic random
access memory) Controller.
1
SDCLK
2
CS
3S
3
RAS
CAS
WE
ADDR
DQ
DQM
3S
3
S
3H
4S
4H
ROW/BA
3H
COL/BA
8
3S
3S
3H
3H
5
3H
6
Data
7
Note: CKE is high during the read/write cycle.
Figure 46. SDRAM Read Cycle Timing Diagram
Table 26. SDRAM Read Timing Parameter Table
Ref
No.
Parameter
1 SDRAM clock high-level width 2.67 – 4 – ns
2 SDRAM clock low-level width
3 SDRAM clock cycle time 11.4 – 10 – ns
3S CS, RAS, CAS, WE, DQM setup time 3.42 – 3 – ns
3H CS, RAS, CAS, WE, DQM hold time 2.28 – 2 – ns
MC9328MXS Advance Information, Rev. 0
56 Freescale Semiconductor
1.8 ± 0.1 V 3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
6–4–ns
Page 57
Table 26. SDRAM Read Timing Parameter Table (Continued)
Specifications
Ref
No.
Parameter
1.8 ± 0.1 V 3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
4S Address setup time 3.42 – 3 – ns
4H Address hold time 2.28 – 2 – ns
5 SDRAM access time (CL = 3) – 6.84 – 6 ns
5 SDRAM access time (CL = 2) – 6.84 – 6 ns
5 SDRAM access time (CL = 1) – 22 – 22 ns
6 Data out hold time 2.85 – 2.5 – ns
7 Data out high-impedance time (CL = 3) – 6.84 – 6 ns
7 Data out high-impedance time (CL = 2) – 6.84 – 6 ns
7 Data out high-impedance time (CL = 1) – 22 – 22 ns
8 Active to read/write command period (RC = 1)
1. t
= SDRAM clock cycle time. This settings can be found in the i.MX reference manual.
RCD
t
RCD
1
–
t
RCD
1
–ns
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 57
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Specifications
SDCLK
CS
RAS
CAS
WE
3
1
2
6
ADDR
DQ
DQM
4
/ BA
5 7
ROW/BA
8
COL/BA
9
DATA
Figure 47. SDRAM Write Cycle Timing Diagram
Table 27. SDRAM Write Timing Parameter Table
Ref
No.
Parameter
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width 2.67 – 4 – ns
2 SDRAM clock low-level width
3 SDRAM clock cycle time 11.4 – 10 – ns
1.8 ± 0.1 V 3.0 ± 0.3 V
6–4–ns
Unit
4 Address setup time 3.42 – 3 – ns
5 Address hold time 2.28 – 2 – ns
6 Precharge cycle period
1
7 Active to read/write command delay
t
RP
t
RCD
2
2
–
–
t
RP
t
RCD
2
2
–ns
–ns
MC9328MXS Advance Information, Rev. 0
58 Freescale Semiconductor
Page 59
Table 27. SDRAM Write Timing Parameter Table (Continued)
Specifications
Ref
No.
Parameter
Minimum Maximum Minimum Maximum
1.8 ± 0.1 V 3.0 ± 0.3 V
8 Data setup time 4.0 – 2 – ns
9 Data hold time 2.28 – 2 – ns
1. Precharge cycle timing is included in the write timing diagram.
2. tRP and t
SDCLK
RAS
= SDRAM clock cycle time. These settings can be found in the i.MX reference manual.
RCD
3
1 2
CS
6
CAS
7
7
Unit
WE
ADDR
DQ
DQM
4
BA
5
ROW/BA
Figure 48. SDRAM Refresh Timing Diagram
Table 28. SDRAM Refresh Timing Parameter Table
Ref
No.
Parameter
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width 2.67 – 4 – ns
2 SDRAM clock low-level width
1.8 ± 0.1 V 3.0 ± 0.3 V
Unit
6–4–ns
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 59
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Specifications
Table 28. SDRAM Refresh Timing Parameter Table (Continued)
Ref
No.
Parameter
Minimum Maximum Minimum Maximum
1.8 ± 0.1 V 3.0 ± 0.3 V
3 SDRAM clock cycle time 11.4 – 10 – ns
4 Address setup time 3.42 – 3 – ns
5 Address hold time 2.28 – 2 – ns
6 Precharge cycle period
7 Auto precharge command period
1. t
and tRC = SDRAM clock cycle time. These settings can be found in the i.MX reference manual.
RP
SDCLK
CS
RAS
1
t
RP
1
t
RC
–
–
1
t
RP
1
t
RC
–ns
–ns
Unit
CAS
WE
ADDR
DQ
DQM
CKE
BA
Figure 49. SDRAM Self-Refresh Cycle Timing Diagram
MC9328MXS Advance Information, Rev. 0
60 Freescale Semiconductor
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Specifications
3.14 USB Device Port
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers,
and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk
data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and
how they work from the ground up.
Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet
transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of
packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is
no end-of-transfer.
USBD_AFE
(Output)
USBD_ROE
(Output)
USBD_VPO
(Output)
1
t
ROE_VPO
t
PERIOD
6
t
VMO_ROE
4
3
t
VPO_ROE
USBD_VMO
(Output)
USBD_SUSPND
(Output)
USBD_RCV
(Input)
USBD_VP
(Input)
USBD_VM
(Input)
Figure 50. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)
Table 29. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX)
Ref
No.
1t
ROE_VPO
2t
ROE_VMO
3t
VPO_ROE
4t
VMO_ROE
5t
FEOPT
6t
PERIOD
t
ROE_VMO
2
t
FEOPT
5
3.0 ± 0.3 V
Parameter
Unit
Minimum Maximum
; USBD_ROE active to USBD_VPO low 83.14 83.47 ns
; USBD_ROE active to USBD_VMO high 81.55 81.98 ns
; USBD_VPO high to USBD_ROE deactivated 83.54 83.80 ns
; USBD_VMO low to USBD_ROE deactivated (includes SE0) 248.90 249.13 ns
; SE0 interval of EOP 160.00 175.00 ns
; Data transfer rate 11.97 12.03 Mb/s
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 61
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Specifications
USBD_AFE
USBD_ROE
USBD_VPO
USBD_VMO
USBD_SUSPND
USBD_RCV
USBD_VP
(Output)
(Output)
(Output)
(Output)
(Output)
(Input)
(Input)
t
FEOPR
1
USBD_VM
(Input)
Figure 51. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)
Table 30. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
3.0 ± 0.3 V
Ref No. Parameter
1t
; Receiver SE0 interval of EOP 82 – ns
FEOPR
Minimum Maximum
Unit
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Specifications
3.15 I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction,
Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA
5
SCL
1
3
2
4
6
Figure 52. Definition of Bus Timing for I2C
Table 31. I2C Bus Timing Parameter Table
1.8 ± 0.1 V 3.0 ± 0.3 V
Ref No. Parameter
Minimum Maximum Minimum Maximum
1 Hold time (repeated) START condition 182 – 160 – ns
2 Data hold time
3 Data setup time 11.4 – 10 – ns
4 HIGH period of the SCL clock 80 – 120 – ns
5 LOW period of the SCL clock 480 – 320 – ns
6 Setup time for STOP condition 182.4 – 160 – ns
01710150ns
Unit
3.16 Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the
transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the
transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock
mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions
only during transmission. The internal and external clock timing diagrams are shown in Figure 54 through
Figure 56 on page 65.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used
in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division
multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These
distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices.
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 63
Page 64
Specifications
1
STCK Output
STFS (bl) Output
STFS (wl) Output
STXD Output
SRXD Input
Note: SRXD input in synchronous mode only.
Figure 53. SSI Transmitter Internal Clock Timing Diagram
SRCK Output
2
4
6
8
12
10
31
11
32
1
SRFS (bl) Output
SRFS (wl) Output
SRXD Input
3
5
7
13
14
Figure 54. SSI Receiver Internal Clock Timing Diagram
9
MC9328MXS Advance Information, Rev. 0
64 Freescale Semiconductor
Page 65
15
Specifications
16
STCK Input
18
STFS (bl) Input
STFS (wl) Input
STXD Output
SRXD Input
Note: SRXD Input in Synchronous mode only
Figure 55. SSI Transmitter External Clock Timing Diagram
15
16
SRCK Input
17
17
22
26
20
33
24
28
27
34
SRFS (bl) Input
SRFS (wl) Input
SRXD Input
Figure 56. SSI Receiver External Clock Timing Diagram
Table 32. SSI (Port C Primary Function) Timing Parameter Table
Ref No. Parameter
Internal Clock Operation
1 STCK/SRCK clock period
2 STCK high to STFS (bl) high
3 SRCK high to SRFS (bl) high
1
95 – 83.3 – ns
3
19
23
21
25
30
29
1.8 ± 0.1 V 3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
1
(Port C Primary Function2)
1.54.51.33.9ns
3
-1.2 -1.7 -1.1 -1.5 ns
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 65
Page 66
Specifications
Table 32. SSI (Port C Primary Function) Timing Parameter Table (Continued)
1.8 ± 0.1 V 3.0 ± 0.3 V
Ref No. Parameter
Minimum Maximum Minimum Maximum
4 STCK high to STFS (bl) low3 2.54.32.23.8ns
3
5 SRCK high to SRFS (bl) low
6 STCK high to STFS (wl) high
7 SRCK high to SRFS (wl) high
8 STCK high to STFS (wl) low
9 SRCK high to SRFS (wl) low
0.1 -0.8 0.1 -0.8 ns
3
1.48 4.45 1.3 3.9 ns
3
-1.1 -1.5 -1.1 -1.5 ns
3
2.51 4.33 2.2 3.8 ns
3
0.1 -0.8 0.1 -0.8 ns
10 STCK high to STXD valid from high impedance 14.25 15.73 12.5 13.8 ns
11a STCK high to STXD high 0.91 3.08 0.8 2.7 ns
11b STCK high to STXD low 0.57 3.19 0.5 2.8 ns
12 STCK high to STXD high impedance 12.88 13.57 11.3 11.9 ns
13 SRXD setup time before SRCK low 21.1 – 18.5 – ns
14 SRXD hold time after SRCK low 0 – 0 – ns
Unit
2
External Clock Operation (Port C Primary Function
15 STCK/SRCK clock period
1
92.8 – 81.4 – ns
)
16 STCK/SRCK clock high period 27.1 – 40.7 – ns
17 STCK/SRCK clock low period 61.1 – 40.7 – ns
18 STCK high to STFS (bl) high
19 SRCK high to SRFS (bl) high
20 STCK high to STFS (bl) low
21 SRCK high to SRFS (bl) low
22 STCK high to STFS (wl) high
23 SRCK high to SRFS (wl) high
24 STCK high to STFS (wl) low
25 SRCK high to SRFS (wl) low
3
3
3
3
3
3
3
3
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
26 STCK high to STXD valid from high impedance 18.01 28.16 15.8 24.7 ns
27a STCK high to STXD high 8.98 18.13 7.0 15.9 ns
27b STCK high to STXD low 9.12 18.24 8.0 16.0 ns
28 STCK high to STXD high impedance 18.47 28.5 16.2 25.0 ns
29 SRXD setup time before SRCK low 1.14 – 1.0 – ns
30 SRXD hole time after SRCK low 0 – 0 – ns
2
Synchronous Internal Clock Operation (Port C Primary Function
)
31 SRXD setup before STCK falling 15.4 – 13.5 – ns
32 SRXD hold after STCK falling 0 – 0 – ns
MC9328MXS Advance Information, Rev. 0
66 Freescale Semiconductor
Page 67
Specifications
Table 32. SSI (Port C Primary Function) Timing Parameter Table (Continued)
1.8 ± 0.1 V 3.0 ± 0.3 V
Ref No. Parameter
Minimum Maximum Minimum Maximum
Synchronous External Clock Operation (Port C Primary Function2)
33 SRXD setup before STCK falling 1.14 – 1.0 – ns
34 SRXD hold after STCK falling 0 – 0 – ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted
frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and
in the figures.
2. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and
Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed
both at Port C primary function and Port B alternate function. When SSI signals are configured as input, the SSI
module selects the input based on status of the FMCR register bits in the Clock controller module (CRM). By default,
the input are selected from Port C primary function.
bl = bit length; wl = word length.
3.
Table 33. SSI (Port B Alternate Function) Timing Parameter Table
Unit
Ref
No.
Parameter
1 STCK/SRCK clock period
2 STCK high to STFS (bl) high
3 SRCK high to SRFS (bl) high
4 STCK high to STFS (bl) low
5 SRCK high to SRFS (bl) low
6 STCK high to STFS (wl) high
7 SRCK high to SRFS (wl) high
8 STCK high to STFS (wl) low
9 SRCK high to SRFS (wl) low
Internal Clock Operation
1
95 – 83.3 – ns
3
3
-0.1 1.0 -0.1 1.0 ns
3
3.08 5.24 2.7 4.6 ns
3
1.25 2.28 1.1 2.0 ns
3
3
3
3.08 5.24 2.7 4.6 ns
3
1
1.8 ± 0.1 V 3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
(Port B Alternate Function2)
1.7 4.8 1.5 4.2 ns
1.71 4.79 1.5 4.2 ns
-0.1 1.0 -0.1 1.0 ns
1.25 2.28 1.1 2.0 ns
10 STCK high to STXD valid from high impedance 14.93 16.19 13.1 14.2 ns
11a STCK high to STXD high 1.25 3.42 1.1 3.0 ns
11b STCK high to STXD low 2.51 3.99 2.2 3.5 ns
12 STCK high to STXD high impedance 12.43 14.59 10.9 12.8 ns
13 SRXD setup time before SRCK low 20 – 17.5 – ns
14 SRXD hold time after SRCK low 0 – 0 – ns
2
)
15 STCK/SRCK clock period
External Clock Operation (Port B Alternate Function
1
92.8 – 81.4 – ns
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 67
Page 68
Specifications
Table 33. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8 ± 0.1 V 3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
16 STCK/SRCK clock high period 27.1 – 40.7 – ns
17 STCK/SRCK clock low period 61.1 – 40.7 – ns
18 STCK high to STFS (bl) high
19 SRCK high to SRFS (bl) high
20 STCK high to STFS (bl) low
21 SRCK high to SRFS (bl) low
22 STCK high to STFS (wl) high
23 SRCK high to SRFS (wl) high
24 STCK high to STFS (wl) low
25 SRCK high to SRFS (wl) low
3
3
3
3
3
3
3
3
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
– 92.8 0 81.4 ns
26 STCK high to STXD valid from high impedance 18.9 29.07 16.6 25.5 ns
27a STCK high to STXD high 9.23 20.75 8.1 18.2 ns
27b STCK high to STXD low 10.60 21.32 9.3 18.7 ns
28 STCK high to STXD high impedance 17.90 29.75 15.7 26.1 ns
29 SRXD setup time before SRCK low 1.14 – 1.0 – ns
30 SRXD hold time after SRCK low 0 – 0 – ns
2
Synchronous Internal Clock Operation (Port B Alternate Function
)
31 SRXD setup before STCK falling 18.81 – 16.5 – ns
32 SRXD hold after STCK falling 0 – 0 – ns
Synchronous External Clock Operation (Port B Alternate Function
2
)
33 SRXD setup before STCK falling 1.14 – 1.0 – ns
34 SRXD hold after STCK falling 0 – 0 – ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted
frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and
in the figures.
2. There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and
Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed
both at Port C primary function and Port B alternate function. When SSI signals are configured as inputs, the SSI
module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input
are selected from Port C primary function.
3. bl = bit length; wl = word length.
MC9328MXS Advance Information, Rev. 0
68 Freescale Semiconductor
Page 69
Freescale Semiconductor 69
4 Pin-Out and Package Information
Table 34 illustrates the package pin assignments for the 225-contact PBGA package.
Table 34. i.MX 225 PBGA Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A PB13 SSI1_
B PB11 PB12 SSI1_
MC9328MXS Advance Information, Rev. 0
C D31 PB8 SSI1_
D A23 A24 PB9 SSI1_
E A21 A22 D30 D29 NVDD1 QVSS UART2_
F A20 A19 D28 D27 NVDD1 NVDD1 UART2_
RXCLK
G A17 A18 D26 D25 NVDD1 NVSS NVDD4 NVSS NVSS QVSS PWMO PA7 PA11 PA13 PA9
H A15 A16 D23 D24 D22 NVSS NVSS NVSS NVSS NVDD2 PA5 PA12 PA14 I2C_DATA TMS
J A14 A12 D21 D20 NVDD1 NVSS NVSS QVDD1 NVSS PA10 I2C_
K A13 A11 CS2
L A10 A9 D17 D18 NVDD1 NVDD1 CS5
M D16 D15 D13 D10 EB3
SSI1_
TXCLK
RXDAT
RXFS
USBD_
ROE
USBD_
AFE
SSI1_
TXFS
TXDAT
D19 NVDD1 NVSS QVSS NVDD1 NVSS D1 BOOT2 TDI BIG_
USBD_
SUSPND
USBD_
RCV
PB10 USBD_
NVDD1 USBD_VPQVDD4 UART2_
USBD_VM SSI0_
USBD_
VMO
VPO
NVDD1 CS4 CS1
RXFS
SSI0_
RXDAT
UART2_
RXD
RTS
CTS
TXCLK
UART1_
UART1_
RXCLK
SSI0_
TXD
SSI0_
TXFS
TXD
RXD
SSI0_
D2 ECB NVSS NVSS POR QVSS XTAL16M EXTAL32K
SPI1_RDY SPI1_
SPI1_SS LSCLK SPL_
UART1_
RTS
NVDD3 SPI1_
UART1_
CTS
SSI0_
TXDAT
BCLK
SCLK
CONTRAST VSYNC LD8 LD9 LD12 NVDD2
MOSI
SPI1_
MISO
CLS QVDD3 LD14 LD15 PA6 PA8
1
RW NVSS BOOT3 QVDD2 RESET_IN EXTAL16M
REV PS LD2 LD4 LD5
SPR
HSYNC LD1 LD11 TOUT2 LD13
OE_
ACD
CLK
LD0 LD3 LD6 LD7
LD10 TIN PA4 PA3
TCK TDO
ENDIAN
BOOT1 BOOT0
RESET_
OUT
XTAL32K
Pin-Out and Package Information
N A8 A7 D12 EB0 D9 D8 CS3 CS0 PA17 D0 DQM2 DQM0 SDCKE0 TRISTATE TRST
P D14 A5 A4 A3 A2 A1 D6 D5 MA10 MA11 DQM1 RAS SDCKE1 CLKO
R A6 D11 EB1 EB2 OE D7 A0
SDCLK
2
D4 LBA D3 DQM3 CAS SDWE AVDD1
RESETSF
1. Burst Clock
2. These signals are not used on the MC9328MXS and should be floated in an actual application.
2
Page 70
Pin-Out and Package Information
4.1 PBGA 225 Package Dimensions
Figure 57 illustrates the 225 PBGA 13 mm × 13 mm package.
Case Outline 1304B
TOP VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
BOTTOM VIEW SIDE VIEW
Figure 57. i.MX Processor’s 225 PBGA Mechanical Drawing
MC9328MXS Advance Information, Rev. 0
70 Freescale Semiconductor
Page 71
NOTES
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor 71
Page 72
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