Freescale MC9328MX1 Advance Information

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Freescale Semiconductor

Advance Information

MC9328MX1/D
Rev. 3.0, 12/2003

MC9328MX1
(i.MX1) Integrated
Por table System
Processor

MC9328MX1

MC9328MX1/D

Rev. 4, 08/2004

MC9328MX1

Package Information

Plastic Package
(MAPBGA–256)

Ordering Information

See Table 2 on page 5

1 Introduction

Motorola’s i.MX family of microprocessors has
demonstrated leadership in the portable handheld market.
Continuing this legacy, the i.MX series provides a leap in
performance with an ARM9™ microprocessor core and
highly integrated system functions. The i.MX products
specifically address the requirements of the personal,
portable product market by providing intelligent integrated
peripherals, an advanced processor core, and power
management capabilities.

The new MC9328MX1 features the advanced and power­efficient ARM920T™ core that operates at speeds up to
200 MHz. Integrated modules, which include an LCD
controller, static RAM, USB support, an A/D converter (with
touch panel control), and an MMC/SD host controller,
support a suite of peripherals to enhance any product seeking
to provide a rich multimedia experience. In addition, the
MC9328MX1 is the first Bluetooth™ technology-ready
applications processor. It is packaged in a 256-pin Mold
Array Process-Ball Grid Array (MAPBGA). Figure 1 on
page 2 shows the functional block diagram of the
MC9328MX1.

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Signals and Connections . . . . . . . . . . . . . . . . . . . . 6

3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Pin-Out and Package Information . . . . . . . . . . . . 93

Contact Information. . . . . . . . . . . . . . . . . . . Last Page

© Freescale Semiconductor, Inc., 2004. All rights reserved.
This document contains information on a new product. Specifications and information herein are
subject to change without notice.

Introduction

1.1 Conventions

JTAG/ICE

Connectivity

MMC/SD

Memory Stick®
Host Controller

SPI 1 and

SPI 2

UART 1

UART 2 & 3

SSI/I2S 1 & 2

I2C

USB Device

SmartCard I/F

Bluetooth

Accelerator

System Control

Bootstrap

AIPI 1

AIPI 2

Power

Control (DPLLx2)

MC9328MX1

CPU Complex

ARM9TDMI™

I Cache

D Cache

VMMU

eSRAMEIM &

(128K)SDRAMC

CGM

Interrupt

Controller

BusDMAC

Control(11 Chnl)

Figure 1. MC9328MX1 Functional Block Diagram

Standard

System I/O

GPIO

PWM

Timer 1 & 2

RTC

Watchdog

Multimedia

Multimedia
Accelerator

Video Port

Human Interface

Analog Signal

Processor

LCD Controller

This document uses the following conventions:

• OVERBAR

is used to indicate a signal that is active when pulled low: for example, RESET.

• Logic level one is a voltage that corresponds to Boolean true (1) state.

• Logic level zero is a voltage that corresponds to Boolean false (0) state.

•To set a bit or bits means to establish logic level one.

•To clear a bit or bits means to establish logic level zero.

•A signal is an electronic construct whose state conveys or changes in state convey information.

•A pin is an external physical connection. The same pin can be used to connect a number of signals.

• Asserted means that a discrete signal is in active logic state.

— Active low signals change from logic level one to logic level zero.

— Active high signals change from logic level zero to logic level one.

• Negated means that an asserted discrete signal changes logic state.

— Active low signals change from logic level zero to logic level one.

— Active high signals change from logic level one to logic level zero.

• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.

• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are
hexadecimal.

MC9328MX1 Advance Information, Rev. 4

2 Freescale Semiconductor

Introduction

1.2 Features

To support a wide variety of applications, the MC9328MX1 provides a robust array of features, including the
following:

• ARM920T Microprocessor Core

• AHB to IP Bus Interfaces (AIPIs)

• External Interface Module (EIM)

• SDRAM Controller (SDRAMC)

• DPLL Clock and Power Control Module

• Three Universal Asynchronous Receiver/Transmitters (UART 1 UART 2 and UART 3)

• Two Serial Peripheral Interfaces (SPI)

• Two General-Purpose 32-bit Counters/Timers

• Watchdog Timer

• Real-Time Clock/Sampling Timer (RTC)

• LCD Controller (LCDC)

• Pulse-Width Modulation (PWM) Module

• Universal Serial Bus (USB) Device

• Multimedia Card and Secure Digital (MMC/SD) Host Controller Module

• Memory Stick® Host Controller (MSHC)

• SmartCard Interface Module (SIM)

• Direct Memory Access Controller (DMAC)

• Two Synchronous Serial Interfaces and Inter-IC Sound (SSI 1 and SSI 2/I

2

• Inter-IC (I

C) Bus Module

2

S) Module

•Video Port

• General-Purpose I/O (GPIO) Ports

• Bootstrap Mode

• Analog Signal Processing (ASP) Module

• Bluetooth Accelerator (BTA)

• Multimedia Accelerator (MMA)

• 256-pin MAPBGA Package

1.3 Target Applications

The MC9328MX1 is targeted for advanced information appliances, smart phones, Web browsers, digital MP3
audio players, handheld computers based on the popular Palm OS platform, and messaging applications such as
Motorola's wireless cellular products, including the Accompli

TM

008 GSM/GPRS interactive communicator.

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 3

Introduction

1.4 Document Revision History

The following table provides revision history for this release. This history includes technical content revisions only
and not stylistic or grammatical changes.

Table 1. MC9328MX1 Data Sheet Revision History

Revision Location Revision

Throughout Clarified instances where BCLK signal is burst clock.

Table 4 on page 14 Maximum Ratings table replaced.

Section 3.3, “Power Sequence
Requirements” on page 15

Section 3.12, “Bluetooth Accelerator”
on page 58

Added reference to AN2537.

Added “Important” note regarding no software support for the BTA.

1.5 Product Documentation

The following documents are required for a complete description of the MC9328MX1 and are necessary to design
properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall
products, the following documents are helpful when used in conjunction with this manual.

ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)

ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)

ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)

EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)

MC9328MX1 Product Brief (order number MC9328MX1P/D)

MC9328MX1S Reference Manual (order number MC9328MX1SRM/D)

MC68VZ328 Product Brief (order number MC68VZ328P/D)

MC68VZ328 User’s Manual (order number MC68VZ328UM/D)

MC68VZ328 User’s Manual Addendum (order number MC68VZ328UMAD/D)

MC68SZ328 Product Brief (order number MC68SZ328P/D)

MC68SZ328 User’s Manual (order number MC68SZ328UM/D)

The Motorola manuals are available on the Motorola Semiconductors Web site at http://www.motorola.com/
semiconductors. These documents may be downloaded directly from the Motorola Web site, or printed versions
may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.

MC9328MX1 Advance Information, Rev. 4

4 Freescale Semiconductor

Introduction

1.6 Ordering Information

Table 2 provides ordering information for the 256-lead mold array process ball grid array (MAPBGA) package.

Table 2. MC9328MX1 Ordering Information

Package Type Frequency Temperature Solderball Type Order Number

256-lead MAPBGA 200 MHz 0°C to 70°C Standard MC9328MX1VH20(R2)

256-lead MAPBGA 200 MHz 0°C to 70°C Pb-free MC9328MX1VM20(R2)

256-lead MAPBGA 200 MHz -30°C to 70°C Standard MC9328MX1DVH20(R2)

256-lead MAPBGA 200 MHz -30°C to 70°C Pb-free MC9328MX1DVM20(R2)

256-lead MAPBGA 150 MHz -40°C to 85°C Standard MC9328MX1CVH15(R2)

256-lead MAPBGA 150 MHz -40°C to 85°C Pb-free MC9328MX1CVM15(R2)

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 5

Signals and Connections

2 Signals and Connections

Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.

Table 3. Signal Names and Descriptions

Signal Name Function/Notes

External Bus/Chip Select (EIM)

A [24:0] Address bus signals

D [31:0] Data bus signals

EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]

EB1 Byte Strobe—Active low external enable byte signal that controls D [23:16]

EB2 Byte Strobe—Active low external enable byte signal that controls D [15:8]

EB3 LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]

OE Memory Output Enable—Active low output enables external data bus

CS [5:0] Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by

the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.

ECB Active low input signal sent by flash device to the EIM whenever the flash device must terminate an

on-going burst sequence and initiate a new (long first access) burst sequence.

LBA Active low signal sent by flash device causing the external burst device to latch the starting burst

address.

BCLK (burst clock) Clock signal sent to external synchronous memories (such as burst flash) during burst mode.

RW RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE

input signal by external DRAM.

Bootstrap

BOOT [3:0] System Boot Mode Select—The operational system boot mode of the MC9328MX1 upon system

reset is determined by the settings of these pins.

SDRAM Controller

SDBA [4:0] SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11].

These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.

SDIBA [3:0] SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A

[19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash
cycles.

MA [11:10] SDRAM address signals

MA [9:0] SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are selected on

SDRAM/SyncFlash cycles.

MC9328MX1 Advance Information, Rev. 4

6 Freescale Semiconductor

Signals and Connections

Table 3. Signal Names and Descriptions (Continued)

Signal Name Function/Notes

DQM [3:0] SDRAM data enable

CSD0 SDRAM/SyncFlash Chip Select signal which is multiplexed with the CS2 signal. These two signals

are selectable by programming the system control register.

CSD1 SDRAM/SyncFlash Chip Select signal which is multiplex with CS3 signal. These two signals are

selectable by programming the system control register. By default, CSD1 is selected, so it can be
used as SyncFlash boot chip select by properly configuring BOOT [3:0] input pins.

RAS SDRAM/SyncFlash Row Address Select signal

CAS SDRAM/SyncFlash Column Address Select signal

SDWE SDRAM/SyncFlash Write Enable signal

SDCKE0 SDRAM/SyncFlash Clock Enable 0

SDCKE1 SDRAM/SyncFlash Clock Enable 1

SDCLK SDRAM/SyncFlash Clock

RESET_SF SyncFlash Reset

Clocks and Resets

EXTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when internal oscillator circuit is shut

down.

XTAL16M Crystal output

EXTAL32K 32 kHz crystal input

XTAL32K 32 kHz crystal output

CLKO Clock Out signal selected from internal clock signals. Please refer to clock controller for internal

clock selection.

RESET_IN Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all

modules (except the reset module and the clock control module) are reset.

RESET_OUT Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from

the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.

POR Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally

generated by an external RC circuit designed to detect a power-up event.

JTAG

TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

TDO Serial Output for test instructions and data. Changes on the falling edge of TCK.

TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK.

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 7

Signals and Connections

Table 3. Signal Names and Descriptions (Continued)

Signal Name Function/Notes

TCK Test Clock to synchronize test logic and control register access through the JTAG port.

TMS Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge

of TCK.

System

BIG_ENDIAN BIG_ENDIAN—This signal determines the memory endian configuration. BIG_ENDIAN is a static

pin to inner module. If the pin is driven logic-high the memory system is configured into big endian. If
it is driven logic-low the memory system is configured into little endian. The pin is not supposed to
be changed on the fly.

ETM

ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.

ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.

ETMPIPESTAT [2:0] ETM status signals which are multiplex with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM

mode.

ETMTRACEPKT [7:0] ETM packet signals which are multiplex with ECB, LBA, BCLK (burst clock), PA17, A [19:16].

ETMTRACEPKT [7:0] are selected in ETM mode.

CMOS Sensor Interface

CSI_D [7:0] Sensor port data

CSI_MCLK Sensor port master clock

CSI_VSYNC Sensor port vertical sync

CSI_HSYNC Sensor port horizontal sync

CSI_PIXCLK Sensor port data latch clock

LCD Controller

LD [15:0] LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.

FLM/VSYNC Frame Sync or Vsync—This signal also serves as the clock signal output for gate.

driver (dedicated signal SPS for Sharp panel HR-TFT).

LP/HSYNC Line Pulse or H Sync

LSCLK Shift Clock

ACD/OE Alternate Crystal Direction/Output Enable

CONTRAST This signal is used to control the LCD bias voltage as contrast control.

SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal).

MC9328MX1 Advance Information, Rev. 4

8 Freescale Semiconductor

Signals and Connections

Table 3. Signal Names and Descriptions (Continued)

Signal Name Function/Notes

PS Control signal output for source driver (Sharp panel dedicated signal).

CLS Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal).

REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal).

SIM

SIM_CLK SIM Clock

SIM_RST SIM Reset

SIM_RX Receive Data

SIM_TX Transmit Data

SIM_PD Presence Detect Schmitt trigger input

SIM_SVEN SIM Vdd Enable

SPI

SPI1_MOSI Master Out/Slave In

SPI1_MISO Slave In/Master Out

SPI1_SS Slave Select (Selectable polarity)

SPI1_SCLK Serial Clock

SPI1_SPI_RDY Serial Data Ready

SPI2_TXD SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin however it does show up

as a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, “Serial
Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module and I/O Multiplexer
(IOMUX),” for information on how to bring this signal to the assigned pin.

SPI2_RXD SPI2 master RxData input—This signal is multiplexed with a GPI/O pin however it does show up as

a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, “Serial
Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module and I/O Multiplexer
(IOMUX),” for information on how to bring this signal to the assigned pin.

SPI2_SS SPI2 Slave Select—This signal is multiplexed with a GPI/O pin, however it does show up as a

primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, “Serial
Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module and I/O Multiplexer
(IOMUX),” for information on how to bring this signal to the assigned pin.

SPI2_SCLK SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin however it does show up as a

primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, “Serial
Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module and I/O Multiplexer
(IOMUX),” for information on how to bring this signal to the assigned pin.

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 9

Signals and Connections

Table 3. Signal Names and Descriptions (Continued)

Signal Name Function/Notes

General Purpose Timers

TIN Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers

simultaneously.

TMR2OUT Timer 2 Output

USB Device

USBD_VMO USB Minus Output

USBD_VPO USB Plus Output

USBD_VM USB Minus Input

USBD_VP USB Plus Input

USBD_SUSPND USB Suspend Output

USBD_RCV USB RxD

USBD_OE USB OE

USBD_AFE USB Analog Front End Enable

Secure Digital Interface

SD_CMD SD Command—If the system designer does not want to make use of the internal pull-up, via the

Pull-up enable register, a 4.7K–69K external pull up resistor must be added.

SD_CLK MMC Output Clock

SD_DAT [3:0] Data—If the system designer does not want to make use of the internal pull-up, via the Pull-up

enable register, a 50 K–69K external pull up resistor must be added.

Memory Stick Interface

MS_BS Memory Stick Bus State (Output)—Serial bus control signal

MS_SDIO Memory Stick Serial Data (Input/Output)

MS_SCLKO Memory Stick Serial Clock (Output)—Serial Protocol clock output

MS_SCLKI Memory Stick External Clock (Input)—Test clock input pin for SCLK divider. This pin is only for test

purposes, not for use in application mode.

MS_PI0 General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect

MS_PI1 General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect

UARTs – IrDA/Auto-Bauding

UART1_RXD Receive Data

MC9328MX1 Advance Information, Rev. 4

10 Freescale Semiconductor

Table 3. Signal Names and Descriptions (Continued)

Signal Name Function/Notes

UART1_TXD Transmit Data

UART1_RTS Request to Send

UART1_CTS Clear to Send

UART2_RXD Receive Data

UART2_TXD Transmit Data

UART2_RTS Request to Send

UART2_CTS Clear to Send

UART2_DSR Data Set Ready

UART2_RI Ring Indicator

UART2_DCD Data Carrier Detect

UART2_DTR Data Terminal Ready

Signals and Connections

UART3_RXD Receive Data

UART3_TXD Transmit Data

UART3_RTS Request to Send

UART3_CTS Clear to Send

UART3_DSR Data Set Ready

UART3_RI Ring Indicator

UART3_DCD Data Carrier Detect

UART3_DTR Data Terminal Ready

Serial Audio Ports – SSI (configurable to I2S protocol)

SSI1_TXDAT TxD

SSI1_RXDAT RxD

SSI1_TXCLK Transmit Serial Clock

SSI1_RXCLK Receive Serial Clock

SSI1_TXFS Transmit Frame Sync

SSI1_RXFS Receive Frame Sync

SSI2_TXDAT TxD

SSI2_RXDAT RxD

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 11

Signals and Connections

Table 3. Signal Names and Descriptions (Continued)

Signal Name Function/Notes

SSI2_TXCLK Transmit Serial Clock

SSI2_RXCLK Receive Serial Clock

SSI2_TXFS Transmit Frame Sync

SSI2_RXFS Receive Frame Sync

I2C

I2C_SCL I2C Clock

I2C_SDA I2C Data

PWM

PWMO PWM Output

ASP

UIN Positive U analog input (for low voltage, temperature measurement)

UIP Negative U analog input (for low voltage, temperature measurement)

PX1 Positive pen-X analog input

PY1 Positive pen-Y analog input

PX2 Negative pen-X analog input

PY2 Negative pen-Y analog input

R1A Positive resistance input (a)

R1B Positive resistance input (b)

R2A Negative resistance input (a)

R2B Negative resistance input (b)

RVP Positive reference for pen ADC

RVM Negative reference for pen ADC

AVDD Analog power supply

AGND Analog ground

BlueTooth

BT1 I/O clock signal

BT2 Output

MC9328MX1 Advance Information, Rev. 4

12 Freescale Semiconductor

Table 3. Signal Names and Descriptions (Continued)

Signal Name Function/Notes

BT3 Input

BT4 Input

BT5 Output

BT6 Output

BT7 Output

BT8 Output

BT9 Output

BT10 Output

BT11 Output

BT12 Output

BT13 Output

Signals and Connections

TRISTATE Sets all I/O pins to tristate; Can be used for flash loading and is pulled low for normal operations.

BTRF VDD Power supply from external BT RFIC

BTRF GND Ground from external BT RFIC

Noisy Supply Pins

NVDD Noisy Supply for the I/O pins

NVSS Noisy Ground for the I/O pins

Supply Pins – Analog Modules

AVDD Supply for analog blocks

AVSS Quiet GND for analog blocks

Internal Power Supply

QVDD Power supply pins for silicon internal circuitry

QVSS GND pins for silicon internal circuitry

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 13

Specifications

3 Specifications

This section contains the electrical specifications and timing diagrams for the MC9328MX1 processor.

3.1 Maximum Ratings

Table 4 provides information on maximum ratings which are those values beyond which damage to the device may
occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on
page 15 or the DC Characteristics table.

Table 4. Maximum Ratings

Symbol Rating Minimum Maximum Unit

1

NV

dd

QV

dd

AV

dd

BTRFV

dd

V

dd

T

A

T

A

T

A

VESD_HBM ESD at human body model (HBM) – 2000 V

VESD_MM ESD at machine model (MM) – 100 V

ILatchup Latch-up current – 200 mA

Test Storage temperature -55 150 °C

DC I/O Supply Voltage – – V

DC Internal (core) Supply Voltage – – V

DC Analog Supply Voltage – – V

DC Bluetooth Supply Voltage – – V

Supply voltage -0.3 3.3 V

Maximum operating temperature range
MC9328MX1VH20/MC9328MX1VM20

Maximum operating temperature range
MC9328MX1DVH20/MC9328MX1DVM20

Maximum operating temperature range
MC9328MX1CVH15/MC9328MX1CVM15

070°C

-30 70 °C

-40 85 °C

Pmax Power Consumption

1. Voltages referenced to Vss and BTRFGND, which are both tied to the same potential.

2. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from
the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.

3. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches
from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core
running its heaviest OS application at 200MHz, and where the whole image is running out of SDRAM. QVDD at

2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment,
max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.

MC9328MX1 Advance Information, Rev. 4

14 Freescale Semiconductor

800

2

1300

3

mW

Specifications

3.2 Recommended Operating Range

Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MX1 processor has
multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic.
All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power
to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system.

Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the
AVDD pins from other VDD pins.

BTRFVDD is the supply voltage for the Bluetooth interface signals. It is quite sensitive to the data transmit/receive
accuracy. Please refer to Bluetooth RF spec for special handling. If Bluetooth is not used in the system, these
Bluetooth pins can be used as general purpose I/O pins and BTRFVDD can be used as other NVDD pins.

For more information about I/O pads grouping per VDD, please refer to Table 3 on page 6.

Table 5. Recommended Operating Range

Symbol Rating Minimum Maximum Unit

1

NVDD I/O supply voltage MSHC, SPI, BTA, USBd, LCD and

CSI are only 3V interface

NVDD I/O supply voltage 1.70 3.30 V

QVDD Internal supply voltage (Core =

150 MHz)

QVDD Internal supply voltage (Core =

200 MHz)

AVDD Analog supply voltage 1.70 3.30 V

BTRFVD

D

BTRFVD

D

1. Voltages referenced to Vss and BTRFGND, which are both tied to the same potential.

Bluetooth I/O voltage (Bluetooth) 1.70 3.10 V

1

Bluetooth I/O voltage (Non Bluetooth
applications)

2

2.70 3.30 V

1.70 1.90 V

1.80 2.00 V

1.70 3.30 V

3.3 Power Sequence Requirements

For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of
application note AN2537 on the i.MX website page.

3.4 DC Electrical Characteristics

Table 6 contains both maximum and minimum DC characteristics of the MC9328MX1.

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 15

Specifications

Table 6. Maximum and Minimum DC Characteristics

Number

or Symbol

Parameter Minimum Typical Maximum Unit

Iop Full running operating current at 1.8V for

QVDD, 3.3V for NVDD/AVDD (Core = 96 MHz,
System = 96 MHz, MPEG4 decoding playback
from external memory card to both external SSI
audio decoder and TFT display panel, and OS
with MMU enabled memory system is running
on external SDRAM)

Please refer to application note: AN2537,
Power Performance of MC9328MX1.

Sidd

Sidd

Sidd

Sidd

V

V

V

OH

IH

IL

Standby current (QVDD = 1.8V, temp = 25°C) – 25 – µA

1

Standby current (QVDD = 1.8V, temp = 55°C) – 45 – µA

2

Standby current (QVDD = 2.0V, temp = 25°C) – 35 – µA

3

Standby current (QVDD = 2.0V, temp = 55°C) – 60 – µA

4

Input high voltage 0.7V

Input low voltage – – 0.4 V

Output high voltage (IOH= 2.0 mA) 0.7V

– QVDD at 1.8v

= 120mA; NVDD+AVDD

at 3.0v = 30mA

DD

DD

– Vdd+0.2 V

–VddV

–mA

V

I

I

I

C

OL

I

IL

I

IH

OH

OL

OZ

C

Output low voltage (IOL= -2.5 mA) – – 0.4 V

Input low leakage current

––±1µA

(VIN= GND, no pull-up or pull-down)

Input high leakage current
(V

IN=VDD

, no pull-up or pull-down)

Output high current

––±1µA

––4.0mA

(VOH=0.8VDD, VDD=1.8V)

Output low current

=0.4V, VDD=1.8V)

(V

OL

Output leakage current
(V

out=VDD

i

o

Input capacitance – – 5 pF

Output capacitance – – 5 pF

, output is tri-stated)

−4.0

––±5µA

––mA

MC9328MX1 Advance Information, Rev. 4

16 Freescale Semiconductor

Specifications

3.5 AC Electrical Characteristics

The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are
specified relative to an appropriate edge of other signals. All timing specifications are specified at a system
operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage
from V

TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z – 20.8 ns

DD min

to V

DD max

under an operating temperature from TL to TH. All timing is measured at 30 pF loading.

Table 7. Tri-State Signal Timing

Pin Parameter Minimum Maximum Unit

Table 8. 32k/16M Oscillator Signal Timing

Parameter Minimum RMS Maximum Unit

EXTAL32k input jitter (peak to peak) for both System PLL and
MCUPLL

EXTAL32k input jitter (peak to peak) for MCUPLL only – 5 100 ns

EXTAL32k startup time 800 – – ms

EXTAL16M input jitter (peak to peak) – TBD TBD –

EXTAL16M startup time TBD – – –

– 5 20 ns

Table 9. CLKO Rise/Fall Time (at 30pF Loaded)

Best

Case

Rise Time 0.80 1.00 1.40 ns

Fall Time 0.74 1.08 1.67 ns

Typical

Worst

Case

Units

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 17

Specifications

3.6 Embedded Trace Macrocell

All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift
register comprised of the following:

• 32-bit data field

• 7-bit address field

• A read/write bit

The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field,
and a 1 into the read/write bit.

A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field
is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing
diagram for the ETM9 is shown in Figure 2. See Table 10 on page 18 for the ETM9 timing parameters used in
Figure 2.

TRACECLK

TRACECLK

(Half-Rate Clocking Mode)

Output Trace Port

3a

2a

2b

3b

Valid Data

4a

1

Valid Data

4b

Figure 2. Trace Port Timing Diagram

Table 10. Trace Port Timing Diagram Parameter Table

1.8V +/- 0.10V 3.0V +/- 0.30V

Ref No. Parameter

MinimumMaximumMinimumMaximum

1 CLK frequency 0 85 0 100 MHz

2a Clock high time 1.3 – 2 – ns

Unit

2b Clock low time 3 – 2 – ns

3a Clock rise time – 4 – 3 ns

3b Clock fall time – 3 – 3 ns

4a Output hold time 2.28 – 2 – ns

4b Output setup time 3.42 – 3 – ns

MC9328MX1 Advance Information, Rev. 4

18 Freescale Semiconductor

3.7 DPLL Timing Specifications

Specifications

Parameters of the DPLL are given in Table 11. In this table, T
and T

is the output double clock period.

dck

is a reference clock period after the pre-divider

ref

Table 11. DPLL Specifications

Parameter Test Conditions Minimum Typical Maximum Unit

Reference clock freq range Vcc = 1.8V 5 – 100 MHz

Pre-divider output clock
freq range

Double clock freq range Vcc = 1.8V 80 – 220 MHz

Pre-divider factor (PD) – 1 – 16 –

Total multiplication factor
(MF)

MF
integer part

MF
numerator

MF
denominator

Vcc = 1.8V 5 – 30 MHz

Includes both integer
and fractional parts

–5–15–

Should be less than the
denominator

– 1 – 1023 –

5–15–

0 – 1022 –

Pre-multiplier lock-in time – – – 312.5

Freq lock-in time after
full reset

Freq lock-in time after
partial reset

Phase lock-in time after
full reset

Phase lock-in time after
partial reset

Freq jitter (p-p) – – 0.005

Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V – 1.0

Power supply voltage – 1.7 – 2.5 V

Power dissipation FOL mode, integer MF,

FOL mode for non-integer MF
(does not include pre-must lock-in time)

FOL mode for non-integer MF (does not
include pre-multi lock-in time)

FPL mode and integer MF (does not include
pre-multi lock-in time)

FPL mode and integer MF (does not include
pre-multi lock-in time)

f

= 200 MHz, Vcc = 1.8V

dck

250 280

(56 µs)

220 250

(~50 µs)

300 350

(70 µs)

270 320

(64 µs)

(0.01%)

(10%)

––4mW

300 T

270 T

400 T

370 T

0.01 2•T

1.5 ns

µsec

ref

ref

ref

ref

dck

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 19

Specifications

3.8 Reset Module

The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4.

NOTE:

Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up
to prevent forward biasing.

90% AVDD

1

POR

10% AVDD

RESET_POR

RESET_DRAM

HRESET

RESET_OUT

CLK32

HCLK

2

Exact 300ms

3

Figure 3. Timing Relationship with POR

7 cycles @ CLK32

4

14 cycles @ CLK32

MC9328MX1 Advance Information, Rev. 4

20 Freescale Semiconductor

RESET_IN

Specifications

5

HRESET

RESET_OUT

CLK32

HCLK

Ref
No.

6

Figure 4. Timing Relationship with RESET_IN

Table 12. Reset Module Timing Parameter Table

1.8V +/- 0.10V 3.0V +/- 0.30V

Parameter

Min Max Min Max

14 cycles @ CLK32

4

Unit

1 Width of input POWER_ON_RESET

2 Width of internal POWER_ON_RESET

note

1

–

300 300 300 300 ms

note

1

––

(9600 *CLK32 at 32 KHz)

3 7K to 32K-cycle stretcher for SDRAM reset 7 7 7 7 Cycles of

CLK32

4 14K to 32K-cycle stretcher for internal system reset

HRESERT

and output reset at pin RESET_OUT

14 14 14 14 Cycles of

CLK32

5 Width of external hard-reset RESET_IN 4 – 4 – Cycles of

CLK32

6 4K to 32K-cycle qualifier 4 4 4 4 Cycles of

CLK32

1. POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should

allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence.
Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have
developed a working knowledge of start-up time of their crystals. Typically, start-up times range from
400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should
be ignored in calculating timing for the start-up process.

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 21

Specifications

3.9 External Interface Module

The External Interface Module (EIM) handles the interface to devices external to the MC9328MX1, including
generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in
Figure 5, and Table 13 defines the parameters of signals.

(HCLK) Bus Clock

1a 1b

Address

Chip-select

Read (Write

)

2a 2b

3b3a

(rising edge)

OE

(falling edge)

OE

EB

(rising edge)

EB

(falling edge)

(negated falling edge)

LBA

LBA

(negated rising edge)

BCLK (burst clock) - rising edge

BCLK (burst clock) - falling edge

Read Data

Write Data (negated falling)

Write Data (negated rising)

DTACK_B

4a 4b

4c 4d

5a 5b

5c 5d

6a

6a

7a 7b

7c

9a

9a

10a

6c

7d

8a

10a

6b

8b

9b

9c

Figure 5. EIM Bus Timing Diagram

Table 13. EIM Bus Timing Parameter Table

± 0.10V 3.0 ± 0.3V

1.8

Ref No. Parameter

Min Typical Max Min Typical Max

1a Clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns

MC9328MX1 Advance Information, Rev. 4

22 Freescale Semiconductor

Unit

Specifications

Table 13. EIM Bus Timing Parameter Table (Continued)

± 0.10V 3.0 ± 0.3V

1.8

Ref No. Parameter

Min Typical Max Min Typical Max

1b Clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns

2a Clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns

2b Clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns

Unit

3a Clock fall to Read (Write

3b Clock fall to Read (Write

4a Clock

4b Clock

4c Clock

4d Clock

5a Clock

5b Clock

5c Clock

5d Clock

6a Clock

6b Clock

6c Clock

7a Clock

1

rise to Output Enable Valid 2.32 2.62 6.85 2.3 2.6 6.8 ns

1

rise to Output Enable Invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns

1

fall to Output Enable Valid 2.38 2.69 7.04 2.3 2.6 6.8 ns

1

fall to Output Enable Invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns

1

rise to Enable Bytes Valid 1.91 2.52 5.54 1.9 2.5 5.5 ns

1

rise to Enable Bytes Invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns

1

fall to Enable Bytes Valid 1.97 2.59 5.69 1.9 2.5 5.5 ns

1

fall to Enable Bytes Invalid 1.76 2.48 5.38 1.7 2.4 5.2 ns

1

fall to Load Burst Address Valid 2.07 2.79 6.73 2.0 2.7 6.5 ns

1

fall to Load Burst Address Invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns

1

rise to Load Burst Address Invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns

1

rise to Burst Clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns

) Valid 1.35 2.79 6.52 1.3 2.7 6.3 ns

) Invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns

7b Clock

7c Clock

7d Clock

1

rise to Burst Clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns

1

fall to Burst Clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns

1

fall to Burst Clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns

8a Read Data setup time 5.54 – – 5.5 – – ns

8b Read Data hold time 0 – – 0 – – ns

9a Clock

9b Clock

9c Clock

10a DTACK

1

rise to Write Data Valid 1.81 2.72 6.85 1.8 2.7 6.8 ns

1

fall to Write Data Invalid 1.45 2.48 5.69 1.4 2.4 5.5 ns

1

rise to Write Data Invalid 1.63 – – 1.62 – – ns

setup time 2.52 – – 2.5 – – ns

1. Clock refers to the system clock signal, HCLK, generated from the System DPLL

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 23

Specifications

3.9.1 DTACK Signal Description

The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a
data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the
external DTACK

signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal

function when the external DTACK signal is used for data acknowledgement.

3.9.2 DTACK Signal Timing

Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of
measure for this figure are found in the associated tables.

3.9.2.1 DTACK READ Cycle without DMA

(3)

Address

(2)

CS5

EB

OE

(1)

programmable
min 0ns

(5)

(8)

(9)

(4)

DTACK

(6)

Databus
(input to MX1)

(10)

(7)

Figure 6. DTACK READ Cycle without DMA

Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz

(3.0 ± 0.3) V

Number Characteristic

Minimum Maximum

1OE and EB assertion time See note 2 – ns

2CS5

3OE

4 DTACK asserted after CS5 asserted – 1019T ns

24 Freescale Semiconductor

pulse width 3T – ns

negated to address inactive 46.44 – ns

MC9328MX1 Advance Information, Rev. 4

Unit

Specifications

(4)

Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)

(3.0 ± 0.3) V

Number Characteristic

Minimum Maximum

5 DTACK asserted to OE negated 3T+2.2 4T+6.86 ns

Unit

6 Data hold timing after OE

7 Data ready after DTACK

8 OE negated to CS negated 0.5T+0.24 0.5T+0.67 ns

9 OE negated after EB negated 0.5 1.5 ns

10 DTACK

Note:

0. DTACK

1. T is the system clock period. (For 96MHz system clock)

2. OE
only when EBC bit in CS5L register is clear.

3. Address becomes valid and CS

4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.

assert means DTACK become low level.

and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur

pulse width 1T 3T ns

negated 0 – ns

asserted 0 T ns

asserts at the start of read access cycle.

3.9.2.2 DTACK Read Cycle DMA Enabled

Address

CS5

(2)

(9)

EB

(1)

programmable
min 0ns

(10)

(3)

OE

(logic high)

RW

(5)

DTACK

(6)

(7)

Databus
(input to MX1)

(11)

(8)

Figure 7. DTACK Read Cycle DMA Enabled

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 25

Specifications

Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz

Number Characteristic

(3.0 ± 0.3) V

Unit

Minimum Maximum

1OE

2CS

3OE

4 Address inactive before CS

5 DTACK

6 DTACK

7 Data hold timing after OE

8 Data ready after DTACK is asserted – T ns

9CS

10 OE negate after EB negate 0.5 1.5 ns

11 DTACK

Note:

0. DTACK assert mean DTACK become low.

1. T is the system clock period. (For 96MHz system clock)

2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only
when EBC bit in CS5L register is clear.

3. Address becomes valid and CS

4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.

and EB assertion time See note 2 – ns

pulse width 3T – ns

negated before CS5 is negated 0.5T+0.24 0.5T+0.67 ns

negated – 0.93 ns

asserted after CS5 asserted – 1019T ns

asserted to OE negated 3T+2.2 4T+6.86 ns

negated 0 – ns

deactive to next CS active T – ns

pulse width 1T 3T ns

asserts at the start of read access cycle.

MC9328MX1 Advance Information, Rev. 4

26 Freescale Semiconductor

3.9.2.3 DTACK Write Cycle without DMA

Specifications

(5)

Address

CS5

EB

(1)

(2)

(3)

programmable

min 0ns

(10)

programmable

min 0ns

(4)

RW

(logic high)

OE

DTACK

Databus
(output from MX1)

(6)

(9)

(7)

(11)

(8)

Figure 8. DTACK Write Cycle without DMA

Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz

(3.0 ± 0.3) V

Number Characteristic

Minimum Maximum

1CS5

2EB

3CS5

4RW

5RW

6 DTACK

7 DTACK asserted to RW negated 2T+1.8 3T+5.26 ns

8 Data hold timing after RW

9 Data ready after CS5

10 EB

11 DTACK

assertion time See note 2. – ns

assertion time See note 2 – ns

pulse width 3T – ns

negated before CS5 is negated 1.5T+0.58 1.5T+1.58 ns

negated to Address inactive 57.31 – ns

asserted after CS5 asserted – 1019T ns

negated 1.5T-0.59 – ns

is asserted – T ns

negated before CS5 is negated 0.5T+0.74 0.5T+2.17 ns

pulse width 1T 3T ns

Unit

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 27

Specifications

(5)

Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)

(3.0 ± 0.3) V

Number Characteristic

Minimum Maximum

Note:

0. DTACK assert mean DTACK become low.

1. T is the system clock period. (For 96MHz system clock)

2. CS5

assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.

3. Address becomes valid and RW

4. The external DTACK

input requirement is eliminated when CS5 is programmed to use internal wait state.

asserts at the start of write access cycle.

3.9.2.4 DTACK Write Cycle DMA Enabled

Unit

(3)

(10)

(11)

Address

CS5

EB

(1)

(2)

programmable

min 0ns

programmable

min 0ns

(4)

RW

(logic high)

OE

DTACK

Databus
(output from MX1)

(6)

(9)

(7)

(12)

(8)

Figure 9. DTACK Write Cycle DMA Enabled

Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz

Number Characteristic

Minimum Maximum

1 CS5

2EB

3CS5

4RW

5 Address inactive before CS

6 DTACK

28 Freescale Semiconductor

assertion time See note 2 – ns

assertion time See note 2 – ns

pulse width 3T – ns

negated before CS5 is negated 1.5T+0.58 1.5T+1.58 ns

negated – 0.93 ns

asserted after CS5 asserted – 1019T ns

MC9328MX1 Advance Information, Rev. 4

(3.0 ± 0.3) V

Unit

Specifications

Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz (Continued)

(3.0 ± 0.3) V

Number Characteristic

Minimum Maximum

7 DTACK asserted to RW negated 2T+1.8 3T+5.26 ns

Unit

8 Data hold timing after RW

9 Data ready after CS5

10 CS

11 EB

12 DTACK

deactive to next CS active T – ns

negate to CS negate 0.5T+0.74 0.5T+2.17 ns

pulse width 1T 3T ns

negated 1.5T-0.59 – ns

is asserted – T ns

Note:

0. DTACK assert mean DTACK become low.

1. T is the system clock period. (For 96MHz system clock)

2. CS5

assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.

3. Address becomes valid and RW

4.The external DTACK

input requirement is eliminated when CS5 is programmed to use internal wait state.

asserts at the start of write access cycle.

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor 29