Freescale MC68HC908JL3E, MC68HC908JK3E, MC68HC908JK1E, MC68HRC908JL3E, MC68HRC908JK3E Technical Data

...

MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E MC68HLC908JL3E/JK3E/JK1E MC68HC908KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E

Data Sheet

M68HC08 Microcontrollers

MC68HC908JL3E Rev. 3 11/2004

freescale.com

MC68HC908JL8/JK3E/JK1E MC68HRC908JL8/JK3E/JK1E MC68HLC908JL8/JK3E/JK1E MC68HC908KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E

Data Sheet

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://www.freescale.com

The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST.

MC68HC908JL3E Family Data Sheet, Rev. 3

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Revision History

Date

Nov 2004 3

Dec 2002 2

May 2002 2 First general release. —

Revision

Level

Description

Added appendix B for ROM parts. 159–166

Added appendix C for ADC-less parts. 167–170

Added appendix A for low-volt devices. 153–224

Updated Monitor Mode Circuit (Figure 7-1) and Monitor Mode Entry Requirements and Options (Table 7-1) in Monitor ROM section.

Page

Number(s)

76, 77

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List of Chapters

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Chapter 3 Configuration Registers (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Chapter 5 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Chapter 6 Oscillator (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Chapter 7 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Chapter 8 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Chapter 9 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Chapter 10 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Chapter 11 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Chapter 12 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Chapter 13 Computer Operating Properly (COP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Chapter 14 Low Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Chapter 15 Break Module (BREAK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Chapter 17 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Chapter 18 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Appendix A MC68HLC908JL3E/JK3E/JK1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Appendix B MC68H(R)C08JL3E/JK3E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Appendix C MC68HC908KL3E/KK3E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

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List of Chapters

MC68HC908JL3E Family Data Sheet, Rev. 3

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Table of Contents

Chapter 1

General Description

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 2

Memory

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.5 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.7 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.8 FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.9 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.10 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.11 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.12 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Chapter 3

Configuration Registers (CONFIG)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3 Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4 Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Chapter 4

Central Processor Unit (CPU)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Table of Contents

4.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Chapter 5

System Integration Module (SIM)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.2.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.2.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.2.5 LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.7.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.7.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.7.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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Chapter 6

Oscillator (OSC)

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.2 X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3 RC Oscillator (MC68HRC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.4.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.4.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.4.4 X-tal Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.4.5 RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.4.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.4.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Chapter 7

Monitor ROM (MON)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.3.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7.3.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.3.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.3.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.3.5 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.3.6 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Chapter 8

Timer Interface Module (TIM)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.4.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

8.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.9.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8.9.2 TIM Counter Registers (TCNTH:TCNTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.9.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1). . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.9.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Chapter 9

Analog-to-Digital Converter (ADC)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

9.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

9.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

9.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

9.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

9.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

9.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

9.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

9.6.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

9.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

9.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

9.7.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

9.7.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Chapter 10

Input/Output (I/O) Ports

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

10.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.2.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.2.2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.2.3 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

10.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

10.3.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

10.3.2 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

10.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

10.4.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

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10.4.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

10.4.3 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Chapter 11

External Interrupt (IRQ)

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.3.1 IRQ1

11.4 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

11.5 IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Chapter 12

Keyboard Interrupt Module (KBI)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.5 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.5.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

12.5.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.7 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Chapter 13

Computer Operating Properly (COP)

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

13.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

13.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.3.1 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.3.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.3.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.3.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.3.5 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

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Chapter 14

Low Voltage Inhibit (LVI)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

14.4 LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Chapter 15

Break Module (BREAK)

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

15.3.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

15.3.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

15.3.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

15.3.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

15.4 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

15.4.1 Break Status and Control Register (BRKSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

15.4.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

15.4.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

15.4.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Chapter 16

Electrical Specifications

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

16.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

16.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

16.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

16.5 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

16.6 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

16.7 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

16.8 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

16.9 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

16.10 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

16.11 Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

16.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

16.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

MC68HC908JL3E Family Data Sheet, Rev. 3

12 Freescale Semiconductor

Chapter 17

Mechanical Specifications

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

17.2 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

17.3 20-Pin SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

17.4 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

17.5 28-Pin SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

17.6 48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Chapter 18

Ordering Information

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

18.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Appendix A

MC68HLC908JL3E/JK3E/JK1E

A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

A.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

A.3 Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

A.4 Oscillator Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

A.5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

A.5.1 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

A.5.2 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

A.5.3 Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

A.5.4 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

A.5.5 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

A.5.6 Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

A.6 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Appendix B

MC68H(R)C08JL3E/JK3E

B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

B.2 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

B.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

B.4 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

B.5 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

B.6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

B.6.1 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

B.6.2 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

B.6.3 Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

B.7 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 13

Table of Contents

Appendix C

MC68HC908KL3E/KK3E

C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

C.2 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

C.3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

C.4 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

C.5 Reserved Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

C.6 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

MC68HC908JL3E Family Data Sheet, Rev. 3

14 Freescale Semiconductor

Chapter 1 General Description

1.1 Introduction

The MC68H(R)C908JL3E is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.

A list of MC68H(R)C908JL3E device variations is shown in Table 1-1.

Table 1-1. Summary of Device Variations

Device

Type

FLASH 3V, 5V Yes Yes

Low Voltage

FLASH

(2)

ROM

FLASH,

ADC-less

Operating

Voltage

2.2 to 5.5V No Yes XTAL

(1)

3V, 5V Yes Yes

(3)

3V, 5 V Yes No XTAL 4,096 bytes FLASH

LVI ADC

Oscillator

Option

XTAL

Memory

4,096 bytes FLASH

1,536 bytes FLASH 20 MC68HC908JK1E

4,096 bytes FLASH

1,536 bytes FLASH 20 MC68HRC908JK3E

4,096 bytes FLASH

1,536 bytes FLASH 20 MC68HLC908JK1E

4,096 bytes ROM

Count

28 MC68HC908JL3E

20 MC68HC908JK3E

28 MC68HRC908JL3E

20 MC68HRC908JK3E

28 MC68HLC908JL3E

20 MC68HLC908JK3E

28 MC68HC08JL3E

20 MC68HC08JK3E

28 MC68HRC08JL3E

20 MC68HRC08JK3E

28 MC68HC908KL3E

20 MC68HC908KK3E

Device

1. Low-voltage FLASH devices are documented in Appendix A MC68HLC908JL3E/JK3E/JK1E.

2. ROM devices are documented in Appendix B MC68H(R)C08JL3E/JK3E.

3. FLASH, ADC-less devices are documented in Appendix C MC68HC908KL3E/KK3E.

All references to the MC68H(R)C908JL3E in this data book apply equally to the MC68H(R)C908JK3E and MC68H(R)C908JK1E, unless otherwise stated.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 15

General Description

1.2 Features

Features of the MC68H(R)C908JL3E include the following:

• EMC enhanced version of MC68H(R)C908JL3/JK3/JK1

• High-performance M68HC08 architecture

• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families

• Low-power design; fully static with stop and wait modes

• Maximum internal bus frequency: – 8-MHz at 5V operating voltage – 4-MHz at 3V operating voltage

• Oscillator options: – Crystal oscillator for MC68HC908JL3E/JK3E/JK1E – RC oscillator for MC68HRC908JL3E/JK3E/JK1E

• User program FLASH memory with security – 4,096 bytes for MC68H(R)C908JL3E/JK3E – 1,536 bytes for MC68H(R)C908JK1E

• 128 bytes of on-chip RAM

• 2-channel, 16-bit timer interface module (TIM)

• 12-channel, 8-bit analog-to-digital converter (ADC)

• 23 general purpose I/O ports for MC68H(R)C908JL3E: – 7 keyboard interrupt with internal pull-up

(6 keyboard interrupt for MC68HC908JL3E)

– 10 LED drivers (sink) –2 × 25mA open-drain I/O with pull-up

• 15 general purpose I/O ports for MC68H(R)C908JK3E/JK1E: – 1 keyboard interrupt with internal pull-up

(MC68HRC908JK3E/JK1E only)

– 4 LED drivers (sink) –2 × 25mA open-drain I/O with pull-up – 10-channel ADC

• System protection features: – Optional computer operating properly (COP) reset – Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation – Illegal opcode detection with reset – Illegal address detection with reset

• Master reset pin with internal pull-up and power-on reset

•IRQ1

with schmitt-trigger input and programmable pull-up

• 28-pin PDIP, 28-pin SOIC, and 48-pin LQFP packages for MC68H(R)C908JL3E

• 20-pin PDIP and 20-pin SOIC packages for MC68H(R)C908JK3E/JK1E

(1)

feature

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

MC68HC908JL3E Family Data Sheet, Rev. 3

16 Freescale Semiconductor

1.3 MCU Block Diagram

Figure 1-1 shows the structure of the MC68H(R)C908JL3E.

INTERNAL BUS

M68HC08 CPU

MCU Block Diagram

CPU

REGISTERS

ARITHMETIC/LOGIC

UNIT (ALU)

CONTROL AND STATUS REGISTERS — 64 BYTES

USER FLASH: MC68H(R)C908JK3E/JL3E — 4,096 BYTES MC68H(R)C908JK1E — 1,536 BYTES

USER RAM — 128 BYTES

MONITOR ROM — 960 BYTES

USER FLASH VECTOR SPACE — 48 BYTES

MC68HC908JL3E/JK3E/JK1E

X-TAL OSCILLATOR

MC68HRC908JL3E/JK3E/JK1E

OSC1

OSC2

RC OSCILLATOR

* RST

* IRQ1

SYSTEM INTEGRATION

MODULE

EXTERNAL INTERRUPT

MODULE

KEYBOARD INTERRUPT

MODULE

8-BIT ANALOG-TO-DIGITAL

CONVERTER MODULE

2-CHANNEL TIMER INTERFACE

MODULE

BREAK

MODULE

COMPUTER OPERATING

PROPERLY MODULE

POWER-ON RESET

MODULE

LOW-VOLTAGE INHIBIT

MODULE

DDRA

DDRB

DDRD

PORTA

PORTB

PORTD

PTA6/KBI6**

PTA5/KBI5**

PTA4/KBI4**

PTA3/KBI3**

PTA2/KBI2**

PTA1/KBI1**

PTA0/KBI0**

PTB7/ADC7

PTB6/ADC6

PTB5/ADC5

PTB4/ADC4

PTB3/ADC3

PTB2/ADC2

PTB1/ADC1

PTB0/ADC0

†‡

PTD7**

†‡

PTD6**

PTD5/TCH1

PTD4/TCH0

PTD3/ADC8

PTD2/ADC9

PTD1/ADC10

PTD0/ADC11

‡

* Pin contains integrated pull-up device.

VDD

POWER

VSS

** Pin contains programmable pull-up device.

† 25mA open-drain if output pin. ‡ LED direct sink pin. # Pins available on MC68H(R)C908JL3E only.

ADC REFERENCE

¥ Shared pin:

MC68HC908JL3E/JK3E/JK1E — OSC2 MC68HRC908JL3E/JK3E/JK1E — RCCLK/PTA6/KBI6

Figure 1-1. MCU Block Diagram

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 17

General Description

1.4 Pin Assignments

IRQ1

PTA0/KBI0

VSS

OSC1

OSC2/RCCLK/PTA6/KBI

PTA1/KBI1

VDD

PTA2/KBI2

PTA3/KBI3

PTB7/ADC7

PTB6/ADC6

PTB5/ADC5

PTD7

PTD6

MC68H(R)C908JL3E

Figure 1-2. 28-Pin PDIP/SOIC Pin Assignment

RST

PTA5/KBI5

PTD4/TCH0

PTD5/TCH1

PTD2/ADC9

PTA4/KBI4

PTD3/ADC8

PTB0/ADC0

PTB1/ADC1

PTD1/ADC10

PTB2/ADC2

PTB3/ADC3

PTD0/ADC11

PTB4/ADC4

IRQ1

VSS

OSC1

OSC2/RCCLK/PTA6/KBI

VDD

PTB7/ADC7

PTB6/ADC6

PTB5/ADC5

PTD7

PTD6

MC68H(R)C908JK3E/JK1E

Figure 1-3. 20-Pin PDIP/SOIC Pin Assignment

RST

PTD4/TCH0

PTD5/TCH1

PTD2/ADC9

PTD3/ADC8

PTB0/ADC0

PTB1/ADC1

PTB2/ADC2

PTB3/ADC3

PTB4/ADC4

Pins not available on 20-pin packages

PTA0/KBI0 PTD0/ADC11

PTA1/KBI1 PTD1/ADC10

PTA2/KBI2

PTA3/KBI3

PTA4/KBI4

PTA5/KBI5

Internal pads are unconnected.

MC68HC908JL3E Family Data Sheet, Rev. 3

18 Freescale Semiconductor

Pin Assignments

RST

IRQ1

PTA0/KBI0

VSS

PTA5/KBI5

PTD5/TCH1

PTD4/TCH0

OSC1

OSC2/RCCLK/PTA6/KBI6

PTA1/KBI1

VDD

PTA2/KBI2

PTA3KBI3

PTB7/ADC7

NC: No connection

MC68H(R)C908JL3E

PTB6/ADC6

PTD7

PTD6

PTB5/ADC5

PTB4/ADC4

PTB3/ADC3

PTD0/ADC11

PTB2/ADC2

PTD2/ADC9

PTA4/KBI4

PTD3/ADC8

PTB0/ADC0

PTB1/ADC1

PTD1/ADC10

Figure 1-4. 48-Pin LQFP Pin Assignment

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 19

General Description

1.5 Pin Functions

Description of the pin functions are provided in Table 1-2.

Table 1-2. Pin Functions

PIN NAME PIN DESCRIPTION IN/OUT VOLTAGE LEVEL

VDD Power supply. In 5V or 3V

VSS Power supply ground Out 0V

RST

IRQ1

OSC1 X-tal or RC oscillator input. In Analog

OSC2

PTA[0:6]

PTB[0:7]

RESET input, active low. With Internal pull-up and schmitt trigger input.

External IRQ pin. With software programmable internal pull-up and schmitt trigger input. This pin is also used for mode entry selection.

MC68HC908JL3E/JK3E/JK1E: X-tal oscillator output, this is the inverting OSC1 signal.

MC68HRC908JL3E/JK3E/JK1E: Default is RC oscillator clock output, RCCLK. Shared with PTA6/KBI6, with programmable pull-up.

7-bit general purpose I/O port. In/Out VDD

Shared with 7 keyboard interrupts KBI[0:6]. In VDD

Each pin has programmable internal pull-up device. In VDD

PTA[0:5] have LED direct sink capability In VSS

8-bit general purpose I/O port. In/Out VDD

Shared with 8 ADC inputs, ADC[0:7]. In Analog

8-bit general purpose I/O port. In/Out VDD

Input VDD

Input

Out Analog

In/Out VDD

VDD to VDD+V

PTD[3:0] shared with 4 ADC inputs, ADC[8:11]. Input Analog

PTD[0:7]

PTD[4:5] shared with TIM channels, TCH0 and TCH1. In/Out VDD

PTD[2:3], PTD[6:7] have LED direct sink capability In VSS

PTD[6:7] can be configured as 25mA open-drain output with pull-up.

In/Out VDD

NOTE

On the MC68H(R)C908JK3E/JK1E, the following pins are not available: PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, and PTD1.

MC68HC908JL3E Family Data Sheet, Rev. 3

20 Freescale Semiconductor

Chapter 2 Memory

2.1 Introduction

The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:

• 4,096 bytes of user FLASH — MC68H(R)C908JL3E/JK3E 1,536 bytes of user FLASH — MC68H(R)C908JK1E

• 128 bytes of RAM

• 48 bytes of user-defined vectors

• 960 bytes of Monitor ROM

2.2 I/O Section

Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses:

• $FE00; Break Status Register, BSR

• $FE01; Reset Status Register, RSR

•$FE02; Reserved

• $FE03; Break Flag Control Register, BFCR

• $FE04; Interrupt Status Register 1, INT1

• $FE05; Interrupt Status Register 2, INT2

• $FE06; Interrupt Status Register 3, INT3

•$FE07; Reserved

• $FE08; FLASH Control Register, FLCR

• $FE09; FLASH Block Protect Register, FLBPR

•$FE0A; Reserved

•$FE0B; Reserved

• $FE0C; Break Address Register High, BRKH

• $FE0D; Break Address Register Low, BRKL

• $FE0E; Break Status and Control Register, BRKSCR

•$FE0F; Reserved

• $FFFF; COP Control Register, COPCTL

2.3 Monitor ROM

The 960 bytes at addresses $FC00–$FDFF and $FE10–$FFCF are reserved ROM addresses that contain the instructions for the monitor functions. (See Chapter 7 Monitor ROM (MON).)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 21

Memory

$0000

↓

$003F

$0040

↓

$007F

$0080

↓

$00FF

$0100

↓

$EBFF

$EC00

↓

$FBFF

$FC00

↓

$FDFF

$FE00 BREAK STATUS REGISTER (BSR)

$FE01 RESET STATUS REGISTER (RSR)

$FE02 RESERVED (UBAR)

$FE03 BREAK FLAG CONTROL REGISTER (BFCR)

$FE04 INTERRUPT STATUS REGISTER 1 (INT1)

I/O REGISTERS

64 BYTES

RESERVED

64 BYTES

RAM

128 BYTES

UNIMPLEMENTED

60,160 BYTES

FLASH MEMORY

MC68H(R)C908JL3E/JK3E

4,096 BYTES

MONITOR ROM

512 BYTES

UNIMPLEMENTED

62,720 BYTES

FLASH MEMORY

MC68H(R)C908JK1E

1,536 BYTES

$0100

↓

$F5FF

$F600

↓

$FBFF

$FE05 INTERRUPT STATUS REGISTER 2 (INT2)

$FE06 INTERRUPT STATUS REGISTER 3 (INT3)

$FE07 RESERVED

$FE08 FLASH CONTROL REGISTER (FLCR)

$FE09 FLASH BLOCK PROTECT REGISTER (FLBPR)

$FE0A RESERVED

$FE0B RESERVED

$FE0C BREAK ADDRESS HIGH REGISTER (BRKH)

$FE0D BREAK ADDRESS LOW REGISTER (BRKL)

$FE0E BREAK STATUS AND CONTROL REGISTER (BRKSCR)

$FE0F RESERVED

$FE10

↓

$FFCF

$FFD0

↓

$FFFF

MONITOR ROM

448 BYTES

USER VECTORS

48 BYTES

Figure 2-1. Memory Map

MC68HC908JL3E Family Data Sheet, Rev. 3

22 Freescale Semiconductor

Monitor ROM

Addr.Register Name Bit 7654321Bit 0

$0000 Port A Data Register (PTA)

$0001 Port B Data Register (PTB)

$0002 Unimplemented

Write:

Reset: Unaffected by reset

Read:

Write:

Reset: Unaffected by reset

Read:

Write:

PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0

$0003 Port D Data Register (PTD)

$0004

$0005

$0006 Unimplemented

$0007

$0008

$0009

$000A

$000B

$000C

Data Direction Register A

Data Direction Register B

Data Direction Register D

↓

Unimplemented

Port D Control Register

↓

Unimplemented

(DDRA)

(DDRB)

(DDRD)

(PDCR)

Port A Input Pull-up

$000D

Enable Register

(PTAPUE)

$000E

↓

$0019

Unimplemented

Read:

Write:

Reset: Unaffected by reset

Write:

Reset:00000000

Read:

Write:

Reset:00000000

Read:

Write:

Read:

Write:

Reset:00000000

Read:

Write:

Write:

Reset:

Read:

Write:

Read:

Write:

Reset:

Read:

Write:

PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

SLOWD7 SLOWD6 PTDPU7 PTDPU6

00000000

PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

00000000

Read: 0000KEYF 0

Write:

Reset:

Write:

Reset:

00000000

KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0

00000000

= Unimplemented R = Reserved

ACKK

IMASKK MODEK

$001A

$001B

Keyboard Status and

Control Register

(KBSCR)

Keyboard Interrupt

Enable Register

(KBIER)

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 4)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 23

Memory

Addr.Register Name Bit 7654321Bit 0

$001C

Unimplemented

Read:

Write:

IRQ Status and Control

$001D

$001E

$001F

† One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.

Configuration Register 2

Configuration Register 1

(INTSCR)

(CONFIG2)

(CONFIG1)

TIM Status and Control

$0020

TIM Counter Register

$0021

(TCNTH)

TIM Counter Register

$0022

(TCNTL)

TIM Counter Modulo

$0023

(TMODH)

TIM Counter Modulo

$0024

(TMODL)

TIM Channel 0 Status and

$0025

Control Register

(TSC0)

TIM Channel 0

$0026

(TCH0H)

TIM Channel 0

$0027

(TCH0L)

TIM Channel 1 Status and

$0028

Control Register

(TSC1)

TIM Channel 1

$0029

(TCH1H)

TIM Channel 1

$002A

(TCH1L)

Read:0000IRQF10

Write:

Reset:00000000

Read:

IRQPUDRRLVIT1LVIT0RRR

Write:

†

Reset:0000*0*000

Read:

Write:

†

Reset:00000000

Read: TOF

Write: 0 TRST

(TSC)

Reset:

COPRS R R LVID R SSREC STOP COPD

TOIE TSTOP

00100000

Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Write:

High

Reset:

00000000

Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Write:

Low

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read: CH0F

Write: 0

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

Read: CH1F

Write: 0

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

00000000

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

11111111

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

00000000

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Indeterminate after reset

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Indeterminate after reset

CH1IE

00000000

MS1A ELS1B ELS1A TOV1 CH1MAX

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Indeterminate after reset

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Indeterminate after reset

= Unimplemented R = Reserved

ACK1

IMASK1 MODE1

PS2 PS1 PS0

Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 4)

MC68HC908JL3E Family Data Sheet, Rev. 3

24 Freescale Semiconductor

Monitor ROM

Addr.Register Name Bit 7654321Bit 0

$002B

$003B

↓

Unimplemented

Read:

Write:

ADC Status and Control

$003C

$003D

$003E

$003F

$FE00 Break Status Register (BSR)

$FE01 Reset Status Register (RSR)

$FE02 Reserved

$FE03

$FE04

$FE05

$FE06

$FE07 Reserved

ADC Data Register

ADC Input Clock Register

Note: Writing a logic 0 clears SBSW.

Break Flag Control

Interrupt Status Register 1

Interrupt Status Register 2

Interrupt Status Register 3

(ADSCR)

(ADR)

(ADICLK)

Unimplemented

(BFCR)

(INT1)

(INT2)

(INT3)

Read: COCO

Write:

Reset:00011111

Read:AD7AD6AD5AD4AD3AD2AD1AD0

Write:

Reset: Indeterminate after reset

Read:

Write:

Reset:00000000

Read:

Write:

Read:

Write: See note

Reset: 0

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

POR:10000000

Read:

Write:

Read:

Write:

Reset: 0

Read: 0 IF5 IF4 IF3 0 IF1 0 0

Write:RRRRRRRR

Reset:00000000

Read:IF140000000

Write:RRRRRRRR

Reset:00000000

Read:0000000IF15

Write:RRRRRRRR

Reset:00000000

Read:

Write:

ADIV2 ADIV1 ADIV0

RRRRRR

RRRRRRRR

BCFERRRRRRR

RRRRRRRR

AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

00000

SBSW

$FE08

$FE09

FLASH Control Register

(FLCR)

FLASH Block Protect

Write:

Reset:00000000

Read:

Write:

Reset:00000000

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

= Unimplemented R = Reserved

HVEN MASS ERASE PGM

Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 4)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 25

Memory

Addr.Register Name Bit 7654321Bit 0

$FE0A

$FE0B

$FE0C

$FE0D

$FE0E

↓

Break Address High

Break Address low

Break Status and Control

Reserved

(BRKH)

(BRKL)

(BRKSCR)

Read:

Write:

Read:

Write:

Reset:00000000

Read:

Write:

Reset:00000000

Read:

Write:

Reset:00000000

RRRRRRRR

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

BRKE BRKA

000000

$FFFF

COP Control Register

(COPCTL)

Read: Low byte of reset vector

Write: Writing clears COP counter (any value)

Reset: Unaffected by reset

= Unimplemented R = Reserved

Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 4)

Table 2-1. Vector Addresses

Vector Priority INT Flag Address Vector

Lowest

—

IF15

IF14

IF13

↓

IF6

IF5

IF4

IF3

IF2 — Not Used

IF1

—

Highest

$FFD0

↓

$FFDD

$FFDE ADC Conversion Complete Vector (High)

$FFDF ADC Conversion Complete Vector (Low)

$FFE0 Keyboard Vector (High)

$FFE1 Keyboard Vector (Low)

— Not Used

$FFF2 TIM Overflow Vector (High)

$FFF3 TIM Overflow Vector (Low)

$FFF4 TIM Channel 1 Vector (High)

$FFF5 TIM Channel 1 Vector (Low)

$FFF6 TIM Channel 0 Vector (High)

$FFF7 TIM Channel 0 Vector (Low)

$FFFA IRQ1

$FFFB IRQ1

$FFFC SWI Vector (High)

$FFFD SWI Vector (Low)

$FFFE Reset Vector (High)

$FFFF Reset Vector (Low)

Not Used

Vector (High)

Vector (Low)

MC68HC908JL3E Family Data Sheet, Rev. 3

26 Freescale Semiconductor

Random-Access Memory (RAM)

2.4 Random-Access Memory (RAM)

Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.

NOTE

For correct operation, the stack pointer must point only to RAM locations.

Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables.

Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.

NOTE

For M6805 compatibility, the H register is not stacked.

During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.

NOTE

Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.

2.5 FLASH Memory

This sub-section describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.

Device

MC68H(R)C908JL3E 4,096 $EC00—$FBFF

MC68H(R)C908JK3E 4,096 $EC00—$FBFF

MC68H(R)C908JK1E 1,536 $F600—$FBFF

Addr.Register Name Bit 7654321Bit 0

Write:

Reset:00000000

Read:

Write:

Reset:00000000

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

$FE08

$FE09

FLASH Control Register

(FLCR)

FLASH Block Protect

(FLBPR)

FLASH Memory Size

(Bytes)

= Unimplemented

Memory Address Range

HVEN MASS ERASE PGM

Figure 2-3. FLASH I/O Register Summary

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 27

Memory

2.6 Functional Description

The FLASH memory consists of an array of 4,096 or 1,536 bytes with an additional 48 bytes for user vectors. The minimum size of FLASH memory that can be erased is 64 bytes (a page); and the maximum size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the Flash Control Register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are:

• $EC00–$FBFF; user memory; 4,096 bytes; MC68H(R)C908JL3E/JK3E $F600–$FBFF; user memory; 1,536 bytes;

MC68H(R)C908JK1E

• $FFD0–$FFFF; user interrupt vectors; 48 bytes

NOTE

An erased bit reads as logic 1 and a programmed bit reads as logic 0. A security feature prevents viewing of the FLASH contents.

(1)

2.7 FLASH Control Register

The FLASH Control Register controls FLASH program and erase operations.

Address: $FE08

Bit 7654321Bit 0

Write:

Reset:00000000

HVEN MASS ERASE PGM

Figure 2-4. FLASH Control Register (FLCR)

HVEN — High Voltage Enable Bit

This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM= 1 or ERASE=1 and the proper sequence for program or erase is followed.

1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off

MASS — Mass Erase Control Bit

This read/write bit configures the memory for mass erase operation or page erase operation when the ERASE bit is set.

1 = Mass erase operation selected 0 = Page erase operation selected

ERASE — Erase Control Bit

This read/write bit configures the memory for erase operation. This bit and the PGM bit should not be set to 1 at the same time.

1 = Erase operation selected 0 = Erase operation not selected

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

MC68HC908JL3E Family Data Sheet, Rev. 3

28 Freescale Semiconductor

FLASH Page Erase Operation

PGM — Program Control Bit

This read/write bit configures the memory for program operation. This bit and the ERASE bit should not be set to 1 at the same time.

1 = Program operation selected 0 = Program operation not selected

2.8 FLASH Page Erase Operation

Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 48-byte user interrupt vectors area also forms a page. Any page within the 4K bytes user memory area ($EC00–$FBFF) can be erased alone.

The 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page.

1. Set the ERASE bit and clear the MASS bit in the FLASH Control Register.

2. Write any data to any FLASH address within the page address range desired.

3. Wait for a time, t

4. Set the HVEN bit.

5. Wait for a time t

6. Clear the ERASE bit.

7. Wait for a time, t

8. Clear the HVEN bit.

9. After time, t

rcv

Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.

(10µs).

nvs

(1ms).

Erase

(5µs).

nvh

(1µs), the memory can be accessed in read mode again.

NOTE

2.9 FLASH Mass Erase Operation

Use the following procedure to erase the entire FLASH memory:

1. Set both the ERASE bit and the MASS bit in the FLASH Control Register.

2. Write any data to any FLASH location within the FLASH memory address range.

3. Wait for a time, t

4. Set the HVEN bit.

5. Wait for a time t

6. Clear the ERASE bit.

7. Wait for a time, t

8. Clear the HVEN bit.

9. After time, t

rcv

Freescale Semiconductor 29

(10µs).

nvs

nvh1

(4ms).

(100µs).

MErase

(1µs), the memory can be accessed in read mode again.

NOTE

MC68HC908JL3E Family Data Sheet, Rev. 3

Memory

2.10 FLASH Program Operation

Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program a row of FLASH memory: (Figure 2-5 shows a flowchart of the programming algorithm.)

1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming.

2. Write any data to any FLASH location within the address range of the row to be programmed.

3. Wait for a time, t

4. Set the HVEN bit.

5. Wait for a time, t

6. Write data to the byte being programmed.

(10µs).

nvs

(5µs).

pgs

7. Wait for time, t

PROG

(30µs).

8. Repeat step 6 and 7 until all the bytes within the row are programmed.

9. Clear the PGM bit.

10. Wait for time, t

nvh

(5µs).

11. Clear the HVEN bit.

12. After time, t

(1µs), the memory can be accessed in read mode again.

rcv

This program sequence is repeated throughout the memory until all data is programmed.

NOTE

The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 6 to step 10), must not exceed the maximum programming time,

max.

PROG

NOTE

Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.

MC68HC908JL3E Family Data Sheet, Rev. 3

30 Freescale Semiconductor

FLASH Program Operation

Algorithm for programming a row (32 bytes) of FLASH memory

Write any data to any FLASH address

Set PGM bit

within the row address range desired

Wait for a time, t

Set HVEN bit

Wait for a time, t

Write data to the FLASH address

to be programmed

Wait for a time, t

nvs

pgs

PROG

Completed

programming

this row?

NOTE:

The time between each FLASH address change (step 6 to step 6), or

the time between the last FLASH address programmed

to clearing PGM bit (step 6 to step 9)

must not exceed the maximum programming

PROG

max.

time, t

This row program algorithm assumes the row/s to be programmed are initially erased.

Figure 2-5. FLASH Programming Flowchart

Clear PGM bit

Wait for a time, t

Clear HVEN bit

Wait for a time, t

nvh

rcv

End of Programming

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 31

Memory

2.11 FLASH Protection

Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH Block Protect Register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations.

2.12 FLASH Block Protect Register

The FLASH Block Protect Register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the FLASH memory.

Address: $FE09

Bit 7654321Bit 0

Read:

Write:

Reset:00000000

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Figure 2-6. FLASH Block Protect Register (FLBPR)

BPR[7:0] — FLASH Block Protect Register Bit 7 to Bit 0

BPR[7:1] represent bits [12:6] of a 16-bit memory address. Bits [15:13] are logic 1’s and bits [5:0] are logic 0’s.

16-bit memory address

Start address of FLASH block protect 1 1 1 000000

BPR[7:1]

BPR0 is used only for BPR[7:0] = $FF, for no block protection. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page boundaries — 64 bytes) within the FLASH memory.

Examples of protect start address:

BPR[7:0] Start of Address of Protect Range

$00–$60 The entire FLASH memory is protected.

$62 or $63

(0110 001x)

$EC40 (1110 1100 0100 0000)

$64 or $65

(0110 010x)

$68 or $69

(0110 100x)

MC68HC908JL3E Family Data Sheet, Rev. 3

32 Freescale Semiconductor

$EC80 (1110 1100 1000 0000)

$ED00 (1110 1101 0000 0000)

BPR[7:0] Start of Address of Protect Range

and so on...

FLASH Block Protect Register

$DE or $DF (1101 111x)

$FE

(1111 1110)

$FF The entire FLASH memory is not protected.

Note: The end address of the protected range is always $FFFF.

$FBC0 (1111 1011 1100 0000)

$FFC0 (1111 1111 1100 0000)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 33

Memory

MC68HC908JL3E Family Data Sheet, Rev. 3

34 Freescale Semiconductor

Chapter 3 Configuration Registers (CONFIG)

3.1 Introduction

This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enables or disables the following options:

• Stop mode recovery time (32 × 2OSCOUT cycles or 4096 × 2OSCOUT cycles)

•STOP instruction

• Computer operating properly module (COP)

• COP reset period (COPRS), (2

18–24

) × 2OSCOUT

• Enable LVI circuit

• Select LVI trip voltage

3.2 Functional Description

The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU it is recommended that this register be written immediately after reset. The configuration register is located at $001E and $001F, and may be read at anytim

13–24

) × 2OSCOUT or

NOTE

The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 3-1 and Figure 3-2.

3.3 Configuration Register 1 (CONFIG1)

Address: $001F

Bit 7654321Bit 0

Read:

Write:

Reset:00000000

COPRS — COP reset period selection bit

1 = COP reset cycle is (2 0 = COP reset cycle is (2

COPRS R R LVID R SSREC STOP COPD

R=Reserved

Figure 3-1. Configuration Register 1 (CONFIG1)

– 24) × 2OSCOUT

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 35

Configuration Registers (CONFIG)

LVID — Low Voltage Inhibit Disable Bit

1 = Low Voltage Inhibit disabled 0 = Low Voltage Inhibit enabled

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32 × 2OSCOUT cycles instead of a 4096 × 2OSCOUT cycle delay.

1 = Stop mode recovery after 32 × 2OSCOUT cycles 0 = Stop mode recovery after 4096 × 2OSCOUT cycles

NOTE

Exiting stop mode by pulling reset will result in the long stop recovery.

If using an external crystal, do not set the SSREC bit.

STOP — STOP Instruction Enable

STOP enables the STOP instruction.

1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD disables the COP module. (See Chapter 13 Computer Operating Properly (COP).)

1 = COP module disabled 0 = COP module enabled

3.4 Configuration Register 2 (CONFIG2)

Address: $001E

Bit 7654321Bit 0

Read:

IRQPUDRRLVIT1LVIT0RRR

Write:

Reset:000

POR:00000000

R=Reserved

Not

affected

Figure 3-2. Configuration Register 2 (CONFIG2)

IRQPUD — IRQ1 Pin Pull-up control bit

1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ1

pin and V

LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits

Detail description of the LVI control signals is given in Chapter 14 Low Voltage Inhibit (LVI)

Not

affected

000

MC68HC908JL3E Family Data Sheet, Rev. 3

36 Freescale Semiconductor

Chapter 4 Central Processor Unit (CPU)

4.1 Introduction

The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.

4.2 Features

• Object code fully upward-compatible with M68HC05 Family

• 16-bit stack pointer with stack manipulation instructions

• 16-bit index register with x-register manipulation instructions

• 8-MHz CPU internal bus frequency

• 64-Kbyte program/data memory space

• 16 addressing modes

• Memory-to-memory data moves without using accumulator

• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions

• Enhanced binary-coded decimal (BCD) data handling

• Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes

• Low-power stop and wait modes

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 37

Central Processor Unit (CPU)

4.3 CPU Registers

Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map.

H X

V11H I NZC

ACCUMULATOR (A)

INDEX REGISTER (H:X)

STACK POINTER (SP)

PROGRAM COUNTER (PC)

CONDITION CODE REGISTER (CCR)

CARRY/BORROW FLAG

ZERO FLAG

NEGATIVE FLAG

INTERRUPT MASK

HALF-CARRY FLAG

TWO’S COMPLEMENT OVERFLOW FLAG

Figure 4-1. CPU Registers

4.3.1 Accumulator

The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.

Bit 7654321Bit 0

Read:

Write:

Reset: Unaffected by reset

Figure 4-2. Accumulator (A)

4.3.2 Index Register

The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.

In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand.

The index register can serve also as a temporary data storage location.

MC68HC908JL3E Family Data Sheet, Rev. 3

38 Freescale Semiconductor

CPU Registers

Bit

1413121110987654321Bit 0

Read:

Write:

Reset:00000000XXXXXXXX

X = Indeterminate

Figure 4-3. Index Register (H:X)

4.3.3 Stack Pointer

The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.

In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.

Bit

1413121110987654321Bit 0

Read:

Write:

Reset:0000000011111111

Figure 4-4. Stack Pointer (SP)

NOTE

The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.

4.3.4 Program Counter

The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.

Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.

During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 39

Central Processor Unit (CPU)

Bit

1413121110987654321Bit 0

Read:

Write:

Reset: Loaded with Vector from $FFFE and $FFFF

Figure 4-5. Program Counter (PC)

4.3.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register.

Bit 7654321Bit 0

Read:

Write:

Reset:X11X1XXX

V11H I NZC

X = Indeterminate

Figure 4-6. Condition Code Register (CCR)

V — Overflow Flag

The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.

1 = Overflow 0 = No overflow

H — Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor.

1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4

I — Interrupt Mask

When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.

1 = Interrupts disabled 0 = Interrupts enabled

NOTE

To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions.

MC68HC908JL3E Family Data Sheet, Rev. 3

40 Freescale Semiconductor

Arithmetic/Logic Unit (ALU)

After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI).

N — Negative flag

The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result.

1 = Negative result 0 = Non-negative result

Z — Zero flag

The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00.

1 = Zero result 0 = Non-zero result

C — Carry/Borrow Flag

The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.

1 = Carry out of bit 7 0 = No carry out of bit 7

4.4 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the instruction set.

Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.

4.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

4.5.1 Wait Mode

The WAIT instruction:

• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

4.5.2 Stop Mode

The STOP instruction:

• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 41

Central Processor Unit (CPU)

4.6 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break interrupt by:

• Loading the instruction register with the SWI instruction

• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode

The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.

A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.

4.7 Instruction Set Summary

Table 4-1 provides a summary of the M68HC08 instruction set.

4.8 Opcode Map

The opcode map is provided in Table 4-2.

Table 4-1. Instruction Set Summary

Source

Form

ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP

ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP

AIS #

opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) ––––––IMM A7 ii 2

AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) ––––––IMM AF ii 2

Add with Carry A ← (A) + (M) + (C) RR– RRR

Add without Carry A ← (A) + (M) RR– RRR

Operation Description

CCR

VH I NZC

IMM DIR EXT IX2 IX1 IX SP1 SP2

Address

Mode

9EDB

Opcode

B9 C9 D9 E9 F9

9EE9 9ED9

AB BB CB DB EB FB

9EEB

ii dd hh ll ee ff ff

ff ee ff

ii dd hh ll ee ff ff

ff ee ff

Operand

2 3 4 4 3 2 4 5

Effect on

Cycles

MC68HC908JL3E Family Data Sheet, Rev. 3

42 Freescale Semiconductor

Table 4-1. Instruction Set Summary

Opcode Map

Source

Form

AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP

ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP

ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP

BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3

Logical AND A ← (A) & (M) 0 – – RR –

Arithmetic Shift Left (Same as LSL)

Arithmetic Shift Right R ––RRR

Operation Description

CCR

VH I NZC

R ––RRR

IMM DIR EXT IX2 IX1 IX SP1 SP2

DIR INH INH IX1 IX SP1

Address

Mode

9EE4 9ED4

A4 B4 C4 D4 E4 F4

38 48 58 68 78

9E68

37 47 57 67 77

9E67

Opcode

Operand

ii dd hh ll ee ff ff

ff ee ff

2 3 4 4 3 2 4 5

4 1 1 4 3 5

Effect on

Cycles

DIR (b0) DIR (b1) DIR (b2)

BCLR n, opr Clear Bit n in M Mn ← 0 ––––––

BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3

BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3

BGE opr

BGT opr

BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3

BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3

BHI rel Branch if Higher PC

BHS rel

BIH rel Branch if IRQ

BIL rel Branch if IRQ

Branch if Greater Than or Equal To (Signed Operands)

Branch if Greater Than (Signed Operands)

Branch if Higher or Same (Same as BCC)

Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3

Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3

PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 ––––––REL 90 rr 3

PC ← (PC) + 2 +rel ? (Z) | (N ⊕ V)=0––––––REL 92 rr 3

← (PC) + 2 + rel ? (C) | (Z) = 0 ––––––REL 22 rr 3

PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3

DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

11 13 15 17 19 1B 1D 1F

dd dd dd dd dd dd dd

4 4 4 4 4 4 4

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 43

Central Processor Unit (CPU)

Table 4-1. Instruction Set Summary

Source

Form

BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP

BLE opr

BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3

BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 ––––––REL 23 rr 3

BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 1 ––––––REL 91 rr 3

BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3

BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3

BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 +

BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3

Bit Test (A) & (M) 0 – – RR–

Branch if Less Than or Equal To (Signed Operands)

Operation Description

PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V)=1––––––REL 93 rr 3

rel ? (I) = 1 ––––––REL 2D rr 3

CCR

VH I NZC

IMM DIR EXT IX2 IX1 IX SP1 SP2

Address

Mode

9EE5 9ED5

A5 B5 C5 D5 E5 F5

Opcode

Operand

ii dd hh ll ee ff ff

ff ee ff

2 3 4 4 3 2 4 5

Effect on

Cycles

BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3

BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3

dd rr

DIR (b0) DIR (b1) DIR (b2)

BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 – – – – – R

BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3

BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 – – – – – R

BSET n,opr Set Bit n in M Mn ← 1 ––––––

DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

01 03 05 07 09 0B 0D 0F

00 02 04 06 08 0A 0C 0E

10 12 14 16 18 1A 1C 1E

dd rr dd rr dd rr dd rr dd rr dd rr dd rr

dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr

dd dd dd dd dd dd dd dd

5 5 5 5 5 5 5

5 5 5 5 5 5 5 5

4 4 4 4 4 4 4 4

MC68HC908JL3E Family Data Sheet, Rev. 3

44 Freescale Semiconductor

Table 4-1. Instruction Set Summary

Opcode Map

Source

Form

BSR rel Branch to Subroutine

CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel

CLC Clear Carry Bit C ← 0 –––––0INH 98 1

CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2

CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP

CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP

Compare and Branch if Equal

Clear

Compare A with M (A) – (M) R ––RRR

Operation Description

PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH)

SP ← (SP) – 1

PC ← (PC) + rel

PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (X) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 2 + rel ? (A) – (M) = $00 PC ← (PC) + 4 + rel ? (A) – (M) = $00

M ← $00 A ← $00 X ←

$00

H ← $00 M ← $00 M ← $00 M ← $00

CCR

Mode

31 41 51 61 71

9E61

3F 4F 5F 8C 6F 7F

9E6F

A1 B1 C1 D1 E1 F1

9EE1 9ED1

Opcode

Operand

dd rr ii rr ii rr ff rr rr ff rr

ii dd hh ll ee ff ff

ff ee ff

5 4 4 5 4 6

3 1 1 1 3 2 4

2 3 4 4 3 2 4 5

VH I NZC

––––––REL AD rr 4

––––––

0––01–

Address

DIR IMM IMM IX1+ IX+ SP1

DIR INH INH INH IX1 IX SP1

IMM DIR EXT IX2 IX1 IX SP1 SP2

Effect on

Cycles

COM opr COMA COMX COM opr,X COM ,X COM opr,SP

CPHX #opr CPHX opr

CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP

DAA Decimal Adjust A (A)

Complement (One’s Complement)

Compare H:X with M (H:X) – (M:M + 1) R ––RRR

Compare X with M (X) – (M) R ––RRR

M ← (M

A ← (A

X ← (X M ← (M M ← (M M ← (M

) = $FF – (M) ) = $FF – (M) ) = $FF – (M)

) = $FF – (M)

DIR INH

0––RR1

U–– RRRINH 72 2

INH IX1 IX SP1

IMM DIR

IMM DIR EXT IX2 IX1 IX SP1 SP2

33 43 53

63 73

9E63

6575ii ii+1dd3

hh ll

ee ff

E3 F3

9EE3

ee ff

9ED3

4 1 1 4 3 5

2 3 4 4 3 2 4 5

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 45

Central Processor Unit (CPU)

Table 4-1. Instruction Set Summary

Source

Form

DBNZ opr,rel DBNZA rel DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel

DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP

DIV Divide

EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP

Decrement and Branch if Not Zero

Decrement

Exclusive OR M with A A ← (A ⊕ M) 0 – – RR –

Operation Description

A ← (A)–1 or M ← (M) –1 or X ← (X)–1

PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 4 + rel ? (result) ≠ 0

M ← (M) – 1

A ←

(A) – 1

X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 M ← (M) – 1

A ← (H:A)/(X)

H ← Remainder

Effect on

CCR

Mode

3B 4B 5B 6B 7B

9E6B

3A 4A 5A 6A 7A

9E6A

A8 B8 C8 D8 E8

F8 9EE8 9ED8

Opcode

Operand

dd rr rr rr ff rr rr ff rr

ii dd hh ll ee ff ff

ff ee ff

VH I NZC

––––––

R ––RR–

––––RRINH 52 7

Address

DIR INH INH IX1 IX SP1

IMM DIR EXT IX2 IX1 IX SP1 SP2

Cycles

5 3 3 5 4 6

4 1 1 4 3 5

2 3 4 4 3 2 4 5

INC opr INCA INCX INC opr,X INC ,X INC opr,SP

JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X

JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X

LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP

LDHX #opr LDHX opr

M ← (M) + 1

A ← (A) + 1

Increment

Jump PC ← Jump Address ––––––

PC ← (PC) + n (n = 1, 2, or 3)

Jump to Subroutine

PC ← Unconditional Address

Load A from M A ← (M) 0 – – RR –

Load H:X from M H:X ← (M:M + 1) 0 – – RR–

X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 M ← (M) + 1

Push (PCL); SP ← (SP) – 1

Push (PCH); SP ← (SP) – 1

R ––RR–

––––––

DIR INH INH IX1 IX SP1

DIR EXT IX2 IX1 IX

IMM DIR EXT IX2 IX1 IX SP1 SP2

IMM DIR

3C 4C 5C

6C 7C

9E6C

hh ll

ee ff

EC FC

hh ll

ee ff

ED FD

hh ll

ee ff

E6 F6

9EE6

ee ff

9ED6

4555ii jjdd3

4 1 1 4 3 5

2 3 4 3 2

4 5 6 5 4

2 3 4 4 3 2 4 5

MC68HC908JL3E Family Data Sheet, Rev. 3

46 Freescale Semiconductor

Table 4-1. Instruction Set Summary

Opcode Map

Source

Form

LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP

LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP

LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP

MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr

Effect on

Operation Description

CCR

VH I NZC

Load X from M X ← (M) 0 – – RR –

Logical Shift Left (Same as ASL)

Logical Shift Right R ––0RR

Move

(M)

Destination

H:X ← (H:X) + 1 (IX+D, DIX+)

← (M)

Source

R ––RRR

0––RR–

IMM DIR EXT IX2 IX1 IX SP1 SP2

DIR INH INH IX1 IX SP1

DD DIX+ IMD IX+D

Address

Mode

9EEE 9EDE

AE BE CE DE EE FE

38 48 58 68 78

9E68

34 44 54 64 74

9E64

4E 5E 6E 7E

Opcode

Operand

ii dd hh ll ee ff ff

ff ee ff

dd dd dd ii dd dd

Cycles

2 3 4 4 3 2 4 5

4 1 1 4 3 5

5 4 4 4

MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5

ii dd hh ll ee ff ff

ff ee ff

4 1 1 4 3 5

2 3 4 4 3 2 4 5

NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP

NOP No Operation None ––––––INH 9D 1

NSA Nibble Swap A A ← (A[3:0]:A[7:4]) ––––––INH 62 3

ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP

PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2

PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2

PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2

PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2

Negate (Two’s Complement)

Inclusive OR A and M A ← (A) | (M) 0 – – RR–

M ← –(M) = $00 – (M)

A ← –(A) = $00 – (A)

X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M)

R ––RRR

DIR INH INH IX1 IX SP1

IMM DIR EXT IX2 IX1 IX SP1 SP2

30 40 50 60 70

9E60

AA BA CA DA EA

FA 9EEA 9EDA

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 47

Central Processor Unit (CPU)

Table 4-1. Instruction Set Summary

Source

Form

PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2

PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2

ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP

ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP

RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1

RTI Return from Interrupt

Rotate Left through Carry R ––RRR

Rotate Right through Carry R ––RRR

Operation Description

SP ← (SP) + 1; Pull (CCR)

SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X)

SP ← (SP) + 1; Pull (PCH)

SP ← (SP) + 1; Pull (PCL)

CCR

Mode

9E69

9E66

Opcode

Operand

VH I NZC

RRRRRRINH 80 7

Address

DIR INH INH IX1 IX SP1

4 1 1 4 3 5

Effect on

Cycles

RTS Return from Subroutine

SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP

SEC Set Carry Bit C ← 1 –––––1INH 99 1

SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2

STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP

STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – RR – DIR 35 dd 4

STOP Enable IRQ

Subtract with Carry A ← (A) – (M) – (C) R ––RRR

Store A in M M ← (A) 0 – – RR –

Pin; Stop Oscillator I ← 0; Stop Oscillator ––0–––INH 8E 1

SP ← SP + 1; Pull (PCH) SP ← SP + 1; Pull (PCL)

––––––INH 81 4

IMM DIR EXT IX2 IX1 IX SP1 SP2

DIR EXT IX2 IX1 IX SP1 SP2

F2 9EE2 9ED2

F7 9EE7 9ED7

dd hh ll ee ff ff

ff ee ff

dd hh ll ee ff ff

ff ee ff

3 4 4 3 2 4 5

MC68HC908JL3E Family Data Sheet, Rev. 3

48 Freescale Semiconductor

Table 4-1. Instruction Set Summary

Opcode Map

Source

Form

STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP

SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP

SWI Software Interrupt

Store X in M M ← (X) 0 – – RR –

Subtract A ← (A) – (M) R ––RRR

Operation Description

PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH)

← (SP) – 1; Push (X)

SP ← (SP) – 1; Push (A)

SP ← (SP) – 1; Push (CCR)

SP ← (SP) – 1; I ← 1

PCH ← Interrupt Vector High Byte

PCL ← Interrupt Vector Low Byte

Effect on

CCR

Mode

FF 9EEF 9EDF

F0 9EE0 9ED0

Opcode

Operand

dd hh ll ee ff ff

ff ee ff

ii dd hh ll ee ff ff

ff ee ff

3 4 4 3 2 4 5

2 3 4 4 3 2 4 5

VH I NZC

––1–––INH 83 9

Address

DIR EXT IX2 IX1 IX SP1 SP2

IMM DIR EXT IX2 IX1 IX SP1 SP2

Cycles

TAP Transfer A to CCR CCR ← (A) RRRRRRINH 84 2

TAX Transfer A to X X ← (A) ––––––INH 97 1

TPA Transfer CCR to A A ← (CCR) ––––––INH 85 1

TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP

TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2

TXA Transfer X to A A ← (X) ––––––INH 9F 1

TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2

Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – RR–

DIR INH INH IX1 IX SP1

7D 9E6D

3 1 1 3

2 4

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 49

Central Processor Unit (CPU)

Table 4-1. Instruction Set Summary

Source

Form

A Accumulator n Any bit C Carry/borrow bit opr Operand (one or two bytes) CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer H Half-carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte & Logical AND IMD Immediate source to direct destination addressing mode | Logical OR IMM Immediate addressing mode INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX+ Indexed, no offset, post increment addressing mode # Immediate value IX+D Indexed with post increment to direct addressing mode IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX1+ Indexed, 8-bit offset, post increment addressing mode ? If IX2 Indexed, 16-bit offset addressing mode : Concatenated with M Memory location R Set or cleared N Negative bit — Not affected

Operation Description

⊕ Logical EXCLUSIVE OR

« Sign extend

CCR

VH I NZC

Address

Mode

Opcode

Effect on

Cycles

Operand

MC68HC908JL3E Family Data Sheet, Rev. 3

50 Freescale Semiconductor

Opcode Map

SUB

CMP

1IX

SUB

CMP

3SP1

SUB

CMP

2IX1

SUB

CMP

4SP2

SUB

CMP

3IX2

SUB

CMP

3EXT

SUB

CMP

2DIR

SUB

CMP

2IMM

BLT

BGE

2REL

RTI

RTS

1INH

NEG

CBEQ

2IX+

1IX

NEG

3SP1

NEG

2IX1

NEGX

1INH

NEGA

1INH

NEG

2DIR

BRA

2REL

BSET0

2DIR

CBEQ

CBEQX

CBEQA

CBEQ

BRN

BCLR0

4SP1

3IX1+

3IMM

3DIR

2REL

2DIR

Table 4-2. Opcode Map

SBC

1IX

SBC

3SP1

SBC

2IX1

SBC

4SP2

SBC

3IX2

SBC

3EXT

SBC

2DIR

SBC

2IMM

BGT

2REL

DAA

1INH

NSA

1INH

DIV

1INH

MUL

1INH

BHI

2REL

BSET1

2DIR

CPX

BLE

SWI

COM

COMX

COMA

COM

BLS

BCLR1

1IX

3SP1

2IX1

4SP2

3IX2

3EXT

2DIR

2IMM

2REL

1INH

1IX

3SP1

2IX1

1INH

2DIR

2REL

2DIR

AND

1IX

AND

3SP1

AND

2IX1

AND

4SP2

AND

3IX2

AND

3EXT

AND

2DIR

AND

2IMM

TXS

1INH

TA P

1INH

LSR

1IX

LSR

3SP1

LSR

2IX1

LSRX

1INH

LSRA

1INH

LSR

2DIR

BCC

2REL

BSET2

2DIR

BIT

TSX

TPA

CPHX

LDHX

STHX

BCS

BCLR2

1IX

3SP1

2IX1

4SP2

3IX2

3EXT

2DIR

2IMM

1INH

2DIR

3IMM

2DIR

3IMM

2DIR

2REL

2DIR

LDA

1IX

LDA

3SP1

LDA

2IX1

LDA

4SP2

LDA

3IX2

LDA

3EXT

LDA

2DIR

LDA

2IMM

PULA

1INH

ROR

1IX

ROR

3SP1

ROR

2IX1

RORX

1INH

RORA

1INH

ROR

2DIR

BNE

2REL

BSET3

2DIR

STA

AIS

TA X

PSHA

ASR

ASRX

ASRA

ASR

BEQ

BCLR3

1IX

3SP1

2IX1

4SP2

3IX2

3EXT

2DIR

2IMM

1INH

1IX

3SP1

2IX1

1INH

2DIR

2REL

2DIR

EOR

1IX

EOR

3SP1

EOR

2IX1

EOR

4SP2

EOR

3IX2

EOR

3EXT

EOR

2DIR

EOR

2IMM

CLC

1INH

PULX

1INH

LSL

1IX

LSL

3SP1

LSL

2IX1

LSLX

1INH

LSLA

1INH

LSL

2DIR

BHCC

2REL

BSET4

2DIR

ADC

SEC

PSHX

ROL

ROLX

ROLA

ROL

BHCS

BCLR4

1IX

3SP1

2IX1

4SP2

3IX2

3EXT

2DIR

2IMM

1INH

1IX

3SP1

2IX1

1INH

2DIR

2REL

2DIR

ORA

1IX

ORA

3SP1

ORA

2IX1

ORA

4SP2

ORA

3IX2

ORA

3EXT

ORA

2DIR

ORA

2IMM

CLI

1INH

PULH

1INH

DEC

1IX

DEC

3SP1

DEC

2IX1

DECX

1INH

DECA

1INH

DEC

2DIR

BPL

2REL

BSET5

2DIR

ADD

SEI

PSHH

DBNZ

DBNZX

DBNZA

DBNZ

BMI

BCLR5

1IX

3SP1

2IX1

4SP2

3IX2

3EXT

2DIR

2IMM

1INH

2IX

4SP1

3IX1

2INH

3DIR

2REL

2DIR

JMP

1IX

JMP

2IX1

JMP

3IX2

JMP

3EXT

JMP

2DIR

RSP

1INH

CLRH

1INH

INC

1IX

INC

3SP1

INC

2IX1

INCX

1INH

INCA

1INH

INC

2DIR

BMC

2REL

BSET6

2DIR

JSR

BSR

NOP

TST

TSTX

TSTA

TST

BMS

BCLR6

1IX

2IX1

3IX2

3EXT

2DIR

2REL

1INH

1IX

3SP1

2IX1

1INH

2DIR

2REL

2DIR

LDX

1IX

LDX

3SP1

LDX

2IX1

LDX

4SP2

LDX

3IX2

LDX

3EXT

LDX

2DIR

LDX

2IMM

STOP

1INH

MOV

2IX+D

MOV

3IMD

MOV

2DIX+

MOV

3DD

BIL

2REL

BSET7

2DIR

STX

1IX

STX

3SP1

STX

2IX1

STX

4SP2

STX

3IX2

STX

3EXT

STX

2DIR

AIX

2IMM

TXA

1INH

WAIT

1INH

CLR

1IX

CLR

3SP1

CLR

2IX1

CLRX

1INH

CLRA

1INH

CLR

2DIR

BIH

2REL

BCLR7

2DIR

Cycles

Opcode Mnemonic

Number of Bytes / Addressing Mode

0 High Byte of Opcode in Hexadecimal

BRSET0

3DIR

MSB

LSB

Low Byte of Opcode in Hexadecimal 0

DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX

Bit Manipulation Branch Read-Modify-Write Control Register/Memory

01234569E6789ABCD9EDE9EEF

MSB

LSB

BRSET0

3DIR

BRCLR0

3DIR

BRSET1

3DIR

BRCLR1

3DIR

BRSET2

3DIR

BRCLR2

3DIR

BRSET3

3DIR

BRCLR3

3DIR

BRSET4

3DIR

BRCLR4

3DIR

BRSET5

3DIR

BRCLR5

3DIR

BRSET6

3DIR

BRCLR6

3DIR

BRSET7

3DIR

BRCLR7

3DIR

INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset

IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset

DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with

EXT Extended IX2 Indexed, 16-Bit Offset Post Increment

DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with

IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 51

*Pre-byte for stack pointer indexed instructions

Central Processor Unit (CPU)

MC68HC908JL3E Family Data Sheet, Rev. 3

52 Freescale Semiconductor

Chapter 5 System Integration Module (SIM)

5.1 Introduction

This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 5-1. Figure 5-2 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for:

• Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control

• Master reset control, including power-on reset (POR) and COP timeout

• Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation

• CPU enable/disable timing

• Modular architecture expandable to 128 interrupt sources

Table 5-1 shows the internal signal names used in this section.

Table 5-1. Signal Name Conventions

Signal Name Description

2OSCOUT Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit.

OSCOUT

IAB Internal address bus

IDB Internal data bus

PORRST Signal from the power-on reset module to the SIM

IRST Internal reset signal

R/W

The 2OSCOUT frequency divided by two. This signal is again divided by two in the SIM to

generate the internal bus clocks. (Bus clock = 2OSCOUT ÷ 4)

Read/write signal

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 53

System Integration Module (SIM)

STOP/WAIT

CONTROL

MODULE STOP

MODULE WAIT

CPU STOP (FROM CPU)

CPU WAIT (FROM CPU)

SIMOSCEN (TO OSCILLATOR)

INTERNAL

PULL-UP

RESET

PIN LOGIC

VDD

CLOCK

CONTROL

POR CONTROL

RESET PIN CONTROL

SIM RESET STATUS REGISTER

INTERRUPT CONTROL

AND PRIORITY DECODE

SIM

COUNTER

÷2

CLOCK GENERATORS

MASTER

RESET

CONTROL

RESET

COP CLOCK

2OSCOUT (FROM OSCILLATOR)

OSCOUT (FROM OSCILLATOR)

INTERNAL CLOCKS

ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS

MAP DECODERS)

COP TIMEOUT (FROM COP MODULE)

USB RESET (FROM USB MODULE)

INTERRUPT SOURCES

CPU INTERFACE

Figure 5-1. SIM Block Diagram

Addr.Register Name Bit 7654321Bit 0

$FE00 Break Status Register (BSR)

Read:

Write: NOTE

RRRRRR

SBSW

Reset:00000000

Note: Writing a logic 0 clears SBSW.

Read: POR PIN COP ILOP ILAD MODRST LVI 0

$FE01 Reset Status Register (RSR)

Write:

POR:10000000

$FE02 Reserved

Read:

Write:

RRRRRRRR

Reset:

Read:

Write:

BCFERRRRRRR

Reset: 0

$FE03

Break Flag Control

(BFCR)

Figure 5-2. SIM I/O Register Summary

MC68HC908JL3E Family Data Sheet, Rev. 3

54 Freescale Semiconductor

SIM Bus Clock Control and Generation

Read: 0 IF5 IF4 IF3 0 IF1 0 0

Write:RRRRRRRR

(INT1)

Reset:00000000

Read:IF140000000

Write:RRRRRRRR

(INT2)

Reset:00000000

Read:0000000IF15

Write:RRRRRRRR

(INT3)

Reset:00000000

= Unimplemented R = Reserved

$FE04

$FE05

$FE06

Interrupt Status Register 1

Interrupt Status Register 2

Interrupt Status Register 3

Figure 5-2. SIM I/O Register Summary

5.2 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 5-3.

From

OSCILLATOR

From

OSCILLATOR

2OSCOUT

OSCOUT

SIM COUNTER

÷ 2

BUS CLOCK

GENERATORS

SIM

Figure 5-3. SIM Clock Signals

5.2.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency (2OSCOUT) divided by four.

5.2.2 Clock Start-Up from POR

When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 2OSCOUT cycle POR time-out has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the time-out.

5.2.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows 2OSCOUT to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This time-out is selectable as 4096 or 32 2OSCOUT cycles. (See 5.6.2 Stop Mode.)

In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 55

System Integration Module (SIM)

5.3 Reset and System Initialization

The MCU has these reset sources:

• Power-on reset module (POR)

• External reset pin (RST

• Computer operating properly module (COP)

• Low-voltage inhibit module (LVI)

• Illegal opcode

• Illegal address

All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in Monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states.

An internal reset clears the SIM counter (see 5.4 SIM Counter), but an external reset does not. Each of

the resets sets a corresponding bit in the reset status register (RSR). (See 5.7 SIM Registers.)

5.3.1 External Pin Reset

The RST pin circuits include an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the reset status register (RSR) is set as long as RST of 67 2OSCOUT cycles, assuming that the POR was not the source of the reset. See Table 5-2 for details.

Figure 5-4 shows the relative timing.

)

is held low for a minimum

Table 5-2. PIN Bit Set Timing

Reset Type Number of Cycles Required to Set PIN

POR 4163 (4096 + 64 + 3)

All others 67 (64 + 3)

2OSCOUT

RST

IAB

VECT H VECT L

Figure 5-4. External Reset Timing

5.3.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST pin low for 32 2OSCOUT cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (Figure 5-5). An internal reset can be caused by an illegal address, illegal opcode, COP time-out, or POR. (See Figure 5-6 . Sources of Internal Reset.) Note that for POR resets, the SIM cycles through 4096 2OSCOUT cycles during which the SIM forces the RST sequence from the falling edge of RST

shown in Figure 5-5.

pin low. The internal reset signal then follows the

MC68HC908JL3E Family Data Sheet, Rev. 3

56 Freescale Semiconductor

IRST

Reset and System Initialization

RST

2OSCOUT

IAB

RST PULLED LOW BY MCU

32 CYCLES 32 CYCLES

VECTOR HIGH

Figure 5-5. Internal Reset Timing

The COP reset is asynchronous to the bus clock.

ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST

COPRST

POR

LVI

INTERNAL RESET

Figure 5-6. Sources of Internal Reset

The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.

5.3.2.1 Power-On Reset

When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST

) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.

At power-on, the following events occur:

• A POR pulse is generated.

• The internal reset signal is asserted.

• The SIM enables the oscillator to drive 2OSCOUT.

• Internal clocks to the CPU and modules are held inactive for 4096 2OSCOUT cycles to allow stabilization of the oscillator.

•The RST

pin is driven low during the oscillator stabilization time.

• The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 57

System Integration Module (SIM)

OSC1

PORRST

2OSCOUT

OSCOUT

RST

IAB

4096

CYCLES

CYCLES32CYCLES

$FFFE $FFFF

Figure 5-7. POR Recovery

5.3.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST

pin for all internal reset sources.

To prevent a COP module time-out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every (2 as possible out of reset to guarantee the maximum amount of time before the first time-out.

– 24) 2OSCOUT cycles, drives the COP counter. The COP should be serviced as soon

The COP module is disabled if the RST

pin or the IRQ1 pin is held at VDD+VHI while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST external noise. During a break state, V

or the IRQ1 pin. This prevents the COP from becoming disabled as a result of

DD+VHI

on the RST pin disables the COP module.

5.3.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the reset status register (RSR) and causes a reset.

If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST

pin for all

internal reset sources.

5.3.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST

pin for all internal reset sources.

MC68HC908JL3E Family Data Sheet, Rev. 3

58 Freescale Semiconductor

5.3.2.5 LVI Reset

SIM Counter

The low-voltage inhibit module (LVI) asserts its output to the SIM when the V trip voltage V

. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin

TRIP

voltage falls to the LVI

(RSTB) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the (RSTB) pin for all internal reset sources.

5.4 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of 2OSCOUT.

5.4.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine.

5.4.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32 2OSCOUT cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG).

5.4.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. (See 5.6.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 5.3.2 Active Resets from Internal Sources for counter control

and internal reset recovery sequences.)

5.5 Exception Control

Normal, sequential program execution can be changed in three different ways:

• Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI)

• Reset

• Break interrupts

5.5.1 Interrupts

An interrupt temporarily changes the sequence of program execution to respond to a particular event.

Figure 5-8 flow charts the handling of system interrupts.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 59

System Integration Module (SIM)

Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared).

FROM RESET

BREAK INTERRUPT?

YES

INTERRUPT?

(As many interrupts as exist on chip)

I BIT SET?

IRQ

TIMER

YES

STACK CPU REGISTERS.

LOAD PC WITH INTERRUPT VECTOR.

SET I BIT.

FETCH NEXT

INSTRUCTION

SWI

INSTRUCTION?

RTI

INSTRUCTION?

YES

UNSTACK CPU REGISTERS.

EXECUTE INSTRUCTION.

Figure 5-8. Interrupt Processing

MC68HC908JL3E Family Data Sheet, Rev. 3

60 Freescale Semiconductor

Exception Control

At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 5-9 shows interrupt entry timing.

Figure 5-10 shows interrupt recovery timing.

MODULE

INTERRUPT

I BIT

IAB

IDB

R/W

MODULE

INTERRUPT

I BIT

IAB

IDB

R/W

DUMMY

SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR

DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE

Figure 5-9. Interrupt Entry

SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1

CCR A X PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND

Figure 5-10. Interrupt Recovery

5.5.1.1 Hardware Interrupts

A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.

If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 5-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 61

System Integration Module (SIM)

CLI

BACKGROUND ROUTINE#$FF

INT1

INT2

LDA

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH

RTI

PSHH

INT2 INTERRUPT SERVICE ROUTINE

PULH

RTI

Figure 5-11. Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation.

NOTE

To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.

5.5.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register.

NOTE

A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does.

5.5.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt sources. Table 5-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging.

MC68HC908JL3E Family Data Sheet, Rev. 3

62 Freescale Semiconductor

Table 5-3. Interrupt Sources

Exception Control

INT

Priority Source Flag

Mask

1(1)

Vector Address

Flag

Highest Reset — — — $FFFE–$FFFF

SWI Instruction — — — $FFFC–$FFFD

IRQ

1 Pin IRQF1 IMASK1 IF1 $FFFA–$FFFB

Timer Channel 0 Interrupt CH0F CH0IE IF3 $FFF6–$FFF7

Timer Channel 1 Interrupt CH1F CH1IE IF4 $FFF4–$FFF5

Timer Overflow Interrupt TOF TOIE IF5 $FFF2–$FFF3

Keyboard Interrupt KEYF IMASKK IF14 $FFE0–$FFE1

Lowest ADC Conversion Complete Interrupt COCO AIEN IF15 $FFDE–$FFDF

1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.

5.5.2.1 Interrupt Status Register 1

Address: $FE04

Bit 7654321Bit 0

Read: 0 IF5 IF4 IF3 0 IF1 0 0

Write:RRRRRRRR

Reset:00000000

R= Reserved

Figure 5-12. Interrupt Status Register 1 (INT1)

IF1, IF3 to IF5 — Interrupt Flags

These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.

1 = Interrupt request present 0 = No interrupt request present

Bit 0, 1, 3 and 7 — Always read 0

5.5.2.2 Interrupt Status Register 2

Address: $FE05

Bit 7654321Bit 0

Read:IF140000000

Write:RRRRRRRR

Reset:00000000

R= Reserved

Figure 5-13. Interrupt Status Register 2 (INT2)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 63

System Integration Module (SIM)

IF14 — Interrupt Flags

This flag indicates the presence of interrupt requests from the sources shown in Table 5-3.

1 = Interrupt request present 0 = No interrupt request present

Bit 0 to 6 — Always read 0

5.5.2.3 Interrupt Status Register 3

Address: $FE06

Bit 7654321Bit 0

Read:0000000IF15

Write:RRRRRRRR

Reset:00000000

R= Reserved

Figure 5-14. Interrupt Status Register 3 (INT3)

IF15 — Interrupt Flags

These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.

1 = Interrupt request present 0 = No interrupt request present

Bit 1 to 7 — Always read 0

5.5.3 Reset

All reset sources always have equal and highest priority and cannot be arbitrated.

5.5.4 Break Interrupts

The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (See Chapter 15 Break Module (BREAK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.

5.5.5 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR).

Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information.

Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.

MC68HC908JL3E Family Data Sheet, Rev. 3

64 Freescale Semiconductor

Low-Power Modes

5.6 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low-power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.

5.6.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 5-15 shows the timing for wait mode entry.

A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option register is logic zero, then the computer operating properly module (COP) is enabled and remains active in wait mode.

WAIT ADDR

IDB

R/W

NOTE: Previous data can be operand data or the WAIT opcode, depending on the

PREVIOUS DATA NEXT OPCODE SAME

last instruction.

WAIT ADDR + 1 SAME SAMEIAB

Figure 5-15. Wait Mode Entry Timing

Figure 5-16 and Figure 5-17 show the timing for WAIT recovery.

IAB

IDB

EXITSTOPWAIT

NOTE: EXITSTOPWAIT =

$A6 $A6 $01 $0B $6E$A6

RST pin OR CPU interrupt OR break interrupt

$6E0C$6E0B $00FF $00FE $00FD $00FC

Figure 5-16. Wait Recovery from Interrupt or Break

SAME

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 65

System Integration Module (SIM)

2OSCOUT

IAB

IDB

RST

$A6

$6E0B

$A6 $A6

Cycles

RST VCT H RST VCT L

Figure 5-17. Wait Recovery from Internal Reset

5.6.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode.

The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG). If SSREC is set, stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode.

NOTE

External crystal applications should use the full stop recovery time by clearing the SSREC bit.

A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register (BSR).

The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 5-18 shows stop mode entry timing.

NOTE

To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.

CPUSTOP

STOP ADDR

IDB

R/W

NOTE: Previous data can be operand data or the STOP opcode, depending on the last

instruction.

PREVIOUS DATA NEXT OPCODE SAME

STOP ADDR + 1 SAME SAMEIAB

SAME

Figure 5-18. Stop Mode Entry Timing

MC68HC908JL3E Family Data Sheet, Rev. 3

66 Freescale Semiconductor

2OSCOUT

INT/BREAK

SIM Registers

STOP RECOVERY PERIOD

IAB

STOP +1

STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3

Figure 5-19. Stop Mode Recovery from Interrupt or Break

5.7 SIM Registers

The SIM has three memory mapped registers. Table 5-4 shows the mapping of these registers.

Table 5 -4. S IM Reg isters

Address Register Access Mode

$FE00 BSR User

$FE01 RSR User

$FE03 BFCR User

5.7.1 Break Status Register (BSR)

The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.

Address: $FE00

Bit 7654321Bit 0

Read:

Write: Note

Reset: 0

RRRRRR

R = Reserved 1. Writing a logic zero clears SBSW.

SBSW

(1)

Figure 5-20. Break Status Register (BSR)

SBSW — SIM Break Stop/Wait

This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.

1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt

SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit clears it.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 67

System Integration Module (SIM)

;

This code works if the H register has been pushed onto the stack in the break

;

service routine software. This code should be executed at the end of the

;

break service routine software. HIBYTE EQU 5 LOBYTE EQU 6

; If not SBSW, do RTI

BRCLR SBSW,BSR, RETURN ;;See if wait mode or stop mode was exited

by break. TST LOBYTE,SP ; If RETURNLO is not zero, BNE DOLO ; then just decrement low byte. DEC HIBYTE,SP ; Else deal with high byte, too.

DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode. RETURN PULH

RTI

; Restore H register.

5.7.2 Reset Status Register (RSR)

This register contains six flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register.

Address: $FE01

Bit 7654321Bit 0

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

POR:10000000

= Unimplemented

Figure 5-21. Reset Status Register (RSR)

POR — Power-On Reset Bit

1 = Last reset caused by POR circuit 0 = Read of SRSR

PIN — External Reset Bit

1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by COP counter 0 = POR or read of SRSR

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR

MC68HC908JL3E Family Data Sheet, Rev. 3

68 Freescale Semiconductor

SIM Registers

ILAD — Illegal Address Reset Bit (opcode fetches only)

1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR

MODRST — Monitor Mode Entry Module Reset bit

1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after

POR while IRQ1

= V

0 = POR or read of SRSR

LVI — Low Voltage Inhibit Reset bit

1 = Last reset caused by LVI circuit 0 = POR or read of SRSR

5.7.3 Break Flag Control Register (BFCR)

The break control register contains a bit that enables software to clear status bits while the MCU is in a break state.

Address: $FE03

Bit 7654321Bit 0

Read:

Write:

Reset: 0

BCFERRRRRRR

R= Reserved

Figure 5-22. Break Flag Control Register (BFCR)

BCFE — Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set.

1 = Status bits clearable during break 0 = Status bits not clearable during break

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 69

System Integration Module (SIM)

MC68HC908JL3E Family Data Sheet, Rev. 3

70 Freescale Semiconductor

Chapter 6 Oscillator (OSC)

6.1 Introduction

The oscillator module provides the reference clock for the MCU system and bus. Two types of oscillator modules are available:

• MC68HC908JL3E/JK3E/JK1E — built-in oscillator module (X-tal) that requires an external crystal or ceramic-resonator. This option also allows an external clock that can be driven directly into OSC1.

• MC68HRC908JL3E/JK3E/JK1E — built-in oscillator module (RC) that requires an external RC connection only.

6.2 X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E)

The X-tal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source.

In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, as shown in Figure 6-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components:

•Crystal, X

• Fixed capacitor, C

• Tuning capacitor, C2 (can also be a fixed capacitor)

• Feedback resistor, R

• Series resistor, RS (optional)

The series resistor (R be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information.

) is included in the diagram to follow strict Pierce oscillator guidelines and may not

6.3 RC Oscillator (MC68HRC908JL3E/JK3E/JK1E)

The RC oscillator circuit is designed for use with external R and C to provide a clock source with tolerance less than 10%.

In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components:

•C

EXT

•R

EXT

The RC connection is shown in Figure 6-2.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 71

Oscillator (OSC)

From SIM

SIMOSCEN

MCU

To SIMTo SIM

OSCOUT2OSCOUT

XTALCLK

OSC2OSC1

RS*

*RS can be zero (shorted) when used with higher-frequency crystals.

Refer to manufacturer’s data.

See Chapter 16 for component value requirements.

÷ 2

Figure 6-1. X-tal Oscillator External Connections

SIMOSCEN

MCU

To SIM

Ext-RC

Oscillator

OSC1

EXT

RCCLK

EXT

PTA6/RCCLK (OSC2)

See Chapter 16 for component value requirements.

PTA6

I/O

Figure 6-2. RC Oscillator External Connections

To SIMFrom SIM

OSCOUT2OSCOUT

÷ 2

PTA6

PTA6EN

MC68HC908JL3E Family Data Sheet, Rev. 3

72 Freescale Semiconductor

I/O Signals

6.4 I/O Signals

The following paragraphs describe the oscillator I/O signals.

6.4.1 Crystal Amplifier Input Pin (OSC1)

OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit.

6.4.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK)

For the X-tal oscillator device, OSC2 pin is the output of the crystal oscillator inverting amplifier.

For the RC oscillator device, OSC2 pin can be configured as a general purpose I/O pin PTA6, or the output of the internal RC oscillator clock, RCCLK.

Device Oscillator OSC2 pin function

MC68HC908JL3E/JK3E/JK1E X-tal Inverting OSC1

Controlled by PTA6EN bit in PTAPUER ($0D)

MC68HRC908JL3E/JK3E/JK1E RC

PTA6EN = 0: RCCLK output PTA6EN = 1: PTA6 I/O

6.4.3 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables the X-tal oscillator circuit or the RC-oscillator.

6.4.4 X-tal Oscillator Clock (XTALCLK)

XTALCLK is the X-tal oscillator output signal. It runs at the full speed of the crystal (f directly from the crystal oscillator circuit. Figure 6-1 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be unstable at start-up.

) and comes

XCLK

6.4.5 RC Oscillator Clock (RCCLK)

RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the external R and C. Figure 6-2 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry.

6.4.6 Oscillator Out 2 (2OSCOUT)

2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal is driven to the SIM module and is used to determine the COP cycles.

6.4.7 Oscillator Out (OSCOUT)

The frequency of this signal is equal to half of the 2OSCOUT, this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one fourth of the XTALCLK or RCCLK frequency.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 73

Oscillator (OSC)

6.5 Low Power Modes

The WAIT and STOP instructions put the MCU in low-power consumption standby modes.

6.5.1 Wait Mode

The WAIT instruction has no effect on the oscillator logic. OSCOUT and 2OSCOUT continues to drive to the SIM module.

6.5.2 Stop Mode

The STOP instruction disables the XTALCLK or the RCCLK output, hence OSCOUT and 2OSCOUT.

6.6 Oscillator During Break Mode

The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state.

MC68HC908JL3E Family Data Sheet, Rev. 3

74 Freescale Semiconductor

Chapter 7 Monitor ROM (MON)

7.1 Introduction

This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. This mode is also used for programming and erasing of FLASH memory in the MCU. Monitor mode entry can be achieved without use of the higher test voltage, V $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.

7.2 Features

Features of the monitor ROM include the following:

• Normal user-mode pin functionality

• One pin dedicated to serial communication between monitor ROM and host computer

• Standard mark/space non-return-to-zero (NRZ) communication with host computer

• Execution of code in RAM or FLASH

• FLASH memory security feature

• FLASH memory programming interface

• 960 bytes monitor ROM code size

• Monitor mode entry without high voltage, V contain $FF)

• Standard monitor mode entry if high voltage, V

(1)

+VHI, as long as vector addresses $FFFE and

+VHI, if reset vector is blank ($FFFE and $FFFF

DD+VHI

, is applied to IRQ1

7.3 Functional Description

The monitor ROM receives and executes commands from a host computer. Figure 7-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface.

Simple monitor commands can access any memory address. In monitor mode, the MCU can execute host-computer code in RAM while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTB0 pin. A level-shifting and multiplexing interface is required between PTB0 and the host computer. PTB0 is used in a wired-OR configuration and requires a pull-up resistor.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 75

Monitor ROM (MON)

RC CIRCUIT

FOR MC68HRC908JL3E/JK3E/JK1E

SW1 MUST BE AT POSITION B

FOR MC68HC908JL3E/JK3E/JK1E

EXT OSC

See Figure 16-1 for component values vs. frequency.

SW1 AT POSITION A OR B

FOR MC68HRC908JL3E/JK3E/JK1E

SW1 MUST BE AT POSITION A

XTAL CIRCUIT

FOR MC68HC908JL3E/JK3E/JK1E

SW1 AT POSITION A OR B

1 µF

DB9

MAX232

C1+

C1–

C2+

C2–

GND

V+

V–

1 µF

VDD + V

1 µF

74HC125

NOTES:

1. Monitor mode entry method: SW1: Position A — High voltage entry (V

Clock source must be EXT OSC or XTAL CIRCUIT.

TST

)

Bus clock depends on SW2.

SW1: Position B — Reset vector must be blank ($FFFE = $FFFF = $FF)

Bus clock = OSC1 ÷ 4.

2. Affects high voltage entry to monitor mode only (SW1 at position A): SW2: Position C — Bus clock = OSC1 ÷ 4 SW2: Position D — Bus clock = OSC1 ÷ 2

5. See Table 16-4 for V

+ VHI voltage level requirements.

(50% DUTY)

20 pF

10 k

9.8304MHz

1 k

8.5 V

(SEE NOTE 2)

20 pF

10 k

OSC1

OSC2

OSC1

OSC2

10M

0.1 µF

SW1

10 k

SW2

0.1 µF

(SEE NOTE 1)

10 k

RST

H(R)C908JL3E

H(R)C908JK3E

H(R)C908JK1E

OSC1

OSC2

IRQ

PTB0

PTB1

PTB3

PTB2

Figure 7-1. Monitor Mode Circuit

MC68HC908JL3E Family Data Sheet, Rev. 3

76 Freescale Semiconductor

Functional Description

7.3.1 Entering Monitor Mode

Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode

may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met:

1. If IRQ1 – Clock on OSC1 is 4.9125MHz (EXT OSC or XTAL)

–PTB3 = low

2. If IRQ1 – Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL)

– PTB3 = high

3. If $FFFE & $FFFF is blank (contains $FF): – Clock on OSC1 is 9.8304MHz (EXT OSC or XTAL or RC)

–IRQ1

= VDD + VHI:

= V

Table 7-1. Monitor Mode Entry Requirements and Options

(1)

IRQ1

(2)

+ V

1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using VDD + VHI for monitor mode entry. The OSC1 clock must be 50% duty cycle for this condition.

2. See Table 16-4 for VDD + VHI voltage level requirements.

3. For IRQ1 MC68HRC908JL3E/JK3E/JK1E — clock must be EXT OSC. MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.

4. For IRQ1 MC68HRC908JL3E/JK3E/JK1E — clock must be RC OSC. MC68HC908JL3E/JK3E/JK1E — clock can be EXT OSC or XTAL.

= VDD + VHI:

= VDD:

and

$FFFF

$FFFE

X 0011 4.9152MHz

X 1011 9.8304MHz

BLANK

(contain

$FF)

NOT

BLANK

PTB2

PTB3

XXX1 9.8304MHz

XXXX

PTB1

OSC1 Frequency

PTB0

At desired frequency

Bus

Frequency

2.4576MHz (OSC1 ÷ 2)

2.4576MHz (OSC1 ÷ 4)

OSC1 ÷ 4 Enters User mode.

High-voltage entry to monitor mode. 9600 baud communication on PTB0. COP disabled.

Low-voltage entry to monitor mode. 9600 baud communication on PTB0. COP disabled.

Comments

(3)

(4)

If VDD+VHI is applied to IRQ1 and PTB3 is low upon monitor mode entry (Table 7-1 condition set 1), the bus frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with V

DD+VHI

applied to IRQ1 upon monitor mode entry (Table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock input to OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if V

DD+VHI

is applied to IRQ1. In this event, the OSCOUT frequency is equal

to the 2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 77

Monitor ROM (MON)

Entering monitor mode with VDD+VHI on IRQ1, the COP is disabled as long as VDD+V either the IRQ1

or the RST. (See Chapter 5 System Integration Module (SIM) for more information on

is applied to

modes of operation.)

If entering monitor mode without high voltage on IRQ1 (Table 7-1 condition set 3, where applied voltage is V

and reset vector being blank ($FFFE and $FFFF)

), then all port B pin requirements and conditions,

including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming.

Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the state of IRQ1

or the RST.

Figure 7-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ1

. An OSC1 frequency of 9.8304MHz is required for a baud rate of 9600.

= V

POR RESET

IS VECTOR

BLANK?

YES

MONITOR MODE

NORMAL USER

MODE

EXECUTE MONITOR

CODE

POR

TRIGGERED?

YES

Figure 7-2. Low-Voltage Monitor Mode Entry Flowchart

Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising edge of RST

latches monitor mode. Once monitor mode is latched, the values on the specified pins can

change.

Once out of reset, the MCU waits for the host to send eight security bytes. (See 7.4 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is ready to receive a command. The break signal also provides a timing reference to allow the host to determine the necessary baud rate.

In monitor mode, the MCU uses different vectors for reset, SWI, and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code.

Table 7-2 is a summary of the vector differences between user mode and monitor mode.

MC68HC908JL3E Family Data Sheet, Rev. 3

78 Freescale Semiconductor

Table 7-2. Monitor Mode Vector Differences

Functions

Functional Description

Modes

User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD

Monitor

Notes:

1. If the high voltage (VDD + VHI) is removed from the IRQ1 pin or the RST pin, the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register.

COP

Disabled

Reset

Vector

High

(1)

$FEFE $FEFF $FEFC $FEFD $FEFC $FEFD

Reset

Vector

Low

Break

Vector

High

Break

Vector

Low

SWI

Vector

High

SWI

Vector

Low

When the host computer has completed downloading code into the MCU RAM, the host then sends a RUN command, which executes an RTI, which sends control to the address on the stack pointer.

7.3.2 Baud Rate

The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud rate if entry to monitor mode is by IRQ1 the PTB3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512.

Table 7-3. Monitor Baud Rate Selection

Monitor Mode

Entry By:

= VDD+VHI. When PTB3 is high, the divide by ratio is 1024. If

Input Clock

Frequency

PTB3 Baud Rate

4.9152 MHz 0 9600 bps

= VDD + V

IRQ1

Blank reset vector,

= V

IRQ1

9.8304 MHz 1 9600 bps

4.9152 MHz 1 4800 bps

9.8304 MHz X 9600 bps

4.9152 MHz X 4800 bps

7.3.3 Data Format

Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 7-3 and Figure 7-4.)

START

BIT

BIT 0 BIT 1

BIT 2 BIT 3 BIT 4 BIT 6 BIT 7

BIT 5

Figure 7-3. Monitor Data Format

STOP

BIT

START

BIT

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 79

Monitor ROM (MON)

$A5

BREAK

START

BIT

START

BIT

BIT 0 BIT 1

BIT 2 BIT 3 BIT 4 BIT 6 BIT 7

BIT 2

BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

BIT 5

STOP

BIT

STOP

BIT

START

BIT

START

BIT

Figure 7-4. Sample Monitor Waveforms

The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and receive baud rates must be identical.

7.3.4 Echoing

As shown in Figure 7-5, the monitor ROM immediately echoes each received byte back to the PTB0 pin for error checking.

SENT TO MONITOR

ADDR. HIGHREADREAD ADDR. HIGH ADDR. LOW ADDR. LOW DATA

ECHO

RESULT

Figure 7-5. Read Transaction

Any result of a command appears after the echo of the last byte of the command.

7.3.5 Break Signal

A start bit followed by nine low bits is a break signal. (See Figure 7-6.) When the monitor receives a break signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal.

MISSING STOP BIT

0 1 2 3 4 5 6 7

TWO-STOP-BIT DELAY BEFORE ZERO ECHO

0 1 2 3 4 5 6 7

Figure 7-6. Break Transaction

7.3.6 Commands

The monitor ROM uses the following commands:

• READ (read memory)

• WRITE (write memory)

• IREAD (indexed read)

• IWRITE (indexed write)

• READSP (read stack pointer)

• RUN (run user program)

MC68HC908JL3E Family Data Sheet, Rev. 3

80 Freescale Semiconductor

Table 7-4. READ (Read Memory) Command

Description Read byte from memory

Operand Specifies 2-byte address in high byte:low byte order

Data Returned Returns contents of specified address

Opcode $4A

Command Sequence

SENT TO MONITOR

ADDR. HIGHREADREAD ADDR. HIGH ADDR. LOW ADDR. LOW DATA

Functional Description

ECHO

RESULT

Table 7-5. WRITE (Write Memory) Command

Description Write byte to memory

Operand Specifies 2-byte address in high byte:low byte order; low byte followed by data byte

Data Returned None

Opcode $49

Command Sequence

SENT TO MONITOR

ADDR. HIGHWRITEWRITE ADDR. HIGH ADDR. LOW ADDR. LOW DATA

ECHO

DATA

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 81

Monitor ROM (MON)

Table 7-6. IREAD (Indexed Read) Command

Description Read next 2 bytes in memory from last address accessed

Operand Specifies 2-byte address in high byte:low byte order

Data Returned Returns contents of next two addresses

Opcode $1A

Command Sequence

SENT TO MONITOR

DATAIREADIREAD DATA

ECHO

Table 7-7. IWRITE (Indexed Write) Command

Description Write to last address accessed + 1

Operand Specifies single data byte

Data Returned None

Opcode $19

Command Sequence

SENT TO MONITOR

DATAIWRITEIWRITE DATA

ECHO

A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map.

RESULT

NOTE

MC68HC908JL3E Family Data Sheet, Rev. 3

82 Freescale Semiconductor

Table 7-8. READSP (Read Stack Pointer) Command

Description Reads stack pointer

Operand None

Data Returned Returns stack pointer in high byte:low byte order

Opcode $0C

Command Sequence

SENT TO MONITOR

SP HIGHREADSPREADSP SP LOW

Security

ECHO

Table 7-9. RUN (Run User Program) Command

Description Executes RTI instruction

Operand None

Data Returned None

Opcode $28

Command Sequence

SENT TO MONITOR

RUNRUN

ECHO

7.4 Security

RESULT

A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.

NOTE

Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.

During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTB0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 7-7.)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 83

Monitor ROM (MON)

RST

4096 + 32 OSCXCLK CYCLES

24 BUS CYCLES

FROM HOST

PTB0

FROM MCU

NOTES:

1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte.

BYTE 1

141 12 1

BYTE 2

BYTE 1 ECHO

BYTE 2 ECHO

BYTE 8

COMMAND

BREAK

BYTE 8 ECHO

COMMAND ECHO

Figure 7-7. Monitor Mode Entry Timing

Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command.

NOTE

The MCU does not transmit a break character until after the host sends the eight security bytes.

To determine whether the security code entered is correct, check to see if bit 6 of RAM address $40 is set. If it is, then the correct security code has been entered and FLASH can be accessed.

If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank).

MC68HC908JL3E Family Data Sheet, Rev. 3

84 Freescale Semiconductor

Chapter 8 Timer Interface Module (TIM)

8.1 Introduction

This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions.

Figure 8-1 is a block diagram of the TIM.

8.2 Features

Features of the TIM include the following:

• Two input capture/output compare channels – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action

• Buffered and unbuffered pulse width modulation (PWM) signal generation

• Programmable TIM clock input with 7-frequency internal bus clock prescaler selection

• Free-running or modulo up-count operation

• Toggle any channel pin on overflow

• TIM counter stop and reset bits

8.3 Pin Name Conventions

The TIM share two I/O pins with two port D I/O pins. The full name of the TIM I/O pins are listed in

Table 8-1. The generic pin name appear in the text that follows.

Table 8-1. Pin Name Conventions

TIM Generic Pin Names: TCH0 TCH1

Full TIM Pin Names: PTD4/TCH0 PTD5/TCH1

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 85

Timer Interface Module (TIM)

8.4 Functional Description

Figure 8-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter

that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence.

The two TIM channels are programmable independently as input capture or output compare channels.

INTERNAL

BUS CLOCK

TSTOP

TRST

INTERNAL BUS

PRESCALER

16-BIT COUNTER

16-BIT COMPARATOR

TMODH:TMODL

CHANNEL 0

16-BIT COMPARATOR

TCH0H:TCH0L

16-BIT LATCH

CHANNEL 1

16-BIT COMPARATOR

TCH1H:TCH1L

16-BIT LATCH

PRESCALER SELECT

PS2 PS1 PS0

ELS0B ELS0A

MS0A

ELS1B ELS1A

MS1A

CH0F

MS0B

CH1F

TOF

TOIE

TOV0

CH0MAX

CH0IE

TOV1

CH1MAX

CH1IE

INTERRUPT

LOGIC

PORT

LOGIC

INTERRUPT

LOGIC

PORT

LOGIC

INTERRUPT

LOGIC

TCH0

TCH1

Figure 8-1. TIM Block Diagram

MC68HC908JL3E Family Data Sheet, Rev. 3

86 Freescale Semiconductor

Functional Description

Addr. Register Name Bit 7654321Bit 0

$0020

$0021

$0022

$0023

$0024

$0025

$0026

$0027

$0028

$0029

$002A

TIM Status and Control

(TSC)

TIM Counter Register High

(TCNTH)

TIM Counter Register Low

(TCNTL)

TIM Counter Modulo Register

High

(TMODH)

TIM Counter Modulo Register

Low

(TMODL)

TIM Channel 0 Status and

Control Register

(TSC0)

TIM Channel 0

(TCH0H)

TIM Channel 0

(TCH0L)

TIM Channel 1 Status and

Control Register

(TSC1)

TIM Channel 1

(TCH1H)

TIM Channel 1

(TCH1L)

Read: TOF

Write: 0 TRST

Reset:00100000

Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Write:

Reset:00000000

Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Write:

Reset:00000000

Read:

Write:

Reset:11111111

Read:

Write:

Reset:11111111

Read: CH0F

Write: 0

Reset:00000000

Read:

Write:

Reset: Indeterminate after reset

Read:

Write:

Reset: Indeterminate after reset

Read: CH1F

Write: 0

Reset:00000000

Read:

Write:

Reset: Indeterminate after reset

Read:

Write:

Reset: Indeterminate after reset

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TOIE TSTOP

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

CH1IE

= Unimplemented

MS1A ELS1B ELS1A TOV1 CH1MAX

PS2 PS1 PS0

Figure 8-2. TIM I/O Register Summary

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 87

Timer Interface Module (TIM)

8.4.1 TIM Counter Prescaler

The TIM clock source is one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source.

8.4.2 Input Capture

With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.

8.4.3 Output Compare

With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests.

8.4.3.1 Unbuffered Output Compare

Any output compare channel can generate unbuffered output compare pulses as described in 8.4.3

Output Compare. The pulses are unbuffered because changing the output compare value requires writing

the new value over the old value currently in the TIM channel registers.

An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written.

Use the following methods to synchronize unbuffered changes in the output compare value on channel x:

• When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value.

• When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.

8.4.3.2 Buffered Output Compare

Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that

MC68HC908JL3E Family Data Sheet, Rev. 3

88 Freescale Semiconductor

Functional Description

control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin.

NOTE

In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.

8.4.4 Pulse Width Modulation (PWM)

By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal.

As Figure 8-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic one. Program the TIM to set the pin if the state of the PWM pulse is logic zero.

OVERFLOW OVERFLOW OVERFLOW

PERIOD

PULSE WIDTH

TCHx

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

Figure 8-3. PWM Period and Pulse Width

The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000 (see 8.9.1 TIM Status and Control Register (TSC)).

The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%.

8.4.4.1 Unbuffered PWM Signal Generation

Any output compare channel can generate unbuffered PWM pulses as described in 8.4.4 Pulse Width

Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new

pulse width value over the old value currently in the TIM channel registers.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 89

Timer Interface Module (TIM)

An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written.

Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:

• When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.

• When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.

NOTE

In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.

8.4.4.2 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin.

NOTE

In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.

8.4.4.3 PWM Initialization

To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure:

1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP.

b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.

MC68HC908JL3E Family Data Sheet, Rev. 3

90 Freescale Semiconductor

Interrupts

2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM

period.

3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.

4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare

or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 8-3.)

b. Write 1 to the toggle-on-overflow bit, TOVx.

c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level

select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 8-3.)

NOTE

In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.

5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.

Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.

Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output.

Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1).)

8.5 Interrupts

The following TIM sources can generate interrupt requests:

• TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register.

• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE= 1. CHxF and CHxIE are in the TIM channel x status and control register.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 91

Timer Interface Module (TIM)

8.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power- consumption standby modes.

8.6.1 Wait Mode

The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode.

If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.

8.6.2 Stop Mode

The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.

8.7 TIM During Break Interrupts

A break interrupt stops the TIM counter.

The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR).)

To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero. After the break, doing the second step clears the status bit.

8.8 I/O Signals

Port D shares two of its pins with the TIM. The two TIM channel I/O pins are PTD4/TCH0 and PTD5/TCH1.

Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTD4/TCH0 can be configured as a buffered output compare or buffered PWM pin.

8.9 I/O Registers

The following I/O registers control and monitor operation of the TIM:

• TIM status and control register (TSC)

• TIM counter registers (TCNTH:TCNTL)

• TIM counter modulo registers (TMODH:TMODL)

• TIM channel status and control registers (TSC0 and TSC1)

• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)

MC68HC908JL3E Family Data Sheet, Rev. 3

92 Freescale Semiconductor

I/O Registers

8.9.1 TIM Status and Control Register (TSC)

The TIM status and control register does the following:

• Enables TIM overflow interrupts

• Flags TIM overflows

• Stops the TIM counter

• Resets the TIM counter

• Prescales the TIM counter clock

Address: $0020

Bit 7654321Bit 0

Read: TOF

Write: 0 TRST

Reset:00100000

TOIE TSTOP

= Unimplemented

Figure 8-4. TIM Status and Control Register (TSC)

TOF — TIM Overflow Flag Bit

This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic zero to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect.

1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value

PS2 PS1 PS0

TOIE — TIM Overflow Interrupt Enable Bit

This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit.

1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled

TSTOP — TIM Stop Bit

This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.

1 = TIM counter stopped 0 = TIM counter active

NOTE

Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode.

TRST — TIM Reset Bit

Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic zero. Reset clears the TRST bit.

1 = Prescaler and TIM counter cleared 0 = No effect

NOTE

Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 93

Timer Interface Module (TIM)

PS[2:0] — Prescaler Select Bits

These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as

Table 8-2 shows. Reset clears the PS[2:0] bits.

Table 8-2. Prescaler Selection

PS2 PS1 PS0 TIM Clock Source

0 0 0 Internal Bus Clock ÷ 1

0 0 1 Internal Bus Clock ÷ 2

0 1 0 Internal Bus Clock ÷ 4

0 1 1 Internal Bus Clock ÷ 8

1 0 0 Internal Bus Clock ÷ 16

1 0 1 Internal Bus Clock ÷ 32

1 1 0 Internal Bus Clock ÷ 64

1 1 1 Not available

8.9.2 TIM Counter Registers (TCNTH:TCNTL)

The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.

NOTE

If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.

Address: $0021 TCNTH

Bit 7654321Bit 0

Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Write:

Reset:00000000

Address: $0022 TCNTL

Bit 7654321Bit 0

Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Write:

Reset:00000000

= Unimplemented

Figure 8-5. TIM Counter Registers (TCNTH:TCNTL)

MC68HC908JL3E Family Data Sheet, Rev. 3

94 Freescale Semiconductor

I/O Registers

8.9.3 TIM Counter Modulo Registers (TMODH:TMODL)

The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.

Address: $0023 TMODH

Bit 7654321Bit 0

Read:

Write:

Reset:11111111

Address: $0024 TMODL

Read:

Write:

Reset:11111111

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit 7654321Bit 0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Figure 8-6. TIM Counter Modulo Registers (TMODH:TMODL)

NOTE

Reset the TIM counter before writing to the TIM counter modulo registers.

8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1)

Each of the TIM channel status and control registers does the following:

• Flags input captures and output compares

• Enables input capture and output compare interrupts

• Selects input capture, output compare, or PWM operation

• Selects high, low, or toggling output on output compare

• Selects rising edge, falling edge, or any edge as the active input capture trigger

• Selects output toggling on TIM overflow

• Selects 0% and 100% PWM duty cycle

• Selects buffered or unbuffered output compare/PWM operation

Address: $0025 TSC0

Bit 7654321Bit 0

Read: CH0F

Write: 0

Reset:00000000

Figure 8-7. TIM Channel Status and Control Registers (TSC0:TSC1)

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 95

Timer Interface Module (TIM)

Address: $0028 TSC1

Bit 7654321Bit 0

Read: CH1F

Write: 0

Reset:00000000

CH1IE

= Unimplemented

MS1A ELS1B ELS1A TOV1 CH1MAX

Figure 8-7. TIM Channel Status and Control Registers (TSC0:TSC1)

CHxF — Channel x Flag Bit

When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE=1), clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a logic zero to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic zero to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.

1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x

CHxIE — Channel x Interrupt Enable Bit

This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit.

1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled

MSxB — Mode Select Bit B

This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit.

1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled

MSxA — Mode Select Bit A

When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 8-3.

1 = Unbuffered output compare/PWM operation

0 = Input capture operation When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See Table 8-3.) Reset clears the MSxA bit.

1 = Initial output level low

0 = Initial output level high

NOTE

Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC).

MC68HC908JL3E Family Data Sheet, Rev. 3

96 Freescale Semiconductor

I/O Registers

ELSxB and ELSxA — Edge/Level Select Bits

When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 8-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.

Table 8-3. Mode, Edge, and Level Selection

MSxB MSxA ELSxB ELSxA Mode Configuration

X0 0 0

X1 0 0

00 0 1

0 0 1 0 Capture on Falling Edge Only

0 0 1 1 Capture on Rising or Falling Edge

01 0 1

0 1 1 0 Clear Output on Compare

0 1 1 1 Set Output on Compare

1X 0 1Buffered

1 X 1 0 Clear Output on Compare

1 X 1 1 Set Output on Compare

Output Preset

Input

Capture

Output

Compare

or PWM

Output

Compare or

Buffered

PWM

Pin under Port Control; Initial Output Level High

Pin under Port Control; Initial Output Level Low

Capture on Rising Edge Only

Toggle Output on Compare

NOTE

Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks.

TOVx — Toggle-On-Overflow Bit

When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit.

1 = Channel x pin toggles on TIM counter overflow.

0 = Channel x pin does not toggle on TIM counter overflow.

NOTE

When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time.

CHxMAX — Channel x Maximum Duty Cycle Bit

When the TOVx bit is at logic one, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 8-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 97

Timer Interface Module (TIM)

OVERFLOW

TCHx

COMPARE

CHxMAX

OVERFLOW OVERFLOW OVERFLOW OVERFLOW

PERIOD

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

Figure 8-8. CHxMAX Latency

8.9.5 TIM Channel Registers (TCH0H/L:TCH1H/L)

These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown.

In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read.

In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.

Address: $0026 TCH0H

Bit 7654321Bit 0

Read:

Write:

Reset: Indeterminate after reset

Address: $0027 TCH0L

Read:

Write:

Reset: Indeterminate after reset

Address: $0029 TCH1H

Read:

Write:

Reset: Indeterminate after reset

Address: $02A TCH1L

Read:

Write:

Reset: Indeterminate after reset

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit 7654321Bit 0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit 7654321Bit 0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit 7654321Bit 0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Figure 8-9. TIM Channel Registers (TCH0H/L:TCH1H/L)

MC68HC908JL3E Family Data Sheet, Rev. 3

98 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (ADC)

9.1 Introduction

This section describes the 12-channel, 8-bit linear successive approximation analog-to-digital converter (ADC).

9.2 Features

Features of the ADC module include:

• 12 channels with multiplexed input

• Linear successive approximation with monotonicity

• 8-bit resolution

• Single or continuous conversion

• Conversion complete flag or conversion complete interrupt

• Selectable ADC clock

Addr.Register Name Bit 7654321Bit 0

Read: COCO

Write:

Reset:00011111

Read:AD7AD6AD5AD4AD3AD2AD1AD0

Write:

(ADR)

Reset: Indeterminate after reset

Read:

Write:

Reset:00000000

ADIV2 ADIV1 ADIV0

AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

00000

$003C

$003D

$003E

ADC Status and Control

(ADSCR)

ADC Data Register

ADC Input Clock Register

(ADICLK)

Figure 9-1. ADC I/O Register Summary

9.3 Functional Description

Twelve ADC channels are available for sampling external sources at pins PTB0–PTB7 and PTD0–PTD3. An analog multiplexer allows the single ADC converter to select one of the 12 ADC channels as ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is 8 bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Figure 9-2 shows a block diagram of the ADC.

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor 99

Analog-to-Digital Converter (ADC)

INTERNAL DATA B US

READ DDRB/DDRD

WRITE DDRB/DDRD

WRITE PTB/PTD

READ PTB/PTD

INTERRUPT

LOGIC

AIEN COCO

CONVERSION COMPLETE

RESET

ADC DATA REGISTER

ADC

DDRBx/DDRDx

PTBx/PTDx

ADC CLOCK

DISABLE

ADC VOLTAGE IN ADCVIN

DISABLE

ADCx

ADC CHANNEL x

CHANNEL

SELECT

(1 OF 12 CHANNELS)

ADCH[4:0]

BUS CLOCK

CLOCK

GENERATOR

ADIV[2:0] ADICLK

Figure 9-2. ADC Block Diagram

9.3.1 ADC Port I/O Pins

PTB0–PTB7 and PTD0–PTD3 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits (ADC status and control register, $003C), define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.

MC68HC908JL3E Family Data Sheet, Rev. 3

100 Freescale Semiconductor

Freescale MC68HC908JL3E, MC68HC908JK3E, MC68HC908JK1E, MC68HRC908JL3E, MC68HRC908JK3E Technical Data

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

Chapter 1 General Description

1.1 Introduction

1.2 Features

1.3 MCU Block Diagram

1.4 Pin Assignments

1.5 Pin Functions

Chapter 2 Memory

2.1 Introduction

2.2 I/O Section

2.3 Monitor ROM

2.4 Random-Access Memory (RAM)

2.5 FLASH Memory

2.6 Functional Description

2.7 FLASH Control Register

2.8 FLASH Page Erase Operation

2.9 FLASH Mass Erase Operation

2.10 FLASH Program Operation

2.11 FLASH Protection

2.12 FLASH Block Protect Register

Chapter 3 Configuration Registers (CONFIG)

3.1 Introduction

3.2 Functional Description

3.3 Configuration Register 1 (CONFIG1)

3.4 Configuration Register 2 (CONFIG2)

Chapter 4 Central Processor Unit (CPU)

4.1 Introduction

4.2 Features

4.3 CPU Registers

4.3.1 Accumulator

4.3.2 Index Register

4.3.3 Stack Pointer

4.3.4 Program Counter

4.3.5 Condition Code Register

4.4 Arithmetic/Logic Unit (ALU)

4.5 Low-Power Modes

4.5.1 Wait Mode

4.5.2 Stop Mode

4.6 CPU During Break Interrupts

4.7 Instruction Set Summary

4.8 Opcode Map

Chapter 5 System Integration Module (SIM)

5.1 Introduction

5.2 SIM Bus Clock Control and Generation

5.2.1 Bus Timing

5.2.2 Clock Start-Up from POR

5.2.3 Clocks in Stop Mode and Wait Mode

5.3 Reset and System Initialization

5.3.1 External Pin Reset

5.3.2 Active Resets from Internal Sources

5.3.2.1 Power-On Reset

5.3.2.2 Computer Operating Properly (COP) Reset

5.3.2.3 Illegal Opcode Reset

5.3.2.4 Illegal Address Reset

5.3.2.5 LVI Reset

5.4 SIM Counter

5.4.1 SIM Counter During Power-On Reset

5.4.2 SIM Counter During Stop Mode Recovery

5.4.3 SIM Counter and Reset States

5.5 Exception Control

5.5.1 Interrupts

5.5.1.1 Hardware Interrupts

5.5.1.2 SWI Instruction

5.5.2 Interrupt Status Registers

5.5.2.1 Interrupt Status Register 1

5.5.2.2 Interrupt Status Register 2

5.5.2.3 Interrupt Status Register 3

5.5.3 Reset

5.5.4 Break Interrupts

5.5.5 Status Flag Protection in Break Mode

5.6 Low-Power Modes

5.6.1 Wait Mode

5.6.2 Stop Mode

5.7 SIM Registers

5.7.1 Break Status Register (BSR)

5.7.2 Reset Status Register (RSR)