MC68HC908LJ24
MC68HC908LK24
Data Sheet
M68HC08
Microcontrollers
Rev. 2.1
MC68HC908LJ24/D
August 16, 2005
freescale.com
MC68HC908LJ24
MC68HC908LK24
Data Sheet
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The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
This product incorporates SuperFlash® technology licensed from SST. © Freescale, Inc., 2005
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor 3
Revision History
Revision History
Date
8/2003 2 First general release. —
Revision
Level
Description
Page
Number(s)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
4 Freescale Semiconductor
Data Sheet — MC68HC908LJ24
Section 1. General Description . . . . . . . . . . . . . . . . . . . .37
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 3. Random-Access Memory (RAM) . . . . . . . . . .67
Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . .69
Section 5. Configuration Registers (CONFIG) . . . . . . . .79
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . .85
Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . .103
Section 8. Clock Generator Module (CGM). . . . . . . . . .109
Section 9. System Integration Module (SIM) . . . . . . . .139
List of Sections
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .163
Section 11. Timer Interface Module (TIM) . . . . . . . . . . .193
Section 12. Real Time Clock (RTC) . . . . . . . . . . . . . . . .217
Section 13. Infrared Serial Communications
Interface Module (IRSCI) . . . . . . . . . . . .245
Section 14. Serial Peripheral Interface Module (SPI). .287
Section 15. Multi-Master IIC Interface (MMIIC) . . . . . . .319
Section 16. Analog-to-Digital Converter (ADC) . . . . . .333
Section 17. Liquid Crystal Display (LCD) Driver . . . . .349
Section 18. Input/Output (I/O) Ports . . . . . . . . . . . . . . .375
Section 19. External Interrupt (IRQ) . . . . . . . . . . . . . . .401
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor List of Sections 5
List of Sections
Section 20. Keyboard Interrupt Module (KBI). . . . . . . .407
Section 21. Computer Operating Properly (COP) . . . .415
Section 22. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . .421
Section 23. Break Module (BRK) . . . . . . . . . . . . . . . . . .427
Section 24. Electrical Specifications. . . . . . . . . . . . . . .435
Section 25. Mechanical Specifications . . . . . . . . . . . . .451
Section 26. Ordering Information . . . . . . . . . . . . . . . . .457
Appendix A. MC68HC908LK24. . . . . . . . . . . . . . . . . . . .459
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
6 List of Sections Freescale Semiconductor
Data Sheet — MC68HC908LJ24
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
1.6.1 Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . .44
1.6.2 Analog Power Supply Pin (V
1.6.3 LCD Bias Voltage (V
1.6.4 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .45
1.6.5 External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .45
1.6.6 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .45
1.6.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .45
1.6.8 ADC Voltage High Reference Pin (V
1.6.9 ADC Voltage Low Reference Pin (V
1.6.10 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . .46
1.6.11 Port B I/O Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . .46
1.6.12 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . .46
1.6.13 Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . .46
1.6.14 Port E I/O Pins (PTE7–PTE0) . . . . . . . . . . . . . . . . . . . . . . .47
1.6.15 Port F I/O Pins (PTF7–PTF0). . . . . . . . . . . . . . . . . . . . . . . .47
1.6.16 LCD Backplane and Frontplane
(BP0-BP2, BP3/FP0, FP1–FP10, FP27–FP32) . . . . . . .47
Table of Contents
Section 1. General Description
). . . . . . . . . . . . . . . . . . . . .44
DDA
) . . . . . . . . . . . . . . . . . . . . . . . . . . .45
LCD
). . . . . . . . . . . . . .45
REFH
) . . . . . . . . . . . . . .46
REFL
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Table of Contents 7
Table of Contents
Section 2. Memory Map
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .49
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .50
2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Section 3. Random-Access Memory (RAM)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Section 4. FLASH Memory (FLASH)
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .72
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .73
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.8 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
4.8.1 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .77
Section 5. Configuration Registers (CONFIG)
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.4 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .81
5.5 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .82
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
8 Table of Contents Freescale Semiconductor
Table of Contents
Section 6. Central Processor Unit (CPU)
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Section 7. Oscillator (OSC)
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.3 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.4 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .106
7.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .106
7.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .106
7.5.4 Internal RC Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . .106
7.5.5 CGM Oscillator Clock (CGMXCLK) . . . . . . . . . . . . . . . . . .106
7.5.6 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . .106
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
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7.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . .107
Section 8. Clock Generator Module (CGM)
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.4.1 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .114
8.4.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
8.4.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . .116
8.4.5 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . .116
8.4.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.4.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . .122
8.4.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . .122
8.4.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . .123
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
8.5.1 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . .124
8.5.2 PLL Analog Power Pin (V
8.5.3 PLL Analog Ground Pin (V
) . . . . . . . . . . . . . . . . . . . . . .124
DDA
) . . . . . . . . . . . . . . . . . . . . .124
SSA
8.5.4 Oscillator Output Frequency Signal (CGMXCLK) . . . . . . .124
8.5.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . .124
8.5.6 CGM VCO Clock Output (CGMVCLK). . . . . . . . . . . . . . . .125
8.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . .125
8.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .125
8.6 CGM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .128
8.6.3 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . .130
8.6.4 PLL VCO Range Select Register. . . . . . . . . . . . . . . . . . . .131
8.6.5 PLL Reference Divider Select Register . . . . . . . . . . . . . . .132
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
10 Table of Contents Freescale Semiconductor
Table of Contents
8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
8.8.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .134
8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .135
8.9.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .135
8.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .135
8.9.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Section 9. System Integration Module (SIM)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .142
9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
9.3.2 Clock Start-up from POR or LVI Reset. . . . . . . . . . . . . . . .143
9.3.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . .144
9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .144
9.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . .145
9.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . .147
9.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.4.2.4 Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .148
9.4.2.6 Monitor Mode Entry Module Reset (MODRST) . . . . . . .148
9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .149
9.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . .149
9.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .149
9.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
9.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
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9.6.1.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .153
9.6.1.4 Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . .153
9.6.1.5 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . .155
9.6.1.6 Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . .155
9.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
9.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
9.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .156
9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
9.8 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
9.8.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .160
9.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .161
9.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .162
Section 10. Monitor ROM (MON)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
10.4.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .167
10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10.4.3 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10.4.5 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
10.6 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
10.6.1 PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
10.6.2 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
10.6.3 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
10.6.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
10.6.5 MON_ERARNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
10.6.6 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
10.6.7 EE_WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
10.6.8 EE_READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
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Section 11. Timer Interface Module (TIM)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
11.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
11.5.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . .199
11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .200
11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .201
11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .201
11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .202
11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .203
11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
11.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .206
11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
11.9.1 TIM Clock Pins (PTD4/KBI4/T1CLK, PTD5/KBI5/T2CLK) .207
11.9.2 TIM Channel I/O Pins (PTB2/T1CH0, PTB3/T1CH1,
PTB4/T2CH0, PTB5/T2CH1) . . . . . . . . . . . . . . . . . . . .207
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
11.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .208
11.10.2 TIM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .210
11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .211
11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .212
11.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .215
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Section 12. Real Time Clock (RTC)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
12.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
12.5.1 Time Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
12.5.2 Calendar Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
12.5.3 Alarm Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
12.5.4 Chronograph Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .223
12.5.5 Timebase Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
12.6 RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
12.7 RTC Clock Calibration and Compensation. . . . . . . . . . . . . . .225
12.7.1 Calibration Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
12.8 RTC Register and Bit Write Protection. . . . . . . . . . . . . . . . . .227
12.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
12.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
12.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
12.10 RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
12.10.1 RTC Calibration Control Register (RTCCOMR). . . . . . . . .231
12.10.2 RTC Calibration Data Register (RTCCDAT) . . . . . . . . . . .233
12.10.3 RTC Control Register 1 (RTCCR1) . . . . . . . . . . . . . . . . . .234
12.10.4 RTC Control Register 2 (RTCCR2) . . . . . . . . . . . . . . . . . .235
12.10.5 RTC Status Register (RTCSR). . . . . . . . . . . . . . . . . . . . . .237
12.10.6 Alarm Minute and Hour Registers (ALMR and ALHR). . . .240
12.10.7 Second Register (SECR) . . . . . . . . . . . . . . . . . . . . . . . . . .241
12.10.8 Minute Register (MINR) . . . . . . . . . . . . . . . . . . . . . . . . . . .241
12.10.9 Hour Register (HRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
12.10.10 Day Register (DAYR). . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
12.10.11 Month Register (MTHR). . . . . . . . . . . . . . . . . . . . . . . . . . .243
12.10.12 Year Register (YRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
12.10.13 Day-Of-Week Register (DOWR) . . . . . . . . . . . . . . . . . . . .244
12.10.14 Chronograph Data Register (CHRR) . . . . . . . . . . . . . . . . .244
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Section 13. Infrared Serial Communications
Interface Module (IRSCI)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
13.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
13.5 IRSCI Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
13.6 Infrared Functional Description. . . . . . . . . . . . . . . . . . . . . . . .250
13.6.1 Infrared Transmit Encoder . . . . . . . . . . . . . . . . . . . . . . . . .251
13.6.2 Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . .251
13.7 SCI Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . .252
13.7.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
13.7.2 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
13.7.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
13.7.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .255
13.7.2.3 Break Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
13.7.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
13.7.2.5 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .257
13.7.3 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
13.7.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
13.7.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .259
13.7.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
13.7.3.4 Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
13.7.3.5 Baud Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . .261
13.7.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
13.7.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
13.7.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
13.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
13.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
13.9 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .267
13.10 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
13.10.1 PTB0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . .267
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13.10.2 PTB1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . .267
13.11 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
13.11.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
13.11.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
13.11.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
13.11.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
13.11.5 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . .280
13.11.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
13.11.7 SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . .282
13.11.8 SCI Infrared Control Register. . . . . . . . . . . . . . . . . . . . . . .285
Section 14. Serial Peripheral Interface Module (SPI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
14.4 Pin Name Conventions and I/O Register Addresses . . . . . . .289
14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
14.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
14.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
14.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
14.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .293
14.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .294
14.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .296
14.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .297
14.7 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . .299
14.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
14.8.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
14.8.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
14.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
14.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
14.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
14.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
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14.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
14.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .308
14.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
14.13.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .309
14.13.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .309
14.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
14.13.4 SS (Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
14.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
14.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
14.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
14.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .314
14.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
Section 15. Multi-Master IIC Interface (MMIIC)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
15.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
15.5 Multi-Master IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .321
15.5.1 Multi-Master IIC Address Register (MMADR) . . . . . . . . . .321
15.5.2 Multi-Master IIC Control Register (MMCR) . . . . . . . . . . . .323
15.5.3 Multi-Master IIC Master Control Register (MIMCR) . . . . . .324
15.5.4 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . .326
15.5.5 Multi-Master IIC Data Transmit Register (MMDTR). . . . . .328
15.5.6 Multi-Master IIC Data Receive Register (MMDRR) . . . . . .329
15.6 Programming Considerations. . . . . . . . . . . . . . . . . . . . . . . . .330
Section 16. Analog-to-Digital Converter (ADC)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
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16.4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
16.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
16.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
16.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
16.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .338
16.4.5 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
16.4.6 Monotonicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
16.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
16.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
16.7.1 ADC Voltage In (V
16.7.2 ADC Analog Power Pin (V
16.7.3 ADC Analog Ground Pin (V
16.7.4 ADC Voltage Reference High Pin (V
16.7.5 ADC Voltage Reference Low Pin (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . .341
ADIN
) . . . . . . . . . . . . . . . . . . . . .341
DDA
). . . . . . . . . . . . . . . . . . . . .341
SSA
). . . . . . . . . . . . .341
REFH
) . . . . . . . . . . . . .341
REFL
16.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
16.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .342
16.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
16.8.3 ADC Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . .346
Section 17. Liquid Crystal Display (LCD) Driver
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
17.4 Pin Name Conventions and I/O Register Addresses . . . . . . .350
17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
17.5.1 LCD Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
17.5.2 LCD Voltages (V
17.5.3 LCD Cycle Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
17.5.4 Fast Charge and Low Current . . . . . . . . . . . . . . . . . . . . . .356
17.5.5 Contrast Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
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LCD
, V
LCD1
, V
LCD2
, V
) . . . . . . . . . . .355
LCD3
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17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
17.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
17.7.1 BP0–BP3 (Backplane Drivers). . . . . . . . . . . . . . . . . . . . . .359
17.7.2 FP0–FP32 (Frontplane Drivers). . . . . . . . . . . . . . . . . . . . .361
17.8 Seven Segment Display Connection . . . . . . . . . . . . . . . . . . .365
17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
17.9.1 LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . .368
17.9.2 LCD Clock Register (LCDCLK) . . . . . . . . . . . . . . . . . . . . .370
17.9.3 LCD Data Registers (LDAT1–LDAT17) . . . . . . . . . . . . . . .372
Section 18. Input/Output (I/O) Ports
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
18.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
18.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .380
18.3.2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . .381
18.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
18.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .383
18.4.2 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . .385
18.4.3 Port B LED Control Register (LEDB) . . . . . . . . . . . . . . . . .386
18.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
18.5.1 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .387
18.5.2 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . .388
18.5.3 Port C LED Control Register (LEDC). . . . . . . . . . . . . . . . .389
18.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390
18.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .390
18.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . .392
18.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
18.7.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . .394
18.7.2 Data Direction Register E (DDRE). . . . . . . . . . . . . . . . . . .395
18.7.3 Port E LED Control Register (LEDE) . . . . . . . . . . . . . . . . .396
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18.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
18.8.1 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . .397
18.8.2 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . .398
18.8.3 Port F LED Control Register (LEDF) . . . . . . . . . . . . . . . . .399
Section 19. External Interrupt (IRQ)
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
19.4.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
19.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .405
19.6 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .405
Section 20. Keyboard Interrupt Module (KBI)
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
20.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
20.5.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
20.6 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . .412
20.6.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . .412
20.6.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .413
20.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
20.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
20.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
20.8 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .414
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Section 21. Computer Operating Properly (COP)
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
21.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
21.4.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
21.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
21.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
21.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
21.4.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
21.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
21.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
21.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .418
21.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
21.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
21.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
21.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
21.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
21.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
21.9 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . .420
Section 22. Low-Voltage Inhibit (LVI)
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421
22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
22.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
22.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .424
22.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .424
22.4.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
22.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
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22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426
22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426
22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426
Section 23. Break Module (BRK)
23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428
23.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .430
23.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .430
23.4.3 TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . .430
23.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .430
23.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430
23.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430
23.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
23.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
23.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .431
23.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .432
23.6.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .432
23.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .434
Section 24. Electrical Specifications
24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435
24.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .436
24.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .437
24.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
24.6 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .438
24.7 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .439
24.8 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .440
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24.9 3.3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441
24.10 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .441
24.11 3.3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . .442
24.12 5V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .443
24.13 3.3V ADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .444
24.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .445
24.15 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . .445
24.16 5V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .446
24.17 3.3V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .447
24.18 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .450
Section 25. Mechanical Specifications
25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451
25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451
25.3 64-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . .452
25.4 64-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . .453
25.5 80-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . .454
25.6 80-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . .455
Section 26. Ordering Information
26.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457
26.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457
26.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457
Appendix A. MC68HC908LK24
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459
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A.3 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .460
A.4 Low-Voltage Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .460
A.5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461
A.5.1 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .461
A.5.2 3.3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .461
A.5.3 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . .462
A.5.4 3.3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . .462
A.6 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .462
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Figure Title Page
1-1 MC68HC908LJ24 Block Diagram. . . . . . . . . . . . . . . . . . . . . . .41
1-2 80-Pin QFP and LQFP Pin Assignment . . . . . . . . . . . . . . . . . .42
1-3 64-pin QFP and LQFP Pin Assignment . . . . . . . . . . . . . . . . . .43
1-4 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2-2 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .52
4-1 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .70
4-2 FLASH Control Regist er (FLCR) . . . . . . . . . . . . . . . . . . . . . . .71
4-3 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . . .75
4-4 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . .77
List of Figures
5-1 CONFIG Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . .80
5-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .81
5-3 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .82
6-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6-3 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .90
7-1 Oscillator Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .104
8-1 CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8-2 CGM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .113
8-3 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .123
8-4 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .126
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Figure Title Page
8-5 PLL Bandwidth Control Register (PBWCR) . . . . . . . . . . . . . .129
8-6 PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . .130
8-7 PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . .130
8-8 PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . .131
8-9 PLL Reference Divider Select Register (PMDS) . . . . . . . . . .132
8-10 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .142
9-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
9-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9-6 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
9-8 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9-9 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9-11 Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . . . .152
9-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .153
9-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .155
9-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .155
9-15 Wait Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
9-16 Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . . .158
9-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .158
9-18 Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
9-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .159
9-20 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .160
9-21 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .161
9-22 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .162
10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
10-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .170
10-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10-4 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
10-6 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
26 List of Figures Freescale Semiconductor
List of Figures
Figure Title Page
10-7 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .176
10-8 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .177
10-9 Data Block Format for ROM-Resident Routines. . . . . . . . . . .180
10-10 EE_WRITE FLASH Memory Usage. . . . . . . . . . . . . . . . . . . .189
11-1 TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
11-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .197
11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .202
11-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .208
11-5 TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . .210
11-6 TIM Counter Registers Low (TCNTL). . . . . . . . . . . . . . . . . . .211
11-7 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .211
11-8 TIM Counter Modulo Register Low (TMODL). . . . . . . . . . . . .211
11-9 TIM Channel 0 Status and Control Register (TSC0) . . . . . . .212
11-10 TIM Channel 1 Status and Control Register (TSC1) . . . . . . .212
11-11 CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
11-12 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . .216
11-13 TIM Channel 0 Register Low (TCH0L). . . . . . . . . . . . . . . . . .216
11-14 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . .216
11-15 TIM Channel 1 Register Low (TCH1L). . . . . . . . . . . . . . . . . .216
12-1 RTC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .219
12-2 RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
12-3 RTC Clock Calibration and Compensation. . . . . . . . . . . . . . .225
12-4 1-Hz Clock Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .227
12-5 RTC Write Protect State Diagram. . . . . . . . . . . . . . . . . . . . . .228
12-6 RTC Calibration Control Register (RTCCOMR) . . . . . . . . . . .231
12-7 RTC Calibration Data Register (RTCCDAT). . . . . . . . . . . . . .233
12-8 RTC Control Register 1 (RTCCR1) . . . . . . . . . . . . . . . . . . . .234
12-9 RTC Control Register 2 (RTCCR2) . . . . . . . . . . . . . . . . . . . .235
12-10 RTC Status Register (RTCSR). . . . . . . . . . . . . . . . . . . . . . . .237
12-11 Alarm Minute Register (ALMR). . . . . . . . . . . . . . . . . . . . . . . .240
12-12 Alarm Hour Register (ALHR) . . . . . . . . . . . . . . . . . . . . . . . . .240
12-13 Second Register (SECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
12-14 Minute Register (MINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
12-15 Hour Register (HRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor List of Figures 27
List of Figures
Figure Title Page
12-16 Day Register (DAYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
12-17 Month Register (MTHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
12-18 Year Register (YRR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
12-19 Day-Of-Week Register (DOWR). . . . . . . . . . . . . . . . . . . . . . .244
12-20 Chronograph Data Register (CHRR) . . . . . . . . . . . . . . . . . . .244
13-1 IRSCI I/O Registers Summary . . . . . . . . . . . . . . . . . . . . . . . .248
13-2 IRSCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
13-3 Infrared Sub-Module Diagram . . . . . . . . . . . . . . . . . . . . . . . .250
13-4 Infrared SCI Data Example. . . . . . . . . . . . . . . . . . . . . . . . . . .251
13-5 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .252
13-6 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
13-7 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
13-8 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .258
13-9 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
13-10 Slow Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
13-11 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
13-12 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .269
13-13 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .272
13-14 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .274
13-15 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .276
13-16 Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
13-17 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .280
13-18 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . .281
13-19 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .282
13-20 SCI Infrared Control Register (SCIRCR) . . . . . . . . . . . . . . . .285
14-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .289
14-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .290
14-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . .291
14-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .295
14-5 CPHA/SS
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
14-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .296
14-7 Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . . . .298
14-8 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . . .299
14-9 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .301
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
28 List of Figures Freescale Semiconductor
List of Figures
Figure Title Page
14-10 Clearing SPRF When OVRF Interrupt Is Not Enabled. . . . . .302
14-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .305
14-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
14-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .312
14-14 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .314
14-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .317
15-1 MMIIC I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .321
15-2 Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . .321
15-3 Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . .323
15-4 Multi-Master IIC Master Control Register (MIMCR) . . . . . . . .324
15-5 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . .326
15-6 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . .328
15-7 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . .329
15-8 Data Transfer Sequences for Master/Slave
Transmit/Receive Modes. . . . . . . . . . . . . . . . . . . . . . . . . .331
16-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .335
16-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
16-3 8-Bit Truncation Mode Error . . . . . . . . . . . . . . . . . . . . . . . . . .339
16-4 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .342
16-5 ADRH and ADRL in 8-Bit Truncated Mode. . . . . . . . . . . . . . .344
16-6 ADRH and ADRL in Right Justified Mode. . . . . . . . . . . . . . . .344
16-7 ADRH and ADRL in Left Justified Mode. . . . . . . . . . . . . . . . .345
16-8 ADRH and ADRL in Left Justified Sign Data Mode . . . . . . . .345
16-9 ADC Clock Control Register (ADCLK) . . . . . . . . . . . . . . . . . .346
17-1 LCD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .351
17-2 LCD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
17-3 Simplified LCD Schematic (1/3 Duty, 1/3 Bias) . . . . . . . . . . .354
17-4 Fast Charge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
17-5 Static LCD Backplane Driver Waveform. . . . . . . . . . . . . . . . .359
17-6 1/3 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . .359
17-7 1/4 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . .360
17-8 Static LCD Frontplane Driver Waveforms. . . . . . . . . . . . . . . .361
17-9 1/3 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . .362
17-10 1/4 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . .363
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor List of Figures 29
List of Figures
Figure Title Page
17-11 1/4 Duty LCD Frontplane Driver Waveforms (continued) . . . .364
17-12 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . . .365
17-13 BP0–BP2 and FP0–FP2 Output Waveforms for
7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . .366
17-14 "f" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . .367
17-15 "e" Segment Voltage Waveform. . . . . . . . . . . . . . . . . . . . . . .367
17-16 LCD Control Register (L CDCR) . . . . . . . . . . . . . . . . . . . . . . .368
17-17 LCD Clock Register (LCDCLK). . . . . . . . . . . . . . . . . . . . . . . .370
17-18 LCD Data Registers 1–17 (LDAT1–LDAT17). . . . . . . . . . . . .372
18-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .376
18-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .380
18-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .381
18-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
18-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .383
18-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .385
18-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
18-8 Port B LED Control Register (LEDB) . . . . . . . . . . . . . . . . . . .386
18-9 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .387
18-10 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . . .388
18-11 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
18-12 Port C LED Control Register (LEDC) . . . . . . . . . . . . . . . . . . .389
18-13 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .390
18-14 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . .392
18-15 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
18-16 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .394
18-17 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .395
18-18 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
18-19 Port E LED Control Register (LEDE) . . . . . . . . . . . . . . . . . . .396
18-20 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . .397
18-21 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . .398
18-22 Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
18-23 Port F LED Control Register (LEDF) . . . . . . . . . . . . . . . . . . .399
19-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .403
19-2 IRQ I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . .403
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
30 List of Figures Freescale Semiconductor
List of Figures
Figure Title Page
19-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .406
20-1 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .408
20-2 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . .409
20-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .412
20-4 Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . .413
21-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
21-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .418
21-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .419
22-1 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .422
22-2 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .422
23-1 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .429
23-2 Break Module I/O Register Summary. . . . . . . . . . . . . . . . . . .429
23-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . .431
23-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .432
23-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .432
23-6 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .433
23-7 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .434
24-1 Typical Internal Oscillator Frequency . . . . . . . . . . . . . . . . . . .442
24-2 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .448
24-3 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .449
25-1 64-Pin Low-Profile Quad Flat Pack (Case No. 840F). . . . . . .452
25-2 64-Pin Quad Flat Pack (Case No. 840B) . . . . . . . . . . . . . . . .453
25-3 80-Pin Low-Profile Quad Flat Pack (Case No. 917). . . . . . . .454
25-4 80-Pin Quad Flat Pack (Case No. 841B) . . . . . . . . . . . . . . . .455
A-1 MC68HC908LK24 Crystal Oscillator Connection. . . . . . . . . 460
A-2 MC68HC908LK24 Configuration Register 1 (CONFIG1) . . . 460
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor List of Figures 31
List of Figures
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
32 List of Figures Freescale Semiconductor
Data Sheet — MC68HC908LJ24
Table Title Page
2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4-1 FLASH Block Protect Register to Physical Address. . . . . . . . .78
5-1 LVI Trip Point Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6-2 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
8-1 Numeric Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
8-3 VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .128
8-2 PRE 1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . .128
List of Tables
9-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9-3 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
10-1 Monitor Mode Signal Requirements and Options. . . . . . . . . .168
10-2 Mode Differences (Vectors) . . . . . . . . . . . . . . . . . . . . . . . . . .170
10-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .172
10-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .173
10-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .174
10-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .174
10-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .175
10-8 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .175
10-9 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .176
10-10 Summary of ROM-Resident Routines . . . . . . . . . . . . . . . . . .179
10-11 PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
10-12 ERARNGE Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
10-13 LDRNGE Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
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Freescale Semiconductor List of Tables 33
List of Tables
Table Title Page
10-14 MON_PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . .185
10-15 MON_ERARNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . .186
10-16 ICP_LDRNGE Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
10-17 EE_WRITE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
10-18 EE_READ Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
11-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
11-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .214
12-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
12-2 Compensation Algorithm for Different Values of E. . . . . . . . .226
12-3 Write-Protected RTC Registers and Bits . . . . . . . . . . . . . . . .227
12-4 CALOUT Pin Output Option . . . . . . . . . . . . . . . . . . . . . . . . . .232
13-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
13-2 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
13-3 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
13-4 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
13-5 SCI Pin Functions (Standard and Infrared). . . . . . . . . . . . . . .268
13-6 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .271
13-7 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .282
13-8 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
13-9 SCI Baud Rate Selection Examples. . . . . . . . . . . . . . . . . . . .284
13-10 Infrared Narrow Pulse Selection. . . . . . . . . . . . . . . . . . . . . . .285
14-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
14-2 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
14-3 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
14-4 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .316
15-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
15-2 Baud Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
16-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
16-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
16-3 ADC Mode Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
34 List of Tables Freescale Semiconductor
List of Tables
Table Title Page
17-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
17-3 LCD Bias Voltage Control. . . . . . . . . . . . . . . . . . . . . . . . . . . .369
17-2 Resistor Ladder Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .369
17-4 Fast Charge Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . .370
17-5 LCD Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .371
17-6 LCD Waveform Base Clock Selection . . . . . . . . . . . . . . . . . .371
18-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .378
18-2 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
18-3 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
18-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
18-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
18-6 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
18-7 Port F Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
20-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
22-1 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .425
22-2 LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
24-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .436
24-2 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .437
24-3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
24-4 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .438
24-5 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .439
24-6 5V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .440
24-7 3.3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441
24-8 5V Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .441
24-9 3.3V Oscillator Specifications. . . . . . . . . . . . . . . . . . . . . . . . .442
24-10 5V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .443
24-11 3.3V ADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .444
24-12 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .445
24-13 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . .445
24-14 5V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .446
24-15 3.3V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .447
24-16 FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . .450
26-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor List of Tables 35
List of Tables
Table Title Page
A-1 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .461
A-2 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .461
A-3 5V Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .462
A-4 3.3V Oscillator Specifications. . . . . . . . . . . . . . . . . . . . . . . . .462
A-5 MC68HC908LK24 Order Numbers. . . . . . . . . . . . . . . . . . . . .462
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
36 List of Tables Freescale Semiconductor
Data Sheet — MC68HC908LJ24
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
1.6.1 Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . .44
1.6.2 Analog Power Supply Pin (V
1.6.3 LCD Bias Voltage (V
1.6.4 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .45
1.6.5 External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .45
1.6.6 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .45
1.6.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .45
1.6.8 ADC Voltage High Reference Pin (V
1.6.9 ADC Voltage Low Reference Pin (V
1.6.10 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . .46
1.6.11 Port B I/O Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . .46
1.6.12 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . .46
1.6.13 Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . .46
1.6.14 Port E I/O Pins (PTE7–PTE0) . . . . . . . . . . . . . . . . . . . . . . .47
1.6.15 Port F I/O Pins (PTF7–PTF0). . . . . . . . . . . . . . . . . . . . . . . .47
1.6.16 LCD Backplane and Frontplane
(BP0-BP2, BP3/FP0, FP1–FP10, FP27–FP32) . . . . . . .47
Section 1. General Description
). . . . . . . . . . . . . . . . . . . . .44
DDA
) . . . . . . . . . . . . . . . . . . . . . . . . . . .45
LCD
). . . . . . . . . . . . . .45
REFH
) . . . . . . . . . . . . . .46
REFL
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor General Description 37
General Description
1.2 Introduction
The MC68HC908LJ24 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
1.3 Features
Features of the MC68HC908LJ24 include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
– 8-MHz at 5V operating voltage
– 4-MHz at 3.3V operating voltage
• 32.768kHz crystal oscillator clock input with 32MHz internal PLL
• Optional continuous crystal oscillator operation in stop mode
• 24K-bytes user program FLASH memory with security1 feature
• 768 bytes of on-chip RAM
• Up to 48 general-purpose input/output (I/O) pins:
– H igh current 15mA sink capability on 30 pins
• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2)
with selectable input capture, output compare, PWM capability on
each channel, and external clock input option (T1CLK and T2CLK)
• Real time clock (RTC) with:
– Clock, calendar, alarm, and chronograph functions
– Selectable periodic interrupt requests for seconds, minutes,
hours, days, 2-Hz, 4-Hz, 8-Hz, 16-Hz, and 128-Hz
1. No security feature is absolutely secure. However, Freescale strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
38 General Description Freescale Semiconductor
General Description
Features
– Temperature drift compensation by user software and external
temperature sensor with temperature drift profile from crystal
vendor
• Serial communications interface module (SCI) with infrared (IR)
encoder/decoder
• Inter-IC Bus interface module (IIC)
• Serial peripheral interface module (SPI)
•IRQ external interrupt pin with integrated pullup
• 8-bit keyboard wakeup port with programmable pullup
• 4/3 backplanes and static with maximum 32/33 frontplanes liquid
crystal display (LCD) driver
• 6-channel, 10-bit successive approximation analog-to-digital
converter (ADC)
• Resident routines for in-circuit programming and EEPROM
emulation
• Low-power design (fully static with stop and wait modes)
• Master reset pin (with integrated pullup) and power-on reset
• Spike filter protection for EMC performance enhancement
• System protection features
– Optional computer operating properly (COP) reset, driven by
internal RC oscillator
– Low-voltage detection with optional reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
• 80-pin quad flat pack (QFP), 80-pin low-profile quad flat pack
(LQFP), 64-pin quad flat pack (QFP), and 64-pin low-profile quad
flat pack (LQFP)
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor General Description 39
General Description
Features of the CPU08 include the following:
• Specific features of the MC68HC908LJ24 in 64-pin packages are:
– 40 general-purpose I/Os only
– H igh current 15-mA sink capability on 22 pins
– 4 /3 backplanes and static with maximum 26 or 27 frontplanes
LCD driver
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit Index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
1.4 MCU Block Diagram
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
Figure 1-1 shows the structure of the MC68HC908LJ24.
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
40 General Description Freescale Semiconductor
M68HC08 CPU
General Description
MCU Block Diagram
INTERNAL BUS
CPU
REGISTERS
CONTROL AND STATUS REGISTERS — 128 BYTES
USER FLASH — 24,576 BYTES
USER RAM — 768 BYTES
MONITOR ROM — 959 BYTES
USER FLASH VECTOR SPACE — 48 BYTES
* RST
* IRQ
ARITHMETIC/LOGIC
UNIT (ALU)
SYSTEM INTEGRATION
MODULE
EXTERNAL INTERRUPT
MODULE
COMPUTER OPERATING
PROPERLY MODULE
KEYBOARD INTERRUPT
MODULE
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
2-CHANNEL TIMER INTERFACE
MODULE 1
2-CHANNEL TIMER INTERFACE
MODULE 2
REAL TIME CLOCK
MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
DDRD
PORTD
PTD7/KBI7/SDA
PTD6/KBI6/SCL
PTD5/KBI5/T2CLK**
PTD4/KBI4/T1CLK**
PTD3/SPSCK/CALOUT
PTD2/MOSI
PTD1/MISO
PTD0/SS
/CALIN
POWER-ON RESET
MODULE
LIQUID CRYSTAL DISPLAY
DRIVER MODULE
VDDA
POWER
VSS
Figure 1-1. MC68HC908LJ24 Block Diagram
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor General Description 41
General Description
1.5 Pin Assignments
BP2
BP1
BP0
FP32
FP31
PTB4/T2CH0
PTB3/T1CH1
PTB2/T1CH0
PTB1/RxD
PTB0/TxDNCCGMXFC
OSC2
OSC1
PTD5/KBI5/T2CLK
PTD6/KBI6/SCL
PTD7/KBI7/SDA
FP0/BP3
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP8
PTF7
PTF6
FP9
FP10
VREFL
VREFH
PTB7/ADC5
PTB6/ADC4
PTA7/ADC3
PTA6/ADC2
PTA5/ADC1
PTA4/ADC0
FP30
FP29
PTA3/KBI3
PTA2/KBI2
PTA1/KBI1
PTA0/KBI0
FP28
FP27
Figure 1-2. 80-Pin QFP and LQFP Pin Assignment
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
42 General Description Freescale Semiconductor
FP0/BP3
General Description
Pin Assignments
PTB2/T1CH0
PTB1/RxD
PTB0/TxD
CGMXFC
OSC2
OSC1
VSS
VDD
50
VDDA
49
48
VREFL
PTD4/KBI4/T1CLK
BP2
BP1
BP0
PTB5/T2CH1
PTB4/T2CH0
PTB3/T1CH1
64
63
62
61
60
59
58
57
56
55
54
53
52
1
51
PTD5/KBI5/T2CLK
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP8
PTD6/KBI6/SCL
PTD7/KBI7/SDA
FP9
FP10
PTE0/FP11
PTE1/FP12
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
Pins not available on 64-LQFP package:
PTF7 FP32
PTF6 FP31
PTF5 FP30
PTF4 FP29
PTF3 FP28
PTF2 FP27
PTF1
PTF0 VLCD
Internal PTF7–PTF0 pads are connected to VSS.
Internal FP32–FP27 pads are unconnected.
Internal VLCD pad is connected to VDD.
19
20
21
22
23
24
25
26
27
28
29
30
31
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
VREFH
PTB7/ADC5
PTB6/ADC4
PTA7/ADC3
PTA6/ADC2
PTA5/ADC1
PTA4/ADC0
PTA3/KBI3
PTA2/KBI2
PTA1/KBI1
PTA0/KBI0
PTC7/FP26
PTC6/FP25
PTC5/FP24
PTD0/SS/CALIN
IRQ
RST
PTE3/FP14
PTE2/FP13
PTE4/FP15
PTE5/FP16
PTE6/FP17
PTE7/FP18
PTC0/FP19
PTD2/MOSI
PTC1/FP20
PTD1/MISO
PTC2/FP21
PTC3/FP22
PTC4/FP23
PTD3/SPSCK/CALOUT
Figure 1-3. 64-pin QFP and LQFP Pin Assignment
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor General Description 43
General Description
1.6 Pin Functions
Description of pin functions are provided here.
1.6.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels. VSS must be grounded for
proper MCU operation.
1.6.2 Analog Power Supply Pin (V
V
DDA
V
DDA
immunity, route V
as close as possible to the package (see Figure 1-4).
)
DDA
is the voltage supply for the analog parts of the MCU. Connect the
pin to the same voltage potential as VDD. For maximum noise
via a separate trace and place bypass capacitors
DDA
MCU
V
DD
0.1 µF
C1(a)
+
C2(a)
V
NOTE: Component values shown
DD
represent typical applications.
V
SS
0.1 µF
C1(b)
+
C2(b)
V
DDA
V
DD
Figure 1-4. Power Supply Bypassing
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
44 General Description Freescale Semiconductor
General Description
Pin Functions
1.6.3 LCD Bias Voltage (V
V
LCD
V
LCD
)
LCD
is the bias voltage supply for the LCD driver module. Connect the
pin to the same voltage potential as VDD. For maximum noise
immunity, route V
as close as possible to the package. See Section 17. Liquid Crystal
Display (LCD) Driver.
1.6.4 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. The OSC1 pin contains a schmitt-trigger and a spike filter for
improved EMC performance. See Section 7. Oscillator (OSC).
1.6.5 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known start-up state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. A Schmitt-trigger and a spike filter
is associated with this pin so that the device is more robust to EMC
noise. This pin also contains an internal pullup resistor. See 9.4 Reset
and System Initialization.
via a separate trace and place bypass capacitors
LCD
1.6.6 External Interrupt Pin (IRQ)
is an asynchronous external interrupt pin. This pin contains an
IRQ
internal pullup resistor. See Section 19. External Interrupt (IRQ).
1.6.7 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM.
See 8.4.9 CGM External Connections.
1.6.8 ADC Voltage High Reference Pin (V
V
is the voltage input pin for the ADC voltage high reference.
REFH
See 16.7.4 ADC Voltage Reference High Pin (V
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor General Description 45
REFH
)
).
REFH
General Description
1.6.9 ADC Voltage Low Reference Pin (V
V
is the voltage input pin for the ADC voltage low reference.
REFL
REFL
See 16.7.5 ADC Voltage Reference Low Pin (V
1.6.10 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are special function, bidirectional port pins. See 18.3 Port A.
PTA7/ADC3–PTA4/ADC0 are shared with ADC, and
PTA3/KBI3–PTA0/KBI0 are shared with the KBI module.
1.6.11 Port B I/O Pins (PTB7–PTB0)
PTB7–PTB0 are special function, bidirectional port pins, with high
current sink capability on PTB5–PTB0. See 18.4 Port B.
PTB1/RxD–PTB0/TxD are shared with the SCI module,
PTB5/T2CH1–PTB4/T2CH0 are shared with the TIM2,
PTB3/T1CH1–PTB2/T1CH0 are shared with the TIM1,
PTB7/ADC5–PTB6/ADC4 are shared with the ADC.
)
).
REFL
1.6.12 Port C I/O Pins (PTC7–PTC0)
PTC7–PTC0 are special function, bidirectional port pins, with high
current sink capability. See 18.5 Port C.
PTC7/FP26–PTC0/FP19 are shared with the LCD frontplane drivers.
1.6.13 Port D I/O Pins (PTD7–PTD0)
PTD7–PTD0 are special function, bidirectional port pins.
PTD7/KBI7/SDA–PTD6/KBI6/SCL are shared with the KBI and IIC
modules. See 18.6 Port D.
PTD5/KBI5/T2CLK–PTD4/KBI4/T1CLK are shared with the KBI, TIM1,
and TIM2 modules.
PTD3/SPSCK/CALOUT–PTD0/SS
RTC modules.
/CALIN are shared with the SPI and
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
46 General Description Freescale Semiconductor
General Description
Pin Functions
1.6.14 Port E I/O Pins (PTE7–PTE0)
PTE7–PTE0 are special function, bidirectional port pins, with high
current sink capability. See 18.7 Port E.
PTE7/FP18–PTE0/FP11 are shared with the LCD frontplane drivers.
1.6.15 Port F I/O Pins (PTF7–PTF0)
PTF7–PTF0 are general purpose bidirectional port pins with high current
sink capability. See 18.8 Port F.
1.6.16 LCD Backplane and Frontplane (BP0-BP2, BP3/FP0, FP1–FP10, FP27–FP32)
BP0–BP2 are the LCD backplane driver pins and FP1– FP10 and
FP27–FP32 are the frontplane driver pins. FP0/BP3 is the shared driver
pin between FP0 and BP3.
See Section 17. Liquid Crystal Display (LCD) Driver.
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor General Description 47
General Description
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
48 General Description Freescale Semiconductor
Data Sheet — MC68HC908LJ24
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .49
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .50
2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
2.2 Introduction
The CPU08 can address 64k-bytes of memory space. The memory
map, shown in Figure 2-1, includes:
Section 2. Memory Map
• 24,576 bytes of user FLASH memory
• 768 bytes of random-access memory (RAM)
• 48 bytes of user-defined vectors
• 959 bytes of monitor ROM
2.3 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address
reset. In the memory map (Figure 2-1) and in register figures in this
document, unimplemented locations are shaded.
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 49
Memory Map
2.4 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU
operation. In Figure 2-2 and in register figures in this document,
reserved locations are marked with the word Reserved or with the
letter R.
2.5 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page
$0000–$007F. Additional I/O registers have the following addresses:
• $FE00; SIM break status register, SBSR
• $FE01; SIM reset status register, SRSR
• $FE03; SIM break flag control register, SBFCR
• $FE04; Interrupt status register 1, INT1
• $FE05; Interrupt status register 2, INT2
• $FE06; Interrupt status register 3, INT3
• $FE07; Reserved
• $FE08; FLASH control register, FLCR
• $FE09; Reserved
• $FE0A; Reserved
• $FE0B; Reserved
• $FE0C; break address register high, BRKH
• $FE0D; break address register low, BRKL
• $FE0E; break status and control register, BRKSCR
• $FE0F; LVI status register, LVISR
• $FFCF; FLASH block protect register, FLBPR (FLASH register)
• $FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2, Table 2-1 is a list of vector
locations.
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
50 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
$0000
↓
$007F
$0080
↓
$037F
$0380
↓
$8FFF
$9000
↓
$EFFF
$F000
↓
$FBFF
$FC00
↓
$FDFF
$FE00 SIM Break Status Register (SBSR)
$FE01 SIM Reset Status Register (SRSR)
$FE02 Reserved
$FE03 SIM Break Flag Control Register (SBFCR)
$FE04 Interrupt Status Register 1 (INT1)
$FE05 Interrupt Status Register 2 (INT2)
$FE06 Interrupt Status Register 3 (INT3)
$FE07 Reserved
$FE08 FLASH Control Register (FLCR)
$FE09 Reserved
$FE0A Reserved
$FE0B Reserved
$FE0C Break Address Register High (BRKH)
$FE0D Break Address Register Low (BRKL)
$FE0E Break Status and Control Register (BRKSCR)
$FE0F LVI Status Register (LVISR)
$FE10
↓
$FFCE
$FFCF FLASH Block Protect Register (FLBPR)
$FFD0
↓
$FFFF
I/O Registers
128 Bytes
RAM
768 Bytes
Unimplemented
35,968 Bytes
User FLASH Memory
24,576 Bytes
Unimplemented
3,072 Bytes
Monitor ROM 1
512 Bytes
Monitor ROM 2
447 Bytes
User Vectors
48 Bytes
Figure 2-1. Memory Map
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 51
Memory Map
Addr.Register Name Bit 7654321Bit 0
Read:
$0000
$0001
$0002
$0003
$0004
$0005
Port A Data Register
(PTA)
Port B Data Register
(PTB)
Port C Data Register
(PTC)
Port D Data Register
(PTD)
Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Data Direction Register C
$0006
Data Direction Register D
$0007
$0008
$0009
Port E Data Register
Data Direction Register E
Read:
(DDRC)
(DDRD)
(DDRE)
U = Unaffected X = Indeterminate
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
(PTE)
Reset:UUUUUUUU
Read:
Write:
Reset:00000000
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 13)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
52 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
$000A
$000B
$000C
$000D
$000E
$000F
Port F Data Register
(PTF)
Data Direction Register F
(DDRF)
Port-B LED Control
Register
(LEDB)
Port-C LED Control
Register
(LEDC)
Port-E LED Control
Register
(LEDE)
Port-F LED Control
Register
(LEDF)
Read:
PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
Write:
Reset:UUUUUUUU
Read:
DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Write:
Reset:00000000
Read: 0 0
LEDB5 LEDB4 LEDB3 LEDB2 LEDB1 LEDB0
Write:
Reset:00000000
Read:
LEDC7 LEDC6 LEDC5 LEDC4 LEDC3 LEDC2 LEDC1 LEDC0
Write:
Reset:00000000
Read:
LEDE7 LEDE6 LEDE5 LEDE4 LEDE3 LEDE2 LEDE1 LEDE0
Write:
Reset:00000000
Read:
LEDF7 LEDF6 LEDF5 LEDF4 LEDF3 LEDF2 LEDF1 LEDF0
Write:
Reset:00000000
$0010
$0011
$0012
$0013
Read:
SPI Control Register
(SPCR)
SPI Status and Control
Register
(SPSCR)
SPI Data Register
(SPDR)
SCI Control Register 1
(SCC1)
U = Unaffected X = Indeterminate
Write:
Reset:00101000
Read: SPRF
Write:
Reset:00001000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:UUUUUUUU
Read:
Write:
Reset:00000000
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 13)
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
ERRIE
LOOPS ENSCI
OVRF MODF SPTE
MODFEN SPR1 SPR0
0
M WAKE ILTY PEN PTY
= Unimplemented R = Reserved
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 53
Memory Map
Addr.Register Name Bit 7654321Bit 0
Read:
$0014
$0015
$0016
$0017
$0018
$0019
SCI Control Register 2
(SCC2)
SCI Control Register 3
(SCC3)
SCI Status Register 1
(SCS1)
SCI Status Register 2
(SCS2)
SCI Data Register
(SCDR)
SCI Baud Rate Register
(SCBR)
Write:
Reset:00000000
Read: R8
Write:
Reset:UU000000
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
Read: 000000BKFRPF
Write:
Reset: 0 0 0 00000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:UUUUUUUU
Read:
Write:
Reset:00000000
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
T8 DMARE DMATE ORIE NEIE FEIE PEIE
CKS
0
SCP1 SCP0 R SCR2 SCR1 SCR0
$001A
$001B
$001C
$001D
SCI Infrared Control
Register
(SCIRCR)
Keyboard Status and
Control Register
(KBSCR)
Keyboard Interrupt
Enable Register
(KBIER)
Configuration Register 2
(CONFIG2)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 13)
Read:
Write:
Reset:00000000
Read: 0000KEYF 0
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
†
Reset:0000000
R
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
PEE
000
STOP_
IRCDIS
STOP_
XCLKEN
DIV2CLK PCEH PCEL LVISEL1 LVISEL0
= Unimplemented R = Reserved
CKTST TNP1 TNP0 IREN
ACKK
IMASKK MODEK
††
††
1
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
54 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
IRQ Status and Control
$001E
$001F
† One-time writable register after each reset.
†† Reset by POR only.
$0020
$0021
$0022
Configuration Register 1
Timer 1 Status and Control
Register
(INTSCR)
(CONFIG1)
Register
(T1SC)
Timer 1 Counter
Register High
(T1CNTH)
Timer 1 Counter
Register Low
(T1CNTL)
Read: 0000IRQF0
Write: ACK
Reset:00000000
Read:
Write:
†
Reset:0000††0000
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
COPRS LVISTOP LVIRSTD LVIPWRD
00
TOIE TSTOP
IMASK MODE
0
SSREC STOP COPD
PS2 PS1 PS0
$0023
$0024
$0025
$0026
Timer 1 Counter Modulo
Register High
(T1MODH)
Timer 1 Counter Modulo
Register Low
(T1MODL)
Timer 1 Channel 0 Status
and Control Register
(T1SC0)
Timer 1 Channel 0
Register High
(T1CH0H)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 13)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:XXXXXXXX
= Unimplemented R = Reserved
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 55
Memory Map
Addr.Register Name Bit 7654321Bit 0
Timer 1 Channel 0
$0027
Timer 1 Channel 1 Status
$0028
$0029
$002A
Timer 2 Status and Control
$002B
$002C
Register Low
(T1CH0L)
and Control Register
(T1SC1)
Timer 1 Channel 1
Register High
(T1CH1H)
Timer 1 Channel 1
Register Low
(T1CH1L)
Register
(T2SC)
Timer 2 Counter
Register High
(T2CNTH)
Read:
Write:
Reset:XXXXXXXX
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Bit 7654321Bit 0
CH1IE
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TOIE TSTOP
0
MS1A ELS1B ELS1A TOV1 CH1MAX
00
PS2 PS1 PS0
$002D
$002E
$002F
$0030
Timer 2 Counter
Register Low
(T2CNTL)
Timer 2 Counter Modulo
Register High
(T2MODH)
Timer 2 Counter Modulo
Register Low
(T2MODL)
Timer 2 Channel 0 Status
and Control Register
(T2SC0)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 13)
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
= Unimplemented R = Reserved
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
56 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
$0031
$0032
$0033
$0034
$0035
$0036
Timer 2 Channel 0
Register High
(T2CH0H)
Timer 2 Channel 0
Register Low
(T2CH0L)
Timer 2 Channel 1 Status
and Control Register
(T2SC1)
Timer 2 Channel 1
Register High
(T2CH1H)
Timer 2 Channel 1
Register Low
(T2CH1L)
PLL Control Register
(PTCL)
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:00100000
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
CH1IE
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
PLLF
PLLIE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
PLLON BCS PRE1 PRE0 VPR1 VPR0
$0037
$0038
$0039
$003A
PLL Bandwidth Control
Register
(PBWC)
PLL Multiplier Select
Register High
(PMSH)
PLL Multiplier Select
Register Low
(PMSL)
PLL VCO Range Select
Register
(PMRS)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 13)
Read:
AUTO
Write:
Reset:00000000
Read: 0000
Write:
Reset:00000000
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
LOCK
ACQ
0000
R
MUL11 MUL10 MUL9 MUL8
= Unimplemented R = Reserved
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 57
Memory Map
Addr.Register Name Bit 7654321Bit 0
PLL Reference Divider
$003B
ADC Status and Control
$003C
$003D
$003E
$003F
$0040
ADC Data Register high
RTC Calibration Control
Select Register
(PMDS)
Register
(ADCSR)
(ADRH)
ADC Data Register low
(ADRL)
ADC Clock Control
Register
(ADCLK)
Register
(RTCCOMR)
Read: 0000
Write:
Reset:00000001
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset:00011111
Read: ADx ADx ADx ADx ADx ADx ADx ADx
Write:RRRRRRRR
Reset:00000000
Read: ADx ADx ADx ADx ADx ADx ADx ADx
Write:RRRRRRRR
Reset:00000000
Read:
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
Write:
Reset:00000100
Read: 0 0
CAL AUTOCAL OUTF1 OUTF0
Write: R R RTCWE1 RTCWE0
Reset:00000010
RDS3 RDS2 RDS1 RDS0
00
R
00
RTC Calibration Data
$0041
$0042
$0043
†† Reset by POR only.
RTC Control Register 1
RTC Control Register 2
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 13)
Register
(RTCCDAT)
(RTCCR1)
(RTCCR2)
Read: EOVL 0
Write:
Reset:U0 UUUUUU
Read:
Write:
Reset:00000000
Read:
Write: CHRCLR
Reset: U 0 0 0
ALMIE CHRIE DAYIE HRIE MINIE SECIE TB1IE TB2IE
0
COMEN
E5 E4 E3 E2 E1 E0
CHRE RTCE TBH
††
= Unimplemented R = Reserved
0000
000
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
58 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
Read: ALMF CHRF DAYF HRF MINF SECF TB1F TB2F
$0044
RTC Status Register
(RTCSR)
Write:
Reset:00000000
$0045
$0046
$0047
$0048
$0049
$004A
Alarm Minute register
(ALMR)
Alarm Hour register
(ALHR)
Second Register
(SECR)
Minute Register
(MINR)
Hour Register
(HRR)
Day Register
(DAYR)
Read: 0 0
AM5 AM4 AM3 AM2 AM1 AM0
Write:
Reset:0 0 UUUUUU
Read: 0 0 0
AH4 AH3 AH2 AH1 AH0
Write:
Reset:0 0 0UUUUU
Read: 0 0
SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
Write:
Reset:0 0 UUUUUU
Read: 0 0
MIN5 MIN4 MIN3 MIN2 MIN1 MIN0
Write:
Reset:0 0 UUUUUU
Read: 0 0 0
HR4 HR3 HR2 HR1 HR0
Write:
Reset:0 0 0UUUUU
Read: 0 0 0
DAY4 DAY3 DAY2 DAY1 DAY0
Write:
Reset:0 0 0UUUUU
$004B
$004C
$004D
Read: 0000
Month Register
(MTHR)
Year Register
Day-Of-Week Register
(DOWR)
U = Unaffected X = Indeterminate
Write:
Reset:0000UUUU
Read:
Write:
(YRR)
Reset:UUUUUUUU
Read: 00000
Write:
Reset:00000UUU
YR7 YR6 YR5 YR4 YR3 YR2 YR1 YR0
= Unimplemented R = Reserved
MTH3 MTH2 MTH1 MTH0
DOW2 DOW1 DOW0
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 13)
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 59
Memory Map
Addr.Register Name Bit 7654321Bit 0
Chronograph Data
$004E
$004F
$0050 Reserved
$0051
$0052
$0053
LCD Clock Register
LCD Control Register
LCD Data Register 1
LCD Data Register 2
Register
(CHRR)
(LCDCLK)
(LCDCR)
(LDAT1)
(LDAT2)
Read: 0 CHR6 CHR5 CHR4 CHR3 CHR2 CHR1 CHR0
Write:
Reset:00000000
Read: 0
Write:
Reset:00000000
Read:
RRRRRRRR
Write:
Reset:
Read:
LCDE
Write:
Reset:00000000
Read:
F1B3 F1B2 F1B1 F1B0 F0B3 F0B2 F0B1 F0B0
Write:
Reset:UUUUUUUU
Read:
F3B3 F3B2 F3B1 F3B0 F2B3 F2B2 F2B1 F2B0
Write:
Reset:UUUUUUUU
FCCTL1 FCCTL0 DUTY1 DUTY0 LCLK2 LCLK1 LCLK0
0
FC LC LCCON3 LCCON2 LCCON1 LCCON0
$0054
$0055
$0056
$0057
Read:
LCD Data Register 3
(LDAT3)
LCD Data Register 4
(LDAT4)
LCD Data Register 5
(LDAT5)
LCD Data Register 6
(LDAT6)
U = Unaffected X = Indeterminate
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
F5B3 F5B2 F5B1 F5B0 F4B3 F4B2 F4B1 F4B0
F7B3 F7B2 F7B1 F7B0 F6B3 F6B2 F6B1 F6B0
F9B3 F9B2 F9B1 F9B0 F8B3 F8B2 F8B1 F8B0
F11B3 F11B2 F11B1 F11B0 F10B3 F10B2 F10B1 F10B0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 13)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
60 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
$0058
$0059
$005A
$005B
$005C
$005D
LCD Data Register 7
(LDAT7)
LCD Data Register 8
(LDAT8)
LCD Data Register 9
(LDAT9)
LCD Data Register 10
(LDAT10)
LCD Data Register 11
(LDAT11)
LCD Data Register 12
(LDAT12)
Read:
F13B3 F13B2 F13B1 F13B0 F12B3 F12B2 F12B1 F12B0
Write:
Reset:UUUUUUUU
Read:
F15B3 F15B2 F15B1 F15B0 F14B3 F14B2 F14B1 F14B0
Write:
Reset:UUUUUUUU
Read:
F17B3 F17B2 F17B1 F17B0 F16B3 F16B2 F16B1 F16B0
Write:
Reset:UUUUUUUU
Read:
F19B3 F19B2 F19B1 F19B0 F18B3 F18B2 F18B1 F18B0
Write:
Reset:UUUUUUUU
Read:
F21B3 F21B2 F21B1 F21B0 F20B3 F20B2 F20B1 F20B0
Write:
Reset:UUUUUUUU
Read:
F23B3 F23B2 F23B1 F23B0 F22B3 F22B2 F22B1 F22B0
Write:
Reset:UUUUUUUU
$005E
$005F
$0060
$0061
Read:
LCD Data Register 13
(LDAT13)
LCD Data Register 14
(LDAT14)
LCD Data Register 15
(LDAT15)
LCD Data Register 16
(LDAT16)
U = Unaffected X = Indeterminate
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
F25B3 F25B2 F25B1 F25B0 F24B3 F24B2 F24B1 F24B0
F27B3 F27B2 F27B1 F27B0 F26B3 F26B2 F26B1 F26B0
F29B3 F29B2 F29B1 F29B0 F28B3 F28B2 F28B1 F28B0
F31B3 F31B2 F31B1 F31B0 F30B3 F30B2 F30B1 F30B0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 13)
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 61
Memory Map
Addr.Register Name Bit 7654321Bit 0
Read:
$0062
$0063
to
$0069
$006A
$006B
$006C
$006D
LCD Data Register 17
(LDAT17)
Unimplemented
MMIIC Master Control
Register
(MIMCR)
MMIIC Address Register
(MMADR)
MMIIC Control Register
(MMCR)
MMIIC Status Register
(MMSR)
Write:
Reset: UUUU
Read:
Write:
Reset:
Read: MMALIF MMNAKIF MMBB
Write: 0 0
Reset:00000000
Read:
Reset:10100000
Read:
Reset:00000000
Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK 0 MMTXBE MMRXBF
Reset:00001010
MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1
Write:
00
MMEN MMIEN
Write:
Write: 0 0
MMAST MMRW MMBR2 MMBR1 MMBR0
F32B3 F32B2 F32B1 F32B0
MMEXTAD
00
MMTXAK REPSEN
$006E
$006F
$0070
to
$007F
MMIIC Data Transmit
Register
(MMDTR)
MMIIC Data Receive
Register
(MMDRR)
Reserved
U = Unaffected X = Indeterminate
Read:
MMTD7 MMTD6 MMTD5 MMTD4 MMTD3 MMTD2 MMTD1 MMTD0
Write:
Reset:11111111
Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0
Write:
Reset:00000000
Read:
RRRRRRRR
Write:
Reset:
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 13)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
62 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Addr.Register Name Bit 7654321Bit 0
SIM Break Status Register
$FE00
Note: Writing a logic 0 clears SBSW.
SIM Reset Status Register
$FE01
$FE02 Reserved
SIM Break Flag Control
$FE03
Interrupt Status Register 1
$FE04
Interrupt Status Register 2
$FE05
(SBSR)
(SRSR)
Register
(SBFCR)
(INT1)
(INT2)
Read:
RRRRRR
Write: Note
Reset: 0
Read: POR PIN COP ILOP ILAD 0 LVI 0
Write:
POR:10000000
Read:
RRRRRRRR
Write:
Reset:
Read:
BCFERRRRRRR
Write:
Reset: 0
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
SBSW
R
Read: 0000IF18IF17IF16IF15
Interrupt Status Register 3
$FE06
$FE07 Reserved
$FE08
FLASH Control Register
(FLCR)
U = Unaffected X = Indeterminate
Write:RRRRRRRR
(INT3)
Reset:00000000
Read:
Write:
Reset:
Read: 0000
Write:
Reset:00000000
RRRRRRRR
HVEN MASS ERASE PGM
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 13)
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 63
Memory Map
Addr.Register Name Bit 7654321Bit 0
$FE09 Reserved
$FE0A Reserved
$FE0B Reserved
Break Address
$FE0C
Break Address
$FE0D
$FE0E
Break Status and Control
Register High
(BRKH)
Register Low
(BRKL)
Register
(BRKSCR)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
RRRRRRRR
RRRRRRRR
RRRRRRRR
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
000000
BRKE BRKA
Low-Voltage Inhibit Status
$FE0F
FLASH Block Protect
$FFCF
# Non-volatile FLASH register; write by programming.
$FFFF
COP Control Register
Register
(LVISR)
Register
(FLBPR)
(COPCTL)
U = Unaffected X = Indeterminate
Read: LVIOUT
Write:
Reset:00000000
Read:
Write:
#
Reset: Unaffected by reset; $FF when blank
Read: Low byte of reset vector
Write: Writing clears COP counter (any value)
Reset: Unaffected by reset
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure 2-2. Control, Status, and Data Registers (Sheet 13 of 13)
LVIIE
LVIIF00000
LVIIACK
= Unimplemented R = Reserved
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
64 Memory Map Freescale Semiconductor
Memory Map
Input/Output (I/O) Section
Table 2-1. Vector Addresses
.
Priority INT Flag Address Vector
Lowest
IF18
IF17
IF16
IF15
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
Highest $FFFF Reset Vector (Low)
—
$FFD8
$FFD9
$FFDA
$FFDB
$FFDC
$FFDD
$FFDE
$FFDF
$FFE0
$FFE1
$FFE2
$FFE3
$FFE4
$FFE5
$FFE6
$FFE7
$FFE8
$FFE9
$FFEA
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA IRQ
$FFFB IRQ
Real Time Clock
ADC Conversion Complete
Keyboard
MMIIC
SCI Transmit
SCI Receive
SCI Error
SPI Receive
SPI Transmit
TIM2 Overflow
TIM2 Channel 1
TIM2 Channel 0
TIM1 Overflow
TIM1 Channel 1
TIM1 Channel 0
PLL
LVI
Vector (High)
Vector (Low)
$FFFC SWI Vector (High)
$FFFD SWI Vector (Low)
$FFFE Reset Vector (High)
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Memory Map 65
Memory Map
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
66 Memory Map Freescale Semiconductor
Data Sheet — MC68HC908LJ24
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.2 Introduction
This section describes the 768 bytes of RAM (random-access memory).
3.3 Functional Description
Addresses $0080 through $037F are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64K-byte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 128 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE: For M6805 compatibility, the H register is not stacked.
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Random-Access Memory (RAM) 67
Random-Access Memory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
68 Random-Access Memory (RAM) Freescale Semiconductor
Data Sheet — MC68HC908LJ24
4.1 Contents
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .72
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .73
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.8 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
4.8.1 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .77
Section 4. FLASH Memory (FLASH)
4.2 Introduction
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor FLASH Memory (FLASH) 69
FLASH Memory (FLASH)
Addr.Register Name Bit 7654321Bit 0
Read: 0000
$FE08
$FFCF
# Non-volatile FLASH register; write by programming.
FLASH Control Register
(FLCR)
FLASH Block Protect
Register
(FLBPR)
Write:
Reset:00000000
Read:
Write:
#
Reset: Unaffected by reset; $FF when blank
Figure 4-1. FLASH I/O Register Summary
4.3 Functional Description
The FLASH memory consists of an array of 24,576 bytes for user
memory plus a block of 48 bytes for user interrupt vectors. An erased bit
reads as logic 1 and a programmed bit reads as a logic 0. The FLASH
memory page size is defined as 128 bytes, and is the minimum size that
can be erased in a page erase operation. Program and erase operations
are facilitated through control bits in FLASH control register (FLCR). The
address ranges for the FLASH memory are:
HVEN MASS ERASE PGM
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
= Unimplemented
• $9000–$EFFF; user memory, 24,576 bytes
• $FFD0–$FFFF; user interrupt vectors, 48 bytes
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
70 FLASH Memory (FLASH) Freescale Semiconductor
1
4.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
Address: $FE08
Read: 0000
Write:
Reset:00000000
HVEN — High Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
FLASH Memory (FLASH)
FLASH Control Register
Bit 7654321Bit 0
HVEN MASS ERASE PGM
Figure 4-2. FLASH Control Register (FLCR)
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or
block erase operation when the ERASE bit is set.
1 = Mass Erase operation selected
0 = Block Erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation not selected
PGM — Program Control Bit
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor FLASH Memory (FLASH) 71
FLASH Memory (FLASH)
4.5 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page
consists of 128 consecutive bytes starting from addresses $xx00 or
$xx80. The 48-byte user interrupt vectors area also forms a page. The
48-byte user interrupt vectors cannot be erased by the page erase
operation because of security reasons. Mass erase is required to erase
this page.
1. Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address within the page address
range desired.
4. Wait for a time, t
(min. 10µs).
nvs
5. Set the HVEN bit.
6. Wait for a time, t
erase
(1ms).
7. Clear the ERASE bit.
8. Wait for a time, t
9. Clear the HVEN bit.
10. After time, t
rcv
again.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory; the code must be
executed from RAM. While these operations must be performed in the
order as shown, but other unrelated operations may occur between the
steps.
(5µs).
nvh
(1µs), the memory can be accessed in read mode
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
72 FLASH Memory (FLASH) Freescale Semiconductor
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory:
1. Set both the ERASE bit and the MASS bit in the FLASH control
register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address within the FLASH memory
address range.
FLASH Memory (FLASH)
FLASH Mass Erase Operation
4. Wait for a time, t
(10µs).
nvs
5. Set the HVEN bit.
6. Wait for a time t
merase
(4ms).
7. Clear the ERASE bit.
8. Wait for a time, t
nvh1
(100µs).
9. Clear the HVEN bit.
10. After time, t
(1µs), the memory can be accessed again in read
rcv
mode.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory; the code must be
executed from RAM. While these operations must be performed in the
order as shown, but other unrelated operations may occur between the
steps.
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor FLASH Memory (FLASH) 73
FLASH Memory (FLASH)
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes starting from addresses $xx00, $xx40,
$xx80, or $xxC0. Use the following procedure to program a row of
FLASH memory. (Figure 4-3 shows a flowchart of the programming
algorithm.)
1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address within the row address
range desired.
4. Wait for a time, t
(10µs).
nvs
5. Set the HVEN bit.
6. Wait for a time, t
7. Write data to the FLASH address to be programmed.
8. Wait for time, t
pgs
prog
(5µs).
(30µs).
9. Repeat steps 7 and 8 until all bytes within the row are programmed.
10. Clear the PGM bit.
11. Wait for time, t
nvh
(5µs).
12. Clear the HVEN bit.
13. After time, t
(1µs), the memory can be accessed in read mode
rcv
again.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE: The time between each FLASH address change (step 7 to step 7), or the
time between the last FLASH addressed programmed to clearing the
PGM bit (step 7 to step 10), must not exceed the maximum programming
time, t
prog
max.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
74 FLASH Memory (FLASH) Freescale Semiconductor
FLASH Memory (FLASH)
FLASH Program Operation
Algorithm for programming
a row (64 bytes) of FLASH memory
1
2
Read the FLASH block protect register
3
Write any data to any FLASH location
Set PGM bit
within the address range of the row to
be programmed
4
5
6
7
Wait for a time, t
Set HVEN bit
Wait for a time, t
Write data to the FLASH address
to be programmed
nvs
pgs
8
Wait for a time, t
Completed
programming
this row?
NOTE:
The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
time, t
prog
max.
This row program algorithm assumes the row/s
to be programmed are initially erased.
prog
Y
N
10
11
12
13
Clear PGM bit
Wait for a time, t
nvh
Clear HVEN bit
Wait for a time, t
rcv
End of programming
Figure 4-3. FLASH Programming Flowchart
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor FLASH Memory (FLASH) 75
FLASH Memory (FLASH)
4.8 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
pages of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH block
protect register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either erase or program operations.
NOTE: The 48 bytes of user interrupt vectors are always protected, regardless
of the value in the FLASH block protect register. A mass erase is
required to erase the vectors.
When the FLBPR is program with $20, the entire memory is protected
from being programmed and erased. When the FLBPR is erased ($FF),
the entire memory is accessible for program and erase.
Once the FLBPR is programmed with a value other than $FF, the FLBPR
itself is protected. It can only be erased using a mass erase operation.
NOTE: In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
76 FLASH Memory (FLASH) Freescale Semiconductor
4.8.1 FLASH Block Protect Register
The FLASH block protect register (FLBPR) is implemented as a byte
within the FLASH memory, and therefore can only be written during a
programming sequence of the FLASH memory. The value in this register
determines the starting location of the protected range within the FLASH
memory.
Address: $FFCF
Bit 7654321Bit 0
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset: Unaffected by reset; $FF when blank
Non-volatile FLASH register; write by programming.
Figure 4-4. FLASH Block Protect Register (FLBPR)
FLASH Memory (FLASH)
FLASH Block Protection
BPR[7:0] — FLASH Block Protect Bits
BPR[7:0] represent bits [14:7] of a 16-bit memory address. Bits
[15:14] are logic 1’s and bits [6:0] are logic 0’s.
16-bit memory address
Start address of FLASH block protect 1 0000000
BPR[7:0]
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be $XX00 or $XX80 (at
page boundaries — 128 bytes) within the FLASH memory.
Examples of protect start address is shown in Table 4-1:
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor FLASH Memory (FLASH) 77
FLASH Memory (FLASH)
Table 4-1. FLASH Block Protect Register to Physical Address
BPR[7:0]
$00 to $1F
$20
$21 $9080 (1001 0000 1000 0000)
$22 $9100 (1001 0001 0000 0000)
$23 $9180 (1001 0001 1000 0000)
$24 $9200 (1001 0010 0000 0000)
and so on...
$DE $EF00 (1110 1111 0000 0000)
$DF $EF80 (1110 1111 1000 0000)
$E0 to $FF
Notes:
1. The end address of the protected range is always $FFFF.
2. Except the 48-byte user vectors, which is always protected.
Start Address of Protection Range
The entire FLASH memory is NOT protected.
$9000 (1001 0000 0000 0000)
The entire FLASH memory is protected.
The entire FLASH memory is NOT protected.
(1)
(2)
(2)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
78 FLASH Memory (FLASH) Freescale Semiconductor
Data Sheet — MC68HC908LJ24
Section 5. Configuration Registers (CONFIG)
5.1 Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.4 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .81
5.5 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .82
5.2 Introduction
This section describes the configuration registers, CONFIG1 and
CONFIG2. The configuration registers enable or disable these options:
• Computer operating properly module (COP)
• COP timeout period (218 – 24 or 213 – 24 ICLK cycles)
• Low-voltage inhibit (LVI) module power
• LVI module reset
• LVI module in stop mode
• LVI module voltage trip point selection
• STOP instruction
• Stop mode recovery time (32 ICLK cycles or 4096 ICLK cycles)
• Oscillator during stop mode
• LCD frontplanes FP19–FP26 on port C
• LCD frontplanes FP11–FP18 on port E
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Configuration Regist ers (CONFIG) 79
Configuration Registers (CONFIG)
Addr.Register Name Bit 7654321Bit 0
$001D
$001F
† One-time writable register after each reset.
†† Reset by POR only.
Configuration Register 2
(CONFIG2)
Configuration Register 1
(CONFIG1)
†
Reset:0000000
†
Reset:0000††0000
5.3 Functional Description
The configuration registers are used in the initialization of various
options. Since the various options affect the operation of the MCU, it is
recommended that these registers be written immediately after reset.
The configuration registers are located at $001D and $001F. The
configuration registers may be read at anytime.
Read:
PEE
Write:
Read:
COPRS LVISTOP LVIRSTD LVIPWRD
Write:
STOP_
IRCDIS
= Unimplemented
STOP_
XCLKEN
DIV2CLK PCEH PCEL LVISEL1 LVISEL0
Figure 5-1. CONFIG Registers Summary
††
0
SSREC STOP COPD
††
1
NOTE: The CONFIG registers are one-time writable by the user after each
reset. These registers are not in the FLASH memory but are special
registers containing one-time writable latches after each reset. Upon a
reset, the CONFIG registers default to predetermined settings as shown
in Figure 5-2 and Figure 5-3.
Although the LVISEL[1:0] bits default to predetermined setting of
LVISEL[1:0] = 0:1 by a POR only, these bits can still be written once after
each reset other than POR.
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
80 Configuration Registers (CONFIG) Freescale Semiconductor
5.4 Configuration Register 1 (CONFIG1)
The CONFIG1 register can be written once after each reset.
Address: $001F
Bit 7654321Bit 0
Configuration Registers (CONFIG)
Configuration Register 1 (CONFIG1)
Read:
COPRS LVISTOP LVIRSTD LVIPWRD
Write:
Reset:0000††0000
†† Reset by POR only.
= Unimplemented
0
SSREC STOP COPD
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS. (See
Section 21. Computer Operating Properly (COP).)
1 = COP time out period = 213 – 24 ICLK cycles
0 = COP time out period = 218 – 24 ICLK cycles
LVISTOP — LVI Enable in Stop Mode
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
Section 22. Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable
LVIRSTD disables the reset signal from the LVI module. (See
Section 22. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 22. Low-Voltage
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Configuration Regist ers (CONFIG) 81
Configuration Registers (CONFIG)
SSREC — Short Stop Recovery
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK
cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
NOTE: When the LVISTOP is enabled, the system stabilization time for power
on reset and long stop recovery (both 4096 ICLK cycles) gives a delay
longer than the enable time for the LVI. There is no period where the
MCU is not protected from a low power condition. However, when using
the short stop recovery configuration option, the 32 ICLK delay is less
than the LVI’s turn-on time and there exists a period in start-up where the
LVI is not protecting the MCU.
STOP — STOP Instruction Enable
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 21. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
5.5 Configuration Register 2 (CONFIG2)
The CONFIG2 register can be written once after each reset.
Address: $001D
Bit 7654321Bit 0
Read:
PEE
Write:
Reset:0000000
STOP_
IRCDIS
STOP_
XCLKEN
DIV2CLK PCEH PCEL LVISEL1 LVISEL0
††
††
1
†† Reset by POR only.
Figure 5-3. Configuration Register 2 (CONFIG2)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
82 Configuration Registers (CONFIG) Freescale Semiconductor
Configuration Registers (CONFIG)
Configuration Register 2 (CONFIG2)
PEE — Port E Enable
Setting PEE configures the PTE0/FP11–PTE7/FP18 pins for LCD
frontplane driver use. Reset clears this bit.
1 = PTE0/FP11–PTE7/FP18 pins configured as LCD frontplane
driver pins: FP11–FP18
0 = PTE0/FP11–PTE7/FP18 pins configured as standard I/O pins:
PTE0–PTE7
STOP_IRCDIS — Internal RC Oscillator Stop Mode Disable
Setting STOP_IRCDIS disables the internal RC oscillator during stop
mode. When this bit is cleared, the internal RC oscillator continues to
operate in stop mode. Reset clears this bit.
1 = Internal RC oscillator disabled during stop mode
0 = Internal RC oscillator enabled during stop mode
STOP_XCLKEN — Crystal Oscillator Stop Mode Enable
Setting STOP_XCLKEN enables the external crystal (XTAL) oscillator
to continue operating in stop mode. This is useful for driving the real
time clock module to allow it to generate periodic wake up while in
stop mode. When this bit is cleared, the external XTAL oscillator will
be disabled during stop mode. Reset clears this bit.
1 = XTAL oscillator enabled during stop mode
0 = XTAL oscillator disabled during stop mode
DIV2CLK — Divide-by-2 Clock Bypass
When CGMXCLK is selected to drive the system clocks (BCS=0),
setting DIV2CLK allows the CGMXCLK to bypass the divide-by-2
divider in the CGM module; CGMOUT will equal CGMXCLK and bus
clock will equal CGMXCLK divide-by-2.
DIV2CLK bit has no effect when the BCS=1 in the PLL control
register (CGMVCLK selected and divide-by-2 always enabled). Reset
clears this bit.
1 = Divide-by-2 divider bypassed;
When BSC=0, CGMOUT equals CGMXCLK
0 = Divide-by-2 divider enabled;
When BSC=0, CGMOUT equals CGMXCLK divide-by-2
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Configuration Regist ers (CONFIG) 83
Configuration Registers (CONFIG)
PCEH — Port C Enable High Nibble
Setting PCEH configures the PTC4/FP23–PTC7/FP26 pins for LCD
frontplane driver use. Reset clears this bit.
1 = PTC4/FP23–PTC7/FP26 pins configured as LCD frontplane
driver pins: FP23–FP26
0 = PTC4/FP23–PTC7/FP26 pins configured as standard I/O pins:
PTC4–PTC7
PCEL — Port C Enable Low Nibble
Setting PCEL configures the PTC0/FP19–PTC3/FP22 pins for LCD
frontplane driver use. Reset clears this bit.
1 = PTC0/FP19–PTC3/FP22 pins configured as LCD frontplane
driver pins: FP19–FP22
0 = PTC0/FP19–PTC3/FP22 pins configured as standard I/O pins:
PTC0–PTC3
LVISEL[1:0] — LVI Operating Mode Selection
LVISEL[1:0] selects the voltage operating mode of the LVI module.
(See Section 22. Low-Voltage Inhibit (LVI).) The voltage mode
selected for the LVI should match the operating VDD. See Section 24.
Electrical Specifications for the LVI voltage trip points for each of
the modes.
Table 5-1. LVI Trip Point Selection
LVISEL1 LVISEL0 Operating Mode
00 Reserved
01
10 5V
11 Reserved
Notes:
1. Default setting after a power-on-reset.
3.3V
(1)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
84 Configuration Registers (CONFIG) Freescale Semiconductor
Data Sheet — MC68HC908LJ24
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 85
Central Processor Unit (CPU)
6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
6.3 Features
Feature of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-Bit index register with X-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64-Kbytes
• Low-power stop and wait modes
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
86 Central Processor Unit (CPU) Freescale Semiconductor
6.4 CPU Registers
Central Processor Unit (CPU)
CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
6.4.1 Accumulator
7
15
H X
15
15
70
V11HINZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 6-2. Accumulator (A)
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 87
Central Processor Unit (CPU)
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64K-byte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
6.4.3 Stack Pointer
Bit
1413121110987654321
15
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Bit
0
Figure 6-3. Index Register (H:X)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
1413121110987654321
15
Read:
Write:
Reset:0000000011111111
Bit
0
Figure 6-4. Stack Pointer (SP)
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
88 Central Processor Unit (CPU) Freescale Semiconductor
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
6.4.4 Program Counter
Central Processor Unit (CPU)
CPU Registers
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
1413121110987654321
15
Read:
Write:
Reset: Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Bit
0
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 89
Central Processor Unit (CPU)
6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:
V11HI NZC
X1 1X1XXX
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction
uses the states of the H and C flags to determine the appropriate
correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
90 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
CPU Registers
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 91
Central Processor Unit (CPU)
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Freescale document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
6.6.1 Wait Mode
The WAIT and STOP ins tr uc ti on s put the MCU in l o w p o w e r- c o ns u m p ti o n
standby modes.
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock.
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
92 Central Processor Unit (CPU) Freescale Semiconductor
6.6.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock.
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. (See Section 23. Break Module (BRK).) The
program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor
mode).
Central Processor Unit (CPU)
CPU During Break Interrupts
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 93
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 1 of 8)
Effect on
Source
Form
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) ––––––IMM A7 ii 2
Add with Carry A ← (A) + (M) + (C) RR– RRR
Add without Carry A ← (A) + (M) RR– RRR
Operation Description
CCR
VHI NZC
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
Opcode
Operand
ii
A9
dd
B9
hh ll
C9
ee ff
D9
ff
E9
F9
ff
9EE9
ee ff
9ED9
ii
AB
dd
BB
hh ll
CB
ee ff
DB
ff
EB
FB
ff
9EEB
ee ff
9EDB
Cycles
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) ––––––IMM AF ii 2
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3
BCLR n, opr Clear Bit n in M Mn ← 0 ––––––
Logical AND A ← (A) & (M) 0 – – RR–
Arithmetic Shift Left
(Same as LSL)
Arithmetic Shift Right R ––RRR
C
b7
b7
0
b0
C
b0
R ––RRR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
A4
B4
C4
D4
E4
F4
9EE4
9ED4
38
48
58
68
78
9E68
37
47
57
67
77
9E67
11
13
15
17
19
1B
1D
1F
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
dd
dd
dd
dd
dd
dd
dd
dd
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
4
4
4
4
4
4
4
4
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
94 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary (Sheet 2 of 8)
Effect on
Source
Form
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
Operation Description
CCR
VHI NZC
Address
Mode
Opcode
Operand
Cycles
BGE opr
BGT opr
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3
BHS rel
BIH rel Branch if IRQ
BIL rel Branch if IRQ
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
BLE opr
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1 ––––––REL 91 rr 3
Branch if Greater Than or Equal To
(Signed Operands)
Branch if Greater Than (Signed
Operands)
Branch if Higher or Same
(Same as BCC)
Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3
Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
Bit Test (A) & (M) 0 – – RR –
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 ––––––REL 90 rr 3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0
PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1
––––––REL 92 rr 3
ii
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
––––––REL 93 rr 3
A5
B5
C5
D5
E5
F5
9EE5
9ED5
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3
BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 95
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 3 of 8)
Effect on
Source
Form
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 –––––R
BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 –––––R
Operation Description
CCR
VHI NZC
Address
Mode
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
00
02
04
06
08
0A
0C
0E
Opcode
Operand
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
Cycles
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
DIR (b0)
DIR (b1)
BSET n,opr Set Bit n in M Mn ← 1 ––––––
PC ← (PC) + 2; push (PCL)
BSR rel Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC Clear Carry Bit C ← 0 –––––0INH 98 1
CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Compare and Branch if Equal
Clear
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
––––––REL AD rr 4
––––––
0––01–
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR
IMM
IMM
IX1+
IX+
SP1
DIR
INH
INH
INH
IX1
IX
SP1
10
12
14
16
18
1A
1C
1E
31
41
51
61
71
9E61
3F
4F
5F
8C
6F
7F
9E6F
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii rr
ii rr
ff rr
rr
ff rr
dd
ff
ff
4
4
4
4
4
4
4
4
5
4
4
5
4
6
3
1
1
1
3
2
4
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
96 Central Processor Unit (CPU) Freescale Semiconductor
Source
Form
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 4 of 8)
Effect on
Operation Description
Compare A with M (A) – (M) R ––RRR
M ← (M
) = $FF – (M)
A ← (A
) = $FF – (M)
X ← (X
Complement (One’s Complement)
M ← (M
M ← (M
M ← (M
) = $FF – (M)
) = $FF – (M)
) = $FF – (M)
) = $FF – (M)
CCR
VHI NZC
0––RR1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
Opcode Map
Address
Mode
Opcode
Operand
Cycles
2
ii
A1
3
dd
B1
C1
D1
E1
F1
9EE1
9ED1
33
43
53
63
73
9E63
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
4
4
3
2
4
5
4
1
1
4
3
5
CPHX #opr
CPHX opr
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
DAA Decimal Adjust A (A)
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
DIV Divide
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Compare H:X with M (H:X) – (M:M + 1) R ––RRR
Compare X with M (X) – (M) R ––RRR
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
Decrement and Branch if Not Zero
Decrement
Exclusive OR M with A A ← (A ⊕ M) 0––RR–
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (H:A)/(X)
H ← Remainder
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
10
U––RRRINH 72 2
DIR
INH
––––––
R ––RR–
––––RRINH 52 7
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
6575ii ii+1dd3
ii
A3
dd
B3
hh ll
C3
ee ff
D3
ff
E3
F3
ff
9EE3
ee ff
9ED3
dd rr
3B
rr
4B
rr
5B
ff rr
6B
rr
7B
ff rr
9E6B
dd
3A
4A
5A
ff
6A
7A
9E6A
ff
ii
A8
dd
B8
hh ll
C8
ee ff
D8
ff
E8
F8
ff
9EE8
ee ff
9ED8
4
2
3
4
4
3
2
4
5
5
3
3
5
4
6
4
1
1
4
3
5
2
3
4
4
3
2
4
5
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 97
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 5 of 8)
Source
Form
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDHX #opr
LDHX opr
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
Increment
Jump PC ← Jump Address ––––––
Jump to Subroutine
Load A from M A ← (M) 0––RR–
Load H:X from M H:X ← (M:M + 1) 0––RR–
Load X from M X ← (M) 0––RR–
Logical Shift Left
(Same as ASL)
Operation Description
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
C
b7
0
b0
Effect on
CCR
VHI NZC
R ––RR–
––––––
R ––RRR
DIR
INH
INH
IX1
IX
SP1
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
Address
Mode
Opcode
Operand
Cycles
dd
ff
ff
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
4
1
1
4
3
5
2
3
4
3
2
4
5
6
5
4
2
3
4
4
3
2
4
5
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
3C
4C
5C
6C
7C
9E6C
BC
CC
DC
EC
FC
BD
CD
DD
ED
FD
A6
B6
C6
D6
E6
F6
9EE6
9ED6
4555ii jjdd3
AE
BE
CE
DE
EE
FE
9EEE
9EDE
38
48
58
68
78
9E68
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Right R ––0RR
b7
C0
b0
DIR
INH
INH
IX1
IX
SP1
34
44
54
64
74
9E64
4
1
1
4
ff
3
5
ff
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
98 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary (Sheet 6 of 8)
Effect on
Source
Form
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP No Operation None – – – – – – INH 9D 1
NSA Nibble Swap A A ← (A[3:0]:A[7:4]) – – – – – – INH 62 3
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2
Move
Negate (Two’s Complement)
Inclusive OR A and M A ← (A) | (M) 0 – – RR–
Operation Description
(M)
Destination
H:X ← (H:X) + 1 (IX+D, DIX+)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
← (M)
Source
CCR
VHI NZC
0––RR–
R ––RRR
DD
DIX+
IMD
IX+D
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
Opcode
Operand
5
dd dd
4E
4
dd
5E
6E
7E
30
40
50
60
70
9E60
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
4
4
4
1
1
4
3
5
2
3
4
4
3
2
4
5
Cycles
PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2
PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2
PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2
PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2
PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2
dd
ff
ff
dd
ff
ff
4
1
1
4
3
5
4
1
1
4
3
5
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1
Rotate Left through Carry R ––RRR
Rotate Right through Carry R ––RRR
C
b7
b7
b0
C
b0
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E69
36
46
56
66
76
9E66
MC68HC908LJ24/LK24 — Rev. 2.1 Data Sheet
Freescale Semiconductor Central Processor Unit (CPU) 99
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 7 of 8)
Effect on
Source
Form
RTI Return from Interrupt
RTS Return from Subroutine
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC Set Carry Bit C ← 1 –––––1INH 99 1
Subtract with Carry A ← (A) – (M) – (C) R ––RRR
Operation Description
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
CCR
VHI NZC
RRRRRRINH 80 7
––––––INH 81 4
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
Address
Mode
Opcode
Operand
ii
A2
dd
B2
hh ll
C2
ee ff
D2
ff
E2
F2
ff
9EE2
ee ff
9ED2
Cycles
2
3
4
4
3
2
4
5
SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – RR– DIR 35 dd 4
STOP Enable IRQ
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Store A in M M ← (A) 0––RR–
Pin; Stop Oscillator I ← 0; Stop Oscillator – – 0 – – – INH 8E 1
Store X in M M ← (X) 0––RR–
Subtract A ← (A) – (M) R ––RRR
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
BF
CF
DF
EF
FF
9EEF
9EDF
A0
B0
C0
D0
E0
F0
9EE0
9ED0
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
Data Sheet MC68HC908LJ24/LK24 — Rev. 2.1
100 Central Processor Unit (CPU) Freescale Semiconductor
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