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MC68HC908LJ12
DATA SHEET
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Freescale MC68HC908LJ12 DATA SHEET

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MC68HC908LJ12 Technical Data
M68HC08 Microcontrollers
Rev. 2.1 MC68HC908LJ12/D August 2, 2005
freescale.com
MC68HC908LJ12

Technical Data

Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating par ameters, including "Typicals" m ust be validated for each customer application by customer's technical experts. Freescale does not convey any license under its pa tent rig hts n or th e righ ts of ot hers . Fre esca le pro duc ts are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur. Should Buyer pur chase or use Freescale products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintend ed or unauthorized use, even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part. Freescale, Inc. is an Equal Opportunity/Affirmative Action Employer.
© Freescale, Inc., 2002
Freescale Semiconductor Technical Data 3
Technical Data
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
February
2002
August, 2005 2.1 Updated to meet Freescale identity guidelines. —
Revision
Level
2 First general release. —
Description
Page
Number(s)
Technical Data MC68HC908LJ12 — Rev. 2.1
4 Technical Data Freescale Semiconductor
Technical Data — MC68HC908LJ12
Section 1. General Description . . . . . . . . . . . . . . . . . . . .33
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .43
Section 3. Random-Access Memory (RAM) . . . . . . . . . .59
Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . .61
Section 5. Configuration Registers (CONFIG) . . . . . . . .71
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . .77
Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . .95
Section 8. Clock Generator Module (CGM). . . . . . . . . .101
Section 9. System Integration Module (SIM) . . . . . . . .131

List of Sections

Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .155
Section 11. Timer Interface Module (TIM) . . . . . . . . . . .185
Section 12. Real Time Clock (RTC) . . . . . . . . . . . . . . . .209
Section 13. Infrared Serial Communications
Interface Module (IRSCI) . . . . . . . . . . . .227
Section 14. Serial Peripheral Interface Module (SPI). .269
Section 15. Analog-to-Digital Converter (ADC) . . . . . .301
Section 16. Liquid Crystal Display Driver (LCD) . . . . .317
Section 17. Input/Output (I/O) Ports . . . . . . . . . . . . . . .341
Section 18. External Interrupt (IRQ) . . . . . . . . . . . . . . .357
Section 19. Keyboard Interrupt Module (KBI). . . . . . . .363
Freescale Semiconductor List of Sections 5
List of Sections
Section 20. Computer Operating Properly (COP) . . . .371
Section 21. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . .377
Section 22. Break Module (BRK) . . . . . . . . . . . . . . . . . .383
Section 23. Electrical Specifications. . . . . . . . . . . . . . .391
Section 24. Mechanical Specifications . . . . . . . . . . . . .407
Section 25. Ordering Information . . . . . . . . . . . . . . . . .411
Technical Data MC68HC908LJ12 — Rev. 2.1
6 List of Sections Freescale Semiconductor
Technical Data — MC68HC908LJ12
Section 1. General Description
1.1 Contents . . . . . . . . . . .

Table of Contents

Freescale Semiconductor Table of Contents 7
Table of Contents
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44
2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Section 3. Random-Access Memory (RAM)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Section 4. FLASH Memory (FLASH)
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .64
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .65
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.8 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.8.1 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .68
Section 5. Configuration Registers (CONFIG)
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5.4 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .73
5.5 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .75
Technical Data MC68HC908LJ12 — Rev. 2.1
8 Table of Contents Freescale Semiconductor
Table of Contents
Section 6. Central Processor Unit (CPU)
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Section 7. Oscillator (OSC)
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.3 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.4 Crystal (X-tal) Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . .98
7.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . .98
7.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . .98
7.5.4 Internal RC Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.5.5 CGM Oscillator Clock (CGMXCLK) . . . . . . . . . . . . . . . . . . .98
7.5.6 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . .98
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7.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . .99
Section 8. Clock Generator Module (CGM)
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8.4.1 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .106
8.4.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
8.4.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . .108
8.4.5 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . .108
8.4.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.4.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . .114
8.4.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . .114
8.4.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . .115
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
8.5.1 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . .116
8.5.2 PLL Analog Power Pin (V
8.5.3 PLL Analog Ground Pin (V
) . . . . . . . . . . . . . . . . . . . . . .116
DDA
) . . . . . . . . . . . . . . . . . . . . .116
SSA
8.5.4 Oscillator Output Frequency Signal (CGMXCLK) . . . . . . .116
8.5.5 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . .116
8.5.6 CGM VCO Clock Output (CGMVCLK). . . . . . . . . . . . . . . .117
8.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . .117
8.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .117
8.6 CGM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
8.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .120
8.6.3 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . .122
8.6.4 PLL VCO Range Select Register. . . . . . . . . . . . . . . . . . . .123
8.6.5 PLL Reference Divider Select Register . . . . . . . . . . . . . . .124
Technical Data MC68HC908LJ12 — Rev. 2.1
10 Table of Contents Freescale Semiconductor
Table of Contents
8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
8.8.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .126
8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .127
8.9.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .127
8.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .127
8.9.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Section 9. System Integration Module (SIM)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .134
9.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.3.2 Clock Start-up from POR or LVI Reset. . . . . . . . . . . . . . . .135
9.3.3 Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . .136
9.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .136
9.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . .137
9.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . .139
9.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.4.2.4 Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.4.2.5 Low-Voltage Inhibit (LVI) Reset. . . . . . . . . . . . . . . . . . .140
9.4.2.6 Monitor Mode Entry Module Reset (MODRST) . . . . . . .140
9.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .141
9.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . .141
9.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .141
9.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.6.1.1 Hardware Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .144
9.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
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9.6.1.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .145
9.6.1.4 Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . .145
9.6.1.5 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . .147
9.6.1.6 Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . .147
9.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .148
9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.8 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9.8.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .152
9.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .153
9.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .154
Section 10. Monitor ROM (MON)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
10.4.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .159
10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.4.3 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.4.5 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
10.6 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10.6.1 PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
10.6.2 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
10.6.3 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
10.6.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
10.6.5 MON_ERARNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
10.6.6 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
10.6.7 EE_WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
10.6.8 EE_READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Technical Data MC68HC908LJ12 — Rev. 2.1
12 Table of Contents Freescale Semiconductor
Table of Contents
Section 11. Timer Interface Module (TIM)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
11.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.5.1 TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . .191
11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .192
11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .193
11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .193
11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .194
11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .195
11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
11.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .198
11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
11.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .200
11.10.2 TIM Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .202
11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .203
11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .204
11.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Section 12. Real Time Clock (RTC)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
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12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
12.4.1 Time Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
12.4.2 Calendar Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
12.4.3 Alarm Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
12.4.4 Timebase Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
12.4.5 Chronograph Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .215
12.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
12.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
12.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
12.6 RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
12.6.1 RTC Control Register 1 (RTCCR1) . . . . . . . . . . . . . . . . . .216
12.6.2 RTC Control Register 2 (RTCCR2) . . . . . . . . . . . . . . . . . .218
12.6.3 RTC Status Register (RTCSR). . . . . . . . . . . . . . . . . . . . . .219
12.6.4 Alarm Minute and Hour Registers (ALMR and ALHR). . . .222
12.6.5 Second Register (SECR) . . . . . . . . . . . . . . . . . . . . . . . . . .223
12.6.6 Minute Register (MINR) . . . . . . . . . . . . . . . . . . . . . . . . . . .223
12.6.7 Hour Register (HRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
12.6.8 Day Register (DAYR). . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
12.6.9 Month Register (MTHR). . . . . . . . . . . . . . . . . . . . . . . . . . .225
12.6.10 Year Register (YRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
12.6.11 Day-Of-Week Register (DOWR) . . . . . . . . . . . . . . . . . . . .226
12.6.12 Chronograph Data Register (CHRR) . . . . . . . . . . . . . . . . .226
Section 13. Infrared Serial Communications
Interface Module (IRSCI)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
13.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
13.5 IRSCI Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
13.6 Infrared Functional Description. . . . . . . . . . . . . . . . . . . . . . . .232
13.6.1 Infrared Transmit Encoder . . . . . . . . . . . . . . . . . . . . . . . . .233
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13.6.2 Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . .233
13.7 SCI Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . .234
13.7.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
13.7.2 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
13.7.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
13.7.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .237
13.7.2.3 Break Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
13.7.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
13.7.2.5 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .239
13.7.3 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
13.7.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
13.7.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .241
13.7.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
13.7.3.4 Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
13.7.3.5 Baud Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . .243
13.7.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
13.7.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
13.7.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
13.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
13.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
13.9 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .249
13.10 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
13.10.1 PTB0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . .249
13.10.2 PTB1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . .249
13.11 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
13.11.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
13.11.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
13.11.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
13.11.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
13.11.5 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . .262
13.11.6 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . .263
13.11.7 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . .264
13.11.8 SCI Infrared Control Register. . . . . . . . . . . . . . . . . . . . . . .267
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Section 14. Serial Peripheral Interface Module (SPI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
14.4 Pin Name Conventions and I/O Register Addresses . . . . . . .271
14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
14.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
14.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
14.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
14.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .275
14.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .276
14.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .278
14.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .279
14.7 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . .281
14.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
14.8.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
14.8.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
14.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
14.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
14.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
14.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
14.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
14.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .290
14.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
14.13.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .291
14.13.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .291
14.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
14.13.4 SS
14.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
(Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
14.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
14.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
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14.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .296
14.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
Section 15. Analog-to-Digital Converter (ADC)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
15.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
15.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
15.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
15.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .306
15.4.5 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
15.4.6 Monotonicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
15.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
15.7.1 ADC Voltage In (V
15.7.2 ADC Analog Power Pin (V
15.7.3 ADC Voltage Reference High Pin (V
15.7.4 ADC Voltage Reference Low Pin (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . .309
ADIN
) . . . . . . . . . . . . . . . . . . . . .309
DDA
). . . . . . . . . . . . .309
REFH
) . . . . . . . . . . . . .309
REFL
15.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
15.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .310
15.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
15.8.3 ADC Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . .314
Section 16. Liquid Crystal Display Driver (LCD)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
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16.4 Pin Name Conventions and I/O Register Addresses . . . . . . .318
16.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
16.5.1 LCD Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
16.5.2 LCD Voltages (V
LCD
, V
LCD1
, V
LCD2
, V
) . . . . . . . . . . .323
LCD3
16.5.3 LCD Cycle Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
16.5.4 Fast Charge and Low Current . . . . . . . . . . . . . . . . . . . . . .324
16.5.5 Contrast Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
16.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
16.7.1 BP0–BP3 (Backplane Drivers). . . . . . . . . . . . . . . . . . . . . .326
16.7.2 FP0–FP26 (Frontplane Drivers). . . . . . . . . . . . . . . . . . . . .328
16.8 Seven Segment Display Connection . . . . . . . . . . . . . . . . . . .332
16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
16.9.1 LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . .335
16.9.2 LCD Clock Register (LCDCLK) . . . . . . . . . . . . . . . . . . . . .337
16.9.3 LCD Data Registers (LDAT1–LDAT14) . . . . . . . . . . . . . . .339
Section 17. Input/Output (I/O) Ports
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
17.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
17.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .344
17.3.2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . .345
17.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
17.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .347
17.4.2 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . .348
17.4.3 Port B LED Control Register (LEDB) . . . . . . . . . . . . . . . . .350
17.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
17.5.1 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .351
17.5.2 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . .352
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17.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
17.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .354
17.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . .355
Section 18. External Interrupt (IRQ)
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
18.4.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360
18.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .361
18.6 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .361
Section 19. Keyboard Interrupt Module (KBI)
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
19.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
19.5.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
19.6 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . .367
19.6.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . .368
19.6.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .369
19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
19.8 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
19.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
19.10 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .370
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Section 20. Computer Operating Properly (COP)
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
20.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
20.4.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
20.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
20.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
20.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
20.4.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
20.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
20.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
20.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .374
20.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
20.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
20.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
20.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
20.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
20.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
20.9 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . .376
Section 21. Low-Voltage Inhibit (LVI)
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
21.4.1 Interrupt LVI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .380
21.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .380
21.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .380
21.4.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
21.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
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21.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
21.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
21.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
Section 22. Break Module (BRK)
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
22.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .386
22.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .386
22.4.3 TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . .386
22.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .386
22.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
22.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
22.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
22.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
22.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .387
22.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .388
22.6.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .388
22.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .390
Section 23. Electrical Specifications
23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .392
23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .393
23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
23.6 5.0V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .394
23.7 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .396
23.8 5.0V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
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23.9 3.3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
23.10 5.0V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . .398
23.11 3.3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . .398
23.12 5.0V ADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .399
23.13 3.3V ADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .400
23.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .401
23.15 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . .401
23.16 5.0V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
23.17 3.3V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
23.18 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .406
Section 24. Mechanical Specifications
24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
24.3 52-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . .408
24.4 64-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . .409
24.5 64-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . .410
Section 25. Ordering Information
25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
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Figure Title Page
1-1 MC68HC908LJ12 Block Diagram. . . . . . . . . . . . . . . . . . . . . . .37
1-2 64-Pin QFP and 64-Pin LQFP Pin Assignment . . . . . . . . . . . .38
1-3 52-Pin LQFP Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . .39
1-4 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
2-2 Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . . . .46
4-1 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .62
4-2 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . .63
4-3 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . . .67
4-4 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . .68
4-5 FLASH Block Protect Start Address. . . . . . . . . . . . . . . . . . . . .68

List of Figures

5-1 CONFIG Registers Summary. . . . . . . . . . . . . . . . . . . . . . . . . .72
5-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .73
5-3 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .75
6-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6-3 Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
6-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .82
7-1 Oscillator Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . .96
8-1 CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8-2 CGM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .105
8-3 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .115
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Figure Title Page
8-4 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .118
8-5 PLL Bandwidth Control Register (PBWCR) . . . . . . . . . . . . . .121
8-6 PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . .122
8-7 PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . .122
8-8 PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . .123
8-9 PLL Reference Divider Select Register (PMDS) . . . . . . . . . .124
8-10 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
9-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .134
9-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9-6 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9-8 Interrupt Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9-9 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
9-11 Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . . . .144
9-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .145
9-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .147
9-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .147
9-15 Wait Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9-16 Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . . .150
9-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .150
9-18 Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .151
9-20 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .152
9-21 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .153
9-22 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .154
10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
10-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .162
10-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10-4 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
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10-6 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
10-7 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .168
10-8 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .169
10-9 Data Block Format for ROM-Resident Routines. . . . . . . . . . .172
10-10 EE_WRITE FLASH Memory Usage. . . . . . . . . . . . . . . . . . . .181
11-1 TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .189
11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .194
11-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .200
11-5 TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . .202
11-6 TIM Counter Registers Low (TCNTL). . . . . . . . . . . . . . . . . . .202
11-7 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .203
11-8 TIM Counter Modulo Register Low (TMODL). . . . . . . . . . . . .203
11-9 TIM Channel 0 Status and Control Register (TSC0) . . . . . . .204
11-10 TIM Channel 1 Status and Control Register (TSC1) . . . . . . .204
11-11 CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
11-12 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . .208
11-13 TIM Channel 0 Register Low (TCH0L). . . . . . . . . . . . . . . . . .208
11-14 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . .208
11-15 TIM Channel 1 Register Low (TCH1L). . . . . . . . . . . . . . . . . .208
12-1 RTC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .210
12-2 RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
12-3 RTC Control Register 1 (RTCCR1) . . . . . . . . . . . . . . . . . . . .216
12-4 RTC Control Register 2 (RTCCR2) . . . . . . . . . . . . . . . . . . . .218
12-5 RTC Status Register (RTCSR). . . . . . . . . . . . . . . . . . . . . . . .219
12-6 Alarm Minute Register (ALMR). . . . . . . . . . . . . . . . . . . . . . . .222
12-7 Alarm Hour Register (ALHR) . . . . . . . . . . . . . . . . . . . . . . . . .222
12-8 Second Register (SECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
12-9 Minute Register (MINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
12-10 Hour Register (HRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
12-11 Day Register (DAYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
12-12 Month Register (MTHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
12-13 Year Register (YRR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
12-14 Day-Of-Week Register (DOWR). . . . . . . . . . . . . . . . . . . . . . .226
12-15 Chronograph Data Register (CHRR) . . . . . . . . . . . . . . . . . . .226
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Figure Title Page
13-1 IRSCI I/O Registers Summary . . . . . . . . . . . . . . . . . . . . . . . .230
13-2 IRSCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
13-3 Infrared Sub-Module Diagram . . . . . . . . . . . . . . . . . . . . . . . .232
13-4 Infrared SCI Data Example. . . . . . . . . . . . . . . . . . . . . . . . . . .233
13-5 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .234
13-6 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
13-7 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
13-8 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .240
13-9 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
13-10 Slow Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
13-11 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
13-12 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .251
13-13 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .254
13-14 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .256
13-15 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .258
13-16 Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
13-17 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .262
13-18 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . .263
13-19 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .264
13-20 SCI Infrared Control Register (SCIRCR) . . . . . . . . . . . . . . . .267
14-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .271
14-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .272
14-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . .273
14-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .277
14-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
14-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .278
14-7 Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . . . .280
14-8 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . . .281
14-9 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .283
14-10 Clearing SPRF When OVRF Interrupt Is Not Enabled. . . . . .284
14-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .287
14-12 CPHA/SS
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
14-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .294
14-14 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .296
14-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .299
Technical Data MC68HC908LJ12 — Rev. 2.1
26 List of Figures Freescale Semiconductor
List of Figures
Figure Title Page
15-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .303
15-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
15-3 8-Bit Truncation Mode Error . . . . . . . . . . . . . . . . . . . . . . . . . .307
15-4 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .310
15-5 ADRH and ADRL in 8-Bit Truncated Mode. . . . . . . . . . . . . . .312
15-6 ADRH and ADRL in Right Justified Mode. . . . . . . . . . . . . . . .312
15-7 ADRH and ADRL in Left Justified Mode. . . . . . . . . . . . . . . . .313
15-8 ADRH and ADRL in Left Justified Sign Data Mode . . . . . . . .313
15-9 ADC Clock Control Register (ADICLK). . . . . . . . . . . . . . . . . .314
16-1 LCD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .319
16-2 LCD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
16-3 Simplified LCD Schematic (1/3 Duty, 1/3 Bias) . . . . . . . . . . .322
16-4 Fast Charge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
16-5 1/3 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . .326
16-6 Static LCD Backplane Driver Waveform. . . . . . . . . . . . . . . . .327
16-7 1/4 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . .327
16-8 Static LCD Frontplane Driver Waveforms. . . . . . . . . . . . . . . .328
16-9 1/3 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . .329
16-10 1/4 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . .330
16-11 1/4 Duty LCD Frontplane Driver Waveforms (continued). . . .331
16-12 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . . .332
16-13 BP0–BP2 and FP0–FP2 Output Waveforms for
7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . .333
16-14 "f" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . .334
16-15 "e" Segment Voltage Waveform. . . . . . . . . . . . . . . . . . . . . . .334
16-16 LCD Control Register (L CDCR) . . . . . . . . . . . . . . . . . . . . . . .335
16-17 LCD Clock Register (LCDCLK). . . . . . . . . . . . . . . . . . . . . . . .337
16-18 LCD Data Registers 1–14 (LDAT1–LDAT14). . . . . . . . . . . . .339
17-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .342
17-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .344
17-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .345
17-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
17-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .347
17-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .349
17-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
Freescale Semiconductor List of Figures 27
List of Figures
Figure Title Page
17-8 Port B LED Control Register (LEDB) . . . . . . . . . . . . . . . . . . .350
17-9 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .351
17-10 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .352
17-11 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
17-12 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .354
17-13 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . .355
17-14 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
18-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .359
18-2 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .362
19-1 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .364
19-2 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . .365
19-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .368
19-4 Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . .369
20-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
20-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .374
20-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .375
21-1 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .378
21-2 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .378
22-1 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .385
22-2 Break Module I/O Register Summary. . . . . . . . . . . . . . . . . . .385
22-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . .387
22-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .388
22-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .388
22-6 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .389
22-7 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .390
23-1 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
23-2 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
24-1 52-Pin Low-Profile Quad Flat Pack (Case No. 848D). . . . . . .408
24-2 64-Pin Low-Profile Quad Flat Pack (Case No. 840F). . . . . . .409
24-3 64-Pin Quad Flat Pack (Case No. 840B) . . . . . . . . . . . . . . . .410
Technical Data MC68HC908LJ12 — Rev. 2.1
28 List of Figures Freescale Semiconductor
Technical Data — MC68HC908LJ12
Table Title Page
2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5-1 LVI Trip Point Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
6-2 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8-1 Numeric Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8-3 VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .120
8-2 PRE 1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . .120
9-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9-3 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

List of Tables

10-1 Monitor Mode Signal Requirements and Options. . . . . . . . . .160
10-2 Mode Differences (Vectors) . . . . . . . . . . . . . . . . . . . . . . . . . .162
10-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .164
10-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .165
10-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .166
10-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .166
10-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .167
10-8 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .167
10-9 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .168
10-10 Summary of ROM-Resident Routines . . . . . . . . . . . . . . . . . .171
10-11 PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
10-12 ERARNGE Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
10-13 LDRNGE Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
10-14 MON_PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . .177
10-15 MON_ERARNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . .178
Freescale Semiconductor List of Tables 29
List of Tables
Table Title Page
10-16 ICP_LDRNGE Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
10-17 EE_WRITE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
10-18 EE_READ Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
11-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
11-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .206
12-1 CGMXCLK Frequency for RTC Input Reference . . . . . . . . . .219
13-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
13-2 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
13-3 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
13-4 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
13-5 SCI Pin Functions (Standard and Infrared). . . . . . . . . . . . . . .250
13-6 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .253
13-7 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .264
13-8 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
13-9 SCI Baud Rate Selection Examples. . . . . . . . . . . . . . . . . . . .266
13-10 Infrared Narrow Pulse Selection. . . . . . . . . . . . . . . . . . . . . . .267
14-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
14-2 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
14-3 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
14-4 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .298
15-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
15-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
15-3 ADC Mode Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
16-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
16-3 LCD Bias Voltage Control. . . . . . . . . . . . . . . . . . . . . . . . . . . .336
16-2 Resistor Ladder Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .336
16-4 Fast Charge Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . .337
16-5 LCD Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .338
16-6 LCD Waveform Base Clock Selection . . . . . . . . . . . . . . . . . .338
Technical Data MC68HC908LJ12 — Rev. 2.1
30 List of Tables Freescale Semiconductor
List of Tables
Table Title Page
17-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .343
17-2 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
17-3 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
17-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
17-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
18-1 IRQ I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . .359
19-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
21-1 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .381
21-2 LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
23-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .392
23-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
23-3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
23-4 5.0V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .394
23-5 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .396
23-6 5.0V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
23-7 3.3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
23-8 5.0V Oscillator Specifications. . . . . . . . . . . . . . . . . . . . . . . . .398
23-9 3.3V Oscillator Specifications. . . . . . . . . . . . . . . . . . . . . . . . .398
23-10 ADC 5.0V Electrical Characteristics. . . . . . . . . . . . . . . . . . . .399
23-11 ADC 3.3V Electrical Characteristics. . . . . . . . . . . . . . . . . . . .400
23-12 FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . .406
25-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
Freescale Semiconductor List of Tables 31
List of Tables
Technical Data MC68HC908LJ12 — Rev. 2.1
32 List of Tables Freescale Semiconductor
Technical Data — MC68HC908LJ12

1.1 Contents

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
1.6.1 Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . .40
1.6.2 Analog Power Supply Pin (V
1.6.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .41
1.6.4 External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . .41
1.6.5 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .41
1.6.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .41
1.6.7 ADC Voltage High Reference Pin (V
1.6.8 ADC Voltage Low Reference Pin (V
1.6.9 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . .42
1.6.10 Port B I/O Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . .42
1.6.11 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . .42
1.6.12 Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . .42
1.6.13 LCD Backplane and Frontplane
(BP0–BP2, FP0/BP3, FP1–FP18). . . . . . . . . . . . . . . . . .42

Section 1. General Description

). . . . . . . . . . . . . . . . . . . . .40
DDA
). . . . . . . . . . . . . .41
REFH
) . . . . . . . . . . . . . .41
REFL
Freescale Semiconductor General Description 33
General Description

1.2 Introduction

The MC68HC908LJ12 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.

1.3 Features

Features of the MC68HC908LJ12 include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• Maximum internal bus frequency: – 8-MHz at 5V operating voltage – 4-MHz at 3.3V operating voltage
• 32-kHz crystal oscillator clock input with 32MHz internal phase­lock-loop
• Optional continuous crystal oscillator operation in stop mode
• 12k-bytes user program FLASH memory with security1 feature
• 512 bytes of on-chip RAM
• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and PWM capability on each channel
• Real time clock (RTC) with clock, calendar, alarm, and chronograph functions. Selectable periodic interrupt requests for seconds, minutes, hours, days, 2-Hz, 4-Hz, and 100-Hz
• Serial communications interface module (SCI) with infrared (IR) encoder/decoder
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.
Technical Data MC68HC908LJ12 — Rev. 2.1
34 General Description Freescale Semiconductor
General Description
• Serial peripheral interface module (SPI)
•IRQ external interrupt pin with integrated pullup
• 8-bit keyboard wakeup port with programmable pullup
• 32 general-purpose input/output (I/O) pins: – H igh current 8-mA sink capability on PTB2–PTB5 – H igh current 20-mA sink capability on PTB0–PTB1
• 4/3 backplanes and static with maximum 27 frontplanes liquid crystal display (LCD) driver
• 6-channel, 10-bit successive approximation analog-to-digital converter (ADC)
• Resident routines for in-circuit programming and EEPROM emulation
• Low-power design (fully static with stop and wait modes)
• Master reset pin (with integrated pullup) and power-on reset
• Spike filter protection for EMC performance enhancement
• System protection features – Optional computer operating properly (COP) reset, driven by
internal 64-kHz RC oscillator – Low-voltage detection with optional reset or interrupt – Illegal opcode detection with reset – Illegal address detection with reset
• 64-pin quad flat pack (QFP), 64-pin low-profile quad flat pack (LQFP), 52-pin low-profile quad flat pack (LQFP), and die form
• Specific features of the MC68HC908LJ12 in 52-pin LQFP are: – 20 general-purpose I/Os only – H igh current 8-mA sink capability on PTB2–PTB3 only – 4-bit keyboard wakeup port with programmable pullup – No serial peripheral interface module (SPI) – No TIM2 input capture/output compare pins – 4 -channel analog-to-digital converter only
Freescale Semiconductor General Description 35
General Description
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit Index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support

1.4 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908LJ12.
Technical Data MC68HC908LJ12 — Rev. 2.1
36 General Description Freescale Semiconductor
M68HC08 CPU
CPU
REGISTERS
CONTROL AND STATUS REGISTERS — 96 BYTES
USER FLASH — 12,288 BYTES
ARITHMETIC/LOGIC
UNIT (ALU)
INTERNAL BUS
KEYBOARD INTERRUPT
MODULE
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
General Description
PTA7/ADC3 PTA6/ADC2 PTA5/ADC1 PTA4/ADC0
DDRA
PTA3/KBI3**
PORTA
PTA2/KBI2** PTA1/KBI1** PTA0/KBI0**
USER RAM — 512 BYTES
MONITOR ROM — 960 BYTES
USER FLASH VECTOR SPACE — 48 BYTES
CLOCK GENERATOR MODULE OSC1 OSC2
CGMXFC
* RST
* IRQ
VDDA
VDD
VSS
VREFH
VREFL
32.768-kHz OSCILLATOR
PHASE-LOCKED LOOP
SYSTEM INTEGRATION
MODULE
EXTERNAL INTERRUPT
MODULE
COMPUTER OPERATING
PROPERLY MODULE
POWER-ON RESET
MODULE
POWER
ADC REFERENCE
2-CHANNEL TIMER INTERFACE
2-CHANNEL TIMER INTERFACE
* Pin contains integrated pullup device.
** Pin contains integrated pullup device if configured as KBI.
†
High current sink pin, 15mA.
‡
High current sink pin, 8mA.
# Pins available on 64-pin packages only.
MODULE 1
MODULE 2
SERIAL COMMUNICATIONS
INTERFACE MODULE
(WITH INFRARED
ENCODER/DECODER)
REAL TIME CLOCK
MODULE
LIQUID CRYSTAL DISPLAY
DRIVER MODULE
SERIAL PERIPHERAL INTERFACE MODULE
LOW-VOLTAGE INHIBIT
MODULE
DDRB
DDRC
DDRD
PORTB
PORTC
PORTD
PTB7/ADC5 PTB6/ADC4 PTB5/T2CH1 PTB4/T2CH0 PTB3/T1CH1 PTB2/T1CH0 PTB1/RxD PTB0/TxD
PTC7/FP26 PTC6/FP25 PTC5/FP24 PTC4/FP23 PTC3/FP22 PTC2/FP21 PTC1/FP20 PTC0/FP19
FP1–FP18
BP0–BP2
FP0/BP3
PTD7/KBI7** PTD6/KBI6** PTD5/KBI5** PTD4/KBI4** PTD3/SPSCK PTD2/MOSI PTD1/MISO PTD0/SS
†
†
#
‡ ‡ ‡ ‡
#
Figure 1-1. MC68HC908LJ12 Block Diagram
Freescale Semiconductor General Description 37
General Description

1.5 Pin Assignments

PTD4/KBI4
64
FP0/BP3
1
BP2
63
BP1
62
BP0
PTB5/T2CH1
61
60
PTB4/T2CH0
59
PTB2/T1CH0
PTB3/T1CH1
58
57
PTB1/RxD
PTB0/TxD
56
55
CGMXFC
54
OSC2
53
OSC1
52
VSS
51
VDD
50
VDDA
49
48
VREFL
16
2 3 4 5 6 7 8 9 10 11 12 13 14 15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PTD5/KBI5
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP8
PTD6/KBI6
PTD7/KBI7
FP9
FP10
FP11
FP12
31
47 46 45 44 43 42 41 40 39 38 37 36 35 34
32
VREFH
PTB7/ADC5
PTB6/ADC4
PTA7/ADC3
PTA6/ADC2
PTA5/ADC1
PTA4/ADC0
PTA3/KBI3
PTA2/KBI2
PTA1/KBI1
PTA0/KBI0
PTC7/FP26
PTC6/FP25
PTC5/FP24
33
PTD0/SS
IRQ
FP14
FP13
PTD3/SPSCK
FP15
FP16
FP17
FP18
PTC0/FP19
PTD2/MOSI
PTC1/FP20
PTD1/MISO
PTC2/FP21
PTC3/FP22
PTC4/FP23
RST
Figure 1-2. 64-Pin QFP and 64-Pin LQFP Pin Assignment
Technical Data MC68HC908LJ12 — Rev. 2.1
38 General Description Freescale Semiconductor
FP0/BP3
General Description
CGMXFC
OSC2
OSC1
VSS
VDD
41
VDDA
40
39
VREFL
BP2
BP1
BP0
PTB3/T1CH1
PTB2/T1CH0
PTB1/RxD
PTB0/TxD
52
51
50
49
48
47
46
45
44
43
1
42
13
2 3 4 5 6 7 8 9 10 11 12
14
FP13
PTD3/SPSCK
PTD2/MOSI PTD1/MISO
15
16
FP15
FP14
PTD0/SS
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP8
FP9
FP10
FP11
FP12
Pins not available on 52-LQFP package:
PTB7ADC5 PTD7/KBI7
PTB6/ADC4 PTD6/KBI6 PTB5/T2CH1 PTD5/KBI5 PTB4/T2CH0 PTD4/KBI4
Internal pads are unconnected.
17
FP16
18
FP17
19
FP18
20
21
PTC0/FP19
PTC1/FP20
22
23
PTC2/FP21
PTC3/FP22
38 37 36 35 34 33 32
31 30 29 28
24
25
IRQ
PTC4/FP23
26
RST
VREFH
PTA7/ADC3
PTA6/ADC2
PTA5/ADC1
PTA4/ADC0
PTA3/KBI3
PTA2/KBI2
PTA1/KBI1
PTA0/KBI0
PTC7/FP26
PTC6/FP25
27
PTC5/FP24
Figure 1-3. 52-Pin LQFP Pin Assignment
Freescale Semiconductor General Description 39
General Description

1.6 Pin Functions

Description of pin functions are provided here.

1.6.1 Power Supply Pins (VDD and VSS)

VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. VSS must be grounded for proper MCU operation.
1.6.2 Analog Power Supply Pin (V
V
DDA
V
DDA
immunity, route V as close as possible to the package (see Figure 1-4).
)
DDA
is the voltage supply for the analog parts of the MCU. Connect the pin to the same voltage potential as VDD. For maximum noise
via a separate trace and place bypass capacitors
DDA
MCU
V
DD
0.1 µF
C1(a)
+
C2(a)
V
NOTE: Component values shown
DD
represent typical applications.
V
SS
0.1 µF
C1(b)
+
C2(b)
V
DDA
V
DD
Figure 1-4. Power Supply Bypassing
Technical Data MC68HC908LJ12 — Rev. 2.1
40 General Description Freescale Semiconductor

1.6.3 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. The OSC1 pin contains a schmitt-trigger and a spike filter for improved EMC performance. See Section 7. Oscillator (OSC).

1.6.4 External Reset Pin (RST)

A logic 0 on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. A schmitt-trigger and a spike filter is associated with this pin so that the device is more robust to EMC noise.This pin also contains an internal pullup resistor. See Section 9.
System Integration Module (SIM).
General Description

1.6.5 External Interrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Section 18. External Interrupt (IRQ).

1.6.6 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the CGM. See
Section 8. Clock Generator Module (CGM).
1.6.7 ADC Voltage High Reference Pin (V
V
is the voltage input pin for the ADC voltage high reference. See
REFH
REFH
Section 15. Analog-to-Digital Converter (ADC)
1.6.8 ADC Voltage Low Reference Pin (V
V
is the voltage input pin for the ADC voltage low reference. See
REFL
REFL
Section 15. Analog-to-Digital Converter (ADC)
)
)
Freescale Semiconductor General Description 41
General Description
1.6.9 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are special function, bidirectional port pins (Section 17.). PTA7/ADC3–PTA4/ADC0 are shared with the ADC (Section 15.), and PTA3/KBI3–PTA0/KBI0 are shared with the KBI module (Section 19.).
1.6.10 Port B I/O Pins (PTB7–PTB0)
PTB7–PTB0 are special function, bidirectional port pins (Section 17.). PTB0/TxD–PTB1/RxD are shared with the SCI module (Section 13.), PTB5/T2CH1–PTB4/T2CH0 are shared with the TIM2 (Section 11.), PTB3/T1CH1–PTB2/T1CH0 are shared with the TIM1(Section 11.), PTB6/ADC4–PTB7/ADC5 are shared with the ADC (Section 15.).
1.6.11 Port C I/O Pins (PTC7–PTC0)
PTC7–PTC0 are special function, bidirectional port pins (Section 17.). PTC7/FP26–PTC0/FP19 are shared with the LCD frontplane drivers (Section 16.).
1.6.12 Port D I/O Pins (PTD7–PTD0)
PTD7–PTD0 are special function, bidirectional port pins (Section 17.). PTD7/KBI7–PTD4/KBI4 are shared with KBI module (Section 19.). PTD3/SPSCK–PTD0/SS
are shared with SPI module (Section 14.).
1.6.13 LCD Backplane and Frontplane (BP0–BP2, FP0/BP3, FP1–FP18)
BP0–BP2 are the LCD backplane driver pins and FP1– FP18 are the frontplane driver pins. FP0/BP3 is the shared driver pin between FP0 and BP3 (Section 16.).
Technical Data MC68HC908LJ12 — Rev. 2.1
42 General Description Freescale Semiconductor
Technical Data — MC68HC908LJ12

2.1 Contents

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .43
2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44
2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

2.2 Introduction

The CPU08 can address 64k-bytes of memory space. The memory map, shown in Figure 2-1, includes:

Section 2. Memory Map

• 12,288 bytes of user FLASH memory
• 512 bytes of random-access memory (RAM)
• 48 bytes of user-defined vectors
• 960 bytes of monitor ROM

2.3 Unimplemented Memory Locations

Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded.
Freescale Semiconductor Memory Map 43
Memory Map

2.4 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R.

2.5 Input/Output (I/O) Section

Most of the control, status, and data registers are in the zero page area of $0000–$005F. Additional I/O registers have these addresses:
• $FE00; SIM break status register, SBSR
• $FE01; SIM reset status register, SRSR
• $FE02; Reserved
• $FE03; SIM break flag control register, SBFCR
• $FE04; Interrupt status register 1, INT1
• $FE05; Interrupt status register 2, INT2
• $FE06; Interrupt status register 3, INT3
• $FE07; Reserved
• $FE08; FLASH control register, FLCR
• $FE09; FLASH block protect register, FLBPR
• $FE0A; Reserved
• $FE0B; Reserved
• $FE0C; Break address register high, BRKH
• $FE0D; Break address register low, BRKL
• $FE0E; Break status and control register, BRKSCR
• $FE0F; LVI status register, LVISR
• $FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
Technical Data MC68HC908LJ12 — Rev. 2.1
44 Memory Map Freescale Semiconductor
Memory Map
$0000
↓
$005F $0060
↓
$025F $0260
↓
$BFFF $C000
↓
$EFFF
$F000
↓
$FBFF $FC00
↓
$FDFF $FE00 SIM Break Status Register (SBSR) $FE01 SIM Reset Status Register (SRSR) $FE02 Reserved $FE03 SIM Break Flag Control Register (SBFCR) $FE04 Interrupt Status Register 1 (INT1) $FE05 Interrupt Status Register 2 (INT2) $FE06 Interrupt Status Register 3 (INT3) $FE07 Reserved $FE08 FLASH Control Register (FLCR) $FE09 FLASH Block Protect Register (FLBPR) $FE0A Reserved $FE0B Reserved $FE0C Break Address Register High (BRKH) $FE0D Break Address Register Low (BRKL) $FE0E Break Status and Control Register (BRKSCR) $FE0F LVI Status Register (LVISR) $FE10
↓
$FFCF $FFD0
↓
$FFFF
I/O Registers
96 Bytes
RAM
512 Bytes
Unimplemented
48,544 Bytes
FLASH Memory
12,288 Bytes
Unimplemented
3,072 Bytes
Monitor ROM 1
512 Bytes
Monitor ROM 2
448 Bytes
FLASH Vectors
48 Bytes
Figure 2-1. Memory Map
Freescale Semiconductor Memory Map 45
Memory Map
Addr.Register Name Bit 7654321Bit 0
Read:
$0000
$0001
$0002
$0003
$0004
$0005
Port A Data Register
(PTA)
Port B Data Register
(PTB)
Port C Data Register
(PTC)
Port D Data Register
(PTD)
Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Data Direction Register C
$0006
Data Direction Register D
$0007
$0008 Unimplemented
$0009 Unimplemented
(DDRC)
(DDRD)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 12)
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset:00000000
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
Read:
Write:
Reset:
Read:
Write:
Reset:
= Unimplemented R = Reserved
Technical Data MC68HC908LJ12 — Rev. 2.1
46 Memory Map Freescale Semiconductor
Memory Map
Addr.Register Name Bit 7654321Bit 0
Read:
$000A Unimplemented
$000B Unimplemented
Port B LED Control
$000C
$000D Unimplemented
$000E
$000F Unimplemented
Register
(LEDB)
Unimplemented
Write:
Reset:
Read:
Write:
Reset:
Read: 0 0
LEDB5 LEDB4 LEDB3 LEDB2 LEDB1 LEDB0
Write:
Reset:00000000
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
$0010
$0011
$0012
$0013
Read:
SPI Control Register
(SPCR)
SPI Status and Control
Register
(SPSCR)
SPI Data Register
(SPDR)
SCI Control Register 1
(SCC1)
U = Unaffected X = Indeterminate
Write:
Reset:00101000
Read: SPRF
Write:
Reset:00001000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:UUUUUUUU
Read:
Write:
Reset:00000000
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12)
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
ERRIE
LOOPS ENSCI
OVRF MODF SPTE
MODFEN SPR1 SPR0
0
M WAKE ILTY PEN PTY
= Unimplemented R = Reserved
Freescale Semiconductor Memory Map 47
Memory Map
Addr.Register Name Bit 7654321Bit 0
Read:
$0014
$0015
$0016
$0017
$0018
$0019
SCI Control Register 2
(SCC2)
SCI Control Register 3
(SCC3)
SCI Status Register 1
(SCS1)
SCI Status Register 2
(SCS2)
SCI Data Register
(SCDR)
SCI Baud Rate Register
(SCBR)
Write:
Reset:00000000
Read: R8
Write:
Reset:
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
Read: 000000BKFRPF
Write:
Reset:00000000
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset:
Read:
Write:
Reset:00000000
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
T8 DMARE DMATE ORIE NEIE FEIE PEIE
UU
UUUUUUUU
0
CKS
000000
SCP1 SCP0 R SCR2 SCR1 SCR0
$001A
$001B
$001C
$001D
SCI Infrared Control
Register
(SCIRCR)
Keyboard Status and
Control Register
(KBSCR)
Keyboard Interrupt
Enable Register
(KBIER)
Configuration Register 2
(CONFIG2)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 12)
Read:
Write:
Reset:00000000
Read: 0000KEYF 0
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: 0
Write:
†
Reset:0000000††0
R
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
000
STOP_ IRCDIS
STOP_
XCLKEN
DIV2CLK PCEH PCEL LVISEL1 LVISEL0
= Unimplemented R = Reserved
R TNP1 TNP0 IREN
IMASKK MODEK
ACKK
††
Technical Data MC68HC908LJ12 — Rev. 2.1
48 Memory Map Freescale Semiconductor
Memory Map
Addr.Register Name Bit 7654321Bit 0
IRQ Status and Control
$001E
$001F
† One-time writable register after each reset. †† Reset by POR only.
$0020
$0021
$0022
Configuration Register 1
Timer 1 Status and
Register
(INTSCR)
(CONFIG1)
Control Register
(T1SC)
Timer 1 Counter
Register High
(T1CNTH)
Timer 1 Counter
Register Low
(T1CNTL)
Read: 0000IRQF0
Write: ACK
Reset:00000000
Read:
Write:
†
Reset:00010000
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
COPRS LVISTOP LVIRSTD LVIPWRD
00
TOIE TSTOP
IMASK MODE
0
SSREC STOP COPD
PS2 PS1 PS0
$0023
$0024
$0025
$0026
Timer 1 Counter Modulo
Register High
(T1MODH)
Timer 1 Counter Modulo
Register Low
(T1MODL)
Timer 1 Channel 0 Status
and Control Register
(T1SC0)
Timer 1 Channel 0
Register High
(T1CH0H)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 12)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:XXXXXXXX
= Unimplemented R = Reserved
Freescale Semiconductor Memory Map 49
Memory Map
Addr.Register Name Bit 7654321Bit 0
Timer 1 Channel 0
$0027
Timer 1 Channel 1 Status
$0028
$0029
$002A
$002B
$002C
Register Low
(T1CH0L)
and Control Register
(T1SC1)
Timer 1 Channel 1
Register High
(T1CH1H)
Timer 1 Channel 1
Register Low
(T1CH1L)
Timer 2 Status and
Control Register
(T2SC)
Timer 2 Counter
Register High
(T2CNTH)
Read:
Write:
Reset:XXXXXXXX
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read: TOF
Write: 0 TRST
Reset:00100000
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
Bit 7654321Bit 0
CH1IE
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
TOIE TSTOP
0
MS1A ELS1B ELS1A TOV1 CH1MAX
00
PS2 PS1 PS0
$002D
$002E
$002F
$0030
Timer 2 Counter
Register Low
(T2CNTL)
Timer 2 Counter Modulo
Register High
(T2MODH)
Timer 2 Counter Modulo
Register Low
(T2MODL)
Timer 2 Channel 0 Status
and Control Register
(T2SC0)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 12)
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
= Unimplemented R = Reserved
Technical Data MC68HC908LJ12 — Rev. 2.1
50 Memory Map Freescale Semiconductor
Memory Map
Addr.Register Name Bit 7654321Bit 0
$0031
$0032
$0033
$0034
$0035
$0036
Timer 2 Channel 0
Register High
(T2CH0H)
Timer 2 Channel 0
Register Low
(T2CH0L)
Timer 2 Channel 1 Status
and Control Register
(T2SC1)
Timer 2 Channel 1
Register High
(T2CH1H)
Timer 2 Channel 1
Register Low
(T2CH1L)
PLL Control Register
(PTCL)
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read: CH1F
Write: 0
Reset:00000000
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:XXXXXXXX
Read:
Write:
Reset:00100000
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
CH1IE
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
PLLF
PLLIE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
PLLON BCS PRE1 PRE0 VPR1 VPR0
$0037
$0038
$0039
$003A
PLL Bandwidth Control
Register (PBWC)
PLL Multiplier Select
Register High
(PMSH)
PLL Multiplier Select
Register Low
(PMSL)
PLL VCO Range Select
Register
(PMRS)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 12)
Read:
AUTO
Write:
Reset:00000000
Read: 0000
Write:
Reset:00000000
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
LOCK
ACQ
0000
R
MUL11 MUL10 MUL9 MUL8
= Unimplemented R = Reserved
Freescale Semiconductor Memory Map 51
Memory Map
Addr.Register Name Bit 7654321Bit 0
PLL Reference Divider
$003B
ADC Status and Control
$003C
$003D
$003E
$003F
ADC Data Register High
ADC Data Register Low
$0040
Select Register
(PMDS)
Register
(ADSCR)
(ADRH)
(ADRL)
ADC Clock Register
(ADCLK)
Unimplemented
Read: 0000
Write:
Reset:
Read: COCO
Write:
Reset:00011111
Read: ADx ADx ADx ADx ADx ADx ADx ADx
Write:RRRRRRRR
Reset:00000000
Read: ADx ADx ADx ADx ADx ADx ADx ADx
Write:RRRRRRRR
Reset:00000000
Read:
Write:
Reset:00000100
Read:
Write:
0
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
00
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
0
RDS3 RDS2 RDS1 RDS0
0001
00
R
$0041 Unimplemented
$0042
$0043
$0044
RTC Control Register 1
(RTCCR1)
RTC Control Register 2
(RTCCR2)
RTC Status Register
(RTCSR)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 12)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:00000000
Read: 0
Write: R CHRCLR
Reset:00000000
Read: ALMF CHRF DAYF HRF MINF SECF TB1F TB2F
Write:
Reset:00000000
ALMIE CHRIE DAYIE HRIE MINIE SECIE TB1IE TB2IE
0
CHRE RTCE
= Unimplemented R = Reserved
0
XTL2 XTL1 XTL0
Technical Data MC68HC908LJ12 — Rev. 2.1
52 Memory Map Freescale Semiconductor
Memory Map
Addr.Register Name Bit 7654321Bit 0
$0045
$0046
$0047
$0048
$0049
$004A
Alarm Minute Register
(ALMR)
Alarm Hour Register
(ALHR)
Second Register
(SECR)
Minute Register
(MINR)
Hour Register
(HRR)
Day Register
(DAYR)
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: 0 0
Write:
Reset:00000000
Read: 0 0
Write:
Reset:00000000
Read: 0 0 0
Write:
Reset:00000000
Read: 0 0 0
Write:
Reset:00000001
00
AM5 AM4 AM3 AM2 AM1 AM0
000
AH4 AH3 AH2 AH1 AH0
SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
MIN5 MIN4 MIN3 MIN2 MIN1 MIN0
HR4 HR3 HR2 HR1 HR0
DAY4 DAY3 DAY2 DAY1 DAY0
$004B
$004C
$004D
$004E
Read: 0000
Month Register
(MTHR)
Year Register
(YRR)
Day-Of-Week Register
(DOWR)
Chronograph Data
Register
(CHRR)
U = Unaffected X = Indeterminate
Write:
Reset:00000001
Read:
Write:
Reset:00000000
Read: 00000
Write:
Reset:00000000
Read: 0 CHR6 CHR5 CHR4 CHR3 CHR2 CHR1 CHR0
Write:
Reset:00000000
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 12)
MTH3 MTH2 MTH1 MTH0
YR7 YR6 YR5 YR4 YR3 YR2 YR1 YR0
DOW2 DOW1 DOW0
= Unimplemented R = Reserved
Freescale Semiconductor Memory Map 53
Memory Map
Addr.Register Name Bit 7654321Bit 0
$004F
$0050 Reserved
$0051
$0052
$0053
$0054
LCD Clock Register
LCD Control Register
LCD Data Register 1
LCD Data Register 2
LCD Data Register 3
(LCDCLK)
(LCDCR)
(LDAT1)
(LDAT2)
(LDAT3)
Read: 0
Write:
Reset:00000000
Read:
RRRRRRRR
Write:
Reset:
Read:
LCDE
Write:
Reset:00000000
Read:
F1B3 F1B2 F1B1 F1B0 F0B3 F0B2 F0B1 F0B0
Write:
Reset:UUUUUUUU
Read:
F3B3 F3B2 F3B1 F3B0 F2B3 F2B2 F2B1 F2B0
Write:
Reset:UUUUUUUU
Read:
F5B3 F5B2 F5B1 F5B0 F4B3 F4B2 F4B1 F4B0
Write:
Reset:UUUUUUUU
FCCTL1 FCCTL0 DUTY1 DUTY0 LCLK2 LCLK1 LCLK0
0
FC LC LCCON3 LCCON2 LCCON1 LCCON0
$0055
$0056
$0057
$0058
Read:
LCD Data Register 4
(LDAT4)
LCD Data Register 5
(LDAT5)
LCD Data Register 6
(LDAT6)
LCD Data Register 7
(LDAT7)
U = Unaffected X = Indeterminate
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
Read:
Write:
Reset:UUUUUUUU
F7B3 F7B2 F7B1 F7B0 F6B3 F6B2 F6B1 F6B0
F9B3 F9B2 F9B1 F9B0 F8B3 F8B2 F8B1 F8B0
F11B3 F11B2 F11B1 F11B0 F10B3 F10B2 F10B1 F10B0
F13B3 F13B2 F13B1 F13B0 F12B3 F12B2 F12B1 F12B0
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 12)
Technical Data MC68HC908LJ12 — Rev. 2.1
54 Memory Map Freescale Semiconductor
Memory Map
Addr.Register Name Bit 7654321Bit 0
$0059
$005A
$005B
$005C
$005D
$005E
LCD Data Register 8
(LDAT8)
LCD Data Register 9
(LDAT9)
LCD Data Register 10
(LDAT10)
LCD Data Register 11
(LDAT11)
LCD Data Register 12
(LDAT12)
LCD Data Register 13
(LDAT13)
Read:
F15B3 F15B2 F15B1 F15B0 F14B3 F14B2 F14B1 F14B0
Write:
Reset:UUUUUUUU
Read:
F17B3 F17B2 F17B1 F17B0 F16B3 F16B2 F16B1 F16B0
Write:
Reset:UUUUUUUU
Read:
F19B3 F19B2 F19B1 F19B0 F18B3 F18B2 F18B1 F18B0
Write:
Reset:UUUUUUUU
Read:
F21B3 F21B2 F21B1 F21B0 F20B3 F20B2 F20B1 F20B0
Write:
Reset:UUUUUUUU
Read:
F23B3 F23B2 F23B1 F23B0 F22B3 F22B2 F22B1 F22B0
Write:
Reset:UUUUUUUU
Read:
F25B3 F25B2 F25B1 F25B0 F24B3 F24B2 F24B1 F24B0
Write:
Reset:UUUUUUUU
$005F
$FE00
Note: Writing a logic 0 clears SBSW.
$FE01
LCD Data Register 14
(LDAT14)
SIM Break Status Register
(SBSR)
SIM Reset Status Register
(SRSR)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12)
Read:
Write:
Reset:UUUUUUUU
Read:
RRRRRR
Write: Note
Reset: 0
Read: POR PIN COP ILOP ILAD 0 LVI 0
Write:
POR:10000000
= Unimplemented R = Reserved
F26B3 F26B2 F26B1 F26B0
SBSW
R
Freescale Semiconductor Memory Map 55
Memory Map
Addr.Register Name Bit 7654321Bit 0
$FE02 Reserved
SIM Break Flag Control
$FE03
Interrupt Status Register 1
$FE04
Interrupt Status Register 2
$FE05
Interrupt Status Register 3
$FE06
$FE07 Reserved
Register
(SBFCR)
(INT1)
(INT2)
(INT3)
Read:
RRRRRRRR
Write:
Reset:
Read:
BCFERRRRRRR
Write:
Reset: 0
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
Read: 00000IF17IF16IF15
Write:RRRRRRRR
Reset:00000000
Read:
RRRRRRRR
Write:
$FE08
$FE09
$FE0A Reserved
$FE0B Reserved
FLASH Control Register
(FLCR)
FLASH Block Protect
Register
(FLBPR)
U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 12)
Reset:
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset:00000000
Read:
RRRRRRRR
Write:
Reset:
Read:
RRRRRRRR
Write:
Reset:
= Unimplemented R = Reserved
Technical Data MC68HC908LJ12 — Rev. 2.1
56 Memory Map Freescale Semiconductor
Memory Map
Addr.Register Name Bit 7654321Bit 0
$FE0C
$FE0D
Break Status and Control
$FE0E
Low-Voltage Inhibit Status
$FE0F
$FFFF
COP Control Register
Break Address
Register High
(BRKH)
Break Address
Register Low
(BRKL)
Register
(BRKSCR)
Register
(LVISR)
(COPCTL)
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read:
Write:
Reset:00000000
Read: LVIOUT
Write:
Reset:00000000
Read: Low byte of reset vector
Write: Writing clears COP counter (any value)
Reset: Unaffected by reset
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7654321Bit 0
000000
BRKE BRKA
LVIIF00000
LVIIE
LVIIAK
U = Unaffected X = Indeterminate
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 12)
Freescale Semiconductor Memory Map 57
Memory Map
Table 2-1. Vector Addresses
.
Priority INT Flag Address Vector
Lowest
Highest
IF17
IF16
IF15
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
—
$FFDA Real Time Clock Vector (High) $FFDB Real Time Clock Vector (Low) $FFDC ADC Conversion Complete Vector (High) $FFDD ADC Conversion Complete Vector (Low) $FFDE Keybo ard Vector (High) $FFDF Keyboard Vector (Low)
$FFE0 SCI Transmit Vector (High) $FFE1 SCI Transmit Vector (Low) $FFE2 SCI Receive Vector (High) $FFE3 SCI Receive Vector (Low) $FFE4 SCI Error Vector (High) $FFE5 SCI Error Vector (Low) $FFE6 SPI Receive Vector (High) $FFE7 SPI Receive Vector (Low) $FFE8 SPI Transmit Vector (High)
$FFE9 SPI Transmit Vector (Low) $FFEA TIM2 Overflow Vector (High) $FFEB TIM2 Overflow Vector (Low) $FFEC TIM2 Channel 1 Vector (High) $FFED TIM2 Channel 1 Vector (Low) $FFEE TIM2 Channel 0 Vector (High) $FFEF TIM2 Channel 0 Vector (Low)
$FFF0 TIM1 Overflow Vector (High)
$FFF1 TIM1 Overflow Vector (Low)
$FFF2 TIM1 Channel 1 Vector (High)
$FFF3 TIM1 Channel 1 Vector (Low)
$FFF4 TIM1 Channel 0 Vector (High)
$FFF5 TIM1 Channel 0 Vector (Low)
$FFF6 PLL Vector (High)
$FFF7 PLL Vector (Low)
$FFF8 LVI Vector (High)
$FFF9 LVI Vector (Low)
$FFFA IRQ $FFFB IRQ $FFFC SWI Vector (High) $FFFD SWI Vector (Low) $FFFE Reset Vector (High)
$FFFF Reset Vector (Low)
Vector (High) Vector (Low)
Technical Data MC68HC908LJ12 — Rev. 2.1
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Technical Data — MC68HC908LJ12

Section 3. Random-Access Memory (RAM)

3.1 Contents

3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.2 Introduction

This section describes the 512 bytes of RAM (random-access memory).

3.3 Functional Description

Addresses $0060 through $025F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64k-byte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.
NOTE: For M6805 compatibility, the H register is not stacked.
Freescale Semiconductor Random-Access Memory (RAM) 59
Random-Access Memory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking operation.
Technical Data MC68HC908LJ12 — Rev. 2.1
60 Random-Access Memory (RAM) Freescale Semiconductor
Technical Data — MC68HC908LJ12

Section 4. FLASH Memory (FLASH)

4.1 Contents

4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .64
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .65
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.8 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.8.1 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .68

4.2 Introduction

This section describes the operation of the embedded FLASH memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.
Freescale Semiconductor FLASH Memory (FLASH) 61
FLASH Memory (FLASH)
Addr.Register Name Bit 7654321Bit 0
$FE08
$FE09
FLASH Control Register
(FLCR)
FLASH Block Protect
Register
(FLBPR)
Reset:00000000
Reset:00000000

4.3 Functional Description

The FLASH memory consists of an array of 12,288 bytes for user memory plus a block of 48 bytes for user interrupt vectors. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. The FLASH memory page size is defined as 128 bytes, and is the minimum size that can be erased in a page erase operation. Program and erase operations are facilitated through control bits in FLASH control register (FLCR). The address ranges for the FLASH memory are:
Read: 0000
HVEN MASS ERASE PGM
Write:
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
= Unimplemented
Figure 4-1. FLASH I/O Register Summary
• $C000–$EFFF; user memory; 12,288 bytes
• $FFD0–$FFFF; user interrupt vectors; 48 bytes
Programming tools are available from Freescale. Contact your local Freescale representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.
1. No security feature is absolutely secure. However, Freescale’s strategy
Technical Data MC68HC908LJ12 — Rev. 2.1
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62 FLASH Memory (FLASH) Freescale Semiconductor

4.4 FLASH Control Register

The FLASH control register (FLCR) controls FLASH program and erase operations.
Address: $FE08
FLASH Memory (FLASH)
Bit 7654321Bit 0
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
Figure 4-2. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed.
1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or block erase operation when the ERASE bit is set.
1 = Mass Erase operation selected 0 = Block Erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected 0 = Erase operation not selected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected 0 = Program operation not selected
Freescale Semiconductor FLASH Memory (FLASH) 63
FLASH Memory (FLASH)

4.5 FLASH Page Erase Operation

Use the following procedure to erase a page of FLASH memory. A page consists of 128 consecutive bytes starting from addresses $xx00 or $xx80. The 48-byte user interrupt vectors area also forms a page. The
48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Write any data to any FLASH address within the page address range desired.
3. Wait for a time, t
(at least 10µs).
nvs
4. Set the HVEN bit.
5. Wait for a time, t
erase
(1ms).
6. Clear the ERASE bit.
7. Wait for a time, t
8. Clear the HVEN bit.
9. After time, t
rcv
mode.
NOTE: Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
(5µs).
nvh
(1µs), the memory can be accessed again in read
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64 FLASH Memory (FLASH) Freescale Semiconductor

4.6 FLASH Mass Erase Operation

Use the following procedure to erase the entire FLASH memory to read as logic 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
2. Write any data to any FLASH address within the FLASH memory address range.
FLASH Memory (FLASH)
3. Wait for a time, t
(10µs).
nvs
4. Set the HVEN bit.
5. Wait for a time t
merase
(4ms).
6. Clear the ERASE bit.
7. Wait for a time, t
nvhl
(100µs).
8. Clear the HVEN bit.
9. After time, t
(1µs), the memory can be accessed again in read
rcv
mode.
NOTE: Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
Freescale Semiconductor FLASH Memory (FLASH) 65
FLASH Memory (FLASH)

4.7 FLASH Program Operation

Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80, or $xxC0. The procedure for programming a row of the FLASH memory is outlined below:
1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming.
2. Write any data to any FLASH address within the row address range desired.
3. Wait for a time, t
(10µs).
nvs
4. Set the HVEN bit.
5. Wait for a time, t
pgs
(5µs).
6. Write data to the FLASH address to be programmed.
7. Wait for time, t
prog
(30µs).
8. Repeat step 6 and 7 until all the bytes within the row are programmed.
9. Clear the PGM bit.
10. Wait for time, t
11. Clear the HVEN bit.
12. After time, t
rcv
mode.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE: Programming and erasing of FLASH locations cannot be performed by
executing code from the FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Do not exceed t
Characteristics.
maximum. See 23.18 FLASH Memory
prog
(5µs).
nvh
(1µs), the memory can be accessed again in read
Figure 4-3 shows a flowchart representation for programming the
FLASH memory.
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66 FLASH Memory (FLASH) Freescale Semiconductor
FLASH Memory (FLASH)
Algorithm for programming a row (64 bytes) of FLASH memory
1
2
Write any data to any FLASH address
Set PGM bit
within the row address range desired
3
4
5
6
Wait for a time, t
Set HVEN bit
Wait for a time, t
Write data to the FLASH address to be programmed
7
Wait for a time, t
nvs
pgs
prog
Completed
programming
this row?
NOTE:
The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step 9) must not exceed the maximum programming
PROG
max.
time, t
This row program algorithm assumes the row/s to be programmed are initially erased.
Figure 4-3. FLASH Programming Flowchart
Y
N
9
10
11
12
Clear PGM bit
Wait for a time, t
Clear HVEN bit
Wait for a time, t
nvh
rcv
End of Programming
Freescale Semiconductor FLASH Memory (FLASH) 67
FLASH Memory (FLASH)

4.8 FLASH Protection

Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect pages of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program operations.
NOTE: When the FLBPR is cleared (all 0’s), the entire FLASH memory is
protected from being programmed and erased. When all the bits are set, the entire FLASH memory is accessible for program and erase.

4.8.1 FLASH Block Protect Register

The FLASH block protect register is implemented as an 8-bit I/O register. The content of this register determine the starting location of the protected range within the FLASH memory.
Address: $FE09
Read:
Write:
Reset:00000000
BPR[7:0] — FLASH Block Protect Register Bit 7 to Bit 0
BPR[7:1] represent bits [13:7] of a 16-bit memory address. Bits [15:14] are logic 1’s and bits [6:0] are logic 0’s.
Bit 7654321Bit 0
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Figure 4-4. FLASH Block Protect Register (FLBPR)
16-bit memory address
Start address of FLASH block protect 11 0000000
BPR[7:1]
Figure 4-5. FLASH Block Protect Start Address
Technical Data MC68HC908LJ12 — Rev. 2.1
68 FLASH Memory (FLASH) Freescale Semiconductor
FLASH Memory (FLASH)
BPR0 is used only for BPR[7:0] = $FF, for no block protection. The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00 or XX80 (at page boundaries — 128 bytes) within the FLASH memory.
Examples of protect start address:
BPR[7:0] Start of Address of Protect Range
$00 or $01
$02 or $03 $C080 (1100 0000 1000 0000) $04 or $05 $C100 (1100 0001 0000 0000) $06 or $07 $C180 (1100 0001 1000 0000) $08 or $09 $C200 (1100 0010 0000 0000)
and so on...
$F8 or $F9 $FE00 (1111 1110 0000 0000)
$FA or $FB $FE80 (1111 1110 1000 0000)
$FC or $FD $FF00 (1111 1111 0000 0000)
$FE $FF80 (1111 1111 1000 0000)
$FF The entire FLASH memory is not protected.
Note: The end address of the protected range is always $FFFF.
$C000 (1100 0000 0000 0000)
The entire FLASH memory is protected.
Freescale Semiconductor FLASH Memory (FLASH) 69
FLASH Memory (FLASH)
Technical Data MC68HC908LJ12 — Rev. 2.1
70 FLASH Memory (FLASH) Freescale Semiconductor
Technical Data — MC68HC908LJ12

Section 5. Configuration Registers (CONFIG)

5.1 Contents

5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5.4 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .73
5.5 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .75

5.2 Introduction

This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options:
• Computer operating properly module (COP)
• COP timeout period (218 – 24 or 213 – 24 ICLK cycles)
• Low-voltage inhibit (LVI) module power
• LVI module reset
• LVI module in stop mode
• LVI module voltage trip point selection
• STOP instruction
• Stop mode recovery time (32 ICLK cycles or 4096 ICLK cycles)
• Oscillator during stop mode
• LCD frontplanes FP19–FP26 on port C
Freescale Semiconductor Configuration Registers (CONFIG) 71
Configuration Registers (CONFIG)
Addr.Register Name Bit 7654321Bit 0
$001D
$001F
† One-time writable register after each reset.
†† Reset by POR only.
Configuration Register 2
(CONFIG2)
Configuration Register 1
(CONFIG1)
†
Reset:0000000††0
†
Reset:00010000

5.3 Functional Description

The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that these registers be written immediately after reset. The configuration registers are located at $001D and $001F. The configuration registers may be read at anytime.
Read: 0
Write:
Read:
COPRS LVISTOP LVIRSTD LVIPWRD
Write:
STOP_ IRCDIS
= Unimplemented
STOP_
XCLKEN
DIV2CLK PCEH PCEL LVISEL1 LVISEL0
Figure 5-1. CONFIG Registers Summary
††
0
SSREC STOP COPD
NOTE: The options except LVISEL[1:0] are one-time writable by the user after
each reset. The LVISEL[1:0] bits are one-time writable by the user only after each POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-2 and Figure 5-3.
Technical Data MC68HC908LJ12 — Rev. 2.1
72 Configuration Registers (CONFIG) Freescale Semiconductor

5.4 Configuration Register 1 (CONFIG1)

Address: $001F
Bit 7654321Bit 0
Configuration Registers (CONFIG)
Read:
COPRS LVISTOP LVIRSTD LVIPWRD
Write:
Reset:00010000
= Unimplemented
0
SSREC STOP COPD
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS. (See
Section 20. Computer Operating Properly (COP).)
1 = COP time out period = 213 – 24 ICLK cycles 0 = COP time out period = 218 – 24 ICLK cycles
LVISTOP — LVI Enable in Stop Mode
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. (See
Section 21. Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode 0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable
LVIRSTD disables the reset signal from the LVI module. (See
Section 21. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled 0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 21. Low-Voltage
Inhibit (LVI).) Reset sets LVIPWRD.
1 = LVI module power disabled 0 = LVI module power enabled
Freescale Semiconductor Configuration Registers (CONFIG) 73
Configuration Registers (CONFIG)
SSREC — Short Stop Recovery
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles 0 = Stop mode recovery after 4096 ICLK cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
NOTE: When the LVISTOP is enabled, the system stabilization time for power
on reset and long stop recovery (both 4096 ICLK cycles) gives a delay longer than the enable time for the LVI. There is no period where the MCU is not protected from a low power condition. However, when using the short stop recovery configuration option, the 32 ICLK delay is less than the LVI’s turn-on time and there exists a period in start-up where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable
STOP enables the STOP instruction.
1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 20. Computer
Operating Properly (COP).)
1 = COP module disabled 0 = COP module enabled
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74 Configuration Registers (CONFIG) Freescale Semiconductor

5.5 Configuration Register 2 (CONFIG2)

Address: $001D
Bit 7654321Bit 0
Configuration Registers (CONFIG)
Read: 0
Write:
Reset:0000000††0
STOP_ IRCDIS
= Unimplemented †† Reset by POR only.
STOP_
XCLKEN
DIV2CLK PCEH PCEL LVISEL1 LVISEL0
Figure 5-3. Configuration Register 2 (CONFIG2)
STOP_IRCDIS — Internal RC Oscillator Stop Mode Disable
Setting STOP_IRCDIS disables the internal RC oscillator during stop mode. When this bit is cleared, the internal RC oscillator continues to operate in stop mode. Reset clears this bit.
1 = Internal RC oscillator disabled during stop mode 0 = Internal RC oscillator enabled during stop mode
STOP_XCLKEN — Crystal Oscillator Stop Mode Enable
Setting STOP_XCLKEN enables the external crystal (XTAL) oscillator to continue operating during stop mode. This is useful for driving the real time clock module to allow it to generate periodic wake-up while in stop mode. When this bit is cleared, the external XTAL oscillator will be disabled during stop mode. Reset clears this bit.
1 = XTAL oscillator enabled during stop mode 0 = XTAL oscillator disabled during stop mode
††
DIV2CLK — Divide-by-2 Clock Bypass
When CGMXCLK is selected to drive the system clocks (BCS=0), setting DIV2CLK allows the CGMXCLK to bypass the divide-by-2 divider in the CGM module; CGMOUT will equal CGMXCLK and bus clock will equal CGMXCLK divide-by-2.
DIV2CLK bit has no effect when the BCS=1 in the PLL control register (CGMVCLK selected and divide-by-2 always enabled). Reset clears this bit.
1 = Divide-by-2 divider bypassed;
When BSC=0, CGMOUT equals CGMXCLK
0 = Divide-by-2 divider enabled;
When BSC=0, CGMOUT equals CGMXCLK divide-by-2
Freescale Semiconductor Configuration Registers (CONFIG) 75
Configuration Registers (CONFIG)
PCEH — Port C Enable High Nibble
Setting PCEH configures the PTC4/FP23–PTC7/FP26 pins for LCD frontplane driver use. Reset clears this bit.
1 = PTC4/FP23–PTC7/FP26 pins configured as LCD frontplane
driver pins: FP23–FP26
0 = PTC4/FP23–PTC7/FP26 pins configured as standard I/O pins:
PTC4–PTC7
PCEL — Port C Enable Low Nibble
Setting PCEL configures the PTC0/FP19–PTC3/FP22 pins for LCD frontplane driver use. Reset clears this bit.
1 = PTC0/FP19–PTC3/FP22 pins configured as LCD frontplane
driver pins: FP19–FP22
0 = PTC0/FP19–PTC3/FP22 pins configured as standard I/O pins:
PTC0–PTC3
LVISEL[1:0] — LVI Operating Mode Selection
LVISEL[1:0] selects the voltage operating mode of the LVI module. (See Section 21. Low-Voltage Inhibit (LVI).) The voltage mode selected for the LVI should match the operating VDD. See Section 23.
Electrical Specifications for the LVI voltage trip points for each of
the modes.
LVISEL1 LVISEL0 Operating Mode
00Reserved (2.5V) 01 3V 10 5V 11 Reserved
Table 5-1. LVI Trip Point Selection
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76 Configuration Registers (CONFIG) Freescale Semiconductor
Technical Data — MC68HC908LJ12

Section 6. Central Processor Unit (CPU)

6.1 Contents

6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Freescale Semiconductor Central Processor Unit (CPU) 77
Central Processor Unit (CPU)

6.2 Introduction

The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.

6.3 Features

Feature of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-Bit index register with X-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range beyond 64-Kbytes
• Low-power stop and wait modes
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6.4 CPU Registers

Central Processor Unit (CPU)
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.

6.4.1 Accumulator

7
15
H X
15
15
70 V11HINZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 6-2. Accumulator (A)
Freescale Semiconductor Central Processor Unit (CPU) 79
Central Processor Unit (CPU)

6.4.2 Index Register

The 16-bit index register allows indexed addressing of a 64K-byte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.

6.4.3 Stack Pointer

Bit
1413121110987654321
15
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Bit
0
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
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80 Central Processor Unit (CPU) Freescale Semiconductor
NOTE: The location of the stack is arbitrary and may be relocated anywhere in

6.4.4 Program Counter

Central Processor Unit (CPU)
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
1413121110987654321
15
Read:
Write:
Reset: Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Bit
0
Freescale Semiconductor Central Processor Unit (CPU) 81
Central Processor Unit (CPU)

6.4.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:
V11HI NZC
X1 1X1XXX
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow 0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add­with-carry (ADC) operation. The half-carry flag is required for binary­coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4
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Central Processor Unit (CPU)
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled 0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result.
1 = Negative result 0 = Non-negative result
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00.
1 = Zero result 0 = Non-zero result
Freescale Semiconductor Central Processor Unit (CPU) 83
Central Processor Unit (CPU)
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7 0 = No carry out of bit 7

6.5 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (Freescale document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.

6.6 Low-Power Modes

6.6.1 Wait Mode

The WAIT and STOP ins tr uc ti on s put the MCU in l o w p o w e r- c o ns u m p ti o n standby modes.
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock.
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84 Central Processor Unit (CPU) Freescale Semiconductor

6.6.2 Stop Mode

The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock.
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.

6.7 CPU During Break Interrupts

If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. (See Section 22. Break Module (BRK).) The program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).
Central Processor Unit (CPU)
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.

6.8 Instruction Set Summary

Table 6-1 provides a summary of the M68HC08 instruction set.

6.9 Opcode Map

The opcode map is provided in Table 6-2.
Freescale Semiconductor Central Processor Unit (CPU) 85
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 1 of 8)
Source
Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP
ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP
AIS #opr Add Immediate Value (Signed) to SP SP ←
Add with Carry A ← (A) + (M) + (C) ↕↕– ↕↕↕
Add without Carry A ← (A) + (M) ↕↕– ↕↕↕
Operation Description
Effect on
CCR
VHI NZC
IMM DIR EXT IX2 IX1 IX SP1 SP2
IMM DIR EXT IX2 IX1 IX SP1 SP2
Address
Mode
Opcode
Operand
Cycles
2
ii
A9
3
dd
B9 C9 D9 E9
F9 9EE9 9ED9
AB
BB
CB
DB
EB
FB
9EEB 9EDB
hh ll ee ff ff
ff ee ff
ii dd hh ll ee ff ff
ff ee ff
4 4 3 2 4 5
2 3 4 4 3 2 4 5
Technical Data MC68HC908LJ12 — Rev. 2.1
86 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 2 of 8)
Effect on
Source
Form
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3 BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
Operation Description
CCR
VHI NZC
Address
Mode
Opcode
Operand
Cycles
BGE opr
BGT opr
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3 BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3 BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3
BHS rel
BIH rel Branch if IRQ BIL rel Branch if IRQ BIT #opr
BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP
BLE opr
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3 BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3 BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1 ––––––REL 91 rr 3
Branch if Greater Than or Equal To (Signed Operands)
Branch if Greater Than (Signed Operands)
Branch if Higher or Same (Same as BCC)
Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3 Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
Bit Test (A) & (M) 0 – – ↕↕–
Branch if Less Than or Equal To (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 ––––––REL 90 rr 3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0
PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1
––––––REL 92 rr 3
ii
IMM DIR EXT IX2 IX1 IX SP1 SP2
––––––REL 93 rr 3
A5
B5
C5
D5
E5
F5 9EE5 9ED5
dd hh ll ee ff ff
ff ee ff
2 3 4 4 3 2 4 5
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3 BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3 BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3 BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3
Freescale Semiconductor Central Processor Unit (CPU) 87
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 3 of 8)
Effect on
Source
Form
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 –––––↕
BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 –––––↕
Operation Description
CCR
VHI NZC
Address
Mode
DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
01
03
05
07
09
0B
0D
0F
00
02
04
06
08
0A
0C
0E
Opcode
Operand
dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr
dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr
Cycles
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
DIR (b0) DIR (b1)
BSET n,opr Set Bit n in M Mn ← 1 ––––––
PC ← (PC) + 2; push (PCL)
BSR rel Branch to Subroutine
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel
CLC Clear Carry Bit C ← 0 –––––0INH 98 1 CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2 CLR opr
CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP
Compare and Branch if Equal
Clear
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (X) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 2 + rel ? (A) – (M) = $00 PC ← (PC) + 4 + rel ? (A) – (M) = $00
M ← $00
A ← $00 X ← $00
H ← $00 M ← $00 M ← $00 M ← $00
––––––REL AD rr 4
––––––
0––01–
DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
DIR IMM IMM IX1+ IX+ SP1
DIR INH INH INH IX1 IX SP1
10 12 14 16 18 1A 1C 1E
31 41 51 61 71
9E61
3F 4F 5F 8C 6F 7F
9E6F
dd dd dd dd dd dd dd dd
dd rr ii rr ii rr ff rr rr ff rr
dd
ff
ff
4 4 4 4 4 4 4 4
5 4 4 5 4 6
3 1 1 1 3 2 4
Technical Data MC68HC908LJ12 — Rev. 2.1
88 Central Processor Unit (CPU) Freescale Semiconductor
Source
Form
CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP
COM opr COMA COMX COM opr,X COM ,X COM opr,SP
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 4 of 8)
Effect on
Operation Description
Compare A with M (A) – (M) ↕ ––↕↕↕
M ← (M
) = $FF – (M)
A ← (A
) = $FF – (M)
X ← (X
Complement (One’s Complement)
M ← (M M ← (M M ← (M
) = $FF – (M)
) = $FF – (M) ) = $FF – (M) ) = $FF – (M)
CCR
VHI NZC
0––↕↕1
IMM DIR EXT IX2 IX1 IX SP1 SP2
DIR INH INH IX1 IX SP1
Address
Mode
Opcode
Operand
Cycles
2
ii
A1
3
dd
B1 C1 D1 E1
F1 9EE1 9ED1
33
43
53
63
73 9E63
hh ll ee ff ff
ff ee ff
dd
ff
ff
4 4 3 2 4 5
4 1 1 4 3 5
CPHX #opr CPHX opr
CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP
DAA Decimal Adjust A (A)
DBNZ opr,rel DBNZA rel DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel
DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP
DIV Divide
EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP
Compare H:X with M (H:X) – (M:M + 1) ↕ ––↕↕↕
Compare X with M (X) – (M) ↕ ––↕↕↕
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0
Decrement and Branch if Not Zero
Decrement
Exclusive OR M with A A ← (A ⊕ M) 0––↕↕–
PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 4 + rel ? (result) ≠ 0
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 M ← (M) – 1
A ← (H:A)/(X)
H ← Remainder
IMM DIR
IMM DIR EXT IX2 IX1 IX SP1 SP2
10
U––↕↕↕INH 72 2
DIR INH
––––––
↕ ––↕↕–
––––↕↕INH 52 7
INH IX1 IX SP1
DIR INH INH IX1 IX SP1
IMM DIR EXT IX2 IX1 IX SP1 SP2
6575ii ii+1dd3
ii
A3
dd
B3
hh ll
C3
ee ff
D3
ff
E3 F3
ff
9EE3
ee ff
9ED3
dd rr
3B
rr
4B
rr
5B
ff rr
6B
rr
7B
ff rr
9E6B
dd
3A 4A 5A
ff
6A 7A
9E6A
ff
ii
A8
dd
B8
hh ll
C8
ee ff
D8
ff
E8 F8
ff
9EE8
ee ff
9ED8
4 2
3 4 4 3 2 4 5
5 3 3 5 4 6
4 1 1 4 3 5
2 3 4 4 3 2 4 5
Freescale Semiconductor Central Processor Unit (CPU) 89
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 5 of 8)
Source
Form
INC opr INCA INCX INC opr,X INC ,X INC opr,SP
JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X
JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X
LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP
LDHX #opr LDHX opr
LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP
LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP
Increment
Jump PC ← Jump Address ––––––
Jump to Subroutine
Load A from M A ← (M) 0––↕↕–
Load H:X from M H:X ← (M:M + 1) 0––↕↕–
Load X from M X ← (M) 0––↕↕–
Logical Shift Left (Same as ASL)
Operation Description
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 M ← (M) + 1
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
C
b7
0
b0
Effect on
CCR
VHI NZC
↕ ––↕↕–
––––––
↕ ––↕↕↕
DIR INH INH IX1 IX SP1
DIR EXT IX2 IX1 IX
DIR EXT IX2 IX1 IX
IMM DIR EXT IX2 IX1 IX SP1 SP2
IMM DIR
IMM DIR EXT IX2 IX1 IX SP1 SP2
DIR INH INH IX1 IX SP1
Address
Mode
Opcode
Operand
Cycles
dd
ff
ff dd
hh ll ee ff ff
dd hh ll ee ff ff
ii dd hh ll ee ff ff
ff ee ff
ii dd hh ll ee ff ff
ff ee ff
dd
ff
ff
4 1 1 4 3 5
2 3 4 3 2
4 5 6 5 4
2 3 4 4 3 2 4 5
4 2
3 4 4 3 2 4 5
4 1 1 4 3 5
3C 4C 5C 6C 7C
9E6C
BC CC DC EC FC
BD CD DD ED FD
A6
B6 C6 D6
E6
F6
9EE6 9ED6
4555ii jjdd3
AE BE CE DE EE FE
9EEE 9EDE
38
48
58
68
78
9E68
dd
LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP
Logical Shift Right ↕ ––0↕↕
b7
C0
b0
DIR INH INH IX1 IX SP1
34
44
54
64
74
9E64
4 1 1 4
ff
3 5
ff
Technical Data MC68HC908LJ12 — Rev. 2.1
90 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 6 of 8)
Effect on
Source
Form
MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr
MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5 NEG opr
NEGA NEGX NEG opr,X NEG ,X NEG opr,SP
NOP No Operation None – – – – – – INH 9D 1 NSA Nibble Swap A A ← (A[3:0]:A[7:4]) – – – – – – INH 62 3 ORA #opr
ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2
Move
Negate (Two’s Complement)
Inclusive OR A and M A ← (A) | (M) 0 – – ↕↕–
Operation Description
(M)
Destination
H:X ← (H:X) + 1 (IX+D, DIX+)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M)
← (M)
Source
CCR
VHI NZC
0––↕↕–
↕ ––↕↕↕
DD DIX+ IMD IX+D
DIR INH INH IX1 IX SP1
IMM DIR EXT IX2 IX1 IX SP1 SP2
Address
Mode
Opcode
Operand
5
dd dd
4E
4
dd
5E 6E 7E
30 40 50 60 70
9E60
AA BA CA DA EA
FA 9EEA 9EDA
ii dd dd
dd
ff
ff
ii dd hh ll ee ff ff
ff ee ff
4 4
4 1 1 4 3 5
2 3 4 4 3 2 4 5
Cycles
PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2 PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2 PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2 PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2 PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2
dd
ff
ff dd
ff
ff
4 1 1 4 3 5
4 1 1 4 3 5
ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP
ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP
RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1
Rotate Left through Carry ↕ ––↕↕↕
Rotate Right through Carry ↕ ––↕↕↕
C
b7
b7
b0
C
b0
DIR INH INH IX1 IX SP1
DIR INH INH IX1 IX SP1
39
49
59
69
79
9E69
36
46
56
66
76
9E66
Freescale Semiconductor Central Processor Unit (CPU) 91
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 7 of 8)
Effect on
Source
Form
RTI Return from Interrupt
RTS Return from Subroutine
SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP
SEC Set Carry Bit C ← 1 –––––1INH 99 1
Subtract with Carry A ← (A) – (M) – (C) ↕ ––↕↕↕
Operation Description
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← SP + 1; Pull (PCH) SP ← SP + 1; Pull (PCL)
CCR
VHI NZC
↕↕↕↕↕↕INH 80 7
––––––INH 81 4
IMM DIR EXT IX2 IX1 IX SP1 SP2
Address
Mode
Opcode
Operand
ii
A2
dd
B2
hh ll
C2
ee ff
D2
ff
E2
F2
ff
9EE2
ee ff
9ED2
Cycles
2 3 4 4 3 2 4 5
SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2 STA opr
STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – ↕↕– DIR 35 dd 4 STOP Enable IRQ STX opr
STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP
SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Store A in M M ← (A) 0––↕↕–
Pin; Stop Oscillator I ← 0; Stop Oscillator – – 0 – – – INH 8E 1
Store X in M M ← (X) 0––↕↕–
Subtract A ← (A) – (M) ↕ ––↕↕↕
DIR EXT IX2 IX1 IX SP1 SP2
DIR EXT IX2 IX1 IX SP1 SP2
IMM DIR EXT IX2 IX1 IX SP1 SP2
B7
C7 D7
E7
F7
9EE7 9ED7
BF CF DF EF
FF
9EEF
9EDF
A0
B0
C0 D0
E0
F0
9EE0 9ED0
dd hh ll ee ff ff
ff ee ff
dd hh ll ee ff ff
ff ee ff
ii dd hh ll ee ff ff
ff ee ff
3 4 4 3 2 4 5
3 4 4 3 2 4 5
2 3 4 4 3 2 4 5
Technical Data MC68HC908LJ12 — Rev. 2.1
92 Central Processor Unit (CPU) Freescale Semiconductor
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 8 of 8)
Effect on
Source
Form
SWI Software Interrupt
TAP Transfer A to CCR CCR ← (A) ↕↕↕↕↕↕INH 84 2 TAX Transfer A to X X ← (A) ––––––INH 97 1 TPA Transfer CCR to A A ← (CCR) – – – – – – INH 85 1 TST opr
TSTA TSTX TST opr,X TST ,X TST opr,SP
TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2 TXA Transfer X to A A ← (X) ––––––INH 9F 1 TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2
A Accumulator n Any bit C Carry/borrow bit opr Operand (one or two bytes) CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer H Half-carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte & Logical AND IMD Immediate source to direct destination addressing mode | Logical OR IMM Immediate addressing mode INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX+ Indexed, no offset, post increment addressing mode # Immediate value IX+D Indexed with post increment to direct addressing mode IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX1+ Indexed, 8-bit offset, post increment addressing mode ? If IX2 Indexed, 16-bit offset addressing mode : Concatenated with M Memory location ↕ Set or cleared N Negative bit — Not affected
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – ↕↕–
Operation Description
PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
⊕ Logical EXCLUSIVE OR
« Sign extend
CCR
VHI NZC
––1–––INH 83 9
DIR INH INH IX1 IX SP1
Address
Mode
Opcode
Operand
dd
3D 4D 5D 6D 7D
9E6D
3 1 1 3
ff
2 4
ff
Cycles
Freescale Semiconductor Central Processor Unit (CPU) 93
94 Central Processor Unit (CPU) Freescale Semiconductor
Technical Data MC68HC908LJ12 — Rev. 2.1
Central Processor Unit (CPU)
Table 6-2. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
MSB
LSB
05BRSET0
15BRCLR0
25BRSET1
35BRCLR1
45BRSET2
55BRCLR2
65BRSET3
75BRCLR3
85BRSET4
95BRCLR4
A5BRSET5
B5BRCLR5
C5BRSET6
D5BRCLR6
E5BRSET7
F5BRCLR7
01234569E6789ABCD9EDE9EEF
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
3DIR
4
BSET0
2DIR
4
BCLR0
2DIR
4
BSET1
2DIR
4
BCLR1
2DIR
4
BSET2
2DIR
4
BCLR2
2DIR
4
BSET3
2DIR
4
BCLR3
2DIR
4
BSET4
2DIR
4
BCLR4
2DIR
4
BSET5
2DIR
4
BCLR5
2DIR
4
BSET6
2DIR
4
BCLR6
2DIR
4
BSET7
2DIR
4
BCLR7
2DIR
3
BRA
2REL
3
BRN
2REL
3
BHI
2REL
3
BLS
2REL
3
BCC
2REL
3
BCS
2REL
3
BNE
2REL
3
BEQ
2REL
3
BHCC
2REL
3
BHCS
2REL
3
BPL
2REL
3
BMI
2REL
3
BMC
2REL
3
BMS
2REL
3
BIL
2REL
3
BIH
2REL
4
NEG
2DIR
5
CBEQ
3DIR
4
COM
2DIR
4
LSR
2DIR
4
STHX
2DIR
4
ROR
2DIR
4
ASR
2DIR
4
LSL
2DIR
4
ROL
2DIR
4
DEC
2DIR
5
DBNZ
3DIR
4
INC
2DIR
3
TST
2DIR
3
CLR
2DIR
1
NEGA
1INH
4
CBEQA
3IMM
5
MUL
1INH
1
COMA
1INH
1
LSRA
1INH
3
LDHX
3IMM
1
RORA
1INH
1
ASRA
1INH
1
LSLA
1INH
1
ROLA
1INH
1
DECA
1INH
3
DBNZA
2INH
1
INCA
1INH
1
TSTA
1INH
5
MOV
3DD
1
CLRA
1INH
1
NEGX
1INH
4
CBEQX
3IMM
7
DIV
1INH
1
COMX
1INH
1
LSRX
1INH
4
LDHX
2DIR
1
RORX
1INH
1
ASRX
1INH
1
LSLX
1INH
1
ROLX
1INH
1
DECX
1INH
3
DBNZX
2INH
1
INCX
1INH
1
TSTX
1INH
4
MOV
2DIX+
1
CLRX
1INH
4
NEG
2IX1
3IX1+
1INH
2IX1
2IX1
3IMM
2IX1
2IX1
2IX1
2IX1
2IX1
3IX1
2IX1
2IX1
3IMD
2IX1
5
CBEQ
3
NSA
4
COM
4
LSR
3
CPHX
4
ROR
4
ASR
4
LSL
4
ROL
4
DEC
5
DBNZ
4
INC
3
TST
4
MOV
3
CLR
3SP1
4SP1
3SP1
3SP1
3SP1
3SP1
3SP1
3SP1
3SP1
4SP1
3SP1
3SP1
3SP1
5
NEG
6
CBEQ
5
COM
5
LSR
ROR
5
ASR
5
LSL
5
ROL
5
DEC
6
DBNZ
5
INC
4
TST
4
CLR
NEG
1IX
CBEQ
2IX+
DAA
1INH
COM
1IX
LSR
1IX
CPHX
2DIR
5
ROR
1IX
ASR
1IX
LSL
1IX
ROL
1IX
DEC
1IX
DBNZ
2IX
INC
1IX
TST
1IX
MOV
2IX+D
CLR
1IX
3
4
2
3
3
4
3
3
3
3
3
4
3
2
4
2
7
RTI
1INH
4
RTS
1INH
9
SWI
1INH
2
TAP
1INH
1
TPA
1INH
2
PULA
1INH
2
PSHA
1INH
2
PULX
1INH
2
PSHX
1INH
2
PULH
1INH
2
PSHH
1INH
1
CLRH
1INH
1
STOP
1INH
1
WAIT
1INH
3
BGE
2REL
3
BLT
2REL
3
BGT
2REL
3
BLE
2REL
2
TXS
1INH
2
TSX
1INH
1
TAX
1INH
1
CLC
1INH
1
SEC
1INH
2
CLI
1INH
2
SEI
1INH
1
RSP
1INH
1
NOP
1INH
*
1
TXA
1INH
2
SUB
2IMM
2
CMP
2IMM
2
SBC
2IMM
2
CPX
2IMM
2
AND
2IMM
2
BIT
2IMM
2
LDA
2IMM
2
AIS
2IMM
2
EOR
2IMM
2
ADC
2IMM
2
ORA
2IMM
2
ADD
2IMM
4
BSR
2REL
2
LDX
2IMM
2
AIX
2IMM
3
SUB
2DIR
3
CMP
2DIR
3
SBC
2DIR
3
CPX
2DIR
3
AND
2DIR
3
BIT
2DIR
3
LDA
2DIR
3
STA
2DIR
3
EOR
2DIR
3
ADC
2DIR
3
ORA
2DIR
3
ADD
2DIR
2
JMP
2DIR
4
JSR
2DIR
3
LDX
2DIR
3
STX
2DIR
4
SUB
3EXT
4
CMP
3EXT
4
SBC
3EXT
4
CPX
3EXT
4
AND
3EXT
4
BIT
3EXT
4
LDA
3EXT
4
STA
3EXT
4
EOR
3EXT
4
ADC
3EXT
4
ORA
3EXT
4
ADD
3EXT
3
JMP
3EXT
5
JSR
3EXT
4
LDX
3EXT
4
STX
3EXT
4
SUB
3IX2
4
CMP
3IX2
4
SBC
3IX2
4
CPX
3IX2
4
AND
3IX2
4
BIT
3IX2
4
LDA
3IX2
4
STA
3IX2
4
EOR
3IX2
4
ADC
3IX2
4
ORA
3IX2
4
ADD
3IX2
4
JMP
3IX2
6
JSR
3IX2
4
LDX
3IX2
4
STX
3IX2
5
SUB
4SP2
5
CMP
4SP2
5
SBC
4SP2
5
CPX
4SP2
5
AND
4SP2
5
BIT
4SP2
5
LDA
4SP2
5
STA
4SP2
5
EOR
4SP2
5
ADC
4SP2
5
ORA
4SP2
5
ADD
4SP2
5
LDX
4SP2
5
STX
4SP2
3
SUB
2IX1
3
CMP
2IX1
3
SBC
2IX1
3
CPX
2IX1
3
AND
2IX1
3
BIT
2IX1
3
LDA
2IX1
3
STA
2IX1
3
EOR
2IX1
3
ADC
2IX1
3
ORA
2IX1
3
ADD
2IX1
3
JMP
2IX1
5
JSR
2IX1
3
LDX
2IX1
3
STX
2IX1
4
SUB
3SP1
4
CMP
3SP1
4
SBC
3SP1
4
CPX
3SP1
4
AND
3SP1
4
BIT
3SP1
4
LDA
3SP1
4
STA
3SP1
4
EOR
3SP1
4
ADC
3SP1
4
ORA
3SP1
4
ADD
3SP1
4
LDX
3SP1
4
STX
3SP1
SUB
1IX
CMP
1IX
SBC
1IX
CPX
1IX
AND
1IX
BIT
1IX
LDA
1IX
STA
1IX
EOR
1IX
ADC
1IX
ORA
1IX
ADD
1IX
JMP
1IX
JSR
1IX
LDX
1IX
STX
1IX
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with IX+D Indexed-Direct DIX+ Direct-Index ed Post Increment
*Pre-byte for stack pointer indexed instructions
MSB
LSB
Low Byte of Opcode in Hexadecimal 05BRSET0
0 High Byte of Opcode in Hexadecimal
3DIR
Cycles Opcode Mnemonic Number of Bytes / Addressing Mode
Technical Data — MC68HC908LJ12

7.1 Contents

7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.3 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.4 Crystal (X-tal) Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . .98
7.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . .98
7.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . .98
7.5.4 Internal RC Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.5.5 CGM Oscillator Clock (CGMXCLK) . . . . . . . . . . . . . . . . . . .98
7.5.6 CGM Reference Clock (CGMRCLK) . . . . . . . . . . . . . . . . . .98

Section 7. Oscillator (OSC)

7.2 Introduction

7.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . .99
The oscillator module provides the reference clock for the clock generator module (CGM), the real time clock module (RTC), and other MCU sub-systems.
The oscillator module consist of two types of oscillator circuits:
• Internal RC oscillator
• Crystal (x-tal) oscillator
Freescale Semiconductor Oscillator (OSC) 95
Oscillator (OSC)
From SIM
SIMOSCEN
CONFIG2
STOP_IRCDIS
The reference clock for the CGM, real time clock module (RTC), and other MCU sub-systems is driven by the crystal oscillator. The COP module is always driven by internal RC oscillator.
The RC internal oscillator runs continuously after a POR or reset and is always available in run and wait modes. In stop mode, it can be disabled by setting the STOP_IRCDIS bit in CONFIG2 register.
Figure 7-1. shows the block diagram of the oscillator module.
EN
INTERNAL RC
OSCILLATOR
ICLK
To SIM, COP
INTERNAL RC OSCILLATOR
CONFIG2
STOP_XCLKEN
MCU
*RS can be zero (shorted) when used with higher-frequency crystals.
Refer to manufacturer’s data.
See Section 23. for component value requirements.
CRYSTAL OSCILLATOR
CGMRCLK
CGMXCLK
OSC2OSC1
R
B
RS*
X
1
C
1
C
2
To CGM PLL
To RTC, ADC, LCD, CGM Clock Selection MUX
Figure 7-1. Oscillator Module Block Diagram
Technical Data MC68HC908LJ12 — Rev. 2.1
96 Oscillator (OSC) Freescale Semiconductor

7.3 Internal Oscillator

The internal RC oscillator clock (ICLK) is a free running 64kHz clock (at VDD = 5V) that requires no external components. It is the reference clock input to the computer operating properly (COP) module.
The ICLK can be turned off in stop mode by setting the STOP_IRCDIS bit in CONFIG2. After reset, the bit is clear by default and ICLK is enabled during stop mode.

7.4 Crystal (X-tal) Oscillator

The crystal (x-tal) oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source.
In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, as shown in Figure 7-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components:
Oscillator (OSC)

7.5 I/O Signals

• Crystal, X
• Fixed capacitor, C
1
1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, R
B
• Series resistor, RS (optional)
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information.
The following paragraphs describe the oscillator I/O signals.
Freescale Semiconductor Oscillator (OSC) 97
Oscillator (OSC)

7.5.1 Crystal Amplifier Input Pin (OSC1)

OSC1 pin is an input to the crystal oscillator amplifier. Schmitt trigger and glitch filter are implemented on this pin to improve EMC performance. See Section 23. Electrical Specifications for detail specification of the glitch filter.

7.5.2 Crystal Amplifier Output Pin (OSC2)

OSC2 pin is the output of the crystal oscillator inverting amplifier.

7.5.3 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal from the system integration module (SIM) enables/disables the internal RC and x-tal oscillator circuits.

7.5.4 Internal RC Clock (ICLK)

The ICLK clock is the output from the internal RC oscillator. This clock drives the SIM and COP modules.

7.5.5 CGM Oscillator Clock (CGMXCLK)

The CGMXCLK clock is the output from the x-tal oscillator. This clock drives to CGM, real time clock module, analog-to-digital converter, liquid crystal display driver module, and other MCU sub-systems.

7.5.6 CGM Reference Clock (CGMRCLK)

This is buffered signal of CGMXCLK, it is used by the CGM as the phase-locked-loop (PLL) reference clock.

7.6 Low Power Modes

The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
Technical Data MC68HC908LJ12 — Rev. 2.1
98 Oscillator (OSC) Freescale Semiconductor

7.6.1 Wait Mode

7.6.2 Stop Mode

Oscillator (OSC)
The WAIT instruction has no effect on the oscillator module. CGMXCLK, CGMRCLK, and ICLK continues to drive the MCU modules.
The STOP instruction clears the SIMOSCEN signal, and hence the CGMXCLK (and CGMRCLK) clock stops running. For continuous CGMXCLK operation in stop mode, set the STOP_XCLKEN to logic 1 before entering stop mode. Continuous CGMXCLK operation in stop mode allows the RTC module to generate interrupts to wake up the CPU.
By default, the internal RC oscillator clock, ICLK, continues to run in stop mode. To disable the ICLK in stop mode, set the STOP_IRCDIS bit to logic 1 before entering stop mode.

7.7 Oscillator During Break Mode

The oscillator circuits continue to drive CGMXCLK, CGMRCLK, and ICLK when the device enters the break state.
Freescale Semiconductor Oscillator (OSC) 99
Oscillator (OSC)
Technical Data MC68HC908LJ12 — Rev. 2.1
100 Oscillator (OSC) Freescale Semiconductor
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